AM29LV256MH101WHI [SPANSION]

Flash, 16MX16, 100ns, PBGA80, 1 MM PITCH, FBGA-80;


型号：	AM29LV256MH101WHI
厂家：	SPANSION
描述：	Flash, 16MX16, 100ns, PBGA80, 1 MM PITCH, FBGA-80
文件：	总8页 (文件大小：106K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADVANCE INFORMATION

Am29LV256M

64 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBit 3.0 Volt-only

Uniform Sector Flash Memory with VersatileI/O Control

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■ Low power consumption (typical values at 3.0 V, 5

MHz)

■ Single power supply operation

— 30 mA typical active read current

— 50 mA typical erase/program current

— 1 µA typical standby mode current

— 2.7–3.6 volt read, erase, and program operations

■ Enhanced VersatileI/O control

— Device generates data output voltages and tolerates

data input voltages as determined by the voltage on

the V_IOpin; operates from 1.65 to 3.6 V

■ Package options

— 56-pin TSOP

— FBGA (Pinout configuration, package dimensions,

and ball count to be determined.)

■ Manufactured on 0.23 µm MirrorBit process

technology

■ SecSi (Secured Silicon) Sector region

SOFTWARE & HARDWARE FEATURES

— 128-word/64-byte sector for permanent, secure

identification through an 8-word/16-byte random

Electronic Serial Number, accessible through a

command sequence

■ Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed

— May be programmed and locked at the factory or by

the customer

— Data# polling & toggle bits provide status

■ Flexible sector architecture

— Unlock Bypass Program command reduces overall

multiple-word or byte programming time

— Five hundred twelve 32 Kword (64 Kbyte) sectors

— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

■ Compatibility with JEDEC standards

— Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent

write protection

■ Hardware features

— Sector Group Protection: hardware-level method of

preventing write operations within a sector group

■ Minimum 100,000 erase cycle guarantee per sector

■ 20-year data retention at 125°C

— Temporary Sector Unprotect: V_ID-level method of

changing code in locked sectors

PERFORMANCE CHARACTERISTICS

■ High performance

— WP#/ACC input accelerates programming time

(when high voltage is applied) for greater throughput

during system production. Protects first or last sector

regardless of sector protection settings

— 90 ns access time

— 25 ns page read times

— 1 s typical sector erase time

— Hardware reset input (RESET#) resets device

— 5.9 µs typical write buffer word programming time:

16-word/32-byte write buffer reduces overall

programming time for multiple-word updates

— Ready/Busy# output (RY/BY#) detects program or

erase cycle completion

— 4-word/8-byte page read buffer

— 16-word/32-byte write buffer

Publication# 25263 Rev: A Amendment/0

Issue Date: August 3, 2001

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Refer to AMD’s Website (www.amd.com) for the latest information.

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION

The Am29LV256M is a 256 Mbit, 3.0 volt single power

supply flash memory devices organized as 16,777,216

words or 33,554,432 bytes. The device have a 16-bit

wide data bus that can also function as an 8-bit wide

data bus by using the BYTE# input. The device can be

programmed either in the host system or in standard

EPROM programmers.

at its data outputs and the voltages tolerated at its data

inputs to the same voltage level that is asserted on the

_IOpin. This allows the device to operate in a 1.8 V or

3 V system environment as required.

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of sectors of memory.

This can be achieved in-system or via programming

equipment.

An access time of 90 ns is available for applications

where V_IO≥ 3.0 V. An access time of 100 ns is avail-

able for applications where V_IO< 3.0 V. The device is

offered in a 56-pin TSOP or an FBGA package (pinout

configuration, ball count, and package dimensions to

be determined). Each device has separate chip enable

(CE#), write enable (WE#) and output enable (OE#)

controls.

The Erase Suspend/Erase Resume feature allows

the host system to pause an erase operation in a given

sector to read or program any other sector and then

complete the erase operation. The Program Sus-

pend/Program Resume feature enables the host sys-

tem to pause a program operation in a given sector to

read any other sector and then complete the program

operation.

Each device requires only a single 3.0 volt power

supply (2.7–3.6 V) for both read and write functions.

In addition to a V_CCinput, a high-voltage accelerated

program (WP#/ACC) input provides shorter program-

ming times through increased current. This feature is

intended to facilitate factory throughput during system

production, but may also be used in the field if desired.

The hardware RESET# pin terminates any operation

in progress and resets the device, after which it is then

ready for a new operation. The RESET# pin may be

tied to the system reset circuitry. A system reset would

thus also reset the device, enabling the host system to

read boot-up firmware from the Flash memory device.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the device using standard

microprocessor write timing. Write cycles also inter-

nally latch addresses and data needed for the pro-

gramming and erase operations.

The device reduces power consumption in the

standby mode when it detects specific voltage levels

on CE# and RESET#, or when addresses have been

stable for a specified period of time.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

The SecSi (Secured Silicon) Sector provides a

128-word/256-byte area for code or data that can be

permanently protected. Once this sector is protected,

no further changes within the sector can occur.

Device programming and erasure are initiated through

command sequences. Once a program or erase oper-

ation has begun, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle) status bits or

monitor the Ready/Busy# (RY/BY#) output to deter-

mine whether the operation is complete. To facilitate

programming, an Unlock Bypass mode reduces com-

mand sequence overhead by requiring only two write

cycles to program data instead of four.

The Write Protect (WP#/ACC) feature protects the

first or last sector by asserting a logic low on the WP#

pin.

AMD MirrorBit flash technology combines years of

Flash memory manufacturing experience to produce

the highest levels of quality, reliability and cost effec-

tiveness. The device electrically erases all bits within a

sector simultaneously via hot-hole assisted erase. The

data is programmed using hot electron injection.

The VersatileI/O™ (V_IO) control allows the host sys-

tem to set the voltage levels that the device generates

Am29LV256M

A D V A N C E I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Part Number

Am29LV256M

101

102

Speed Option

V_CC= 2.7–3.6 V all devices

(V_IO= 3.0–3.6 V)

(V_IO= 2.7–3.0 V) (V_IO= 1.65–2.7 V)

Max. Access Time (ns)

100

Max. CE# Access Time (ns)

Max. Page access time (t_PACC

Max. OE# Access Time (ns)

)

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V_CC

Sector Switches

V_SS

V_IO

Erase Voltage

Generator

Input/Output

Buffers

RESET#

WE#

State

WP#/ACC

Control

BYTE#

Command

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

X-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

A23–A0

Am29LV256M

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

A23

A22

A15

A14

A13

A12

A11

A10

56 NC

55 NC

54 A16

53 BYTE#

52 V_SS

51 DQ15/A-1

50 DQ7

49 DQ14

48 DQ6

47 DQ13

46 DQ5

45 DQ12

44 DQ4

43 V_CC

42 DQ11

41 DQ3

40 DQ10

39 DQ2

38 DQ9

37 DQ1

36 DQ8

35 DQ0

34 OE#

33 V_SS

56-Pin Standard TSOP

A8 10

A19 11

A20 12

WE# 13

RESET# 14

A21 15

WP#/ACC 16

RY/BY# 17

A18 18

A17 19

A7 20

A6 21

A5 22

A4 23

A3 24

A2 25

32 CE#

31 A0

30 NC

29 V_IO

A1 26

NC 27

NC 28

Am29LV256M

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

FBGA

Top View, Balls Facing Down

RFU

A22

A23

V_IO

V_SS

RFU

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

RFU

A10

A11

DQ7

DQ14

DQ13

DQ6

RFU

V_CC

RFU

WE# RESET#

A21

A19

DQ5

DQ12

DQ4

RFU

B4 C4

RFU RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

RFU

A17

DQ0

DQ8

DQ9

DQ1

RFU

V_SS

RFU

CE#

OE#

RFU

V_IO

Note: The FBGA package pinout configuration shown is preliminary. The ball count and package physical dimensions have not

yet been determined. Contact AMD for further information. RFU = Reserved for Future Use.

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

Special Handling Instructions for FBGA

Package

The package and/or data integrity may be

Special handling is required for Flash Memory products

compromised if the package body is exposed to

in FBGA packages.

temperatures above 150°C for prolonged periods of

time.

Am29LV256M

A D V A N C E I N F O R M A T I O N

PIN DESCRIPTION

LOGIC SYMBOL

A23–A0

= 24 Addresses inputs

DQ15–DQ0 = 16 Data inputs/outputs

A23–A0

16 or 8

CE#

= Chip Enable input

= Output Enable input

= Write Enable input

DQ15–DQ0

(A-1)

CE#

OE#

WE#

WP#/ACC

= Hardware Write Protect input;

Acceleration Input

WP#/ACC

RESET#

V_IO

RESET#

BYTE#

RY/BY#

V_CC

= Hardware Reset Pin input

= Selects 8-bit or 16-bit mode

= Ready/Busy output

RY/BY#

BYTE#

= 3.0 volt-only single power supply

(see Product Selector Guide for

speed options and voltage

supply tolerances)

V_IO

V_SS

= Output Buffer power

= Device Ground

= Pin Not Connected Internally

Am29LV256M

A D V A N C E I N F O R M A T I O N

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29LV256M

TEMPERATURE RANGE

Industrial (–40°C to +85°C)

PACKAGE TYPE

56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056)

Fine-Pitch Ball Grid Array (FBGA)

1.0 mm pitch (Pinout configuration, package dimensions and ball count to

be determined. Contact AMD for further information.)

SPEED OPTION

See Product Selector Guide and Valid Combinations

SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = 0)

Uniform sector device, highest address sector protected

Uniform sector device, lowest address sector protected

DEVICE NUMBER/DESCRIPTION

Am29LV256MH/L

256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO Control

3.0 Volt-only Read, Program, and Erase

Valid Combinations for

TSOP Package

Valid Combinations for FBGA Package

Package

Speed/

_IORange

Speed/V_IORange

Am29LV256MH90,

90 ns

Order Number

Marking

Am29LV256ML90

_IO= 2.7–3.6 V

Am29LV256MH90,

Am29LV256ML90

L256MH90V,

L256ML90V

90 ns, V_IO=

2.7–3.6 V

Am29LV256MH101,

Am29LV256ML101

100 ns

_IO= 2.7–3.0 V

Am29LV256MH101,

Am29LV256ML101

L256MH01V,

L256ML01V

100 ns, V_IO

2.7–3.0 V

WHI

Am29LV256MH102,

Am29LV256ML102

100 ns

_IO= 1.65–2.7 V

Am29LV256MH102,

Am29LV256ML102

L256MH02V,

L256ML02V

100 ns, V_IO

1.65–2.7 V

Valid Combinations

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult the local AMD sales office to confirm

availability of specific valid combinations and to check on newly re-

leased combinations.

Am29LV256M

A D V A N C E I N F O R M A T I O N

REVISION SUMMARY

Revision A (August 3, 2001)

Initial release as abbreviated Advance Information

data sheet.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29LV256M

AM29LV256MH101WHI [SPANSION]

相关型号：

AM29LV256MH102EF

AM29LV256MH102EI

AM29LV256MH102WHF

AM29LV256MH102WHI

AM29LV256MH103EF

AM29LV256MH103EI

AM29LV256MH103FF

AM29LV256MH103FI

AM29LV256MH103PGF

AM29LV256MH103PGI

AM29LV256MH103REF

AM29LV256MH103REI