AM29LV640MB120R [SPANSION]
64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit-TM 3.0 Volt-only Boot Sector Flash Memory; 64兆位(4M ×16位/ 8的M× 8位)的MirrorBit -TM 3.0伏只引导扇区闪存型号: | AM29LV640MB120R |
厂家: | SPANSION |
描述: | 64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit-TM 3.0 Volt-only Boot Sector Flash Memory |
文件: | 总66页 (文件大小:1397K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Am29LV640MT/B
Data Sheet
For new designs, S29GL064M supercedes Am29LV640MT/B and is the factory-recommended migra-
tion path for this device. Please refer to the S29GLxxxM Family Datasheet for specifications and
ordering information.
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 26190 Revision C Amendment +3 Issue Date February 12, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
For new designs, S29GL064M supercedes Am29LV640MT/B and is the factory-recommended migration path
for this device. Please refer to the S29GLxxxM Family Datasheet for specifications and ordering information.
Am29LV640MT/B
64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit™
3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■ Low power consumption (typical values at 3.0 V, 5
MHz)
■ Single power supply operation
— 3 V for read, erase, and program operations
— 30 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
■ Manufactured on 0.23 µm MirrorBit process
technology
■ Package options
— 48-pin TSOP
■ SecSi™ (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— 63-ball Fine-pitch BGA
— 64-ball Fortified BGA
SOFTWARE & HARDWARE FEATURES
— May be programmed and locked at the factory or by
the customer
■ Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
■ Flexible sector architecture
— One hundred twenty-seven 32 Kword/64-Kbyte
sectors
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Eight 4 Kword/8 Kbyte boot sectors
— Data# polling & toggle bits provide status
■ Compatibility with JEDEC standards
— Unlock Bypass Program command reduces overall
multiple-word programming time
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
■ Minimum 100,000 erase cycle guarantee per sector
■ 20-year data retention at 125°C
■ Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
PERFORMANCE CHARACTERISTICS
■ High performance
— Temporary Sector Unprotect: VID-level method of
changing code in locked sectors
— 90 ns access time
— 25 ns page read times
— WP#/ACC input:
Write Protect input (WP#) protects top or bottom two
sectors regardless of sector protection settings
ACC (high voltage) accelerates programming time for
higher throughput during system production
— 0.5 s typical sector erase time
— 22 µs typical effective write buffer word programming
time: 16-word/32-byte write buffer reduces overall
programming time for multiple-word/byte updates
— Hardware reset input (RESET#) resets device
— 4-word/8-byte page read buffer
— 16-word/32-byte write buffer
— Ready/Busy# output (RY/BY#) indicates program or
erase cycle completion
Publication# 26190 Rev: C Amendment/+3
Issue Date: February 12, 2004
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV640MT/B is a 64 Mbit, 3.0 volt single
power supply flash memory device organized as
4,194,304 words or 8,388,608 bytes. The device has
an 8-bit/16-bit bus and can be programmed either in
the host system or in standard EPROM programmers.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (VCC) and an I/O voltage range (VIO), as
specified in the Product Selector Guide and the Order-
ing Information sections. The device is offered in a
48-pin TSOP, 63-ball Fine-pitch BGA or 64-ball Forti-
fied BGA package. Each device has separate chip en-
able (CE#), write enable (WE#) and output enable
(OE#) controls.
The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a given
sector to read or program any other sector and then
complete the erase operation. The Program Sus-
pend/Program Resume feature enables the host sys-
tem to pause a program operation in a given sector to
read any other sector and then complete the program
operation.
Each device requires only a single 3.0 volt power
supply for both read and write functions. In addition to
a VCC input, a high-voltage accelerated program
(ACC) function provides shorter programming times
through increased current on the WP#/ACC input. This
feature is intended to facilitate factory throughput dur-
ing system production, but may also be used in the
field if desired.
The hardware RESET# pin terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power consumption in the
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The Write Protect (WP#) feature protects the top or
bottom two sectors by asserting a logic low on the
WP#/ACC pin. The protected sector will still be pro-
tected even during accelerated programming.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
The SecSi™ (Secured Silicon) Sector provides a
128-word/256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to deter-
mine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
2
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
MIRRORBIT 64 MBIT DEVICE FAMILY
Device
Bus
Sector Architecture
Packages
VIO
RY/BY#
WP#, ACC
WP# Protection
48-pin TSOP (std. & rev. pinout),
63-ball FBGA
LV065MU
x8
Uniform (64 Kbyte)
Yes
Yes
ACC only
No WP#
Boot (8 x 8 Kbyte
at top & bottom)
48-pin TSOP, 63-ball Fine-pitch BGA,
64-ball Fortified BGA
2 x 8 Kbyte
top or bottom
LV640MT/B
LV640MH/L
LV641MH/L
LV640MU
x8/x16
x8/x16
x16
No
Yes
Yes
Yes
Yes
Yes
No
WP#/ACC pin
WP#/ACC pin
56-pin TSOP (std. & rev. pinout),
64-ball Fortified BGA
1 x 64 Kbyte
high or low
Uniform (64 Kbyte)
Uniform (32 Kword)
Uniform (32 Kword)
Separate WP#
and ACC pins
1 x 32 Kword
top or bottom
48-pin TSOP (std. & rev. pinout)
64-ball Fortified BGA,
63-ball Fine-pitch BGA
x16
Yes
ACC only
No WP#
RELATED DOCUMENTS
To download related documents, click on the following
links or go to www.amd.com→Flash Memory→Prod-
uct Information→MirrorBit→Flash Information→Tech-
nical Documentation.
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
Migrating from Single-byte to Three-byte Device IDs
AMD MirrorBit™ White Paper
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
February 12, 2004
Am29LV640MT/B
3
A D V A N C E I N F O R M A T I O N
TABLE OF CONTENTS
Table 12. Command Definitions (x16 Mode, BYTE# = VIH) ............ 35
Table 13. Command Definitions (x8 Mode, BYTE# = VIL)............... 36
Write Operation Status. . . . . . . . . . . . . . . . . . . . . 37
DQ7: Data# Polling ................................................................. 37
Figure 8. Data# Polling Algorithm .................................................. 37
RY/BY#: Ready/Busy#............................................................ 38
DQ6: Toggle Bit I .................................................................... 38
Figure 9. Toggle Bit Algorithm........................................................ 39
DQ2: Toggle Bit II ................................................................... 39
Reading Toggle Bits DQ6/DQ2 ............................................... 39
DQ5: Exceeded Timing Limits ................................................ 40
DQ3: Sector Erase Timer ....................................................... 40
DQ1: Write-to-Buffer Abort ..................................................... 40
Table 14. Write Operation Status ................................................... 40
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 41
Figure 10. Maximum Negative Overshoot Waveform ................... 41
Figure 11. Maximum Positive Overshoot Waveform..................... 41
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 41
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations .....................................................10
Word/Byte Configuration ........................................................ 10
Requirements for Reading Array Data ................................... 10
Page Mode Read .................................................................... 11
Writing Commands/Command Sequences ............................ 11
Write Buffer ............................................................................. 11
Accelerated Program Operation ............................................. 11
Autoselect Functions .............................................................. 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 12
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 12
Table 2. Am29LV640MT Top Boot Sector Architecture ..................12
Table 3. Am29LV640MB Bottom Boot Sector Architecture .............15
Autoselect Mode..................................................................... 18
Table 4. Autoselect Codes, (High Voltage Method) .......................18
Sector Group Protection and Unprotection ............................. 19
Table 5. Am29LV640MT Top Boot Sector Protection .....................19
Table 6. Am29LV640MB Bottom Boot Sector Protection ................19
Write Protect (WP#) ................................................................ 20
Temporary Sector Group Unprotect ....................................... 20
Figure 1. Temporary Sector Group Unprotect Operation................ 20
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 21
SecSi (Secured Silicon) Sector Flash Memory Region .......... 22
Table 7. SecSi Sector Contents ......................................................22
Figure 3. SecSi Sector Protect Verify.............................................. 23
Hardware Data Protection ...................................................... 23
Low VCC Write Inhibit ............................................................ 23
Write Pulse “Glitch” Protection ............................................... 23
Logical Inhibit .......................................................................... 23
Power-Up Write Inhibit ............................................................ 23
Common Flash Memory Interface (CFI). . . . . . . 23
Table 9. System Interface String......................................................24
Command Definitions . . . . . . . . . . . . . . . . . . . . . 26
Reading Array Data ................................................................ 26
Reset Command ..................................................................... 27
Autoselect Command Sequence ............................................ 27
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 27
Word/Byte Program Command Sequence ............................. 27
Unlock Bypass Command Sequence ..................................... 28
Write Buffer Programming ...................................................... 28
Accelerated Program .............................................................. 29
Figure 4. Write Buffer Programming Operation............................... 30
Figure 5. Program Operation .......................................................... 31
Program Suspend/Program Resume Command Sequence ... 31
Figure 6. Program Suspend/Program Resume............................... 32
Chip Erase Command Sequence ........................................... 32
Sector Erase Command Sequence ........................................ 32
Figure 7. Erase Operation............................................................... 33
Erase Suspend/Erase Resume Commands ........................... 34
Command Definitions ............................................................. 35
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. Test Setup.................................................................... 43
Table 15. Test Specifications ......................................................... 43
Key to Switching Waveforms. . . . . . . . . . . . . . . . 43
Figure 13. Input Waveforms and
Measurement Levels...................................................................... 43
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44
Read-Only Operations ........................................................... 44
Figure 14. Read Operation Timings............................................... 44
Figure 15. Page Read Timings ...................................................... 45
Hardware Reset (RESET#) .................................................... 46
Figure 16. Reset Timings............................................................... 46
Erase and Program Operations .............................................. 47
Figure 17. Program Operation Timings.......................................... 48
Figure 18. Accelerated Program Timing Diagram.......................... 48
Figure 19. Chip/Sector Erase Operation Timings .......................... 49
Figure 20. Data# Polling Timings (During Embedded Algorithms). 50
Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 51
Figure 22. DQ2 vs. DQ6................................................................. 51
Temporary Sector Unprotect .................................................. 52
Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 52
Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 53
Alternate CE# Controlled Erase and Program Operations ..... 54
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 55
Erase And Programming Performance. . . . . . . . 56
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 56
TSOP Pin and BGA Package Capacitance . . . . . 56
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 58
TS 048—48-Pin Standard Pinout Thin Small Outline Package
(TSOP) ................................................................................... 58
FBE063—63-Ball Fine-pitch Ball Grid Array (FBGA)
12 x 11 mm Package .............................................................. 59
LAA064—64-Ball Fortified Ball Grid Array (FBGA)
13 x 11 mm Package .............................................................. 60
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61
4
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Part Number
Am29LV640MT/B
110R
VCC = 3.0–3.6 V
VCC = 2.7–3.6 V
90R
100R
100
100
100
30
120R
Speed
Option
110
120
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page access time (tPACC
Max. OE# Access Time (ns)
Note:
90
90
25
25
110
110
120
120
)
30
30
40
40
30
30
40
40
30
1. See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ15 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
State
WP#/ACC
Control
BYTE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A21–A0
February 12, 2004
Am29LV640MT/B
5
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A19
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
48-Pin Standard TSOP
9
A20
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
VCC
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
A17
A7
A6
A5
A4
A3
A2
A1
63-ball Fine-pitch BGA (FBGA)
Top View, Balls Facing Down
L8
M8
A8
B8
NC
NC
NC*
NC*
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
VSS
NC
NC
NC*
NC*
A13
A12
A14
A15
A16
BYTE# DQ15/A-1
C6
A9
D6
A8
E6
F6
G6
H6
J6
K6
A10
A11
DQ7
DQ14
DQ13
DQ6
C5
D5
E5
F5
G5
H5
J5
K5
VCC
WE# RESET#
A21
A19
DQ5
DQ12
DQ4
C4 D4
E4
F4
G4
H4
J4
K4
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
C3
A7
D3
E3
A6
F3
A5
G3
H3
J3
K3
A17
DQ0
DQ8
DQ9
DQ1
C2
A3
D2
A4
E2
A2
F2
A1
G2
A0
H2
J2
K2
L2
M2
A2
VSS
CE#
OE#
NC*
NC*
NC*
A1
B1
L1
M1
* Balls are shorted together via the substrate but not connected to the die.
NC*
NC*
NC*
NC*
6
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
64-Ball Fortified BGA (fBGA)
Top View, Balls Facing Down
A8
B8
C8
D8
E8
F8
G8
NC
H8
NC
NC
NC
NC
VSS
NC
NC
A7
B7
C7
D7
E7
F7
G7
H7
A13
A12
A14
A15
A16
BYTE# DQ15/A-1 VSS
A6
A9
B6
A8
C6
D6
E6
F6
G6
H6
DQ6
A10
A11
DQ7
DQ14
DQ13
A5
B5
C5
D5
E5
F5
G5
H5
WE# RESET#
A21
A19
DQ5
DQ12
VCC
DQ4
A4 B4
C4
D4
E4
F4
G4
H4
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
A3
A7
B3
C3
A6
D3
A5
E3
F3
G3
H3
A17
DQ0
DQ8
DQ9
DQ1
A2
A3
B2
A4
C2
A2
D2
A1
E2
A0
F2
G2
H2
CE#
OE#
VSS
A1
B1
C1
D1
E1
F1
G1
NC
H1
NC
NC
NC
NC
NC
NC
NC
and/or data integrity may be compromised if the
package body is exposed to temperatures above 150°C
for prolonged periods of time.
Special Package Handling Instructions
Special handling is required for Flash Memory products
in molded packages (TSOP and BGA). The package
February 12, 2004
Am29LV640MT/B
7
A D V A N C E I N F O R M A T I O N
PIN DESCRIPTION
LOGIC SYMBOL
A21–A0
= 22 Address inputs
22
DQ14–DQ0 = 15 Data inputs/outputs
A21–A0
16 or 8
DQ15/A-1
= DQ15 (Data input/output, word mode),
DQ15–DQ0
(A-1)
CE#
OE#
WE#
A-1 (LSB Address input, byte mode)
CE#
= Chip Enable input
OE#
= Output Enable input
WP#/ACC
RESET#
BYTE#
WE#
= Write Enable input
WP#/ACC
= Hardware Write Protect input/Pro-
gramming Acceleration input
RY/BY#
RESET#
RY/BY#
BYTE#
VCC
= Hardware Reset Pin input
= Ready/Busy output
= Selects 8-bit or 16-bit mode
= 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and voltage
supply tolerances)
VSS
NC
= Device Ground
= Pin Not Connected Internally
8
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29LV640M
T
120R
PC
I
TEMPERATURE RANGE
Industrial (–40°C to +85°C)
I
=
PACKAGE TYPE
E
=
=
48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
PC
64-Ball Fortified Ball Grid Array
1.0 mm pitch, 13 x 11 mm package (LAA064)
WH
=
63-Ball Fine Pitch Ball Grid Array
0.80 mm pitch, 12 x 11 mm package (FBE063)
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE AND WP# PROTECTION (WP# = VIL)
T
B
=
=
Top boot sector device, top two address sectors protected
Bottom boot sector device, bottom two address sectors protected
DEVICE NUMBER/DESCRIPTION
Am29LV640MT/B
64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit™ Boot Sector Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations for
Speed
(ns)
VCC
Range
Valid Combinations for
TSOP Package
Speed
(ns)
VCC
Range
BGA Packages
Order Number Package Marking
WHI L640MT90RI
Am29LV640MT90R,
Am29LV640MB90R
90
3.0–3.6 V
Am29LV640MT90R
Am29LV640MB90R
Am29LV640MT100
Am29LV640MB100
Am29LV640MT110
Am29LV640MB110
Am29LV640MT120
Am29LV640MB120
Am29LV640MT100R
Am29LV640MB100R
Am29LV640MT110R
Am29LV640MB110R
Am29LV640MT120R
Am29LV640MB120R
PCI L640MT90NI
WHI L640MB90RI
PCI L640MB90NI
WHI L640MT10VI
PCI L640MT10PI
WHI L640MB10VI
PCI L640MB10PI
WHI L640MT11VI
PCI L640MT11PI
WHI L640MB11VI
PCI L640MB11PI
WHI L640MT12VI
PCI L640MT12PI
WHI L640MB12VI
PCI L640MB12PI
WHI L640MT10RI
PCI L640MT10NI
WHI L640MB10RI
PCI L640MB10NI
WHI L640MT11RI
PCI L640MT11NI
WHI L640MB11RI
PCI L640MB11NI
WHI L640MT12RI
PCI L640MT12NI
WHI L640MB12RI
PCI L640MB12NI
3.0–
3.6 V
90
Am29LV640MT100,
Am29LV640MB100
100
110
120
100
110
120
Am29LV640MT110,
Am29LV640MB110
2.7–3.6 V
100
110
120
100
110
120
Am29LV640MT120,
Am29LV640MB120
EI
Am29LV640MT100R,
Am29LV640MB100R
2.7–
3.6 V
3.0–3.6 V
Am29LV640MT110R,
Am29LV640MB110R
Am29LV640MT120R,
Am29LV640MB120R
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
3.0–
3.6 V
February 12, 2004
Am29LV640MT/B
9
A D V A N C E I N F O R M A T I O N
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
DQ8–DQ15
DQ0–
DQ7
BYTE#
= VIH
BYTE#
= VIL
Addresses
(Note 2)
Operation
CE# OE# WE# RESET#
WP#
X
ACC
X
Read
L
L
L
L
H
H
H
L
L
H
H
H
AIN
AIN
AIN
DOUT
DOUT
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
Accelerated Program
(Note 3)
(Note 3)
X
(Note 4) (Note 4)
(Note 4) (Note 4)
VHH
VCC
0.3 V
VCC
0.3 V
Standby
X
X
X
H
X
High-Z High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
X
X
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
SA, A6 =L,
A3=L, A2=L, (Note 4)
A1=H, A0=L
Sector Group Protect
(Note 2)
L
H
L
VID
H
X
X
X
X
SA, A6=H,
A3=L, A2=L, (Note 4)
A1=H, A0=L
Sector Group Unprotect
(Note 2)
L
H
X
L
VID
VID
H
H
X
X
X
Temporary Sector Group
Unprotect
X
X
AIN
(Note 4) (Note 4)
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
IN = Address In, DIN = Data In, DOUT = Data Out
A
Notes:
1. Addresses are A21:A0 in word mode; A21:A-1 in byte mode. Sector addresses are A21:A12 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
3. If WP# = VIL, the first or last sector remains protected. If WP# = VIH, the top two or bottom two sectors will be protected or
unprotected as determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected
when shipped from the factory (The SecSi Sector may be factory protected depending on version ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
Requirements for Reading Array Data
BYTE# pin is set at logic ‘1’, the device is in word con-
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
10
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
The internal state machine is set for reading array data
acteristics section contains timing specification tables
and timing diagrams for write operations.
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
Write Buffer
Write Buffer Programming allows the system to write a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms. See
“Write Buffer” for more information.
Accelerated Program Operation
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing speci-
fications and to Figure 14 for the timing diagram. Refer
to the DC Characteristics table for the active current
specification on reading array data.
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
Page Mode Read
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the WP#/ACC pin returns the device to nor-
mal operation. Note that the WP#/ACC pin must not be
at VHH for operations other than accelerated program-
ming, or device damage may result. In addition, no ex-
ternal pullup is necessary since the WP#/ACC pin has
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is
selected by the higher address bits A(max)–A2. Ad-
dress bits A1–A0 in word mode (A1–A-1 in byte mode)
determine the specific word within a page. This is an
asynchronous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to tACC or
tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Fast page mode ac-
cesses are obtained by keeping the “read-page ad-
dresses” constant and changing the “intra-read page”
addresses.
internal pullup to VCC
.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command se-
quences.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode,
but the standby current will be greater. The device re-
quires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 3 and 2 indicates the
address space that each sector occupies.
Refer to the DC Characteristics table for the active
current specification for the write mode. The AC Char-
February 12, 2004
Am29LV640MT/B
11
A D V A N C E I N F O R M A T I O N
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Refer to the DC Characteristics table for the standby
current specification.
Automatic Sleep Mode
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for tACC
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the DC Characteristics table for the automatic
sleep mode current specification.
+
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 16 for the timing diagram.
RESET#: Hardware Reset Pin
Output Disable Mode
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 2. Am29LV640MT Top Boot Sector Architecture
Sector Address
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
A21–A12
SA0
SA1
0000000xxx
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
12
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
Table 2. Am29LV640MT Top Boot Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
Address Range
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
0011000xxx
0011101xxx
0011110xxx
0011111xxx
0100000xxx
0100001xxx
0100010xxx
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
0101111xxx
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0100100xxx
0110101xxx
0110110xxx
0110111xxx
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
0111110xxx
0111111xxx
1000000xxx
1000001xxx
1000010xxx
1000011xxx
1000100xxx
1000101xxx
1000110xxx
1000111xxx
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
1010000xxx
1010001xxx
1010010xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
400000h–40FFFFh
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
470000h–47FFFFh
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
4B0000h–4BFFFFh
4C0000h–4CFFFFh
4D0000h–4DFFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
February 12, 2004
Am29LV640MT/B
13
A D V A N C E I N F O R M A T I O N
Table 2. Am29LV640MT Top Boot Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
Address Range
SA83
SA84
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
1011101xxx
1011110xxx
1011111xxx
1100000xxx
1100001xxx
1100010xxx
1100011xxx
1100100xxx
1100101xxx
1100110xxx
1100111xxx
1101000xxx
1101001xxx
1101010xxx
1101011xxx
1101100xxx
1101101xxx
1101110xxx
1101111xxx
1110000xxx
1110001xxx
1110010xxx
1110011xxx
1110100xxx
1110101xxx
1110110xxx
1110111xxx
1111000xxx
1111001xxx
1111010xxx
1111011xxx
1111100xxx
1111101xxx
1111110xxx
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
580000h–58FFFFh
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
650000h–65FFFFh
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
6B0000h–6BFFFFh
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7F1FFFh
7F2000h–7F3FFFh
7F4000h–7F5FFFh
7F6000h–7F7FFFh
7F8000h–7F9FFFh
7FA000h–7FBFFFh
7FC000h–7FDFFFh
7FE000h–7FFFFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3F8FFFh
3F9000h–3F9FFFh
3FA000h–3FAFFFh
3FB000h–3FBFFFh
3FC000h–3FCFFFh
3FD000h–3FDFFFh
3FE000h–3FEFFFh
3FF000h–3FFFFFh
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
8/4
8/4
8/4
8/4
8/4
8/4
8/4
14
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
Table 3. Am29LV640MB Bottom Boot Sector Architecture
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
Address Range
SA0
SA1
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
0011101xxx
0011110xxx
0011111xxx
0100000xxx
0100001xxx
0100010xxx
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
8/4
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
8/4
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
February 12, 2004
Am29LV640MT/B
15
A D V A N C E I N F O R M A T I O N
Table 3. Am29LV640MB Bottom Boot Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
Address Range
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
0101111xxx
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0100100xxx
0110101xxx
0110110xxx
0110111xxx
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
0111110xxx
0111111xxx
1000000xxx
1000001xxx
1000010xxx
1000011xxx
1000100xxx
1000101xxx
1000110xxx
1000111xxx
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
1010000xxx
1010001xxx
1010010xxx
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
1011101xxx
1011110xxx
1011111xxx
1100000xxx
1100001xxx
1100010xxx
1100011xxx
1100100xxx
1100101xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
400000h–40FFFFh
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
470000h–47FFFFh
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
4B0000h–4BFFFFh
4C0000h–4CFFFFh
4D0000h–4DFFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
580000h–58FFFFh
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
650000h–65FFFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
16
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
Table 3. Am29LV640MB Bottom Boot Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
Address Range
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
1100110xxx
1100111xxx
1101000xxx
1101001xxx
1101010xxx
1101011xxx
1101100xxx
1101101xxx
1101110xxx
1101111xxx
1110000xxx
1110001xxx
1110010xxx
1110011xxx
1110100xxx
1110101xxx
1110110xxx
1110111xxx
1111000xxx
1111001xxx
1111010xxx
1111011xxx
1111100xxx
1111101xxx
1111110xxx
1111111000
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
6B0000h–6BFFFFh
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7FFFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3FFFFFh
Note: The address range is A21:A-1 in byte mode (BYTE# = VIL) or A21:A0 in word mode (BYTE# = VIH)
February 12, 2004
Am29LV640MT/B
17
A D V A N C E I N F O R M A T I O N
In addition, when verifying sector protection, the sector
Autoselect Mode
address must appear on the appropriate highest order
address bits (see Tables 2 and 3). Table 4 shows the
remaining address bits that are don’t care. When all
necessary bits have been set as required, the pro-
gramming equipment may then read the correspond-
ing identifier code on DQ7–DQ0.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Tables 12 and 13. This
method does not require VID. Refer to the Autoselect
Command Sequence section for more information.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A3, A2, A1, and A0 must be as shown in Table 4.
Table 4. Autoselect Codes, (High Voltage Method)
DQ8 to DQ15
A21 A14
A8
A9 to A6
A7
A5 A3
to to
A4 A2
Description
CE# OE# WE# to
to
A1 A0
DQ7 to DQ0
BYTE# BYTE#
A15 A10
= VIH
= VIL
VID
Manufacturer ID: AMD
Cycle 1
L
L
L
L
H
H
X
X
X
X
X
L
X
L
L
L
L
L
H
L
00
X
01h
7Eh
10h
22
X
Cycle 2
H
H
22
X
VID
X
L
X
00 (bottom boot)
01h (top boot)
Cycle 3
H
L
H
H
H
L
22
X
X
X
Sector Protection
Verification
01h (protected),
00h (unprotected)
VID
L
L
L
L
H
H
SA
X
X
X
X
X
L
L
X
X
SecSi Sector Indicator
Bit (DQ7), WP#
protects top two
address sector
98h (factory locked),
18h (not factory locked)
VID
L
L
H
H
H
H
X
X
X
X
SecSi Sector Indicator
Bit (DQ7), WP#
protects bottom two
address sector
88h (factory locked),
08h (not factory locked)
VID
L
L
H
X
X
X
L
X
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
18
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
Sector Group Protection and
Unprotection
Sector/
Sector Block Size
Sector
A21–A12
SA80-SA83
SA84-SA87
SA88-SA91
SA92-SA95
SA96-SA99
SA100-SA103
SA104-SA107
SA108-SA111
SA112-SA115
SA116-SA119
SA120-SA123
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
The hardware sector group protection feature disables
both program and erase operations in any sector
group. In this device, a sector group consists of four
adjacent sectors that are protected or unprotected at
the same time (see Tables 5 and 6). The hardware
sector group unprotection feature re-enables both pro-
gram and erase operations in previously protected
sector groups. Sector group protection/unprotection
can be implemented via two methods.
Sector protection/unprotection requires VID on the RE-
SET# pin only, and can be implemented either in-sys-
tem or via programming equipment. Figure 2 shows
the algorithms and Figure 24 shows the timing dia-
gram. This method uses standard microprocessor bus
cycle timing. For sector group unprotect, all unpro-
tected sector groups must first be protected prior to
the first sector group unprotect write cycle.
1111100XXX
1111101XXX
1111110XXX
SA124-SA126
192 (3x64) Kbytes
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
The device is shipped with all sector groups unpro-
tected. AMD offers the option of programming and pro-
tecting sector groups at its factory prior to shipping the
device through AMD’s ExpressFlash™ Service. Con-
tact an AMD representative for details.
It is possible to determine whether a sector group is
protected or unprotected. See the Autoselect Mode
section for details.
Table 6. Am29LV640MB Bottom Boot
Sector Protection
Table 5. Am29LV640MT Top Boot
Sector Protection
Sector/
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A21–A12
Sector Block Size
Sector/
Sector
A21–A12
Sector Block Size
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
8 Kbytes
SA0-SA3
00000XXXXX
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
8 Kbytes
SA4-SA7
8 Kbytes
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
SA44-SA47
SA48-SA51
SA52-SA55
SA56-SA59
SA60-SA63
SA64-SA67
SA68-SA71
SA72-SA75
SA76-SA79
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
0000001XXX,
0000010XXX,
0000011XXX,
SA8–SA10
192 (3x64) Kbytes
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
February 12, 2004
Am29LV640MT/B
19
A D V A N C E I N F O R M A T I O N
Table 6. Am29LV640MB Bottom Boot
Sector Protection (Continued)
Temporary Sector Group Unprotect
(Note: In this device, a sector group consists of four adjacent
sectors that are protected or unprotected at the same time
(see Table 6).
Sector/
Sector
A21–A12
Sector Block Size
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
This feature allows temporary unprotection of previ-
ously protected sector groups to change data in-sys-
tem. The Sector Group Unprotect mode is activated by
setting the RESET# pin to VID. During this mode, for-
merly protected sector groups can be programmed or
erased by selecting the sector group addresses. Once
VID is removed from the RESET# pin, all the previously
protected sector groups are protected again. Figure 1
shows the algorithm, and Figure 23 shows the timing
diagrams, for this feature.
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
SA83–SA86
SA87–SA90
SA91–SA94
SA95–SA98
SA99–SA102
SA103–SA106
SA107–SA110
SA111–SA114
SA115–SA118
SA119–SA122
SA123–SA126
SA127–SA130
SA131–SA134
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
11111XXXXX
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting the top two or bottom two sectors
without using VID. WP# is one of two functions pro-
vided by the WP#/ACC input.
Temporary Sector
Group Unprotect
Completed (Note 2)
If the system asserts VIL on the WP#/ACC pin, the de-
vice disables program and erase functions in the first
or last sector independently of whether those sectors
were protected or unprotected using the method de-
scribed in “Sector Group Protection and Unprotection”.
Note that if WP#/ACC is at VIL when the device is in
the standby mode, the maximum input load current is
increased. See the table in “DC Characteristics”.
Notes:
1. All protected sector groups unprotected (If WP# = VIL,
the first or last sector will remain protected).
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group
Unprotect Operation
If the system asserts VIH on the WP#/ACC pin, the de-
vice reverts to whether the top or bottom two sectors
were previously set to be protected or unprotected
using the method described in “Sector Group Protec-
tion and Unprotection”. Note: No external pullup is
necessary since the WP#/ACC pin has internal pullup
to VCC
20
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
START
START
PLSCNT = 1
PLSCNT = 1
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
RESET# = VID
Wait 1 µs
Wait 1 µs
Temporary Sector
Group Unprotect
Mode
Temporary Sector
Group Unprotect
Mode
No
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Yes
Yes
Set up sector
group address
All sector
groups
No
protected?
Yes
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up first sector
group address
Sector Group
Unprotect:
Wait 150 µs
Write 60h to sector
group address with
A6–A0 = 1xx0010
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
Read from
sector group address
with A6–A0
= 0xx0010
Increment
PLSCNT
A6–A0 = 1xx0010
No
No
PLSCNT
= 25?
Read from
sector group
address with
Data = 01h?
Yes
A6–A0 = 1xx0010
No
Yes
Set up
next sector group
address
Protect
another
sector group?
Yes
No
PLSCNT
= 1000?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
Last sector
group
verified?
No
Device failed
Write reset
command
Yes
Remove VID
from RESET#
Sector Group
Unprotect
Sector Group
Protect
Sector Group
Protect complete
Write reset
command
Algorithm
Algorithm
Sector Group
Unprotect complete
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
Am29LV640MT/B
February 12, 2004
21
A D V A N C E I N F O R M A T I O N
Factory Locked: SecSi Sector Programmed and
SecSi (Secured Silicon) Sector Flash
Memory Region
Protected At the Factory
In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. See Table 7 for
SecSi Sector addressing.
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 128 words/256 bytes in
length, and uses a SecSi Sector Indicator Bit (DQ7) to
indicate whether or not the SecSi Sector is locked
when shipped from the factory. This bit is permanently
set at the factory and cannot be changed, which pre-
vents cloning of a factory locked part. This ensures the
security of the ESN once the product is shipped to the
field.
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. The de-
vices are then shipped from AMD’s factory with the
SecSi Sector permanently locked. Contact an AMD
representative for details on using AMD’s Express-
Flash service.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unprotected, allowing customers to program the
sector after receiving the device. The customer-lock-
able version also has the SecSi Sector Indicator Bit
permanently set to a “0.” Thus, the SecSi Sector Indi-
cator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
As an alternative to the factory-locked version, the de-
vice may be ordered such that the customer may pro-
gram and protect the 128-word/256 bytes SecSi
sector.
The system may program the SecSi Sector using the
write-buffer, accelerated and/or unlock bypass meth-
ods, in addition to the standard programming com-
mand sequence. See Command Definitions.
Programming and protecting the SecSi Sector must be
used with caution since, once protected, there is no
procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory
space can be modified in any way.
The SecSi sector address space in this device is allo-
cated as follows:
Table 7. SecSi Sector Contents
SecSi Sector Address
Standard
Factory
Locked
The SecSi Sector area can be protected using one of
the following procedures:
Range
ExpressFlash
Factory Locked
Customer
Lockable
x16
x8
ESN or
determined
by customer
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RESET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
000000h–
000007h
000000h–
00000Fh
ESN
Determined
by customer
000008h–
00007Fh
000010h–
0000FFh
Determined
by customer
Unavailable
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresses normally occupied by the first sector (SA0).
This mode of operation continues until the system is-
sues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to sector SA0. Note that the ACC
function and unlock bypass modes are not available
when the SecSi Sector is enabled.
■ To verify the protect/unprotect status of the SecSi
Sector, follow the algorithm shown in Figure 3.
Once the SecSi Sector is programmed, locked and
verified, the system must write the Exit SecSi Sector
Region command sequence to return to reading and
writing within the remainder of the array.
22
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
START
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
RESET# =
VIH or VID
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is
Wait 1 ms
Write 60h to
any address
Remove VIH or VID
from RESET#
Write 40h to SecSi
Sector address
with A6 = 0,
Write reset
command
greater than VLKO
.
A1 = 1, A0 = 0
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
SecSi Sector
Protect Verify
complete
Read from SecSi
Sector address
with A6 = 0,
Logical Inhibit
A1 = 1, A0 = 0
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Figure 3. SecSi Sector Protect Verify
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Tables 12 and 13
for command definitions). In addition, the following
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 8–11. The
system must write the reset command to return the
device to reading array data.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi. Alterna-
tively, contact an AMD representative for copies of
these documents.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables 8–11. To terminate reading CFI data,
the system must write the reset command.
February 12, 2004
Am29LV640MT/B
23
A D V A N C E I N F O R M A T I O N
Table 8. CFI Query Identification String
Addresses
(x16)
Addresses
(x8)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Table 9. System Interface String
Addresses
(x16)
Addresses
(x8)
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
1Ch
36h
38h
0027h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0007h
0007h
000Ah
0000h
0001h
0005h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
24
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
Table 10. Device Geometry Definition
Addresses Addresses
(x16)
(x8)
Data
Description
27h
4Eh
0017h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device (01h = uniform device, 02h = boot
device)
2Ch
58h
0002h
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
007Fh
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
007Eh
0000h
0000h
0001h
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
February 12, 2004
Am29LV640MT/B
25
A D V A N C E I N F O R M A T I O N
Table 11. Primary Vendor-Specific Extended Query
Addresses Addresses
(x16)
(x8)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
0008h
Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
8Ch
8Eh
90h
92h
94h
96h
98h
0002h
0001h
0001h
0004h
0000h
0000h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = 29LV800 mode
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
9Ah
9Ch
00B5h
00C5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
0002h/
0003h
00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top
Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top
WP# protect
4Fh
50h
9Eh
A0h
Program Suspend
0001h
00h = Not Supported, 01h = Supported
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Tables 12 and 13 define the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper sequence
may place the device in an unknown state. A reset
command is then required to return the device to read-
ing array data.
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
26
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
which the system can read data from any
Autoselect Command Sequence
non-erase-suspended sector. After completing a pro-
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The autoselect command sequence allows the host
system to read several identifier codes at specific ad-
dresses:
A7:A0
(x16)
A6:A-1
(x8)
Identifier Code
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode if
DQ5 goes high during an active program or erase op-
eration, or if the device is in the autoselect mode. See
the next section, Reset Command, for more informa-
tion.
Manufacturer ID
Device ID, Cycle 1
00h
01h
00h
02h
Device ID, Cycle 2
0Eh
1Ch
Device ID, Cycle 3
0Fh
1Eh
SecSi Sector Factory Protect
Sector Protect Verify
03h
06h
(SA)02h
(SA)04h
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read pa-
rameters, and Figure 14 shows the timing diagram.
Note: The device ID is read over three cycles. SA = Sector
Address
Tables 12 and 13 show the address and data require-
ments. This method is an alternative to that shown in
Table 4, which is intended for PROM programmers
and requires VID on address pin A9. The autoselect
command sequence may be written to an address that
is either in the read or erase-suspend-read mode. The
autoselect command may not be written while the de-
vice is actively programming or erasing.
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autoselect command sequence.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing an 8-word/16-byte random Electronic Serial
Number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi
Sector command sequence. The device continues to
access the SecSi Sector region until the system is-
sues the four-cycle Exit SecSi Sector command se-
quence. The Exit SecSi Sector command sequence
returns the device to normal operation. Tables 12 and
13 show the address and data requirements for both
command sequences. See also “SecSi (Secured Sili-
con) Sector Flash Memory Region” for further informa-
tion.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Pro-
gramming operation, the system must write the
Write-to-Buffer-Abort Reset command sequence to
reset the device for the next operation.
Word/Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
February 12, 2004
Am29LV640MT/B
27
A D V A N C E I N F O R M A T I O N
controls or timings. The device automatically provides
Write Buffer Programming
internally generated program pulses and verifies the
programmed cell margin. Tables 12 and 13 show the
address and data requirements for the word program
command sequence. Note that the autoselect and CFI
functions are unavailable when a program operation is
in progress.
Write Buffer Programming allows the system write to a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms. The
Write Buffer Programming command sequence is initi-
ated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which pro-
gramming will occur. The fourth cycle writes the sector
address and the number of word locations, minus one,
to be programmed. For example, if the system will pro-
gram 6 unique address locations, then 05h should be
written to the device. This tells the device how many
write buffer addresses will be loaded with data and
therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot
exceed the size of the write buffer or the operation will
abort.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7 or DQ6. Refer to the Write Operation Status sec-
tion for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
The fifth cycle writes the first address location and
data to be programmed. The write-buffer-page is se-
lected by address bits AMAX–A4. All subsequent ad-
dress/data pairs must fall within the
selected-write-buffer-page. The system then writes the
remaining address/data pairs into the write buffer.
Write buffer locations may be loaded in any order.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
The write-buffer-page address must be the same for
all address/data pairs loaded into the write buffer.
(This means Write Buffer Programming cannot be per-
formed across multiple write-buffer pages. This also
means that Write Buffer Programming cannot be per-
formed across multiple sectors. If the system attempts
to load programming data outside of the selected
write-buffer page, the operation will abort.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram words to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Tables 12 and 13 show the requirements
for the command sequence.
Note that if a Write Buffer address location is loaded
multiple times, the address/data pair counter will be
decremented for every data load operation. The host
system must therefore account for loading a
write-buffer location more than once. The counter dec-
rements for each data load operation, not for each
unique write-buffer-address location. Note also that if
an address location is loaded more than once into the
buffer, the final data loaded for that address will be
programmed.
Once the specified number of write buffer locations
have been loaded, the system must then write the Pro-
gram Buffer to Flash command at the sector address.
Any other address and data combination aborts the
Write Buffer Programming operation. The device then
begins programming. Data polling should be used
while monitoring the last address location loaded into
the write buffer. DQ7, DQ6, DQ5, and DQ1 should be
monitored to determine the device status during Write
Buffer Programming.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
28
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
The write-buffer programming operation can be sus-
command sequence must be written to reset the de-
vice for the next operation. Note that the full 3-cycle
Write-to-Buffer-Abort Reset command sequence is re-
quired when using Write-Buffer-Programming features
in Unlock Bypass mode.
pended using the standard program suspend/resume
commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to
execute the next command.
The Write Buffer Programming Sequence can be
aborted in the following ways:
Accelerated Program
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at VHH for operations
other than accelerated programming, or device dam-
age may result. In addition, no external pullup is nec-
essary since the WP#/ACC pin has internal pullup to
■ Load a value that is greater than the page buffer
size during the Number of Locations to Program
step.
■ Write to an address in a sector different than the
one specified during the Write-Buffer-Load com-
mand.
■ Write an Address/Data pair to
a
different
write-buffer-page than the one selected by the
Starting Address during the write buffer data load-
ing stage of the operation.
VCC
.
■ Write data other than the Confirm Command after
Figure 5 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 17 for timing diagrams.
the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 =
DATA# (for the last address location loaded), DQ6 =
toggle, and DQ5=0. A Write-to-Buffer-Abort Reset
February 12, 2004
Am29LV640MT/B
29
A D V A N C E I N F O R M A T I O N
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Yes
Buffer Operation?
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
(Note 1)
Write next address/data pair
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Notes:
1. When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.
Read DQ7 - DQ0 at
Last Loaded Address
2. DQ7 may change simultaneously with DQ5.
Therefore, DQ7 should be verified.
3. If this flowchart location was reached because
DQ5= “1”, then the device FAILED. If this
flowchart location was reached because DQ1=
“1”, then the Write to Buffer operation was
ABORTED. In either case, the proper reset
command must be written before the device can
begin another operation. If DQ1=1, write the
Write-Buffer-Programming-Abort-Reset
Yes
DQ7 = Data?
No
No
command. if DQ5=1, write the Reset command.
No
DQ1 = 1?
Yes
DQ5 = 1?
Yes
4. See Table 13 for command sequences required for
write buffer programming.
Read DQ7 - DQ0 with
address = Last Loaded
Address
Yes
(Note 2)
DQ7 = Data?
No
(Note 3)
FAIL or ABORT
PASS
Figure 4. Write Buffer Programming Operation
Am29LV640MT/B
30
February 12, 2004
A D V A N C E I N F O R M A T I O N
Program Suspend/Program Resume
Command Sequence
The Program Suspend command allows the system to
interrupt a programming operation or a Write to Buffer
programming operation so that data can be read from
any non-suspended sector. When the Program Sus-
pend command is written during a programming pro-
cess, the device halts the program operation within 15
µs maximum (5 µs typical) and updates the status bits.
Addresses are not required when writing the Program
Suspend command.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
After the programming operation has been sus-
pended, the system can read array data from any
non-suspended sector. The Program Suspend com-
mand may also be issued during a programming oper-
ation while an erase is suspended. In this case, data
may be read from any addresses not in Erase Sus-
pend or Program Suspend. If a read is needed from
the SecSi Sector area (One-time Program area), then
user must use the proper command sequences to
enter and exit this region.
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autoselect codes
as required. When the device exits the autoselect
mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See
Autoselect Command Sequence for more information.
Programming
Completed
Note: See Table 13 for program command sequence.
After the Program Resume command is written, the
device reverts to programming. The system can deter-
mine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard pro-
gram operation. See Write Operation Status for more
information.
Figure 5. Program Operation
February 12, 2004
Am29LV640MT/B
31
A D V A N C E I N F O R M A T I O N
The system must write the Program Resume com-
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2.
Refer to the Write Operation Status section for infor-
mation on these status bits.
mand (address bits are don’t care) to exit the Program
Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ig-
nored. Another Program Suspend command can be
written after the device has resume programming.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Write address/data
XXXh/B0h
Command Sequence
Figure 7 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 19 section for timing diagrams.
Command is also valid for
Erase-suspended-program
operations
Wait 15 µs
Sector Erase Command Sequence
Autoselect and SecSi Sector
Read data as
required
read operations are also allowed
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Tables 12 and 13 shows
the address and data requirements for the sector
erase command sequence. Note that the autoselect
and CFI functions are unavailable when an erase op-
eration is in progress.
Data cannot be read from erase- or
program-suspended sectors
Done
reading?
No
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
Device reverts to
operation prior to
Program Suspend
Figure 6. Program Suspend/Program Resume
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase ad-
dress and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to en-
sure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets
the device to the read mode. The system must re-
write the command sequence and any additional ad-
dresses and commands.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Tables 12 and
13 shows the address and data requirements for the
chip erase command sequence. Note that the autose-
lect and CFI functions are unavailable when an erase
operation is in progress.
32
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
START
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6, or
DQ2 in the erasing sector. Refer to the Write Opera-
tion Status section for information on these status bits.
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Figure 7 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 19 section for timing diagrams.
Yes
Erasure Completed
Notes:
1. See Table 12 and Table 13 for erase command
sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 7. Erase Operation
February 12, 2004
Am29LV640MT/B
33
A D V A N C E I N F O R M A T I O N
Autoselect Mode and Autoselect Command Sequence
Erase Suspend/Erase Resume
Commands
sections for details.
To resume the sector erase operation, the system
must write the Erase Resume command. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip
has resumed erasing.
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the sec-
tor erase operation, including the 50 µs time-out pe-
riod during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.
Note: During an erase operation, this flash device per-
forms multiple internal operations which are invisible
to the system. When an erase operation is suspended,
any of the internal operations that were not fully com-
pleted must be restarted. As such, if this flash device
is continually issued suspend/resume commands in
rapid succession, erase progress will be impeded as a
function of the number of suspends. The result will be
a longer cumulative erase time than without suspends.
Note that the additional suspends do not affect device
reliability or future performance. In most systems rapid
erase/suspend activity occurs only briefly. In such
cases, erase performance will not be significantly im-
pacted.
When the Erase Suspend command is written during
the sector erase operation, the device requires a typi-
cal of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend com-
mand is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation.
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for infor-
mation on these status bits.
After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard word program operation.
Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
34
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
Command Definitions
Table 12. Command Definitions (x16 Mode, BYTE# = VIH)
Bus Cycles (Notes 1–4)
First
Second
Third
Fourth
Fifth
Sixth
Command Sequence
(Notes)
Addr Data
Addr Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
RA
XXX
555
RD
F0
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
2200/
X0E 2210 X0F
2201
Device ID (Note 8)
6
4
4
555
555
555
AA
AA
AA
SecSi™ Sector Factory Protect
(Note 9)
2AA
2AA
55
55
555
555
90
90
X03
(Note 9)
00/01
Sector Group Protect Verify
(Note 10)
(SA)X02
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
6
1
3
3
2
2
6
6
1
1
1
555
555
555
555
SA
AA
AA
AA
AA
29
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
00
PD
WC
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 12)
Unlock Bypass
SA
PA
PD
WBL
PD
555
555
XXX
XXX
555
555
XXX
XXX
55
AA
AA
A0
90
2AA
2AA
PA
55
55
PD
00
55
55
555
555
F0
20
Unlock Bypass Program (Note 13)
Unlock Bypass Reset (Note 14)
Chip Erase
XXX
2AA
2AA
AA
AA
B0
30
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend (Note 15)
Program/Erase Resume (Note 16)
CFI Query (Note 17)
98
Legend:
X = Don’t care
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE#
or CE# pulse, whichever happens later.
WC = Word Count. Number of write buffer locations to load minus 1.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
bottom two address sectors, the data is 88h for factory locked and
08h for not factor locked.
2. All values are in hexadecimal.
10. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
11. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 21.
4. During unlock cycles, when lower address bits are 555 or 2AAh
as shown in table, address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
5. No unlock or command cycles required when device is in read
mode.
13. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
6. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
while the device is providing status information.
14. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
7. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. Except RD, PD and
WC. See the Autoselect Command Sequence section for more
information.
15. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
8. The device ID must be read in three cycles. The data is 2201h for
top boot and 2200h for bottom boot.
16. The Erase Resume command is valid only during the Erase
Suspend mode.
9. If WP# protects the top two address sectors, the data is 98h for
factory locked and 18h for not factory locked. If WP# protects the
17. Command is valid when device is ready to read array data or when
device is in autoselect mode.
February 12, 2004
Am29LV640MT/B
35
A D V A N C E I N F O R M A T I O N
Table 13. Command Definitions (x8 Mode, BYTE# = VIL)
Bus Cycles (Notes 1–4)
First
Second
Third
Fourth
Fifth
Sixth
Command Sequence
(Notes)
Addr Data
Addr Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
6
RA
RD
F0
XXX
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
90
90
X00
X02
01
7E
Device ID (Note 8)
X1C
10
X1E 00/01
SecSi™ Sector Factory Protect
(Note 9)
4
4
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
90
90
X06
(Note 9)
00/01
Sector Group Protect Verify
(Note 10)
(SA)X04
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
6
1
3
3
2
2
6
6
1
1
1
AAA
AAA
AAA
AAA
SA
AA
AA
AA
AA
29
555
555
555
555
55
55
55
55
AAA
AAA
AAA
SA
88
90
A0
25
XXX
PA
00
PD
BC
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 12)
Unlock Bypass
SA
PA
PD
WBL
PD
AAA
AAA
XXX
XXX
AAA
AAA
XXX
XXX
AA
AA
AA
A0
90
555
555
PA
55
55
PD
00
55
55
AAA
AAA
F0
20
Unlock Bypass Program (Note 13)
Unlock Bypass Reset (Note 14)
Chip Erase
XXX
555
555
AA
AA
B0
30
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Program/Erase Suspend (Note 15)
Program/Erase Resume (Note 16)
CFI Query (Note 17)
98
Legend:
X = Don’t care
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE#
or CE# pulse, whichever happens later.
BC = Byte Count. Number of write buffer locations to load minus 1.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
bottom two address sectors, the data is 88h for factory locked and
08h for not factor locked.
2. All values are in hexadecimal.
10. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
11. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 37.
4. During unlock cycles, when lower address bits are 555 or AAAh
as shown in table, address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
5. No unlock or command cycles required when device is in read
mode.
13. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
6. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
while the device is providing status information.
14. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
7. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect
Command Sequence section for more information.
15. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
8. The device ID must be read in three cycles. The data is 01h for
top boot and 00h for bottom boot
16. The Erase Resume command is valid only during the Erase
Suspend mode.
9. If WP# protects the top two address sectors, the data is 98h for
factory locked and 18h for not factory locked. If WP# protects the
17. Command is valid when device is ready to read array data or when
device is in autoselect mode.
36
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 14 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is com-
plete or in progress. The device also provides a hard-
ware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is
in progress or has been completed.
valid data, the data outputs on DQ0–DQ6 may be still
invalid. Valid data on DQ0–DQ7 will appear on suc-
cessive read cycles.
Table 14 shows the outputs for Data# Polling on DQ7.
Figure 8 shows the Data# Polling algorithm. Figure 20
in the AC Characteristics section shows the Data#
Polling timing diagram.
DQ7: Data# Polling
START
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 µs, then the device returns to the
read mode.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Yes
Read DQ7–DQ0
Addr = VA
Yes
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 8. Data# Polling Algorithm
February 12, 2004
Am29LV640MT/B
37
A D V A N C E I N F O R M A T I O N
After an erase command sequence is written, if all sectors
RY/BY#: Ready/Busy#
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de-
vice enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alterna-
tively, the system can use DQ7 (see the subsection on
DQ7: Data# Polling).
pull-up resistor to VCC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or in the erase-suspend-read mode. Table 14
shows the outputs for RY/BY#.
DQ6: Toggle Bit I
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 14 shows the outputs for Toggle Bit I on DQ6.
Figure 9 shows the toggle bit algorithm. Figure 21 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 22 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
38
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
START
Read DQ7–DQ0
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 14 to compare out-
puts for DQ2 and DQ6.
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
Figure 9 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the RY/BY#: Ready/Busy# sub-
section. Figure 21 shows the toggle bit timing diagram.
Figure 22 shows the differences between DQ2 and
DQ6 in graphical form.
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Reading Toggle Bits DQ6/DQ2
Refer to Figure 9 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Figure 9. Toggle Bit Algorithm
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
February 12, 2004
Am29LV640MT/B
39
A D V A N C E I N F O R M A T I O N
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 9).
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or
write-to-buffer time has exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a
“1,” indicating that the program or erase cycle was not suc-
cessfully completed.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset
command to return the device to the reading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
Table 14 shows the status of DQ3 relative to the other
status bits.
DQ3: Sector Erase Timer
DQ1: Write-to-Buffer Abort
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
DQ1 indicates whether a Write-to-Buffer operation
was aborted. Under these conditions DQ1 produces a
“1”.
The
system
must
issue
the
Write-to-Buffer-Abort-Reset command sequence to re-
turn the device to reading array data. See Write Buffer
Table 14. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
DQ1 RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Program-Suspended
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
0
Standard
Mode
N/A
Invalid (not allowed)
Data
1
1
1
1
0
Program
Suspend
Mode
Program-
Sector
Suspend
Non-Program
Read
Suspended Sector
Erase-Suspended
1
No toggle
Toggle
0
N/A
Toggle
N/A
N/A
N/A
Erase-
Sector
Suspend
Erase
Suspend
Mode
Non-EraseSuspended
Read
Data
Sector
Erase-Suspend-Program
(Embedded Program)
DQ7#
0
N/A
Busy (Note 3)
Abort (Note 4)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Write-to-
Buffer
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.
40
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
20 ns
+0.8 V
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
–0.5 V
–2.0 V
Voltage with Respect to Ground
V
CC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VIO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
20 ns
A9, OE#, ACC, and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
Figure 10. Maximum Negative
Overshoot Waveform
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 10. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to 20 ns.
See Figure 11.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2. Minimum DC input voltage on pins A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 10. Maximum DC
input voltage on pin A9, OE#, ACC, and RESET# is
+12.5 V which may overshoot to +14.0 V for periods up
to 20 ns.
2.0 V
20 ns
20 ns
Figure 11. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC for full voltage range . . . . . . . . . . . . . . . 2.7–3.6 V
VCC for regulated voltage range . . . . . . . . . . 3.0–3.6V
Note: Operating ranges define those limits between which
the functionality of the device is guaranteed.
February 12, 2004
Am29LV640MT/B
41
A D V A N C E I N F O R M A T I O N
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
(Notes)
Test Conditions
VIN = VSS to VCC
CC = VCC max
VCC = VCC max; A9 = 12.5 V
VOUT = VSS to VCC
CC = VCC max
Min
Typ
Max
1.0
35
Unit
µA
,
ILI
Input Load Current (1)
V
ILIT
ILO
ILR
A9, ACC Input Load Current
Output Leakage Current
Reset Leakage Current
µA
,
1.0
µA
V
VCC = VCC max; RESET= 12.5 V
35
20
20
50
20
60
µA
5 MHz
CE# = VIL, OE# = VIH,
1 MHz
15
15
30
10
50
VCC Active Read Current
(2, 3)
ICC1
mA
ICC2
ICC3
ICC4
VCC Initial Page Read Current (2, 3)
VCC Intra-Page Read Current (2, 3)
VCC Active Write Current (3, 4)
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
mA
mA
mA
CE#, RESET# = VCC 0.3 V,
WP# = VIH
ICC5
ICC6
ICC7
VCC Standby Current (3)
VCC Reset Current (3)
1
1
1
5
5
5
µA
µA
µA
RESET# = VSS 0.3 V, WP# = VIH
VIH = VCC 0.3 V;
VIL = VSS 0.3 V, WP# = VIH
Automatic Sleep Mode (3, 5)
VIL
VIH
Input Low Voltage
Input High Voltage
–0.5
1.9
0.8
V
V
VCC + 0.5
Voltage for Autoselect and Temporary
Sector Unprotect
VID
V
CC = 2.7 –3.6 V
11.5
12.5
V
VOL
VOH1
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
OH = –2.0 mA, VCC = VCC min
IOH = –100 µA, VCC = VCC min
0.15 x VCC
V
V
V
V
I
0.85 VCC
VCC–0.4
2.3
Output High Voltage
VOH2
VLKO
Low VCC Lock-Out Voltage (6)
2.5
Notes:
1. On the WP#/ACC pin only, the maximum input load current when
4.
I
CC active while Embedded Erase or Embedded Program is in
WP# = VIL is ± 5.0 µA.
progress.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at
VIH.
5. Automatic sleep mode enables the low power mode when
addresses remain stable for tACC + 30 ns.
3. Maximum ICC specifications are tested with VCC = VCCmax.
7. Includes RY/BY#
6. Not 100% tested.
42
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
TEST CONDITIONS
Table 15. Test Specifications
Test Condition All Speeds
Output Load 1 TTL gate
3.3 V
Unit
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
0.0–3.0
Input timing measurement
reference levels (See Note)
1.5
V
V
Output timing measurement
reference levels
0.5 VIO
Note: Diodes are IN3064 or equivalent
Figure 12. Test Setup
Note: If VIO < VCC, the reference level is 0.5 VIO.
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Changing, State Unknown
Don’t Care, Any Change Permitted
Does Not Apply
Center Line is High Impedance State (High Z)
3.0 V
1.5 V
0.5 VIO V
Input
Measurement Level
Output
0.0 V
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 13. Input Waveforms and
Measurement Levels
February 12, 2004
Am29LV640MT/B
43
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Options
100R 100 110R 110, 120R 120 Unit
JEDEC Std. Description
Test Setup
90R
tAVAV
tRC Read Cycle Time (Note 1)
Min
90
100
100
100
30
110
110
110
120
120
120
ns
ns
ns
ns
ns
ns
CE#, OE#
= VIL
tAVQV tACC Address to Output Delay
Max
90
90
25
25
tELQV
tCE Chip Enable to Output Delay
OE# = VIL Max
tPAC
Page Access Time
Max
Max
Max
30
30
16
40
40
30
30
40
40
C
tGLQV
tEHQZ
tOE Output Enable to Output Delay
30
Chip Enable to Output High Z
(Note 1)
tDF
Output Enable to Output High
Z (Note 1)
tGHQZ
tDF
Max
Min
16
0
ns
ns
Output Hold Time From
tOH Addresses, CE# or OE#,
Whichever Occurs First
tAXQX
Read
Min
Min
0
ns
ns
Output Enable
tOEH Hold Time
Toggle and
Data# Polling
10
(Note 1)
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 15 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
Output Valid
HIGH Z
HIGH Z
Outputs
RESET#
RY/BY#
0 V
Figure 14. Read Operation Timings
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Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Same Page
A21
-
-
A2
A0
A1
Ad
Aa
tACC
Ab
tPACC
Ac
tPACC
tPACC
Data Bus
Qa
Qb
Qc
Qd
CE#
OE#
* Figure shows word mode. Addresses are A1–A-1 for byte mode.
Figure 15. Page Read Timings
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Am29LV640MT/B
45
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
RESET# Pin Low (During Embedded Algorithms)
All Speed Options
Unit
tReady
Max
Max
20
µs
to Read Mode (See Note)
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
500
ns
tRP
tRH
RESET# Pulse Width
Min
Min
Min
500
50
ns
ns
µs
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
tRPD
20
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 16. Reset Timings
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February 12, 2004
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed Options
100,
112,
120,
JEDEC
tAVAV
Std.
tWC
tAS
Description
90R
100R
112R
120R Unit
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
90
100
110
120
ns
ns
tAVWL
0
15
45
0
Address Setup Time to OE# low during toggle bit
polling
tASO
tAH
Min
Min
Min
ns
ns
ns
tWLAX
Address Hold Time
Address Hold Time From CE# or OE# high
during toggle bit polling
tAHT
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
45
0
ns
ns
ns
Data Hold Time
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Typ
0
0
ns
ns
ns
ns
µs
µs
µs
µs
µs
CE# Hold Time
tWP
Write Pulse Width
35
30
352
11
22
8.8
tWPH
Write Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Per Byte
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word
Per Byte
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
tWHWH1
tWHWH1
Per Word
17.6
100
100
90
Byte
Single Word/Byte Program
Operation (Note 2, 5)
Typ
Typ
µs
µs
Word
Byte
Accelerated Single Word/Byte
Programming Operation (Note 2, 5)
Word
90
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
Typ
Min
Min
Min
Max
0.5
250
50
sec
ns
µs
ns
µs
tVHH
tVCS
tBUSY
tPOLL
VHH Rise and Fall Time (Note 1)
VCC Setup Time (Note 1)
WE# High to RY/BY# Low
90
100
110
120
Program Valid Before Status Polling (Note 6)
4
Notes:
1. Not 100% tested.
5. Word/Byte programming specification is based upon a single
word/byte programming operation not utilizing the write buffer.
2. See the “Erase And Programming 32-byte Performance” section
for more information.
6. When using the program suspend/resume feature, if the suspend
command is issued within tPOLL, tPOLL must be fully re-applied
upon resuming the programming operation. If the suspend
command is issued after tPOLL, tPOLL is not required again prior to
reading the status bits upon resuming.
3. For 1–16 words/ 1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/
32-byte write buffer operation.
February 12, 2004
Am29LV640MT/B
47
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tPOLL
tWP
WE#
Data
tWPH
tWHWH1
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 17. Program Operation Timings
VHH
VIL or VIH
VIL or VIH
ACC
tVHH
tVHH
Figure 18. Accelerated Program Timing Diagram
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Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.
Figure 19. Chip/Sector Erase Operation Timings
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Am29LV640MT/B
49
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
tRC
Addresses
VA
tACC
VA
VA
tPOLL
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
tOH
WE#
High Z
High Z
DQ15 and DQ7
Valid Data
Complement
Complement
True
DQ14–DQ8, DQ6–DQ0
RY/BY#
Status Data
True
Valid Data
Status Data
tBUSY
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 20. Data# Polling Timings (During Embedded Algorithms)
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February 12, 2004
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE#
tOEH
WE#
tCEPH
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
RY/BY#
Valid Data
(first read)
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 21. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 22. DQ2 vs. DQ6
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51
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Note: Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 23. Temporary Sector Group Unprotect Timing Diagram
52
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
V
ID
IH
V
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Group Protect or Unprotect
Verify
40h
Data
60h
60h
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector group protect, A6–A0 = 0xx0010. For sector group unprotect, A6–A0 = 1xx0010.
Figure 24. Sector Group Protect and Unprotect Timing Diagram
February 12, 2004
Am29LV640MT/B
53
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
100, 112, 120,
JEDEC
tAVAV
Std.
tWC
tAS
Description
90R 100R 112R 120R Unit
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
90
100
110
120
ns
ns
ns
ns
ns
tAVWL
tELAX
tDVEH
tEHDX
0
45
45
0
tAH
tDS
tDH
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Typ
0
0
ns
ns
ns
ns
µs
µs
µs
µs
µs
WE# Hold Time
CE# Pulse Width
45
30
352
11
22
8.8
tCPH
CE# Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Per Byte
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word
Per Byte
Per Word
Byte
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
tWHWH1
tWHWH1
17.6
100
100
90
Single Word/Byte Program
Operation (Note 2)
Typ
Typ
µs
µs
Word
Byte
Accelerated Single Word/Byte
Programming Operation (Note 2)
Word
90
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
Typ
Min
Max
0.5
50
sec
ns
tRH
RESET High Time Before Write (Note 1)
Program Valid Before Status Polling (Note 6)
tPOLL
4
µs
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. For 1–16 words programmed/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer.
6. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied
upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to
reading the status bits upon resuming.
54
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
OE#
tPOLL
tGHEL
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tDS
tBUSY
tDH
DQ7#,
DQ15
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings
February 12, 2004
Am29LV640MT/B
55
A D V A N C E I N F O R M A T I O N
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1) Max (Note 2)
Unit
sec
sec
µs
Comments
Sector Erase Time
Chip Erase Time
0.5
32
15
128
Byte
Word
Byte
100
100
90
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Single Word/Byte Program Time (Note 3)
µs
µs
Accelerated Single Word/Byte Program Time
(Note 3)
Word
90
µs
Total Write Buffer Program Time (Note 4)
Effective Write Buffer Program Time (Note 5)
352
11
µs
Per Byte
Per Word
µs
22
µs
Total Accelerated Effective Write Buffer
Program Time (Note 4)
282
8.8
TBD
TBD
µs
µs
Effective Accelerated Write Buffer PRogram
Time (Note 4)
Byte
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC. Programming specifications assume that
all bits are programmed to 00h.
2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000
program/erase cycles.
3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer.
4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation.
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Tables 12 and
11 for further information on command definitions.
8. The device has a minimum erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
+100 mA
V
CC Current
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN AND BGA PACKAGE CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
Typ
6
Max
7.5
5.0
12
Unit
pF
pF
pF
pF
pF
pF
TSOP
CIN
Input Capacitance
VIN = 0
VOUT = 0
VIN = 0
Fine-pitch BGA
TSOP
4.2
8.5
5.4
7.5
3.9
COUT
Output Capacitance
Fine-pitch BGA
TSOP
6.5
9
CIN2
Control Pin Capacitance
Fine-pitch BGA
4.7
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
56
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
DATA RETENTION
Parameter Description
Test Conditions
Min
10
Unit
Years
Years
150°C
125°C
Minimum Pattern Data Retention Time
20
February 12, 2004
Am29LV640MT/B
57
A D V A N C E I N F O R M A T I O N
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard Pinout Thin Small Outline Package (TSOP)
Dwg rev AA; 10/99
58
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
PHYSICAL DIMENSIONS
FBE063—63-Ball Fine-pitch Ball Grid Array (FBGA) 12 x 11 mm Package
Dwg rev AF; 10/99
February 12, 2004
Am29LV640MT/B
59
A D V A N C E I N F O R M A T I O N
PHYSICAL DIMENSIONS
LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package
60
Am29LV640MT/B
February 12, 2004
REVISION SUMMARY
Revision A (April 26, 2002)
Revision B+3 (September 19, 2002)
Initial release.
Ordering Information
Deleted FI from Valid Combinations Table.
Revision B (May 23, 2002)
Revision B+4 (October 15, 2002)
Changed packaging from 64-ball FBGA to 64-ball For-
tified BGA.
Connection Diagrams
Changed Block Diagram: Moved VIO from RY/BY# to
Input/Output Buffers.
Changed from 56-Pin Standard TSOP to 48-Pin Stan-
dard TSOP.
Changed Note about WP#/ACC pin to indicate internal
Product Selector Guide
pullup to VCC
.
Added regulated OPNs.
Revision B+1 (July 31, 2002)
Revision C (December 5, 2002)
MIRRORBIT 64 MBIT Device Family
SecSi Sector Flash Memory Region, and Enter
SecSi Sector/Exit SecSi Sector Command
Sequence
Added 64 Fortified BGA to LV640MU device.
Alternate CE# Controlled Erase and Program
Operations
Noted that the ACC function and unlock bypass modes
are not available when the SecSi sector is enabled.
Added tRH parameter to table.
Byte/Word Program Command Sequence, Sector
Erase Command Sequence, and Chip Erase Com-
mand Sequence
Erase and Program Operations
Added tBUSY parameter to table.
Noted that the SecSi Sector, autoselect, and CFI func-
tions are unavailable when a program or erase opera-
tion is in progress.
Figure 16. Program Operation Timings
Added RY/BY# to waveform.
TSOP and BGA PIN Capacitance
Common Flash Memory Interface (CFI)
Added the FBGA package.
Changed CFI website address.
Program Suspend/Program Resume Command
Sequence
Command Definitions
Changed wording in last sentence of first paragraph
from, “...resets the device to reading array data.” to
...”may place the device to an unknown state. A reset
command is then required to return the device to read-
ing array data.”
Changed 15 µs typical to maximum and added 5 µs
typical.
Erase Suspend/Erase Resume Commands
Changed typical from 20 µs to 5 µs and added a maxi-
mum of 20 µs.
CMOS Compatible
Added ILR parameter to table.
Revision B+2 (August 9, 2002)
Removed VIL, VIH, VOL, and VOH from table and added
VIL1, VIH1, VIL2, VIH2, VOL, VOH1, and VOH2 from the
CMOS table in the Am29LV640MH/L datasheet.
Valid Combinations for TSOP Package
Added 100R, 110R, and 120R OPNs.
Changed VIH1 and VIH2 minimum to 1.9.
Removed typos in notes.
Valid Combinations for BGA Package
Added 100R, 110R, and 120R OPNs.
AC Characteristics and Read-Only Operations
CMOS Compatible
Changed the Chip Enable to Output High Z and Out-
put Enable to Output High Z Speed Options from 30
ns to 16 ns.
Added Note 8.
Special package handling instructions
Modified the special handling wording.
Word/Byte Configuration
DC Characteristics table
Deleted the IACC specification row.
CFI
Changed BYTE# Switching Low to Output High Z
Speed Options from 30 ns to 16 ns.
Customer Lockable: SecSi Sector NOT
Programmed or Protected at the factory.
Changed text in the third paragraph of CFI to read
“reading array data.”
Added second bullet, SecSi sector-protect.
A D V A N C E I N F O R M A T I O N
Erase and Programming Performance
Revision C+1 (February 16, 2003)
Modified table and notes, inserted values for Typical.
Distinctive Characteristics
Revision C+3 (February 12, 2004)
Corrected performance characteristics.
Product Selector Guide
Erase Suspend/Erase Resume Commands
Added note 2.
Added note reference to erase operation.
Connection Diagrams
Table 12 & Table 13: Command Definitions
Changed pin F1 to NC.
Modified the Addr information for both Program/Erase
Suspend and Program/Erase Resume from BA to
XXX.
Ordering Information
Corrected Valid Combinations table.
AC Characteristics - Erase and Program
Operations, and Alternate CE# Controlled Erase
and Program Operations
Added Note.
AC Characteristics
Added tPOLL information.
Removed 93, 93R speed option.
AC Characteristics Figures - Program Operation
Timings, Data# Polling Timings (During Embedded
Algorithms, and Alternate CE# Controlled Write
(Erase/Program) Operation Timings
Added Note
Input values in the tWHWH1 and tWHWH2 parameters in
the Erase and Program Options table that were previ-
ously TBD. Also, added note 5.
Updated figures with tPOLL information.
Input values in the tWHWH1 and tWHWH2 parameters in
the Alternate CE# Controlled Erase and Program Op-
tions table that were previously TBD. Also, added note
5.
Erase and Programming Performance
Input values into table that were previously TBD.
Added note 3 and 4
Revision C+2 (June 12, 2003)
Ordering Information
Added 90R speed grade.
62
Am29LV640MT/B
February 12, 2004
A D V A N C E I N F O R M A T I O N
Trademarks
Copyright © 2004 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
February 12, 2004
Am29LV640MT/B
63
Representatives in U.S. and Canada
Sales Offices and Representatives
ARIZONA,
North America
Tempe - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(480)839-2320
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ILLINOIS,
Chicago . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(630)773-4422
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MICHIGAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(248)471-6294
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NEW JERSEY,
Chatham . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 97 3 ) 7 0 1 - 1 7 7 7
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PENNSYLVANIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 1 5 ) 3 4 0 - 1 1 8 7
SOUTH DAKOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(605)692-5777
TEXAS,
Golden - Compass Marketing . . . . . . . . . . . . . . . . . . . . . .(303)277-0456
FLORIDA,
Melbourne - Marathon Technical Sales . . . . . . . . . . . . . . . .(321)728-7706
Ft. Lauderdale - Marathon Technical Sales . . . . . . . . . . . . . .(954)527-4949
Orlando - Marathon Technical Sales . . . . . . . . . . . . . . . . . .(407)872-5775
St. Petersburg - Marathon Technical Sales . . . . . . . . . . . . . .(727)894-3603
GEORGIA,
Duluth - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . (678)584-1128
ILLINOIS,
Skokie - Industrial Reps, Inc. . . . . . . . . . . . . . . . . . . . . . . . .(847)967-8430
INDIANA,
Kokomo - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (765)457-7241
IOWA,
Cedar Rapids - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . (319)294-1000
KANSAS,
Lenexa - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 1 3 ) 4 69 - 1 3 1 2
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Austin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (512)346-7830
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Houston . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(281)376-8084
VIRGINIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(703)736-9568
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MICHIGAN,
Brighton - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(810)227-0007
MINNESOTA,
St. Paul - Cahill, Schmitz & Cahill, Inc. . . . . . . . . . . . . . . . . .(651)699-0200
MISSOURI,
St. Louis - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . . (314)997-4558
NEW JERSEY,
International
AUSTRALIA, North Ryde . . . . . . . . . . . . . . . . . . . . . . .TEL(61)2-88-777-222
BELGIUM,Antwerpen . . . . . . . . . . . . . . . . . . . . . . . .TEL(32)3-248-43-00
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Beijing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(86)10-6510-2188
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FINLAND, Helsinki . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 5 8 ) 8 8 1 - 3 1 1 7
FRANCE, Paris . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 3 ) - 1 - 4 975 1 0 1 0
GERMANY,
Bad Homburg . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(49)-6172-92670
Munich . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 4 9 ) - 8 9 - 4 5 0 5 3 0
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ITALY, Milan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 9 ) - 0 2 - 3 8 1 9 6 1
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JAPAN,
es
Mt. Laurel - SJ Associates . . . . . . . . . . . . . . . . . . . . . . . . .(856)866-1234
NEWYORK,
Buffalo - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 1 6 ) 74 1 - 7 1 1 6
East Syracuse - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . (315)437-8343
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Rockville Centre - SJ Associates . . . . . . . . . . . . . . . . . . . . (516)536-4242
NORTH CAROLINA,
Raleigh - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . .(919)846-5728
OHIO,
Middleburg Hts - Dolfuss Root & Co. . . . . . . . . . . . . . . . . (440)816-1660
Powell - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . . . (614)781-0725
Vandalia - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . .(937)898-9610
Westerville - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . (614)523-1990
OREGON,
Lake Oswego - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . .(503)670-0557
UTAH,
Murray - Front Range Marketing . . . . . . . . . . . . . . . . . . . .(801)288-2500
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Osaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(81)6-6243-3250
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KOREA, Seoul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(82)2-3468-2600
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SWEDEN, Stockholm . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(46)8-562-540-00
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UNITED KINGDOM,
Frimley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(44)1276-803100
Haydock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(44)1942-272888
Glen Burnie - Coherent Solution, Inc. . . . . . . . . . . . . . . . . ( 4 1 0 ) 76 1 - 2 2 5 5
WASHINGTON,
Kirkland - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . .(425)822-9220
WISCONSIN,
Pewaukee - Industrial Representatives . . . . . . . . . . . . . . . .(262)574-9393
Advanced Micro Devices reserves the right to make changes in its product without notice
in order to improve design or performance characteristics.The performance
characteristics listed in this document are guaranteed by specific tests, guard banding,
design and other practices common to the industry. For specific testing details, contact
your local AMD sales representative.The company assumes no responsibility for the use of
any circuits described herein.
Representatives in Latin America
ARGENTINA,
Capital Federal Argentina/WW Rep. . . . . . . . . . . . . . . . . . . .54-11)4373-0655
CHILE,
Santiago - LatinRep/WWRep. . . . . . . . . . . . . . . . . . . . . . . . . .(+562)264-0993
COLUMBIA,
Bogota - Dimser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 5 7 1 ) 4 1 0 - 4 1 8 2
MEXICO,
Guadalajara - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . .(523)817-3900
Mexico City - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . .(525)752-2727
Monterrey - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . .(528)369-6828
PUERTO RICO,
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Advanced Micro Devices, Inc. Other product names are for informational purposes only
and may be trademarks of their respective companies.
Boqueron - Infitronics. . . . . . . . . . . . . . . . . . . . . . . . . . . .(787)851-6000
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©2003 Advanced Micro Devices, Inc.
01/03
Printed in USA
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