AM29LV641DH121RFFN_技术文档

Am29LV640D/Am29LV641D

Data Sheet (Retired Product)

Am29LV640D/Am29LV641D Cover Sheet

This product has been retired and is not recommended for designs. For new and current designs, S29GL064N supercedes

Am29LV640D/Am29LV641D. This is the factory-recommended migration path. Please refer to the S29GL-N data sheet for

specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been

made are the result of normal data sheet improvement and are noted in the document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number 22366

Revision C

Amendment 7

Issue Date February 26, 2009

D a t a S h e e t ( R e t i r e d P r o d u c t )

This page left intentionally blank.

2

Am29LV640D/Am29LV641D

22366_C7 February 26, 2009

DATA SHEET

Am29LV640D/Am29LV641D

64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only

Uniform Sector Flash Memory with VersatileIO™ Control

This product has been retired and is not recommended for designs. For new and current designs, S29GL064N supercedes

Am29LV640D/Am29LV641D. This is the factory-recommended migration path. Please refer to the S29GL-N data sheet for spec-

ifications and ordering information. Availability of this document is retained for reference and historical purposes only.

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

— Pinout and software compatible with single-power

supply Flash

— 3.0 to 3.6 volt read, erase, and program operations

— Superior inadvertent write protection

■ VersatileIO™ control

— Device generates output voltages and tolerates data

input voltages on the DQ input/outputs as determined

by the voltage on V_IO

■ Minimum 1 million erase cycle guarantee per sector

■ Package options

— 48-pin TSOP (Am29LV641DH/DL only)

■ High performance

— 56-pin SSOP (Am29LV640DH/DL only)

— 63-ball Fine-Pitch BGA (Am29LV640DU only)

— 64-ball Fortified BGA (Am29LV640DU only)

— Access times as fast as 90 ns

■ Manufactured on 0.23 µm process technology

■ CFI (Common Flash Interface) compliant

— Provides device-specific information to the system,

allowing host software to easily reconfigure for

different Flash devices

■ Erase Suspend/Erase Resume

— Suspends an erase operation to read data from, or

program data to, a sect27

— or that is not being erased, then resumes the erase

operation

■ SecSi (Secured Silicon) Sector region

— 128-word sector for permanent, secure identification

through an 8-word random Electronic Serial Number

■ Data# Polling and toggle bits

— Provides a software method of detecting program or

— May be programmed and locked at the factory or by

the customer

erase operation completion

■ Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

— Accessible through a command sequence

■ Ultra low power consumption (typical values at 3.0 V,

5 MHz)

■ Ready/Busy# pin (RY/BY#) (Am29LV640DU in FBGA

package only)

— 9 mA typical active read current

— 26 mA typical erase/program current

— 200 nA typical standby mode current

— Provides a hardware method of detecting program or

erase cycle completion

■ Flexible sector architecture

■ Hardware reset pin (RESET#)

— One hundred twenty-eight 32 Kword sectors

— Hardware method to reset the device for reading array

data

■ Sector Protection

— A hardware method to lock a sector to prevent

■ WP# pin (Am29LV641DH/DL in TSOP,

Am29LV640DH/DL in SSOP only)

program or erase operations within that sector

— Sectors can be locked in-system or via programming

equipment

— At V_IL, protects the first or last 32 Kword sector,

regardless of sector protect/unprotect status

— Temporary Sector Unprotect feature allows code

changes in previously locked sectors

— At V_IH, allows removal of sector protection

— An internal pull up to V_CCis provided

■ Embedded Algorithms

■ ACC pin

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Accelerates programming time for higher throughput

during system production

■ Program and Erase Performance (V_HHnot applied to

the ACC input pin)

— Embedded Program algorithm automatically writes

and verifies data at specified addresses

— Word program time: 11 µs typical

■ Compatibility with JEDEC standards

— Sector erase time: 0.9 s typical for each 32 Kword

sector

Publication# 22366 Rev: C Amendment 7

Issue Date: February 26, 2009

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

D A T A S H E E T

GENERAL DESCRIPTION

The Am29LV640DU/Am29LV641DU is a 64 Mbit, 3.0

Volt (3.0 V to 3.6 V) single power supply flash memory

device organized as 4,194,304 words. Data appears

on DQ0-DQ15. The device is designed to be pro-

grammed in-system with the standard system 3.0 volt

gle) status bits. After a program or erase cycle com-

pletes, the device is ready to read array data or accept

another command.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

V

_CCsupply. A 12.0 volt V_PPis not required for program

or erase operations. You can also program this device

in standard EPROM programmers.

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of sectors of memory.

This is achieved in-system or via programming equip-

ment.

Access times of 90 and 120 ns are available for appli-

cations where V_IO≥ V_CC. An access time 120 ns are

available for applications where V_IO< V_CC. The device

is offered in 48-pin TSOP, 56-pin SSOP, 63-ball

Fine-Pitch BGA and 64-ball Fortified BGA packages.

To eliminate bus contention, each device has separate

chip enable (CE#), write enable (WE#), and output en-

able (OE#) controls.

The Erase Suspend/Erase Resume feature enables

the user to put erase on hold for any period of time to

read data from, or program data to, any sector that is

not selected for erasure. True background erase can

thus be achieved.

Each device requires only a single 3.0 Volt power

supply (3.0 V to 3.6 V) for both read and write func-

tions. Internally generated and regulated voltages are

provided for the program and erase operations.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin can be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read boot-up firmware from the Flash memory de-

vice.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timing. Register con-

tents serve as inputs to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data

needed for the programming and erase operations.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

The device offers a standby mode as a power-saving

feature. Once the system places the device into the

standby mode, power consumption is greatly reduced.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm — an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

The SecSi (Secured Silicon) Sector provides an

minimum 128-word area for code or data that can be

permanently protected. Once this sector is protected,

no further programming or erasing within the sector

can occur.

The Write Protect (WP#) feature protects the first or

last sector by asserting a logic low on the WP# pin.

The protected sector is still protected even during ac-

celerated programming.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm — an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase,

the device automatically times the erase pulse widths

and verifies proper cell margin.

The accelerated program (ACC) feature allows the

system to program the device at a much faster rate.

When ACC is pulled high to V_HH, the device enters the

Unlock Bypass mode, enabling the user to reduce the

time needed to do the program operation. This feature

is intended to increase factory throughput during sys-

tem production, but may also be used in the field if de-

sired.

The VersatileIO™ (V_IO) control allows the host system

to set the voltage levels that the device generates and

tolerates on CE# and DQ I/Os to the same voltage

level that is asserted on V_IO. V_IOis available in two

configurations (1.8–2.9 V and 3.0–5.0 V) for operation

in various system environments.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunnelling.

The data is programmed using hot electron injection.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-

2

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Special Handling Instructions for FBGA/fBGA Packages ......... 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations .....................................................10

VersatileIO™ (V_IO) Control ..................................................... 10

Requirements for Reading Array Data ................................... 10

Writing Commands/Command Sequences ............................ 11

Accelerated Program Operation ......................................................11

Autoselect Functions .......................................................................11

Standby Mode ........................................................................ 11

Automatic Sleep Mode ........................................................... 11

RESET#: Hardware Reset Pin ............................................... 11

Output Disable Mode .............................................................. 12

Table 2. Sector Address Table ........................................................12

Autoselect Mode ..................................................................... 16

Table 3. Autoselect Codes, (High Voltage Method) .......................16

Sector Group Protection and Unprotection ............................. 17

Table 4. Sector Group Protection/Unprotection Address Table .....17

Write Protect (WP#) ................................................................ 18

Temporary Sector Group Unprotect ....................................... 18

Figure 1. Temporary Sector Group Unprotect Operation................ 18

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 19

SecSi (Secured Silicon) Sector Flash Memory Region .......... 20

Table 5. SecSi Sector Contents ......................................................20

Hardware Data Protection ...................................................... 20

Low VCC Write Inhibit .....................................................................20

Write Pulse “Glitch” Protection ........................................................21

Logical Inhibit ..................................................................................21

Power-Up Write Inhibit ....................................................................21

Common Flash Memory Interface (CFI). . . . . . . 21

Table 6. CFI Query Identification String.......................................... 21

System Interface String................................................................... 22

Table 8. Device Geometry Definition .............................................. 22

Table 9. Primary Vendor-Specific Extended Query ........................ 23

Command Definitions . . . . . . . . . . . . . . . . . . . . . 23

Reading Array Data ................................................................ 23

Reset Command ..................................................................... 24

Autoselect Command Sequence ............................................ 24

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 24

Word Program Command Sequence ..................................... 24

Unlock Bypass Command Sequence ..............................................25

Figure 3. Program Operation .......................................................... 25

Chip Erase Command Sequence ........................................... 25

Sector Erase Command Sequence ........................................ 26

Erase Suspend/Erase Resume Commands ........................... 26

Figure 4. Erase Operation............................................................... 27

Command Definitions ............................................................. 28

Command Definitions...................................................................... 28

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 29

DQ7: Data# Polling ................................................................. 29

Figure 5. Data# Polling Algorithm ................................................... 29

RY/BY#: Ready/Busy# ............................................................ 30

DQ6: Toggle Bit I .................................................................... 30

Figure 6. Toggle Bit Algorithm........................................................ 30

DQ2: Toggle Bit II ................................................................... 31

Reading Toggle Bits DQ6/DQ2 ............................................... 31

DQ5: Exceeded Timing Limits ................................................ 31

DQ3: Sector Erase Timer ....................................................... 31

Table 11. Write Operation Status ................................................... 32

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33

Figure 7. Maximum Negative Overshoot Waveform ..................... 33

Figure 8. Maximum Positive Overshoot Waveform....................... 33

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 33

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 9. I_CC1Current vs. Time (Showing

Active and Automatic Sleep Currents) ........................................... 35

Figure 10. Typical I_CC1vs. Frequency............................................ 35

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 11. Test Setup.................................................................... 36

Table 12. Test Specifications ......................................................... 36

Key to Switching Waveforms. . . . . . . . . . . . . . . . 36

Figure 12. Input Waveforms and

Measurement Levels...................................................................... 36

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37

Read-Only Operations ........................................................... 37

Figure 13. Read Operation Timings............................................... 37

Hardware Reset (RESET#) .................................................... 38

Figure 14. Reset Timings............................................................... 38

Erase and Program Operations .............................................. 39

Figure 15. Program Operation Timings.......................................... 40

Figure 16. Accelerated Program Timing Diagram.......................... 40

Figure 17. Chip/Sector Erase Operation Timings .......................... 41

Figure 18. Data# Polling Timings

(During Embedded Algorithms)...................................................... 42

Figure 19. Toggle Bit Timings

(During Embedded Algorithms)...................................................... 43

Figure 20. DQ2 vs. DQ6................................................................. 43

Temporary Sector Unprotect .................................................. 44

Figure 21. Temporary Sector Group Unprotect Timing Diagram ... 44

Figure 22. Sector Group Protect and Unprotect Timing Diagram .. 45

Alternate CE# Controlled Erase and Program Operations ..... 46

Figure 23. Alternate CE# Controlled Write

(Erase/Program) Operation Timings .............................................. 47

Erase And Programming Performance . . . . . . . 48

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 48

TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 48

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 49

SSO056—56-Pin Shrink Small Outline Package (SSOP) ...... 49

FBE063—63-Ball Fine-Pitch Ball Grid Array

(FBGA) 12 x 11 mm package ................................................. 50

LAA064—64-Ball Fortified Ball Grid Array

(FBGA) 13 x 11 mm package ................................................. 51

TS 048—48-Pin Standard TSOP ............................................ 52

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

3

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Part Number

Am29LV640D/Am29LV641D

V_CC= 3.0–3.6 V, V_IO= 3.0–5.0 V

V_CC= 3.0–3.6 V, V_IO= 1.8–2.9 V

90R

120R

121R

120

Speed Option

Max Access Time (ns)

CE# Access Time (ns)

OE# Access Time (ns)

90

35

120

50

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ15

RY/BY# (Note 1)

V_CC

Sector Switches

V_SS

V_IO

Erase Voltage

Generator

Input/Output

Buffers

RESET#

WE#

State

WP#

Control

(Note 2)

Command

Register

ACC

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

X-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

A0–A21

Notes:

1. RY/BY# is only available in the FBGA package.

2. WP# is only available in the TSOP and SSOP packages.

4

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

V_IO

V_SS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

A8

48-Pin Standard TSOP

(Am29LV641DH/DL only)

A21

A20

WE#

RESET#

ACC

WP#

A19

A18

A17

A7

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A6

A5

A4

A3

A2

A1

OE#

V_SS

CE#

A0

ACC

WP#

A19

A18

A17

A7

1

2

3

4

5

6

7

8

9

56 RESET#

55 WE#

54 A20

53 A21

52 A8

51 A9

A6

50 A10

49 A11

48 A12

47 A13

46 A14

45 A15

44 NC

A5

A4

A3 10

A2 11

A1 12

56-Pin SSOP

(Am29LV640DH/DL

only)

NC 13

NC 14

43 NC

NC 15

42 NC

NC 16

41 NC

A0 17

40 A16

39 V_IO

CE# 18

V_SS19

OE# 20

DQ0 21

DQ8 22

DQ1 23

DQ9 24

DQ2 25

DQ10 26

DQ3 27

DQ11 28

38 V_SS

37 DQ15

36 DQ7

35 DQ14

34 DQ6

33 DQ13

32 DQ5

31 DQ12

30 DQ4

29 V_CC

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

5

D A T A S H E E T

CONNECTION DIAGRAM

63-Ball Fine-Pitch BGA (FBGA)

Top View, Balls Facing Down

(Am29LV640DU only)

L8

M8

A8

B8

NC

NC*

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

V_SS

NC

NC*

A13

A12

A14

A15

A16

V_IO

DQ15

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

V_CC

WE# RESET#

A21

A19

DQ5

DQ12

DQ4

C4

D4

E4

F4

G4

H4

J4

K4

RY/BY#

ACC

A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

L2

M2

A2

V_SS

CE#

OE#

NC*

A1

B1

L1

M1

* Balls are shorted together via the substrate but not connected to the die.

NC*

6

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

CONNECTION DIAGRAMS

64-Ball Fortified BGA (FBGA)

Top View, Balls Facing Down

(Am29LV640DU only)

A8

B8

C8

D8

E8

F8

G8

H8

RFU

V_IO

V_SS

RFU

A7

B7

C7

D7

E7

F7

G7

H7

A13

A12

A14

A15

A16

NC

DQ15

V_SS

A6

A9

B6

A8

C6

D6

E6

F6

G6

H6

DQ6

A10

A11

DQ7

DQ14

DQ13

A5

B5

C5

D5

E5

F5

G5

H5

WE# RESET#

A21

A19

DQ5

DQ12

V_CC

DQ4

A4

B4

C4

D4

E4

F4

G4

H4

RY/BY#

ACC

A18

A20

DQ2

DQ10

DQ11

DQ3

A3

A7

B3

C3

A6

D3

A5

E3

F3

G3

H3

A17

DQ0

DQ8

DQ9

DQ1

A2

A3

B2

A4

C2

A2

D2

A1

E2

A0

F2

G2

H2

CE#

OE#

V_SS

A1

B1

C1

D1

E1

F1

G1

H1

RFU

V_IO

RFU

Flash memory devices in BGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be compromised

if the package body is exposed to temperatures above

150°C for prolonged periods of time.

Special Handling Instructions for

FBGA/fBGA Packages

Special handling is required for Flash Memory products

in BGA packages.

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

7

D A T A S H E E T

PIN DESCRIPTION

LOGIC SYMBOL

A0–A21

= 22 Addresses inputs

22

DQ0–DQ15 = 16 Data inputs/outputs

A0–A21

16

CE#

OE#

WE#

WP#

= Chip Enable input

= Output Enable input

= Write Enable input

DQ0–DQ15

CE#

OE#

WE#

WP#

ACC

RESET#

V_IO

= Hardware Write Protect input (N/A on

FBGA)

ACC

= Acceleration Input

RESET#

RY/BY#

V_CC

= Hardware Reset Pin input

= Ready/Busy output (FBGA only)

RY/BY#

= 3.0 volt-only single power supply

(see Product Selector Guide for

speed options and voltage

supply tolerances)

Note: WP# is not available on the FBGA package. RY/BY#

is not available on the TSOP and SSOP packages.

V_IO

= Output Buffer power

= Device Ground

V_SS

NC

= Pin Not Connected Internally

= Reserved for Future Use

RFU

8

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29LV640D

Am29LV641D

H

90R

E

I

N

OPTIONAL PROCESSING

Blank = Standard Processing

N

=

32-byte ESN devices

(Contact an AMD representative for more information)

TEMPERATURE RANGE

I

F

=

Industrial (–40°C to +85°C)

Industrial (–40°C to +85°C) with Pb-Free Package

PACKAGE TYPE

E

Z

PC

=

48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)

56-Pin Shrink Small Outline Package (SSO056)

64-Ball Fortified Ball Grid Array

1.0 mm pitch, 13 x 11 mm package (LAA064)

63-Ball Fine-Pitch Ball Grid Array

WH

=

0.80 mm pitch, 11 x 12 mm package (FBE063)

SPEED OPTION

See Product Selector Guide and Valid Combinations

SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = 0)

H

L

U

=

Uniform sector device, highest address sector protected

Uniform sector device, lowest address sector protected

Uniform sector device (WP# not available)

DEVICE NUMBER/DESCRIPTION

Am29LV640DU/DH/DL, Am29LV641DH/DL

64 Megabit (4 M x 16-Bit) CMOS Uniform Sector Flash Memory with VersatileIO™ Control

3.0 Volt-only Read, Program, and Erase

Valid Combinations for

TSOP and SSOP Packages

Valid Combinations for BGA Packages

Order Number Package Marking

Speed/

V_IORange

Speed/V_IORange

AM29LV640DH90R,

PCI,

PCF

WHI,

WHF

PCI,

PCF

WHI,

WHF

PCI,

PCF

WHI,

WHF

ZI, ZF

EI, FI, EF

ZI, ZF

L640DU90N

L640DU90R

L640DU12N

L640DU12R

L640DU21N

L640DU21R

AM29LV640DL90R

AM29LV641DH90R,

AM29LV641DL90R

AM29LV640DH120R,

AM29LV640DL120R

AM29LV641DH120R,

AM29LV641DL120R

AM29LV640DH121R,

AM29LV640DL121R

AM29LV641DH121R,

AM29LV641DL121R

90 ns,

_IO= 3.0 V – 5.0 V

90 ns, V_IO

3.0 V – 5.0 V

=

AM29LV640DU90R

I, F

V

120 ns,

_IO= 3.0 V – 5.0 V

120 ns, V_IO

=

AM29LV640DU120R

AM29LV640DU121R

3.0 V – 5.0 V

EI, FI, EF

ZI, ZF

I, F

120 ns,

_IO= 1.8 V – 2.9 V

120 ns, V_IO

=

1.8 V – 2.9 V

EI, FI, EF

Note: LV640/641DH & DL have WP#, but no RY/BY#. U designator

in base part number replaced by H or L.

Note: LV640DU has RY/BY#, but no WP#.

Note: Reverse pinout TSOP (TSR048) packages are not Note: offered

for new designs. For 128 Mb requirements, the S29GL128N product is

recommended as a single-device substitute for the 64 Mb + 64 Mb

clamshell design; please refer to the S29GL128N data sheet for

specifications and ordering information.

Valid Combinations

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult the local AMD sales office to confirm

availability of specific valid combinations and to check on newly re-

leased combinations.

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

9

D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each oper-

ation in further detail.

Table 1. Device Bus Operations

Addresses

(Note 2)

DQ0–

DQ15

Operation

CE# OE# WE# RESET#

WP#

X

ACC

X

Read

L

H

L

H

A_IN

D_OUT

Write (Program/Erase)

Accelerated Program

(Note 3)

X

(Note 4)

L

H

V_HH

V_CC

0.3 V

±

V_CC±

0.3 V

Standby

X

H

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z

X

SA, A6 = L,

A1 = H, A0 = L

Sector Group Protect (Note 2)

L

H

X

L

X

V_ID

H

X

(Note 4)

Sector Group Unprotect

(Note 2)

SA, A6 = H,

A1 = H, A0 = L

Temporary Sector Group

Unprotect

X

A_IN

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 8.5–12.5 V, V_HH= 11.5–12.5 V, X = Don’t Care, SA = Sector Address,

A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A21:A0. Sector addresses are A21:A15.

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

3. If WP# = V_IL, the first or last sector remains protected. If WP# = V_IH, the first or last sector is protected or unprotected as

determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped

from the factory (The SecSi Sector may be factory protected depending on version ordered.)

4. D_INor D_OUTas required by command sequence, data polling, or sector protect algorithm (see Figure 2, on page 20).

VersatileIO™ (V_IO) Control

Requirements for Reading Array Data

The VersatileIO™ (V_IO) control allows the host system

to set the voltage levels that the device generates and

tolerates on CE# and DQ I/Os to the same voltage

level that is asserted on V_IO. V_IOis available in two

configurations (1.8–2.9 V and 3.0–5.0 V) for operation

in various system environments.

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V_IH.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

For example, a V_IOof 4.5–5.0 volts allows for I/O at the

5 volt level, driving and receiving signals to and from

other 5 V devices on the same data bus.

10

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

and “Autoselect Command Sequence” on page 25 for

more information.

Standby Mode

See “Requirements for Reading Array Data” on

page 11 for more information. Refer to the AC

“Read-Only Operations” on page 38 table for timing

specifications and to Figure 13, on page 38 for the tim-

ing diagram. I_CC1in the “DC Characteristics” on

page 35 table represents the active current specifica-

tion for reading array data.

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_CC0.3 V, the device is in the standby mode, but the

standby current is greater. The device requires stan-

dard access time (t_CE) for read access when the de-

vice is in either of these standby modes before it is

ready to read data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word instead of four. The “Word

Program Command Sequence” on page 25 has de-

tails on programming data to the device using both

standard and Unlock Bypass command sequences.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

I

_CC3in the table “DC Characteristics” on page 35 rep-

resents the standby current specification.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 on page 13 indicates

the address space that each sector occupies.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

I_CC2in the DC Characteristics table represents the ac-

this mode when addresses remain stable for t_ACC

+

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This function is primarily in-

tended to allow faster manufacturing throughput dur-

ing system production.

I

_CC4in the table “DC Characteristics” on page 35 rep-

resents the automatic sleep mode current specifica-

tion.

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. To ensure data integrity,

the operation that was interrupted should be reinitiated

once the device is ready to accept another command

sequence.

V

_HHfrom the ACC pin returns the device to normal op-

eration. Note that the ACC pin must not be at V_HHfor

operations other than accelerated programming, or

device damage may result.

Autoselect Functions

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS0.3 V, the standby current is

greater.

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the “Autoselect Mode” on page 17

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

11

D A T A S H E E T

The RESET# pin can be tied to the system reset cir-

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

Refer to the table “AC Characteristics” on page 38 for

RESET# parameters and to Figure 14, on page 39 for

the timing diagram.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Table 2. Sector Address Table (Sheet 1 of 4)

16-bit Address Range

(in hexadecimal)

Sector

SA0

A21

0

A20

0

A19

0

1

A18

0

1

0

1

A17

0

1

0

1

0

1

0

A16

0

1

0

1

0

1

0

1

0

1

0

1

0

A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

000000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

12

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

Table 2. Sector Address Table (Sheet 2 of 4)

16-bit Address Range

(in hexadecimal)

Sector

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

A21

0

A20

0

1

A19

1

0

1

A18

1

0

1

0

1

A17

0

1

0

1

0

1

0

1

0

1

A16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FFFFF

100000–107FFF

108000–10FFFF

110000–117FFF

118000–11FFFF

120000–127FFF

128000–12FFFF

130000–137FFF

138000–13FFFF

140000–147FFF

148000–14FFFF

150000–157FFF

158000–15FFFF

160000–167FFF

168000–16FFFF

170000–177FFF

178000–17FFFF

180000–187FFF

188000–18FFFF

190000–197FFF

198000–19FFFF

1A0000–1A7FFF

1A8000–1AFFFF

1B0000–1B7FFF

1B8000–1BFFFF

1C0000–1C7FFF

1C8000–1CFFFF

1D0000–1D7FFF

1D8000–1DFFFF

1E0000–1E7FFF

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

13

D A T A S H E E T

Table 2. Sector Address Table (Sheet 3 of 4)

16-bit Address Range

(in hexadecimal)

Sector

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

A21

0

1

A20

1

0

A19

1

0

1

A18

1

0

1

0

1

A17

1

0

1

0

1

0

1

0

1

A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1E8000–1EFFFF

1F0000–1F7FFF

1F8000–1FFFFF

200000–207FFF

208000–20FFFF

210000–217FFF

218000–21FFFF

220000–227FFF

228000–22FFFF

230000–237FFF

238000–23FFFF

240000–247FFF

248000–24FFFF

250000–257FFF

258000–25FFFF

260000–267FFF

268000–26FFFF

270000–277FFF

278000–27FFFF

280000–287FFF

288000–28FFFF

290000–297FFF

298000–29FFFF

2A0000–2A7FFF

2A8000–2AFFFF

2B0000–2B7FFF

2B8000–2BFFFF

2C0000–2C7FFF

2C8000–2CFFFF

2D0000–2D7FFF

2D8000–2DFFFF

2E0000–2E7FFF

2E8000–2EFFFF

2F0000–2F7FFF

2F8000–2FFFFF

14

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

Table 2. Sector Address Table (Sheet 4 of 4)

16-bit Address Range

(in hexadecimal)

Sector

SA96

A21

1

A20

1

A19

0

1

A18

0

1

0

1

A17

0

1

0

1

0

1

0

1

A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

300000–307FFF

308000–30FFFF

310000–317FFF

318000–31FFFF

320000–327FFF

328000–32FFFF

330000–337FFF

338000–33FFFF

340000–347FFF

348000–34FFFF

350000–357FFF

358000–35FFFF

360000–367FFF

368000–36FFFF

370000–377FFF

378000–37FFFF

380000–387FFF

388000–38FFFF

390000–397FFF

398000–39FFFF

3A0000–3A7FFF

3A8000–3AFFFF

3B0000–3B7FFF

3B8000–3BFFFF

3C0000–3C7FFF

3C8000–3CFFFF

3D0000–3D7FFF

3D8000–3DFFFF

3E0000–3E7FFF

3E8000–3EFFFF

3F0000–3F7FFF

3F8000–3FFFFF

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

Note: All sectors are 32 Kwords in size.

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

15

D A T A S H E E T

the sector address must appear on the appropriate

Autoselect Mode

highest order address bits (see Table 2 on page 13).

Table 3 shows the remaining address bits that are

don’t care. When all necessary bits are set as re-

quired, the programming equipment may then read the

corresponding identifier code on DQ7–DQ0.

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be pro-

grammed with its corresponding programming

algorithm. However, the autoselect codes can also be

accessed in-system through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 10 on page 29.

This method does not require V_ID. Refer to “Autoselect

Command Sequence” on page 25 for more informa-

tion.

When using programming equipment, the autoselect

mode requires V_ID(8.5 V to 12.5 V) on address pin A9.

Address pins A6, A1, and A0 must be as shown in

Table 3. In addition, when verifying sector protection,

Table 3. Autoselect Codes, (High Voltage Method)

A21

to

A14

to

A8

to

A5

to

Description

CE# OE# WE# A15

A10 A9 A7 A6 A2 A1 A0

DQ15 to DQ0

Manufacturer ID: AMD

L

H

X

V_ID

X

L

X

L

0001h

Device ID: LV640DU/H/L,

LV641DH/L

H

22D7h

Sector Protection

Verification

XX01h (protected),

XX00h (unprotected)

L

H

SA

X

V_ID

X

L

X

H

L

SecSi Sector Indicator Bit

(DQ7), WP# protects

highest address sector

(LV640DH/641DH), or

no WP# (LV640DU)

XX98h (factory locked),

XX18h (not factory locked)

V_ID

H

SecSi Sector Indicator Bit

(DQ7), WP# protects

lowest address sector

(LV640DL/641DL)

XX88h (factory locked),

XX08h (not factory locked)

L

H

X

V_ID

X

L

X

H

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.

16

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

Table 4. Sector Group Protection/Unprotection

Address Table

Sector Group Protection and

Unprotection

Sector Group

A21–A17

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

The hardware sector group protection feature disables

both program and erase operations in any sector

group. In this device, a sector group consists of four

adjacent sectors that are protected or unprotected at

the same time (see Table 4). The hardware sector

group unprotection feature re-enables both program

and erase operations in previously protected sector

groups. Sector group protection/unprotection is imple-

mented via two methods.

SA0–SA3

SA4–SA7

SA8–SA11

SA12–SA15

SA16–SA19

SA20–SA23

SA24–SA27

SA28–SA31

SA32–SA35

SA36–SA39

SA40–SA43

SA44–SA47

SA48–SA51

SA52–SA55

SA56–SA59

SA60–SA63

SA64–SA67

SA68–SA71

SA72–SA75

SA76–SA79

SA80–SA83

SA84–SA87

SA88–SA91

SA92–SA95

SA96–SA99

SA100–SA103

SA104–SA107

SA108–SA111

SA112–SA115

SA116–SA119

SA120–SA123

SA124–SA127

Sector protection/unprotection requires V_IDon the RE-

SET# pin only, and can be implemented either in-sys-

tem or via programming equipment. Figure 2, on page

20 shows the algorithms and Figure 22, on page 46

shows the timing diagram. This method uses standard

microprocessor bus cycle timing. For sector group un-

protect, all unprotected sector groups must first be

protected prior to the first sector group unprotect write

cycle.

The device is shipped with all sector groups unpro-

tected. AMD offers the option of programming and pro-

tecting sector groups at its factory prior to shipping the

device through AMD’s ExpressFlash™ Service. Con-

tact an AMD representative for details.

It is possible to determine whether a sector group is

protected or unprotected. See “Autoselect Mode” on

page 17 for details.

Note: All sector groups are 128 Kwords in size.

that if WP# is at V_ILwhen the device is in the standby

mode, the maximum input load current is increased.

See the table in “DC Characteristics” on page 35.

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting the first or last sector without

using V_ID.

If the system asserts V_IHon the WP# pin, the device

reverts to whether the first or last sector was previ-

ously set to be protected or unprotected using the

method described in “Sector Group Protection and

Unprotection” on page 18.

If the system asserts V_ILon the WP# pin, the device

disables program and erase functions in the first or last

sector independently of whether those sectors were

protected or unprotected using the method described

in “Sector Group Protection and Unprotection”. Note

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

17

D A T A S H E E T

Temporary Sector Group Unprotect

(Note: In this device, a sector group consists of four adjacent

sectors that are protected or unprotected at the same time

(see Table 4 on page 18)).

START

This feature allows temporary unprotection of previ-

ously protected sector groups to change data in-sys-

tem. The Sector Group Unprotect mode is activated by

setting the RESET# pin to V_ID(8.5 V – 12.5 V). During

this mode, formerly protected sector groups can be

programmed or erased by selecting the sector group

addresses. Once V_IDis removed from the RESET#

pin, all the previously protected sector groups are

protected again. Figure 1, on page 19 shows the algo-

rithm, and Figure 21, on page 45 shows the timing dia-

grams, for this feature.

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Group Unprotect

Completed (Note 2)

Notes:

1. All protected sector groups unprotected (If WP# = V_IL,

the first or last sector remains protected).

2. All previously protected sector groups are protected

once again.

Figure 1. Temporary Sector Group

Unprotect Operation

18

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

START

PLSCNT = 1

RESET# = V_ID

Protect all sector

groups: The indicated

portion of the sector

group protect algorithm

must be performed for all

unprotected sector

groups prior to issuing

the first sector group

unprotect address

RESET# = V_ID

Wait 1 μs

Temporary Sector

Group Unprotect

Mode

Temporary Sector

Group Unprotect

Mode

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Yes

Set up sector

group address

All sector

groups

No

protected?

Sector Group Protect:

Write 60h to sector

group address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

group address

Sector Group

Unprotect:

Wait 150 µs

Write 60h to sector

group address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector Group

Protect: Write 40h

to sector group

address twith A6 = 0,

A1 = 1, A0 = 0

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

Verify Sector Group

Unprotect: Write

40h to sector group

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector group address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector group

address with A6 = 1,

A1 = 1, A0 = 0

Data = 01h?

Yes

No

Yes

Set up

next sector group

address

Protect

another

sector group?

Yes

No

PLSCNT

= 1000?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

Last sector

group

verified?

No

Device failed

Write reset

command

Yes

Remove V_ID

from RESET#

Sector Group

Unprotect

Sector Group

Protect

Sector Group

Protect complete

Write reset

command

Algorithm

Sector Group

Unprotect complete

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

19

D A T A S H E E T

SecSi Sector permanently locked. Contact an AMD

SecSi (Secured Silicon) Sector Flash

Memory Region

representative for details on using AMD’s Express-

Flash service.

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 128 words in length, and

uses a SecSi Sector Indicator Bit (DQ7) to indicate

whether or not the SecSi Sector is locked when

shipped from the factory. This bit is permanently set at

the factory and cannot be changed, which prevents

cloning of a factory locked part. This ensures the secu-

rity of the ESN once the product is shipped to the field.

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

As an alternative to the factory-locked version, the de-

vice can be ordered such that the customer may pro-

gram and protect the 128-word SecSi sector.

Programming and protecting the SecSi Sector must be

used with caution since, once protected, there is no

procedure available for unprotecting the SecSi Sector

area and none of the bits in the SecSi Sector memory

space can be modified in any way.

AMD offers the device with the SecSi Sector either

factory locked or customer lockable. The fac-

tory-locked version is always protected when shipped

from the factory, and has the SecSi (Secured Silicon)

Sector Indicator Bit permanently set to a “1.” The cus-

tomer-lockable version is shipped with the SecSi Sec-

tor unprotected, allowing customers to utilize that

sector in any manner they choose. The customer-lock-

able version also has the SecSi Sector Indicator Bit

permanently set to a “0.” Thus, the SecSi Sector Indi-

cator Bit prevents customer-lockable devices from

being used to replace devices that are factory locked.

You can protect the SecSi Sector area using one of the

following procedures:

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, on

page 20, except that RESET# may be at either V_IH

or V_ID. This allows in-system protection of the SecSi

Sector without raising any device pin to a high volt-

age. Note that this method is only applicable to the

SecSi Sector.

■ Write the three-cycle Enter SecSi Sector Region

command sequence, then use the alternate method

of sector protection described in the “Sector Group

Protection and Unprotection” on page 18.

The SecSi sector address space in this device is allo-

cated as shown in Table 5:

Table 5. SecSi Sector Contents

SecSi Sector

Address Range

Standard

Factory Locked Factory Locked

ExpressFlash

Customer

Lockable

Once the SecSi Sector is programmed, locked, and

verified, the system must write the Exit SecSi Sector

Region command sequence to return to reading and

writing within the remainder of the array.

ESN or

determined by

customer

000000h–000007h

000008h–00007Fh

ESN

Determined by

customer

Determined by

customer

Unavailable

Hardware Data Protection

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi Sector/Exit

SecSi Sector Command Sequence” on page 25). After

the system writes the Enter SecSi Sector command

sequence, it may read the SecSi Sector by using the

addresses normally occupied by the first sector (SA0).

This mode of operation continues until the system is-

sues the Exit SecSi Sector command sequence, or

until power is removed from the device. On power-up,

or following a hardware reset, the device reverts to

sending commands to sector SA0.

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 10 on

page 29 for command definitions). In addition, the fol-

lowing hardware data protection measures prevent ac-

cidental erasure or programming, which might

otherwise be caused by spurious system level signals

during V_CCpower-up and power-down transitions, or

from system noise.

Low V_CCWrite Inhibit

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V_CCis greater than V_LKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when V_CCis

In devices with an ESN, the SecSi Sector is protected

when the device is shipped from the factory. The SecSi

Sector cannot be modified in any way. A factory locked

device has an 8-word random ESN at addresses

000000h–000007h.

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service. The de-

vices are then shipped from AMD’s factory with the

greater than V_LKO

.

20

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

CE# and WE# must be a logical zero while OE# is a

Write Pulse “Glitch” Protection

logical one.

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE#, do not initiate a write cycle.

Power-Up Write Inhibit

Logical Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward-and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

terminate reading CFI data, the system must write the

reset command.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Table 6 on page 22

to Table 9 on page 24 The system must write the reset

command to return the device to the autoselect mode.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/products/nvd/over-

view/cfi.html. Alternatively, contact an AMD represen-

tative for copies of these documents.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h, any time the device is ready to read array data.

The system reads CFI information at the addresses

given in Table 6 on page 22 to Table 9 on page 24. To

Table 6. CFI Query Identification String

Description

Addresses (x16)

Data

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

Primary OEM Command Set

13h

14h

0002h

0000h

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

0000h

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

21

D A T A S H E E T

Table 7. System Interface String

Addresses (x16)

Data

Description

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

0027h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0036h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V

_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 8. Device Geometry Definition

Description

Addresses (x16)

Data

27h

0017h

Device Size = 2^Nbyte

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ch

0001h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

007Fh

0000h

0001h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

0000h

Erase Block Region 2 Information (refer to CFI publication 100)

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

35h

36h

37h

38h

0000h

39h

3Ah

3Bh

3Ch

0000h

22

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

Table 9. Primary Vendor-Specific Extended Query

Addresses (x16)

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

00b = Required, 01b = Not Required

45h

0000h

Silicon Revision Number (Bits 7-2) 000000b = 0.23 µm Process Technology

Erase Suspend

46h

47h

48h

49h

4Ah

4Bh

4Ch

0002h

0004h

0001h

0004h

0000h

00 = Not Supported, 01 = To Read Only, 02 = To Read & Write

Sector Protect

00 = Not Supported, X = Number of sectors per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

04 = 29LV800A mode

Simultaneous Operation

00 = Not Supported, XX = Number of Sectors in Bank

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

00B5h

00C5h

Bits 7–4 = Hex Value in Volts, Bits 0–3 = BCD Value in 100 mV

ACC (Acceleration) Supply Maximum

Bits 7–4 = Hex Value in Volts, Bits 0–3 = BCD Value in 100 mV

Top/Bottom Boot Sector Flag

00h = Uniform Sector, No WP# Control

04h = Uniform Sector, WP# Protects Bottom Sector

05h = Uniform Sector, WP# Protects Top Sector

4Fh

000Xh

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 10 on page 29 defines the valid

register command sequences. Writing incorrect ad-

dress and data values or writing them in the im-

proper sequence, resets the device to reading array

data.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the erase-suspend-read mode, after

which the system can read data from any

non-erase-suspended sector. After completing a pro-

gramming operation in the Erase Suspend mode, the

system may once again read array data with the same

exception. See “Erase Suspend/Erase Resume Com-

mands” on page 27, for more information.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to “AC Characteristics” on page 38 for tim-

ing diagrams.

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

23

D A T A S H E E T

The system must issue the reset command to return

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the autoselect command. The

device then enters the autoselect mode. The system

may read at any address any number of times without

initiating another autoselect command sequence:

the device to the read (or erase-suspend-read) mode if

DQ5 goes high during an active program or erase op-

eration, or if the device is in the autoselect mode. See

the next section, Reset Command, for more informa-

tion.

See also “Requirements for Reading Array Data” on

page 11 in the Device Bus Operations section for

more information. The “Read-Only Operations” on

page 38 table provides the read parameters, and Fig-

ure 13, on page 38 shows the timing diagram.

■ A read cycle at address XX00h returns the manu-

facturer code.

■ A read cycle at address XX01h returns the device

code.

■ A read cycle to an address containing a sector

group address (SA), and the address 02h on A7–A0

returns 01h if the sector group is protected, or 00h

if it is unprotected. (Refer to Table 4 on page 18 for

valid sector addresses).

Reset Command

Writing the reset command resets the device to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the de-

vice was previously in Erase Suspend).

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to the read

mode. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

Enter SecSi Sector/Exit SecSi Sector

Command Sequence

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device to

the read mode. If the program command sequence is

written while the device is in the Erase Suspend mode,

writing the reset command returns the device to the

erase-suspend-read mode. Once programming be-

gins, however, the device ignores reset commands

until the operation is complete.

The SecSi Sector region provides a secured data area

containing an 8-word random Electronic Serial Num-

ber (ESN). The system can access the SecSi Sector

region by issuing the three-cycle Enter SecSi Sector

command sequence. The device continues to access

the SecSi Sector region until the system issues the

four-cycle Exit SecSi Sector command sequence. The

Exit SecSi Sector command sequence returns the de-

vice to normal operation. Table 10 on page 29 shows

the address and data requirements for both command

sequences. See also “SecSi (Secured Silicon) Sector

Flash Memory Region” on page 21 for further informa-

tion.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If the de-

vice entered the autoselect mode while in the Erase

Suspend mode, writing the reset command returns the

device to the erase-suspend-read mode.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. The “Command Definitions”

on page 29 shows the address and data requirements

for the word program command sequence.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to the

read mode (or erase-suspend-read mode if the device

was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

Table 10 on page 29 shows the address and data re-

quirements. This method is an alternative to that

shown in Table 3 on page 17, which is intended for

PROM programmers and requires V_IDon address pin

A9. The autoselect command sequence may be writ-

ten to an address that is either in the read or

erase-suspend-read mode. The autoselect command

cannot be written while the device is actively program-

ming or erasing.

When the Embedded Program algorithm is complete,

the device returns to the read mode and addresses

are no longer latched. The system determines the sta-

tus of the program operation by using DQ7, DQ6, or

RY/BY#. Refer to “Write Operation Status” on page 30

for information on these status bits.

24

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

Any commands written to the device during the Em-

page 40 table in the AC Characteristics section for pa-

rameters, and Figure 15, on page 41 for timing dia-

grams.

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once the device returns to the read

mode, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause the device to set DQ5 = 1, or cause the DQ7

and DQ6 status bits to indicate the operation was suc-

cessful. However, a succeeding read shows that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

START

Write Program

Command Sequence

Data Poll

from System

Unlock Bypass Command Sequence

Embedded

Program

algorithm

in progress

The unlock bypass feature allows the system to pro-

gram words to the device faster than using the stan-

dard program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Table 10 on page 29 shows the require-

ments for the command sequence.

Verify Data?

No

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 10 on page 29, for program command

sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h. The second cycle must contain the data 00h. The

device then returns to the read mode.

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 10 on

page 29 shows the address and data requirements for

the chip erase command sequence.

The device offers accelerated program operations

through the ACC pin. When the system asserts V_HHon

the ACC pin, the device automatically enters the Un-

lock Bypass mode. The system may then write the

two-cycle Unlock Bypass program command se-

quence. The device uses the higher voltage on the

ACC pin to accelerate the operation. Note that the

ACC pin must not be at V_HHfor operations other than

accelerated programming, or device damage may re-

sult.

Figure 3 illustrates the algorithm for the program oper-

ation. Refer to the “Erase and Program Operations” on

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

25

D A T A S H E E T

When the Embedded Erase algorithm is complete, the

gins from the rising edge of the final WE# pulse in the

command sequence.

device returns to the read mode and addresses are no

longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6, DQ2, or

RY/BY#. Refer to “Write Operation Status” on page 30

for information on these status bits.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses

are no longer latched. The system can determine the

status of the erase operation by reading DQ7, DQ6,

DQ2, or RY/BY#. Refer to “Write Operation Status” on

page 30 for information on these status bits.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once the device has returned to reading

array data, to ensure data integrity.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once the device returns to read-

ing array data, to ensure data integrity.

Figure 4, on page 28 illustrates the algorithm for the

erase operation. Refer to the table “Erase and Pro-

gram Operations” on page 40 in the AC Characteris-

tics section for parameters, and Figure 17, on page 42

for timing diagrams.

Figure 4, on page 28 illustrates the algorithm for the

erase operation. Refer to the table “Erase and Pro-

gram Operations” on page 40 in the AC Characteris-

tics section for parameters, and Figure 17, on page 42

for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 10 on page 29

shows the address and data requirements for the sec-

tor erase command sequence.

Erase Suspend/Erase Resume

Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. This command is valid only during the sec-

tor erase operation, including the 50 µs time-out pe-

riod during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program

algorithm.

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation.

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise erasure may begin. Any sector erase ad-

dress and command following the exceeded time-out

may or may not be accepted. It is recommended that

processor interrupts be disabled during this time to en-

sure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets

the device to the read mode. The system must re-

write the command sequence and any additional ad-

dresses and commands.

After the erase operation is suspended, the device en-

ters the erase-suspend-read mode. The system can

read data from or program data to any sector not se-

lected for erasure. (The device “erase suspends” all

sectors selected for erasure.) Reading at any address

within erase-suspended sectors produces status infor-

mation on DQ7–DQ0. The system can use DQ7, or

DQ6 and DQ2 together, to determine if a sector is ac-

tively erasing or is erase-suspended. Refer to “Write

Operation Status” on page 30 for information on these

status bits.

After an erase-suspended program operation is com-

plete, the device returns to the erase-suspend-read

mode. The system determines the status of the pro-

gram operation using the DQ7 or DQ6 status bits, just

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section “DQ3:

Sector Erase Timer” on page 32.). The time-out be-

26

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

as in the standard word program operation. Refer to

“Write Operation Status” on page 30 for more informa-

tion.

START

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. Refer to

“Autoselect Mode” on page 17 and “Autoselect Com-

mand Sequence” on page 25 for details.

Write Erase

Command Sequence

(Notes 1, 2)

To resume the sector erase operation, the system

must write the Erase Resume command. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the chip

resumes erasing.

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 10 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 4. Erase Operation

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

27

D A T A S H E E T

Command Definitions

Table 10. Command Definitions

Bus Cycles (Notes 1–4)

Third Fourth

Addr

First

Second

Fifth

Sixth

Command

Sequence

Addr Data Addr Data

Data

Addr

Data

Addr Data Addr Data

Read (Note 5)

Reset (Note 6)

Manufacturer ID

Device ID

1

4

RA

XXX

555

RD

F0

AA

2AA

55

555

90

X00

X01

0001

22D7

see

X02 (Note

9)

SecSi™ Sector Factory

Protect (Note 8)

6

555

AA

2AA

55

555

88

X02

60

X02

40

Sector Group Protect Verify

(Note 9)

XX00/

XX01

4

555

AA

2AA

55

555

90 (SA)X02

88

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

3

4

3

555

AA

2AA

55

555

90

A0

20

XXX

PA

00

PD

Unlock Bypass

Unlock Bypass Program (Note 10)

XXX

A0

PA

PD

00

55

2

Unlock Bypass Reset (Note 11)

Chip Erase

XXX

555

XXX

55

90

AA

B0

30

XXX

2AA

2

6

1

555

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Erase Suspend (Note 12)

Erase Resume (Note 13)

CFI Query (Note 14)

98

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A21–A15 uniquely select any sector.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses

latch on the falling edge of the WE# or CE# pulse, whichever happens

later.

Notes:

1. See Table 1 on page 11 for a description of bus operations.

8. If WP# protects the highest address sector (or if WP# is not

available), the data is 98h for factory locked and 18h for not

factory locked. If WP# protects the lowest address sector, the

data is 88h for factory locked and 08h for not factor locked.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

9. The data is 00h for an unprotected sector group and 01h for a

protected sector group.

4. During unlock cycles, (when lower address bits are 555 or 2AAh

as shown in table) address bits higher than A11 (except where BA

is required) and data bits higher than DQ7 are don’t cares.

10. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

5. No unlock or command cycles required when device is in read

mode.

11. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

6. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when the device is in the autoselect mode, or if DQ5 goes high

(while the device is providing status information).

12. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation.

7. The fourth cycle of the autoselect command sequence is a read

cycle. Data bits DQ15–DQ8 are don’t care. See the “Autoselect

Command Sequence” on page 25 section for more information.

13. The Erase Resume command is valid only during the Erase

Suspend mode.

14. Command is valid when device is ready to read array data or when

device is in autoselect mode.

28

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 11 on page 33 and the following subsections

describe the function of these bits. DQ7 and DQ6 each offer

a method for determining whether a program or erase oper-

ation is complete or in progress. The device also provides a

hardware-based output signal, RY/BY#, to determine

whether an Embedded Program or Erase operation is in

progress or was completed.

invalid. Valid data on DQ0–DQ7 appears on succes-

sive read cycles.

Table 11 on page 33 shows the outputs for Data# Poll-

ing on DQ7. Figure 5, on page 30 shows the Data#

Polling algorithm. Figure 18, on page 43 in the AC

Characteristics section shows the Data# Polling timing

diagram.

DQ7: Data# Polling

START

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether the device is in Erase

Suspend. Data# Polling is valid after the rising edge of the

final WE# pulse in the command sequence.

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, at thai time the device returns to

the read mode.

Yes

DQ7 = Data?

No

DQ5 = 1?

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Yes

Read DQ7–DQ0

Addr = VA

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

device returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ0–DQ6 may be still

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

29

D A T A S H E E T

Table 11 on page 33 shows the outputs for Toggle Bit I

RY/BY#: Ready/Busy#

on DQ6. Figure 6, on page 31 shows the toggle bit al-

gorithm. Figure 19, on page 44 in the “AC Characteris-

tics” section shows the toggle bit timing diagrams.

Figure 20, on page 44 shows the differences between

DQ2 and DQ6 in graphical form. See also the subsec-

tion “DQ2: Toggle Bit II” on page 32.

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or the device is in the erase-suspend-read

mode.

START

Read DQ7–DQ0

Table 11 on page 33 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Read DQ7–DQ0

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

No

Toggle Bit

= Toggle?

Yes

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

No

DQ5 = 1?

Yes

After an erase command sequence is written, if all sectors

selected for erasing are protected, DQ6 toggles for approxi-

mately 100 µs, then returns to reading array data. If not all

selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

No

The system can use DQ6 and DQ2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), DQ6 toggles. When the de-

vice enters the Erase Suspend mode, DQ6 stops toggling.

However, the system must also use DQ2 to determine

which sectors are erasing or erase-suspended. Alterna-

tively, the system can use DQ7 (see the subsection “DQ7:

Data# Polling” on page 30).

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if

DQ5 = “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 μs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

Figure 6. Toggle Bit Algorithm

30

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

the toggle bit and DQ5 through successive read cy-

DQ2: Toggle Bit II

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 6, on

page 31).

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ5: Exceeded Timing Limits

DQ2 toggles when the system reads at addresses

within those sectors that were selected for erasure.

(The system may use either OE# or CE# to control the

read cycles.) But DQ2 cannot distinguish whether the

sector is actively erasing or is erase-suspended. DQ6,

by comparison, indicates whether the device is ac-

tively erasing, or is in Erase Suspend, but cannot dis-

tinguish which sectors are selected for erasure. Thus,

both status bits are required for sector and mode infor-

mation. Refer to Table 11 on page 33 to compare out-

puts for DQ2 and DQ6.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a “1,” indicating that the program

or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit is

exceeded, DQ5 produces a “1.”

Figure 6, on page 31 shows the toggle bit algorithm in

flowchart form, and the section “DQ2: Toggle Bit II” ex-

plains the algorithm. See also the “DQ6: Toggle Bit I”

on page 31 subsection. Figure 19, on page 44 shows

the toggle bit timing diagram. Figure 20, on page 44

shows the differences between DQ2 and DQ6 in

graphical form.

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if the device was previ-

ously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the time between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also “Sector Erase Command Se-

quence” on page 27.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6, on page 31 for the following discus-

sion. Whenever the system initially begins reading tog-

gle bit status, it must read DQ7–DQ0 at least twice in a

row to determine whether a toggle bit is toggling. Typi-

cally, the system would note and store the value of the

toggle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device accepts additional sector erase commands. To

ensure the command was accepted, the system soft-

ware should check the status of DQ3 prior to and fol-

lowing each subsequent sector erase command. If

DQ3 is high on the second status check, the last com-

mand might not have been accepted.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the sub-section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no

longer toggling, the device has successfully completed

the program or erase operation. If it is still toggling, the

device did not completed the operation successfully,

and the system must write the reset command to re-

turn to reading array data.

Table 11 on page 33 shows the status of DQ3 relative

to the other status bits.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

31

D A T A S H E E T

Table 11. Write Operation Status

DQ7

(Note 2)

DQ5

(Note 1)

DQ2

(Note 2)

RY/BY#

(Note 3)

Status

DQ6

DQ3

N/A

1

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase-Suspend-

Read

Erase

Suspend

Mode

Non-Erase

Data

0

Data

N/A

Data

N/A

1

0

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. RY/BY# is only available on the FBGA package.

32

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

20 ns

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

+0.8 V

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

–0.5 V

–2.0 V

Voltage with Respect to Ground

V

_CC(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

20 ns

V_IO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +5.5 V

Figure 7. Maximum Negative

Overshoot Waveform

A9, OE#, ACC, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

All other pins (Note 1). . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

See Figure 7. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 8.

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

2.0 V

2. Minimum DC input voltage on pins A9, OE#, ACC, and

RESET# is –0.5 V. During voltage transitions, A9, OE#,

ACC, and RESET# may overshoot V_SSto –2.0 V for

periods of up to 20 ns. See Figure 7. Maximum DC input

voltage on pin A9, OE#, ACC, and RESET# is +12.5 V

which may overshoot to +14.0 V for periods up to 20 ns.

20 ns

Figure 8. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Supply Voltages

V

_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0–3.6 V

V_IO. . . . . . . . . . . . . . . . .either 1.8–2.9 V or 3.0–5.0 V

(see “Ordering Information” on page 10)

Operating ranges define those limits between which the

functionality of the device is guaranteed.

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

33

D A T A S H E E T

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

V_IN= V_SSto V_CC

Min

Typ

Max

±1.0

35

Unit

µA

,

I_LI

Input Load Current (Note 1)

A9, ACC Input Load Current

Output Leakage Current

V_CC= V_{CC max}

I_LIT

V_CC= V_{CC max}; A9 = 12.5 V

µA

V_OUT= V_SSto V_CC

,

I_LO

±1.0

µA

V_CC= V_{CC max}

5 MHz

1 MHz

9

2

16

4

V_CCActive Read Current

(Notes 2, 3)

I_CC1

CE# = V_IL,OE# ₌V_IH

mA

I_CC2

I_CC3

I_CC4

I_CC5

V_CCActive Write Current (Notes 3, 4) CE# = V_IL,OE# ₌V_IH, WE# = V_IL

26

30

mA

µA

CE#, RESET# = V_CC± 0.3 V,

V_CCStandby Current (Note 3)

WP# = V_IH

0.2

5

V_CCReset Current (Note 3)

RESET# = V_SS± 0.3 V, WP# = V_IH

_IH= V_CC± 0.3 V;

V_IL= V_SS± 0.3 V, WP# = V_IH

ACC pin

_CCpin

V

Automatic Sleep Mode (Notes 3, 5)

5

10

30

mA

V

I_ACC

ACC Accelerated Program Current

CE# = V_IL, OE# = V_IH

V

15

V_IL

V_IH

Input Low Voltage (Note 6)

Input High Voltage (Note 6)

–0.5

0.8

0.7 x V_CC

V_CC+ 0.3

V

Voltage for ACC Program

Acceleration

V_HH

V_ID

V

_CC= 3.0 V 10%

V_CC= 3.0 V ± 10%

I_OL= 4.0 mA, V_CC= V_{CC min}

11.5

8.5

12.5

V

Voltage for Autoselect and Temporary

Sector Unprotect

12.5

0.45

V_OL

V_OH1

V_OH2

V_LKO

Output Low Voltage

V

I_OH= –2.0 mA, V_CC= V_{CC min}

I_OH= –100 µA, V_CC= V_{CC min}

0.8 V_IO

V_IO–0.4

2.3

Output High Voltage

Low V_CCLock-Out Voltage (Note 7)

2.5

Notes:

1. On the WP# pin only, the maximum input load current when WP# = V_ILis 5.0 ꢀA.

2. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

3. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

4. I_CCactive while Embedded Erase or Embedded Program is in progress.

5. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns. Typical sleep mode current is

200 nA.

6. If V_IO< V_CC, maximum V_ILfor CE# and DQ I/Os is 0.3 V_IO. If V_IO< V_CC, minimum V_IHfor CE# and DQ I/Os is 0.7 V_IO. Maximum V_IH

for these connections is V_IO+ 0.3 V

7. Not 100% tested.

34

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

DC CHARACTERISTICS

Zero-Power Flash

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

12

10

8

3.6 V

3.0 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I_CC1vs. Frequency

Am29LV640D/Am29LV641D

February 26, 2009 22366C7

35

D A T A S H E E T

TEST CONDITIONS

Table 12. Test Specifications

120R,

3.3 V

Test Condition

90R

121R

Unit

2.7 kΩ

Output Load

1 TTL gate

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

100

pF

C

L

6.2 kΩ

Input Rise and Fall Times

Input Pulse Levels

5

0.0–3.0

ns

V

Input timing measurement

reference levels (See Note)

1.5

V

Note: Diodes are IN3064 or equivalent

Output timing measurement

reference levels

0.5 V_IO

Figure 11. Test Setup

Note: If V_IO< V_CC, the reference level is 0.5 V_IO.

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Changing, State Unknown

Don’t Care, Any Change Permitted

Does Not Apply

Center Line is High Impedance State (High Z)

3.0 V

1.5 V

0.5 V_IOV

Input

Measurement Level

Output

0.0 V

Note: If V_IO< V_CC, the input measurement reference level is 0.5 V_IO.

Figure 12. Input Waveforms and

Measurement Levels

36

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed Options

120R,

JEDEC

t_AVAV

Std.

t_RC

t_ACC

t_CE

Description

Test Setup

90R

90

35

30

121R

120

50

Unit

ns

Read Cycle Time (Note 1)

Address to Output Delay

Min

Max

t_AVQV

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

CE#, OE# = V_IL

OE# = V_IL

ns

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

ns

t_OE

t_DF

ns

30

ns

t_DF

30

ns

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First

t_AXQX

t_OH

Min

0

ns

Read

Output Enable Hold

Time (Note 1)

t_OEH

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 12 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operation Timings

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

37

D A T A S H E E T

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

20

μs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

μs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RH

t_RP

Figure 14. Reset Timings

38

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed Options

120R,

JEDEC

t_AVAV

Std.

t_WC

t_AS

Description

90R

121R

Unit

ns

Write Cycle Time (Note 1)

Min

90

120

t_AVWL

Address Setup Time

0

ns

t_ASO

t_AH

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

ns

t_WLAX

45

50

ns

Address Hold Time From CE# or OE# high

during toggle bit polling

t_AHT

Min

0

ns

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

ns

Data Hold Time

0

t_OEPH

Output Enable High during toggle bit polling

20

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# Setup Time

Min

Typ

Min

Max

0

ns

µs

sec

ns

µs

ns

CE# Hold Time

t_WP

Write Pulse Width

35

50

t_WPH

t_WHWH1

t_WHWH2

t_VHH

Write Pulse Width High

30

11

7

t_WHWH1

t_WHWH2

Word Programming Operation (Note 2)

Accelerated Word Programming Operation (Note 2)

Sector Erase Operation (Note 2)

V_HHRise and Fall Time (Note 1)

V_CCSetup Time (Note 1)

0.9

250

50

0

t_VCS

t_RB

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

t_BUSY

90

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

39

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 15. Program Operation Timings

V_HH

V_ILor V_IH

ACC

t_VHH

Figure 16. Accelerated Program Timing Diagram

40

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.

2. These waveforms are for the word mode.

Figure 17. Chip/Sector Erase Operation Timings

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

41

D A T A S H E E T

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

Status Data

True

DQ0–DQ6

Valid Data

Status Data

True

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 18. Data# Polling Timings

(During Embedded Algorithms)

42

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle

Figure 19. Toggle Bit Timings

(During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 20. DQ2 vs. DQ6

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

43

D A T A S H E E T

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

t_VIDR

V_IDRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Group Unprotect

t_RRB

Min

Note: Not 100% tested.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 21. Temporary Sector Group Unprotect Timing Diagram

44

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

60h

Valid*

Status

Sector Group Protect or Unprotect

Verify

40h

Data

60h

Sector Group Protect: 150 µs,

Sector Group Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 22. Sector Group Protect and Unprotect Timing Diagram

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

45

D A T A S H E E T

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

Speed Options

120R,

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

90R

121R

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

90

120

t_AVWL

t_ELAX

t_DVEH

t_EHDX

0

ns

t_AH

t_DS

t_DH

45

50

ns

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

ns

t_WLEL

t_EHWH

t_ELEH

t_WS

t_WH

WE# Setup Time

Min

Typ

0

ns

WE# Hold Time

t_CP

CE# Pulse Width

45

50

ns

t_EHEL

t_CPH

CE# Pulse Width High

30

11

7

ns

t_WHWH1

t_WHWH2

t_WHWH1

t_WHWH2

Word Programming Operation (Note 2)

Accelerated Word Programming Operation (Note 2)

Sector Erase Operation (Note 2)

µs

0.9

sec

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

46

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. Waveforms are for the word mode.

Figure 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

47

D A T A S H E E T

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

Comments

Sector Erase Time

Chip Erase Time

0.9

15

Excludes 00h programming

prior to erasure (Note 4)

115

Excludes system level

overhead (Note 5)

Word Program Time

11

300

µs

Accelerated Word Program Time

Chip Program Time (Note 3)

Notes:

7

210

144

µs

48

sec

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 3.0 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

10 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

6

Max

7.5

12

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

Control Pin Capacitance

V_OUT= 0

V_IN= 0

8.5

7.5

pF

9

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

48

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

PHYSICAL DIMENSIONS

SSO056—56-Pin Shrink Small Outline Package (SSOP)

Dwg rev AB; 10/99

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

49

D A T A S H E E T

PHYSICAL DIMENSIONS

FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 12 x 11 mm package

Dwg rev AF; 10/99

50

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

PHYSICAL DIMENSIONS

LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm package

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

51

D A T A S H E E T

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard TSOP

Dwg rev AA; 10/99

Note: For reference only. BSC is an ANSI standard for Basic Space Centering.

* For reference only. BSC is an ANSI standard for Basic Space Centering.

52

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

REVISION SUMMARY

Ordering Information

Revision A (April 26, 1999)

Added the valid combinations for the SSOP package.

Initial release.

Revision A+6 (September 28, 1999)

Revision A+1 (May 4, 1999)

Connection Diagrams

Global

Clarified which packages are available for a particular

part number.

Deleted references to the 4-word unique ESN. Re-

placed references to V_CCQwith V_IO.

Device Bus Operations

Connection Diagrams

VersatileIO Control: Added comment to contact AMD

for more information on this feature.

63-ball FBGA: Corrected signal for ball H7 to V_IO.

Ordering Information

DC Characteristics

Added “U” designator description.

CMOS Compatible table: Added notes (1 and 2) for I_LI

and test conditions column.

SecSi (Secured Silicon) Sector Flash Memory

Region

Test Conditions

In the third paragraph, replaced references to boot

sectors with SA0. Added table to show SecSi sector

contents.

In Test Specifications table and Input Waveforms and

Measurement Levels figure, changed the output mea-

surement level to V_IO/2.

DC Characteristics table

AC Characteristics

Added V_IO= V_CCas a test condition for I_CC1and I_CC2

Changed V_HHminimum specification from 8.5 V to

11.5 V.

.

Read-only Operations table: Added note for test setup

column.

Revision B (June 20, 2000)

Revision A+2 (May 14, 1999)

Global

Ordering Information

Deleted references to 150 ns speed option. Added

more information and specifications on V_IOfeature, in-

cluding part number distinctions. At V_IO< V_CC, the

available speed options are 100 ns and 120 ns. At V_IO

≥ V_CC, the available speed options are 90 ns and 120

ns. Changed data sheet status to “Preliminary.”

Clarified the differences between the H, L, and U

designators.

Revision A+3 (June 7, 1999)

Product Selector Guide

Added note under table.

Distinctive Characteristics

Ordering Information

Clarified on which devices RY/BY# and WP# are avail-

able. Clarified package options for devices.

Deleted the “0” from the 120 and 150 ns part numbers.

Corrected the FBGA package marking for the 150 ns

speed option.

Ordering Information

Clarified on which devices RY/BY# and WP# are avail-

able. Clarified package options for devices. Reinstated

“0” into the 120 ns speed part number for V_IO= 3.0 V

to 5.0 V; added part numbers for V_IO= 1.8 V to 2.9 V.

Revision A+4 (June 25, 1999)

Global

Information on the 56-pin SSOP package has been

added: pinout information and physical dimension

drawings.

Device Bus Operations table

In the legend, corrected the V_HHvoltage range.

SecSi Sector Contents table

Command Definitions

Corrected ending address in second row to 7Fh.

Corrected the data for SecSi Sector protection in Note

9. Added device ID data to the table.

DC Characteristics table

Redefined V_OH1and V_OH2in terms of V_IO. Added note

relative to V_IOfor V_IHand V_IL. Deleted note regarding

Revision A+5 (August 2, 1999)

Block Diagram

test condition assumption of V_IO= V_CC

.

Separated WP# and ACC.

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

53

D A T A S H E E T

Test Conditions

Revision B+5 (October 11, 2001)

Test Conditions table: Redefined output timing mea-

surement reference level as 0.5 V_IO.

Connection Diagrams, Ordering Information,

Physical Dimensions

Added note to table and figure.

Added 64-ball Fortified BGA package information.

Erase and Program Operations table, Alternate

CE# Controlled Erase and Program Operations

table, Erase and Programming Performance table

Revision B+6 (January 10, 2002)

Global

Changed the typical sector erase time to 1.6 s.

Clarified description of VersatileIO (V_IO) in the follow-

ing sections: Distinctive Characteristics; General De-

scription; VersatileIO (V_IO) Control; Operating Ranges;

DC Characteristics; CMOS compatible.

AC Characteristics—Figure 15. Program

Operations Timing and Figure 17. Chip/Sector

Erase Operations

Reduced typical sector erase time from 1.6 s to 0.9 s.

Deleted t_GHWLand changed OE# waveform to start at

high.

DC Characteristics

Physical Dimensions

Changed minimum V_OH1from 0.85V_IOto 0.8V_IO. De-

leted reference to Note 6 for both V_OH1and V_OH2

.

Replaced figures with more detailed illustrations.

Erase and Program Performance table

Revision B+1 (August 4, 2000)

Reduced typical sector erase time from 1.6 s to 0.9 s.

Changed typical chip program time from 90 s to 115 s.

Global

Added trademarks for SecSi Sector.

Revision B+7 (April 15, 2002)

Accelerated Program Operation (page 12), Unlock

Bypass Command Sequence (page 26)

Ordering Information

Added N designator for Fortified BGA package mark-

ings.

Added caution note regarding ACC pin.

Absolute Maximum Ratings

Common Flash Interface (CFI)

Corrected the maximum voltage on V_IOto +5.5V.

Revised data value at address 44h. Clarified descrip-

tion of data for addresses 45–47h, 49, 4A, 4D–4Fh.

DC Characteristics table

Added WP# = V_IHto test conditions for standby cur-

Table 10, Command Definitions

rents I_CC3, I_CC4, I_CC5

.

Clarified and combined Notes 4 and 5 into Note 4.

Revision B+2 (October 18, 2000)

Revision B+8 (September 20, 2002)

Distinctive Characteristics

Sector Erase Command Sequence

Corrected package options for 56-pin SSOP as being

available on Am29LV640DH/DL only.

Changed sentence arrangement in fourth paragraph.

Revision B+9 (March 3, 2004)

Revision B+3 (January 18, 2001)

Table 10, Command Definitions

Global

Revised SecSi Sector Factory Protect (note 8) com-

mand definitions.

Deleted “Preliminary” status from document.

General Description

Revision B+10 (April 5, 2004)

In the second paragraph, corrected references to V_IO

voltage ranges. The 90 and 120 speeds are available

where V_IO≥ V_CC, and 100 and 120 ns speeds are avail-

Command Definitions

Changed first Address data for Erase Suspend/Re-

sume from BA to XXX.

able where V_IO< V_CC

.

Revision B+4 (March 8, 2001)

Revision C (June 4, 2004)

Table 4, Sector Group Protection/Unprotection

Address Table

Ordering Information

Added Pb-free OPNs.

Corrected the sector group address bits for sectors

64–127.

54

Am29LV640D/Am29LV641D

22366C7 February 26, 2009

D A T A S H E E T

Revision C + 1 (October 14, 2004)

Revision C + 4 (September 13, 2005)

Ordering Information

Valid Combinations

Added t_RHreference line to Figure 14.

New option FF added on TSOP and SSOP packages.

Revision C5 (December 23, 2005)

Corrected description of Sector Erase Command Se-

quence on page 30.

Global

Added Colophon

Deleted reverse TSOP package option and 100 ns

speed option.

Revision C + 2 (January 7, 2005)

Valid Combinations

Revision C6 (January 22, 2007)

Updated table to include a note regarding product of-

ferings for new designs.

AC Characteristics

Erase and Program Operations table: Changed t_BUSY

to a maximum specification.

Revision C + 3 (February 9, 2005)

Pin Description

Revision C7 (February 26, 2009)

Added RFU to the list of pins.

Global

Added obsolescence information.

Removed references to byte mode.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable

to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating

conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks

marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are

for identification purposes only and may be trademarks of their respective companies.

ORNAND2™, HD-SIM™, EcoRAM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names

used are for informational purposes only and may be trademarks of their respective owners.

February 26, 2009 22366C7

Am29LV640D/Am29LV641D

55


型号：	AM29LV641DH121RFFN
厂家：	SPANSION
描述：	Flash, 4MX16, 120ns, PDSO48, MO-142DD, TSOP-48 光电二极管
文件：	总57页 (文件大小：1322K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29LV641DH121RFFN [SPANSION]

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