AM29LV641GH103EK_技术文档

ADVANCE INFORMATION

Am29LV641GH/L / Am29LV640GU

64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only

Uniform Sector Flash Memory with VersatileI/O Control

DISTINCTIVE CHARACTERISTICS

■ Ultra low power consumption (typical values at 3.0 V,

ARCHITECTURAL ADVANTAGES

5 MHz)

■ Single power supply operation

— 9 mA typical active read current

— 26 mA typical erase/program current

— 200 nA typical standby mode current

— 2.7 to 3.6 volt read, erase, and program operations

■ SecSi (Secured Silicon) Sector region

— 128-word sector for permanent, secure identification

through an 8-word random Electronic Serial Number

■ Program and erase performance (V_HHnot applied to

the ACC input pin)

— May be programmed and locked at the factory or by

the customer

— Word program time: 7 µs typical

— Sector erase time: 0.6 s typical for each 32 Kword

sector

— Accessible through a command sequence

■ VersatileI/O control

— Device generates data output voltages and tolerates

data input voltages as determined by the voltage on

the V_IOpin

SOFTWARE AND HARDWARE FEATURES

■ Hardware features

— Hardware reset input (RESET#): resets device for

■ Manufactured on 0.17 µm process technology

new operation

— WP# input: protects first or last 32 Kword sector

regardless of sector protection settings

(LV641GH/L only)

■ Flexible sector architecture

— One hundred twenty-eight 32 Kword sectors

■ Compatibility with JEDEC standards

— ACC input: Accelerates programming time for higher

— Pinout and software compatible with single-power

supply Flash standard

throughput during system production

■ Software features

■ Package options

— Program Suspend & Resume: read other sectors

— 48-pin TSOP and Reverse TSOP (LV641GH/L only)

— 63-ball Fine-pitch BGA (LV640GU only)

before programming operation is completed

— Sector Group Protection: V_CC-level method of

preventing program or erase operations within a

sector

— 64-ball Fortified BGA (LV640GU only)

■ Minimum 1 million erase cycle guarantee per sector

■ 20-year data retention at 125°C

— Temporary Sector Group Unprotect: V_ID-level method

of changing in previously locked sectors

— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

PERFORMANCE CHARCTERISTICS

■ High performance

— Access time ratings as fast as 70 ns

— Erase Suspend/Erase Resume: read/program other

sectors before an erase operation is complete

— Data# Polling and toggle bits provide erase and

programming operation status

— Unlock Bypass Program command reduces overall

multiple-word programming time

Publication# 25295 Rev: A Amendment/1

Issue Date: August 28, 2002

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you

evaluate this product. Do not design in this product without contacting the factory. AMD reserves the right to change or discontinue work

on this proposed product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION

The Am29LV641GH/L / Am29LV640GU are 64 Mbit,

3.0 volt (2.7 V to 3.6 V) single power supply flash

memory devices organized as 4,194,304 words. Data

appears on DQ15–DQ0. These devices are designed

to be programmed in-system with the standard system

3.0 volt V_CCsupply. A 12.0 volt V_PPis not required for

program or erase operations. The device can also be

programmed in standard EPROM programmers.

vice is ready to read array data or accept another

command.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of sectors of memory.

This can be achieved in-system or via programming

equipment.

Access times of 70, 90, and 100 ns are available for

applications where V_IO≥ V_CC. Access times of 90 and

100 ns are available for applications where V_IO< V_CC

.

The Am29LV641GH/L is offered in 48-pin TSOP and

reverse TSOP packages. The Am29LV640GU is of-

fered in a 63-ball Fine-pitch BGA package and a

64-ball Fortified BGA. To eliminate bus contention

each device has separate chip enable (CE#), write en-

able (WE#) and output enable (OE#) controls.

The Erase Suspend/Erase Resume feature enables

the user to put erase on hold for any period of time to

read data from, or program data to, any sector that is

not selected for erasure. True background erase can

thus be achieved. The Program Suspend/Program

Resume feature enables the host system to pause a

program operation in a given sector to read any other

sector and then complete the program operation.

Each device requires only a single 3.0 volt power

supply (2.7 V to 3.6 V) for both read and write func-

tions. Internally generated and regulated voltages are

provided for the program and erase operations.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timing. Register con-

tents serve as inputs to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data

needed for the programming and erase operations.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to

the system reset circuitry. A system reset would thus

also reset the device, enabling the system micropro-

cessor to read boot-up firmware from the Flash mem-

ory device.

The device offers a standby mode as a power-saving

feature. Once the system places the device into the

standby mode power consumption is greatly reduced.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

The SecSi (Secured Silicon) Sector provides an

minimum 128-word area for code or data that can be

permanently protected. Once this sector is protected,

no further programming or erasing within the sector

can occur.

The Write Protect (WP#) feature protects the first or

last sector by asserting a logic low on the WP# pin.

The protected sector will still be protected even during

accelerated programming. (Am29LV641GH/L only)

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already pro-

grammed) before executing the erase operation. Dur-

ing erase, the device automatically times the erase

pulse widths and verifies proper cell margin.

The accelerated program (ACC) feature allows the

system to program the device at a much faster rate.

When ACC is pulled high to V_HH, the device enters the

Unlock Bypass mode, enabling the user to reduce the

time needed to do the program operation. This feature

is intended to increase factory throughput during sys-

tem production, but may also be used in the field if de-

sired.(Am29LV641GH/L only)

The VersatileI/O™ (V_IO) control allows the host sys-

tem to set the voltage levels that the device generates

at its data outputs and the voltages tolerated at its

data inputs to the same voltage level that is asserted

on the V_IOpin. This allows the device to operate in 1.8

V or 3 V system environment as required.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunnelling.

The data is programmed using hot electron injection.

The host system can detect whether a program or

erase operation is complete by reading the DQ7

(Data# Polling) or DQ6 (toggle) status bits. After a

program or erase cycle has been completed, the de-

2

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Special Package Handling Instructions ....................................7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations .....................................................10

DQ7: Data# Polling .................................................................29

Figure 5. Data# Polling Algorithm .................................................. 29

DQ6: Toggle Bit I ....................................................................29

Figure 6. Toggle Bit Algorithm........................................................ 30

DQ2: Toggle Bit II ...................................................................31

Reading Toggle Bits DQ6/DQ2 ...............................................31

DQ5: Exceeded Timing Limits ................................................31

DQ3: Sector Erase Timer .......................................................31

Table 11. Write Operation Status ................................................... 32

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33

Figure 7. Maximum Negative Overshoot Waveform ..................... 33

Figure 8. Maximum Positive Overshoot Waveform....................... 33

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 33

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 9. I_CC1Current vs. Time (Showing

Active and Automatic Sleep Currents) ........................................... 35

Figure 10. Typical I_CC1vs. Frequency............................................ 35

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 11. Test Setup.................................................................... 36

Table 12. Test Specifications ......................................................... 36

Key to Switching Waveforms. . . . . . . . . . . . . . . . 36

Figure 12. Input Waveforms and

VersatileI/O (V ) Control ....................................................10

IO

Requirements for Reading Array Data ...................................10

Writing Commands/Command Sequences ............................11

Accelerated Program Operation ......................................................11

Autoselect Functions .......................................................................11

Standby Mode ........................................................................ 11

Automatic Sleep Mode ...........................................................11

RESET#: Hardware Reset Pin ...............................................11

Output Disable Mode ..............................................................12

Table 2. Sector Address Table ........................................................12

Autoselect Mode ..................................................................... 16

Table 3. Am29LV641GH/L / Am29LV640GU Autoselect Codes,

(High Voltage Method) ...................................................................16

Sector Group Protection and Unprotection .............................17

Table 4. Sector Group Protection/Unprotection Address Table .....17

Write Protect (WP#) ................................................................18

Temporary Sector Group Unprotect .......................................18

Figure 1. Temporary Sector Group Unprotect Operation................ 18

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 19

SecSi (Secured Silicon) Sector Flash Memory Region .......20

Table 5. SecSi Sector Contents ......................................................20

Hardware Data Protection ......................................................20

Low V_CCWrite Inhibit .......................................................................20

Write Pulse “Glitch” Protection ........................................................21

Logical Inhibit ..................................................................................21

Power-Up Write Inhibit ....................................................................21

Common Flash Memory Interface (CFI) . . . . . . . 21

Table 6. CFI Query Identification String.......................................... 21

Table 7. System Interface String..................................................... 22

Table 8. Device Geometry Definition .............................................. 22

Table 9. Primary Vendor-Specific Extended Query ........................ 23

Command Definitions . . . . . . . . . . . . . . . . . . . . . 23

Reading Array Data ................................................................23

Reset Command .....................................................................24

Autoselect Command Sequence ............................................24

Enter SecSi Sector/Exit SecSi Sector Command Sequence ..24

Word Program Command Sequence .....................................24

Unlock Bypass Command Sequence ..............................................25

Figure 3. Program Operation .......................................................... 25

Chip Erase Command Sequence ...........................................25

Sector Erase Command Sequence ........................................26

Erase Suspend/Erase Resume Commands ...........................26

Program Suspend/Program Resume Commands ..................27

Figure 4. Erase Operation............................................................... 27

Command Definitions ............................................................. 28

Table 10. Command Definitions...................................................... 28

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 29

Measurement Levels...................................................................... 36

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37

Read-Only Operations ...........................................................37

Figure 13. Read Operation Timings............................................... 37

Hardware Reset (RESET#) ....................................................38

Figure 14. Reset Timings............................................................... 38

Erase and Program Operations ..............................................39

Figure 15. Program Operation Timings.......................................... 40

Figure 16. Accelerated Program Timing Diagram.......................... 40

Figure 17. Chip/Sector Erase Operation Timings .......................... 41

Figure 18. Data# Polling Timings

(During Embedded Algorithms)...................................................... 42

Figure 19. Toggle Bit Timings

(During Embedded Algorithms)...................................................... 43

Figure 20. DQ2 vs. DQ6................................................................. 43

Temporary Sector Unprotect ..................................................44

Figure 21. Temporary Sector Group Unprotect Timing Diagram ... 44

Figure 22. Sector Group Protect and Unprotect Timing Diagram.. 45

Alternate CE# Controlled Erase and Program Operations .....46

Figure 23. Alternate CE# Controlled Write

(Erase/Program) Operation Timings .............................................. 47

Erase And Programming Performance . . . . . . . 48

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 48

TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 48

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 49

FBE063—63-Ball Fine-Pitch Ball Grid Array

(FBGA) 11 x 12 mm package .................................................49

LAA064—64-Ball Fortified Ball Grid Array (Fortified

BGA) 13 x 11 mm package .....................................................50

TS 048—48-Pin Standard TSOP ............................................51

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52

August 28, 2002

Am29LV641GH/L / Am29LV640GU

3

A D V A N C E I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Family Part Number

Speed Option

Am29LV641GH/L / Am29LV640GU

Standard Voltage Range: V_CC= 2.7–3.6 V

70

90

35

100

Max Access Time (ns)

CE# Access (ns)

OE# Access (ns)

70

35

100

50

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ15–DQ0

V_CC

V_SS

Sector Switches

V_IO

Erase Voltage

Generator

Input/Output

Buffers

RESET#

WE#

State

WP#

Control

ACC

Command

Register

RY/BY#

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

X-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

A21–A0

4

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

V_IO

V_SS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

A8

48-Pin Standard TSOP

A21

A20

WE#

RESET#

ACC

WP#

A19

A18

A17

A7

A6

A5

A4

A3

A2

A1

OE#

V_SS

CE#

A0

A15

A14

A13

A12

A11

A10

A9

A16

V_IO

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

V_SS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

48-Pin Reverse TSOP

A8

A21

A20

WE#

RESET#

ACC

WP#

A19

A18

A17

A7

A6

A5

A4

A3

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

OE#

V_SS

CE#

A0

A2

A1

August 28, 2002

Am29LV641GH/L / Am29LV640GU

5

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

ACC

1

2

3

4

5

6

7

8

9

56 RESET#

55 WE#

54 A20

53 A21

52 A8

WP#

A19

A18

A17

A7

51 A9

A6

50 A10

49 A11

48 A12

47 A13

46 A14

45 A15

44 NC

A5

A4

56-pin SSOP

A3 10

A2 11

A1 12

NC 13

NC 14

43 NC

NC 15

42 NC

NC 16

41 NC

A0 17

40 A16

39 V_IO

CE# 18

V_SS19

OE# 20

DQ0 21

DQ8 22

DQ1 23

DQ9 24

DQ2 25

DQ10 26

DQ3 27

DQ11 28

38 V_SS

37 DQ15

36 DQ7

35 DQ14

34 DQ6

33 DQ13

32 DQ5

31 DQ12

30 DQ4

29 V_CC

63-Ball Fine-pitch BGA

Top View, Balls Facing Down

L8

M8

A8

B8

NC

NC*

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

V_SS

NC

NC*

A13

A12

A14

A15

A16

V_IO

DQ15

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

V_CC

WE# RESET#

A21

A19

DQ5

DQ12

DQ4

C4

D4

E4

F4

G4

H4

J4

K4

RY/BY#

ACC

A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

L2

M2

A2

V_SS

CE#

OE#

NC*

A1

B1

L1

M1

* Balls are shorted together via the substrate but not connected to the die.

NC*

6

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

64-Ball Fortified BGA

Top View, Balls Facing Down

A8

B8

C8

D8

E8

F8

G8

H8

RFU

V_IO

V_SS

RFU

A7

B7

C7

D7

E7

F7

G7

H7

A13

A12

A14

A15

A16

BYTE#

DQ15

V_SS

A6

A9

B6

A8

C6

D6

E6

F6

G6

H6

DQ6

A10

A11

DQ7

DQ14

DQ13

A5

B5

C5

D5

E5

F5

G5

H5

WE# RESET#

A21

A19

DQ5

DQ12

V_CC

DQ4

A4 B4

C4

D4

E4

F4

G4

H4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

A3

A7

B3

C3

A6

D3

A5

E3

F3

G3

H3

A17

DQ0

DQ8

DQ9

DQ1

A2

A3

B2

A4

C2

A2

D2

A1

E2

A0

F2

G2

H2

CE#

OE#

V_SS

A1

B1

C1

D1

E1

F1

G1

H1

RFU

V_IO

RFU

compromised if the package body is exposed to

temperatures above 150 for prolonged periods of

times.

Special Package Handling Instructions

Special handling is required for Flash Memory

products in molded packages (TSOP, BGA, PLCC,

PDIP). The package and/or data integrity may be

August 28, 2002

Am29LV641GH/L / Am29LV640GU

7

A D V A N C E I N F O R M A T I O N

PIN DESCRIPTION

LOGIC SYMBOL

A21–A0

= 22 Addresses inputs

22

DQ15–DQ0 = 16 Data inputs/outputs

A21–A0

16

CE#

= Chip Enable input

DQ15–DQ0

CE#

OE#

= Output Enable input

= Write Enable input

OE#

WE#

WP#

ACC

RESET#

V_IO

WP#

= Hardware Write Protect input

= Acceleration Input

ACC

RY/BY#

RESET#

V_CC

= Ready/Busy output

= Hardware Reset Pin input

RY/BY#

= 3.0 volt-only single power supply

(see Product Selector Guide for

speed options and voltage

supply tolerances)

V_IO

V_SS

NC

= Output Buffer power

= Device Ground

= Pin Not Connected Internally

Note:WP# functionality is available only for

Am29LV641GH/L devices. RY/BY# functionality is available

only for Am29LV640GU devices .

8

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29LV641G

H

70

WH

I

TEMPERATURE RANGE

I

=

Industrial (–40°C to +85°C)

Extended (–55°C to +125°C)

E

PACKAGE TYPE

E

=

48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)

48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)

F

WH

63-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 11 x 12 mm package (FBE063)

PC

=

64-Ball Fortified Ball Grid Array (Fortified BGA)

1.0 mm pitch, 13 x 11 mm package (LAA064)

SPEED OPTION

See Product Selector Guide and Valid Combinations

SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = 0)

H

L

=

Uniform sector device, highest address sector protected

Uniform sector device, lowest address sector protected

DEVICE NUMBER/DESCRIPTION

Am29LV641GH/L / Am29LV640GU

64 Megabit (4 M x 16-Bit) CMOS Uniform Sector Flash Memory with VersatileIO Control

3.0 Volt-only Read, Program, and Erase

Valid Combinations for

TSOP Packages

Valid Combinations for FBGA Packages

Package

Speed/

V_IORange

Speed/V_IORange

Am29LV641GH78,

70 ns

Order Number

Marking

Am29LV641GL78

V

_IO= 1.65 V – 1.95 V

70 ns

V_IO= 1.65 V

– 1.95 V

EI, FI

L640GH78V,

L640GL78V

Am29LV641GH93,

Am29LV641GL93

90 ns

_IO= 2.7 V – 3.6 V

90 ns,

AM29LV640GU78

WHI

PCI

V

I

Am29LV641GH98,

Am29LV641GL98

90 ns

_IO= 2.7 V –

3.6 V

L640GH93P,

L640GL93P

V

_IO= 1.65 V – 1.95 V

AM29LV640GU93

AM29LV640GU98

AM29LV640GU103

V

EI, FI,

EE, FE

Am29LV641GH103,

Am29LV641GL103

100 ns

V_IO= 2.7 V – 3.6 V

WHI L640GH98V

PCI L640GL98P

WHE L640GL98V

PCI L640GH103P

90 ns,

V_IO= 1.65 V

– 1.95 V

Marking Convention

I,

E

For the Am29xxxxx Enhanced-Vio device, the last digit of the

speed indicator specifies Vio range. Speed grades ending in

3 (e.g. 93, 103, etc.) indicate a 3 Volt Vio range; speed grades

ending in 8 (e.g. 98, 108, etc.) indicate a 1.8V Vio range.

100 ns

V_IO= 2.7 V –

3.6 V

PCE L640GL103P

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

August 28, 2002

Am29LV641GH/L / Am29LV640GU

9

A D V A N C E I N F O R M A T I O N

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Device Bus Operations

Addresses

(Note 2)

DQ15–

DQ0

Operation

CE#

OE# WE# RESET#

ACC

X

Read

L

H

L

H

A_IN

D_OUT

Write (Program/Erase)

Accelerated Program

X

(Note 4)

H

V_HH

V_CC

0.3 V

±

V_CC±

0.3 V

Standby

X

H

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z

X

SA, A6 = L,

A1 = H, A0 = L

Sector Group Protect (Note 2)

L

X

H

X

L

X

V_ID

X

(Note 4)

Sector Group Unprotect

(Note 2)

SA, A6 = H,

A1 = H, A0 = L

Temporary Sector Group

Unprotect

A_IN

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 11.5 –12.5 V, V_HH= 8.5 – 9.5 V, X = Don’t Care, SA = Sector Address,

A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A21:A0. Sector addresses are A21:A15.

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

3. All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version

ordered.)

4. D_INor D_OUTas required by command sequence, data polling, or sector protect algorithm (see Figure 2).

VersatileI/O (V_IO) Control

Requirements for Reading Array Data

The VersatileI/O (V_IO) control allows the host system

to set the voltage levels that the device generates at

its data outputs and the voltages tolerated at its data

inputs to the same voltage level that is asserted on the

V_IOpin. This allows the device to operate in 1.8 V or 3

V system environment as required.

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V_IH.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. The device remains

For example, a V_I/Oof 1.65–1.95 volts allows for I/O at

the 3 volt level, driving and receiving signals to and

from other 3 V devices on the same bus.

10

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

enabled for read access until the command register

contents are altered.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

See “Requirements for Reading Array Data” for more

information. Refer to the AC Read-Only Operations

table for timing specifications and to Figure 13 for the

timing diagram. I_CC1in the DC Characteristics table

represents the active current specification for reading

array data.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC± 0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_CC± 0.3 V, the device will be in the standby mode,

but the standby current will be greater. The device re-

quires standard access time (t_CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

The device features an Unlock Bypass mode to facil-

itate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word, instead of four. The “Word

Program Command Sequence” section has details on

programming data to the device using both standard

and Unlock Bypass command sequences.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

I_CC3in the DC Characteristics table represents the

standby current specification.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 indicates the address

space that each sector occupies.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

this mode when addresses remain stable for t_ACC+

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

I_CC4in the DC Characteristics table represents the

automatic sleep mode current specification.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This function is primarily in-

tended to allow faster manufacturing throughput dur-

ing system production.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

V_HHfrom the ACC pin returns the device to normal op-

eration. Note that the ACC pin must not be at V_HHfor

operations other than accelerated programming, or

device damage may result.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS±0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS±0.3 V, the standby current will

be greater.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

August 28, 2002

Am29LV641GH/L / Am29LV640GU

11

A D V A N C E I N F O R M A T I O N

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Table 2. Sector Address Table

8-bit Address Range

16-bit Address Range

(in hexadecimal)

Sector

SA0

A21

0

A20

0

A19

0

1

A18

0

1

0

1

A17

0

1

0

1

0

1

0

1

A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

(in hexadecimal)

000000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

000000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

12

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

Table 2. Sector Address Table (Continued)

8-bit Address Range

16-bit Address Range

(in hexadecimal)

Sector

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

A21

0

1

A20

0

1

0

A19

1

0

1

0

A18

1

0

1

0

1

0

A17

1

0

1

0

1

0

1

0

1

0

A16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(in hexadecimal)

1F0000–1FFFFF

200000–20FFFF

210000–21FFFF

220000–22FFFF

230000–23FFFF

240000–24FFFF

250000–25FFFF

260000–26FFFF

270000–27FFFF

280000–28FFFF

290000–29FFFF

2A0000–2AFFFF

2B0000–2BFFFF

2C0000–2CFFFF

2D0000–2DFFFF

2E0000–2EFFFF

2F0000–2FFFFF

300000–30FFFF

310000–31FFFF

320000–32FFFF

330000–33FFFF

340000–34FFFF

350000–35FFFF

360000–36FFFF

370000–37FFFF

380000–38FFFF

390000–39FFFF

3A0000–3AFFFF

3B0000–3BFFFF

3C0000–3CFFFF

3D0000–3DFFFF

3E0000–3EFFFF

3F0000–3FFFFF

400000–40FFFF

410000–41FFFF

0F8000–0FFFFF

100000–107FFF

108000–10FFFF

110000–117FFF

118000–11FFFF

120000–127FFF

128000–12FFFF

130000–137FFF

138000–13FFFF

140000–147FFF

148000–14FFFF

150000–157FFF

158000–15FFFF

160000–167FFF

168000–16FFFF

170000–177FFF

178000–17FFFF

180000–187FFF

188000–18FFFF

190000–197FFF

198000–19FFFF

1A0000–1A7FFF

1A8000–1AFFFF

1B0000–1B7FFF

1B8000–1BFFFF

1C0000–1C7FFF

1C8000–1CFFFF

1D0000–1D7FFF

1D8000–1DFFFF

1E0000–1E7FFF

1E8000–1EFFFF

1F0000–1F7FFF

1F8000–1FFFFF

200000–207FFF

208000–20FFFF

August 28, 2002

Am29LV641GH/L / Am29LV640GU

13

A D V A N C E I N F O R M A T I O N

Table 2. Sector Address Table (Continued)

8-bit Address Range

16-bit Address Range

(in hexadecimal)

Sector

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

A21

1

A20

0

1

A19

0

1

0

A18

0

1

0

1

0

A17

0

1

0

1

0

1

0

1

0

1

A16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

(in hexadecimal)

420000–42FFFF

430000–43FFFF

440000–44FFFF

450000–45FFFF

460000–46FFFF

470000–47FFFF

480000–48FFFF

490000–49FFFF

4A0000–4AFFFF

4B0000–4BFFFF

4C0000–4CFFFF

4D0000–4DFFFF

4E0000–4EFFFF

4F0000–4FFFFF

500000–50FFFF

510000–51FFFF

520000–52FFFF

530000–53FFFF

540000–54FFFF

550000–55FFFF

560000–56FFFF

570000–57FFFF

580000–58FFFF

590000–59FFFF

5A0000–5AFFFF

5B0000–5BFFFF

5C0000–5CFFFF

5D0000–5DFFFF

5E0000–5EFFFF

5F0000–5FFFFF

600000–60FFFF

610000–61FFFF

620000–62FFFF

630000–63FFFF

640000–64FFFF

210000–217FFF

218000–21FFFF

220000–227FFF

228000–22FFFF

230000–237FFF

238000–23FFFF

240000–247FFF

248000–24FFFF

250000–257FFF

258000–25FFFF

260000–267FFF

268000–26FFFF

270000–277FFF

278000–27FFFF

280000–287FFF

288000–28FFFF

290000–297FFF

298000–29FFFF

2A0000–2A7FFF

2A8000–2AFFFF

2B0000–2B7FFF

2B8000–2BFFFF

2C0000–2C7FFF

2C8000–2CFFFF

2D0000–2D7FFF

2D8000–2DFFFF

2E0000–2E7FFF

2E8000–2EFFFF

2F0000–2F7FFF

2F8000–2FFFFF

300000–307FFF

308000–30FFFF

310000–317FFF

318000–31FFFF

320000–327FFF

14

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

Table 2. Sector Address Table (Continued)

8-bit Address Range

16-bit Address Range

(in hexadecimal)

Sector

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

A21

1

A20

1

A19

0

1

A18

0

1

0

1

A17

1

0

1

0

1

0

1

A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(in hexadecimal)

650000–65FFFF

660000–66FFFF

670000–67FFFF

680000–68FFFF

690000–69FFFF

6A0000–6AFFFF

6B0000–6BFFFF

6C0000–6CFFFF

6D0000–6DFFFF

6E0000–6EFFFF

6F0000–6FFFFF

700000–70FFFF

710000–71FFFF

720000–72FFFF

730000–73FFFF

740000–74FFFF

750000–75FFFF

760000–76FFFF

770000–77FFFF

780000–78FFFF

790000–79FFFF

7A0000–7AFFFF

7B0000–7BFFFF

7C0000–7CFFFF

7D0000–7DFFFF

7E0000–7EFFFF

7F0000–7FFFFF

328000–32FFFF

330000–337FFF

338000–33FFFF

340000–347FFF

348000–34FFFF

350000–357FFF

358000–35FFFF

360000–367FFF

368000–36FFFF

370000–377FFF

378000–37FFFF

380000–387FFF

388000–38FFFF

390000–397FFF

398000–39FFFF

3A0000–3A7FFF

3A8000–3AFFFF

3B0000–3B7FFF

3B8000–3BFFFF

3C0000–3C7FFF

3C8000–3CFFFF

3D0000–3D7FFF

3D8000–3DFFFF

3E0000–3E7FFF

3E8000–3EFFFF

3F0000–3F7FFF

3F8000–3FFFFF

Note: All sectors are 32 Kwords in size.

August 28, 2002

Am29LV641GH/L / Am29LV640GU

15

A D V A N C E I N F O R M A T I O N

Table 3. In addition, when verifying sector protection,

Autoselect Mode

the sector address must appear on the appropriate

highest order address bits (see Table 2). Table 3

shows the remaining address bits that are don’t care.

When all necessary bits have been set as required,

the programming equipment may then read the corre-

sponding identifier code on DQ7–DQ0.

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be pro-

grammed with its corresponding programming

algorithm. However, the autoselect codes can also be

accessed in-system through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 10. This method

does not require V_ID. Refer to the Autoselect Com-

mand Sequence section for more information.

When using programming equipment, the autoselect

mode requires V_ID(11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Table 3. Am29LV641GH/L / Am29LV640GU Autoselect Codes, (High Voltage Method)

A22

to

A15

to

A8

to

A5

to

Description

CE# OE# WE# A16

A10 A9 A7 A6 A2 A1 A0

DQ7 to DQ0

Manufacturer ID: AMD

L

H

X

V_ID

X

L

X

L

01h

Device ID:

Am29LV641GH/L

L

H

V_ID

L

H

D7h

Am29LV640GU

Sector Protection

Verification

01h (protected),

00h (unprotected)

L

H

SA

X

V_ID

X

L

X

H

L

SecSi Sector Indicator Bit

(DQ7)

90h (factory locked),

10h (not factory locked)

H

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.

16

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

Table 4. Sector Group Protection/Unprotection

Address Table

Sector Group Protection and

Unprotection

Sector Group

A21–A17

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

The hardware sector group protection feature disables

both program and erase operations in any sector

group. In this device, a sector group consists of four

adjacent sectors that are protected or unprotected at

the same time (see Table 4). The hardware sector

group unprotection feature re-enables both program

and erase operations in previously protected sector

groups. Sector group protection/unprotection can be

implemented via two methods.

SA0–SA3

SA4–SA7

SA8–SA11

SA12–SA15

SA16–SA19

SA20–SA23

SA24–SA27

SA28–SA31

SA32–SA35

SA36–SA39

SA40–SA43

SA44–SA47

SA48–SA51

SA52–SA55

SA56–SA59

SA60–SA63

SA64–SA67

SA68–SA71

SA72–SA75

SA76–SA79

SA80–SA83

SA84–SA87

SA88–SA91

SA92–SA95

SA96–SA99

SA100–SA103

SA104–SA107

SA108–SA111

SA112–SA115

SA116–SA119

SA120–SA123

SA124–SA127

The primary method requires V_IDon the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 2 shows the algo-

rithms and Figure 22 shows the timing diagram. This

method uses standard microprocessor bus cycle tim-

ing. For sector group unprotect, all unprotected sector

groups must first be protected prior to the first sector

group unprotect write cycle.

The alternate method intended only for programming

equipment requires V_IDon address pin A9 and OE#.

This method is compatible with programmer routines

written for earlier 3.0 volt-only AMD flash devices.

Publication number 22367 contains further details;

contact an AMD representative to request a copy.

The device is shipped with all sector groups unpro-

tected. AMD offers the option of programming and

protecting sector groups at its factory prior to shipping

the device through AMD’s ExpressFlash™ Service.

Contact an AMD representative for details.

It is possible to determine whether a sector group is

protected or unprotected. See the Autoselect Mode

section for details.

Note: All sector groups are 128 Kwords in size.

August 28, 2002

Am29LV641GH/L / Am29LV640GU

17

A D V A N C E I N F O R M A T I O N

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting the first or last sector without

using V_ID.

START

If the system asserts V_ILon the WP# pin, the device

disables program and erase functions in the first or

last sector independently of whether those sectors

were protected or unprotected using the method de-

scribed in “Sector Group Protection and Unprotection”.

Note that if WP# is at V_ILwhen the device is in the

standby mode, the maximum input load current is in-

creased. See the table in “DC Characteristics”.

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

If the system asserts V_IHon the WP# pin, the device

reverts to whether the first or last sector was previ-

ously set to be protected or unprotected using the

method described in “Sector Group Protection and Un-

protection”.

Temporary Sector

Group Unprotect

Completed (Note 2)

Temporary Sector Group Unprotect

(Note: In this device, a sector group consists of four adjacent

sectors that are protected or unprotected at the same time

(see Table 4)).

Notes:

1. All protected sector groups unprotected (If WP# = V_IL,

the first or last sector will remain protected).

This feature allows temporary unprotection of previ-

ously protected sector groups to change data in-sys-

tem. The Sector Group Unprotect mode is activated by

setting the RESET# pin to V_ID(11.5 V – 12.5 V). Dur-

ing this mode, formerly protected sector groups can be

programmed or erased by selecting the sector group

addresses. Once V_IDis removed from the RESET#

pin, all the previously protected sector groups are

protected again. Figure 1 shows the algorithm, and

Figure 21 shows the timing diagrams, for this feature.

2. All previously protected sector groups are protected

once again.

Figure 1. Temporary Sector Group

Unprotect Operation

18

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

START

PLSCNT = 1

Protect all sector

groups: The indicated

portion of the sector

group protect algorithm

must be performed for all

unprotected sector

groups prior to issuing

the first sector group

unprotect address

RESET# = V_ID

Wait 1 µs

Temporary Sector

Group Unprotect

Mode

Temporary Sector

Group Unprotect

Mode

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Yes

Set up sector

group address

All sector

groups

No

protected?

Sector Group Protect:

Write 60h to sector

group address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

group address

Sector Group

Unprotect:

Wait 150 µs

Write 60h to sector

group address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector Group

Protect: Write 40h

to sector group

address twith A6 = 0,

A1 = 1, A0 = 0

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

Verify Sector Group

Unprotect: Write

40h to sector group

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector group address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector group

address with A6 = 1,

A1 = 1, A0 = 0

Data = 01h?

Yes

No

Yes

Set up

next sector group

address

Protect

another

sector group?

Yes

No

PLSCNT

= 1000?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

Last sector

group

verified?

No

Device failed

Write reset

command

Yes

Remove V_ID

from RESET#

Sector Group

Unprotect

Sector Group

Protect

Sector Group

Protect complete

Write reset

command

Algorithm

Sector Group

Unprotect complete

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

Am29LV641GH/L / Am29LV640GU

August 28, 2002

19

A D V A N C E I N F O R M A T I O N

device has an 8-word random ESN at addresses

SecSi (Secured Silicon) Sector Flash

Memory Region

000000h–000007h.

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service. The de-

vices are then shipped from AMD’s factory with the

SecSi Sector permanently locked. Contact an AMD

representative for details on using AMD’s Express-

Flash service.

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 128 words in length, and

uses a SecSi Sector Indicator Bit (DQ7) to indicate

whether or not the SecSi Sector is locked when

shipped from the factory. This bit is permanently set at

the factory and cannot be changed, which prevents

cloning of a factory locked part. This ensures the secu-

rity of the ESN once the product is shipped to the field.

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

As an alternative to the factory-locked version, the de-

vice may be ordered such that the customer may pro-

gram and protect the 128-word SecSi sector.

Programming and protecting the SecSi Sector must be

used with caution since, once protected, there is no

procedure available for unprotecting the SecSi Sector

area and none of the bits in the SecSi Sector memory

space can be modified in any way.

AMD offers the device with the SecSi Sector either

factory locked or customer lockable. The fac-

tory-locked version is always protected when shipped

from the factory, and has the SecSi (Secured Silicon)

Sector Indicator Bit permanently set to a “1.” The cus-

tomer-lockable version is shipped with the SecSi Sec-

tor unprotected, allowing customers to utilize that

sector in any manner they choose. The customer-lock-

able version also has the SecSi Sector Indicator Bit

permanently set to a “0.” Thus, the SecSi Sector Indi-

cator Bit prevents customer-lockable devices from

being used to replace devices that are factory locked.

The SecSi Sector area can be protected using one of

the following procedures:

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, ex-

cept that RESET# may be at either V_IHor V_ID. This

allows in-system protection of the SecSi Sector

without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

The SecSi sector address space in this device is allo-

cated as follows:

Table 5. SecSi Sector Contents

SecSi Sector

Address Range

Standard

Factory Locked Factory Locked

ExpressFlash

Customer

Lockable

Uniform Low*

000000h–000007h

Uniform High

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then use the alternate

method of sector protection described in the “Sector

Group Protection and Unprotection” section.

ESN or

determined by

customer

ESN

3FFFF8h-3FFFFFh

Determined by

customer

Uniform Low*

000008h–00007Fh

Uniform High

Determined by

customer

Unavailable

Once the SecSi Sector is programmed, locked and

verified, the system must write the Exit SecSi Sector

Region command sequence to return to reading and

writing within the remainder of the array.

3FFF80h-3FFFF7h

*All Uniform Devices (not including Uniform High) such as Am29LV640GU

has its Sector starting at address 0.

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi Sector/Exit

SecSi Sector Command Sequence”). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the ad-

dresses normally occupied by the first sector (SA0).

This mode of operation continues until the system is-

sues the Exit SecSi Sector command sequence, or

until power is removed from the device. On power-up,

or following a hardware reset, the device reverts to

sending commands to sector SA0.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 10 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

spurious system level signals during V_CCpower-up

and power-down transitions, or from system noise.

Low V_CCWrite Inhibit

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V_CCis greater than V_LKO. The

In devices with an ESN, the SecSi Sector is protected

when the device is shipped from the factory. The SecSi

Sector cannot be modified in any way. A factory locked

20

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

system must provide the proper signals to the control

pins to prevent unintentional writes when V_CCis

greater than V_LKO

CE# and WE# must be a logical zero while OE# is a

logical one.

.

Power-Up Write Inhibit

Write Pulse “Glitch” Protection

If WE# = CE# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

given in Tables 6–9. To terminate reading CFI data,

the system must write the reset command.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 6–9. The

system must write the reset command to return the de-

vice to reading array data.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the

World Wide Web at http://www.amd.com/prod-

ucts/nvd/overview/cfi.html. Alternatively, contact an

AMD representative for copies of these documents.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h, any time the device is ready to read array data.

The system can read CFI information at the addresses

Table 6. CFI Query Identification String

Description

Addresses (x16)

Data

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

Primary OEM Command Set

13h

14h

0002h

0000h

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

0000h

August 28, 2002

Am29LV641GH/L / Am29LV640GU

21

A D V A N C E I N F O R M A T I O N

Table 7. System Interface String

Description

Addresses (x16)

Data

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

0027h

V

_CCMax. (write/erase)

1Ch

0036h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0003h

0000h

000Ah

0000h

0005h

0000h

0002h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 8. Device Geometry Definition

Description

Addresses (x16)

Data

27h

0017h

Device Size = 2^Nbyte

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ch

0001h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

007Fh

0000h

0001h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

0000h

Erase Block Region 2 Information (refer to CFI publication 100)

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

35h

36h

37h

38h

0000h

39h

3Ah

3Bh

3Ch

0000h

22

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

Table 9. Primary Vendor-Specific Extended Query

Addresses (x16)

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

0004h

Silicon Revision Number (Bits 5-2)

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

0002h

0004h

0001h

0004h

0000h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

04 = 29LV800 mode

Simultaneous Operation

00 = Not Supported, X = Number of Sectors in Bank

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

0085h

0095h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

00h = Uniform sector device

4Fh

50h

00XXh

01h

04h = Uniform sector with bottom WP# protect

05h = Uniform sector with top WP# protect

Program Suspend

00h = Not Supported, 01h = Supported

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 10 defines the valid register command

sequences. Writing incorrect address and data val-

ues or writing them in the improper sequence resets

the device to reading array data.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the AC Characteristics section for timing

diagrams.

After the device accepts an Erase Suspend command,

the device enters the erase-suspend-read mode, after

which the system can read data from any

non-erase-suspended sector. After completing a pro-

gramming operation in the Erase Suspend mode, the

system may once again read array data with the same

August 28, 2002

Am29LV641GH/L / Am29LV640GU

23

A D V A N C E I N F O R M A T I O N

exception. See the Erase Suspend/Erase Resume

Commands section for more information.

autoselect command may not be written while the de-

vice is actively programming or erasing.

The system must issue the reset command to return

the device to the read (or erase-suspend-read) mode

if DQ5 goes high during an active program or erase

operation, or if the device is in the autoselect mode.

See the next section, Reset Command, for more infor-

mation.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the autoselect command. The

device then enters the autoselect mode. The system

may read at any address any number of times without

initiating another autoselect command sequence:

See also Requirements for Reading Array Data in the

Device Bus Operations section for more information.

The Read-Only Operations table provides the read pa-

rameters, and Figure 13 shows the timing diagram.

■ A read cycle at address XX00h returns the manu-

facturer code.

■ A read cycle at address XX01h returns the device

code.

■ A read cycle to an address containing a sector

group address (SA), and the address 02h on A7–A0

in word mode returns 01h if the sector group is pro-

tected, or 00h if it is unprotected. (Refer to Table 4

for valid sector addresses).

Reset Command

Writing the reset command resets the device to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to the read

mode. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the de-

vice was previously in Erase Suspend).

Enter SecSi Sector/Exit SecSi Sector

Command Sequence

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device to

the read mode. If the program command sequence is

written while the device is in the Erase Suspend mode,

writing the reset command returns the device to the

erase-suspend-read mode. Once programming be-

gins, however, the device ignores reset commands

until the operation is complete.

The SecSi Sector region provides a secured data area

containing an 8-word random Electronic Serial Num-

ber (ESN). The system can access the SecSi Sector

region by issuing the three-cycle Enter SecSi Sector

command sequence. The device continues to access

the SecSi Sector region until the system issues the

four-cycle Exit SecSi Sector command sequence. The

Exit SecSi Sector command sequence returns the de-

vice to normal operation. Table 10 shows the address

and data requirements for both command sequences.

See also “SecSi (Secured Silicon) Sector Flash

Memory Region” for further information.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If the de-

vice entered the autoselect mode while in the Erase

Suspend mode, writing the reset command returns the

device to the erase-suspend-read mode.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 10 shows the address

and data requirements for the word program com-

mand sequence.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to the

read mode (or erase-suspend-read mode if the device

was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

Table 10 shows the address and data requirements.

This method is an alternative to that shown in Table 3,

which is intended for PROM programmers and re-

quires V_IDon address pin A9. The autoselect com-

mand sequence may be written to an address that is

either in the read or erase-suspend-read mode. The

When the Embedded Program algorithm is complete,

the device then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7 or DQ6. Refer to the Write Operation Status sec-

tion for information on these status bits.

24

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

Any commands written to the device during the Em-

Figure 3 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 15 for timing diagrams.

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once the device has returned to the read

mode, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause the device to set DQ5 = 1, or cause the DQ7

and DQ6 status bits to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a

“0” to a “1.”

START

Write Program

Command Sequence

Data Poll

from System

Unlock Bypass Command Sequence

Embedded

The unlock bypass feature allows the system to pro-

gram words to the device faster than using the stan-

dard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write

cycle containing the unlock bypass command, 20h.

The device then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

with the initial two unlock cycles required in the stan-

dard program command sequence, resulting in faster

total programming time. Table 10 shows the require-

ments for the command sequence.

Program

algorithm

in progress

Verify Data?

No

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 10 for program command sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h. The second cycle must contain the data 00h. The

device then returns to the read mode.

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 10

shows the address and data requirements for the chip

erase command sequence.

The device offers accelerated program operations

through the ACC pin. When the system asserts V_HHon

the ACC pin, the device automatically enters the Un-

lock Bypass mode. The system may then write the

two-cycle Unlock Bypass program command se-

quence. The device uses the higher voltage on the

ACC pin to accelerate the operation. Note that the

ACC pin must not be at V_HHfor operations other than

accelerated programming, or device damage may re-

sult.

August 28, 2002

Am29LV641GH/L / Am29LV640GU

25

A D V A N C E I N F O R M A T I O N

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses

are no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing sector. The system can de-

termine the status of the erase operation by reading

DQ7, DQ6, or DQ2 in the erasing sector. Refer to the

Write Operation Status section for information on

these status bits.

device returns to the read mode and addresses are no

longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6 or DQ2.

Refer to the Write Operation Status section for infor-

mation on these status bits.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once the device has returned to reading

array data, to ensure data integrity.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 17 section for timing diagrams.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 17 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 10 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

Erase Suspend/Erase Resume

Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. This command is valid only during the

sector erase operation, including the 50 µs time-out

period during the sector erase command sequence.

The Erase Suspend command is ignored if written dur-

ing the chip erase operation or Embedded Program

algorithm.

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation.

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise erasure may begin. Any sector erase

address and command following the exceeded

time-out may or may not be accepted. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector

Erase command is written. Any command other than

Sector Erase or Erase Suspend during the

time-out period resets the device to the read

mode. The system must rewrite the command se-

quence and any additional addresses and commands.

After the erase operation has been suspended, the

device enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors pro-

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

Refer to the Write Operation Status section for infor-

mation on these status bits.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

After an erase-suspended program operation is com-

plete, the device returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard word program operation.

26

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

Refer to the Write Operation Status section for more

information.

After the Program Resume command is written, the

device reverts to programming. The system can deter-

mine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard pro-

gram operation.

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. Refer to the

Autoselect Mode and Autoselect Command Sequence

sections for details.

The system must write the Program Resume com-

mand (address bits are “don’t care”) to exit the Pro-

gram Suspend mode and continue the programming

operation. Further writes of the Resume command are

ignored. Another Program Suspend command can be

written after the device has resume programming.

To resume the sector erase operation, the system

must write the Erase Resume command. The address

of the erase-suspended sector is required when writ-

ing this command. Further writes of the Resume com-

mand are ignored. Another Erase Suspend command

can be written after the chip has resumed erasing.

Program Suspend/Program Resume

Commands

START

The Program Suspend command, B0h, allows the sys-

tem to interrupt a programming operation so that data

can be read from a non-suspended sector. When the

Program Suspend command is written during a pro-

gramming process, the device halts the program oper-

ation within 1 microsecond and updates the status

bits. Addresses are “don’t cares” when writing the Pro-

gram Suspend command.

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Embedded

After the programming operation has been sus-

pended, the system can read array data from any

non-suspended sector. The Program Suspend com-

mand can also be issued during a programming oper-

ation while an erase is suspended. In this case, data

may be read from any addresses not in Erase Sus-

pend or Program Suspend. If a read is needed from

the SecSi Sector area, then the user must use the

proper command sequences to enter or exit this re-

gion.

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

The system may also write the autoselect command

sequence when the device is in Program Suspend

mode. The device allows reading autoselect codes in

suspended sectors, since the codes are not stored in

the memory array. When the device exits the autose-

lect mode, the device reverts to Program Suspend

mode, and is ready for another valid operation. See

“Autoselect Command Sequence” for more informa-

tion.

Notes:

1. See Table 10 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 4. Erase Operation

August 28, 2002

Am29LV641GH/L / Am29LV640GU

27

A D V A N C E I N F O R M A T I O N

Command Definitions

Table 10. Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Sixth

Addr Data Addr Data

Data

Addr

Data

Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

Manufacturer ID

Device ID

1

4

RA

XXX

555

RD

F0

AA

2AA

55

555

90

X00

X01

0001

22D7

SecSi Sector Factory

Protect (Note 9)

(see

Note 9)

4

555

AA

2AA

55

555

90

X03

Sector Group Protect Verify

(Note 10)

XX00/

XX01

90 (SA)X02

88

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

3

4

3

555

AA

2AA

55

555

90

A0

20

XXX

PA

00

PD

Unlock Bypass

Unlock Bypass Program (Note 11)

XXX

A0

PA

PD

2

Unlock Bypass Reset (Note 12)

Chip Erase

XXX

555

90

AA

XXX

2AA

00

55

2

6

555

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Erase Suspend/Program Suspend

(Note 13)

1

BA

B0

Erase Resume/Program Resume

(Note 14)

1

BA

55

30

98

CFI Query (Note 15)

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A21–A15 uniquely select any sector.

latch on the falling edge of the WE# or CE# pulse, whichever happens

later.

Notes:

1. See Table 1 for description of bus operations.

9. If WP# protects the highest address sector, the data is 98h for

factory locked and 18h for not factory locked. If WP# protects the

lowest address sector, the data is 88h for factory locked and 08h

for not factor locked.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

10. The data is 00h for an unprotected sector group and 01h for a

protected sector group.

4. Data bits DQ15–DQ8 are don’t care in command sequences,

except for RD and PD.

11. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

5. Unless otherwise noted, address bits A21–A15 are don’t cares.

6. No unlock or command cycles required when device is in read

mode.

12. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

7. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when the device is in the autoselect mode, or if DQ5 goes high

(while the device is providing status information).

13. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation. The Program Suspend command is also valid during

Erase Suspend.

8. The fourth cycle of the autoselect command sequence is a read

cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect

Command Sequence section for more information.

14. The Erase Resume and Program Resume commands are valid

only during the Erase Suspend and Program Suspend modes.

15. Command is valid when device is ready to read array data or

when device is in autoselect mode.

16. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state.

The system must write a reset command to return the device to

reading array data.

28

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

WRITE OPERATION STATUS

The device provides several bits to determine the status of

a program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 11 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method

for determining whether a program or erase operation is

complete or in progress.

in the AC Characteristics section shows the Data#

Polling timing diagram.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether the device is in Erase

Suspend. Data# Polling is valid after the rising edge of the

final WE# pulse in the command sequence.

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, then the device returns to the

read mode.

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then

the device returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ6–DQ0 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ6–DQ0 may be still

invalid. Valid data on DQ7–DQ0 will appear on suc-

cessive read cycles.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

Table 11 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm. Figure 18

August 28, 2002

Am29LV641GH/L / Am29LV640GU

29

A D V A N C E I N F O R M A T I O N

program or erase operation), and during the sector

erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

START

Read DQ7–DQ0

After an erase command sequence is written, if all sectors

selected for erasing are protected, DQ6 toggles for approxi-

mately 100 µs, then returns to reading array data. If not all

selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

Read DQ7–DQ0

No

Toggle Bit

= Toggle?

The system can use DQ6 and DQ2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), DQ6 toggles. When the de-

vice enters the Erase Suspend mode, DQ6 stops toggling.

However, the system must also use DQ2 to determine

which sectors are erasing or erase-suspended. Alterna-

tively, the system can use DQ7 (see the subsection on

DQ7: Data# Polling).

Yes

No

DQ5 = 1?

Yes

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

Read DQ7–DQ0

Twice

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

Toggle Bit

= Toggle?

No

Table 11 shows the outputs for Toggle Bit I on DQ6.

Figure 6 shows the toggle bit algorithm. Figure 19 in

the “AC Characteristics” section shows the toggle bit

timing diagrams. Figure 20 shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Figure 6. Toggle Bit Algorithm

Note: The system should recheck the toggle bit even if

DQ5 = “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

30

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

the toggle bit and DQ5 through successive read cy-

DQ2: Toggle Bit II

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 6).

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ5: Exceeded Timing Limits

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 11 to compare out-

puts for DQ2 and DQ6.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a “1,” indicating that the program

or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit

has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if the device was previ-

ously in the erase-suspend-program mode).

Figure 6 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the DQ6: Toggle Bit I subsection.

Figure 19 shows the toggle bit timing diagram. Figure

20 shows the differences between DQ2 and DQ6 in

graphical form.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the time between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also the Sector Erase Command

Sequence section.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

Table 11 shows the status of DQ3 relative to the other

status bits.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

August 28, 2002

Am29LV641GH/L / Am29LV640GU

31

A D V A N C E I N F O R M A T I O N

Table 11. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

Toggle

Not

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Program-

DQ7#

0

No toggle

Toggle

Not

0

Standard

Mode

Not

1

Program

Suspend

Mode

Program-

Suspended Sector

Allowed

Allowed Allowed

Allowed

Suspend-Read

Non-Program

Suspended Sector

Data

1

Data

0

Data

N/A

Data

Erase

No toggle

Toggle

Erase-

Suspended Sector

Non-Erase

Erase

Suspend

Mode

Suspend-Read

Data

0

Data

N/A

Data

N/A

1

0

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. Data are invalid for addresses in a Program Suspended Sector.

32

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

20 ns

with Power Applied . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

+0.8 V

V

_CC(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

–0.5 V

–2.0 V

V_IO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +5.5 V

ACC . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +9.5 V

A9, OE#, RESET#, and WP#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

20 ns

All other pins (Note 1) . . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Figure 7. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

See Figure 7. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 8.

20 ns

V_CC

+2.0 V

2. Minimum DC input voltage on pins A9, OE#, RESET#,

WP#, and ACC is –0.5 V. During voltage transitions, A9,

OE#, WP#, ACC, and RESET# may overshoot V_SSto

–2.0 V for periods of up to 20 ns. See Figure 7. Maximum

DC input voltage on pin A9 is +12.5 V which may

overshoot to +14.0 V for periods up to 20 ns. Maximum

DC input voltage on WP# is +9.5 V which may overshoot

to +12.0 V for periods up to 20 ns

V_CC

+0.5 V

2.0 V

20 ns

Figure 8. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not

implied.Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T_A) . . . . . . . . –55°C to +125°C

V_CCSupply Voltages

V_CCfor all devices . . . . . . . . . . . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

August 28, 2002

Am29LV641GH/L / Am29LV640GU

33

A D V A N C E I N F O R M A T I O N

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Input Load Current (Note 1)

Test Conditions

V_IN= V_SSto V_CC

Min

Typ

Max

Unit

,

I_LI

±1.0

µA

V_CC= V_{CC max}

A9, OE#, RESET# Input Load

Current

I_LIT

I_LO

V_CC= V_{CC max}; V_ID= 12.5 V

35

µA

V_OUT= V_SSto V_CC

,

Output Leakage Current

±1.0

V_CC= V_{CC max}

5 MHz

1 MHz

9

2

16

4

V_CCActive Read Current

(Notes 2, 3)

I_CC1

CE# = V_IL,OE# = V_IH

mA

I_CC2

I_CC3

I_CC4

I_CC5

V_CCActive Write Current (Notes 3, 4) CE# = V_IL,OE# = V_IH, WE# = V_IL

15

26

mA

µA

CE#, RESET# = V_CC± 0.3 V,

V_CCStandby Current (Note 3)

WP# = V_IH

0.2

5

V_CCReset Current (Note 3)

RESET# = V_SS± 0.3 V, WP# = V_IH

V_IH= V_CC± 0.3 V;

V_IL= V_SS± 0.3 V, WP# = V_IH

Automatic Sleep Mode (Notes 3, 5)

V_IL

V_IH

Input Low Voltage (Note 6)

Input High Voltage (Note 6)

–0.5

0.8

V

0.7 x V_CC

V_CC+ 0.3

Voltage for ACC Program

Acceleration

V_HH

V_ID

V

_CC= 3.0 V ± 10%

8.5

9.5

V

VoltageforAutoselectandTemporary

Sector Unprotect

V_CC= 3.0 V ± 10%

11.5

12.5

0.45

V_OL

V_OH1

V_OH2

V_LKO

Output Low Voltage

I_OL= 4.0 mA, V_CC= V_{CC min}

_OH= –2.0 mA, V_CC= V_{CC min}

I_OH= –100 µA, V_CC= V_{CC min}

V

I

0.85 x V_IO

V_IO–0.4

2.3

Output High Voltage (Note 7)

Low V_CCLock-Out Voltage (Note 7)

2.5

Notes:

1. On the WP# pin only, the maximum input load current when WP# = V_ILis ± 5.0 µA.

2. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

3. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

4. I_CCactive while Embedded Erase or Embedded Program is in progress.

5. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns. Typical sleep mode current is

200 nA.

6. If V_IO< V_CC, maximum V_ILfor CE# is 0.3 x V_IO. If V_IO< V_CC, minimum V_IHfor CE# is 0.3 x V_IO.

7. Not 100% tested.

34

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

DC CHARACTERISTICS

Zero-Power Flash

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

12

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I_CC1vs. Frequency

Am29LV641GH/L / Am29LV640GU

August 28, 2002

35

A D V A N C E I N F O R M A T I O N

TEST CONDITIONS

Table 12. Test Specifications

3.3 V

Test Condition

Output Load

70

90, 100 Unit

1 TTL gate

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

100

pF

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

C

L

6.2 kΩ

0.0–3.0

Input timing measurement

reference levels (See Note)

1.5

V

Output timing measurement

reference levels

0.5 V_IO

Note: Diodes are IN3064 or equivalent

Figure 11. Test Setup

Note: If V_IO< V_CC, the reference level is 0.5 V_IO.

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

1.5 V

0.5 V_IOV

Input

Measurement Level

Output

0.0 V

Note: If V_IO< V_CC, the input measurement reference level is 0.5 V_IO.

Figure 12. Input Waveforms and

Measurement Levels

36

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std. Description

Test Setup

70

30

90

35

16

100

35

Unit

ns

t_RC

Read Cycle Time (Note 1)

Address to Output Delay

Min

t_AVQV

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_ACC

t_CE

t_OE

t_DF

CE#, OE# = V_ILMax

ns

Chip Enable to Output Delay

OE# = V_IL

Max

ns

Output Enable to Output Delay

ns

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

ns

t_DF

ns

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First

t_AXQX

t_OH

Min

0

ns

Read

Output Enable Hold

Time (Note 1)

t_OEH

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 12 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

Output Valid

HIGH Z

Outputs

RESET#

Figure 13. Read Operation Timings

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37

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

RESET# Pin Low (During Embedded Algorithms)

All Speed Options

Unit

t_Ready

Max

20

µs

to Read Mode (See Note)

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

RESET# Pulse Width

Min

500

50

ns

µs

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

t_RPD

20

Note: Not 100% tested.

CE#, OE#

t_RH

RESET#

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

CE#, OE#

RESET#

t_RP

Figure 14. Reset Timings

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August 28, 2002

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std.

t_WC

t_AS

Description

70

90

0

100

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Min

70

100

t_AVWL

ns

Address Setup Time to OE# low during toggle bit

polling

t_ASO

t_AH

Min

15

45

0

ns

t_WLAX

Address Hold Time

40

50

Address Hold Time From CE# or OE# high

during toggle bit polling

t_AHT

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

45

0

ns

Data Hold Time

t_OEPH

Output Enable High during toggle bit polling

20

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

t_WP

t_WPH

CE# Setup Time

Min

Typ

Min

0

ns

µs

sec

ns

µs

CE# Hold Time

Write Pulse Width

Write Pulse Width High

30

25

30

t_WHWH1

t_WHWH2

t_WHWH1Word Programming Operation (Note 2)

t_WHWH1Accelerated Word Programming Operation (Note 2)

t_WHWH2Sector Erase Operation (Note 2)

7

4

0.6

250

50

t_VHH

t_VCS

V_HHRise and Fall Time (Note 1)

V_CCSetup Time (Note 1)

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

August 28, 2002

Am29LV641GH/L / Am29LV640GU

39

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

Data

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 15. Program Operation Timings

V_HH

V_ILor V_IH

ACC

t_VHH

Figure 16. Accelerated Program Timing Diagram

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Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

V_CC

Complete

55h

30h

Progress

10 for Chip Erase

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.

2. These waveforms are for the word mode.

Figure 17. Chip/Sector Erase Operation Timings

August 28, 2002

Am29LV641GH/L / Am29LV640GU

41

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

t_RC

Addresses

VA

t_ACC

t_CE

VA

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ6–DQ0

Valid Data

Status Data

True

Status Data

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 18. Data# Polling Timings

(During Embedded Algorithms)

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Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle

Figure 19. Toggle Bit Timings

(During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 20. DQ2 vs. DQ6

August 28, 2002

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

t_VIDR

V_IDRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

4

µs

Note: Not 100% tested.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

Figure 21. Temporary Sector Group Unprotect Timing Diagram

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Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Sector Group Protect or Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector Group Protect: 150 µs,

Sector Group Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 22. Sector Group Protect and Unprotect Timing Diagram

August 28, 2002

Am29LV641GH/L / Am29LV640GU

45

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

70

90

0

100

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

70

100

t_AVWL

t_ELAX

t_DVEH

t_EHDX

ns

t_AH

t_DS

t_DH

40

45

0

50

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

µs

CE# Pulse Width

CE# Pulse Width High

40

45

30

7

50

t_EHEL

t_CPH

t_WHWH1

t_WHWH1Word Programming Operation (Note 2)

Accelerated Word Programming Operation

(Note 2)

t_WHWH1

t_WHWH2

Notes:

t_WHWH1

Typ

4

µs

t_WHWH2Sector Erase Operation (Note 2)

0.6

sec

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

46

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. Waveforms are for the word mode.

Figure 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings

August 28, 2002

Am29LV641GH/L / Am29LV640GU

47

A D V A N C E I N F O R M A T I O N

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

Comments

Sector Erase Time

Chip Erase Time

0.6

50

4

Excludes 00h programming

prior to erasure (Note 4)

Excludes system level

overhead (Note 5)

Word Program Time

7

210

µs

Accelerated Word Program Time

Chip Program Time (Note 3)

Notes:

4

120

36

µs

29.4

sec

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 3.0 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

10 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

6

Max

7.5

12

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

Control Pin Capacitance

V_OUT= 0

V_IN= 0

8.5

7.5

pF

9

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

48

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS

FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 11 x 12 mm package

Dwg rev AF; 10/99

August 28, 2002

Am29LV641GH/L / Am29LV640GU

49

A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS

LAA064—64-Ball Fortified Ball Grid Array (Fortified BGA) 13 x 11 mm package

50

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard TSOP

)

Dwg rev AA; 10/99

Note: For reference only. BSC is an ANSI standard for Basic Space Centering.

51

Am29LV641GH/L / Am29LV640GU

August 28, 2002

A D V A N C E I N F O R M A T I O N

REVISION SUMMARY

Revision A (August 9, 2002)

Revision A + 1 (August 28, 2002)

Initial Release.

Ordering Information

Corrected order numbers and package markings.

Added Marking Convention explanation about En-

hanced-Vio markings.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

August 28, 2002

Am29LV641GH/L / Am29LV640GU

52


型号：	AM29LV641GH103EK
厂家：	SPANSION
描述：	Flash, 4MX16, 100ns, PDSO48, TSOP-48 光电二极管内存集成电路
文件：	总52页 (文件大小：1100K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29LV641GH103EK [SPANSION]

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