AM29PDL129H53VKF_技术文档

Am29PDL129H

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not available for designs. For new and current designs,

S29PL129J supersedes Am29PDL129H and is the factory-recommended migration path. Please refer

to the S29PL129J datasheet for specifications and ordering information. Availability of this document

is retained for reference and historical purposes only.

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that

originally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appro-

priate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number 26842 Revision B Amendment +3 Issue Date November 2, 2005

THIS PAGE LEFT INTENTIONALLY BLANK.

Am29PDL129H

128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode

Simultaneous Read/Write Flash Memory with Enhanced

VersatileIO^TMControl and Dual Chip Enable Inputs

This product has been retired and is not available for designs. For new and current designs, S29PL129J supersedes Am29PDL129H and is the factory-recom-

mended migration path. Please refer to the S29PL129J datasheet for specifications and ordering information. Availability of this document is retained for reference

and historical purposes only.

DISTINCTIVE CHARACTERISTICS

—

45 mA active read current

15 mA program/erase current

1 µA typical standby mode current

ARCHITECTURAL ADVANTAGES

■

128 Mbit Page Mode device

—

Page size of 8 words: Fast page read access from random

locations within the page

SOFTWARE FEATURES

Dual Chip Enable inputs

■

Software command-set compatible with JEDEC 42.4

standard

—

Two CE# inputs control selection of each half of the memory

space

Backward compatible with Am29F and Am29LV families

Single power supply operation

CFI (Common Flash Interface) complaint

—

Full Voltage range: 2.7 to 3.6 volt read, erase, and program

operations for battery-powered applications

Provides device-specific information to the system, allowing

host software to easily reconfigure for different Flash devices

Simultaneous Read/Write Operation

Erase Suspend / Erase Resume

—

Data can be continuously read from one bank while

executing erase/program functions in another bank

Zero latency switching from write to read operations

Suspends an erase operation to allow read or program

operations in other sectors of same bank

—

Unlock Bypass Program command

—

■

FlexBank Architecture

Reduces overall programming time when issuing multiple

program command sequences

—

4 separate banks, with up to two simultaneous operations

per device

—

Bank 1A: 48 Mbit (32 Kw x 96)

Bank 1B: 16 Mbit (4 Kw x 8 and 32 Kw x 31)

Bank 2A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)

HARDWARE FEATURES

■

Ready/Busy# pin (RY/BY#)

—

Provides a hardware method of detecting program or erase

cycle completion

—

Bank 2B: 48 Mbit (32 Kw x 96)

■

Enhanced VersatileI/O^TM(V_IO) Control

—

■

Hardware reset pin (RESET#)

Hardware method to reset the device to reading array data

WP#/ACC (Write Protect/Acceleration) input

Output voltage generated and input voltages tolerated on all

control inputs and I/Os is determined by the voltage on the

V_IOpin

—

At V_IL, hardware level protection for the first and last two 4K

word sectors.

At V_IH, allows removal of sector protection

At V_HH, provides accelerated programming in a factory

setting

—

V

_IOoptions at 1.8 V and 3 V I/O

SecSi^TM(Secured Silicon) Sector region

—

Up to 128 words accessible through a command sequence

Up to 64 factory-locked words

Up to 64 customer-lockable words

■

Persistent Sector Protection

—

A command sector protection method to lock combinations

of individual sectors and sector groups to prevent program or

erase operations within that sector

■

Both top and bottom boot blocks in one device

Manufactured on 0.13 µm process technology

20-year data retention at 125°C

—

Sectors can be locked and unlocked in-system at V_CClevel

Minimum 1 million erase cycle guarantee per sector

■

Password Sector Protection

—

A sophisticated sector protection method to lock

combinations of individual sectors and sector groups to

prevent program or erase operations within that sector using

a user-defined 64-bit password

PERFORMANCE CHARACTERISTICS

■

High Performance

—

Page access times as fast as 20 ns

Random access times as fast as 55 ns

Package options

—

80-ball Fine-pitch BGA

Multi Chip Packages (MCP)

■

Power consumption (typical values at 10 MHz)

Publication Number: 26842 Rev: B Amendment/ +3

Issue Date: November 2, 2005

GENERAL DESCRIPTION

The Am29PDL129H is a 128 Mbit, 3.0 volt-only Page Mode

and Simultaneous Read/Write Flash memory device orga-

nized as 8 Mwords. The device is offered in an 80-ball Fine-

pitch BGA package, and various multi-chip packages. The

word-wide data (x16) appears on DQ15-DQ0. This device

can be programmed in-system or in standard EPROM pro-

The device is entirely command set compatible with the

JEDEC 42.4 single-power-supply Flash standard. Com-

mands are written to the command register using standard

microprocessor write timing. Register contents serve as in-

puts to an internal state-machine that controls the erase and

programming circuitry. Write cycles also internally latch ad-

dresses and data needed for the programming and erase

operations. Reading data out of the device is similar to read-

ing from other Flash or EPROM devices.

grammers. A 12.0 V V is not required for write or erase op-

PP

erations.

The device offers fast page access times of 20 to 30 ns, with

corresponding random access times of 55 to 85 ns, respec-

tively, allowing high speed microprocessors to operate with-

out wait states. To eliminate bus contention the device has

separate chip enable (CE1#, CE2#), write enable (WE#) and

output enable (OE#) controls. Dual Chip Enables allow ac-

cess to two 64 Mbit partitions of the 128 Mbit memory space.

Device programming occurs by executing the program com-

mand sequence. The Unlock Bypass mode facilitates faster

programming times by requiring only two write cycles to pro-

gram data instead of four. Device erasure occurs by execut-

ing the erase command sequence.

The host system can detect whether a program or erase op-

eration is complete by reading the DQ7 (Data# Polling) and

DQ6 (toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data or ac-

cept another command.

Simultaneous Read/Write Operation with

Zero Latency

The Simultaneous Read/Write architecture provides simul-

taneous operation by dividing the memory space into 4

banks, which can be considered to be four separate memory

arrays as far as certain operations are concerned. The de-

vice can improve overall system performance by allowing a

host system to program or erase in one bank, then immedi-

ately and simultaneously read from another bank with zero

latency (with two simultaneous operations operating at any

one time). This releases the system from waiting for the

completion of a program or erase operation, greatly improv-

ing system performance.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data con-

tents of other sectors. The device is fully erased when

shipped from the factory.

Hardware data protection measures include a low V de-

CC

tector that automatically inhibits write operations during

power transitions. The hardware sector protection feature

disables both program and erase operations in any combina-

tion of sectors of memory. This can be achieved in-system or

via programming equipment.

The device can be organized in both top and bottom sector

configurations. The banks are organized as follows:

The Erase Suspend/Erase Resume feature enables the

user to put erase on hold for any period of time to read data

from, or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved. If a

read is needed from the SecSi Sector area (One Time Pro-

gram area) after an erase suspend, then the user must use

the proper command sequence to enter and exit this region.

Chip Enable Configuration

CE1# Control

CE2# Control

Bank 1A

48 Mbit (32 Kw x 96)

Bank 2A

16 Mbit (4 Kw x 8 and 32 Kw x 31)

Bank 1B

16 Mbit (4 Kw x 8 and 32 Kw x 31)

Bank 2B

48 Mbit (32 Kw x 96)

The device offers two power-saving features. When ad-

dresses have been stable for a specified amount of time, the

device enters the automatic sleep mode. The system can

also place the device into the standby mode. Power con-

sumption is greatly reduced in both these modes.

Page Mode Features

The page size is 8 words. After initial page access is accom-

plished, the page mode operation provides fast read access

speed of random locations within that page.

Standard Flash Memory Features

AMD’s Flash technology combined years of Flash memory

manufacturing experience to produce the highest levels of

quality, reliability and cost effectiveness. The device electri-

cally erases all bits within a sector simultaneously via

Fowler-Nordheim tunneling. The data is programmed using

hot electron injection.

The device requires a single 3.0 volt power supply (2.7 V

to 3.6 V or 2.7 V to 3.3 V) for both read and write functions.

Internally generated and regulated voltages are provided for

the program and erase operations.

Note: The next-generation S29PL129J will have a different bank configuration, as follows:

Chip Enable Configuration

CE1# Control

CE2# Control

Bank 1A

16 Mbit (4 Kw x 8 and 32 Kw x 31)

Bank 2A

48 Mbit (32 Kw x 96)

Bank 1B

48 Mbit (32 Kw x 96)

Bank 2B

16 Mbit (4 Kw x 8 and 32 Kw x 31)

2

Am29PDL129H

November 2, 2005

TABLE OF CONTENTS

Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Simultaneous Operation Block Diagram . . . . . . . 6

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10

Table 1. Am29PDL129H Device Bus Operations ...........................10

Random Read (Non-Page Read) ........................................... 10

Page Mode Read .................................................................... 10

Table 2. Page Select .......................................................................10

Simultaneous Operation ......................................................... 10

Table 3. Bank Select .......................................................................11

Table 4. Am29PDL129H Sector Architecture ..................................12

Table 5. Addresses .......................................................................19

Table 6. Autoselect Codes (High Voltage Method) ........................19

Table 7. Am29PDL129H Boot Sector/Sector Block Addresses for

Protection/Unprotection

PPB Lock Bit Status ..............................................................27

Table 14. Memory Array Command Definitions ............................. 28

Table 15. Sector Protection Command Definitions ........................ 29

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 30

Figure 6. Maximum Negative Overshoot Waveform ...................... 30

Figure 7. Maximum Positive Overshoot Waveform........................ 30

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 8. Test Setup, VIO = 2.7 – 3.6 V........................................ 32

Figure 9. Input Waveforms and Measurement Levels ................... 32

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

CE1#/CE2# Timing ................................................................. 33

Figure 10. Timing Diagram for Alternating Between CE1# and CE2#

Control............................................................................................ 33

Read-Only Operations ........................................................... 33

Figure 11. Read Operation Timings............................................... 34

Figure 12. Page Read Operation Timings...................................... 34

Hardware Reset (RESET#) .................................................... 35

Figure 13. Reset Timings............................................................... 35

Erase and Program Operations .............................................. 36

Figure 14. Program Operation Timings.......................................... 37

Figure 15. Accelerated Program Timing Diagram.......................... 37

Figure 16. Chip/Sector Erase Operation Timings .......................... 38

Figure 17. Back-to-back Read/Write Cycle Timings ...................... 39

Figure 18. Data# Polling Timings (During Embedded Algorithms). 39

Figure 19. Toggle Bit Timings (During Embedded Algorithms)...... 40

Figure 20. DQ2 vs. DQ6................................................................. 40

Temporary Sector Unprotect .................................................. 41

Figure 21. Temporary Sector Unprotect Timing Diagram .............. 41

Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram

42

CE1# Control ...................................................................................20

Table 8. Am29PDL129H Boot Sector/Sector Block Addresses for

Protection/Unprotection

CE2# Control ...................................................................................20

Table 9. Sector Protection Schemes ...............................................21

Write Protect (WP#) ................................................................ 21

Persistent Protection Bit Lock ................................................. 21

High Voltage Sector Protection .............................................. 21

Figure 1. ......................................................................................... 21

Temporary Sector Unprotect .................................................. 21

Figure 2. ......................................................................................... 21

Flash Memory Region ............................................................ 21

Factory-Locked Area (64 words) ............................................ 21

Customer-Lockable Area (64 words) ...................................... 22

Figure 3. SecSi Sector Protection Algorithm................................... 23

SecSi Sector Protection Bits ................................................... 24

Figure 4. SecSi Sector Protect Verify.............................................. 24

Common Flash Memory Interface (CFI) . . . . . . . 24

Command Definitions . . . . . . . . . . . . . . . . . . . . . 27

Enter /Exit Command Sequence ............................................ 27

Figure 5. ......................................................................................... 27

Alternate CE# Controlled Erase and Program Operations ..... 43

Figure 23. Alternate CE# Controlled Write (Erase/Program)

Operation Timings.......................................................................... 44

Erase And Programming Performance. . . . . . . . 45

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 45

BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 45

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46

November 2, 2005

Am29PDL129H

3

PRODUCT SELECTOR GUIDE

Part Number

Am29PDL129H

V

, V = 2.7–3.6 V

53

63

CC IO

Speed Option

= 2.7–3.6 V, V = 1.65–1.95 V

68

88

CC

IO

Max Access Time, ns (t

)

55

60

65

ACC

65

70

85

Max CE# Access, ns (t

)

CE

Max Page Access, ns (t

)

PACC

20

25

30

Max OE# Access, ns (t

)

OE

BLOCK DIAGRAM

DQ15–DQ0

RY/BY# (See Note)

V

CC

V

Sector

SS

Switches

V

IO

Input/Output

Buffers

RESET#

WE#

Erase Voltage

Generator

State

Control

Command

Register

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

CE1#

CE2#

OE#

Data Latch

Y-Gating

Y-Decoder

X-Decoder

V

Detector

Timer

CC

A21–A3

Cell Matrix

A2–A0

Note:RY/BY# is an open drain output.

4

Am29PDL129H

November 2, 2005

SIMULTANEOUS OPERATION BLOCK DIAGRAM

V

CC

SS

OE#

CE1#=L

CE2#=H

Mux

Bank 1A

Bank 1A Address

Bank 1B Address

A21–A0

X-Decoder

RY/BY#

Bank 1B

X-Decoder

A21–A0

RESET#

WE#

CE1#

STATE

CONTROL

&

Status

DQ15–DQ0

CE2#

COMMAND

REGISTER

Control

Mux

WP#/ACC

CE1#=H

CE2#=L

X-Decoder

Bank 2A

DQ0–DQ15

Bank 2A Address

Bank 2B Address

X-Decoder

Bank 2B

A21–A0

Mux

November 2, 2005

Am29PDL129H

5

CONNECTION DIAGRAMS

80-Ball Fine-pitch BGA

Top View, Balls Facing Down

A8

B8

C8

D8

E8

F8

G8

H8

J8

K8

L8

M8

NC

V_IO

V_SS

NC

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

NC

A13

A12

A14

A15

A16

NC

DQ15

V_SS

NC

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

WE# RESET#

A21

A19

DQ5

DQ12

V_CC

DQ4

C4 D4

E4

F4

G4

H4

J4

K4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

A2

B2

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

L2

M2

NC

CE1#

OE#

V_SS

NC

A1

B1

C1

D1

E1

F1

G1

H1

J1

K1

L1

M1

NC

CE2#

NC

V_IO

NC

Note: On S29PL129J, G1= NC and J1= CE2#

6

Am29PDL129H

November 2, 2005

the device is either executing an em-

bedded algorithm or the device is

executing a hardware reset opera-

tion.

PIN DESCRIPTION

A21–A0

=

22-bit address bus for 2 x 64 Mb de-

vice. A9 supports 12 V autoselect in-

puts.

WP#/ACC

=

Write Protect/Acceleration Input.

DQ15–DQ0 =

CE1#, CE2# =

16-bit data inputs/outputs/float

When WP/ACC#= V , the highest

IL

Chip Enable Inputs. CE1# controls

the 64 Mb in Banks 1A and 1B.

CE2# controls the 64 Mb in Banks

2A and 2B.

and lowest two 4K-word sectors are

write protected regardless of other

sector protection configurations.

When WP/ACC#= V , these sector

IH

are unprotected unless the DYB or

PPB is programmed. When WP/

ACC#= 12V, program and erase op-

erations are accelerated.

OE#

WE#

=

Output Enable Input

Write Enable

V

Device Ground

SS

V

=

Input/Output Buffer Power Supply

(1.65 V to 1.95 V or 2.7 V to 3.6 V)

IO

NC

Pin Not Connected Internally

Ready/Busy output and open drain.

RY/BY#

Chip Power Supply

(2.7 V to 3.6 V)

CC

When RY/BY#= V , the device is

IH

ready to accept read operations and

commands. When RY/BY#= V

,

RESET#

Hardware Reset Pin

OL

LOGIC SYMBOL

22

A21–A0

16

DQ15–DQ0

CE1#

CE2#

OE#

WE#

WP#/ACC

RESET#

RY/BY#

V

(V

)

CCQ

IO

November 2, 2005

Am29PDL129H

7

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29PDL129

H

53

VK

I

OPTIONAL PROCESSING

Blank = Standard Processing

N

=

16-byte ESN devices

(Contact an AMD representative for more information)

TEMPERATURE RANGE

I

=

Industrial (–40°C to +85°C)

PACKAGE TYPE

VK

=

80-Ball Fine-pitch Ball Grid Array

0.8 mm pitch, 11.5 x 9 mm package (VBB080)

SPEED OPTION

See Product Selector Guide and Valid Combinations

PROCESS TECHNOLOGY

H = 0.13 µm

DEVICE NUMBER/DESCRIPTION

Am29PDL129H

128 Megabit (8 M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Dual Chip Enable Inputs

Note: For the Am29PDL129H, the last digit of the speed grade

specifies the V_IOrange of the device. Speed grades ending in 3 (for

example: 53, 63) indicate a 3 Volt V_IOrange. Speed grades ending in 8

(for example: 68, 88) indicate a 1.8 Volt V_IOrange. Contact AMD or

Fujitsu for availability of 1.8V V_IOrange devices.

Valid Combinations

Valid Combinations list configurations planned to be supported in

volume for this device. Consult the local AMD sales office to con-

firm availability of specific valid combinations and to check on

newly released combinations.

Valid Combinations for BGA Packages

Speed

Order Number

Am29PDL129H53

Am29PDL129H63

Am29PDL129H68

Am29PDL129H88

Package Marking

(ns)

55

65

85

V_IORange

PD129H53V

2.7–3.6 V

PD129H63V

VKI

I

PD129H68V

1.65–1.95 V

PD129H88V

8

Am29PDL129H

November 2, 2005

DEVICE BUS OPERATIONS

Table 1. Am29PDL129H Device Bus Operations

Addresses

(A21–A0)

DQ15–

DQ0

Operation

CE1#

CE2#

OE#

WE#

RESET#

WP#/ACC

L

H

L

H

L

Read

L

H

X

A_IN

D_OUT

H

L

X

Write

H

X

L

H

A_IN

X

D_IN

(Note 2)

H

V_IO

0.3 V

±

V_IO

0.3 V

±

V_IO±

0.3 V

Standby

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z

X

Temporary Sector Unprotect (High

Voltage)

X

V_ID

X

A_IN

D_IN

Legend: L = Logic Low = V , H = Logic High = V , V = 11.5–12.5 V, V = 8.5–9.5 V, X = Don’t Care, SA = Sector Address,

IL

IH

ID

HH

A

= Address In, D = Data In, D

= Data Out

IN

OUT

Notes:

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. .

2. WP#/ACC must be high when writing to sectors SA1-133, SA1-134, SA2-0, or SA2-1.

Random Read (Non-Page Read)

Table 2. Page Select

Address access time (t

) is equal to the delay from

ACC

stable addresses to valid output data. The chip enable

Word

A2

0

A1

A0

0

access time (t ) is the delay from the stable ad-

CE

dresses and stable CE# to valid data at the output in-

puts. The output enable access time is the delay from

the falling edge of the OE# to valid data at the output

inputs (assuming the addresses have been stable for

Word 0

Word 1

Word 2

Word 3

Word 4

Word 5

Word 6

Word 7

0

1

0

1

0

1

0

at least t

–t time).

ACC OE

0

1

Page Mode Read

1

0

The device is capable of fast page mode read and is

compatible with the page mode Mask ROM read oper-

ation. This mode provides faster read access speed

for random locations within a page. Address bits A21–

A3 select an 8-word page, and address bits A2–A0 se-

lect a specific work within that page. This is an asyn-

chronous operation with the microprocessor supplying

the specific word location.

1

0

1

Simultaneous Operation

In addition to the conventional features (read, pro-

gram, erase-suspend read, and erase-suspend pro-

gram), the device is capable of reading data from one

bank of memory while a program or erase operation is

in progress in another bank of memory (simultaneous

operation), The bank can be selected by bank ad-

dresses (A21–A20) with zero latency.

The random or initial page access is t

subsequent page read accesses (as long as the loca-

tions specified by the microprocessor fall within that

or t and

CE

ACC

page) are t

. When CE1# and CE2# are deas-

PACC

serted (CE1#=CE2#=V ), the reassertion of CE1# or

IH

CE2# for subsequent access has access time of t

ACC

or t . Here again, CE1#/CE2# selects the device and

CE

The simultaneous operation can execute multi-func-

tion mode in the same bank.

OE# is the output control and should be used to gate

data to the output inputs if the device is selected. Fast

page mode accesses are obtained by keeping A21–

A3 constant and changing A2 to A0 to select the spe-

cific word within that page.

November 2, 2005

Am29PDL129H

9

Table 3. Bank Select

Bank 2A

Bank 2B

1

0

00

Bank

CE1#

CE2#

A21–A20

01, 10, 11

Bank 1A

Bank 1B

0

1

00, 01, 10

11

10

Am29PDL129H

November 2, 2005

Table 4. Am29PDL129H Sector Architecture

Sector Address (A21- Sector Size

Bank

Sector

CE1#

CE2#

Address Range (x16)

A12)

(Kwords)

32

SA1-0

SA1-1

0

1

0000000XXX

0000001XXX

0000010XXX

0000011XXX

0000100XXX

0000101XXX

0000110XXX

0000111XXX

0001000XXX

0001001XXX

0001010XXX

0001011XXX

0001100XXX

0001101XXX

0001110XXX

0001111XXX

0010000XXX

0010001XXX

0010010XXX

0010011XXX

0010100XXX

0010101XXX

0010110XXX

0010111XXX

0011000XXX

0011001XXX

0011010XXX

0011011XXX

0011100XXX

0011101XXX

0011110XXX

0011111XXX

0100000XXX

0100001XXX

0100010XXX

0100011XXX

0100100XXX

0100101XXX

000000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

SA1-2

SA1-3

SA1-4

SA1-5

SA1-6

SA1-7

SA1-8

SA1-9

SA1-10

SA1-11

SA1-12

SA1-13

SA1-14

SA1-15

SA1-16

SA1-17

SA1-18

SA1-19

SA1-20

SA1-21

SA1-22

SA1-23

SA1-24

SA1-25

SA1-26

SA1-27

SA1-28

SA1-29

SA1-30

SA1-31

SA1-32

SA1-33

SA1-34

SA1-35

SA1-36

SA1-37

November 2, 2005

Am29PDL129H

11

Table 4. Am29PDL129H Sector Architecture

Sector Address (A21- Sector Size

Bank

Sector

CE1#

CE2#

Address Range (x16)

A12)

(Kwords)

32

SA1-38

SA1-39

SA1-40

SA1-41

SA1-42

SA1-43

SA1-44

SA1-45

SA1-46

SA1-47

SA1-48

SA1-49

SA1-50

SA1-51

SA1-52

SA1-53

SA1-54

SA1-55

SA1-56

SA1-57

SA1-58

SA1-59

SA1-60

SA1-61

SA1-62

SA1-63

SA1-64

SA1-65

SA1-66

SA1-67

SA1-68

SA1-69

SA1-70

SA1-71

SA1-72

SA1-73

SA1-74

SA1-75

SA1-76

SA1-77

0

1

0100110XXX

0100111XXX

0101000XXX

0101001XXX

0101010XXX

0101011XXX

0101100XXX

0101101XXX

0101110XXX

0101111XXX

0110000XXX

0110001XXX

0110010XXX

0110011XXX

0110100XXX

0110101XXX

0110110XXX

0110111XXX

0111000XXX

0111001XXX

0111010XXX

0111011XXX

0111100XXX

0111101XXX

0111110XXX

0111111XXX

1000000XXX

1000001XXX

1000010XXX

1000011XXX

1000100XXX

1000101XXX

1000110XXX

1000111XXX

1001000XXX

1001001XXX

1001010XXX

1001011XXX

1001100XXX

1001101XXX

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

12

Am29PDL129H

November 2, 2005

Table 4. Am29PDL129H Sector Architecture

Sector Address (A21- Sector Size

Bank

Sector

CE1#

CE2#

Address Range (x16)

A12)

(Kwords)

SA1-78

SA1-79

SA1-80

SA1-81

SA1-82

SA1-83

SA1-84

SA1-85

SA1-86

SA1-87

SA1-88

SA1-89

SA1-90

SA1-91

SA1-92

SA1-93

SA1-94

SA1-95

0

1

1001110XXX

1001111XXX

1010000XXX

1010001XXX

1010010XXX

1010011XXX

1010100XXX

1010101XXX

1010110XXX

1010111XXX

1011000XXX

1011001XXX

1011010XXX

1011011XXX

1011100XXX

1011101XXX

1011110XXX

1011111XXX

32

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

32

November 2, 2005

Am29PDL129H

13

Table 4. Am29PDL129H Sector Architecture

Sector Address (A21- Sector Size

Bank

Sector

CE1#

CE2#

Address Range (x16)

A12)

(Kwords)

32

4

SA1-96

SA1-97

0

1

1100000XXX

1100001XXX

1100010XXX

1100011XXX

1100100XXX

1100101XXX

1100110XXX

1100111XXX

1101000XXX

1101001XXX

1101010XXX

1101011XXX

1101100XXX

1101101XXX

1101110XXX

1101111XXX

1110000XXX

1110001XXX

1110010XXX

1110011XXX

1110100XXX

1110101XXX

1110110XXX

1110111XXX

1111000XXX

1111001XXX

1111010XXX

1111011XXX

1111100XXX

1111101XXX

1111110XXX

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3F8FFFh

3F9000h–3F9FFFh

3FA000h–3FAFFFh

3FB000h–3FBFFFh

3FC000h–3FCFFFh

3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

SA1-98

SA1-99

SA1-100

SA1-101

SA1-102

SA1-103

SA1-104

SA1-105

SA1-106

SA1-107

SA1-108

SA1-109

SA1-110

SA1-111

SA1-112

SA1-113

SA1-114

SA1-115

SA1-116

SA1-117

SA1-118

SA1-119

SA1-120

SA1-121

SA1-122

SA1-123

SA1-124

SA1-125

SA1-126

SA1-127

SA1-128

SA1-129

SA1-130

SA1-131

SA1-132

SA1-133

SA1-134

4

14

Am29PDL129H

November 2, 2005

Table 4. Am29PDL129H Sector Architecture

Sector Address (A21- Sector Size

Bank

Sector

CE1#

CE2#

Address Range (x16)

A12)

(Kwords)

SA2-0

SA2-1

1

0

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

0000100XXX

0000101XXX

0000110XXX

0000111XXX

0001000XXX

0001001XXX

0001010XXX

0001011XXX

0001100XXX

0001101XXX

0001110XXX

0001111XXX

0010000XXX

0010001XXX

0010010XXX

0010011XXX

0010100XXX

0010101XXX

0010110XXX

0010111XXX

0011000XXX

0011001XXX

0011010XXX

0011011XXX

0011100XXX

0011101XXX

0011110XXX

0011111XXX

4

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

4

SA2-2

4

SA2-3

4

SA2-4

4

SA2-5

4

SA2-6

4

SA2-7

4

SA2-8

32

SA2-9

SA2-10

SA2-11

SA2-12

SA2-13

SA2-14

SA2-15

SA2-16

SA2-17

SA2-18

SA2-19

SA2-20

SA2-21

SA2-22

SA2-23

SA2-24

SA2-25

SA2-26

SA2-27

SA2-28

SA2-29

SA2-30

SA2-31

SA2-32

SA2-33

SA2-34

SA2-35

SA2-36

SA2-37

SA2-38

November 2, 2005

Am29PDL129H

15

Table 4. Am29PDL129H Sector Architecture

Sector Address (A21- Sector Size

Bank

Sector

CE1#

CE2#

Address Range (x16)

A12)

(Kwords)

32

SA2-39

SA2-40

SA2-41

SA2-42

SA2-43

SA2-44

SA2-45

SA2-46

SA2-47

SA2-48

SA2-49

SA2-50

SA2-51

SA2-52

SA2-53

SA2-54

SA2-55

SA2-56

SA2-57

SA2-58

SA2-59

SA2-60

SA2-61

SA2-62

SA2-63

SA2-64

SA2-65

SA2-66

SA2-67

SA2-68

SA2-69

SA2-70

SA2-71

SA2-72

SA2-73

SA2-74

SA2-75

SA2-76

SA2-77

SA2-78

1

0

0100000XXX

0100001XXX

0100010XXX

0100011XXX

0100100XXX

0100101XXX

0100110XXX

0100111XXX

0101000XXX

0101001XXX

0101010XXX

0101011XXX

0101100XXX

0101101XXX

0101110XXX

0101111XXX

0110000XXX

0110001XXX

0110010XXX

0110011XXX

0110100XXX

0110101XXX

0110110XXX

0110111XXX

0111000XXX

0111001XXX

0111010XXX

0111011XXX

0111100XXX

0111101XXX

0111110XXX

0111111XXX

1000000XXX

1000001XXX

1000010XXX

1000011XXX

1000100XXX

1000101XXX

1000110XXX

1000111XXX

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

16

Am29PDL129H

November 2, 2005

Table 4. Am29PDL129H Sector Architecture

Sector Address (A21- Sector Size

Bank

Sector

CE1#

CE2#

Address Range (x16)

A12)

(Kwords)

32

SA2-79

SA2-80

SA2-81

SA2-82

SA2-83

SA2-84

SA2-85

SA2-86

SA2-87

SA2-88

SA2-89

SA2-90

SA2-91

SA2-92

SA2-93

SA2-94

SA2-95

SA2-96

SA2-97

SA2-98

SA2-99

SA2-100

SA2-101

SA2-102

SA2-103

SA2-104

SA2-105

SA2-106

SA2-107

SA2-108

SA2-109

SA2-110

SA2-111

SA2-112

SA2-113

SA2-114

SA2-115

SA2-116

SA2-117

SA2-118

1

0

1001000XXX

1001001XXX

1001010XXX

1001011XXX

1001100XXX

1001101XXX

1001110XXX

1001111XXX

1010000XXX

1010001XXX

1010010XXX

1010011XXX

1010100XXX

1010101XXX

1010110XXX

1010111XXX

1011000XXX

1011001XXX

1011010XXX

1011011XXX

1011100XXX

1011101XXX

1011110XXX

1011111XXX

1100000XXX

1100001XXX

1100010XXX

1100011XXX

1100100XXX

1100101XXX

1100110XXX

1100111XXX

1101000XXX

1101001XXX

1101010XXX

1101011XXX

1101100XXX

1101101XXX

1101110XXX

1101111XXX

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

November 2, 2005

Am29PDL129H

17

Table 4. Am29PDL129H Sector Architecture

Sector Address (A21- Sector Size

Bank

Sector

CE1#

CE2#

Address Range (x16)

A12)

(Kwords)

SA2-119

SA2-120

SA2-121

SA2-122

SA2-123

SA2-124

SA2-125

SA2-126

SA2-127

SA2-128

SA2-129

SA2-130

SA2-131

SA2-132

SA2-133

1

0

1110000XXX

1110001XXX

1110010XXX

1110011XXX

1110100XXX

1110101XXX

1110110XXX

1110111XXX

1111000XXX

1111001XXX

1111010XXX

1111011XXX

1111100XXX

1111101XXX

1111110XXX

1111111XXX

32

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3FFFFFh

32

SA2-134

1

32

Table 5.

Addresses

Sector Size

Address Range

Am29PDL129H

128 words

64 words

000000h–00007Fh

000000h-00003Fh

000040h-00007Fh

Factory-Locked Area

Customer-Lockable Area

Table 6. Autoselect Codes (High Voltage Method)

A21

to

A12

A5

to

A4

DQ15

to DQ0

Description

CE1#

CE2#

H

OE#

WE#

A10

A9

A8

A7

A6

A3

A2

A1

A0

L

H

L

Manufacturer ID:

AMD

V_ID

L

H

X

L

X

L

H

L

0001h

L

H

Read

Cycle 1

L

H

L

H

L

227Eh

2221h

2200h

H

L

H

Read

Cycle 2

V_ID

L

H

X

L

H

L

H

Read

Cycle 3

H

L

H

L

H

Sector Protection

Verification

0001h (protected),

0000h (unprotected)

V_ID

L

H

SA

X

L

H

L

H

00C0h (factory and

customer locked),

0080h (factory

locked)

Indicator Bit

(DQ7, DQ6)

V_ID

X

L

H

L

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, BA = Bank Address, SA = Sector Address, X = Don’t care. Note: The autoselect codes may also

be accessed in-system via command sequences

Table 7. Am29PDL129H Boot Sector/Sector Block

Addresses for Protection/Unprotection

CE1# Control

Sector

Group

Sector/Sector Block

Size

A21-12

SA1-0–SA1-3

00000XXXXX

128 (4x32) Kwords

18

Am29PDL129H

November 2, 2005

Table 8. Am29PDL129H Boot Sector/Sector Block

Addresses for Protection/Unprotection

CE2# Control

Sector

Group

Sector/Sector Block

Size

A21-12

SA1-4–SA1-7

SA1-8–SA1-11

SA1-12–SA1-15

SA1-16–SA1-19

SA1-20–SA1-23

SA1-24–SA1-27

SA1-28–SA1-31

SA1-32–SA1-35

SA1-36–SA1-39

SA1-40–SA1-43

SA1-44–SA1-47

SA1-48–SA1-51

SA1-52–SA1-55

SA1-56–SA1-59

SA1-60–SA1-63

SA1-64–SA1-67

SA1-68–SA1-71

SA1-72–SA1-75

SA1-76–SA1-79

SA1-80–SA1-83

SA1-84–SA1-87

SA1-88–SA1-91

SA1-92–SA1-95

SA1-96–SA1-99

SA1-100–SA1-103

SA1-104–SA1-107

SA1-108–SA1-111

SA1-112–SA1-115

SA1-116–SA1-119

SA1-120–SA1-123

SA1-124

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

1111100XXX

1111101XXX

1111110XXX

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

128 (4x32) Kwords

32 Kwords

Sector

Group

Sector/Sector Block

Size

A21-12

SA2-0

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

11111XXXXX

4 Kwords

SA2-1

4 Kwords

SA2-2

4 Kwords

SA2-3

4 Kwords

SA2-4

4 Kwords

SA2-5

4 Kwords

SA2-6

4 Kwords

SA2-7

4 Kwords

SA2-8

32 Kwords

SA2-9

32 Kwords

SA2-10

32 Kwords

SA2-11 - SA2-14

SA2-15 - SA2-18

SA2-19 - SA2-22

SA2-23 - SA2-26

SA2-27 - SA2-30

SA2-31 - SA2-34

SA2-35 - SA2-38

SA2-39 - SA2-42

SA2-43 - SA2-46

SA2-47 - SA2-50

SA2-51 - SA2-54

SA2-55 - SA2-58

SA2-59 - SA2-62

SA2-63 - SA2-66

SA2-67 - SA2-70

SA2-71 - SA2-74

SA2-75 - SA2-78

SA2-79 - SA2-82

SA2-83 - SA2-86

SA2-87 - SA2-90

SA2-91 - SA2-94

SA2-95 - SA2-98

SA2-99 - SA2-102

SA2-103 - SA2-106

SA2-107 - SA2-110

SA2-111 - SA2-114

SA2-115 - SA2-118

SA2-119 - SA2-122

SA2-123 - SA2-126

SA2-127 - SA2-130

SA2-131 - SA2-134

128 (4x32) Kwords

SA1-125

32 Kwords

SA1-126

32 Kwords

SA1-127

4 Kwords

SA1-128

4 Kwords

SA1-129

4 Kwords

SA1-130

4 Kwords

SA1-131

4 Kwords

SA1-132

4 Kwords

SA1-133

4 Kwords

SA1-134

4 Kwords

November 2, 2005

Am29PDL129H

19

Selecting a Sector Protection Mode

Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile

bit that reflects the state of the Password Mode Lock-

ing Bit after power-up reset. If the Password Mode

Lock Bit is also set after a hardware reset (RESET#

asserted) or a power-up reset, the ONLY means for

clearing the PPB Lock Bit in Password Protection

Mode is to issue the Password Unlock command. Suc-

cessful execution of the Password Unlock command

clears the PPB Lock Bit, allowing for sector PPBs

modifications. Asserting RESET#, taking the device

through a power-on reset, or issuing the PPB Lock Bit

Set command sets the PPB Lock Bit to a “1” when the

Password Mode Lock Bit is not set.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at the factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possible to determine whether a sector is pro-

tected or unprotected. See Autoselect Mode for de-

tails.

Table 9. Sector Protection Schemes

Write Protect (WP#)

The Write Protect feature provides a hardware method

of protecting sectors without using V . This function

If the Password Mode Locking Bit is not set, including

Persistent Protection Mode, the PPB Lock Bit is

cleared after power-up or hardware reset. The PPB

Lock Bit is set by issuing the PPB Lock Bit Set com-

mand. Once set the only means for clearing the PPB

Lock Bit is by issuing a hardware or power-up reset.

The Password Unlock command is ignored in Persis-

tent Protection Mode.

ID

is provided by the WP# pin and overrides the previ-

ously discussed High Voltage Sector Protection

method.

If the system asserts V on the WP#/ACC pin, the de-

IL

vice disables program and erase functions in the two

outermost 4 Kword sectors on both ends of the flash

array independent of whether it was previously pro-

tected or unprotected.

High Voltage Sector Protection

Sector protection and unprotection may also be imple-

mented using programming equipment. The proce-

If the system asserts V on the WP#/ACC pin, the de-

IH

vice reverts to whether sectors were last set to be pro-

tected or unprotected. That is, sector protection or

unprotection for these sectors depends on whether

they were last protected or unprotected using the

method described in High Voltage Sector Protection.

dure requires high voltage (V ) to be placed on the

ID

RESET# pin. Refer to Figure 1 for details on this pro-

cedure. Note that for sector unprotect, all unprotected

sectors must first be protected prior to the first sector

write cycle.

Note that the WP#/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may

result.

Figure 1.

indicator bits (DQ6, DQ7) to indicate the factory-

locked and customer-locked status of the part.

Temporary Sector Unprotect

The system accesses the through a command se-

quence (see “Enter /Exit Command Sequence”). After

the system has written the Enter command sequence,

it may read the by using the addresses normally occu-

pied by the boot sectors. This mode of operation con-

tinues until the system issues the Exit command

sequence, or until power is removed from the device.

On power-up, or following a hardware reset, the device

reverts to sending commands to the normal address

space.

Notes:

1. All protected sectors unprotected (If WP#/ACC = V ,

IL

sectors will remain protected).

2. All previously protected sectors are protected once

again.

Figure 2.

Flash Memory Region

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN) The 128-word SecSi sector is divided into 64

factory-lockable words that can be programmed and

locked by the customer. The SecSi sector is located at

addresses 000000h-00007Fh in both Persistent Pro-

tection mode and Password Protection mode. It uses

Factory-Locked Area (64 words)

The factory-locked area of the SecSi Sector (000000h-

00003Fh) is locked when the part is shipped, whether

or not the area was programmed at the factory. The

SecSi Sector Factory-locked Indicator Bit (DQ7) is per-

manently set to a “1”. AMD offers the ExpressFlash

service to program the factory-locked area with a ran-

dom ESN, a customer-defined code, or any combina-

20

Am29PDL129H

November 2, 2005

tion of the two. Because only AMD can program and

protect the factory-locked area, this method ensures

the security of the ESN once the product is shipped to

the field. Contact an AMD representative for details on

using AMD’s ExpressFlash service. Note that the ACC

function and unlock bypass modes are not available

when the SecSi Sector is enabled.

the SecSi Protection Bit Program Command. The

SecSi Sector can be read any number of times, but

can be programmed and locked only once. Note that

the accelerated programming (ACC) and unlock by-

pass functions are not available when programming

the SecSi Sector.

The Customer-lockable area can be protected using

one of the following procedures:

Customer-Lockable Area (64 words)

Follow the SecSi Sector Protection Algorithm as

shown in . This allows in-system protection of the

SecSi Sector without raising any device pin to a high

voltage. Note that this method is only applicable to the

SecSi Sector.

The customer-lockable area of the SecSi Sector

(000040h-00007Fh) is shipped unprotected, which al-

lows the customer to program and optionally lock the

area as appropriate for the application. The SecSi

Sector Customer-locked Indicator Bit (DQ6) is shipped

as “0” and can be permanently locked to “1” by issuing

November 2, 2005

Am29PDL129H

21

START

SecSi^TMSector Entry

Write AAh to address 555h

Write 55h to address 2AAh

Write 88h to address 555h

SecSi Sector

Protection Entry

Write AAh to address 555h

Write 55h to address 2AAh

Write 60h to address 555h

PLSCNT = 1

Protect SecSi Sector:

write 68h to sector address

with A7–A0 = 00011010

Time out 256 μs

Verify SecSi Sector:

write 48h to sector address

with A7–A0 = 00011010

Read from sector address

with A7–A0 = 00011010

No

Data = 01h?

Yes

SecSi Sector

Protection Completed

SecSi Sector Exit

Write 555h/AAh

Write 2AAh/55h

Write SA0+555h/90h

Write XXXh/00h

Figure 3. SecSi Sector Protection Algorithm

■ To verify the protect/unprotect status of the SecSi

Sector, follow the algorithm shown in Figure 4.

22

Am29PDL129H November 2, 2005

Once the is locked and verified, the system must write the Exit Region command sequence to return to reading and

writing the remainder of the array.

The must be used with caution since, once locked, there is no procedure available for unlocking the area and none

of the bits in the memory space can be modified in any way.

SecSi Sector Protection Bits

The SecSi Sector Protection Bits prevent programming of the SecSi Sector memory area. Once set, the SecSi

Sector memory area contents are non-modifiable.

START

If data = 00h,

RESET# =

SecSi Sector is

V_IHor V_ID

unprotected.

If data = 01h,

SecSi Sector is

protected.

Wait 1 μs

Write 60h to

any address

Remove V_IHor V_ID

from RESET#

Write 40h to SecSi

Sector address

Write reset

with A6 = 0,

command

A1 = 1, A0 = 0

SecSi Sector

Read from SecSi

Protect Verify

Sector address

complete

with A6 = 0,

A1 = 1, A0 = 0

Figure 4. SecSi Sector Protect Verify

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software interrogation hand-

shake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Soft-

ware support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for

the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibil-

ity.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any

time the device is ready to read array data. The system can read CFI information at the addresses given in Tables

10–13. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not ac-

cessible when the device is executing an Embedded Program or embedded Erase algorithm.

The system can also write the CFI query command when the device is in the autoselect mode. The device enters

the CFI query mode, and the system can read CFI data at the addresses given in Tables 10–13. The system must

write the reset command to return the device to reading array data.

For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide

Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents.

Table 10. CFI Query Identification String

Addresses

Data

Description

November 2, 2005

Am29PDL129H

23

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

0000h

Table 11. System Interface String

Description

Addresses

Data

V

Min. (write/erase)

CC

1Bh

0027h

D7–D4: volt, D3–D0: 100 millivolt

V

Max. (write/erase)

CC

1Ch

0036h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0004h

0000h

0009h

0000h

0005h

0000h

0004h

0000h

V

Min. voltage (00h = no V pin present)

PP

Max. voltage (00h = no V pin present)

PP

N

Typical timeout per single byte/word write 2 µs

N

Typical timeout for Min. size buffer write 2 µs (00h = not supported)

N

Typical timeout per individual block erase 2 ms

N

Typical timeout for full chip erase 2 ms (00h = not supported)

N

Max. timeout for byte/word write 2 times typical

N

Max. timeout for buffer write 2 times typical

N

Max. timeout per individual block erase 2 times typical

N

Max. timeout for full chip erase 2 times typical (00h = not supported)

Table 12. Device Geometry Definition

Description

Addresses

Data

N

27h

0018h

Device Size = 2 byte

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

N

2Ah

2Bh

0000h

Max. number of byte in multi-byte write = 2

(00h = not supported)

2Ch

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

00FDh

0000h

0001h

Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

24

Am29PDL129H

November 2, 2005

35h

36h

37h

38h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

39h

3Ah

3Bh

3Ch

0000h

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

November 2, 2005

Am29PDL129H

25

Table 13. Primary Vendor-Specific Extended Query

Data Description

Addresses

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII (reflects modifications to the silicon)

Minor version number, ASCII (reflects modifications to the CFI table)

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

000Ch

Silicon Revision Number (Bits 7-2)

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

0002h

0001h

0007h

00E7h

0000h

0002h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode

Simultaneous Operation

00 = Not Supported, X = Number of Sectors excluding Bank 1

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

0085h

0095h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

4Fh

0001h

00h = Uniform device, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both

Top and Bottom

Program Suspend

50h

57h

58h

59h

5Ah

5Bh

0001h

0004h

0027h

0060h

0027h

0 = Not supported, 1 = Supported

Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

Bank 1 Region Information

X = Number of Sectors in Bank 1

Bank 2 Region Information

X = Number of Sectors in Bank 2

Bank 3 Region Information

X = Number of Sectors in Bank 3

Bank 4 Region Information

X = Number of Sectors in Bank 4

26

Am29PDL129H

November 2, 2005

COMMAND DEFINITIONS

Bit Program Command should be reissued to improve

program margin. µµAfter programming a PPB, two ad-

ditional cycles are needed to determine whether the

PPB has been programmed with margin. If the PPB

has been programmed without margin, the program

command should be reissued to improve the program

margin. Also note that the total number of PPB pro-

gram/erase cycles is limited to 100 cycles. Cycling the

PPBs beyond 100 cycles is not guaranteed.

Enter /Exit Command Sequence

The region provides a secured data area containing a

random, eight word electronic serial number (ESN).

The system can access the region by issuing the

three-cycle Enter command sequence. The device

continues to access the region until the system issues

the four-cycle Exit command sequence. The Exit om-

mand sequence returns the device to normal opera-

tion. The SecSi Sector is not accessible when the

device is executing an Embedded Program or embed-

ded Erase algorithm. shows the address and data re-

quirements for both command sequences. See also

“SecSi Sector Flash Memory Region and Enter SecSi

Sector/Exit SecSi Sector Command Sequence” for fur-

ther information. Note that the ACC function and un-

lock bypass modes are not available when the SecSi

Sector is enabled.

After erasing the PPBs, two additional cycles are

needed to determine whether the PPB has been

erased with margin. If the PPBs has been erased with-

out margin, the erase command should be reissued to

improve the program margin.

PPB Lock Bit Status

Sector Protection Status The programming of

either the PPB or DYB for a given sector or sector

group can be verified by writing a Sector Protection

Status command to the device.

Figure 5.

If the Persistent Sector Protection Mode Locking Bit is

verified as programmed without margin, the Persistent

Sector Protection Mode Locking Bit Program Com-

mand should be reissued to improve program margin.

If the SecSi Sector Protection Bit is verified as pro-

grammed without margin, the SecSi Sector Protection

Note that there is no single command to independently

verify the programming of a DYB for a given sector

group.

November 2, 2005

Am29PDL129H

27

Command Definitions Tables

Table 14. Memory Array Command Definitions

Bus Cycles (Notes 1–4)

Command (Notes)

Addr Data Addr Data Addr Data

RA RD

XXX F0

Addr

Data

Addr

Data

Addr

Data

Read (5)

Reset (6)

1

4

6

Manufacturer ID

555

AA 2AA

55

555

90 (BA)X00

90 (BA)X01

01

7E

Device ID (10)

AA 2AA

(BA)X0E 21 (BA)X0F

00

Autoselect

(Note 7)

SecSi Sector Factory

Protect (8)

(see

note 8)

4

555

AA 2AA

55

555

90

X03

Sector Group Protect Verify

(9)

XX00/

XX01

555 AAA 2AA

90 (SA)X02

Program

4

6

1

2

3

2

1

2

555

BA

55

AA 2AA

B0

55

555

A0

80

PA

PD

AA

Chip Erase

Sector Erase

555

2AA

55

555

SA

10

30

Program/Erase Suspend (11)

Program/Erase Resume (12)

CFI Query (13)

30

98

Accelerated Program (15)

Unlock Bypass Entry (15)

Unlock Bypass Program (15)

Unlock Bypass Erase (15)

Unlock Bypass CFI (13, 15)

Unlock Bypass Reset (15)

XX

555

XX

A0

PA

PD

55

AA 2AA

555

20

A0

80

98

PA

XX

PD

10

XXX 90 XXX 00

Legend:

BA = Address of bank switching to autoselect mode, bypass mode, or

erase operation. Determined by A21:A20, see Tables 4 and for more

detail.

PA = Program Address (A21:A0). Addresses latch on falling edge of

WE# or CE1#/CE2# pulse, whichever happens later.

PD = Program Data (DQ15:DQ0) written to location PA. Data latches

on rising edge of WE# or CE1#/CE2# pulse, whichever happens first.

RA = Read Address (A21:A0).

RD = Read Data (DQ15:DQ0) from location RA.

SA = Sector Address (A21:A12) for verifying (in autoselect mode) or

erasing.

WD = Write Data. See “Configuration Register” definition for specific

write data. Data latched on rising edge of WE#.

X = Don’t care

Notes:

1. See Table 1 for description of bus operations.

8. The data is C0h for factory or customer locked and 80h for factory

locked.

2. All values are in hexadecimal.

9. The data is 00h for an unprotected sector group and 01h for a

protected sector group.

3. Shaded cells in table denote read cycles. All other cycles are

write operations.

10. Device ID must be read across cycles 4, 5, and 6.

4. During unlock and command cycles, when lower address bits are

555 or 2AAh as shown in table, address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are

don’t cares.

11. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Program/Erase Suspend mode.

Program/Erase Suspend command is valid only during a sector

erase operation, and requires bank address.

5. No unlock or command cycles required when bank is reading

array data.

12. Program/Erase Resume command is valid only during Erase

Suspend mode, and requires bank address.

6. The Reset command is required to return to reading array (or to

erase-suspend-read mode if previously in Erase Suspend) when

bank is in autoselect mode, or if DQ5 goes high (while bank is

providing status information).

13. Command is valid when device is ready to read array data or

when device is in autoselect mode.

14. must be at V_IDduring the entire operation of command.

7. Fourth cycle of autoselect command sequence is a read cycle.

System must provide bank address to obtain manufacturer ID or

device ID information. See Autoselect Command Sequence for

more information.

15. Unlock Bypass Entry command is required prior to any Unlock

Bypass operation. Unlock Bypass Reset command is required to

return to the reading array.

28

Am29PDL129H

November 2, 2005

Table 15. Sector Protection Command Definitions

Bus Cycles (Notes 1-4)

Command

(Notes)

Addr Data Addr Data Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Reset

1

3

4

XXX

555

F0

SecSi Sector Entry

SecSi Sector Exit

AA 2AA

55

555

88

90

XX

00

68

SecSi Protection

Bit Program (5, 6)

6

5

4

7

555

AA 2AA

55

555

60

38

C8

28

OW

48

OW

RD(0)

SecSi Protection

Bit Status

OW

48

RD(0)

Password Program

(5, 7, 8)

XX[0-3]

PD[0-3]

PasswordVerify (6,

8, 9)

PWA[0-3] PWD[0-3]

Password Unlock

(7, 10, 11)

PWA[0]

PWD[0]

PWA[1]

PWD[1]

PWA[2]

(SA)WP

PWD[2]

RD(0)

PWA[3]

PWD[3]

PPBProgram(5, 6,

12, 17)

6

5

6

555

AA 2AA

55

555

60

(SA)WP

WP

68

48

60

(SA)WP

(SA)

48

RD (0)

40

PPB Status

All PPB Erase (5,

6, 13, 14)

(SA)WP

RD(0)

PPB Lock Bit Set

(17)

3

4

555

AA 2AA

55

555

78

58

PPB Lock Bit

Status (15)

SA

RD(1)

DYB Write (7)

4

555

AA 2AA

55

555

48

58

SA

X1

X0

DYB Erase (7)

DYB Status (6, 18)

RD(0)

PPMLB Program

(5, 6, 12)

6

5

6

5

555

AA 2AA

55

555

60

PL

SL

68

48

68

48

PL

SL

48

PL

SL

RD(0)

PPMLB Status (5)

RD(0)

48

SPMLB Program

(5, 6, 12)

SPMLB Status (5)

RD(0)

Legend:

DYB = Dynamic Protection Bit

RD(1) = Read Data DQ1 for PPB Lock status.

OW = Address (A7:A0) is (00011010)

PD[3:0] = Password Data (1 of 4 portions)

PPB = Persistent Protection Bit

PWA = Password Address. A1:A0 selects portion of password.

PWD = Password Data being verified.

SA = Sector Address where security command applies. Address bits

A21:A12 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)

WP = PPB Address (A7:A0) is (00000010) (Note16)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

PL = Password Protection Mode Lock Address (A7:A0) is (00001010)

RD(0) = Read Data DQ0 for protection indicator bit.

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

11. A 2 µs timeout is required between any two portions of password.

12. A 100 µs timeout is required between cycles 4 and 5.

13. A 1.2 ms timeout is required between cycles 4 and 5.

3. Shaded cells in table denote read cycles. All other cycles are

write operations.

14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been

fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command

must be issued and verified again. Before issuing erase

command, all PPBs should be programmed to prevent PPB

overerasure.

4. During unlock and command cycles, when lower address bits are

555 or 2AAh as shown in table, address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are

don’t cares.

5. The reset command returns device to reading array.

15. DQ1 = 1 if PPB locked, 0 if unlocked.

6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6

validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0

in cycle 6, program command must be issued and verified again.

16. For PDL128G and PDL640G, the WP address is 0111010. The

EP address (PPB Erase Address) is 1111010.

17. Following the final cycle of the command sequence, the user must

write the first three cycles of the Autoselect command and then

write a Reset command.

7. Data is latched on the rising edge of WE#.

8. Entire command sequence must be entered for each portion of

password.

18. If checking the DYB status of sectors in multiple banks, the user

must follow Note 17 before crossing a bank boundary.

9. Command sequence returns FFh if PPMLB is set.

10. The password is written over four consecutive cycles, at

addresses 0-3.

November 2, 2005

Am29PDL129H

29

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V

(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

CC

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +13.0 V

20 ns

(Note 2) . . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1). . . . . . –0.5 V to V +0.5 V

CC

Figure 6. Maximum Negative

Overshoot Waveform

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V

to –2.0 V for periods of up to 20 ns.

SS

Maximum DC voltage on input or I/O pins is V +0.5 V.

See . During voltage transitions, input or I/O pins may

20 ns

CC

V

overshoot to V

Figure 7.

+2.0 V for periods up to 20 ns. See

CC

+2.0 V

V

+0.5 V

CC

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and WP#/ACC is –0.5 V. During voltage transitions, A9,

OE#, WP#/ACC, and RESET# may overshoot V to –

2.0 V

SS

2.0 V for periods of up to 20 ns. See . Maximum DC input

voltage on pin A9, OE#, and RESET# is +12.5 V which

may overshoot to +14.0 V for periods up to 20 ns.

Maximum DC input voltage on WP#/ACC is +9.5 V which

may overshoot to +12.0 V for periods up to 20 ns.

20 ns

Figure 7. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C

A

Supply Voltages

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7–3.6V

(see Note) . . . . . . . . . . .1.65–1.95 V or 2.7–3.6 V

CC

IO

For all AC and DC specifications, V = V ; contact

IO

CC

AMD for other V options.

IO

Operating ranges define those limits between which the

functionality of the device is guaranteed.

30

Am29PDL129H

November 2, 2005

DC CHARACTERISTICS

CMOS Compatible

Parameter

Parameter Description

Test Conditions

_IN= V_SSto V_CC

Min

Typ

Max

Unit

Symbol

V

,

I_LI

Input Load Current

±1.0

µA

V_CC= V_{CC max}

I_LIT

I_LR

A9, OE#, RESET# Input Load Current

Reset Leakage Current

V_CC= V_{CC max}; V_ID= 12.5 V

35

µA

V

_OUT= V_SSto V_CC, OE# = V_IH

I_LO

Output Leakage Current

±1.0

µA

V_CC= V_{CC max}

5 MHz

20

45

15

30

55

25

OE# = V_IH, V_CC= V_{CC max}

(Note 1)

I_CC1

V_CCActive Read Current (Notes 1, 2, 3)

mA

10 MHz

I_CC2

I_CC3

I_CC4

I_CC5

V_CCActive Write Current (Notes 1, 3, 4)

V_CCStandby Current (Note 3)

OE# = V_IH, WE# = V_IL

mA

µA

CE1#, CE2#, RESET#, WP/ACC#

1

5

= V_IO± 0.3 V

V_CCReset Current (Note 3)

RESET# = V_SS± 0.3 V, CE# = V_SS

V_IH= V_IO± 0.3 V;

V_IL= V_SS± 0.3 V, CE# = V_SS

Automatic Sleep Mode (Notes 3, 5)

V_CCActive Read-While-Program Current

(Notes 1, 2, 3)

I_CC6

I_CC7

I_CC8

OE# = V_IH

Word

21

17

45

25

mA

V_CCActive Read-While-Erase Current

(Notes 1, 2, 3)

V_CCActive Program-While-Erase-

Suspended Current (Notes 1, 3, 6)

V

_IO= 1.65–1.95 V

_IO= 2.7–3.6 V

–0.4

–0.5

0.4

0.8

V

V_IL

V_IH

Input Low Voltage

V

V_IO–0.4

V_IO+0.4

V_IO= 1.65–1.95 V

_IO= 2.7–3.6 V

Input High Voltage

V_CC+0.3

9.5

V

2.0

8.5

V

V_HH

V_ID

Voltage for ACC Program Acceleration

V_CC= 3.0 V 10ꢀ

Voltage for Autoselect and Temporary

Sector Unprotect

V_CC= 3.0 V ± 10ꢀ

11.5

12.5

V

I_OL= 100 µA, V_CC= V_{CC min}, V_IO= 1.65–1.95

0.1

0.4

V

V_OL

Output Low Voltage

I_OL= 2.0 mA, V_CC= V_{CC min}, V_IO= 2.7–3.6 V

I_OH= –100 µA, V_CC= V_{CC min}, V_IO= 1.65–1.95 V

I_OH= –2.0 mA, V_CC= V_{CC min}, V_IO= 2.7–3.6 V

V

V_IO–0.1

2.4

V_OH

Output High Voltage

V_LKO

Low V_CCLock-Out Voltage (Note 6)

2.3

2.5

Notes:

1. Valid CE1#/CE2# conditions: (CE1#= V , CE2#= V ) or (CE1#=

4. I_CCactive while Embedded Erase or Embedded Program is in

progress.

IL

IH

V

, CE2#= V )

IH

IL

2. The I_CCcurrent listed is typically less than 5 mA/MHz, with OE# at

V_IH

5. Automatic sleep mode enables the low power mode when

addresses remain stable for t_ACC+ 150 ns. Typical sleep mode

current is 1 μA.

.

3. Maximum I_CCspecifications are tested with V_CC= V_CCmax

.

6. Not 100% tested.

November 2, 2005

Am29PDL129H

31

TEST CONDITIONS

Table 16. Test Specifications

Test Condition All Speeds

1 TTL gate

3.6 V

Unit

Output Load

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C

(including jig capacitance)

L

30

pF

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

C

L

6.2 kΩ

0.0–3.0

Input timing measurement

reference levels

1.5

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

Figure 8. Test Setup, V = 2.7 – 3.6 V

Note: For 70 pF output load capacitance, 2 ns will be added

to certain read-only operation parameters.

IO

* For V = 1.65 – 1.95 Test Setup, the device is tested

IO

using C only

L

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

V_IO

V

_IO/2

V_IO/2

Input

Measurement Level

Output

0.0 V

Figure 9. Input Waveforms and Measurement Levels

32

Am29PDL129H

November 2, 2005

AC CHARACTERISTICS

CE1#/CE2# Timing

Parameter

JEDEC

Std

Description

CE1#/CE2# Recover Time

All Speed Options

Unit

t

Min

30

ns

CCR

CE1#

t_CCR

CE2#

Figure 10. Timing Diagram for Alternating Between CE1# and CE2# Control

Read-Only Operations

Parameter

Speed Options

JEDEC Std. Description

Test Setup

53

55

60

20

63

65

25

68

65

70

88 Unit

t

Read Cycle Time (Note 1)

Min

Max

85

ns

AVAV

RC

t

Address to Output Delay (Note 3)

Chip Enable to Output Delay (Note 4)

Page Access Time

CE#, OE# = V

IL

AVQV

ACC

t

OE# = V

IL

ELQV

CE

t

30

PACC

t

Output Enable to Output Delay

Chip Enable to Output High Z (Notes 1, 5, 6)

Output Enable to Output High Z (Notes 1, 5)

GLQV

EHQZ

GHQZ

OE

t

16

DF

t

Output Hold Time From Addresses, CE#/CE2#

or OE#, Whichever Occurs First (Notes 5, 6)

t

Min

5

0

ns

AXQX

OH

Read

Output Enable Hold Time

(Note 1)

t

OEH

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 8 and Table 16 for test specifications

3. Valid CE1#/CE2# conditions: (CE1#= V_IL, CE2#= V_IH) or (CE1#=

_IH, CE2#=V_IL).

5. Measurements performed by placing a 50 ohm termination on the

data pin with a bias of V_CC/2. The time from OE# high to the data

bus driven to V_CC/2 is taken as t_DF

6. Valid CE1#/CE2# transitions: (CE1#= V_IL, CE2#= V_IH) or (CE1#=

_IH, CE2#=V_IL) to (CE1#= CE2#= V_IH).

.

V

4. Valid CE1#/CE2# transitions: (CE1#= CE2#= V_IH) to (CE1#= V_IL,

CE2#=V_IH) or (CE1#= V_IH, CE2#=V_IL).

7. For 70 pF output load capacitance, 2 ns will be added to t_ACC, t_CE

t_PACC, t_OEvalues for all speed options.

,

November 2, 2005

Am29PDL129H

33

AC CHARACTERISTICS

t_RC

Addresses Stable

Addresses

t_ACC

CE1# or CE2#

t_RH

t_DF

t_OE

OE#

WE#

t_OEH

t_CE

t_OH

HIGH Z

Valid Data

Data

RESET#

RY/BY#

0 V

Figure 11. Read Operation Timings

Note:

1. During CE1# transitions, CE2#= V ; During CE2# transitions, CE1#= V

IH

Same Page

Addresses

A2-A0

Ad

Aa

Ab

Ac

t_PACC

t_ACC

Data

Qa

Qb

Qc

Qd

CE1# or CE2#

OE#

Figure 12. Page Read Operation Timings

Note:

1. During CE1# transitions, CE2#= V ; During CE2# transitions, CE1#= V

IH

34

Am29PDL129H

November 2, 2005

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t

Max

20

µs

Ready

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

500

ns

Ready

t

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

RP

t

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

RH

t

RPD

t

RB

Note: Not 100% tested.

RY/BY#

CE1# or CE2#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE1# or CE2#, OE#

RESET#

t_RP

Figure 13. Reset Timings

Note:

1. During CE1# transitions, CE2#= V ; During CE2# transitions, CE1#= V

IH

November 2, 2005

Am29PDL129H

35

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed Options

JEDEC

Std.

Description

53

63

68

88

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Min

55

65

85

AVAV

WC

t

0

ns

AVWL

AS

Address Setup Time to OE# low

during toggle bit polling

t

Min

15

ns

ASO

t

Address Hold Time

30

25

35

30

WLAX

AH

Address Hold Time From CE1#, CE2#, or OE# high

during toggle bit polling

t

0

AHT

t

Data Setup Time

Min

ns

DVWH

DS

t

Data Hold Time

0

WHDX

DH

t

Output Enable High during toggle bit polling

10

OEPH

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHWL

t

CE1# or CE2# Setup Time

Min

Typ

Min

Max

0

ns

µs

sec

µs

ns

ELWL

WHEH

WLWH

CS

CH

WP

t

CE1# or CE2# Hold Time

t

Write Pulse Width

35

20

40

25

t

Write Pulse Width High

WHDL

WPH

t

Latency Between Read and Write Operations

Programming Operation (Note 2)

Accelerated Programming Operation (Note 2)

Sector Erase Operation (Note 2)

0

6

SR/W

t

WHWH1

WHWH2

WHWH1

WHWH2

4

0.5

50

0

t

V

Setup Time (Note 1)

CC

VCS

t

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

RB

t

90

BUSY

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

36

Am29PDL129H

November 2, 2005

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE1# or CE2#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D

is the true data at the program address.

OUT

2. During CE1# transitions, CE2#= V ; During CE2# transitions, CE1#= V

IH

Figure 14. Program Operation Timings

V_HH

V_ILor V_IH

WP#/ACC

t_VHH

Figure 15. Accelerated Program Timing Diagram

t_VHH

November 2, 2005

Am29PDL129H

37

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE1# or CE2#

OE#

2AAh

555h for chip erase

t_AH

t_CH

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

Data

Status

D

OUT

55h

30h

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (.)

2. During CE1# transitions, CE2#= V ; During CE2# transitions, CE1#= V

IH

Figure 16. Chip/Sector Erase Operation Timings

38

Am29PDL129H

November 2, 2005

AC CHARACTERISTICS

t_WC

Valid PA

t_WC

t_RC

t_WC

Valid PA

Valid RA

Valid PA

Addresses

t_AH

t_AS

t_CPH

t_AS

t_AH

t_ACC

t_CE

CE1# or CE2#

OE#

t_CP

t_OE

t_OEH

t_GHWL

t_WP

WE#

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

Data

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

Note:

1. During CE1# transitions, CE2#= V ; During CE2# transitions, CE1#= V

IH

Figure 17. Back-to-back Read/Write Cycle Timings

t_RC

Addresses

VA

t_ACC

t_CE

VA

CE1# or CE2#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ6–DQ0

Status Data

True

Valid Data

Status Data

t_BUSY

RY/BY#

Note:

1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read

cycle. During CE1# transitions, CE2#= V ;

IH

2. During CE2# transitions, CE1#= V

IH

Figure 18. Data# Polling Timings (During Embedded Algorithms)

November 2, 2005

Am29PDL129H

39

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE1# or CE2#

t_CEPH

t_OEH

WE#

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

RY/BY#

Valid Data

(first read)

(second read)

(stops toggling)

Notes:

1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

2. During CE1# transitions, CE2#= V ; During CE2# transitions, CE1#= V

IH

Figure 19. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note:

1. DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 20. DQ2 vs. DQ6

40

Am29PDL129H

November 2, 2005

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

ns

t

V

Rise and Fall Time (See Note)

HH

Min

500

250

VIDR

ID

t

V

ns

VHH

RESET# Setup Time for Temporary Sector

Unprotect

t

Min

4

µs

RSP

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t

RRB

Note: Not 100% tested.

V_ID

RESET#

V_ILor V_IH

t_VIDR

Program or Erase Command Sequence

CE1# or CE2#

WE#

t_RRB

t_RSP

RY/BY#

Note: During CE1# transitions, CE2#= V ; During CE2# transitions, CE1#= V

IH

Figure 21. Temporary Sector Unprotect Timing Diagram

November 2, 2005

Am29PDL129H

41

AC CHARACTERISTICS

V

ID

V

IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector Group Protect/Unprotect

Verify

40h

Data

60h

1 µs

Sector Group Protect: 150 µs

Sector Group Unprotect: 15 ms

CE1# or CE2#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Notes:

1. During CE1# transitions, CE2#= V ; During CE2# transitions, CE1#= V

IH

Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram

42

Am29PDL129H

November 2, 2005

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

Speed Options

JEDEC

Std.

Description

53

63

68

88

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

55

65

85

AVAV

WC

t

0

ns

AVWL

AS

AH

DS

DH

t

30

25

35

30

ns

ELAX

DVEH

EHDX

t

ns

t

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

ns

GHEL

t

WE# Setup Time

Min

0

ns

WLEL

WS

t

WE# Hold Time

EHWH

WH

t

CE1# or CE2# Pulse Width

CE1# or CE2# Pulse Width High

35

20

40

25

ELEH

EHEL

CP

t

CPH

Programming Operation

(Note 2)

t

Typ

6

µs

WHWH1

t

Accelerated Programming Operation (Note 2)

Sector Erase Operation (Note 2)

Typ

4

µs

WHWH1

WHWH2

WHWH1

0.5

sec

WHWH2

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

November 2, 2005

Am29PDL129H

43

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE1# or CE2#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. During CE1# transitions, CE2#= V_IH; During CE2# transitions, CE1#= V_IH

Figure 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings

44

Am29PDL129H

November 2, 2005

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

Comments

Sector Erase Time

Chip Erase Time

0.4

5

Excludes 00h programming

prior to erasure (Note 4)

108

Excludes system level

overhead (Note 5)

Word Program Time

6

210

µs

Accelerated Word Program Time

Chip Program Time (Note 3)

Notes:

4

120

200

µs

50

sec

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 1,000,000 cycles. Additionally,

CC

programming typicals assume checkerboard pattern. All values are subject to change.

2. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles. All values are subject to change.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables

for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V on all pins except I/O pins

(including A9, OE#, and RESET#)

SS

–1.0 V

13 V

Input voltage with respect to V on all I/O pins

–1.0 V

V

+ 1.0 V

SS

CC

V

Current

–100 mA

+100 mA

CC

Note: Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time, V = V

CC

IO

CC

BGA BALL CAPACITANCE

Parameter

Symbol

Parameter Description

Test Setup

Typ

4.2

5.4

3.9

Max

5.0

Unit

pF

C

Input Capacitance

Output Capacitance

V

= 0

IN

C

V

= 0

6.5

pF

OUT

C

Control Pin Capacitance

V

= 0

IN

4.7

pF

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

November 2, 2005

Am29PDL129H

45

Sector Erase Command Sequence and Chip Erase

Command Sequence

REVISION SUMMARY

Revision A (September 30, 2002)

Added “”

Initial release.

Table 14. “Memory Array Command Definitions

Revision A+1 (October 30, 2002)

Changed the first address of the unlock bypass reset

command sequence from BA to XXX.

Product Selector Guide

CMOS Compatible

Modified format of product selector guide table.

Added I parameter to table.

LR

Ordering Information

Deleted I

parameter from table.

ACC

Changed TBD to VK under the package type classifi-

cation.

Revision A+2 (January 24, 2003)

Added VK packages to Valid Combinations table.

Ordering Information

Global

Corrected the ordering part number and package

markings for the 83 and 88 speed options.

Changed 55 speed option to 53, changed 65 speed

option to 63 and 68.

Revision A+3 (February 26, 2003)

Table 1. Am29PDL127H Device Bus Operations

Table 16. Test Specifications

Added note #2.

Updated output load capacitance.

Requirements for Reading Array Data

Revision A + 4 (April 22, 2003)

Reworded Page Mode Read section

Inserted and revised cross references.

Common Flash Memory Interface (CFI)

Revision A+5 (June 20, 2003)

Changed wording in last sentence of third paragraph

from, “...the autoselect mode.” to “...reading array

data.”

Distinctive Characteristics

Changed the active read current to 55 mA.

Changed CFI website address.

Product Selector Guide

Command Definitions

Added row to table to expand speed options and allow

Changed wording in last sentence of first paragraph

from, “...resets the device to reading array data.” to

...”may place the device to an unknown state. A reset

command is then required to return the device to

reading array data.”

for another V range.

CC

Physical Dimensions

Removed the LAA064 package.

Revision B (July 29, 2003)

Customer Lockable: SecSi Sector NOT

Programmed or Protected at the factory.

Global

Added second bullet, SecSi sector-protect verify text

and Figure 3.

Changed most CE# references to CE1#.

Changed Bank C to Bank 1A, Bank D to Bank 1B,

Bank A to Bank 2A, and Bank B to Bank 2B.

SecSi Sector Flash Memory Region and Enter

SecSi Sector/Exit SecSi Sector Command

Sequence

Sector Configuration Table

Added notes, “Note that the ACC function and unlock

bypass modes are not available when the SecSi sector

is enabled.”

Corrected CE1# and CE2# bank references.

Table 4. Am29PDL129H Sector Architecture

Changed the Bank order to 1A, 1B, 2A, and 2B.

46

Am29PDL129H

November 2, 2005

Table 7. Am29PDL129H Boot Sector/Sector Block

Addresses for Protection/Unprotection

mA; changed program/erase current from 25 to 15

mA.

Broke table up into CE1# and CE2# versions and made

modifications to table values to reflect change.

Connection Diagrams

Corrected signal descriptions for balls G1 and J1 on

80-ball fine-pitch BGA package (VBB080).

WP# Hardware Protection

Indicated that a write protect pin that can prevent pro-

gram or erase operations in sectors SA1-133, SA1-

134, SA2-0 and SA2-1.

DC Characteristics

Changed I test conditions for V from 4.0 mA to 2.0

OL

mA.

Table 15. Sector Protection Command Definitions

Table 16, Test Specifications

Corrected typos in the PPB status row.

Changed C from 70 pF to 30 pF. Added note for 70

L

pF load capacitance.

Added Note 17 to PPB Program and PPB Lock Bit Set

commands.

AC Characteristics

Added Note 18 to DYB Status.

Read-only Operations table: Added note for 70 pF

load capacitance.

Test Conditions

TM

Added note to Figure 10.

SecSi (Secured Silicon) Sector Flash Memory

Region

Table 16. Test Specifications

Customer-Lockable Area: Added sector protection fig-

ure and changed figure reference in this section from

Figure 1 to Figure 3.

Added specific speed options to table.

CMOS Compatible Table

Added CE# = V to I

and I

CC5.

Table 16. Sector Protection Command Definitions

SS

CC4

Corrected number of cycles for SecSi Protection Bit

Status, PPMLB Status, and SPMLB Status from 4 to 5

cycles. For these command sequences, inserted a

cycle before the final read cycle (RD0).

Figure 11. Input Waveforms and Measurement

Levels

Modified values to read V

CC.

Revision B+1 (August 8, 2003)

Revision B+3 (November 2, 2005)

Updated migration statement on cover page and first

page of data sheet.

Ordering Information

Corrected typo in package marking.

This product has been retired and is not available for

designs. For new and current designs, Am29PDL129J

supersedes Am29PDL129H and is the factory-recom-

mended migration path. Please refer to the

Am29PDL129J datasheet for specifications and order-

ing information. Availability of this document is

retained for reference and historical purposes only.

Revision B+2 (December 5, 2003)

Global

Deleted the 83 speed option (85 ns t

, V = 2.7–

IO

ACC

3.6V). Replaced the 88 speed option (85 ns t

, V

ACC

IO

= 1.65–1.95V) with 78 (70 ns t

, V = 1.65–1.95V).

ACC IO

Updated trademarks.

Distinctive Characteristics

Performance Characteristics: Under Power Consump-

tion bullet, changed active read current from 55 to 45

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

November 2, 2005

Am29PDL129H

47


型号：	AM29PDL129H53VKF
厂家：	SPANSION
描述：	Flash, 8MX16, 55ns, PBGA80, 11.50 X 9 MM, 0.80 MM PITCH, PLASTIC, FBGA-80 闪存
文件：	总49页 (文件大小：847K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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