AM41DL1634DB85IS [SPANSION]
Memory Circuit, Flash+SRAM, 1MX16, CMOS, PBGA69, 8 X 11 MM, FBGA-69;
| 型号： | AM41DL1634DB85IS |
| 厂家： | 
SPANSION |
| 描述： | Memory Circuit, Flash+SRAM, 1MX16, CMOS, PBGA69, 8 X 11 MM, FBGA-69 静态存储器 内存集成电路 |
| 文件： | 总63页 (文件大小：1056K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Am41DL16x4D
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 25562 Revision A Amendment 0 Issue Date October 24, 2001
PRELIMINARY
Am41DL16x4D
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous
Operation Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
SOFTWARE FEATURES
MCP Features
■ Power supply voltage of 2.7 to 3.3 volt
■ Data Management Software (DMS)
—
AMD-supplied software manages data programming and
erasing, enabling EEPROM emulation
Eases sector erase limitations
■ High performance
—
Access time as fast as 70 ns
—
■ Package
■ Supports Common Flash Memory Interface (CFI)
■ Erase Suspend/Erase Resume
—
69-Ball FBGA
■ Operating Temperature
—
Suspends erase operations to allow programming in same
bank
—
–40°C to +85°C
■ Data# Polling and Toggle Bits
Flash Memory Features
—
Provides a software method of detecting the status of
program or erase cycles
ARCHITECTURAL ADVANTAGES
■ Unlock Bypass Program command
■ Simultaneous Read/Write operations
—
Reduces overall programming time when issuing multiple
program command sequences
—
Data can be continuously read from one bank while
executing erase/program functions in other bank
Zero latency between read and write operations
—
HARDWARE FEATURES
■ Secured Silicon (SecSi) Sector: Extra 64 KByte sector
■ Any combination of sectors can be erased
—
Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function.
■ Ready/Busy# output (RY/BY#)
—
Hardware method for detecting program or erase cycle
completion
—
Customer lockable: Can be read, programmed, or erased
just like other sectors. Once locked, data cannot be changed
■ Hardware reset pin (RESET#)
—
Hardware method of resetting the internal state machine to
reading array data
■ Zero Power Operation
Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero
—
■ WP#/ACC input pin
—
Write protect (WP#) function allows protection of two outermost
boot sectors, regardless of sector protect status
■ Top or bottom boot block
■ Manufactured on 0.23 µm process technology
—
Acceleration (ACC) function accelerates program timing
■ Compatible with JEDEC standards
■ Sector protection
—
Pinout and software compatible with single-power-supply
flash standard
—
Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
PERFORMANCE CHARACTERISTICS
—
Temporary Sector Unprotect allows changing data in
protected sectors in-system
■ High performance
—
—
70 ns access time
Program time: 4 µs/word typical utilizing Accelerate function
SRAM Features
■ Power dissipation
■ Ultra low power consumption (typical values)
—
—
—
2 mA active read current at 1 MHz
—
—
Operating: 22 mA maximum
Standby: 10 µA maximum
10 mA active read current at 5 MHz
200 nA in standby or automatic sleep mode
■ CE1#s and CE2s Chip Select
■ Minimum 1 million write cycles guaranteed per sector
■ 20 Year data retention at 125°C
■ Power down features using CE1#s and CE2s
■ Data retention supply voltage: 1.5 to 3.3 volt
■ Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)
—
Reliable operation for the life of the system
Publication# 25562 Rev: A Amendment/0
Issue Date: October 24, 2001
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
Am29DL16xD Features
reading and writing like any other flash sector, or may
permanently lock their own code there.
The Am29DL16xD family is a 16 megabit, 3.0 volt-only
flash memory device, organized as 1,048,576 words of
16 bits or 2,097,152 bytes of 8 bits each. Word mode
data appears on DQ15–DQ0; byte mode data ap-
pears on DQ7–DQ0. The device is designed to be
programmed in-system with the standard 3.0 volt VCC
supply, and can also be programmed in standard
EPROM programmers.
DMS (Data Management Software) allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
is an advantage compared to systems where
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and
software integration efforts.
The device is available with access times of 70 ns or
85 ns. The device is offered in a 69-ball FBGA pack-
age. Standard control pins—chip enable (CE#f), write
enable (WE#), and output enable (OE#)—control nor-
mal read and write operations, and avoid bus
contention issues.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and
simultaneously read from the other bank, with zero la-
tency. This releases the system from waiting for the
completion of program or erase operations.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to reading array data.
The Am29DL16xD devices uses multiple bank archi-
tectures to provide flexibility for different applications.
Four devices are available with the following bank
sizes:
Device
DL161
DL162
DL163
DL164
Bank 1
0.5 Mb
2 Mb
Bank 2
15.5 Mb
14 Mb
12 Mb
8 Mb
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
4 Mb
8 Mb
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via
programming equipment.
The Secured Silicon (SecSi) Sector is an extra 64
Kbit sector capable of being permanently locked by
AMD or customers. The SecSi Sector Indicator Bit
(DQ7) is permanently set to a 1 if the part is factory
locked, and set to a 0 if customer lockable. This
way, customer lockable parts can never be used to re-
place a factory locked part.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re-
duced in both modes.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number). Customer Lockable
parts may utilize the SecSi Sector as bonus space,
2
Am41DL16x4D
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Package ....................7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Reading Array Data ................................................................26
Reset Command .....................................................................26
Autoselect Command Sequence ............................................26
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..27
Byte/Word Program Command Sequence .............................27
Unlock Bypass Command Sequence ..................................27
Figure 3. Program Operation ......................................................... 28
Chip Erase Command Sequence ...........................................28
Sector Erase Command Sequence ........................................28
Erase Suspend/Erase Resume Commands ...........................29
Figure 4. Erase Operation.............................................................. 29
Table 16. Command Definitions (Flash Word Mode)...................... 30
Table 17. Autoselect Device IDs (Word Mode) .............................. 30
Table 18. Command Definitions (Flash Byte Mode) ....................... 31
Table 19. Autoselect Device IDs (Byte Mode) ............................... 31
Write Operation Status . . . . . . . . . . . . . . . . . . . . 32
DQ7: Data# Polling .................................................................32
Figure 5. Data# Polling Algorithm .................................................. 32
RY/BY#: Ready/Busy# ............................................................ 33
DQ6: Toggle Bit I ....................................................................33
Figure 6. Toggle Bit Algorithm........................................................ 33
DQ2: Toggle Bit II ...................................................................34
Reading Toggle Bits DQ6/DQ2 ...............................................34
DQ5: Exceeded Timing Limits ................................................34
DQ3: Sector Erase Timer .......................................................34
Table 20. Write Operation Status ................................................... 35
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 36
Industrial (I) Devices ............................................................36
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V ;
IH
SRAM Word Mode, CIOs = VCC ..................................................... 11
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V ;
IH
SRAM Byte Mode, CIOs = V ......................................................12
SS
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V ;
SS
SRAM Word Mode, CIOs = V .....................................................13
CC
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V ; SRAM
IL
Byte Mode, CIOs = V ..................................................................14
SS
Word/Byte Configuration ....................................................... 15
Requirements for Reading Array Data ...................................15
Writing Commands/Command Sequences ............................15
Accelerated Program Operation ..........................................15
Autoselect Functions ...........................................................15
Simultaneous Read/Write Operations with Zero Latency .......15
Standby Mode ........................................................................ 16
Automatic Sleep Mode ...........................................................16
RESET#: Hardware Reset Pin ...............................................16
Output Disable Mode ..............................................................16
Table 5. Device Bank Division ........................................................16
Table 6. Sector Addresses for Top Boot Sector Devices ............... 17
Table 7. SecSi Sector Addresses for Top Boot Devices ................17
Table 8. Sector Addresses for Bottom Boot Sector Devices ...........18
Table 9. SecSi Addresses for Bottom Boot Devices ..................18
Autoselect Mode ..................................................................... 19
Table 10. Top Boot Sector/Sector Block Addresses for Protection/Un-
protection ........................................................................................19
Table 11. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................19
Write Protect (WP#) ................................................................19
Temporary Sector/Sector Block Unprotect .............................20
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algo-
rithms .............................................................................................. 21
SecSi (Secured Silicon) Sector Flash Memory Region .......... 22
Factory Locked: SecSi Sector Programmed and Protected At
the Factory ..........................................................................22
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ...........................................................22
Hardware Data Protection ......................................................22
Low VCC Write Inhibit ...........................................................22
Write Pulse “Glitch” Protection ............................................ 23
Logical Inhibit ......................................................................23
Power-Up Write Inhibit .........................................................23
Common Flash Memory Interface (CFI) . . . . . . .23
Table 12. CFI Query Identification String........................................ 23
System Interface String................................................................... 24
Table 14. Device Geometry Definition ............................................ 24
Table 15. Primary Vendor-Specific Extended Query ...................... 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 26
V f/V s Supply Voltage ...................................................36
CC CC
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
CMOS Compatible ..................................................................37
SRAM DC and Operating Characteristics . . . . . 38
Zero-Power Flash .................................................................39
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep
Currents)........................................................................................ 39
Figure 10. Typical ICC1 vs. Frequency............................................ 39
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Test Setup.................................................................... 40
Table 21. Test Specifications ......................................................... 40
Key To Switching Waveforms . . . . . . . . . . . . . . . 40
Figure 12. Input Waveforms and Measurement Levels ................. 40
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
SRAM CE#s Timing ................................................................41
Figure 13. Timing Diagram for Alternating Between
SRAM to Flash............................................................................... 41
Flash Read-Only Operations .................................................42
Figure 14. Read Operation Timings............................................... 42
Hardware Reset (RESET#) ....................................................43
Figure 15. Reset Timings............................................................... 43
Flash Word/Byte Configuration (CIOf) ....................................44
Figure 16. CIOf Timings for Read Operations................................ 44
Figure 17. CIOf Timings for Write Operations................................ 44
Flash Erase and Program Operations ....................................45
Figure 18. Program Operation Timings.......................................... 46
Figure 19. Accelerated Program Timing Diagram.......................... 46
Figure 20. Chip/Sector Erase Operation Timings .......................... 47
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 48
Am41DL16x4D
3
P R E L I M I N A R Y
Figure 22. Data# Polling Timings (During Embedded Algorithms).. 48
Figure 31. SRAM Write Cycle—CE1#s Control............................. 57
Figure 32. SRAM Write Cycle—UB#s and LB#s Control............... 58
Flash Erase And Programming Performance . 59
Flash Latchup Characteristics. . . . . . . . . . . . . . . 59
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 59
FLASH Data Retention . . . . . . . . . . . . . . . . . . . . . 59
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 60
Figure 33. CE1#s Controlled Data Retention Mode....................... 60
Figure 34. CE2s Controlled Data Retention Mode......................... 60
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 61
FLA069—69-Ball Fine-Pitch Grid Array 8 x 11 mm ...............61
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 62
Revision A (October 24, 2001) ...............................................62
Figure 23. Toggle Bit Timings (During Embedded Algorithms)....... 49
Figure 24. DQ2 vs. DQ6.................................................................. 49
Temporary Sector/Sector Block Unprotect .............................50
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram............................................................................... 50
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram............................................................................... 51
Alternate CE#f Controlled Erase and Program Operations .... 52
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op-
eration Timings................................................................................ 53
SRAM Read Cycle .................................................................. 54
Figure 28. SRAM Read Cycle—Address Controlled....................... 54
Figure 29. SRAM Read Cycle......................................................... 55
SRAM Write Cycle .................................................................. 56
Figure 30. SRAM Write Cycle—WE# Control................................. 56
4
Am41DL16x4D
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Part Number
Am41DL16x4D
Flash Memory
SRAM
Standard Voltage Range:
Speed Options
VCC = 2.7–3.3 V
70
70
70
30
85
85
85
35
70
70
70
35
85
85
85
45
Max Access Time (ns)
CE# Access (ns)
OE# Access (ns)
MCP BLOCK DIAGRAM
VCC
f
VSS
A0 to A19
RY/BY#
A0 to A19
A–1
WP#/ACC
RESET#
CE#f
16 Mbit
Flash Memory
DQ0 to DQ15/A–1
CIOf
DQ0 to DQ15/A–1
VCCs/VCCQ VSS/VSSQ
A0 to A17
SA
4 Mbit
Static RAM
LB#s
UB#s
WE#
DQ0 to DQ15/A–1
OE#
CE1#s
CE2s
CIOs
Am41DL16x4D
5
P R E L I M I N A R Y
FLASH MEMORY BLOCK DIAGRAM
OE# CIOf
V
V
CC
SS
Upper Bank Address
A19–A0
Upper Bank
X-Decoder
RY/BY#
A19–A0
RESET#
STATE
CONTROL
&
COMMAND
REGISTER
WE#
CE#
Status
DQ15–DQ0
CIOf
Control
WP#/ACC
DQ15–DQ0
X-Decoder
Lower Bank
A19–A0
Lower Bank Address
6
Am41DL16x4D
P R E L I M I N A R Y
CONNECTION DIAGRAM
69-Ball FBGA
Top View
Flash only
SRAM only
Shared
A1
A5
A6
A10
NC
NC
NC
NC
B1
B3
A7
C3
A6
D3
A5
E3
A4
B4
B5
B6
B7
A8
B8
A11
C8
NC
LB#s WP#/ACC WE#
C4 C5 C6
UB#s RESET# CE2s
C2
A3
D2
A2
E2
A1
F2
A0
C7
C9
A15
D9
A19
D7
A12
D8
D4
A18
E4
D5
D6
RY/BY#
NC
A9
A13
E8
NC
E9
E1
NC
F1
E7
E10
NC
A17
F4
A10
F7
A14
F8
NC
F9
F3
F10
NC
VSS
NC
DQ1
DQ6
SA
A16
G2
G3
G4
G5
G6
G7
G8
G9
CE#f
OE#
DQ9
DQ3
DQ4
DQ13 DQ15/A
-
1
CIOf
H9
H2
H3
H4
H5
H6
H7
H8
CE1#s
DQ0
V
CCf
J5
VCC
s
DQ12
DQ7
VSS
DQ10
J8
J3
J4
J7
J6
CIOs
K6
DQ14
DQ8
DQ2
DQ11
K5
DQ5
K1
K10
NC
NC
NC
NC
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compro-
mised if the package body is exposed to temperatures
above 150°C for prolonged periods of time.
Special Handling Instructions for FBGA
Package
Special handling is required for Flash Memory prod-
ucts in FBGA packages.
Am41DL16x4D
7
P R E L I M I N A R Y
PIN DESCRIPTION
LOGIC SYMBOL
A17–A0
= 18 Address Inputs (Common)
A–1, A19–A18 = 3 Address Inputs (Flash)
18
A0–A17
SA
= Highest Order Address Input
(SRAM) Byte mode
DQ15–DQ0
CE#f
= 16 Data Inputs/Outputs (Common)
= Chip Enable (Flash)
A–1, A18–A19
SA
16 or 8
CE#s
= Chip Enable (SRAM)
CE#f
DQ15–DQ0
OE#
= Output Enable (Common)
= Write Enable (Common)
= Ready/Busy Output
CE1#s
CE2s
WE#
RY/BY#
UB#s
RY/BY#
OE#
= Upper Byte Control (SRAM)
= Lower Byte Control (SRAM)
WE#
LB#s
WP#/ACC
RESET#
UB#s
CIOf
= I/O Configuration (Flash)
CIOf = VIH = Word mode (x16),
CIOf = VIL = Byte mode (x8)
CIOs
= I/O Configuration (SRAM)
CIOs = VIH = Word mode (x16),
CIOs = VIL = Byte mode (x8)
LB#s
CIOf
CIOs
RESET#
= Hardware Reset Pin, Active Low
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
V
CCf
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
VCC
VSS
NC
s
= SRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
8
Am41DL16x4D
P R E L I M I N A R Y
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am41DL16x
4
D
T
70
I
T
TAPE AND REEL
T
S
=
=
7 inches
13 inches
TEMPERATURE RANGE
Industrial (–40°C to +85°C)
I
=
FLASH SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
B
=
=
Top Sector
Bottom Sector
FLASH PROCESS TECHNOLOGY
CS49S
D
=
SRAM DEVICE DENSITY
4 Mbits
4
=
AMD DEVICE NUMBER/DESCRIPTION
Am41DL16x4D
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL16xD 16 Megabit (1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash
Memory and 4 Mbit (512 K x 8-Bit/ 256 K x 16-Bit) Static RAM
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
Order Number
Package Marking
Am41DL1614DT70I
Am41DL1614DB70I
M410000000
M410000001
Am41DL1614DT85I
Am41DL1614DB85I
M410000002
M410000003
Am41DL1624DT70I
Am41DL1624DB70I
M410000004
M410000005
Am41DL1624DT85I
Am41DL1624DB85I
M410000006
M410000007
T, S
Am41DL1634DT70I
Am41DL1634DB70I
M410000008
M410000009
Am41DL1634DT85I
Am41DL1634DB85I
M41000000A
M41000000B
Am41DL1644DT70I
Am41DL1644DB70I
M41000000C
M41000000D
Am41DL1644DT85I
Am41DL1644DB85I
M41000000E
M41000000F
Am41DL16x4D
9
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
10
Am41DL16x4D
P R E L I M I N A R Y
Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH; SRAM Word Mode, CIOs = VCC
Operation
(Notes 1, 2)
WP#/ACC DQ7– DQ15–
CE#f CE1#s CE2s OE# WE# SA
Addr. LB#s UB#s RESET#
(Note 4)
DQ0
DQ8
H
X
H
X
H
X
X
L
X
L
X
L
Read from Flash
L
L
H
X
H
L
X
X
X
AIN
AIN
X
X
X
X
X
X
X
H
L/H
DOUT
DOUT
Write to Flash
Standby
L
H
(Note 4)
H
DIN
DIN
VCC
0.3 V
±
VCC ±
0.3 V
X
High-Z High-Z
High-Z High-Z
High-Z High-Z
H
H
H
H
X
X
X
X
L
X
L
Output Disable
L
L
H
H
L/H
X
H
X
H
X
L
Flash Hardware
Reset
X
L
X
X
X
X
X
X
X
L
L/H
X
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Protect
(Note 5)
H
L
X
X
VID
L/H
DIN
X
X
X
H
X
L
X
L
SADD,
A6 = H,
A1 = H,
A0 = L
Sector Unprotect
(Note 5)
L
X
H
H
X
L
L
X
H
X
X
X
X
X
X
X
VID
VID
H
(Note 6)
(Note 6)
X
DIN
H
X
X
L
Temporary Sector
Unprotect
X
DIN
High-Z
DOUT
L
H
L
L
L
DOUT
Read from SRAM
Write to SRAM
L
L
H
H
AIN
High-Z DOUT
DOUT High-Z
H
L
L
DIN
High-Z
DIN
DIN
DIN
H
X
L
X
AIN
H
L
L
H
X
H
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “The autoselect
mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on
DQ7–DQ0. The autoselect codes can be accessed in-system through the command register. Refer to the Autoselect Command
Sequence section for more information.Sector/Sector Block Protection and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “The autoselect mode provides
manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. The
autoselect codes can be accessed in-system through the command register. Refer to the Autoselect Command Sequence section
for more information.Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
Am41DL16x4D
11
P R E L I M I N A R Y
Table 2. Device Bus Operations—Flash Word Mode, CIOf = VIH; SRAM Byte Mode, CIOs = VSS
Operation
(Notes 1, 2)
LB#s
(Note 3) (Note 3)
UB#s
WP#/ACC DQ7– DQ15–
CE#f CE1#s CE2s OE# WE# SA Addr.
RESET#
(Note 4)
DQ0
DQ8
H
X
H
X
H
X
L
X
L
Read from Flash
Write to Flash
L
L
H
L
X
X
AIN
AIN
X
X
X
X
H
L/H
DOUT
DOUT
X
L
L
H
H
(Note 3)
DIN
DIN
X
L
VCC
0.3 V
±
VCC ±
0.3 V
Standby
X
H
X
X
H
X
X
SA
X
X
X
X
X
DNU
X
X
DNU
X
H
High-Z High-Z
High-Z High-Z
High-Z High-Z
Output Disable
L
H
X
L
H
L/H
L/H
H
X
H
Flash Hardware
Reset
X
L
L
X
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Protect
(Note 5)
H
L
X
X
X
VID
L/H
DIN
X
X
H
X
L
X
L
SADD,
A6 = H,
A1 = H,
A0 = L
Sector Unprotect
(Note 5)
L
H
X
L
X
X
X
X
X
X
VID
(Note 6)
(Note 6)
DIN
DIN
X
H
X
L
X
L
Temporary Sector
Unprotect
X
X
AIN
VID
High-Z
Read from SRAM
Write to SRAM
H
H
H
H
L
H
L
SA
SA
AIN
AIN
X
X
X
X
H
H
X
X
DOUT High-Z
DIN High-Z
L
X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out, DNU = Do Not Use
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “The autoselect
mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on
DQ7–DQ0. The autoselect codes can be accessed in-system through the command register. Refer to the Autoselect Command
Sequence section for more information.Sector/Sector Block Protection and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “The autoselect mode provides
manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. The
autoselect codes can be accessed in-system through the command register. Refer to the Autoselect Command Sequence section
for more information.Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
12
Am41DL16x4D
P R E L I M I N A R Y
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = VSS; SRAM Word Mode, CIOs = VCC
Operation
(Notes 1, 2)
LB#s
(Note 3) (Note 3)
UB#s
WP#/ACC DQ7– DQ15–
CE#f CE1#s CE2s OE# WE# SA
Addr.
RESET#
(Note 4)
DQ0
DQ8
H
X
H
X
H
X
X
L
X
L
X
L
Read from Flash
Write to Flash
Standby
L
L
H
X
H
X
H
L
X
X
X
X
X
AIN
X
X
X
X
X
X
H
L/H
DOUT
High-Z
L
AIN
X
H
(Note 3)
H
DIN
High-Z
VCC
0.3 V
±
VCC ±
0.3 V
X
H
X
High-Z High-Z
High-Z High-Z
High-Z High-Z
L
X
L
Output Disable
L
L
H
X
H
L/H
X
H
X
H
X
L
Flash Hardware
Reset
X
L
X
X
X
X
L
L/H
X
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Protect
(Note 5)
H
L
X
X
VID
L/H
DIN
X
X
H
X
L
X
L
SADD,
A6 = L,
A1 = H,
A0 = L
Sector
Unprotect
(Note 5)
L
X
H
H
X
L
L
X
H
X
X
X
X
X
X
X
VID
VID
H
(Note 6)
(Note 6)
X
DIN
X
Temporary
Sector
Unprotect
H
X
x
AIN
DIN
High-Z
L
L
H
L
L
L
DOUT
High-Z
DOUT
DIN
DOUT
DOUT
High-Z
DIN
Read from
SRAM
L
L
H
H
AIN
H
L
L
Write to SRAM
H
X
L
X
AIN
H
L
L
H
X
High-Z
DIN
DIN
H
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In, DOUT
Data Out
=
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “The autoselect
mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on
DQ7–DQ0. The autoselect codes can be accessed in-system through the command register. Refer to the Autoselect Command
Sequence section for more information.Sector/Sector Block Protection and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “The autoselect mode provides
manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. The
autoselect codes can be accessed in-system through the command register. Refer to the Autoselect Command Sequence section
for more information.Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
Am41DL16x4D
13
P R E L I M I N A R Y
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = VIL; SRAM Byte Mode, CIOs = VSS
Operation
(Notes 1, 2)
LB#s
(Note 3) (Note 3)
UB#s
WP#/ACC DQ7– DQ15–
CE#f CE1#s CE2s OE# WE# SA
Addr.
RESET#
(Note 4)
DQ0
DQ8
H
X
H
X
H
X
L
X
L
Read from Flash
Write to Flash
L
L
H
L
X
X
AIN
X
X
X
X
H
L/H
DOUT
High-Z
X
L
L
H
AIN
H
(Note 3)
DIN
High-Z
X
L
VCC
0.3 V
±
VCC ±
0.3 V
Standby
X
H
X
X
H
X
X
SA
X
X
X
X
X
DNU
X
X
DNU
X
H
High-Z High-Z
High-Z High-Z
High-Z High-Z
Output Disable
H
H
X
L
H
L/H
L/H
H
X
H
Flash Hardware
Reset
X
L
L
X
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Protect
(Note 5)
H
L
X
X
X
VID
L/H
DIN
X
X
H
X
L
X
L
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Unprotect
(Note 5)
L
H
X
L
X
X
X
X
X
X
VID
(Note 6)
(Note 6)
DIN
X
H
X
L
X
L
Temporary
Sector Unprotect
X
X
AIN
VID
DIN
High-Z
Read from SRAM
Write to SRAM
H
H
H
H
L
H
L
SA
SA
AIN
AIN
X
X
X
X
H
H
X
X
DOUT
DIN
High-Z
High-Z
L
X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In, DOUT
Data Out, DNU = Do Not Use
=
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “The autoselect
mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on
DQ7–DQ0. The autoselect codes can be accessed in-system through the command register. Refer to the Autoselect Command
Sequence section for more information.Sector/Sector Block Protection and Unprotection”.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “The autoselect mode provides
manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. The
autoselect codes can be accessed in-system through the command register. Refer to the Autoselect Command Sequence section
for more information.Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
14
Am41DL16x4D
P R E L I M I N A R Y
An erase operation can erase one sector, multiple sec-
Word/Byte Configuration
tors, or the entire device. Tables 6–7 indicate the
address space that each sector occupies. The device
address space is divided into two banks: Bank 1 con-
tains the boot/parameter sectors, and Bank 2 contains
the larger, code sectors of uniform size. A “bank ad-
dress” is the address bits required to uniquely select a
bank. Similarly, a “sector address” is the address bits
required to uniquely select a sector.
The CIOf pin controls whether the device data I/O pins
operate in the byte or word configuration. If the CIOf
pin is set at logic ‘1’, the device is in word configura-
tion, DQ0–DQ15 are active and controlled by CE# and
OE#.
If the CIOf pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE#f and OE# pins to VIL. CE#f is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. The CIOf pin determines
whether the device outputs array data in words or
bytes.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the WP#/ACC pin returns the device to nor-
mal operation. Note that the WP#/ACC pin must not
be at VHH for operations other than accelerated pro-
gramming, or device damage may result. In addition,
the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavior of the device may result.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
See “Requirements for Reading Array Data” for more
information. Refer to the AC Flash Read-Only Opera-
tions table for timing specifications and to Figure 14 for
the timing diagram. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more
information.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE#f to VIL, and OE# to VIH.
For program operations, the CIOf pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased). Figure 21 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. ICC6 and ICC7 in the DC Characteristics table
represent the current specifications for read-while-pro-
gram and read-while-erase, respectively.
The device features an Unlock Bypass mode to facil-
itate faster programming. Once a bank enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Configuration” section has details on pro-
gramming data to the device using both standard and
Unlock Bypass command sequences.
Am41DL16x4D
15
P R E L I M I N A R Y
RESET# pin is driven low for at least a period of tRP,
Standby Mode
the device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE#f and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE#f and RESET# are held at VIH, but not
within VCC ± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The de-
vice requires standard access time (tCE) for read
access when the device is in either of these standby
modes, before it is ready to read data.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS ± 0.3 V, the de-
vice draws CMOS standby current (ICC4). If RESET# is
held at VIL but not within VSS ± 0.3 V, the standby cur-
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of tREADY (not during Embed-
ded Algorithms). The system can read data tRH after
the RESET# pin returns to VIH.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for tACC
+
30 ns. The automatic sleep mode is independent of
the CE#f, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
ICC4 in the DC Characteristics table represents the
automatic sleep mode current specification.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 15 for the timing diagram.
Output Disable Mode
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 5. Device Bank Division
Bank 1
Bank 2
Sector Sizes
Device
Part Number
Megabits
Sector Sizes
Megabits
Thirty-one
64 Kbyte/32 Kword
Am29DL161D
0.5 Mbit
Eight 8 Kbyte/4 Kword
15.5 Mbit
Eight 8 Kbyte/4 Kword,
three 64 Kbyte/32 Kword
Twenty-eight
64 Kbyte/32 Kword
Am29DL162D
Am29DL163D
Am29DL164D
2 Mbit
4 Mbit
8 Mbit
14 Mbit
12 Mbit
8 Mbit
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
Twenty-four
64 Kbyte/32 Kword
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
Sixteen
64 Kbyte/32 Kword
16
Am41DL16x4D
P R E L I M I N A R Y
Table 6. Sector Addresses for Top Boot Sector Devices
Sector Address
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
A19–A12
Address Range
SA0
SA1
00000xxx
00001xxx
00010xxx
00011xxx
00100xxx
00101xxx
00110xxx
00111xxx
01000xxx
01001xxx
01010xxx
01011xxx
01100xxx
01101xxx
01110xxx
01111xxx
10000xxx
10001xxx
10010xxx
10011xxx
10100xxx
10101xxx
10110xxx
10111xxx
11000xxx
11001xxx
11010xxx
11011xxx
11100xxx
11101xxx
11110xxx
11111000
11111001
11111010
11111011
11111100
11111101
11111110
11111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1F1FFFh
1F2000h-1F3FFFh
1F4000h-1F5FFFh
1F6000h-1F7FFFh
1F8000h-1F9FFFh
1FA000h-1FBFFFh
1FC000h-1FDFFFh
1FE000h-1FFFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–F8FFFh
F9000h–F9FFFh
FA000h–FAFFFh
FB000h–FBFFFh
FC000h–FCFFFh
FD000h–FDFFFh
FE000h–FEFFFh
FF000h–FFFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Note: The address range is A19:A-1 in byte mode (CIOf=VIL) or A19:A0 in word mode (CIOf=VIH). The bank address bits are A19–15 for
Am29DL161DT, A19–A17 for Am29DL162DT, A19 and A18 for Am29DL163DT, and A19 for Am29DL164DT.
Table 7. SecSi Sector Addresses for Top Boot Devices
Sector Address
Sector
Size
(x8)
(x16)
Address Range
Device
A19–A12
Address Range
Am29DL16xDT
11111XXX
64/32
1F0000h-1FFFFFh F8000h–FFFFFh
Am41DL16x4D
17
P R E L I M I N A R Y
Table 8. Sector Addresses for Bottom Boot Sector Devices
Sector Address
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
A19–A12
Address Range
SA0
SA1
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001XXX
00010XXX
00011XXX
00100XXX
00101XXX
00110XXX
00111XXX
01000XXX
01001XXX
01010XXX
01011XXX
01100XXX
01101XXX
01110XXX
01111XXX
10000XXX
10001XXX
10010XXX
10011XXX
10100XXX
10101XXX
10110XXX
10111XXX
11000XXX
11001XXX
11010XXX
11011XXX
11100XXX
11101XXX
11110XXX
11111XXX
8/4
000000h-001FFFh
002000h-003FFFh
004000h-005FFFh
006000h-007FFFh
008000h-009FFFh
00A000h-00BFFFh
00C000h-00DFFFh
00E000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
00000h-00FFFh
01000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-04FFFh
05000h-05FFFh
06000h-06FFFh
07000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
40000h-47FFFh
48000h-4FFFFh
50000h-57FFFh
58000h-5FFFFh
60000h-67FFFh
68000h-6FFFFh
70000h-77FFFh
78000h-7FFFFh
80000h-87FFFh
88000h-8FFFFh
90000h-97FFFh
98000h-9FFFFh
A0000h-A7FFFh
A8000h-AFFFFh
B0000h-B7FFFh
B8000h-BFFFFh
C0000h-C7FFFh
C8000h-CFFFFh
D0000h-D7FFFh
D8000h-DFFFFh
E0000h-E7FFFh
E8000h-EFFFFh
F0000h-F7FFFh
F8000h-FFFFFh
8/4
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Note: The address range is A19:A-1 in byte mode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH). The bank address bits are A19–A15 for
Am29DL161DB, A19–A17 for Am29DL162DB, A19 and A18 for Am29DL163DB, and A19 for Am29DL164DB.
Table 9. SecSi Addresses for Bottom Boot Devices
Sector Address
Sector
Size
(x8)
(x16)
Address Range
Device
A19–A12
Address Range
Am29DL16xDB
00000XXX
64/32 000000h-00FFFFh 00000h-07FFFh
18
Am41DL16x4D
P R E L I M I N A R Y
Table 11. Bottom Boot Sector/Sector Block
Addresses for Protection/Unprotection
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. The au-
toselect codes can be accessed in-system through the
command register. Refer to the Autoselect Command
Sequence section for more information.Sector/Sector
Block Protection and Unprotection
Sector / Sector
Block
A19–A12
Sector / Sector Block Size
SA38
11111XXX
64 Kbytes
11110XXX,
11101XXX,
11100XXX
SA37-SA35
192 (3x64) Kbytes
SA34-SA31
SA30-SA27
SA26-SA23
SA22-SA19
SA18-SA15
SA14-SA11
110XXXXX
101XXXXX
100XXXXX
011XXXXX
010XXXXX
001XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Tables
10 and 11).
00001XXX,
00010XXX,
00011XXX
SA10-SA8
192 (3x64) Kbytes
Table 10. Top Boot Sector/Sector Block
Addresses for Protection/Unprotection
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
00000111
00000110
00000101
00000100
00000011
00000010
00000001
00000000
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
Sector / Sector
Block
A19–A12
Sector / Sector Block Size
SA0
00000XXX
64 Kbytes
00001XXX,
00010XXX,
00011XXX
SA1-SA3
192 (3x64) Kbytes
SA4-SA7
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
001XXXXX
010XXXXX
011XXXXX
100XXXXX
101XXXXX
110XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors. Sector protection and unprotection can be im-
plemented as follows.
11100XXX,
11101XXX,
11110XXX
SA28-SA30
192 (3x64) Kbytes
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
11111000
11111001
11111010
11111011
11111100
11111101
11111110
11111111
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
Sector protection/unprotection requires VID on the RE-
SET# pin only, and can be implemented either
in-system or via programming equipment. Figure 2
shows the algorithms and Figure 26 shows the timing
diagram. This method uses standard microprocessor
bus cycle timing. For sector unprotect, all unprotected
sectors must first be protected prior to the first sector
unprotect write cycle. Note that the sector unprotect
algorithm unprotects all sectors in parallel. All previ-
ously protected sectors must be individually
re-protected. To change data in protected sectors effi-
ciently, the temporary sector un protect function is
available. See “Temporary Sector/Sector Block
Unprotect”.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is pro-
tected or unprotected. See the Autoselect Mode
section for details.
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting certain boot sectors without
using VID. This function is one of two provided by the
WP#/ACC pin.
Am41DL16x4D
19
P R E L I M I N A R Y
If the system asserts VIL on the WP#/ACC pin, the de-
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID (8.5 V – 12.5 V). During this mode,
formerly protected sectors can be programmed or
erased by selecting the sector addresses. Once VID is
removed from the RESET# pin, all the previously pro-
tected sectors are protected again. Figure 1 shows the
algorithm, and Figure 25 shows the timing diagrams,
for this feature.
vice disables program and erase functions in the two
“outermost” 8 Kbyte boot sectors independently of
whether those sectors were protected or unprotected
using the method described in “The autoselect mode
provides manufacturer and device identification, and
sector protection verification, through identifier codes
output on DQ7–DQ0. The autoselect codes can be ac-
cessed in-system through the command register.
Refer to the Autoselect Command Sequence section
for more information.Sector/Sector Block Protection
and Unprotection”. The two outermost 8 Kbyte boot
sectors are the two sectors containing the lowest ad-
dresses in a top-boot-configured device, or the two
sectors containing the highest addresses in a
top-boot-configured device.
START
If the system asserts VIH on the WP#/ACC pin, the de-
vice reverts to whether the two outermost 8 Kbyte boot
sectors were last set to be protected or unprotected.
That is, sector protection or unprotection for these two
sectors depends on whether they were last protected
or unprotected using the method described in “The au-
toselect mode provides manufacturer and device
identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. The au-
toselect codes can be accessed in-system through the
command register. Refer to the Autoselect Command
Sequence section for more information.Sector/Sector
Block Protection and Unprotection”.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Note that the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may
result.
Notes:
1. All protected sectors unprotected (If WP#/ACC = VIL,
outermost boot sectors will remain protected).
Temporary Sector/Sector Block Unprotect
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Tables
10 and 11).
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
20
Am41DL16x4D
P R E L I M I N A R Y
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 µs
Wait 1 µs
unprotect address
No
No
First Write
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Note: The term “sector” in the figure applies to both sectors and sector blocks.
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms
Am41DL16x4D
21
P R E L I M I N A R Y
Customer Lockable: SecSi Sector NOT
SecSi (Secured Silicon) Sector Flash
Memory Region
Programmed or Protected At the Factory
If the security feature is not required, the SecSi Sector
can be treated as an additional Flash memory space,
expanding the size of the available Flash array by 64
Kbytes. Current version of this device has 64
Kbytes; future versions will have only 256 bytes.
This should be considered during system design.
The SecSi Sector can be read, programmed, and erased
as often as required. Note that the accelerated program-
ming (ACC) and unlock bypass functions are not
available when programming the SecSi Sector.
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 64 Kbytes in length, and
uses a SecSi Sector Indicator Bit to indicate whether
or not the SecSi Sector is locked when shipped from
the factory. This bit is permanently set at the factory
and cannot be changed, which prevents cloning of a
factory locked part. This ensures the security of the
ESN once the product is shipped to the field. Current
version of this device has 64 Kbytes; future ver-
sions will have only 256 bytes. This should be
considered during system design.
The SecSi Sector area can be protected using one of the
following procedures:
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RESET# may be at either VIH or VID. This
allows in-system protection of the without raising
any device pin to a high voltage. Note that this
method is only applicable to the SecSi Sector.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the SecSi Sector Indicator
Bit permanently set to a “1.” The customer-lockable
version is shipped with the unprotected, allowing cus-
tomers to utilize the that sector in any manner they
choose. The customer-lockable version has the SecSi
Sector Indicator Bit permanently set to a “0.” Thus, the
SecSi Sector Indicator Bit prevents customer-lockable
devices from being used to replace devices that are
factory locked.
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then use the alternate
method of sector protection described in the “The
autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on DQ7–DQ0. The autoselect
codes can be accessed in-system through the com-
mand register. Refer to the Autoselect Command Se-
quence section for more information.Sector/Sector Block
Protection and Unprotection”.
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the
addresses normally occupied by the boot sectors. This
mode of operation continues until the system issues
the Exit SecSi Sector command sequence, or until
power is removed from the device. On power-up, or
following a hardware reset, the device reverts to send-
ing commands to the boot sectors.
Once the SecSi Sector is locked and verified, the sys-
tem must write the Exit SecSi Sector Region
command sequence to return to reading and writing
the remainder of the array.
The SecSi Sector protection must be used with cau-
tion since, once protected, there is no procedure
available for unprotecting the SecSi Sector area and
none of the bits in the SecSi Sector memory space
can be modified in any way.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In a factory locked device, the SecSi Sector is pro-
tected when the device is shipped from the factory.
The SecSi Sector cannot be modified in any way. The
device is available preprogrammed with a random, se-
cure ESN only
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 16 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
In devices that have an ESN, the Top Boot device will
have the 16-byte ESN, with the starting address of the
ESN will be at the bottom of the lowest 8 Kbyte boot
sector at addresses F8000h–F8007h in word mode (or
1F0000h–1F000Fh in byte mode).
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
22
Am41DL16x4D
P R E L I M I N A R Y
and all internal program/erase circuits are disabled,
and the device resets to reading array data. Subse-
quent writes are ignored until VCC is greater than VLKO
The system must provide the proper signals to the
control pins to prevent unintentional writes when VCC
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
.
is greater than VLKO
.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The sys-
tem can read CFI information at the addresses given
in Tables 12–15. To terminate reading CFI data, the
system must write the reset command. The CFI Query
mode is not accessible when the device is executing
an Embedded Program or embedded erase algorithm.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#f
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE#f = VIH or WE# = VIH. To initiate a write cycle,
CE#f and WE# must be a logical zero while OE# is a
logical one.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 12–15. The
system must write the reset command to return the de-
vice to the autoselect mode.
Power-Up Write Inhibit
If WE# = CE#f = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/prod-
ucts/nvd/overview/cfi.html. Alternatively, contact an
AMD representative for copies of these documents.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
Table 12. CFI Query Identification String
Addresses
(Word Mode)
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Am41DL16x4D
23
P R E L I M I N A R Y
Table 13. System Interface String
Addresses
(Word Mode)
Data
0027h
0036h
Description
V
CC Min. (write/erase)
1Bh
1Ch
D7–D4: volt, D3–D0: 100 millivolt
V
CC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
V
V
PP Min. voltage (00h = no VPP pin present)
PP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 14. Device Geometry Definition
Addresses
(Word Mode)
Data
Description
27h
0016h
Device Size = 2N byte
28h
29h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
0002h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
003Eh
0000h
0000h
0001h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
35h
36h
37h
38h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
24
Am41DL16x4D
P R E L I M I N A R Y
Table 15. Primary Vendor-Specific Extended Query
Addresses
(Word Mode)
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
0001h
Silicon Revision Number (Bits 7-2)
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
0002h
0001h
0001h
0004h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = 29LV800 mode
00XXh
(See Note)
Simultaneous Operation
00 = Not Supported, X= Number of Sectors in Bank 2 (Uniform Bank)
Burst Mode Type
00 = Not Supported, 01 = Supported
0000h
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
4Fh
0085h
0095h
000Xh
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
Note:
The number of sectors in Bank 2 is device dependent.
Am29DL161 = 1Fh
Am29DL162 = 1Ch
Am29DL163 = 18h
Am29DL164 = 10h
Am41DL16x4D
25
P R E L I M I N A R Y
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device
operations. Table 16 defines the valid register com-
mand sequences. Writing incorrect address and
data values or writing them in the improper se-
quence resets the device to reading array data.
which the system was writing to reading array data. If
the program command sequence is written to a bank
that is in the Erase Suspend mode, writing the reset
command returns that bank to the erase-sus-
pend-read mode. Once programming begins,
however, the device ignores reset commands until the
operation is complete.
All addresses are latched on the falling edge of WE#
or CE#f, whichever happens later. All data is latched
on the rising edge of WE# or CE#f, whichever hap-
pens first. Refer to the AC Characteristics section for
timing diagrams.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to reading array data. If a
bank entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns
that bank to the erase-suspend-read mode.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to read-
ing array data (or erase-suspend-read mode if that
bank was in Erase Suspend).
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read
data from any non-erase-suspended sector within the
same bank. After completing a programming operation
in the Erase Suspend mode, the system may once
again read array data with the same exception. See
the Erase Suspend/Erase Resume Commands sec-
tion for more information.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Table 16 shows the address and data requirements.
The autoselect command sequence may be written to
an address within a bank that is either in the read or
erase-suspend-read mode. The autoselect command
may not be written while the device is actively pro-
gramming or erasing in the other bank.
The system must issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the
next section, Reset Command, for more information.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the au-
toselect command. The bank then enters the
autoselect mode. The system may read at any ad-
dress within the same bank any number of times
without initiating another autoselect command
sequence:
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Flash Read-Only Operations table provides the
read parameters, and Figure 14 shows the timing
diagram.
■ A read cycle at address (BA)XX00h (where BA is
Reset Command
the bank address) returns the manufacturer code.
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
■ A read cycle at address (BA)XX01h in word mode
(or (BA)XX02h in byte mode) returns the device
code.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the bank to which the sys-
tem was writing to reading array data. Once erasure
begins, however, the device ignores reset commands
until the operation is complete.
■ A read cycle to an address containing a sector ad-
dress (SA) within the same bank, and the address
02h on A7–A0 in word mode (or the address 04h on
A6–A-1 in byte mode) returns 01h if the sector is
protected, or 00h if it is unprotected. (Refer to Ta-
bles 6–7 for valid sector addresses).
The system must write the reset command to return to
reading array data (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the bank to
26
Am41DL16x4D
P R E L I M I N A R Y
DQ6 status bits to indicate the operation was success-
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
ful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
The system can access the SecSi Sector region by is-
suing the three-cycle Enter SecSi Sector command
sequence. The device continues to access the SecSi
Sector region until the system issues the four-cycle
Exit SecSi Sector command sequence. The Exit SecSi
Sector command sequence returns the device to nor-
mal operation. The SecSi Sector is not accessible
when the device is executing an Embedded Program
or Embedded Erase algorithm. Table 16 shows the ad-
dress and data requirements for both command
sequences. See also “SecSi (Secured Silicon) Sector
Flash Memory Region” for further information. Note
that a hardware reset (RESET#=VIL) will reset the de-
vice to reading array data.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to a bank faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
That bank then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 16 shows the require-
ments for the command sequence.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the CIOf pin. Programming
is a four-bus-cycle operation. The program command
sequence is initiated by writing two unlock write cy-
cles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or
timings. The device automatically provides internally
generated program pulses and verifies the pro-
grammed cell margin. Table 16 shows the address
and data requirements for the byteword program com-
mand sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need
only contain the data 00h. The bank then returns to
the reading array data.
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at VHH any operation
other than accelerated programming, or device dam-
age may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
When the Embedded Program algorithm is complete,
that bank then returns to reading array data and ad-
dresses are no longer latched. The system can
determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. Refer to the Write Oper-
ation Status section for information on these status
bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the Flash Erase and Program
Operations table in the AC Characteristics section for
parameters, and Figure 18 for timing diagrams.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and
Am41DL16x4D
27
P R E L I M I N A R Y
mediately terminates the erase operation. If that
occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
START
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Flash Erase and Program
Operations tables in the AC Characteristics section for
parameters, and Figure 20 section for timing
diagrams.
Write Program
Command Sequence
Sector Erase Command Sequence
Data Poll
from System
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then
followed by the address of the sector to be erased,
and the sector erase command. Table 16 shows the
address and data requirements for the sector erase
command sequence.
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
No
Increment Address
Last Address?
Yes
Programming
Completed
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than
50 µs, otherwise erasure may begin. Any sector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the
time-out period resets that bank to reading array
data. The system must rewrite the command se-
quence and any additional addresses and commands.
Note: See Table 16 for program command sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 16
shows the address and data requirements for the chip
erase command sequence.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete,
that bank returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. Refer to the Write Operation Status
section for information on these status bits.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing bank. The system can de-
termine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
28
Am41DL16x4D
P R E L I M I N A R Y
Refer to the Write Operation Status section for infor-
program operation using the DQ7 or DQ6 status bits,
just as in the standard Byte Program operation.
Refer to the Write Operation Status section for more
information.
mation on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once that bank has returned to
reading array data, to ensure data integrity.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
To resume the sector erase operation, the system
must write the Erase Resume command. The bank
address of the erase-suspended bank is required
when writing this command. Further writes of the Re-
sume command are ignored. Another Erase Suspend
command can be written after the chip has resumed
erasing.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Flash Erase and Program
Operations tables in the AC Characteristics section for
parameters, and Figure 20 section for timing
diagrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. The bank address is required when writing
this command. This command is valid only during the
sector erase operation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase operation or Embedded Program
algorithm.
START
Write Erase
Command Sequence
(Notes 1, 2)
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation.
However, when the Erase Suspend command is writ-
ten during the sector erase time-out, the device
immediately terminates the time-out period and sus-
pends the erase operation.
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Yes
Erasure Completed
Notes:
1. See Table 16 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
After an erase-suspended program operation is com-
plete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the
Figure 4. Erase Operation
Am41DL16x4D
29
P R E L I M I N A R Y
Table 16. Command Definitions (Flash Word Mode)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Sixth
Addr Data Addr Data
Data
Addr
Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
Manufacturer ID
1
1
4
4
RA
XXX
555
555
RD
F0
AA
AA
2AA
2AA
55
55
(BA)555
(BA)555
90 (BA)X00
0001
Device ID
90 (BA)X01 see Table 17
SecSi Sector Factory
Protect (Note 9)
4
4
555
555
AA
AA
2AA
2AA
55
55
(BA)555
(BA)555
90 (BA)X03 0081/0001
Sector Protect Verify
(Note 10)
90 (SA)X02 0000/0001
88
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
555
555
555
555
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
555
90
A0
20
XXX
PA
00
PD
Unlock Bypass
Unlock Bypass Program
(Note 11)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 12)
Chip Erase
2
6
6
1
1
1
BA
555
555
BA
BA
55
90
AA
AA
B0
30
98
XXX
2AA
2AA
00
55
55
555
555
80
80
555
555
AA
AA
2AA
2AA
55
555
10
Sector Erase
55 SADD 30
Erase Suspend (Note 13)
Erase Resume (Note 14)
CFI Query (Note 15)
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE#f pulse, whichever happens first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
SADD = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE#f pulse, whichever happens
later.
Notes:
1. See Table 1 for description of bus operations.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
2. All values are in hexadecimal.
12. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
5. Unless otherwise noted, address bits A19–A11 are don’t cares.
6. No unlock or command cycles required when bank is in read
mode.
14. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
7. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information).
15. Command is valid when device is ready to read array data or when
device is in autoselect mode.
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. See the Autoselect Command Sequence section for
more information.
Table 17. Autoselect Device IDs (Word Mode)
Device
Autoselect Device ID
2236h (T), 2239h (B)
222Dh (T), 222Eh (B)
2228h (T), 222Bh (B)
2233h (T), 2235h (B)
Am29DL161D
Am29DL162D
Am29DL163D
Am29DL164D
9. The data is 80h for factory locked and 00h for not factory locked.
10. The data is 00h for an unprotected sector/sector block and 01h
for a protected sector/sector block.
T = Top Boot Sector, B = Bottom Boot Sector
30
Am41DL16x4D
P R E L I M I N A R Y
Table 18. Command Definitions (Flash Byte Mode)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Data
Fifth
Sixth
Addr Data Addr Data Addr Data Addr
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
Manufacturer ID
1
1
4
6
RA
RD
F0
XXX
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
90
90
00
02
01
Device ID
see Table 19
SecSi Sector Factory
Protect (Note 9)
(BA)
AAA
(BA)
X06
4
4
AAA
AAA
AA
AA
555
555
55
55
90
90
81/01
00
01
Sector Protect Verify
(Note 10)
(SA)
X04
AAA
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
2
2
6
6
1
1
1
AAA
AAA
AAA
AAA
XXX
XXX
AAA
AAA
BA
AA
AA
AA
AA
A0
90
555
555
555
555
PA
55
55
55
55
PD
00
55
55
AAA
AAA
AAA
AAA
88
90
A0
20
XXX
PA
00
PD
Unlock Bypass
Unlock Bypass Program (Note 11)
Unlock Bypass Reset (Note 12)
Chip Erase
XXX
555
555
AA
AA
B0
30
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
AAA
10
Sector Erase
55 SADD 30
Erase Suspend (Note 13)
Erase Resume (Note 14)
CFI Query (Note 15)
BA
55
98
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE#f pulse, whichever happens first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
SADD = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE#f pulse, whichever happens
later.
Notes:
1. See Table 1 for description of bus operations.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
2. All values are in hexadecimal.
14. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
15. Command is valid when device is ready to read array data or when
device is in autoselect mode.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
5. Unless otherwise noted, address bits A19–A11 are don’t cares.
6. No unlock or command cycles required when bank is in read
mode.
Table 19. Autoselect Device IDs (Byte Mode)
Device
Autoselect Device ID
36h (T), 39h (B)
7. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information).
Am29DL161D
Am29DL162D
Am29DL163D
Am29DL164D
2Dh (T), 2Eh (B)
28h (T), 2Bh (B)
33h (T), 35h (B)
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. Data bits DQ15–DQ8 are don’t care. See the
Autoselect Command Sequence section for more information.
T = Top Boot Sector, B = Bottom Boot Sector
9. The data is 80h for factory locked and 00h for not factory locked.
10. The data is 00h for an unprotected sector/sector block and 01h
for a protected sector/sector block.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
12. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
Am41DL16x4D
31
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7. Table 20 and the following subsec-
tions describe the function of these bits. DQ7 and DQ6
each offer a method for determining whether a pro-
gram or erase operation is complete or in progress.
The device also provides a hardware-based output
signal, RY/BY#, to determine whether an Embedded
Program or Erase operation is in progress or has been
completed.
invalid. Valid data on DQ0–DQ7 will appear on suc-
cessive read cycles.
Table 20 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm. Figure 22
in the AC Characteristics section shows the Data#
Polling timing diagram.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Program or Erase
algorithm is in progress or completed, or whether a
bank is in Erase Suspend. Data# Polling is valid after
the rising edge of the final WE# pulse in the command
sequence.
Read DQ7–DQ0
Addr = VA
Yes
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then that bank returns to reading
array data.
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Yes
DQ7 = Data?
No
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then
the bank returns to reading array data. If not all se-
lected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected. However, if the
system reads DQ7 at an address within a protected
sector, the status may not be valid.
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ0–DQ6 may be still
DQ7 may change simultaneously with DQ5.
Figure 5. Data# Polling Algorithm
32
Am41DL16x4D
P R E L I M I N A R Y
DQ6 also toggles during the erase-suspend-program
RY/BY#: Ready/Busy#
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
Table 20 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 23 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 24 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
pull-up resistor to VCC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is reading array data, the standby
mode, or one of the banks is in the erase-sus-
pend-read mode.
START
Table 20 shows the outputs for RY/BY#.
Read DQ7–DQ0
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE#f to control the read cycles. When the operation is
complete, DQ6 stops toggling.
Yes
No
DQ5 = 1?
Yes
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
Read DQ7–DQ0
Twice
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data#
Polling).
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
Figure 6. Toggle Bit Algorithm
Am41DL16x4D
33
P R E L I M I N A R Y
cles, determining the status as described in the
DQ2: Toggle Bit II
previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system
must start at the beginning of the algorithm when it re-
turns to determine the status of the operation (top of
Figure 6).
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ5: Exceeded Timing Limits
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE#f to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 20 to compare out-
puts for DQ2 and DQ6.
DQ5 indicates whether the program or erase time
has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1,” indicating
that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 23 shows the toggle bit timing diagram. Figure
24 shows the differences between DQ2 and DQ6 in
graphical form.
Under both these conditions, the system must write
the reset command to return to reading array data (or
to the erase-suspend-read mode if a bank was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
Reading Toggle Bits DQ6/DQ2
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
Table 20 shows the status of DQ3 relative to the other
status bits.
34
Am41DL16x4D
P R E L I M I N A R Y
Table 20. Write Operation Status
DQ7
(Note 2)
DQ5
(Note 1)
DQ2
(Note 2)
Status
DQ6
DQ3
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
DQ7#
0
Toggle
Toggle
0
0
N/A
1
No toggle
Toggle
0
0
Standard
Mode
1
No toggle
0
N/A
Toggle
1
Suspended Sector
Erase-Suspend-
Read
Erase
Suspend
Mode
Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
Am41DL16x4D
35
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . –40°C to +85°C
VCCf/VCCs Supply Voltage
Voltage with Respect to Ground
VCCf/VCCs for standard voltage range . . 2.7 V to 3.3 V
VCCf/VCCs (Note 1) . . . . . . . . . . . .–0.3 V to +4.0 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
OE# and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 7. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 8.
2. Minimum DC input voltage on pins OE#, RESET#, and
WP#/ACC is –0.5 V. During voltage transitions, OE#,
WP#/ACC, and RESET# may overshoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 7. Maximum DC
input voltage on pin RESET# is +12.5 V which may
overshoot to +14.0 V for periods up to 20 ns. Maximum
DC input voltage on WP#/ACC is +9.5 V which may
overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
20 ns
20 ns
20 ns
+0.8 V
VCC
+2.0 V
–0.5 V
–2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 7. Maximum Negative
Overshoot Waveform
Figure 8. Maximum Positive
Overshoot Waveform
36
Am41DL16x4D
P R E L I M I N A R Y
DC CHARACTERISTICS
CMOS Compatible
Parameter
Parameter Description
Test Conditions
Min
Typ
Max
Unit
Symbol
VIN = VSS to VCC
CC = VCC max
,
ILI
Input Load Current
±1.0
35
µA
µA
µA
V
ILIT
RESET# Input Load Current
Output Leakage Current
VCC = VCC max; RESET# = 12.5 V
VOUT = VSS to VCC
,
ILO
±1.0
VCC = VCC max
VCC = VCC max
WP#/ACC = VACC max
,
ILIA
ACC Input Leakage Current
35
µA
5 MHz
1 MHz
10
2
16
4
Flash VCC Active Read Current
(Notes 1, 2)
CE#f = VIL, OE# = VIH,
Word Mode
ICC1
f
f
mA
Flash VCC Active Write Current
(Notes 2, 3)
ICC2
CE#f = VIL, OE# = VIH, WE# = VIL
15
0.2
0.2
0.2
30
5
mA
µA
µA
µA
VCCf = VCC max, CE#f, RESET#,
ICC3f
Flash VCC Standby Current (Note 2)
Flash VCC Reset Current (Note 2)
WP#/ACC = VCCf ± 0.3 V
VCCf = VCC max, RESET# = VSS
±
ICC4f
5
0.3 V, WP#/ACC = VCCf ± 0.3 V
Flash VCC Current Automatic Sleep
Mode (Notes 2, 4)
VCCf = VCC max, VIH = VCC ± 0.3 V;
ICC5f
5
VIL = VSS ± 0.3 V
Flash VCC Active
I
CC6f
Read-While-Program Current (Notes CE#f = VIL, OE# = VIH
1, 2)
21
21
17
45
45
35
mA
mA
mA
Flash VCC Active Read-While-Erase
CE#f = VIL, OE# = VIH
ICC7
f
f
Current (Notes 1, 2)
Flash VCC Active
ICC8
Program-While-Erase-Suspended
Current (Notes 2, 5)
CE#f = VIL, OE#f = VIH
CE#f = VIL, OE# = VIH
ACC pin
CC pin
CE1#s ≥ VCCs – 0.2V, CE2s ≥
CCs – 0.2V
5
10
30
mA
mA
IACC
ACC Accelerated Program Current
SRAM VCC Standby Current
V
15
I
CC4s
10
µA
V
I
CC5s
VIL
SRAM VCC Standby Current
Input Low Voltage
CE2s ≤ 0.2V
10
0.8
µA
V
–0.2
VIH
Input High Voltage
2.4
VCC + 0.2
V
Voltage for WP#/ACC Program
Acceleration and Sector
Protection/Unprotection
VHH
8.5
8.5
9.5
V
Voltage for Sector Protection,
Autoselect and Temporary Sector
Unprotect
VID
12.5
0.45
V
V
IOL = 4.0 mA, VCCf = VCCs =
VCC min
VOL
Output Low Voltage
I
OH = –2.0 mA, VCCf = VCCs =
0.85 x
VCC
VOH1
VOH2
VCC min
Output High Voltage
V
IOH = –100 µA, VCC = VCC min
VCC–0.4
Am41DL16x4D
37
P R E L I M I N A R Y
DC CHARACTERISTICS (Continued)
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
Flash Low VCC Lock-Out Voltage
(Note 5)
VLKO
2.3
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3.
ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
5. Not 100% tested.
SRAM DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Parameter Description
Input Leakage Current
Test Conditions
Min
–1.0
–1.0
Typ
Max
1.0
Unit
µA
ILI
VIN = VSS to VCC
CE1#s = VIH, CE2s = VIL or OE# =
IH or WE# = VIL, VIO= VSS to VCC
ILO
Output Leakage Current
1.0
µA
V
Cycle time = 1 µs, 100% duty,
IIO = 0 mA, CE1#s ≤ 0.2 V,
CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
ICC1
s
Average Operating Current
3
mA
mA
Cycle time = Min., IIO = 0 mA,
100% duty, CE1#s = VIL, CE2s =
VIH, VIN = VIL = or VIH
ICC2s
Average Operating Current
22
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
0.4
V
V
IOH = –1.0 mA
2.4
CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC
0.2 V (CE1#s controlled) or 0 V ≤
CE2 ≤ 0.2 V (CE2s controlled),
CIOs = VSS or VCC, Other input = 0
~ VCC
–
ISB1
Standby Current (CMOS)
10
µA
38
Am41DL16x4D
P R E L I M I N A R Y
DC CHARACTERISTICS
Zero-Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12
10
8
3.3 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
Am41DL16x4D
39
P R E L I M I N A R Y
TEST CONDITIONS
Table 21. Test Specifications
3.3 V
Test Condition
70, 85 ns
Unit
Output Load
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
0.0–3.0
Input timing measurement reference
levels
1.5
1.5
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
KS000010-PAL
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 12. Input Waveforms and Measurement Levels
40
Am41DL16x4D
P R E L I M I N A R Y
AC CHARACTERISTICS
SRAM CE#s Timing
Parameter
Test Setup
All Speed Options
Unit
JEDEC
Std
Description
—
tCCR
CE#s Recover Time
—
Min
0
ns
CE#f
tCCR
tCCR
CE1#s
CE2s
tCCR
tCCR
Figure 13. Timing Diagram for Alternating Between
SRAM to Flash
Am41DL16x4D
41
P R E L I M I N A R Y
AC CHARACTERISTICS
Flash Read-Only Operations
Parameter
Speed Options
Test Setup
Unit
JEDEC
tAVAV
Std
tRC
tACC
tCE
Description
70
70
70
70
30
85
85
85
85
35
Read Cycle Time (Note 1)
Min
Max
Max
Max
Max
Max
ns
ns
ns
ns
ns
ns
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
Address to Output Delay
CE#f, OE# = VIL
OE# = VIL
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
tOE
tDF
16
16
tDF
Output Hold Time From Addresses, CE#f or
OE#, Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold
tOEH
Toggle and
Data# Polling
Time (Note 1)
10
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 21 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#f
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
Output Valid
HIGH Z
HIGH Z
Outputs
RESET#
RY/BY#
0 V
Figure 14. Read Operation Timings
42
Am41DL16x4D
P R E L I M I N A R Y
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
Description
All Speed Options
Unit
JEDEC
Std
RESET# Pin Low (During Embedded Algorithms) to
Read Mode (See Note)
tReady
Max
Max
20
µs
RESET# Pin Low (NOT During Embedded Algorithms) to
Read Mode (See Note)
tReady
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#f, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#f, OE#
RESET#
tRP
Figure 15. Reset Timings
Am41DL16x4D
43
P R E L I M I N A R Y
AC CHARACTERISTICS
Flash Word/Byte Configuration (CIOf)
Parameter
Speed Options
JEDEC
Std
Description
70
85
Unit
ns
t
ELFL/tELFH CE#f to CIOf Switching Low or High
Max
Max
Min
5
tFLQZ
tFHQV
CIOf Switching Low to Output HIGH Z
CIOf Switching High to Output Active
25
70
30
85
ns
ns
CE#f
OE#
CIOf
tELFL
Data Output
Data Output
CIOf
Switching
DQ14–DQ0
(DQ14–DQ0)
(DQ7–DQ0)
from word
to byte
mode
Address
Input
DQ15
Output
DQ15/A-1
tFLQZ
tELFH
CIOf
CIOf
Switching
from byte
to word
Data Output
(DQ7–DQ0)
Data Output
(DQ14–DQ0)
DQ14–DQ0
mode
Address
Input
DQ15
Output
DQ15/A-1
tFHQV
Figure 16. CIOf Timings for Read Operations
CE#f
WE#
The falling edge of the last WE# signal
CIOf
tSET
(tAS
)
tHOLD (tAH
)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 17. CIOf Timings for Write Operations
Am41DL16x4D
44
P R E L I M I N A R Y
AC CHARACTERISTICS
Flash Erase and Program Operations
Parameter
Speed Options
Unit
JEDEC
tAVAV
Std
tWC
tAS
Description
Min
Min
Min
70
85
Write Cycle Time (Note 1)
Address Setup Time (WE# to Address)
70
85
ns
ns
tAVWL
0
Address Setup Time to OE# or CE#f low during toggle bit
polling
tASO
tAH
Min
Min
Min
15
45
0
ns
ns
ns
tWLAX
Address Hold Time (WE# to Address)
Address Hold Time From CE#f or OE# high during toggle bit
polling
tAHT
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
Max
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
sec
µs
ns
ns
Read
OE# Hold Time
0
tOEH
Toggle and Data# Polling
10
20
0
tOEPH
tGHEL
tGHWL
tWS
Output Enable High during toggle bit polling
Read Recovery Time Before Write (OE# High to CE#f Low)
Read Recovery Time Before Write (OE# High to WE# Low)
WE# Setup Time (CE#f to WE#)
tGHEL
tGHWL
tWLEL
tELWL
tEHWH
tWHEH
tWLWH
tELEH
tWHDL
0
0
tCS
CE#f Setup Time (WE# to CE#f)
0
tWH
WE# Hold Time (CE#f to WE#)
0
tCH
CE#f Hold Time (CE#f to WE#)
0
tWP
Write Pulse Width
30
30
35
35
tCP
CE#f Pulse Width
tWPH
tSR/W
Write Pulse Width High
0
0
Latency Between Read and Write Operations
tWHWH1
tWHWH1
tWHWH2
tWHWH1 Programming Operation (Note 2)
tWHWH1 Accelerated Programming Operation (Note 2)
tWHWH2 Sector Erase Operation (Note 2)
7
4
0.7
50
0
tVCS
tRB
VCCf Setup Time (Note 1)
Write Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
tBUSY
90
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
Am41DL16x4D
45
P R E L I M I N A R Y
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#f
OE#
tCH
tGHWL
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
tBUSY
tRB
RY/BY#
VCC
f
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 18. Program Operation Timings
VHH
VIL or VIH
WP#/ACC
VIL or VIH
tVHH
tVHH
Figure 19. Accelerated Program Timing Diagram
46
Am41DL16x4D
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
tWC
VA
Addresses
CE#f
2AAh
SADD
555h for chip erase
tAH
tGHWL
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
f
Notes:
1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. These waveforms are for the word mode.
Figure 20. Chip/Sector Erase Operation Timings
Am41DL16x4D
47
P R E L I M I N A R Y
AC CHARACTERISTICS
tWC
Valid PA
tWC
tRC
tWC
Valid PA
Valid RA
Valid PA
Addresses
tAH
tCPH
tACC
tCE
CE#f
tCP
tOE
OE#
tOEH
tGHWL
tWP
WE#
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
Data
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE#f Controlled Write Cycles
Figure 21. Back-to-back Read/Write Cycle Timings
tRC
Addresses
CE#f
VA
tACC
tCE
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ6–DQ0
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 22. Data# Polling Timings (During Embedded Algorithms)
48
Am41DL16x4D
P R E L I M I N A R Y
AC CHARACTERISTICS
tAHT
tAS
Addresses
CE#f
tAHT
tASO
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 23. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to
toggle DQ2 and DQ6.
Figure 24. DQ2 vs. DQ6
Am41DL16x4D
49
P R E L I M I N A R Y
AC CHARACTERISTICS
Temporary Sector/Sector Block Unprotect
Parameter
All Speed Options
Unit
JEDEC
Std
tVIDR
tVHH
Description
VID Rise and Fall Time (See Note)
VHH Rise and Fall Time (See Note)
Min
Min
500
250
ns
ns
RESET# Setup Time for Temporary
Sector/Sector Block Unprotect
tRSP
Min
Min
4
4
µs
µs
RESET# Hold Time from RY/BY# High for
Temporary Sector/Sector Block Unprotect
tRRB
Note: Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#f
WE#
tRRB
tRSP
RY/BY#
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram
50
Am41DL16x4D
P R E L I M I N A R Y
AC CHARACTERISTICS
VID
VIH
RESET#
SADD, A6,
A1, A0
Valid*
60h
Valid*
Valid*
Status
Sector/Sector Block Protect or Unprotect
Verify
40h
Data
60h
Sector/Sector Block Protect: 150 µs,
Sector/Sector Block Unprotect: 15 ms
1 µs
CE#f
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. SADD = Sector Address
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram
Am41DL16x4D
51
P R E L I M I N A R Y
AC CHARACTERISTICS
Alternate CE#f Controlled Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
Description
70
85
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time (WE# to Address)
Min
Min
70
85
tAVWL
0
15
45
0
ns
Address Setup Time to CE#f Low During Toggle
Bit Polling
tASO
tAH
Min
Min
Min
ns
ns
ns
tELAX
Address Hold Time
Address Hold time from CE#f or OE# High During
Toggle Bit Polling
tAHT
tDVEH
tEHDX
tDS
tDH
Data Setup Time
Data Hold Time
Min
Min
35
0
ns
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tWS
tWH
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
0
0
ns
ns
WE# Hold Time
tCP
CE#f Pulse Width
30
30
35
35
ns
tEHEL
tCPH
CE#f Pulse Width High
ns
tWHWH1
tWHWH1
tWHWH2
tWHWH1
tWHWH1
tWHWH2
Programming Operation (Note 2)
Accelerated Programming Operation (Note 2)
Sector Erase Operation (Note 2)
7
4
µs
µs
0.7
sec
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
52
Am41DL16x4D
P R E L I M I N A R Y
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SADD for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#f
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SADD = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings
Am41DL16x4D
53
P R E L I M I N A R Y
AC CHARACTERISTICS
SRAM Read Cycle
Speed Options
Parameter
Description
Symbol
Unit
70
70
70
70
35
70
85
85
85
85
45
85
tRC
tAA
CO1, tCO2
tOE
Read Cycle Time
Min
ns
ns
ns
ns
ns
Address Access Time
Chip Enable to Output
Output Enable Access Time
LB#s, UB#s to Valid Output
Max
Max
Max
Max
t
tBA
Chip Enable (CE1#s Low and CE2s High) to Low-Z
Output
tLZ1, tLZ2
Min
10
ns
tBLZ
tOLZ
UB#, LB# Enable to Low-Z Output
Output Enable to Low-Z Output
Min
Min
Min
Max
Min
Max
Min
Max
Min
10
5
ns
ns
0
t
HZ1, tHZ2
Chip disable to High-Z Output
ns
ns
25
0
tBHZ
UB#s, LB#s Disable to High-Z Output
25
0
tOHZ
tOH
Output Disable to High-Z Output
ns
ns
25
Output Data Hold from Address Change
10
15
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
Note: CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL
Figure 28. SRAM Read Cycle—Address Controlled
54
Am41DL16x4D
P R E L I M I N A R Y
AC CHARACTERISTICS
tRC
Address
tAA
tCO1
tOH
CS#1
CS2
tCO2
tBA
tHZ
UB#, LB#
OE#
tBHZ
tOE
tOLZ
tBLZ
tLZ
tOHZ
Data Out
High-Z
Data Valid
Figure 29. SRAM Read Cycle
Notes:
1. WE# = VIH, if CIOs is low, ignore UB#s/LB#s timing.
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
2. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device
interconnection.
Am41DL16x4D
55
P R E L I M I N A R Y
AC CHARACTERISTICS
SRAM Write Cycle
Speed Options
Unit
Parameter
Description
Symbol
70
70
60
85
85
70
tWC
tCw
tAS
Write Cycle Time
Min
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of Write
Address Setup Time
Min
Min
Min
Min
Min
Min
Min
Max
Min
Min
Min
0
tAW
tBW
tWP
tWR
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
60
60
50
70
70
60
Write Recovery Time
0
0
tWHZ
Write to Output High-Z
ns
20
30
25
35
tDW
tDH
tOW
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
ns
ns
ns
0
5
tWC
Address
tCW
(See Note 2)
tWR (See Note 3)
CS1#s
tAW
CS2s
tCW
(See Note 2)
tBW
UB#s, LB#s
tWP
(See Note 5)
WE#
tAS
(See Note 4)
tDH
tDW
Data In
Data Out
High-Z
Data Valid
High-Z
tBW
tOW
Data Undefined
Notes:
1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
2.
3.
4.
t
CW is measured from CE1#s going low to the end of write.
WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
AS is measured from the address valid to the beginning of write.
t
t
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 30. SRAM Write Cycle—WE# Control
56
Am41DL16x4D
P R E L I M I N A R Y
AC CHARACTERISTICS
tWC
Address
tAS (See Note 2 )
tCW
tWR (See Note 4)
(See Note 3)
CE1#s
tAW
CE2s
tBW
UB#s, LB#s
tWP
(See Note 5)
WE#
tDW
tDH
Data Valid
Data In
Data Out
High-Z
High-Z
Notes:
1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing.
2.
3.
4.
t
CW is measured from CE1#s going low to the end of write.
WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
AS is measured from the address valid to the beginning of write.
t
t
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 31. SRAM Write Cycle—CE1#s Control
Am41DL16x4D
57
P R E L I M I N A R Y
AC CHARACTERISTICS
tWC
Address
CE1#s
tCW
(See Note 2)
tWR (See Note 3)
tAW
tCW (See Note 2)
CE2s
tBW
UB#s, LB#s
tAS
tWP
(See Note 5)
(See Note 4)
WE#
tDW
tDH
Data In
Data Out
Data Valid
High-Z
High-Z
Notes:
1. UB#s and LB#s controlled, CIOs must be high.
2.
3.
4.
t
CW is measured from CE1#s going low to the end of write.
WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
AS is measured from the address valid to the beginning of write.
t
t
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 32. SRAM Write Cycle—UB#s and LB#s Control
58
Am41DL16x4D
P R E L I M I N A R Y
FLASH ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1) Max (Note 2)
Unit
sec
sec
µs
Comments
Sector Erase Time
0.7
27
5
15
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
Byte Program Time
Word Program Time
Accelerated Byte/Word Program Time
150
210
120
27
7
µs
4
µs
Excludes system level
overhead (Note 5)
Byte Mode
Word Mode
9
Chip Program Time
(Note 3)
6
18
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most byteswords
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytewords are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
16 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
FLASH LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including OE# and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
+100 mA
V
CC Current
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Parameter
Symbol
Test Setup
Typ
Max
Unit
Description
CIN
Input Capacitance
VIN = 0
VOUT = 0
VIN = 0
VIN = 0
11
12
14
17
14
16
16
20
pF
pF
pF
pF
COUT
CIN2
Output Capacitance
Control Pin Capacitance
WP#/ACC Pin Capacitance
CIN3
Note: 7.Test conditions TA = 25°C, f = 1.0 MHz.
FLASH DATA RETENTION
Parameter Description
Test Conditions
Min
10
Unit
Years
Years
150°C
125°C
Minimum Pattern Data Retention Time
20
Am41DL16x4D
59
P R E L I M I N A R Y
SRAM DATA RETENTION
Parameter
Symbol
Parameter Description
Min
Typ
Max
3.3
10
Unit
V
Test Setup
VDR
VCC for Data Retention
Data Retention Current
CS1#s ≥ VCC – 0.2 V (Note 1)
1.5
VCC = 3.0 V, CE1#s ≥ VCC – 0.2 V
(Note 1)
1.0
(Note 2)
IDR
µA
tSDR
tRDR
Data Retention Set-Up Time
Recovery Time
0
ns
ns
See data retention waveforms
tRC
Notes:
1. CE1#s ≥ VCC – 0.2 V, CE2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled), CIOs = VSS or VCC
.
2. Typical values are not 100% tested.
Data Retention Mode
tRDR
tSDR
VCC
2.7V
2.2V
VDR
CE1#s ≥ VCC
-0.2 V, CE2s ≥ VCC -0.2 V
CE1#s
GND
Figure 33. CE1#s Controlled Data Retention Mode
Data Retention Mode
VCC
2.7 V
CE2s
tSDR
tRDR
VDR
CE2s £ 0.2 V
0.4 V
GND
Figure 34. CE2s Controlled Data Retention Mode
Am41DL16x4D
60
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
FLA069—69-Ball Fine-Pitch Grid Array 8 x 11 mm
11.00 BSC
A
0.15 C
(2x)
DATUM B
8.00 BSC
Pin A1
Corner Index Mark
B
DATUM A
0.15 C
(2x)
0.97
0.20 C
0.08 C
1.40 (max)
1.07
C
0.20 (min)
7.20 BSC
0.40
0.80
10
9
8
7
6
5
4
3
2
1
0.40
7.20 BSC
0.80
K
J
H
G
F
E
D
C
B
A
0.25
0.35
(69x)
M
M
0.15
0.08
C A B
C
61
Am41DL16x4D
P R E L I M I N A R Y
REVISION SUMMARY
Revision A (October 24, 2001)
Initial release.
Trademarks
Copyright © 2001 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am41DL16x4D
62
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