AM41LV320MB10IS [SPANSION]
Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM; 堆叠式多芯片封装（ MCP ） 32兆位（ 4米×8位/ 2的M× 16位）闪存和4兆位（ 512K ×8位/ 256千×16位）静态RAM
| 型号： | AM41LV320MB10IS |
| 厂家： | 
SPANSION |
| 描述： | Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM |
| 文件： | 总67页 (文件大小：968K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Am41LV3204M
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 30119 Revision A Amendment +1 Issue Date June 10, 2003
PRELIMINARY
Am41LV3204M
Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash
Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
— 4-word/8-byte page read buffer
MCP Features
— 16-word/32-byte write buffer
■ Power supply voltage of 2.7 to 3.3 volt
■ Low power consumption (typical values at 3.0 V, 5
■ High Performance
MHz)
— Access time as fast as 100ns initial 30 ns page Flash
— 30 mA typical initial Page read current; 10 mA typical
70 ns SRAM
intra-Page read current
■ Package
— 50 mA typical erase/program current
— 69-Ball FBGA
— 1 µA typical standby mode current
— 8 x 10 x 1.2 mm
■ Operating Temperature
— –40°C to +85°C
SOFTWARE & HARDWARE FEATURES
■ Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
Flash Memory Features
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
ARCHITECTURAL ADVANTAGES
■ Single power supply operation
— 3 V for read, erase, and program operations
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
■ Manufactured on 0.23 µm MirrorBit process
technology
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
■ SecSi (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
■ Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of
changing code in locked sectors
— May be programmed and locked at the factory or by
the customer
— WP#/ACC input:
■ Flexible sector architecture
Write Protect input (WP#) protects top or bottom two
sectors regardless of sector protection settings
ACC (high voltage) accelerates programming time for
higher throughput during system production
— Sixty-three 32 Kword/64-kbyte sectors
— Eight 4 Kword/8-kbyte boot sectors
■ Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
— Hardware reset input (RESET#) resets device
SRAM Features
■ Minimum 100,000 erase cycle guarantee per sector
■ 20-year data retention at 125°C
■ Power dissipation
— Operating: 30 mA maximum
— Standby: 10 µA maximum
PERFORMANCE CHARACTERISTICS
■ High performance
■ CE1s# and CE2s Chip Select
■ Power down features using CE1s# and CE2s
■ Data retention supply voltage: 1.5 to 3.3 volt
— 100 ns access time
— 30 ns page read times
■ Byte data control: LB#s (DQ7–DQ0),
— 0.5 s typical sector erase time
UB#s (DQ15–DQ8)
— 15 µs typical write buffer word programming time:
16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
Publication# 30119 Rev: A Amendment/+1
Issue Date: June 10, 2003
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
Am29LV320MT Features
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The Am29LV320MT/B is a 32 Mbit, 3.0 volt single
power supply flash memory device organized as
2,097,152 words or 4,194,304 bytes. The device has
an 8/16-bit bus and can be programmed either in the
host system or in standard EPROM programmers.
Word mode data appears on DQ15–DQ0. The device
is designed to be programmed in-system with the
standard 3.0 volt VCC supply, and can also be pro-
grammed in standard EPROM programmers.
The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a
given sector to read or program any other sector and
then complete the erase operation. The Program
Suspend/Program Resume feature enables the host
system to pause a program operation in a given sector
to read any other sector and then complete the pro-
gram operation.
LV320MT/B has an access time of 100 ns. Note that
the access time has a specific operating voltage range
(VCC) as specified in the Product Selector Guide and
the Ordering Information sections. The device is of-
fered in a 69-ball Fine Pitch BGA.
The hardware RESET# pin terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The devices require only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The device reduces power consumption in the
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The Write Protect (WP#) feature protects the top or
bottom two sectors by asserting a logic low on the
WP#/ACC pin. The protected sector will still be pro-
tected even during accelerated programming.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
The SecSi (Secured Silicon) Sector provides a
128-word/256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to deter-
mine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
2
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Device Bus Operations—Flash Word Mode, CIOf = VIH,
DQ7: Data# Polling .................................................................35
Figure 8. Data# Polling Algorithm .................................................. 35
DQ6: Toggle Bit I ....................................................................36
Figure 9. Toggle Bit Algorithm........................................................ 37
DQ2: Toggle Bit II ................................................................... 37
Reading Toggle Bits DQ6/DQ2 ...............................................37
DQ5: Exceeded Timing Limits ................................................ 38
DQ3: Sector Erase Timer ....................................................... 38
DQ1: Write-to-Buffer Abort .....................................................38
Table 15. Write Operation Status ................................................... 38
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 39
Figure 10. Maximum Negative Overshoot Waveform ................... 39
Figure 11. Maximum Positive Overshoot Waveform..................... 39
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 39
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40
SRAM DC and Operating Characteristics. . . . . . 41
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 12. Test Setup.................................................................... 42
Table 16. Test Specifications ......................................................... 42
Key to Switching Waveforms. . . . . . . . . . . . . . . . 42
Figure 13. Input Waveforms and Measurement Levels ................. 42
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43
Flash Read-Only Operations .................................................43
Figure 14. Read Operation Timings ............................................... 43
Figure 15. Page Read Timings ...................................................... 44
Hardware Reset (RESET#) .................................................... 45
Figure 16. Reset Timings ............................................................... 45
Flash Erase and Program Operations .................................... 46
Figure 17. Program Operation Timings.......................................... 47
Figure 18. Accelerated Program Timing Diagram.......................... 47
Figure 19. Chip/Sector Erase Operation Timings .......................... 48
Figure 20. Data# Polling Timings (During Embedded Algorithms). 49
Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 50
Figure 22. DQ2 vs. DQ6................................................................. 50
Temporary Sector Unprotect .................................................. 51
Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 51
Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 52
Alternate CE# Controlled Erase and Program Operations ..... 53
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 54
SRAM Read Cycle ..................................................................55
Figure 26. SRAM Read Cycle—Address Controlled...................... 55
Figure 27. SRAM Read Cycle........................................................ 56
SRAM Write Cycle ..................................................................57
Figure 28. SRAM Write Cycle—WE# Control ................................ 57
Figure 29. SRAM Write Cycle—CE1#s Control ............................. 58
Figure 30. SRAM Write Cycle—UB#s and LB#s Control............... 59
Erase And Programming Performance. . . . . . . . 60
Flash Latchup Characteristics. . . . . . . . . . . . . . . 60
Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 61
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SRAM Data Retention. . . . . . . . . . . . . . . . . . . . . . 62
Figure 31. CE#1 Controlled Data Retention Mode......................... 62
Figure 32. CE2s Controlled Data Retention Mode......................... 62
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 63
TLB069—69-Ball Fine-pitch Ball Grid Array (FBGA)
SRAM Word Mode, CIOs = V ......................................................11
IL
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V ;
SS
SRAM Word Mode, CIOs = V .....................................................12
CC
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V ; SRAM
IL
Byte Mode, CIOs = V ..................................................................13
SS
Requirements for Reading Array Data ...................................14
Page Mode Read ....................................................................14
Writing Commands/Command Sequences ............................14
Write Buffer ............................................................................. 14
Accelerated Program Operation .............................................14
Autoselect Functions .............................................................. 14
Automatic Sleep Mode ...........................................................15
RESET#: Hardware Reset Pin ...............................................15
Output Disable Mode .............................................................. 15
................................................................................................ 16
Sector Group Protection and Unprotection ............................. 18
Table 6. Am29LV320MT Top Boot Sector Protection .....................18
................................................................................................ 18
Table 7. Am29LV320MB Bottom Boot Sector Protection ................18
Write Protect (WP#) ................................................................18
Temporary Sector Group Unprotect ....................................... 19
Figure 1. Temporary Sector Group Unprotect Operation................ 19
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 20
SecSi (Secured Silicon) Sector Flash Memory Region .......... 21
Table 8. SecSi Sector Contents ......................................................21
Figure 3. SecSi Sector Protect Verify.............................................. 22
Hardware Data Protection ......................................................22
Low VCC Write Inhibit ............................................................ 22
Write Pulse “Glitch” Protection ...............................................22
Logical Inhibit .......................................................................... 22
Power-Up Write Inhibit ............................................................ 22
Common Flash Memory Interface (CFI). . . . . . . 22
Command Definitions . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ................................................................25
Reset Command .....................................................................26
Autoselect Command Sequence ............................................26
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..26
Word Program Command Sequence .....................................26
Unlock Bypass Command Sequence .....................................27
Write Buffer Programming ......................................................27
Accelerated Program .............................................................. 28
Figure 4. Write Buffer Programming Operation............................... 29
Figure 5. Program Operation .......................................................... 30
Program Suspend/Program Resume Command Sequence ... 30
Figure 6. Program Suspend/Program Resume............................... 31
Chip Erase Command Sequence ........................................... 31
Sector Erase Command Sequence ........................................31
Figure 7. Erase Operation............................................................... 32
Erase Suspend/Erase Resume Commands ........................... 32
Write Operation Status . . . . . . . . . . . . . . . . . . . . 35
8 x 10 mm Package ................................................................ 64
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 65
June 10, 2003
Am41LV3204M
3
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Am41LV3204M
Family Part Number
Flash Memory
SRAM
Standard Voltage
Speed Option
10
10
Range: VCC = 2.7–3.3 V
Max Access Time (ns)
Max. CE# Access (ns)
100
100
30
70
70
Max. Page Access Time (tPACC
OE# Access (ns)
)
N/A
35
30
Note: See “AC Characteristics” for full specifications.
MCP BLOCK DIAGRAM
VCC
f
VSS
A20 to A0
RY/BY#
A20 to A0
A–1
WP#/ACC
RESET#
CE#f
32 M Bit
Flash Memory
DQ15/A-1 to DQ0
CIOf
DQ15/A-1 to DQ0
VCCs/VCCQ VSS/VSSQ
A17 to A0
SA
4 M Bit
Static RAM
LB#s
UB#s
WE#
DQ15/A-1 to DQ0
OE#
CE1#s
CE2s
CIOs
4
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
FLASH MEMORY BLOCK DIAGRAM
DQ15–DQ0
VCC
VSS
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
RESET#f
WE#
State
Control
WP#/ACC
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#f
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A20–A0
June 10, 2003
Am41LV3204M
5
P R E L I M I N A R Y
CONNECTION DIAGRAMS
69-ball Fine-pitch BGA
Top View, Balls Facing Down
Flash only
SRAM only
A1
A5
NC
B5
A6
A10
NC
NC
NC
B1
B3
B4
B6
B7
B8
NC
A7
LB# WP#/ACC WE#
A8
A11
Shared
C2
A3
C3
A6
C4
C5
C6
C7
A19
D7
A9
C8
A12
D8
A13
E8
A14
F8
C9
A15
D9
NC
UB# RESET# CE2s
D5
D2
A2
D3
A5
D4
D6
A18 RY/BY# A20
E1
NC
F1
NC
E2
A1
E3
A4
E4
A17
F4
E7
A10
F7
E9
NC
E10
NC
F2
A0
F3
F9
A16
G9
F10
NC
V
SS
DQ1
DQ6
G7
SA#
G8
G2
CE#f
H2
G3
OE#
H3
G4
DQ9
H4
G5
DQ3
H5
G6
DQ4
H6
DQ13 DQ15/A-1 CIOf
H7
DQ12
J7
H8
DQ7
J8
H9
V
CC
f
V s
CC
CE1#s DQ0
DQ10
J4
V
SS
J3
J5
J6
DQ8
DQ2
DQ11 CIOs
DQ5
DQ14
K1
K5
K6
K10
NC
NC
NC
NC
integrity may be compromised if the package body is
exposed to temperatures about 150°C for prolonged
periods of time.
SPECIAL PACKAGE HANDLING
INSTRUCTIONS FOR FBGA PACKAGES
Special handling is required for Flash Memory products
in molded packages (BGA). The package and/or data
6
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
PIN DESCRIPTION
A20–A0
= 21 Address inputs
LOGIC SYMBOL
DQ14–DQ0 = 15 Data inputs/outputs
21
DQ15/A-1
= DQ15 (Data input/output, word mode),
A20–A0
CE1#s
16 or 8
A-1 (25B Address input, byte mode)
DQ15–DQ0
(A-1)
CE#f
= Chip Enable input (Flash)
CE2s
OE#
CE1#s, CE2s= Chip Enable (SRAM)
OE#
WE#
= Output Enable input (Flash)
= Write Enable input (Flash)
WE#
WP#/ACC
WP#/ACC = Hardware Write Protect input/Pro-
gramming Acceleration input (Flash)
RESET#f
UB#s
RESET#f
= Hardware Reset Pin input (Flash)
VCC
f
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage
LB#s
CIOs
RY/BY#
supply tolerances)
SA#
CIOf
VCC
VSS
NC
s
= SRAM Power Supply
= Device Ground
= Pin Not Connected Internally
= Upper Byte Control (SRAM)
= Lower Byte Control (SRAM)
= I/O Configuration (SRAM)
CIOs = VIH = Word Mode (x16)
CIOs = VIL = Byte Mode (X8)
= Highest Order Address Pin (SRAM)
Byte Mode
UB#s
LB#s
CIOs
SA
CIOf
= I/O Configuration (Flash)
CIOf = VIH = Word Mode (x16)
CIOf = VIL = Byte Mode (X8)
June 10, 2003
Am41LV3204M
7
P R E L I M I N A R Y
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am41LV32x 10
4
M
T
I
T
TAPE AND REEL
T
S
=
=
7 inches
13 inches
TEMPERATURE RANGE
Industrial (–40°C to +85°C)
I
=
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
B
=
=
Top sector
Bottom sector
PROCESS TECHNOLOGY
0.23 µm MirrorBit
M
=
SRAM DEVICE DENSITY
4 Mbits
4
=
AMD DEVICE NUMBER/DESCRIPTION
Am41LV3204M
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29LV320M 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) Flash Memory and
4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations
Order Number
Am41LV3204MT10I
Am41LV3204MB10I
Package Marking
M410000095
T
M410000096
8
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
June 10, 2003
Am41LV3204M
9
P R E L I M I N A R Y
Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH, SRAM Word Mode, CIOs = VIH
Operation
(Notes 1, 2)
WP#/ACC DQ7– DQ15–
CE#f CE1#s CE2s OE# WE# SA
Addr. LB#s UB#s RESET#
(Note 4)
DQ0
DQ8
H
X
H
X
H
X
X
L
X
L
X
L
Read from Flash
L
L
H
X
H
L
X
X
X
AIN
AIN
X
X
X
X
X
X
X
H
L/H
DOUT
DOUT
Write to Flash
Standby
L
H
(Note 4)
H
DIN
DIN
VCC
0.3 V
±
VCC ±
0.3 V
X
High-Z High-Z
High-Z High-Z
High-Z High-Z
H
H
H
H
X
X
X
X
L
X
L
Output Disable
L
L
H
H
L/H
X
H
X
H
X
L
Flash Hardware
Reset
X
L
X
X
X
X
X
X
X
L
L/H
X
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Protect
(Note 5)
H
L
X
X
VID
L/H
DIN
X
X
X
H
X
L
X
L
SADD,
A6 = H,
A1 = H,
A0 = L
Sector Unprotect
(Note 5)
L
X
H
H
X
L
L
X
H
X
X
X
X
X
X
X
VID
VID
H
(Note 6)
(Note 6)
X
DIN
H
X
X
L
Temporary Sector
Unprotect
X
DIN
High-Z
DOUT
L
H
L
L
L
DOUT
Read from SRAM
Write to SRAM
L
L
H
H
AIN
High-Z DOUT
DOUT High-Z
H
L
L
DIN
High-Z
DIN
DIN
DIN
H
X
L
X
AIN
H
L
L
H
X
H
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “”. If WP#/ACC = VHH, all sectors will
be unprotected.
10
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
Table 2. Device Bus Operations—Flash Word Mode, CIOf = VIH, SRAM Word Mode, CIOs = VIL
Operation
(Notes 1, 2)
LB#s
(Note 3) (Note 3)
UB#s
WP#/ACC DQ7– DQ15–
CE#f CE1#s CE2s OE# WE# SA Addr.
RESET#
(Note 4)
DQ0
DQ8
H
X
H
X
H
X
L
X
L
Read from Flash
Write to Flash
L
L
H
L
X
X
AIN
AIN
X
X
X
X
H
L/H
DOUT
DOUT
X
L
L
H
H
(Note 3)
DIN
DIN
X
L
VCC
0.3 V
±
VCC ±
0.3 V
Standby
X
H
X
X
H
X
X
SA
X
X
X
X
X
DNU
X
X
DNU
X
H
High-Z High-Z
High-Z High-Z
High-Z High-Z
Output Disable
L
H
X
L
H
L/H
L/H
H
X
H
Flash Hardware
Reset
X
L
L
X
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Protect
(Note 5)
H
L
X
X
X
VID
L/H
DIN
X
X
H
X
L
X
L
SADD,
A6 = H,
A1 = H,
A0 = L
Sector Unprotect
(Note 5)
L
H
X
L
X
X
X
X
X
X
VID
(Note 6)
(Note 6)
DIN
X
H
X
L
X
L
Temporary Sector
Unprotect
X
X
AIN
VID
DIN
High-Z
Read from SRAM
Write to SRAM
H
H
H
H
L
H
L
SA
SA
AIN
AIN
X
X
X
X
H
H
X
X
DOUT High-Z
DIN High-Z
L
X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out, DNU = Do Not Use
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “”. If WP#/ACC = VHH, all sectors will
be unprotected.
June 10, 2003
Am41LV3204M
11
P R E L I M I N A R Y
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = VIL; SRAM Word Mode, CIOs = VCC
Operation
(Notes 1, 2)
LB#s
(Note 3) (Note 3)
UB#s
WP#/ACC DQ7– DQ15–
CE#f CE1#s CE2s OE# WE# SA
Addr.
RESET#
(Note 4)
DQ0
DQ8
H
X
H
X
H
X
X
L
X
L
X
L
Read from Flash
Write to Flash
Standby
L
L
H
X
H
X
H
L
X
X
X
X
X
AIN
X
X
X
X
X
X
H
L/H
DOUT
High-Z
L
AIN
X
H
(Note 3)
H
DIN
High-Z
VCC
0.3 V
±
VCC ±
0.3 V
X
H
X
High-Z High-Z
High-Z High-Z
High-Z High-Z
L
X
L
Output Disable
L
L
H
X
H
L/H
X
H
X
H
X
L
Flash Hardware
Reset
X
L
X
X
X
X
L
L/H
X
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Protect
(Note 5)
H
L
X
X
VID
L/H
DIN
X
X
H
X
L
X
L
SADD,
A6 = L,
A1 = H,
A0 = L
Sector
Unprotect
(Note 5)
L
X
H
H
X
L
L
X
H
X
X
X
X
X
X
X
VID
VID
H
(Note 6)
(Note 6)
X
DIN
X
Temporary
Sector
Unprotect
H
X
x
AIN
DIN
High-Z
L
L
H
L
L
L
DOUT
High-Z
DOUT
DIN
DOUT
DOUT
High-Z
DIN
Read from
SRAM
L
L
H
H
AIN
H
L
L
Write to SRAM
H
X
L
X
AIN
H
L
L
H
X
High-Z
DIN
DIN
H
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In, DOUT
Data Out
=
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “”. If WP#/ACC = VHH, all sectors will
be unprotected.
12
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = VIL; SRAM Byte Mode, CIOs = VSS
Operation
(Notes 1, 2)
LB#s
(Note 3) (Note 3)
UB#s
WP#/ACC DQ7– DQ15–
CE#f CE1#s CE2s OE# WE# SA
Addr.
RESET#
(Note 4)
DQ0
DQ8
H
X
H
X
H
X
L
X
L
Read from Flash
Write to Flash
L
L
H
L
X
X
AIN
X
X
X
X
H
L/H
DOUT
High-Z
X
L
L
H
AIN
H
(Note 3)
DIN
High-Z
X
L
VCC
0.3 V
±
VCC ±
0.3 V
Standby
X
H
X
X
H
X
X
SA
X
X
X
X
X
DNU
X
X
DNU
X
H
High-Z High-Z
High-Z High-Z
High-Z High-Z
Output Disable
H
H
X
L
H
L/H
L/H
H
X
H
Flash Hardware
Reset
X
L
L
X
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Protect
(Note 5)
H
L
X
X
X
VID
L/H
DIN
X
X
H
X
L
X
L
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Unprotect
(Note 5)
L
H
X
L
X
X
X
X
X
X
VID
(Note 6)
(Note 6)
DIN
DIN
X
H
X
L
X
L
Temporary
Sector Unprotect
X
X
AIN
VID
High-Z
Read from SRAM
Write to SRAM
H
H
H
H
L
H
L
SA
SA
AIN
AIN
X
X
X
X
H
H
X
X
DOUT
DIN
High-Z
High-Z
L
X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In, DOUT
Data Out, DNU = Do Not Use
=
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “”.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “”. If WP#/ACC = VHH, all sectors will
be unprotected.
June 10, 2003
Am41LV3204M
13
P R E L I M I N A R Y
tails on programming data to the device using both
standard and Unlock Bypass command sequences.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. The CIOf pin determines
whether the device outputs array data in words or
bytes.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 3 and 2 indicates the
address space that each sector occupies.
Refer to the DC Characteristics table for the active
current specification for the write mode. The AC Char-
acteristics section contains timing specification tables
and timing diagrams for write operations.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
Write Buffer
Write Buffer Programming allows the system to write a
maximum of 16 words/32-bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms. See
“Write Buffer” for more information.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
See “Reading Array Data” for more information. Refer
to the AC Flash Read-Only Operations table for timing
specifications and to Figure 14 for the timing diagram.
Refer to the DC Characteristics table for the active
current specification on reading array data.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the WP#/ACC pin returns the device to nor-
mal operation. Note that the WP#/ACC pin must not
be at VHH for operations other than accelerated pro-
gramming, or device damage may result. In addition,
no external pullup is necessary since the WP#/ACC
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 4 words/8-bytes. The appropriate page is
selected by the higher address bits A(max)–A2. Ad-
dress bits A1–A0 determine the specific word within a
page. This is an asynchronous operation; the micro-
processor supplies the specific word location.
The random or initial page access is equal to tACC or
tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE#f is
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Fast page mode ac-
cesses are obtained by keeping the “read-page ad-
dresses” constant and changing the “intra-read page”
addresses.
pin has internal pullup to VCC
.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word Program Command Sequence” section has de-
The device enters the CMOS standby mode when the
CE#f and RESET# pins are both held at VCC ± 0.3 V.
14
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
(Note that this is a more restricted voltage range than
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
VIH.) If CE#f and RESET# are held at VIH, but not
within VCC ± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The de-
vice requires standard access time (tCE) for read ac-
cess when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
Refer to the DC Characteristics table for the standby
current specification.
Automatic Sleep Mode
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for tACC
+
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the DC Characteristics table for the automatic
sleep mode current specification.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 16 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
June 10, 2003
Am41LV3204M
15
P R E L I M I N A R Y
Table 5. Am29LV320M Top Boot Sector Architecture
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
Address Range
SA0
SA1
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001101xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011000xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
101011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
110011xxx
100100xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
16
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
Table 5. Am29LV320M Top Boot Sector Architecture
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
Address Range
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3F1FFFh
3F2000h–3F3FFFh
3F4000h–3F5FFFh
3F6000h–3F7FFFh
3F8000h–3F9FFFh
3FA000h–3FBFFFh
3FC000h–3FDFFFh
3FE000h–3FFFFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1F8FFFh
1F9000h–1F9FFFh
1FA000h–1FAFFFh
1FB000h–1FBFFFh
1FC000h–1FCFFFh
1FD000h–1FDFFFh
1FE000h–1FEFFFh
1FF000h–1FFFFFh
8/4
8/4
8/4
8/4
8/4
8/4
8/4
June 10, 2003
Am41LV3204M
17
P R E L I M I N A R Y
Sector Group Protection and
Unprotection
Sector/
Sector Block Size
Sector
A20–A12
111111011h
111111100h
111111101h
111111110h
111111111h
SA66
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
The hardware sector group protection feature disables
both program and erase operations in any sector
group. In this device, a sector group consists of four
adjacent sectors that are protected or unprotected at
the same time (see Tables 4 and 6). The hardware
sector group unprotection feature re-enables both pro-
gram and erase operations in previously protected
sector groups. Sector group protection/unprotection
can be implemented via two methods.
SA67
SA68
SA69
SA70
Table 7. Am29LV320MB Bottom Boot
Sector Protection
Sector protection/unprotection requires VID on the RE-
SET# pin only, and can be implemented either in-sys-
tem or via programming equipment. Figure 2 shows
the algorithms and Figure 24 shows the timing dia-
gram. This method uses standard microprocessor bus
cycle timing. For sector group unprotect, all unpro-
tected sector groups must first be protected prior to
the first sector group unprotect write cycle.
Sector/
Sector Block Size
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A20–A12
000000000h
000000001h
000000010h
000000011h
000000100h
000000101h
000000110h
000000111h
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
The device is shipped with all sector groups unpro-
tected. AMD offers the option of programming and
protecting sector groups at its factory prior to shipping
the device through AMD’s ExpressFlash™ Service.
Contact an AMD representative for details.
8 Kbytes
8 Kbytes
000001XXXh,
000010XXXh,
000011XXXh,
SA8–SA10
192 (3x64) Kbytes
It is possible to determine whether a sector group is
protected or unprotected. See the Autoselect Mode
section for details.
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
0001XXXXXh
0010XXXXXh
0011XXXXXh
0100XXXXXh
0101XXXXXh
0110XXXXXh
0111XXXXXh
1000XXXXXh
1001XXXXXh
1010XXXXXh
1011XXXXXh
1100XXXXXh
1101XXXXXh
1110XXXXXh
1111XXXXXh
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
Table 6. Am29LV320MT Top Boot
Sector Protection
Sector/
Sector
A20–A12
Sector Block Size
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
SA0-SA3
0000XXXXXh
0001XXXXXh
0010XXXXXh
0011XXXXXh
0100XXXXXh
0101XXXXXh
0110XXXXXh
0111XXXXXh
1000XXXXXh,
1001XXXXXh
1010XXXXXh
1011XXXXXh
1100XXXXXh
1101XXXXXh
1110XXXXXh
SA4-SA7
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52-SA55
SA56-SA59
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting the top two or bottom two sectors
without using VID. WP# is one of two functions pro-
vided by the WP#/ACC input.
If the system asserts VIL on the WP#/ACC pin, the de-
vice disables program and erase functions in the first
or last sector independently of whether those sectors
were protected or unprotected using the method de-
scribed in “Sector Group Protection and Unprotection”.
Note that if WP#/ACC is at VIL when the device is in
111100XXXh
111101XXXh
111110XXXh
SA60-SA62
192 (3x64) Kbytes
SA63
SA64
SA65
111111000h
111111001h
111111010h
8 Kbytes
8 Kbytes
8 Kbytes
18
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
the standby mode, the maximum input load current is
increased. See the table in “DC Characteristics”.
START
If the system asserts VIH on the WP#/ACC pin, the de-
vice reverts to whether the top or bottom two sectors
were previously set to be protected or unprotected
using the method described in “Sector Group Protec-
tion and Unprotection”. Note: No external pullup is
necessary since the WP#/ACC pin has internal pullup
to VCC
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
Temporary Sector Group Unprotect
(Note: In this device, a sector group consists of four adjacent
sectors that are protected or unprotected at the same time
(see Table 6).
RESET# = VIH
This feature allows temporary unprotection of previ-
ously protected sector groups to change data in-sys-
tem. The Sector Group Unprotect mode is activated by
setting the RESET# pin to VID. During this mode, for-
merly protected sector groups can be programmed or
erased by selecting the sector group addresses. Once
VID is removed from the RESET# pin, all the previ-
ously protected sector groups are protected again.
Figure 1 shows the algorithm, and Figure 23 shows
the timing diagrams, for this feature.
Temporary Sector
Group Unprotect
Completed (Note 2)
Notes:
1. All protected sector groups unprotected (If WP# = VIL,
the first or last sector will remain protected).
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group
Unprotect Operation
June 10, 2003
Am41LV3204M
19
P R E L I M I N A R Y
START
START
PLSCNT = 1
PLSCNT = 1
RESET# = VID
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
Wait 1 µs
Wait 1 µs
Temporary Sector
Group Unprotect
Mode
Temporary Sector
Group Unprotect
Mode
No
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Yes
Yes
Set up sector
group address
All sector
groups
No
protected?
Yes
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up first sector
group address
Sector Group
Unprotect:
Wait 150 µs
Write 60h to sector
group address with
A6–A0 = 1xx0010
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
Read from
sector group address
with A6–A0
= 0xx0010
Increment
PLSCNT
A6–A0 = 1xx0010
No
No
PLSCNT
= 25?
Read from
sector group
address with
Data = 01h?
Yes
A6–A0 = 1xx0010
No
Yes
Set up
next sector group
address
Protect
another
sector group?
Yes
No
PLSCNT
= 1000?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
Last sector
group
verified?
No
Device failed
Write reset
command
Yes
Remove VID
from RESET#
Sector Group
Unprotect
Sector Group
Protect
Sector Group
Protect complete
Write reset
command
Algorithm
Algorithm
Sector Group
Unprotect complete
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
Am41LV3204M
20
June 10, 2003
P R E L I M I N A R Y
Factory Locked: SecSi Sector Programmed and
SecSi (Secured Silicon) Sector Flash
Memory Region
Protected At the Factory
In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. See Table 5 for
SecSi Sector addressing.
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 128 words in length, and
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the secu-
rity of the ESN once the product is shipped to the field.
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. The de-
vices are then shipped from AMD’s factory with the
SecSi Sector permanently locked. Contact an AMD
representative for details on using AMD’s Express-
Flash service.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unprotected, allowing customers to program the
sector after receiving the device. The customer-lock-
able version also has the SecSi Sector Indicator Bit
permanently set to a “0.” Thus, the SecSi Sector Indi-
cator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
As an alternative to the factory-locked version, the de-
vice may be ordered such that the customer may pro-
gram and protect the 128-word/256-bytes SecSi
sector.
The system may program the SecSi Sector using the
write-buffer, accelerated and/or unlock bypass meth-
ods, in addition to the standard programming com-
mand sequence. See Command Definitions.
Programming and protecting the SecSi Sector must be
used with caution since, once protected, there is no
procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory
space can be modified in any way.
The SecSi sector address space in this device is allo-
cated as follows:
Table 8. SecSi Sector Contents
SecSi Sector
Address
Range
Standard
Factory
Locked
The SecSi Sector area can be protected using one of
the following procedures:
ExpressFlash
Factory Locked
Customer
Lockable
x16
000000h–
000007h
ESN or determined
by customer
ESN
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RESET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
Determined by
customer
000008h–
00007Fh
Determined
by customer
Unavailable
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresses normally occupied by the first sector (SA0).
This mode of operation continues until the system is-
sues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to sector SA0.
■ To verify the protect/unprotect status of the SecSi
Sector, follow the algorithm shown in Figure 3.
Once the SecSi Sector is programmed, locked and
verified, the system must write the Exit SecSi Sector
Region command sequence to return to reading and
writing within the remainder of the array.
June 10, 2003
Am41LV3204M
21
P R E L I M I N A R Y
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
START
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
RESET# =
VIH or VID
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is
Wait 1 µs
Write 60h to
any address
Remove VIH or VID
from RESET#
Write 40h to SecSi
Sector address
with A6 = 0,
Write reset
command
greater than VLKO
.
A1 = 1, A0 = 0
Write Pulse “Glitch” Protection
SecSi Sector
Protect Verify
complete
Read from SecSi
Sector address
with A6 = 0,
Noise pulses of less than 5 ns (typical) on OE#, CE#f
or WE# do not initiate a write cycle.
A1 = 1, A0 = 0
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Figure 3. SecSi Sector Protect Verify
Power-Up Write Inhibit
Hardware Data Protection
If WE# = CE#f = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Tables 10 and 13
for command definitions). In addition, the following
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
given in Tables 6–9. To terminate reading CFI data,
the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 6–9. The
system must write the reset command to return the de-
vice to reading array data.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/flash/cfi. Al-
ternatively, contact an AMD representative for copies
of these documents.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
22
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
Table 9. CFI Query Identification String
Addresses
(x16)
Addresses
(x8)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Table 10. System Interface String
Addresses
(x16)
Addresses
(x8)
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
1Ch
36h
38h
0027h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0007h
0007h
000Ah
0000h
0001h
0005h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
V
PP Max. voltage (00h = no VPP pin present)
Typical timeout per single word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
June 10, 2003
Am41LV3204M
23
P R E L I M I N A R Y
Table 11. Device Geometry Definition
Addresses Addresses
(x16)
(x8)
Data
Description
27h
4Eh
0016h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device (01h = uniform device, 02h = boot
device)
2Ch
58h
0002h
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
007Fh
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
003Eh
0000h
0000h
0001h
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
24
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
Table 12. Primary Vendor-Specific Extended Query
Addresses Addresses
(x16)
(x8)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
0008h
Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
8Ch
8Eh
90h
92h
94h
96h
98h
0002h
0001h
0001h
0004h
0000h
0000h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = 29LV800 mode
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
9Ah
9Ch
00B5h
00C5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top
Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top
WP# protect
4Fh
50h
9Eh
A0h
0003h
0001h
Program Suspend
00h = Not Supported, 01h = Supported
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Tables 10 and 13 define the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper se-
quence may place the device in an unknown state. A
reset command is then required to return the device to
reading array data.
pens first. Refer to the AC Characteristics section for
timing diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
All addresses are latched on the falling edge of WE#
or CE#f, whichever happens later. All data is latched
on the rising edge of WE# or CE#f, whichever hap-
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
June 10, 2003
Am41LV3204M
25
P R E L I M I N A R Y
which the system can read data from any
Autoselect Command Sequence
non-erase-suspended sector. After completing a pro-
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The autoselect command sequence allows the host
system to read several identifier codes at specific ad-
dresses:
A7:A0
(x16)
A6:A-1
(x8)
Identifier Code
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode
if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode.
See the next section, Reset Command, for more infor-
mation.
Manufacturer ID
Device ID, Cycle 1
00h
01h
00h
02h
Device ID, Cycle 2
0Eh
1Ch
Device ID, Cycle 3
0Fh
1Eh
SecSi Sector Factory Protect
Sector Protect Verify
03h
06h
(SA)02h
(SA)04h
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Flash Read-Only Operations table provides the
read parameters, and Figure 14 shows the timing dia-
gram.
Note: The device ID is read over three cycles. SA = Sector
Address.
Tables 10 and 13 show the address and data require-
ments. This method is an alternative to that shown in
Table 3, which is intended for PROM programmers
and requires VID on address pin A9. The autoselect
command sequence may be written to an address that
is either in the read or erase-suspend-read mode. The
autoselect command may not be written while the de-
vice is actively programming or erasing.
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autoselect command sequence.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing an 8-word/16-byte random Electronic Serial
Number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi
Sector command sequence. The device continues to
access the SecSi Sector region until the system is-
sues the four-cycle Exit SecSi Sector command se-
quence. The Exit SecSi Sector command sequence
returns the device to normal operation. Tables 10 and
13 show the address and data requirements for both
command sequences. See also “SecSi (Secured Sili-
con) Sector Flash Memory Region” for further informa-
tion. Note that the ACC function and unlock bypass
modes are not available when the SecSi Sector is en-
abled.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Pro-
gramming operation, the system must write the
Write-to-Buffer-Abort Reset command sequence to
reset the device for the next operation.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
26
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
next, which in turn initiate the Embedded Program al-
Write Buffer Programming
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Tables 10 and 13 show the
address and data requirements for the word program
command sequence.
Write Buffer Programming allows the system write to a
maximum of 16 words in one programming operation.
This results in faster effective programming time than
the standard programming algorithms. The Write
Buffer Programming command sequence is initiated
by first writing two unlock cycles. This is followed by a
third write cycle containing the Write Buffer Load com-
mand written at the Sector Address in which program-
ming will occur. The fourth cycle writes the sector
address and the number of word locations, minus one,
to be programmed. For example, if the system will pro-
gram 6 unique address locations, then 05h should be
written to the device. This tells the device how many
write buffer addresses will be loaded with data and
therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot
exceed the size of the write buffer or the operation will
abort.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7 or DQ6. Refer to the Write Operation Status sec-
tion for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity. Note that the SecSi
Sector, autoselect, and CFI functions are unavailable
when a program operation is in progress.
The fifth cycle writes the first address location and
data to be programmed. The write-buffer-page is se-
lected by address bits AMAX–A4. All subsequent ad-
dress/data pairs must fall within the
selected-write-buffer-page. The system then writes the
remaining address/data pairs into the write buffer.
Write buffer locations may be loaded in any order.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
The write-buffer-page address must be the same for
all address/data pairs loaded into the write buffer. This
means Write Buffer Programming cannot be per-
formed across multiple write-buffer pages. This also
means that Write Buffer Programming cannot be per-
formed across multiple sectors. If the system attempts
to load programming data outside of the selected
write-buffer page, the operation will abort.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram words to the device faster than using the stan-
dard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Tables 10 and 13 show the re-
quirements for the command sequence.
Note that if a Write Buffer address location is loaded
multiple times, the address/data pair counter will be
decremented for every data load operation. The host
system must therefore account for loading a
write-buffer location more than once. The counter
decrements for each data load operation, not for each
unique write-buffer-address location. Note also that if
an address location is loaded more than once into the
buffer, the final data loaded for that address will be
programmed.
Once the specified number of write buffer locations
have been loaded, the system must then write the Pro-
gram Buffer to Flash command at the sector address.
Any other address and data combination aborts the
Write Buffer Programming operation. The device then
begins programming. Data polling should be used
while monitoring the last address location loaded into
the write buffer. DQ7, DQ6, DQ5, and DQ1 should be
monitored to determine the device status during Write
Buffer Programming.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
June 10, 2003
Am41LV3204M
27
P R E L I M I N A R Y
The write-buffer programming operation can be sus-
command sequence must be written to reset the de-
vice for the next operation. Note that the full 3-cycle
Write-to-Buffer-Abort Reset command sequence is re-
quired when using Write-Buffer-Programming features
in Unlock Bypass mode.
pended using the standard program suspend/resume
commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to
execute the next command.
The Write Buffer Programming Sequence can be
aborted in the following ways:
Accelerated Program
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at VHH for operations
other than accelerated programming, or device dam-
age may result. In addition, no external pullup is nec-
essary since the WP#/ACC pin has internal pullup to
■ Load a value that is greater than the page buffer
size during the Number of Locations to Program
step.
■ Write to an address in a sector different than the
one specified during the Write-Buffer-Load com-
mand.
■ Write an Address/Data pair to
a
different
write-buffer-page than the one selected by the
Starting Address during the write buffer data load-
ing stage of the operation.
VCC
.
■ Write data other than the Confirm Command after
Figure 5 illustrates the algorithm for the program oper-
ation. Refer to the Flash Erase and Program Opera-
tions table in the AC Characteristics section for
parameters, and Figure 17 for timing diagrams.
the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 =
DATA# (for the last address location loaded), DQ6 =
toggle, and DQ5=0. A Write-to-Buffer-Abort Reset
28
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Yes
Buffer Operation?
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
(Note 1)
Write next address/data pair
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Notes:
1. When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.
Read DQ7 - DQ0 at
Last Loaded Address
2. DQ7 may change simultaneously with DQ5.
Therefore, DQ7 should be verified.
3. If this flowchart location was reached because
DQ5= “1”, then the device FAILED. If this
flowchart location was reached because DQ1=
“1”, then the Write to Buffer operation was
ABORTED. In either case, the proper reset
command must be written before the device can
begin another operation. If DQ1=1, write the
Write-Buffer-Programming-Abort-Reset
Yes
DQ7 = Data?
No
No
command. if DQ5=1, write the Reset command.
No
DQ1 = 1?
Yes
DQ5 = 1?
Yes
4. See Tables 10 and 13 for command sequences
required for write buffer programming.
Read DQ7 - DQ0 with
address = Last Loaded
Address
Yes
(Note 2)
DQ7 = Data?
No
(Note 3)
FAIL or ABORT
PASS
Figure 4. Write Buffer Programming Operation
Am41LV3204M
June 10, 2003
29
P R E L I M I N A R Y
Program Suspend/Program Resume
Command Sequence
The Program Suspend command allows the system to
interrupt a programming operation or a Write to Buffer
programming operation so that data can be read from
any non-suspended sector. When the Program Sus-
pend command is written during a programming pro-
cess, the device halts the program operation within 15
µs maximum (5 µs typical) and updates the status bits.
Addresses are not required when writing the Program
Suspend command.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
After the programming operation has been sus-
pended, the system can read array data from any
non-suspended sector. The Program Suspend com-
mand may also be issued during a programming oper-
ation while an erase is suspended. In this case, data
may be read from any addresses not in Erase Sus-
pend or Program Suspend. If a read is needed from
the SecSi Sector area (One-time Program area), then
user must use the proper command sequences to
enter and exit this region.
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autoselect
codes as required. When the device exits the autose-
lect mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See
Autoselect Command Sequence for more information.
Programming
Completed
Note: See Tables 10 and 13 for program command
sequence.
After the Program Resume command is written, the
device reverts to programming. The system can de-
termine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard pro-
gram operation. See Write Operation Status for more
information.
Figure 5. Program Operation
The system must write the Program Resume com-
mand (address bits are don’t care) to exit the Program
Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ig-
nored. Another Program Suspend command can be
written after the device has resume programming.
30
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Write address/data
XXXh/B0h
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Command is also valid for
Erase-suspended-program
operations
Wait 15 µs
Autoselect and SecSi Sector
Read data as
required
read operations are also allowed
Figure 7 illustrates the algorithm for the erase opera-
tion. Refer to the Flash Erase and Program Opera-
tions tables in the AC Characteristics section for
parameters, and Figure 19 section for timing dia-
grams.
Data cannot be read from erase- or
program-suspended sectors
Done
reading?
No
Sector Erase Command Sequence
Yes
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Tables 10 and 13 shows
the address and data requirements for the sector
erase command sequence. Note that the SecSi Sec-
tor, autoselect, and CFI functions are unavailable
when a program operation is in progress.
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Figure 6. Program Suspend/Program Resume
Chip Erase Command Sequence
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Tables 10 and
13 shows the address and data requirements for the
chip erase command sequence. Note that the SecSi
Sector, autoselect, and CFI functions are unavailable
when a program operation is in progress.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the
time-out period resets the device to the read
mode. The system must rewrite the command se-
quence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
June 10, 2003
Am41LV3204M
31
P R E L I M I N A R Y
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the
sector erase operation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase operation or Embedded Program
algorithm.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6, or
DQ2 in the erasing sector. Refer to the Write Opera-
tion Status section for information on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Erase Suspend command is written during
the sector erase operation, the device requires a typi-
cal of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend com-
mand is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation.
Figure 7 illustrates the algorithm for the erase opera-
tion. Refer to the Flash Erase and Program Opera-
tions tables in the AC Characteristics section for
parameters, and Figure 19 section for timing dia-
grams.
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for infor-
mation on these status bits.
START
Write Erase
Command Sequence
(Notes 1, 2)
After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard word program operation.
Refer to the Write Operation Status section for more
information.
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
No
Data = FFh?
Yes
To resume the sector erase operation, the system
must write the Erase Resume command. The address
of the erase-suspended sector is required when writ-
ing this command. Further writes of the Resume com-
mand are ignored. Another Erase Suspend command
can be written after the chip has resumed erasing.
Erasure Completed
Notes:
1. See Tables 10 and 13 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 7. Erase Operation
32
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
Command Definitions
Table 13. Command Definitions (Flash, x16 mode, CIOf = VIH)
Bus Cycles (Notes 1–4)
First
Second
Third
Fourth
Fifth
Sixth
Command Sequence
(Notes)
Addr Data
Addr Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
6
RA
XXX
555
555
RD
F0
AA
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
Device ID (Note 8)
X0E 221A X0F 2201
SecSi Sector Factory Protect
(Note 9)
4
4
555
555
AA
AA
2AA
2AA
55
55
555
555
90
90
X03
(Note 9)
00/01
Sector Group Protect Verify
(Note 10)
(SA)X02
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
6
1
3
3
2
2
6
6
1
1
1
555
555
555
555
SA
AA
AA
AA
AA
29
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
00
PD
WC
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 12)
Unlock Bypass
SA
PA
PD
WBL
PD
555
555
XXX
XXX
555
555
BA
AA
AA
A0
90
2AA
2AA
PA
55
55
PD
00
55
55
555
555
F0
20
Unlock Bypass Program (Note 13)
Unlock Bypass Reset (Note 14)
Chip Erase
XXX
2AA
2AA
AA
AA
B0
30
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend (Note 15)
Program/Erase Resume (Note 16)
CFI Query (Note 17)
BA
55
98
Legend:
X = Don’t care
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A20–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address . Addresses latch on the falling edge of the
WE# or CE# pulse, whichever happens later.
WC = Word Count. Number of write buffer locations to load minus 1.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
9. WP# protects the top two address sectors, the data is 98h for
factory locked and 18h for not factory locked.
2. All values are in hexadecimal.
10. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
11. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 21.
4. During unlock cycles, when lower address bits are 555 or 2AAh
as shown in table, address bits higher than A11 (except where
BA, PA, or SA is required) and data bits higher than DQ7 are
don’t cares.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
5. No unlock or command cycles required when device is in read
mode.
13. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
6. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
while the device is providing status information.
14. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
15. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
7. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care except for RD, PD,
and WC. See the Autoselect Command Sequence section for
more information.
16. The Erase Resume command is valid only during the Erase
Suspend mode.
8. The device ID must be read in three cycles. The data is 2201h for
top boot.
17. Command is valid when device is ready to read array data or when
device is in autoselect mode.
June 10, 2003
Am41LV3204M
33
P R E L I M I N A R Y
Table 14. Command Definitions (Flash x8 Mode, CIOf = VIL)
Bus Cycles (Notes 1–4)
First
Second
Third
Fourth
Fifth
Sixth
Command Sequence
(Notes)
Addr Data
Addr Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
6
RA
RD
F0
XXX
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
90
90
X00
X02
01
7E
Device ID (Note 8)
X1C
1A
X1E 00/01
SecSi Sector Factory Protect
(Note 9)
4
4
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
90
90
X06
(Note 9)
00/01
Sector Group Protect Verify
(Note 10)
(SA)X04
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
6
1
3
3
2
2
6
6
1
1
1
AAA
AAA
AAA
AAA
SA
AA
AA
AA
AA
29
555
555
555
555
55
55
55
55
AAA
AAA
AAA
SA
88
90
A0
25
XXX
PA
00
PD
BC
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 12)
Unlock Bypass
SA
PA
PD
WBL
PD
AAA
AAA
XXX
XXX
AAA
AAA
BA
AA
AA
A0
90
555
555
PA
55
55
PD
00
55
55
AAA
AAA
F0
20
Unlock Bypass Program (Note 13)
Unlock Bypass Reset (Note 14)
Chip Erase
XXX
555
555
AA
AA
B0
30
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Program/Erase Suspend (Note 15)
Program/Erase Resume (Note 16)
CFI Query (Note 17)
BA
AA
98
Legend:
X = Don’t care
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A20–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address . Addresses latch on the falling edge of the
WE# or CE# pulse, whichever happens later.
BC = Byte Count. Number of write buffer locations to load minus 1.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
bottom two address sectors, the data is 88h for factory locked and
08h for not factor locked.
2. All values are in hexadecimal.
10. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
11. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 37.
4. During unlock cycles, when lower address bits are 555 or AAAh
as shown in table, address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
5. No unlock or command cycles required when device is in read
mode.
13. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
6. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
while the device is providing status information.
14. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
7. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect
Command Sequence section for more information.
15. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
8. The device ID must be read in three cycles. The data is 01h for
top boot and 00h for bottom boot
16. The Erase Resume command is valid only during the Erase
Suspend mode.
9. If WP# protects the top two address sectors, the data is 98h for
factory locked and 18h for not factory locked. If WP# protects the
17. Command is valid when device is ready to read array data or when
device is in autoselect mode.
34
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the status of
a program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 11 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method
for determining whether a program or erase operation is
complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is
in progress or has been completed.
valid data, the data outputs on DQ0–DQ6 may be still
invalid. Valid data on DQ0–DQ7 will appear on suc-
cessive read cycles.
Table 11 shows the outputs for Data# Polling on DQ7.
Figure 8 shows the Data# Polling algorithm. Figure 20
in the AC Characteristics section shows the Data#
Polling timing diagram.
DQ7: Data# Polling
START
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 µs, then the device returns to the
read mode.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Yes
Read DQ7–DQ0
Addr = VA
Yes
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then
the device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 8. Data# Polling Algorithm
June 10, 2003
Am41LV3204M
35
P R E L I M I N A R Y
After an erase command sequence is written, if all sectors
RY/BY#: Ready/Busy#
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de-
vice enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alterna-
tively, the system can use DQ7 (see the subsection on
DQ7: Data# Polling).
pull-up resistor to VCC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or in the erase-suspend-read mode. Table 11
shows the outputs for RY/BY#.
DQ6: Toggle Bit I
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 11 shows the outputs for Toggle Bit I on DQ6.
Figure 9 shows the toggle bit algorithm. Figure 21 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 22 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
36
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
START
Read DQ7–DQ0
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 11 to compare out-
puts for DQ2 and DQ6.
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
Figure 9 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the RY/BY#: Ready/Busy# sub-
section. Figure 21 shows the toggle bit timing diagram.
Figure 22 shows the differences between DQ2 and
DQ6 in graphical form.
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Reading Toggle Bits DQ6/DQ2
Refer to Figure 9 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Figure 9. Toggle Bit Algorithm
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
June 10, 2003
Am41LV3204M
37
P R E L I M I N A R Y
other system tasks. In this case, the system must start
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 9).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or
write-to-buffer time has exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a
“1,” indicating that the program or erase cycle was not suc-
cessfully completed.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset
command to return the device to the reading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
Table 11 shows the status of DQ3 relative to the other
status bits.
DQ3: Sector Erase Timer
DQ1: Write-to-Buffer Abort
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
DQ1 indicates whether a Write-to-Buffer operation
was aborted. Under these conditions DQ1 produces a
“1”.
The
system
must
issue
the
Write-to-Buffer-Abort-Reset command sequence to re-
turn the device to reading array data. See Write Buffer
Table 15. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
DQ1 RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Program-Suspended
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
0
Standard
Mode
N/A
Invalid (not allowed)
Data
1
1
1
1
0
Program
Suspend
Mode
Program-
Sector
Suspend
Non-Program
Read
Suspended Sector
Erase-Suspended
1
No toggle
Toggle
0
N/A
Toggle
N/A
N/A
N/A
Erase-
Sector
Suspend
Erase
Suspend
Mode
Non-EraseSuspended
Read
Data
Sector
Erase-Suspend-Program
(Embedded Program)
DQ7#
0
N/A
Busy (Note 3)
Abort (Note 4)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Write-to-
Buffer
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when tthe device has aborted the write-to-buffer operation.
38
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
20 ns
+0.8 V
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –65°C to +125°C
–0.5 V
–2.0 V
Voltage with Respect to Ground
VCCf/VCCs (Note 1) . . . . . . . . . . . .–0.3 V to +4.0 V
RESET#f (Note 2). . . . . . . . . . . .–0.5 V to +12.5 V
WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
20 ns
Figure 10. Maximum Negative
Overshoot Waveform
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 10. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to 20
ns. See Figure 11.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2. Minimum DC input voltage on pins A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 10. Maximum DC
input voltage on pin A9, OE#, ACC, and RESET# is
+12.5 V which may overshoot to +14.0 V for periods up
to 20 ns.
2.0 V
20 ns
20 ns
Figure 11. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Supply Voltages
V
CCf/VCCs for full voltage range . . . . . . . . . . 2.7–3.3 V
Note: Operating ranges define those limits between which
the functionality of the device is guaranteed.
June 10, 2003
Am41LV3204M
39
P R E L I M I N A R Y
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
(Notes)
Test Conditions
Min
Typ
Max
Unit
VIN = VSS to VCC
VCC = VCC max
,
ILI
Input Load Current (1)
±1.0
µA
ILIT
ILR
A9, ACC Input Load Current
Reset Leakage Current
VCC = VCC max; A9 = 12.5 V
35
35
µA
µA
VCC = VCC max; RESET# = 12.5 V
VOUT = VSS to VCC
VCC = VCC max
,
ILO
Output Leakage Current
±1.0
µA
5 MHz
1 MHz
15
15
30
10
50
20
20
50
20
60
VCC Active Read Current
(2, 3)
ICC1
CE# = VIL, OE# = VIH,
mA
ICC2
ICC3
ICC4
VCC Initial Page Read Current (2, 3)
VCC Intra-Page Read Current (2, 3)
VCC Active Write Current (3, 4)
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
mA
mA
mA
CE#, RESET# = VCC ± 0.3 V,
WP# = VIH
ICC5
ICC6
ICC7
VCC Standby Current (3)
VCC Reset Current (3)
1
1
1
5
5
5
µA
µA
µA
RESET# = VSS ± 0.3 V, WP# = VIH
VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V, WP# = VIH
Automatic Sleep Mode (3, 5)
VIL
VIH
Input Low Voltage (6)
Input High Voltage (6)
–0.5
0.8
V
V
0.7 x VCC
VCC + 0.5
Voltage for Autoselect and Temporary
Sector Unprotect
VID
VCC = 2.7 –3.6 V
11.5
12.5
V
VOL
VOH1
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min = VIO
0.15 x VCC
V
V
V
V
IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VCC
IOH = –100 µA, VCC = VCC min = VIO VCC–0.4
2.3
Output High Voltage
VOH2
VLKO
Low VCC Lock-Out Voltage (7)
2.5
Notes:
1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
3. Maximum ICC specifications are tested with VCC = VCCmax.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
6. VCC voltage requirements.
7. Not 100% tested.
40
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
SRAM DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Parameter Description
Input Leakage Current
Test Conditions
VIN = VSS to VCC
Min
–1.0
–1.0
Typ
Max
1.0
Unit
µA
ILI
CE1#s = VIH, CE2s = VIL or OE# =
VIH or WE# = VIL, VIO= VSS to VCC
ILO
Output Leakage Current
1.0
µA
IIO = 0 mA, CE1#s = VIL, CE2s =
WE# = VIH, VIN = VIH or VIL
ICC
Operating Power Supply Current
3
3
mA
mA
Cycle time = 1 µs, 100% duty,
I
IO = 0 mA, CE1#s ≤ 0.2 V,
CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or
IN ≥ VCC – 0.2 V, CIOs = VSS or
I
CC1s
Average Operating Current
Average Operating Current
V
VCC
Cycle time = Min., IIO = 0 mA,
100% duty, CE1#s = VIL, CE2s =
VIH, VIN = VIL = or VIH, CIOs = VSS
or VCC
I
CC2s
30
mA
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
0.4
V
V
IOH = –1.0 mA
2.4
CE1#s = VIH, CE2 = VIL, Other
inputs = VIH or VIL
ISB
Standby Current (TTL)
0.3
10
mA
CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC
–
0.2 V (CE1#s controlled) or CE2 ≤
0.2 V (CE2s controlled) Other
input = 0 ~ VCC, CIOs = VSS or VCC
ISB1
Standby Current (CMOS)
µA
June 10, 2003
Am41LV3204M
41
P R E L I M I N A R Y
TEST CONDITIONS
Table 16. Test Specifications
Test Condition All Speeds
1 TTL gate
3.3 V
Unit
Output Load
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
0.0–3.0
Input timing measurement
reference levels
1.5
1.5
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 12. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 13. Input Waveforms and Measurement Levels
42
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
AC CHARACTERISTICS
Flash Read-Only Operations
Parameter
JEDEC
tAVAV
Std. Description
Test Setup
Speed
100
100
100
30
Unit
ns
tRC Read Cycle Time (Note 1)
tACC Address to Output Delay
tCE Chip Enable to Output Delay
tPACC Page Access Time
Min
Max
Max
Max
Max
Max
Max
tAVQV
CE#, OE# = VIL
OE# = VIL
ns
tELQV
ns
ns
tGLQV
tEHQZ
tGHQZ
tOE Output Enable to Output Delay
30
ns
tDF
tDF
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
ns
30
ns
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold
tOEH
Toggle and
Data# Polling
Time (Note 1)
10
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 12 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#f
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#f
Figure 14. Read Operation Timings
June 10, 2003
Am41LV3204M
43
P R E L I M I N A R Y
AC CHARACTERISTICS
Same Page
A20
-
-
A2
A0
A1
Ad
Aa
tACC
Ab
tPACC
Ac
tPACC
tPACC
Data Bus
Qa
Qb
Qc
Qd
CE#f
OE#
Figure 15. Page Read Timings
44
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
RESET# Pin Low (NOT During Embedded
Speed
Unit
tReady
Max
500
ns
Algorithms) to Read Mode (See Note)
tRP
tRH
RESET# Pulse Width
Min
Min
Min
500
50
ns
ns
µs
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
tRPD
20
Note: Not 100% tested.
CE#f, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
CE#f, OE#
RESET#
tRP
Figure 16. Reset Timings
June 10, 2003
Am41LV3204M
45
P R E L I M I N A R Y
AC CHARACTERISTICS
Flash Erase and Program Operations
Parameter
JEDEC
tAVAV
Std.
tWC
tAS
Description
Speed
100
0
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
Min
Min
tAVWL
ns
tASO
tAH
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
ns
tWLAX
45
ns
Address Hold Time From CE# or OE# high
during toggle bit polling
tAHT
Min
0
ns
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
45
0
ns
ns
ns
Data Hold Time
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
tWP
tWPH
CE# Setup Time
Min
Min
Min
Min
Typ
0
0
ns
ns
ns
ns
µs
CE# Hold Time
Write Pulse Width
35
30
240
Write Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Effective Write Buffer Program Operation
(Notes 2, 4)
Per Word
Typ
Typ
15
µs
µs
tWHWH1
tWHWH1
Accelerated Effective Write Buffer
Per Word
11.8
Program Operation (Notes 2, 4)
Single Word Program Operation (Note 2)
Single Word Accelerated Programming Operation (Note 2)
Sector Erase Operation (Note 2)
Typ
Typ
Typ
Min
Min
60
54
µs
µs
tWHWH2
tWHWH2
tVHH
0.5
250
50
sec
ns
VHH Rise and Fall Time (Note 1)
tVCS
VCC Setup Time (Note 1)
µs
Notes:
1. Not 100% tested.
2. See the “AC Characteristics” section for more information.
3. For 1–16 words programmed.
4. Effective write buffer specification is based upon a 16-word write buffer operation.
46
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#f
OE#
tCH
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 17. Program Operation Timings
VHH
VIL or VIH
VIL or VIH
ACC
tVHH
tVHH
Figure 18. Accelerated Program Timing Diagram
June 10, 2003
Am41LV3204M
47
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#f
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
VCC
Complete
55h
30h
Progress
10 for Chip Erase
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.
Figure 19. Chip/Sector Erase Operation Timings
48
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#f
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
Complement
High Z
High Z
DQ7
Valid Data
Complement
Status Data
True
DQ6–DQ0
Valid Data
Status Data
True
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 20. Data# Polling Timings (During Embedded Algorithms)
June 10, 2003
Am41LV3204M
49
P R E L I M I N A R Y
AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE#f
tOEH
WE#
tCEPH
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 21. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 22. DQ2 vs. DQ6
50
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Note: Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
Figure 23. Temporary Sector Group Unprotect Timing Diagram
June 10, 2003
Am41LV3204M
51
P R E L I M I N A R Y
AC CHARACTERISTICS
V
ID
IH
V
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Group Protect or Unprotect
60h 60h
Verify
40h
Data
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector group protect, A6–A0 = 0xx0010. For sector group unprotect, A6–A0 = 1xx0010.
Figure 24. Sector Group Protect and Unprotect Timing Diagram
52
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
JEDEC
tAVAV
Std.
tWC
tAS
Description
Speed
100
0
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
tAVWL
tELAX
tDVEH
tEHDX
ns
tAH
45
ns
tDS
45
ns
tDH
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
Min
Min
Min
Min
Typ
0
0
ns
ns
ns
ns
µs
WE# Hold Time
CE# Pulse Width
45
30
240
tCPH
CE# Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Effective Write Buffer Program
Per Word
Typ
15
µs
Operation (Notes 2, 4)
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
tWHWH1
tWHWH1
Per Word
Typ
Typ
Typ
11.8
60
µs
µs
µs
Single Word Program Operation (Note 2)
Single Word Accelerated Programming Operation (Note
2)
54
tWHWH2
tWHWH2
tRH
Sector Erase Operation (Note 2)
Typ
Min
0.5
50
sec
ns
RESET# High Time Before Write (Note 1)
Notes:
1. Not 100% tested.
2. See the “AC Characteristics” section for more information.
3. For 1–16 words programmed.
4. Effective write buffer specification is based upon a 16-word write buffer operation.
June 10, 2003
Am41LV3204M
53
P R E L I M I N A R Y
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#f
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings
54
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
AC CHARACTERISTICS
SRAM Read Cycle
Speed Option
Parameter
Symbol
Unit
Description
10
70
70
70
35
70
tRC
tAA
CO1, tCO2
tOE
Read Cycle Time
Min
ns
ns
ns
ns
ns
Address Access Time
Chip Enable to Output
Output Enable Access Time
LB#s, UB#s to Access Time
Max
Max
Max
Max
t
tBA
Chip Enable (CE1#s Low and CE2s High) to Low-Z
Output
tLZ1, tLZ2
Min
10
ns
tBLZ
tOLZ
HZ1, tHZ2
tBHZ
UB#, LB# Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Min
Min
Max
Max
Max
Min
10
5
ns
ns
ns
ns
ns
ns
t
25
25
25
10
UB#s, LB#s Disable to High-Z Output
Output Disable to High-Z Output
Output Data Hold from Address Change
tOHZ
tOH
tRC
Address
Data Out
tAA
tOH
Data Valid
Previous Data Valid
Figure 26. SRAM Read Cycle—Address Controlled
Note: CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL
June 10, 2003
Am41LV3204M
55
P R E L I M I N A R Y
AC CHARACTERISTICS
tRC
Address
tAA
tCO1
tOH
CE#1s
CE2s
tCO2
tBA
tHZ
UB#s, LB#s
tBHZ
tOE
OE#
tOLZ
tBLZ
tLZ
tOHZ
Data Out
High-Z
Data Valid
Figure 27. SRAM Read Cycle
Notes:
1. WE# = VIH, if CIOs is low.
2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to
device interconnection.
56
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
AC CHARACTERISTICS
SRAM Write Cycle
Speed Option
Parameter
Description
Symbol
Unit
10
70
60
0
tWC
tCw
tAS
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of Write
Address Setup Time
tAW
tBW
tWP
tWR
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
60
60
50
0
Write Recovery Time
0
tWHZ
Write to Output High-Z
ns
20
30
0
tDW
tDH
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
ns
ns
ns
tOW
5
tWC
Address
CE1#s
CE2s
tWR
tCW
(See Note 1)
tAW
tCW
(See Note 1)
tWP
(See Note 4)
WE#
tAS
(See Note 3)
tDH
tDW
Data In
Data Out
High-Z
Data Valid
High-Z
tWHZ
tOW
Data Undefined
Notes:
1. WE# controlled.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 28. SRAM Write Cycle—WE# Control
June 10, 2003
Am41LV3204M
57
P R E L I M I N A R Y
AC CHARACTERISTICS
tWC
Address
tAS (See Note 2 )
tCW
tWR (See Note 4)
(See Note 3)
CE1#s
tAW
CE2s
tBW
UB#s, LB#s
tWP
(See Note 5)
WE#
tDW
tDH
Data Valid
Data In
Data Out
High-Z
High-Z
Notes:
1. CE1#s controlled.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 29. SRAM Write Cycle—CE1#s Control
58
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
AC CHARACTERISTICS
tWC
Address
CE1#s
tCW
(See Note 2)
tWR (See Note 3)
tAW
tCW (See Note 2)
CE2s
tBW
UB#s, LB#s
tAS
tWP
(See Note 4)
(See Note 5)
WE#
tDW
tDH
Data In
Data Out
Data Valid
High-Z
High-Z
Notes:
1. UB#s and LB#s controlled.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 30. SRAM Write Cycle—UB#s and LB#s Control
June 10, 2003
Am41LV3204M
59
P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
sec
sec
µs
Comments
Sector Erase Time
Chip Erase Time
0.5
32
3.5
64
Excludes 00h programming
prior to erasure (Note 6)
Byte
Word
Byte
60
600
600
540
540
1200
38
Single Word/Byte Program Time (Note 3)
60
µs
54
µs
Accelerated Single Word/Byte Program Time
(Note 3)
Word
54
µs
Total Write Buffer Program Time (Note 4)
Effective Write Buffer Program Time (Note 5)
240
7.5
15
µs
Excludes system level
overhead (Note 7)
Per Byte
Per Word
µs
75
µs
Total Accelerated Write Buffer Program Time (Note 4)
200
6.25
12.5
31.5
1040
33
µs
Per Byte
Per Word
µs
Effective Accelerated Write Buffer Program Time
(Note 5)
65
µs
Chip Program Time
73
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, Programming specification assume that
all bits are programmed to 00h.
2. Maximum values are measured at VCC = 3.0, worst case temperature. Maximum values are valid up to and including 100,000
program/erase cycles.
3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer.
4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation.
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence (s) for the program command. See Table11 for
further information on command definitions.
8. The device has a minimum erase and program cycle endurance of 100,000 cycles.
FLASH LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including OE#, and RESET#f)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
+100 mA
V
CC Current
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
60
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
PACKAGE PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
Typ
4.2
5.4
3.9
Max
5.0
6.5
4.7
Unit
pF
CIN
COUT
CIN2
Input Capacitance
Output Capacitance
Control Pin Capacitance
VIN = 0
VOUT = 0
VIN = 0
Fine-Pitch BGA
Fine-Pitch BGA
Fine-Pitch BGA
pF
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Description
Test Conditions
150°C
Min
Unit
Years
Years
10
20
Minimum Pattern Data Retention Time
125°C
June 10, 2003
Am41LV3204M
61
P R E L I M I N A R Y
SRAM DATA RETENTION
Parameter
Symbol
Parameter Description
Min
Typ
Max
3.3
10
Unit
V
Test Setup
VDR
VCC for Data Retention
Data Retention Current
CE1#s ≥ VCC – 0.2 V (Note 1)
2.7
VCC = 3.0 V, CE1#s ≥ VCC – 0.2 V
(Note 1)
1.0
(Note 2)
IDR
µA
tSDR
tRDR
Data Retention Set-Up Time
Recovery Time
0
ns
ns
See data retention waveforms
tRC
Notes:
1. CE1#s ≥ VCC – 0.2 V, CE2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled).
2. Typical values are not 100% tested.
Data Retention Mode
tSDR
tRDR
VCC
2.7V
2.2V
VDR
CE1#s ≥ VCC
-0.2 V
CE1#s
GND
Figure 31. CE#1 Controlled Data Retention Mode
Data Retention Mode
VCC
2.7 V
CE2#s
tSDR
tRDR
VDR
<
CE2#s 0.2 V
0.4 V
GND
Figure 32. CE2s Controlled Data Retention Mode
62
Am41LV3204M
June 10, 2003
Representatives in U.S. and Canada
Sales Offices and Representatives
ARIZONA,
North America
Tempe - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(480)839-2320
CALIFORNIA,
ALABAMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(256)830-9192
ARIZONA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(602)242-4400
CALIFORNIA,
Calabasas - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(818)878-5800
Irvine - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (949)261-2123
San Diego - Centaur. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(858)278-4950
Santa Clara - Fourfront. . . . . . . . . . . . . . . . . . . . . . . . . . . .(408)350-4800
CANADA,
Burnaby, B.C. - Davetek Marketing. . . . . . . . . . . . . . . . . . . .(604)430-3680
Calgary,Alberta - Davetek Marketing. . . . . . . . . . . . . . . . .(403)283-3577
Kanata, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . . . .(613)592-9540
Mississauga, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . .(905)672-2030
St Laurent, Quebec - J-Squared Tech. . . . . . . . . . . . . . . . ( 5 1 4 ) 74 7 - 1 2 1 1
COLORADO,
Irvine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(949)450-7500
Sunnyvale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(408)732-2400
COLORADO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(303)741-2900
CONNECTICUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(203)264-7800
FLORIDA,
Clearwater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(727)793-0055
Miami (Lakes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 3 0 5 ) 8 2 0 - 1 1 1 3
GEORGIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(770)814-0224
ILLINOIS,
Chicago . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(630)773-4422
MASSACHUSETTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (781)213-6400
MICHIGAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(248)471-6294
MINNESOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(612)745-0005
NEW JERSEY,
Chatham . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 97 3 ) 7 0 1 - 1 7 7 7
NEWYORK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(716)425-8050
NORTH CAROLINA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(919)840-8080
OREGON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(503)245-0080
PENNSYLVANIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 1 5 ) 3 4 0 - 1 1 8 7
SOUTH DAKOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(605)692-5777
TEXAS,
Golden - Compass Marketing . . . . . . . . . . . . . . . . . . . . . .(303)277-0456
FLORIDA,
Melbourne - Marathon Technical Sales . . . . . . . . . . . . . . . .(321)728-7706
Ft. Lauderdale - Marathon Technical Sales . . . . . . . . . . . . . .(954)527-4949
Orlando - Marathon Technical Sales . . . . . . . . . . . . . . . . . .(407)872-5775
St. Petersburg - Marathon Technical Sales . . . . . . . . . . . . . .(727)894-3603
GEORGIA,
Duluth - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . (678)584-1128
ILLINOIS,
Skokie - Industrial Reps, Inc. . . . . . . . . . . . . . . . . . . . . . . . .(847)967-8430
INDIANA,
Kokomo - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (765)457-7241
IOWA,
Cedar Rapids - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . (319)294-1000
KANSAS,
Lenexa - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 1 3 ) 4 69 - 1 3 1 2
MASSACHUSETTS,
Austin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(512)346-7830
Dallas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(972)985-1344
Houston . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(281)376-8084
VIRGINIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(703)736-9568
Burlington - Synergy Associates . . . . . . . . . . . . . . . . . . . . .(781)238-0870
MICHIGAN,
Brighton - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(810)227-0007
MINNESOTA,
St. Paul - Cahill, Schmitz & Cahill, Inc. . . . . . . . . . . . . . . . . .(651)699-0200
MISSOURI,
St. Louis - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . .(314)997-4558
NEW JERSEY,
International
AUSTRALIA, North Ryde . . . . . . . . . . . . . . . . . . . . . . .TEL(61)2-88-777-222
BELGIUM,Antwerpen . . . . . . . . . . . . . . . . . . . . . . . .TEL(32)3-248-43-00
BRAZIL, San Paulo . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(55)11-5501-2105
CHINA,
Beijing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(86)10-6510-2188
Shanghai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(86)21-635-00838
Shenzhen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(86)755-246-1550
FINLAND, Helsinki . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 5 8 ) 8 8 1 - 3 1 1 7
FRANCE, Paris . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 3 ) - 1 - 4 975 1 0 1 0
GERMANY,
Bad Homburg . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(49)-6172-92670
Munich . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 4 9 ) - 8 9 - 4 5 0 5 3 0
HONG KONG, Causeway Bay . . . . . . . . . . . . . . . . . . .TEL(85)2-2956-0388
ITALY, Milan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 9 ) - 0 2 - 3 8 1 9 6 1
INDIA, New Delhi . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 9 1 ) 1 1 - 62 3 - 8 62 0
JAPAN,
es
Mt. Laurel - SJ Associates . . . . . . . . . . . . . . . . . . . . . . . . .(856)866-1234
NEWYORK,
Buffalo - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 1 6 ) 74 1 - 7 1 1 6
East Syracuse - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . (315) 437-8343
Pittsford - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . .(716)586-3660
Rockville Centre - SJ Associates . . . . . . . . . . . . . . . . . . . . (516)536-4242
NORTH CAROLINA,
Raleigh - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . .(919)846-5728
OHIO,
Middleburg Hts - Dolfuss Root & Co. . . . . . . . . . . . . . . . .(440)816-1660
Powell - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . . . (614)781-0725
Vandalia - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . .(937)898-9610
Westerville - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . (614)523-1990
OREGON,
Lake Oswego - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . .(503)670-0557
UTAH,
Murray - Front Range Marketing . . . . . . . . . . . . . . . . . . . .(801)288-2500
VIRGINIA,
Osaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(81)6-6243-3250
Tokyo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(81)3-3346-7600
KOREA, Seoul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(82)2-3468-2600
RUSSIA, Moscow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(7)-095-795-06-22
SWEDEN, Stockholm . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(46)8-562-540-00
TAIWAN,Taipei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(886)2-8773-1555
UNITED KINGDOM,
Frimley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(44)1276-803100
Haydock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(44)1942-272888
Glen Burnie - Coherent Solution, Inc. . . . . . . . . . . . . . . . . ( 4 1 0 ) 76 1 - 2 2 5 5
WASHINGTON,
Kirkland - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . .(425)822-9220
WISCONSIN,
Pewaukee - Industrial Representatives . . . . . . . . . . . . . . . .(262)574-9393
Advanced Micro Devices reserves the right to make changes in its product without notice
in order to improve design or performance characteristics.The performance
characteristics listed in this document are guaranteed by specific tests, guard banding,
design and other practices common to the industry. For specific testing details, contact
your local AMD sales representative.The company assumes no responsibility for the use of
any circuits described herein.
Representatives in Latin America
ARGENTINA,
Capital Federal Argentina/WW Rep. . . . . . . . . . . . . . . . . . . .54-11)4373-0655
CHILE,
Santiago - LatinRep/WWRep. . . . . . . . . . . . . . . . . . . . . . . . . .(+562)264-0993
COLUMBIA,
Bogota - Dimser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 5 7 1 ) 4 1 0 - 4 1 8 2
MEXICO,
Guadalajara - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . .(523)817-3900
Mexico City - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . .(525)752-2727
Monterrey - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . .(528)369-6828
PUERTO RICO,
© Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD Arrow logo and combination thereof, are trademarks of
Advanced Micro Devices, Inc. Other product names are for informational purposes only
and may be trademarks of their respective companies.
Boqueron - Infitronics. . . . . . . . . . . . . . . . . . . . . . . . . . . .(787)851-6000
One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 408-732-2400
TWX 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com
©2003 Advanced Micro Devices, Inc.
01/03
Printed in USA
PHYSICAL DIMENSIONS
P R E L I M I N A R Y
TLB069—69-Ball Fine-pitch Ball Grid Array (FBGA) 8 x 10 mm Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
7
6
5
4
3
2
1
SE
7
E
B
E1
eE
J
H
G
F
E
D
C
B
A
K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
C
C
A2
A
0.08
C
A1
SIDE VIEW
6
69X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
PACKAGE
JEDEC
TLB 069
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
10.00 mm X 8.00 mm PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX IN THE "E" DIRECTION.
SYMBOL
A
MIN.
---
NOM.
---
MAX.
1.20
---
PROFILE
BALL HEIGHT
A1
0.20
0.81
---
A2
---
0.97
BODY THICKNESS
BODY SIZE
n IS THE NUMBER OF POPULATED SOLDER BALL
POSITIONS FOR MATRIX SIZE MD X ME.
D
10.00 BSC
8.00 BSC
7.20 BSC
7.20 BSC
10
E
BODY SIZE
6. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
E1
7. SD AND SE ARE MEASURED WITH RESPECT TO
DATUMS A AND B AND DEFINE THE POSITION OF THE
CENTER SOLDER BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS
IN THE OUTER ROW SD OR SE = 0.000.
69
Ob
eE
0.33
---
0.43
BALL DIAMETER
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS
IN THE OUTER ROW, SD OR SE = E/2
0.80 BSC
0.80 BSC
0.40 BSC
eD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
SD/SE
SOLDER BALL PLACEMENT
9. NOT USED.
A2,A3,A4,A7,A8,A9,B2,B9,B10 DEPOPULATED SOLDER BALLS
C1,C10,D1,D10,E5,E6,F5,F6
G1,G10,H1,H10
J1,J2,J9,J10,K2,K3,K4,K7,K8,K9
10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER
OR INK MARK, METALLIZED MARK INDENTATION OR
OTHER MEANS.
w052903-163814C
64
Am41LV3204M
June 10, 2003
P R E L I M I N A R Y
REVISION SUMMARY
Connection Diagram
Revision A (March 21, 2003)
Corrected pinout numbering.
Initial release.
Pin Description
Revision A+1 (June 10, 2003)
Added CIOf and DQ15/A-1
Global
Changed datasheet name to Am41LV3204.
Trademarks
Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
June 10, 2003
Am41LV3204M
65
P R E L I M I N A R Y
66
Am41LV3204M
June 10, 2003
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