AM42BDS6408HE3IT_技术文档

ADVANCE INFORMATION

Am42BDS6408H

Am29BDS640H 64 Megabit (4 M x 16-Bit)

Stacked MultiChip Package (MCP) Flash Memory and SRAM

CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash

Memory, and 8 Mbit (512 K x 16-Bit) SRAM

FLASH DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

PERFORMANCE CHARCTERISTICS

■

Read access times at 66/54 MHz (C_L=30 pF)

— Burst access times of 11/13.5 ns at industrial

temperature range

■ Single 1.8 volt read, program and erase (1.65 to 1.95

volt)

■ Manufactured on 0.13 µm process technology

— Synchronous latency of 56/69 ns

■ VersatileIO™ (V ) Feature

IO

— Asynchronous random access times of 45/50/55 ns

— Device generates data output voltages and tolerates

data input voltages as determined by the voltage on

■ Power dissipation (typical values, C = 30 pF)

L

the V pin

IO

— Burst Mode Read: 10 mA

— Simultaneous Operation: 25 mA

— Program/Erase: 15 mA

— 1.8V compatible I/O signals

— Contact factory for availability of 1.5V compatible I/O

signals

— Standby mode: 0.2 µA

■

Simultaneous Read/Write operation

— Data can be continuously read from one bank while

executing erase/program functions in other bank

HARDWARE FEATURES

■ Handshaking feature

— Zero latency between read and write operations

— Four bank architecture: 8Mb/24Mb/24Mb/8Mb

— Provides host system with minimum possible latency

by monitoring RDY

Programable Burst Interface

— Reduced Wait-state handshaking option further

reduces initial access cycles required for burst

accesses beginning on even addresses

— 2 Modes of Burst Read Operation

— Linear Burst: 8, 16, and 32 words with

wrap-around

■ Hardware reset input (RESET#)

— Hardware method to reset the device for reading array

data

— Continuous Sequential Burst

■

SecSi^TM(Secured Silicon) Sector region

— Up to 128 words accessible through a command

sequence

■ WP# input

— Write protect (WP#) function allows protection of the

four highest and four lowest 4 kWord boot sectors,

regardless of sector protect status

— Up to 64 factory-locked words

— Up to 64 customer-lockable words

■ Persistent Sector Protection

Sector Architecture

— A command sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector

— Sixteen 4 Kword sectors and one hundred twenty-six

32 Kword sectors

— Banks A and D each contain eight 4 Kword sectors

and fifteen 32 Kword sectors; Banks B and C each

contain forty-eight 32 Kword sectors

— Sectors can be locked and unlocked in-system at V

CC

level

— Sixteen 4 Kword boot sectors: eight at the top of the

address range and eight at the bottom of the address

range

■ Password Sector Protection

— A sophisticated sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector using a user-defined 64-bit password

■ Minimum 1 million erase cycle guarantee per sector

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ 89-ball FBGA package

■ ACC input: Acceleration function reduces

programming time; all sectors locked when ACC =

V

IL

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. Do not design in this product without contacting the factory. AMD re-

serves the right to change or discontinue work on this proposed product without notice.

Publication# 30491

Issue Date: October 23, 2003

Rev: A Amendment:+3

Refer to AMD’s Website (www.amd.com) for the latest information.

A D V A N C E I N F O R M A T I O N

■ CMOS compatible inputs, CMOS compatible outputs

■ Unlock Bypass Program command

■ Low V write inhibit

— Reduces overall programming time when issuing

multiple program command sequences

CC

SOFTWARE FEATURES

■ Burst Suspend/Resume

■ Supports Common Flash Memory Interface (CFI)

— Suspends a burst operation to allow system use of the

address and data bus, than resumes the burst at the

previous state

■ Software command set compatible with JEDEC 42.4

standards

— Backwards compatible with Am29F and Am29LV

families

SRAM FEATURES

■ Power dissipation

— Operating: 10 mA typical

— Standby: 2 µA

■ Data# Polling and toggle bits

— Provides a software method of detecting program and

erase operation completion

■ Erase Suspend/Resume

■ CE1s# and CE2 Chip Select

— Suspends an erase operation to read data from, or

program data to, a sector that is not being erased,

then resumes the erase operation

■ Power down features using CE1s# and CE2s

■ Data retention supply voltage: 1.0 to 2.2 volt

■ Byte data control: LB# (DQ7-DQ0), UB#s (DQ15-DQ8)

2

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION

The Am29BDS640H is a 64 Mbit, 1.8 Volt-only, simultaneous

Read/Write, Burst Mode Flash memory device, organized as

4,194,304 words of 16 bits each. This device uses a single

dresses and data needed for the programming and erase

operations. Reading data out of the device is similar to read-

ing from other Flash or EPROM devices.

V

of 1.65 to 1.95 V to read, program, and erase the mem-

CC

The Erase Suspend/Erase Resume feature enables the

user to put erase on hold for any period of time to read data

from, or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved. If a

read is needed from the SecSi Sector area (One Time Pro-

gram area) after an erase suspend, then the user must use

the proper command sequence to enter and exit this region.

ory array. A 12.0-volt V

program performance if desired.

on ACC may be used for faster

HH

At 66 MHz, the device provides a burst access of 11 ns at 30

pF with a latency of 56 ns at 30 pF.At 54 MHz, the device

provides a burst access of 13.5 ns at 30 pF with a latency of

69ns at 30 pF. The device operates within the industrial tem-

perature range of -40°C to +85°C. The device is offered in

the 64-ball FBGA package.

The hardware RESET# pin terminates any operation in

progress and resets the internal state machine to reading

array data. The RESET# pin may be tied to the system reset

circuitry. A system reset would thus also reset the device,

enabling the system microprocessor to read boot-up firm-

ware from the Flash memory device.

The Simultaneous Read/Write architecture provides simul-

taneous operation by dividing the memory space into four

banks. The device can improve overall system performance

by allowing a host system to program or erase in one bank,

then immediately and simultaneously read from another

bank, with zero latency. This releases the system from wait-

ing for the completion of program or erase operations.

The host system can detect whether a program or erase op-

eration is complete by using the device status bit DQ7

(Data# Polling) and DQ6/DQ2 (toggle bits). After a program

or erase cycle has been completed, the device automatically

returns to reading array data.

The device is divided as shown in the following table:

Bank

Quantity

Size

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data con-

tents of other sectors. The device is fully erased when

shipped from the factory.

8

4 Kwords

32 Kwords

4 Kwords

A

15

48

15

8

B

C

Hardware data protection measures include a low V de-

CC

tector that automatically inhibits write operations during

power transitions. The device also offers two types of data

protection at the sector level. When at V , WP# locks the

IL

D

four highest and four lowest boot sectors.

The device offers two power-saving features. When ad-

dresses have been stable for a specified amount of time, the

device enters the automatic sleep mode. The system can

also place the device into the standby mode. Power con-

sumption is greatly reduced in both modes.

The VersatileIO™ (V ) control allows the host system to set

the voltage levels that the device generates at its data out-

puts and the voltages tolerated at its data inputs to the same

IO

voltage level that is asserted on the V pin.

IO

AMD’s Flash technology combines years of Flash memory

manufacturing experience to produce the highest levels of

quality, reliability and cost effectiveness. The device electri-

cally erases all bits within a sector simultaneously via

Fowler-Nordheim tunnelling. The data is programmed using

hot electron injection.

The device uses Chip Enable (CE#), Write Enable (WE#),

Address Valid (AVD#) and Output Enable (OE#) to control

asynchronous read and write operations. For burst opera-

tions, the device additionally requires Ready (RDY), and

Clock (CLK). This implementation allows easy interface with

minimal glue logic to a wide range of microprocessors/micro-

controllers for high performance read operations.

The burst read mode feature gives system designers flexibil-

ity in the interface to the device. The user can preset the

burst length and wrap through the same memory space, or

read the flash array in continuous mode.

The clock polarity feature provides system designers a

choice of active clock edges, either rising or falling. The ac-

tive clock edge initiates burst accesses and determines

when data will be output.

The device is entirely command set compatible with the

JEDEC 42.4 single-power-supply Flash standard. Com-

mands are written to the command register using standard

microprocessor write timing. Register contents serve as in-

puts to an internal state-machine that controls the erase and

programming circuitry. Write cycles also internally latch ad-

October 23, 2003

Am42BDS6408H

3

A D V A N C E I N F O R M A T I O N

TABLE OF CONTENTS

Table 10. Sector Address Table ........................................................... 26

Command Definitions . . . . . . . . . . . . . . . . . . . . . 30

Reading Array Data ......................................................................30

Set Configuration Register Command Sequence ........................30

Figure 3. Synchronous/Asynchronous State Diagram.......................... 30

Read Mode Setting ......................................................................30

Programmable Wait State Configuration ...................................... 30

Table 11. Programmable Wait State Settings ....................................... 31

Reduced Wait-state Handshaking Option .................................... 31

Table 12. Wait States for Reduced wait-state Handshaking ............... 32

Standard Handshaking Option .....................................................32

Table 13. Wait States for Standard Handshaking ................................. 32

Read Mode Configuration ............................................................ 32

Table 14. Read Mode Settings ............................................................. 33

Burst Active Clock Edge Configuration ........................................ 33

RDY Configuration ....................................................................... 33

Table 15. Configuration Register .......................................................... 33

Reset Command .......................................................................... 33

Autoselect Command Sequence .................................................. 34

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence ................................................................... 34

Program Command Sequence .....................................................34

Unlock Bypass Command Sequence ........................................... 35

Figure 4. Program Operation ................................................................ 35

Chip Erase Command Sequence ................................................. 35

Sector Erase Command Sequence ..............................................36

Erase Suspend/Erase Resume Commands ................................36

Figure 5. Erase Operation .................................................................... 37

Password Program Command .....................................................37

Password Verify Command .......................................................... 37

Password Protection Mode Locking Bit Program Command ....... 37

Persistent Sector Protection Mode Locking Bit Program Command

38

SecSi Sector Protection Bit Program Command .......................... 38

PPB Lock Bit Set Command ........................................................ 38

DYB Write Command ................................................................... 38

Password Unlock Command ........................................................ 38

PPB Program Command ..............................................................38

All PPB Erase Command .............................................................39

DYB Write Command ................................................................... 39

PPB Status Command ................................................................. 39

PPB Lock Bit Status Command ................................................... 39

DYB Status Command ................................................................. 39

Command Definitions ................................................................... 40

Table 16. Command Definitions .......................................................... 40

Write Operation Status . . . . . . . . . . . . . . . . . . . . 43

DQ7: Data# Polling ......................................................................43

Figure 6. Data# Polling Algorithm ......................................................... 43

DQ6: Toggle Bit I .......................................................................... 44

Figure 7. Toggle Bit Algorithm .............................................................. 45

..................................................................................................... 45

DQ2: Toggle Bit II ......................................................................... 45

Table 17. DQ6 and DQ2 Indications ..................................................... 46

Reading Toggle Bits DQ6/DQ2 .................................................... 46

DQ5: Exceeded Timing Limits ......................................................46

DQ3: Sector Erase Timer .............................................................46

Table 18. Write Operation Status .........................................................47

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 48

Figure 8. Maximum Negative Overshoot Waveform............................. 48

Figure 9. Maximum Positive Overshoot Waveform .............................. 48

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6

Flash Memory Block Diagram. . . . . . . . . . . . . . . . 7

Block Diagram of Simultaneous

Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 9

Special Handling Instructions for FBGA Package ..........................9

Ordering Information . . . . . . . . . . . . . . . . . . . . . . 11

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 12

Table 1. Device Bus Operations ..........................................................12

VersatileIO™ (V_IO) Control ..........................................................12

Requirements for Asynchronous Read

Operation (Non-Burst) ..................................................................12

Requirements for Synchronous (Burst) Read Operation .............12

8-, 16-, and 32-Word Linear Burst with Wrap Around ..................13

Table 2. Burst Address Groups .............................................................13

Burst Suspend/Resume ...............................................................13

Configuration Register .................................................................14

Reduced Wait-state Handshaking Option ....................................14

Simultaneous Read/Write Operations with Zero Latency ............14

Writing Commands/Command Sequences ..................................14

Accelerated Program Operation ...................................................15

Table 3. Am42BDS6408H Boot Sector/Sector Block Addresses for Protec-

tion/Unprotection ...................................................................................16

Sector/Sector Block Protection and Unprotection ........................16

Sector Protection ..........................................................................16

Selecting a Sector Protection Mode .............................................16

Persistent Sector Protection .........................................................17

Persistent Protection Bit (PPB) ....................................................17

Persistent Protection Bit Lock (PPB Lock) ...................................17

Dynamic Protection Bit (DYB) ......................................................17

Table 4. Sector Protection Schemes .....................................................18

Persistent Sector Protection Mode Locking Bit ............................18

Password Protection Mode ..........................................................18

Password and Password Mode Locking Bit .................................19

64-bit Password ...........................................................................19

Persistent Protection Bit Lock ......................................................19

High Voltage Sector Protection ....................................................19

Standby Mode ..............................................................................19

Automatic Sleep Mode .................................................................20

RESET#: Hardware Reset Input ..................................................20

Output Disable Mode ...................................................................20

Figure 1. Temporary Sector Unprotect Operation................................. 20

Figure 2. In-System Sector Protection/

Sector Unprotection Algorithms ............................................................ 21

SecSi™ (Secured Silicon) Sector

Flash Memory Region ..................................................................22

Factory-Locked Area (64 words) ..................................................22

Table 5. SecSi^TMSector Addresses .....................................................22

Customer-Lockable Area (64 words) ...........................................22

SecSi Sector Protection Bits ........................................................22

Hardware Data Protection ............................................................22

Write Protect (WP#) .....................................................................23

Low V_CCWrite Inhibit ...................................................................23

Write Pulse “Glitch” Protection .....................................................23

Logical Inhibit ...............................................................................23

Power-Up Write Inhibit .................................................................23

Table 6. CFI Query Identification String ................................................23

Table 7. System Interface String........................................................... 24

Table 8. Device Geometry Definition .................................................... 24

Table 9. Primary Vendor-Specific Extended Query ..............................25

4

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

Figure 30. Reset Timings...................................................................... 64

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 48

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 49

CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . 49

SRAM DC and Operating Characteristics . . . . . . 50

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 10. Test Setup............................................................................ 51

Table 19. Test Specifications ................................................................51

Key to Switching Waveforms . . . . . . . . . . . . . . . 51

Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 51

Figure 11. Input Waveforms and Measurement Levels ........................ 51

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 52

V_CCPower-up ..............................................................................52

Figure 12. V_CCPower-up Diagram ....................................................... 52

Synchronous/Burst Read (V_IO= 1.8 V) ........................................53

Figure 13. CLK Synchronous Burst Mode Read (rising active CLK)..... 54

Figure 14. CLK Synchronous Burst Mode Read (Falling Active Clock) 54

Figure 15. Synchronous Burst Mode Read........................................... 55

Figure 16. 8-word Linear Burst with Wrap Around................................ 55

Figure 17. Linear Burst with RDY Set One Cycle Before Data ............. 56

Figure 18. Reduced Wait-state Handshake Burst Suspend/Resume at an

even address......................................................................................... 57

Figure 19. Reduced Wait-state Handshake Burst Suspend/Resume at an

odd address .......................................................................................... 57

Figure 20. Reduced Wait-state Handshake Burst Suspend/Resume at ad-

dress 3Eh (or offset from 3Eh).............................................................. 58

Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at ad-

dress 3Fh (or offset from 3Fh by a multiple of 64) ................................ 58

Figure 22. Standard Handshake Burst Suspend prior to Initial Access 59

Figure 23. Standard Handshake Burst Suspend at or after Inital Access..

59

Figure 24. Standard Handshake Burst Suspend at address 3Fh (starting

address 3Dh or earlier) ......................................................................... 60

Figure 25. Standard Handshake Burst Suspend at address 3Eh/3Fh (with-

out a valid Initial Access)....................................................................... 60

Figure 26. Standard Handshake Burst Suspend at address 3Eh/3Fh (with

1 Access CLK) ...................................................................................... 61

Figure 27. Read Cycle for Continuous Suspend................................... 61

Asynchronous Mode Read (V_IO= 1.8 V) ......................................62

Erase/Program Operations (V_IO= 1.8 V) ..................................... 65

Figure 31. Asynchronous Program Operation Timings: AVD# Latched Ad-

dresses ................................................................................................. 66

Figure 32. Asynchronous Program Operation Timings: WE# Latched Ad-

dresses ................................................................................................. 67

Figure 33. Synchronous Program Operation Timings: WE# Latched Ad-

dresses ................................................................................................. 68

Figure 34. Synchronous Program Operation Timings: CLK Latched Ad-

dresses ................................................................................................. 69

Figure 35. Chip/Sector Erase Command Sequence............................. 70

Figure 36. Accelerated Unlock Bypass Programming Timing .............. 71

Figure 37. Data# Polling Timings (During Embedded Algorithm)......... 72

Figure 38. Toggle Bit Timings (During Embedded Algorithm) .............. 72

Figure 39. Synchronous Data Polling Timings/Toggle Bit Timings....... 73

Figure 40. DQ2 vs. DQ6 ....................................................................... 73

Temporary Sector Unprotect ........................................................ 74

Figure 41. Temporary Sector Unprotect Timing Diagram..................... 74

Figure 42. Sector/Sector Block Protect and

Unprotect Timing Diagram.................................................................... 75

Figure 43. Latency with Boundary Crossing......................................... 76

Figure 44. Latency with Boundary Crossing

into Program/Erase Bank...................................................................... 77

Figure 45. Example of Wait States Insertion ........................................ 78

Figure 46. Back-to-Back Read/Write Cycle Timings............................. 79

SRAM AC Characteristics . . . . . . . . . . . . . . . . . . 80

Read Cycle ...................................................................................80

Figure 47. SRAM Read Cycle—Address Controlled ............................ 80

Figure 48. SRAM Read Cycle............................................................... 81

Write Cycle ...................................................................................82

Figure 49. SRAM Write Cycle—WE# Control....................................... 82

Figure 50. SRAM Write Cycle—CE1#s Control.................................... 83

Figure 51. SRAM Write Cycle—UB#s and LB#s Control...................... 84

Erase and Programming Performance . . . . . . . 85

BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 85

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 86

TLB 089—89-ball Fine-Pitch Ball Grid Array (FBGA) 10 x

8 mm Package .............................................................................86

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 87

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 28. Asynchronous Mode Read with Latched Addresses ........... 63

Figure 29. Asynchronous Mode Read................................................... 63

October 23, 2003

Am42BDS6408H

5

A D V A N C E I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Part Number

Am42BDS6408H

66 MHz 54 MHz

E8, E9 E3, E4 D8, D9 D3, D4

Burst Frequency

Speed Option

V

, V = 1.65 – 1.95 V

IO

CC

Max Initial Synchronous Access Time, ns (T

)

IACC

56

71

56

71

69

Reduced Wait-state Handshaking; Even Address

Max Initial Synchronous Access Time, ns (T

)

IACC

87.5

Reduced Wait-state Handshaking; Odd Address; or Standard Handshaking

Max Burst Access Time, ns (T

)

11

13.5

BACC

Max Asynchronous Access Time, ns (T

)

ACC

50

55

Max CE# Access Time, ns (T

Max OE# Access Time, ns (T

)

CE

)

13.5

OE

Max Access time, ns (t

)

70

35

55

25

70

35

55

25

ACC

Max CE# Access time, ns (t

)

CE

Max OE# Access, ns (t

)

OE

Note: Speed Options ending in “8” and “6” indicate the “reduced wait-state handshaking” option, which speeds initial

synchronous accesses for even addresses.

Speed Options ending in “9” and “7” indicate the “standard handshaking” option.

See the AC Characteristics section of this datasheet for full specifications.

6

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

FLASH MEMORY BLOCK DIAGRAM

V

CC

V

SS

V

SSIO

DQ15–DQ0

V

IO

RDY

Buffer

Erase Voltage

Generator

Input/Output

Buffers

WE#

RESET#

WP#

State

Control

Command

Register

ACC

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

CE#

OE#

Y-Decoder

Y-Gating

V

CC

Timer

Detector

Cell Matrix

X-Decoder

Burst

State

Control

Burst

Address

Counter

AVD#

CLK

A21–A0

October 23, 2003

Am42BDS6408H

7

A D V A N C E I N F O R M A T I O N

BLOCK DIAGRAM OF SIMULTANEOUS

OPERATION CIRCUIT

V

CC

V

SS

IO

Bank A Address

DQ15–DQ0

Bank A

A21–A0

X-Decoder

OE#

Bank B Address

DQ15–DQ0

Bank B

WP#

ACC

X-Decoder

A21–A0

STATE

CONTROL

&

COMMAND

REGISTER

RESET#

WE#

DQ15–DQ0

Status

CE#

AVD#

RDY

Control

A21–A0

DQ15–DQ0

X-Decoder

Bank C

DQ15–DQ0

Bank C Address

A21–A0

X-Decoder

Bank D

Bank D Address

DQ15–DQ0

8

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAM

89-ball Fine-Pitch Ball Grid Array

(Top View, Balls Facing Down)

A9

A10

NC

A1

A2

A3

A4

A5

A6

A7

A8

Flash Only

SRAM Only

NC

ADV#

V_SS

CLK

NC

B9

B1

B2

B3

A7

B4

B5

B6

B7

A8

B8

A11

NC

WP#

LB#

ACC

WE#

C9

C2

A3

C3

A6

C4

C5

C6

C7

C8

A15

UB#

RESET# CE2s

A19

A12

D9

D2

A2

D3

A5

D4

D5

D6

D7

A9

D8

A21

A18

RDY

A20

A13

E9

E10

NC

E1

E2

A1

E3

A4

E4

E5

E6

E7

E8

NC

A17

NC

A10

A14

F9

F10

NC

F1

F2

A0

F3

F4

F5

F6

F7

F8

A16

NC

V_SS

DQ1

NC

DQ6

NC

G9

NC

G2

G3

G4

G5

G6

G7

G8

DQ15

CE#f

OE#

DQ9

DQ3

DQ4

DQ13

H9

H7

H2

H3

H4

H5

H6

H8

V_SS

CE1#s

DQ0

DQ10

V_CC

f

V_CCs

DQ12

DQ7

J9

J2

J3

J4

J5

J6

J7

J8

DQ14

NC

DQ8

DQ2

DQ11

K5

NC

DQ5

K9

K7

K10

NC

K1

K2

K3

K4

K6

K8

NC

V_SS

V_IOf

NC

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be compro-

mised if the package body is exposed to temperatures

above 150°C for prolonged periods of time.

Special Handling Instructions for FBGA

Package

Special handling is required for Flash Memory products

in FBGA packages.

October 23, 2003

Am42BDS6408H

9

A D V A N C E I N F O R M A T I O N

High = device ignores address in-

PIN DESCRIPTION

puts

A18–A0

A21–A19

DQ15–DQ0

CE#f

=

19 Address Inputs (Common)

3 Address Inputs (Flash)

16 Data Inputs/Outputs (Common)

Chip Enable (Flash)

WP#

=

Hardware write protect input. At V_IL,

disables program and erase func-

tions in the two outermost sectors.

Should be at V_IHfor all other condi-

tions.

CE1#s

CE2s

Chip Enable 1 (SRAM)

ACC

=

At V_ID, accelerates programming;

automatically places device in un-

lock bypass mode. At V_IL, locks all

sectors. Should be at V_IHfor all

other conditions.

Chip Enable 2 (SRAM)

OE#

Output Enable (Common)

Write Enable (Common)

Upper Byte Control (SRAM)

Lower Byte Control (SRAM)

Hardware Reset Pin, Active Low

WE#

UB#s

LB#s

LOGIC SYMBOL

RESET#

19

V_CC

f

Flash 1.8 volt-only single power

supply (see Product Selector Guide

for speed options andvoltage supply

tolerances)

A18–A0

A21–A19

CE#f

V_IOf

V_CC

=

Input & Output Buffer Power Supply

16

must be tied to V_CC

.

CE1#s

CE2s

OE#

DQ15–DQ0

RDY

s

=

SRAM Power Supply

V

_SSIOf

Output Buffer Ground

V_SS

NC

Device Ground (Common)

Pin Not Connected Internally

WE#

WP#

RDY

Ready output; indicates the status of

the Burst read. Low = data not valid

at expected time. High = data valid.

RESET#

UB#s

LB#s

ACC

CLK

=

CLK is not required in asynchronous

mode. In burst mode, after the initial

word is output, subsequent active

edges of CLK increment the internal

address counter.

AVD#

CLK

AVD#

Address Valid input. Indicates to de-

vice that the valid address is present

on the address inputs (A21–A0).

Low = for asynchronous mode, indi-

cates valid address; for burst mode,

causes starting address to be

latched.

10

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following:

Am42BDS6408

H

D

8

I

T

Tape and Reel

T

S

=

7 Inches

13 Inches

TEMPERATURE RANGE

Industrial (–40°C to +85°C)

I

=

HANDSHAKING OPTIONS + SRAM speed

8

=

Reduced wait-state handshaking

Enabled + 70 ns SRAM

9

3

=

Standard handshaking + 70 ns SRAM

Reduced Wait-state handshaking

Enabled + 55 ns SRAM

4

=

Standard handshaking + 55 ns SRAM

SPEED

E

D

=

66 MHz

54 MHz

PROCESS TECHNOLOGY

0.13 um

H

=

DEVICE NUMBER/DESCRIPTION

Am42BDS6408H

64 Megabit (4 M x 16-Bit) CMOS Flash Memory, Simultaneous Read/Write,

Burst Mode Flash Memory, 1.8 Volt-only Read, Program, and Erase

8 Mb (512 K x 16-bit) SRAM

WP# at V level protects top and bottom sectors

IL

Valid Combinations

Valid Combinations list configurations planned to be supported in

volume for this device. Consult the local AMD sales office to con-

firm availability of specific valid combinations and to check on

newly released combinations.

Valid Combinations

Package

Flash

Burst

Frequency

(MHz)

SRAM

Speed

(ns)

Marking

Order Number

Am42BDS6408HE8

Am42BDS6408HE9

Am42BDS6408HD8

Am42BDS6408HD9

Am42BDS6408HE3

Am42BDS6408HE4

Am42BDS6408HD3

Am42BDS6408HD4

Note: For the Am29BDS640H, the last digit of the speed

M420000070

M420000071

M420000072

M420000073

M420000074

M420000075

M420000076

M420000077

grade specifies the V range of the device. Speed options

IO

66

54

66

54

ending in “8” and “9” (e.g., D8, D9) indicate a 1.8 Volt V

range.

IO

70

55

I

October 23, 2003

Am42BDS6408H

11

A D V A N C E I N F O R M A T I O N

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state

machine. The state machine outputs dictate the func-

tion of the device. Table 1 lists the device bus opera-

tions, the inputs and control levels they require, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1. Device Bus Operations

CLK

(See

Operation

CE#

L

OE#

L

WE#

H

A21–0

Addr In

HIGH Z

DQ15–0 RESET# Note) AVD#

Asynchronous Read - Addresses Latched

Asynchronous Read - Addresses Steady State

Asynchronous Write

I/O

H

L

X

L

H

L

H

L

I/O

Synchronous Write

L

H

L

I/O

Standby (CE#)

H

X

HIGH Z

X

Hardware Reset

X

Burst Read Operations

Load Starting Burst Address

L

X

L

H

Addr In

HIGH Z

X

H

Advance Burst to next address with appropriate

Data presented on the Data Bus

Burst

Data Out

H

Terminate current Burst read cycle

H

X

H

HIGH Z

H

L

X

Terminate current Burst read cycle via RESET#

X

Terminate current Burst read cycle and start

new Burst read cycle

L

X

H

HIGH Z

I/O

H

Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions.

Note: Default active edge of CLK is the rising edge.

Address access time (t_ACC) is equal to the delay from

stable addresses to valid output data. The chip enable

access time (t_CE) is the delay from the stable

addresses and stable CE# to valid data at the outputs.

The output enable access time (t_OE) is the delay from

the falling edge of OE# to valid data at the output.

VersatileIO™ (V ) Control

IO

The VersatileIO^TM(V_IO) control allows the host system

to set the voltage levels that the device generates at its

data outputs and the voltages tolerated at its data

inputs to the same voltage level that is asserted on the

V

_IOpin.

The internal state machine is set for reading array data

in asynchronous mode upon device power-up, or after

a hardware reset. This ensures that no spurious alter-

ation of the memory content occurs during the power

transition.

Requirements for Asynchronous Read

Operation (Non-Burst)

To read data from the memory array, the system must

first assert a valid address on A21–A0, while driving

AVD# and CE# to V_IL. WE# should remain at V_IH. The

rising edge of AVD# latches the address. The data will

appear on DQ15–DQ0. Since the memory array is

divided into four banks, each bank remains enabled for

read access until the command register contents are

altered.

Requirements for Synchronous (Burst)

Read Operation

The device is capable of continuous sequential burst

operation and linear burst operation of a preset length.

12

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

When the device first powers up, it is enabled for asyn-

chronous read operation.

If the clock frequency is less than 6 MHz during a burst

mode operation, additional latencies will occur. RDY

indicates the length of the latency by pulsing low.

Prior to entering burst mode, the system should deter-

mine how many wait states are desired for the initial

word (t_IACC) of each burst access, what mode of burst

operation is desired, which edge of the clock will be the

active clock edge, and how the RDY signal will transi-

tion with valid data. The system would then write the

configuration register command sequence. See “Set

Configuration Register Command Sequence” section

on page 30 and “Command Definitions” section on

page 30 for further details.

8-, 16-, and 32-Word Linear Burst with Wrap Around

The remaining three modes are of the linear wrap

around design, in which a fixed number of words are

read from consecutive addresses. In each of these

modes, the burst addresses read are determined by

the group within which the starting address falls. The

groups are sized according to the number of words

read in a single burst sequence for a given mode (see

Table 2.)

Once the system has written the “Set Configuration

Register” command sequence, the device is enabled

for synchronous reads only.

Table 2. Burst Address Groups

Mode

8-word

16-word

32-word

Group Size Group Address Ranges

The initial word is output t_IACCafter the active edge of

the first CLK cycle. Subsequent words are output t_BACC

after the active edge of each successive clock cycle,

which automatically increments the internal address

counter. Note that the device has a fixed internal

address boundary that occurs every 64 words, starting

at address 00003Fh. During the time the device is out-

putting data at this fixed internal address boundary

(address 00003Fh, 00007Fh, 0000BFh, etc.), a two

cycle latency occurs before data appears for the next

address (address 000040h, 000080h, 0000C0h, etc.).

The RDY output indicates this condition to the system

by pulsing low. For standard handshaking devices,

there is no two cycle latency between 3Fh and 40h (or

offset from these values by a multiple of 64) if the

latched address was 3Eh or 3Fh (or offset from these

values by a multiple of 64). See Figure 43, “Latency

with Boundary Crossing,” on page 76.

8 words

16 words

32 words

0-7h, 8-Fh, 10-17h,...

0-Fh, 10-1Fh, 20-2Fh,...

00-1Fh, 20-3Fh, 40-5Fh,...

As an example: if the starting address in the 8-word

mode is 39h, the address range to be read would be

38-3Fh, and the burst sequence would be

39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence

begins with the starting address written to the device,

but wraps back to the first address in the selected

group. In a similar fashion, the 16-word and 32-word

Linear Wrap modes begin their burst sequence on the

starting address written to the device, and then wrap

back to the first address in the selected address group.

Note that in these three burst read modes the

address pointer does not cross the boundary that

occurs every 64 words; thus, no wait states are

inserted (except during the initial access).

For reduced wait-state handshaking devices, if the

address latched is 3Eh or 3Fh (or offset from these

values by a multiple of 64) two additional cycle latency

occurs prior to the initial access and the two cycle

latency between 3Fh and 40h (or offset from these

values by a multiple of 64) will not occur.

The RDY pin indicates when data is valid on the bus.

The devices can wrap through a maximum of 128

words of data (8 words up to 16 times, 16 words up to

8 times, or 32 words up to 4 times) before requiring a

new synchronous access (latching of a new address).

The device will continue to output sequential burst

data, wrapping around to address 000000h after it

reaches the highest addressable memory location,

until the system drives CE# high, RESET# low, or

AVD# low in conjunction with a new address. See

Table 1, “Device Bus Operations,” on page 12.

Burst Suspend/Resume

The Burst Suspend/Resume feature allows the system

to temporarily suspend a synchronous burst operation

during the initial access (before data is available) or

after the device is outputting data. When the burst

operation is suspended, any previously latched internal

data and the current state are retained.

If the host system crosses the bank boundary while

reading in burst mode, and the device is not program-

ming or erasing, a two-cycle latency will occur as

described above in the subsequent bank. If the host

system crosses the bank boundary while the device is

programming or erasing, the device will provide read

status information. The clock will be ignored. After the

host has completed status reads, or the device has

completed the program or erase operation, the host

can restart a burst operation using a new address and

AVD# pulse.

Burst Suspend requires CE# to be asserted, WE#

de-asserted, and the initial address latched by AVD# or

the CLK edge. Burst Suspend occurs when OE# is

de-asserted. See Figure 18, “Reduced Wait-state

Handshake Burst Suspend/Resume at an even

address,” on page 57, Figure 19, “Reduced Wait-state

Handshake Burst Suspend/Resume at an odd

address,” on page 57, Figure 20, “Reduced Wait-state

October 23, 2003

Am42BDS6408H

13

A D V A N C E I N F O R M A T I O N

Handshake Burst Suspend/Resume at address 3Eh (or

The autoselect function allows the host system to

determine whether the flash device is enabled for

reduced wait-state handshaking. See the “Autoselect

Command Sequence” section for more information.

offset from 3Eh),” on page 58, Figure 21, “Reduced

Wait-state Handshake Burst Suspend/Resume at

address 3Fh (or offset from 3Fh by a multiple of 64),” on

page 58, Figure 22, “Standard Handshake Burst

Suspend prior to Initial Access,” on page 59, Figure 23,

“Standard Handshake Burst Suspend at or after Inital

Access,” on page 59, Figure 24, “Standard Handshake

Burst Suspend at address 3Fh (starting address 3Dh

or earlier),” on page 60, Figure 25, “Standard Hand-

shake Burst Suspend at address 3Eh/3Fh (without a

valid Initial Access),” on page 60, and Figure 26, “Stan-

dard Handshake Burst Suspend at address 3Eh/3Fh

(with 1 Access CLK),” on page 61.

Simultaneous Read/Write Operations with

Zero Latency

This device is capable of reading data from one bank of

memory while programming or erasing in another bank

of memory. An erase operation may also be suspended

to read from or program to another location within the

same bank (except the sector being erased).

Figure 46, “Back-to-Back Read/Write Cycle Timings,”

on page 79 shows how read and write cycles may be

initiated for simultaneous operation with zero latency.

Refer to the DC Characteristics table for

read-while-program and read-while-erase current

specifications.

Burst plus Burst Suspend should not last longer than

t_RCCwithout re-latching an address or crossing an

address boundary. To resume the burst access, OE#

must be re-asserted. The next active CLK edge will

resume the burst sequence where it had been sus-

pended. See, Figure 27, “Read Cycle for Continuous

Suspend,” on page 61.

Writing Commands/Command Sequences

The device has the capability of performing an asyn-

chronous or synchronous write operation. While the

device is configured in Asynchronous read it is able to

perform Asynchronous write operations only. CLK is

ignored in the Asynchronous programming mode.

When in the Synchronous read mode configuration, the

device is able to perform both Asynchronous and Syn-

chronous write operations. CLK and WE# address

latch is supported in the Synchronous programming

mode. During a synchronous write operation, to write a

command or command sequence (which includes pro-

gramming data to the device and erasing sectors of

memory), the system must drive AVD# and CE# to V_IL,

and OE# to V_IHwhen providing an address to the

device, and drive WE# and CE# to V_IL, and OE# to V_IH

when writing commands or data. During an asynchro-

nous write operation, the system must drive CE# and

WE# to V_ILand OE# to V_IHwhen providing an address,

command, and data. Addresses are latched on the last

falling edge of WE# or CE#, while data is latched on the

1st rising edge of WE# or CE#. The asynchronous and

synchronous programing operation is independent of

the Set Device Read Mode bit in the Configuration

Register (see Table 15, “Configuration Register,” on

page 33).

The RDY pin is only controlled by CE#. RDY will remain

active and is not placed into a high-impedance state

when OE# is de-asserted.

Configuration Register

The device uses a configuration register to set the

various burst parameters: number of wait states, burst

read mode, active clock edge, RDY configuration, and

synchronous mode active.

Reduced Wait-state Handshaking Option

The device can be equipped with a reduced wait-state

handshaking feature that allows the host system to

simply monitor the RDY signal from the device to deter-

mine when the initial word of burst data is ready to be

read. The host system should use the programmable

wait state configuration to set the number of wait states

for optimal burst mode operation. The initial word of

burst data is indicated by the rising edge of RDY after

OE# goes low.

The presence of the reduced wait-state handshaking

feature may be verified by writing the autoselect

command sequence to the device. See “Autoselect

Command Sequence” for details.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are

required to program a word, instead of four.

For optimal burst mode performance on devices

without the reduced wait-state handshaking option, the

host system must set the appropriate number of wait

states in the flash device depending on clock frequency

and the presence of a boundary crossing. See “Set

Configuration Register Command Sequence” section

on page 30 section for more information. The device

will automatically delay RDY and data by one additional

clock cycle when the starting address is odd.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 10, “Sector Address

Table,” on page 26 indicates the address space that

each sector occupies. The device address space is

divided into four banks: Banks B and C contain only 32

Kword sectors, while Banks A and D contain both 4

Kword boot sectors in addition to 32 Kword sectors. A

14

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

“bank address” is the address bits required to uniquely

mode and uses the higher voltage on the input to

reduce the time required for program operations. The

system would use a two-cycle program command

sequence as required by the Unlock Bypass mode.

Removing V_HHfrom the ACC input returns the device

to normal operation. Note that sectors must be

unlocked prior to raising ACC to V_HH. Note that the

ACC pin must not be at V_HHfor operations other than

accelerated programming, or device damage may

result. In addition, the ACC pin must not be left floating

or unconnected; inconsistent behavior of the device

may result.

select a bank. Similarly, a “sector address” is the

address bits required to uniquely select a sector.

I_CC2in the “DC Characteristics” section on page 49

represents the active current specification for the write

mode. The AC Characteristics section contains timing

specification tables and timing diagrams for write oper-

ations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. ACC is primarily intended to

allow faster manufacturing throughput at the factory.

When at V_IL, ACC locks all sectors. ACC should be at

V

_IHfor all other conditions.

If the system asserts V_HHon this input, the device auto-

matically enters the aforementioned Unlock Bypass

October 23, 2003

Am42BDS6408H

15

A D V A N C E I N F O R M A T I O N

Table 3. Am42BDS6408H Boot Sector/Sector

Sector/

Block Addresses for Protection/Unprotection

Sector

SA135

SA136

SA137

SA138

SA139

SA140

SA141

A21–A12

Sector Block Size

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

4 Kwords

Sector/

Sector

SA0

A21–A12

Sector Block Size

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

1111100XXX

1111101XXX

1111110XXX

1111111000

4 Kwords

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

Sector/Sector Block Protection and Un-

protection

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

The hardware sector protection feature disables both

programming and erase operations in any sector. The

hardware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

SA8

32 Kwords

SA9

32 Kwords

SA10

32 Kwords

SA11–SA14

SA15–SA18

SA19–SA22

SA23-SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51–SA54

SA55–SA58

SA59–SA62

SA63–SA66

SA67–SA70

SA71–SA74

SA75–SA78

SA79–SA82

SA83–SA86

SA87–SA90

SA91–SA94

SA95–SA98

SA99–SA102

SA103–SA106

SA107–SA110

SA111–SA114

SA115–SA118

SA119–SA122

SA123–SA126

SA127–SA130

SA131

128 (4x32) Kwords

32 Kwords

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Table 3,

“Am42BDS6408H Boot Sector/Sector Block

Addresses for Protection/Unprotection,” on page 16

Sector Protection

The Am42BDS6408H features several levels of sector

protection, which can disable both the program and

erase operations in certain sectors or sector groups:

Persistent Sector Protection

A command sector protection method that replaces

the old 12 V controlled protection method.

Password Sector Protection

A highly sophisticated protection method that requires

a password before changes to certain sectors or sec-

tor groups are permitted

WP# Hardware Protection

A write protect pin that can prevent program or erase

operations in the outermost sectors.

The WP# Hardware Protection feature is always avail-

able, independent of the software managed protection

method chosen.

Selecting a Sector Protection Mode

All parts default to operate in the Persistent Sector

Protection mode. The customer must then choose if

the Persistent or Password Protection method is most

desirable. There are two one-time programmable

non-volatile bits that define which sector protection

method will be used. If the customer decides to con-

tinue using the Persistent Sector Protection method,

they must set the Persistent Sector Protection Mode

Locking Bit. This will permanently set the part to op-

SA132

32 Kwords

SA133

32 Kwords

SA134

4 Kwords

16

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

erate only using Persistent Sector Protection. If the

ity of the user to perform the preprogramming

operation. Otherwise, an already erased sector PPBs

has the potential of being over-erased. There is no

hardware mechanism to prevent sector PPBs

over-erasure.

customer decides to use the password method, they

must set the Password Mode Locking Bit. This will

permanently set the part to operate only using pass-

word sector protection.

It is important to remember that setting either the Per-

sistent Sector Protection Mode Locking Bit or the

Password Mode Locking Bit permanently selects the

protection mode. It is not possible to switch between

the two methods once a locking bit has been set. It is

important that one mode is explicitly selected

when the device is first programmed, rather than

relying on the default mode alone. This is so that it

is not possible for a system program or virus to later

set the Password Mode Locking Bit, which would

cause an unexpected shift from the default Persistent

Sector Protection Mode into the Password Protection

Mode.

Persistent Protection Bit Lock (PPB Lock)

A global volatile bit. When set to “1”, the PPBs cannot

be changed. When cleared (“0”), the PPBs are

changeable. There is only one PPB Lock bit per de-

vice. The PPB Lock is cleared after power-up or hard-

ware reset. There is no command sequence to unlock

the PPB Lock.

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector.

After power-up or hardware reset, the contents of all

DYBs is “0”. Each DYB is individually modifiable

through the DYB Write Command.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at the factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

When the parts are first shipped, the PPBs are

cleared. The DYBs and PPB Lock are defaulted to

power up in the cleared state – meaning the PPBs are

changeable.

When the device is first powered on the DYBs power

up cleared (sectors not protected). The Protection

State for each sector is determined by the logical OR

of the PPB and the DYB related to that sector. For the

sectors that have the PPBs cleared, the DYBs control

whether or not the sector is protected or unprotected.

By issuing the DYB Write command sequences, the

DYBs will be set or cleared, thus placing each sector in

the protected or unprotected state. These are the

so-called Dynamic Locked or Unlocked states. They

are called dynamic states because it is very easy to

switch back and forth between the protected and un-

protected conditions. This allows software to easily

protect sectors against inadvertent changes yet does

not prevent the easy removal of protection when

changes are needed. The DYBs maybe set or cleared

as often as needed.

It is possible to determine whether a sector is pro-

tected or unprotected. See “Autoselect Command Se-

quence” section on page 33 for details.

Persistent Sector Protection

The Persistent Sector Protection method replaces the

old 12 V controlled protection method while at the

same time enhancing flexibility by providing three dif-

ferent sector protection states:

■ Persistently Locked—A sector is protected and

cannot be changed.

■ Dynamically Locked—The sector is protected and

can be changed by a simple command

■ Unlocked—The sector is unprotected and can be

changed by a simple command

In order to achieve these states, three types of “bits”

are going to be used:

The PPBs allow for a more static, and difficult to

change, level of protection. The PPBs retain their state

across power cycles because they are Non-Volatile.

Individual PPBs are set with a command but must all

be cleared as a group through a complex sequence of

program and erasing commands. The PPBs are also

limited to 100 erase cycles.

Persistent Protection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is as-

signed to a maximum four sectors (“Am42BDS6408H

Boot Sector/Sector Block Addresses for Protec-

tion/Unprotection” section on page 16). All 4 Kbyte

boot-block sectors have individual sector Persistent

Protection Bits (PPBs) for greater flexibility. Each PPB

is individually modifiable through the PPB Program

Command.

The PBB Lock bit adds an additional level of protec-

tion. Once all PPBs are programmed to the desired

settings, the PPB Lock may be set to “1”. Setting the

PPB Lock disables all program and erase commands

to the Non-Volatile PPBs. In effect, the PPB Lock Bit

locks the PPBs into their current state. The only way to

clear the PPB Lock is to go through a power cycle.

System boot code can determine if any changes to the

Note: If a PPB requires erasure, all of the sector PPBs

must first be preprogrammed prior to PPB erasing. All

PPBs erase in parallel, unlike programming where in-

dividual PPBs are programmable. It is the responsibil-

October 23, 2003

Am42BDS6408H

17

A D V A N C E I N F O R M A T I O N

PPB are needed e.g. to allow new system code to be

In summary, if the PPB is set, and the PPB lock is set,

the sector is protected and the protection can not be

removed until the next power cycle clears the PPB

lock. If the PPB is cleared, the sector can be dynami-

cally locked or unlocked. The DYB then controls

whether or not the sector is protected or unprotected.

downloaded. If no changes are needed then the boot

code can set the PPB Lock to disable any further

changes to the PPBs during system operation.

The WP# write protect pin adds a final level of hard-

ware protection to the four highest and four lowest 4

Kbyte sectors (SA0 - SA3, SA138 - SA141 for a dual

boot). When this pin is low it is not possible to change

the contents of these four sectors. These sectors gen-

erally hold system boot code. So, the WP# pin can

prevent any changes to the boot code that could over-

ride the choices made while setting up sector protec-

tion during system initialization.

If the user attempts to program or erase a protected

sector, the device ignores the command and returns to

read mode. A program command to a protected sector

enables status polling for approximately 1 µs before

the device returns to read mode without having modi-

fied the contents of the protected sector. An erase

command to a protected sector enables status polling

for approximately 50 µs after which the device returns

to read mode without having erased the protected sec-

tor.

It is possible to have sectors that have been persis-

tently locked, and sectors that are left in the dynamic

state. The sectors in the dynamic state are all unpro-

tected. If there is a need to protect some of them, a

simple DYB Write command sequence is all that is

necessary. The DYB write command for the dynamic

sectors switch the DYBs to signify protected and un-

protected, respectively. If there is a need to change the

status of the persistently locked sectors, a few more

steps are required. First, the PPB Lock bit must be dis-

abled by either putting the device through a power-cy-

cle, or hardware reset. The PPBs can then be

changed to reflect the desired settings. Setting the

PPB lock bit once again will lock the PPBs, and the de-

vice operates normally again.

The programming of the DYB, PPB, and PPB lock for a

given sector can be verified by writing a

DYB/PPB/PPB lock verify command to the device.

Persistent Sector Protection Mode

Locking Bit

Like the password mode locking bit, a Persistent Sec-

tor Protection mode locking bit exists to guarantee that

the device remain in software sector protection. Once

set, the Persistent Sector Protection locking bit pre-

vents programming of the password protection mode

locking bit. This guarantees that a hacker could not

place the device in password protection mode.

Note: to achieve the best protection, it’s recommended

to execute the PPB lock bit set command early in the

boot code, and protect the boot code by holding WP#

= V_IL.

Password Protection Mode

The Password Sector Protection Mode method allows

an even higher level of security than the Persistent

Sector Protection Mode. There are two main differ-

ences between the Persistent Sector Protection and

the Password Sector Protection Mode:

Table 4. Sector Protection Schemes

PPB

Lock

■ When the device is first powered on, or comes out

of a reset cycle, the PPB Lock bit is set to the

locked state, rather than cleared to the unlocked

state.

DYB

PPB

Sector State

Unprotected—PPB and DYB are

changeable

0

■ The only means to clear the PPB Lock bit is by writ-

ing a unique 64-bit Password to the device.

Unprotected—PPB not

changeable, DYB is changeable

0

1

The Password Sector Protection method is otherwise

identical to the Persistent Sector Protection method.

0

1

0

1

0

1

0

1

0

1

Protected—PPB and DYB are

changeable

A 64-bit password is the only additional tool utilized in

this method.

The password is stored in a one-time programmable

(OTP) region of the flash memory. Once the Password

Mode Locking Bit is set, the password is permanently

set with no means to read, program, or erase it. The

password is used to clear the PPB Lock bit. The Pass-

word Unlock command must be written to the flash,

along with a password. The flash device internally

compares the given password with the pre-pro-

Protected—PPB not

changeable, DYB is changeable

Table 4 contains all possible combinations of the DYB,

PPB, and PPB lock relating to the status of the sector.

18

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

grammed password. If they match, the PPB Lock bit is

Password Verify command from reading the contents

of the password on the pins of the device.

cleared, and the PPBs can be altered. If they do not

match, the flash device does nothing. There is a

built-in 2 µs delay for each “password check.” This

delay is intended to thwart any efforts to run a program

that tries all possible combinations in order to crack

the password.

Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile

bit that reflects the state of the Password Mode Lock-

ing Bit after power-up reset. If the Password Mode

Lock Bit is also set, after a hardware reset (RESET#

asserted) or a power-up reset the ONLY means for

clearing the PPB Lock Bit in Password Protection

Mode is to issue the Password Unlock command. Suc-

cessful execution of the Password Unlock command

clears the PPB Lock Bit, allowing for sector PPBs

modifications. Asserting RESET#, taking the device

through a power-on reset, or issuing the PPB Lock Bit

Set command sets the PPB Lock Bit to a “1”.

Password and Password Mode Locking Bit

In order to select the Password sector protection

scheme, the customer must first program the pass-

word. AMD recommends that the password be

somehow correlated to the unique Electronic Serial

Number (ESN) of the particular flash device. Each ESN

is different for every flash device; therefore each pass-

word should be different for every flash device. While

programming in the password region, the customer

may perform Password Verify operations.

If the Password Mode Locking Bit is not set, including

Persistent Protection Mode, the PPB Lock Bit is

cleared after power-up or hardware reset. The PPB

Lock Bit is set by issuing the PPB Lock Bit Set com-

mand. Once set the only means for clearing the PPB

Lock Bit is by issuing a hardware or power-up reset.

The Password Unlock command is ignored in Persis-

tent Protection Mode.

Once the desired password is programmed in, the

customer must then set the Password Mode Locking

Bit. This operation achieves two objectives:

1. It permanently sets the device to operate using the

Password Protection Mode. It is not possible to re-

verse this function.

2. It also disables all further commands to the pass-

word region. All program, and read operations are

ignored.

High Voltage Sector Protection

Sector protection and unprotection may also be imple-

mented using programming equipment. The procedure

requires high voltage (V_ID) to be placed on the

RESET# pin. Refer to Figure 2, “In-System Sector Pro-

tection/ Sector Unprotection Algorithms,” on page 21

for details on this procedure. Note that for sector unpro-

tect, all unprotected sectors must be first protected

prior to the first sector write cycle. Once the Password

Mode Locking bit or Persistent Protection Locking bit

are set, the high voltage sector protect/unprotect capa-

bility is disabled.

Both of these objectives are important, and if not care-

fully considered, may lead to unrecoverable errors.

The user must be sure that the Password Protection

method is desired when setting the Password Mode

Locking Bit. More importantly, the user must be sure

that the password is correct when the Password Mode

Locking Bit is set. Due to the fact that read operations

are disabled, there is no means to verify what the

password is afterwards. If the password is lost after

setting the Password Mode Locking Bit, there will be

no way to clear the PPB Lock bit.

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The Password Mode Locking Bit, once set, prevents

reading the 64-bit password on the DQ bus and further

password programming. The Password Mode Locking

Bit is not erasable. Once Password Mode Locking Bit

is programmed, the Persistent Sector Protection Lock-

ing Bit is disabled from programming, guaranteeing

that no changes to the protection scheme are allowed.

The device enters the CMOS standby mode when the

CE# and RESET# inputs are both held at V_CC0.2 V.

The device requires standard access time (t_CE) for read

access, before it is ready to read data.

64-bit Password

The 64-bit Password is located in its own memory

space and is accessible through the use of the Pass-

word Program and Verify commands (see “Password

Program Command” section on page 37 and “Pass-

word Verify Command” section on page 37). The

password function works in conjunction with the Pass-

word Mode Locking Bit, which when set, prevents the

If the device is deselected during erasure or program-

ming, the device draws active current until the opera-

tion is completed.

I_CC3in the “DC Characteristics” section on page 49

represents the standby current specification.

October 23, 2003

Am42BDS6408H

19

A D V A N C E I N F O R M A T I O N

Embedded Algorithms) before the device is ready to

Automatic Sleep Mode

read data again. If RESET# is asserted when a

program or erase operation is not executing, the reset

operation is completed within a time of t_READY(not

during Embedded Algorithms). The system can read

data t_RHafter RESET# returns to V_IH.

The automatic sleep mode minimizes Flash device

energy consumption. While in asynchronous mode, the

device automatically enables this mode when

addresses remain stable for t_ACC+ 60 ns. The auto-

matic sleep mode is independent of the CE#, WE#, and

OE# control signals. Standard address access timings

provide new data when addresses are changed. While

in sleep mode, output data is latched and always avail-

able to the system. While in synchronous mode, the

device automatically enables this mode when either the

first active CLK level is greater than t_ACCor the CLK

runs slower than 5 MHz. Note that a new burst opera-

tion is required to provide new data.

Refer to the “AC Characteristics” section on page 64 for

RESET# parameters and to Figure 30, “Reset Tim-

ings,” on page 64 for the timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The outputs are placed in the high imped-

ance state.

I_CC6in the “DC Characteristics” section on page 49

represents the automatic sleep mode current specifica-

tion.

Figure 1. Temporary Sector Unprotect Operation

START

RESET#: Hardware Reset Input

The RESET# input provides a hardware method of

resetting the device to reading array data. When

RESET# is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all outputs, resets the configuration

register, and ignores all read/write commands for the

duration of the RESET# pulse. The device also resets

the internal state machine to reading array data. The

operation that was interrupted should be reinitiated

once the device is ready to accept another command

sequence, to ensure data integrity.

RESET# = V

ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V

IH

Temporary Sector

Unprotect Completed

(Note 2)

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS0.2 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS0.2 V, the standby current will

be greater.

Notes:

RESET# may be tied to the system reset circuitry. A

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from

the Flash memory.

1. All protected sectors unprotected (If WP# = V ,

IL

outermost boot sectors will remain protected).

2. All previously protected sectors are protected once

again.

If RESET# is asserted during a program or erase oper-

ation, the device requires a time of t_READY(during

20

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

START

Protect all sectors:

PLSCNT = 1

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

RESET# = V_ID

Wait 1 µs

unprotect address

No

First Write

Cycle = 60h?

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

Yes

Set up first sector

address

A7–A0 =

00000010

Sector Unprotect:

Write 60h to sector

address with

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A7–A0 =

00000010

A7–A0 =

01000010

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

Read from

sector address

with A7–A0 =

00000010

Increment

PLSCNT

A7–A0 =

00000010

No

PLSCNT

= 25?

Read from

sector address

with A7–A0 =

00000010

Data = 01h?

Yes

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protection/

Sector Unprotection Algorithms

October 23, 2003

Am42BDS6408H

21

A D V A N C E I N F O R M A T I O N

the accelerated programming (ACC) and unlock by-

pass functions are not available when programming

the SecSi Sector.

SecSi™ (Secured Silicon) Sector

Flash Memory Region

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN) The 128-word SecSi sector is divided into 64

factory-lockable words that can be programmed and

locked by the customer. The SecSi sector is located at

addresses 000000h-00007Fh in both Persistent Pro-

tection mode and Password Protection mode. It uses

indicator bits (DQ6, DQ7) to indicate the fac-

tory-locked and customer-locked status of the part.

The Customer-lockable SecSi Sector area can be pro-

tected using one of the following procedures:

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, ex-

cept that RESET# may be at either V_IHor V_ID. This

allows in-system protection of the SecSi Sector Re-

gion without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi™ Sector/Exit

SecSi Sector Command Sequence”). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the ad-

dresses normally occupied by the boot sectors. This

mode of operation continues until the system issues

the Exit SecSi Sector command sequence, or until

power is removed from the device. On power-up, or

following a hardware reset, the device reverts to send-

ing commands to the normal address space.

■ Write the three-cycle Enter SecSi Sector Secure

Region command sequence, and then use the alter-

nate method of sector protection described in the

High Voltage Sector Protection section.

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region com-

mand sequence to return to reading and writing the

remainder of the array.

The SecSi Sector lock must be used with caution

since, once locked, there is no procedure available for

unlocking the SecSi Sector area and none of the bits

in the SecSi Sector memory space can be modified in

any way.

Factory-Locked Area (64 words)

The factory-locked area of the SecSi Sector

(000000h-00003Fh) is locked when the part is

shipped, whether or not the area was programmed at

the factory. The SecSi Sector Factory-locked Indicator

Bit (DQ7) is permanently set to a “1”. AMD offers the

ExpressFlash service to program the factory-locked

area with a random ESN, a customer-defined code, or

any combination of the two. Because only AMD can

program and protect the factory-locked area, this

method ensures the security of the ESN once the

product is shipped to the field. Contact an AMD repre-

sentative for details on using AMD’s ExpressFlash ser-

vice.

SecSi Sector Protection Bits

The SecSi Sector Protection Bits prevent program-

ming of the SecSi Sector memory area. Once set, the

SecSi Sector memory area contents are non-modifi-

able.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 16, “Com-

mand Definitions,” on page 40 for command defini-

tions).

Table 5. SecSi^TMSector Addresses

The device offers two types of data protection at the

sector level:

Sector Size

128 words

64 words

Address Range

000000h–00007Fh

000000h-00003Fh

000040h-00007Fh

Am42BDS6408H

Factory-Locked Area

Customer-Lockable Area

■ The PPB and DYB associated command se-

quences disables or re-enables both program and

erase operations in any sector or sector group.

64 words

Customer-Lockable Area (64 words)

■ When WP# is at V_IL, the four outermost sectors are

locked.

The customer-lockable area of the SecSi Sector

(000040h-00007Fh) is shipped unprotected, which al-

lows the customer to program and optionally lock the

area as appropriate for the application. The SecSi

Sector Customer-locked Indicator Bit (DQ6) is shipped

as “0” and can be permanently locked to “1” by issuing

the SecSi Protection Bit Program Command. The

SecSi Sector can be read any number of times, but

can be programmed and locked only once. Note that

■ When ACC is at V_IL, all sectors are locked.

The following hardware data protection measures

prevent accidental erasure or programming, which

might otherwise be caused by spurious system level

signals during V_CCpower-up and power-down transi-

tions, or from system noise.

22

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

CE# and WE# must be a logical zero while OE# is a

Write Protect (WP#)

logical one.

The Write Protect feature provides a hardware method

of protecting the four outermost sectors. This function

is provided by the WP# pin and overrides the previ-

ously discussed Sector Protection/Unprotection

method.

Power-Up Write Inhibit

If WE# = CE# = RESET# = V_ILand OE# = V_IHduring

power up, the device does not accept commands on

the rising edge of WE#. The internal state machine is

automatically reset to the read mode on power-up.

If the system asserts V_ILon the WP# pin, the device

disables program and erase functions in the eight “out-

ermost” 4 Kword boot sectors.

COMMON FLASH MEMORY INTERFACE

(CFI)

If the system asserts V_IHon the WP# pin, the device

reverts to whether sectors 0–3 and 138–141 were last

set to be protected or unprotected. That is, sector pro-

tection or unprotection for these sectors depends on

whether they were last protected or unprotected using

the method described in “PPB Program Command”

section on page 38.

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-indepen-

dent, JEDEC ID-independent, and forward- and back-

ward-compatible for the specified flash device families.

Flash vendors can standardize their existing interfaces

for long-term compatibility.

Note that the WP# pin must not be left floating or un-

connected; inconsistent behavior of the device may re-

sult.

This device enters the CFI Query mode when the

system writes the CFI Query command, 98h, to

address 55h any time the device is ready to read array

data. The system can read CFI information at the

addresses given in Tables 6-9. To terminate reading

CFI data, the system must write the reset command.

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not

accept any write cycles. This protects data during V_CC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets to reading array data. Subsequent writes

are ignored until V_CCis greater than V_LKO. The system

must provide the proper signals to the control inputs to

prevent unintentional writes when V_CCis greater than

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 6-9. The

system must write the reset command to return the

device to the autoselect mode.

V_LKO

.

Write Pulse “Glitch” Protection

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the AMD

site at the following URL:

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

http://www.amd.com/flash/cfi.

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

Alternatively, contact an AMD representative for copies

Table 6. CFI Query Identification String

Description

Addresses

Data

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

Primary OEM Command Set

13h

14h

0002h

0000h

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

0000h

October 23, 2003

Am42BDS6408H

23

A D V A N C E I N F O R M A T I O N

Table 7. System Interface String

Description

Addresses

Data

V

Min. (write/erase)

CC

1Bh

0017h

D7–D4: volt, D3–D0: 100 millivolt

V

Max. (write/erase)

CC

1Ch

0019h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0004h

0000h

0009h

0000h

0004h

0000h

0004h

0000h

V

Min. voltage (00h = no V pin present)

PP

Max. voltage (00h = no V pin present)

PP

N

Typical timeout per single byte/word write 2 µs

N

Typical timeout for Min. size buffer write 2 µs (00h = not supported)

N

Typical timeout per individual block erase 2 ms

N

Typical timeout for full chip erase 2 ms (00h = not supported)

N

Max. timeout for byte/word write 2 times typical

N

Max. timeout for buffer write 2 times typical

N

Max. timeout per individual block erase 2 times typical

N

Max. timeout for full chip erase 2 times typical (00h = not supported)

Table 8. Device Geometry Definition

Description

Addresses

Data

N

27h

0017h

Device Size = 2 byte

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

N

2Ah

2Bh

0000h

Max. number of bytes in multi-byte write = 2

(00h = not supported)

2Ch

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

007Dh

0000h

0001h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

0007h

0000h

0020h

0000h

39h

3Ah

3Bh

3Ch

0000h

24

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

Table 9. Primary Vendor-Specific Extended Query

Addresses

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

000Ch

Silicon Technology (Bits 5-2) 0011 = 0.13 µm

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

0002h

0001h

0000h

0007h

0077h

0001h

0000h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

07 = Advanced Sector Protection

Simultaneous Operation

Number of Sectors in all banks except boot block

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

4Fh

00B5h

00C5h

0001h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

01h = Dual Boot Device, 02h = Bottom Boot Device, 03h = Top Boot Device

50h

57h

58h

59h

5Ah

5Bh

0000h

0004h

0017h

0030h

0017h

Program Suspend. 00h = not supported

Bank Organization: X = Number of banks

Bank A Region Information. X = Number of sectors in bank

Bank B Region Information. X = Number of sectors in bank

Bank C Region Information. X = Number of sectors in bank

Bank D Region Information. X = Number of sectors in bank

October 23, 2003

Am42BDS6408H

25

A D V A N C E I N F O R M A T I O N

Table 10. Sector Address Table

Bank

Sector

SA0

Sector Size

4 Kwords

Address Range

000000h-000FFFh

001000h-001FFFh

002000h-002FFFh

003000h-003FFFh

004000h-004FFFh

005000h-005FFFh

006000h-006FFFh

007000h-007FFFh

008000h-00FFFFh

010000h-017FFFh

018000h-01FFFFh

020000h-027FFFh

028000h-02FFFFh

030000h-037FFFh

038000h-03FFFFh

040000h-047FFFh

048000h-04FFFFh

050000h-057FFFh

058000h-05FFFFh

060000h-067FFFh

068000h-06FFFFh

070000h-077FFFh

078000h-07FFFFh

080000h-087FFFh

088000h-08FFFFh

090000h-097FFFh

098000h-09FFFFh

0A0000h-0A7FFFh

0A8000h-0AFFFFh

0B0000h-0B7FFFh

0B8000h-0BFFFFh

0C0000h-0C7FFFh

0C8000h-0CFFFFh

0D0000h-0D7FFFh

0D8000h-0DFFFFh

0E0000h-0E7FFFh

0E8000h-0EFFFFh

0F0000h-0F7FFFh

0F8000h-0FFFFFh

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank D

Bank C

26

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

Bank

Sector

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Sector Size

32 Kwords

Address Range

100000h-107FFFh

108000h-10FFFFh

110000h-117FFFh

118000h-11FFFFh

120000h-127FFFh

128000h-12FFFFh

130000h-137FFFh

138000h-13FFFFh

140000h-147FFFh

148000h-14FFFFh

150000h-157FFFh

158000h-15FFFFh

160000h-167FFFh

168000h-16FFFFh

170000h-177FFFh

178000h-17FFFFh

180000h-187FFFh

188000h-18FFFFh

190000h-197FFFh

198000h-19FFFFh

1A0000h-1A7FFFh

1A8000h-1AFFFFh

1B0000h-1B7FFFh

1B8000h-1BFFFFh

1C0000h-1C7FFFh

1C8000h-1CFFFFh

1D0000h-1D7FFFh

1D8000h-1DFFFFh

1E0000h-1E7FFFh

1E8000h-1EFFFFh

1F0000h-1F7FFFh

1F8000h-1FFFFFh

Bank C

October 23, 2003

Am42BDS6408H

27

A D V A N C E I N F O R M A T I O N

Bank

Sector

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

Sector Size

32 Kwords

Address Range

200000h-207FFFh

208000h-20FFFFh

210000h-217FFFh

218000h-21FFFFh

220000h-227FFFh

228000h-22FFFFh

230000h-237FFFh

238000h-23FFFFh

240000h-247FFFh

248000h-24FFFFh

250000h-257FFFh

258000h-25FFFFh

260000h-267FFFh

268000h-26FFFFh

270000h-277FFFh

278000h-27FFFFh

280000h-287FFFh

288000h-28FFFFh

290000h-297FFFh

298000h-29FFFFh

2A0000h-2A7FFFh

2A8000h-2AFFFFh

2B0000h-2B7FFFh

2B8000h-2BFFFFh

2C0000h-2C7FFFh

2C8000h-2CFFFFh

2D0000h-2D7FFFh

2D8000h-2DFFFFh

2E0000h-2E7FFFh

2E8000h-2EFFFFh

2F0000h-2F7FFFh

2F8000h-2FFFFFh

Bank B

28

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

Bank

Sector

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

Sector Size

32 Kwords

4 Kwords

Address Range

300000h-307FFFh

308000h-30FFFFh

310000h-317FFFh

318000h-31FFFFh

320000h-327FFFh

328000h-32FFFFh

330000h-337FFFh

338000h-33FFFFh

340000h-347FFFh

348000h-34FFFFh

350000h-357FFFh

358000h-35FFFFh

360000h-367FFFh

368000h-36FFFFh

370000h-377FFFh

378000h-37FFFFh

380000h-387FFFh

388000h-38FFFFh

390000h-397FFFh

398000h-39FFFFh

3A0000h-3A7FFFh

3A8000h-3AFFFFh

3B0000h-3B7FFFh

3B8000h-3BFFFFh

3C0000h-3C7FFFh

3C8000h-3CFFFFh

3D0000h-3D7FFFh

3D8000h-3DFFFFh

3E0000h-3E7FFFh

3E8000h-3EFFFFh

3F0000h-3F7FFFh

3F8000h-3F8FFFh

3F9000h-3F9FFFh

3FA000h-3FAFFFh

3FB000h-3FBFFFh

3FC000h-3FCFFFh

3FD000h-3FDFFFh

3FE000h-3FEFFFh

3FF000h-3FFFFFh

Bank B

Bank A

4 Kwords

October 23, 2003

Am42BDS6408H

29

A D V A N C E I N F O R M A T I O N

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 16, “Command Definitions,” on

page 40 defines the valid register command

sequences. Writing incorrect address and data values

or writing them in the improper sequence may place the

device in an unknown state. The system must write the

reset command to return the device to reading array

data. Refer to the AC Characteristics section for timing

diagrams.

be C0h, address bits A11–A0 should be 555h, and

address bits A19–A12 set the code to be latched. The

device will power up or after a hardware reset with the

default setting, which is in asynchronous mode. The

register must be set before the device can enter syn-

chronous mode. The configuration register can not be

changed during device operations (program, erase, or

sector lock).

Reading Array Data

Power-up/

Hardware Reset

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data in asynchronous mode. Each bank is

ready to read array data after completing an Embedded

Program or Embedded Erase algorithm.

Asynchronous Read

Mode Only

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read data

from any non-erase-suspended sector within the same

bank. After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data from any non-erase-suspended sector

within the same bank. See the “Erase Suspend/Erase

Resume Commands” section on page 36 for more

information.

Set Burst Mode

Configuration Register

Command for

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(A19 = 0)

Asynchronous Mode

(A19 = 1)

Synchronous Read

The system must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase operation,

or if the bank is in the autoselect mode. See the “Reset

Command” section on page 33 for more information.

Mode Only

Figure 3. Synchronous/Asynchronous State

Diagram

See also “Requirements for Asynchronous Read Oper-

ation (Non-Burst)” section on page 12 and “Require-

ments for Synchronous (Burst) Read Operation”

section on page 12 for more information. The Asyn-

chronous Read and Synchronous/Burst Read tables

provide the read parameters, and Figure 13, “CLK Syn-

chronous Burst Mode Read (rising active CLK),” on

page 54, Figure 15, “Synchronous Burst Mode Read,”

on page 55, and Figure 28, “Asynchronous Mode Read

with Latched Addresses,” on page 63 show the timings.

Read Mode Setting

On power-up or hardware reset, the device is set to be

in asynchronous read mode. This setting allows the

system to enable or disable burst mode during system

operations. Address A19 determines this setting: “1” for

asynchronous mode, “0” for synchronous mode.

Programmable Wait State Configuration

The programmable wait state feature informs the

device of the number of clock cycles that must elapse

after AVD# is driven active before data will be available.

This value is determined by the input frequency of the

device. Address bits A14–A12 determine the setting

(see Table 11, “Programmable Wait State Settings,” on

page 31).

Set Configuration Register Command Se-

quence

The device uses a configuration register to set the

various burst parameters: number of wait states, burst

read mode, active clock edge, RDY configuration, and

synchronous mode active. The configuration register

must be set before the device will enter burst mode.

The wait state command sequence instructs the device

to set a particular number of clock cycles for the initial

access in burst mode. The number of wait states that

should be programmed into the device is directly

related to the clock frequency.

The configuration register is loaded with a three-cycle

command sequence. The first two cycles are standard

unlock sequences. On the third cycle, the data should

30

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

Table 11. Programmable Wait State Settings

Total Initial Access

Table 12. Wait States for Reduced wait-state

Handshaking

A14

A13

A12

Cycles

V

= 1.8 V

IO

0

2

System

Frequency

Range

Device

Speed

Rating

Even Initial

Address

Odd Initial

Address

0

1

3

0

1

0

4

6–22 MHz

22–28 MHz

28–43 MHz

43–54 MHz

6–28 MHz

28–35 MHz

35–53 MHz

53–66 MHz

2

3

4

2

3

4

2

3

4

5

2

3

4

5

0

1

5

D

1

0

6

(54 MHz)

1

0

1

7 (default)

Reserved

1

0

1

E

Notes:

(66 MHz)

1. Upon power-up or hardware reset, the default setting is

seven wait states.

2. RDY will default to being active with data when the Wait

State Setting is set to a total initial access cycle of 2.

V

= 1.5 V

IO

System

Frequency

Range

Device

Speed

Rating

It is recommended that the wait state command

sequence be written, even if the default wait state value

is desired, to ensure the device is set as expected. A

hardware reset will set the wait state to the default set-

ting.

Even Initial

Address

Odd Initial

Address

6–18 MHz

2

3

4

5

2

3

4

5

2

3

4

5

6

2

3

4

5

6

18–22 MHz

22–33 MHz

33–45 MHz

45–54 MHz

6–23 MHz

Reduced Wait-state Handshaking Option

D

If the device is equipped with the reduced wait-state

handshaking option, the host system should set

address bits A14–A12 to 010 for the system/device to

execute at maximum speed.

(54 MHz)

Table 12 describes the typical number of clock cycles

(wait states) for various conditions.

23–28 MHz

28–42 MHz

42–56 MHz

56–66 MHz

E

(66 MHz)

Notes:

1. If the latched address is 3Eh or 3Fh (or an address offset

from either address by a multiple of 64), add two access

cycles to the values listed.

2. In the 8-, 16-, and 32-word burst modes, the address

pointer does not cross 64-word boundaries (3Fh, or

addresses offset from 3Fh by a multiple of 64).

3. Typical initial access cycles may vary depending on

system margin requirements.

Standard Handshaking Option

For optimal burst mode performance on devices with

the standard handshaking option, the host system

must set the appropriate number of wait states in the

flash device depending on the clock frequency.

October 23, 2003

Am42BDS6408H

31

A D V A N C E I N F O R M A T I O N

Table 13 describes the typical number of clock cycles

(wait states) for various conditions with A14-A12 set to

101.

Table 14 shows the address bits and settings for the

four read modes.

Table 14. Read Mode Settings

Address Bits

A16 A15

Table 13. Wait States for Standard Handshaking

Typical No. of Clock

Burst Modes

Conditions at Address

Cycles after AVD# Low

Continuous

0

Initial address

7

8-word linear wrap around

16-word linear wrap around

32-word linear wrap around

0

1

0

1

Initial address is 3E or 3Fh (or

offset from these addresses by

a multiple of 64) and is at

boundary crossing*

7

Note: Upon power-up or hardware reset the default setting is

continuous.

* In the 8-, 16- and 32-word burst read modes, the address

pointer does not cross 64-word boundaries (addresses

which are multiples of 3Fh).

Burst Active Clock Edge Configuration

The autoselect function allows the host system to

determine whether the flash device is enabled for

handshaking. See the “Autoselect Command

Sequence” section on page 33 for more information.

By default, the device will deliver data on the rising

edge of the clock after the initial synchronous access

time. Subsequent outputs will also be on the following

rising edges, barring any delays. The device can be set

so that the falling clock edge is active for all synchro-

nous accesses. Address bit A17 determines this set-

ting; “1” for rising active, “0” for falling active.

Read Mode Configuration

The device supports four different read modes: contin-

uous mode, and 8, 16, and 32 word linear wrap around

modes. A continuous sequence begins at the starting

address and advances the address pointer until the

burst operation is complete. If the highest address in

the device is reached during the continuous burst read

mode, the address pointer wraps around to the lowest

address.

RDY Configuration

By default, the device is set so that the RDY pin will

output V_OHwhenever there is valid data on the outputs.

The device can be set so that RDY goes active one

data cycle before active data. Address bit A18 deter-

mines this setting; “1” for RDY active with data, “0” for

RDY active one clock cycle before valid data. In asyn-

chronous mode, RDY is an open-drain output.

For example, an eight-word linear read with wrap

around begins on the starting address written to the

device and then advances to the next 8 word boundary.

The address pointer then returns to the 1st word after

the previous eight word boundary, wrapping through

the starting location. The sixteen- and thirty-two linear

wrap around modes operate in a fashion similar to the

eight-word mode.

Configuration Register

Table 15 shows the address bits that determine the

configuration register settings for various device func-

tions.

32

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

Table 15. Configuration Register

Settings (Binary)

Address BIt

Function

Set Device

0 = Synchronous Read (Burst Mode) Enabled

A19

Read Mode 1 = Asynchronous Mode (default)

0 = RDY active one clock cycle before data

1 = RDY active with data (default)

A18

A17

RDY

0 = Burst starts and data is output on the falling edge of CLK

1 = Burst starts and data is output on the rising edge of CLK (default)

Clock

Synchronous Mode

00 = Continuous (default)

A16

A15

Read Mode

01 = 8-word linear with wrap around

10 = 16-word linear with wrap around

11 = 32-word linear with wrap around

000 = Data is valid on the 2th active CLK edge after AVD# transition to V

001 = Data is valid on the 3th active CLK edge after AVD# transition to V

010 = Data is valid on the 4th active CLK edge after AVD# transition to V

011 = Data is valid on the 5th active CLK edge after AVD# transition to V

100 = Data is valid on the 6th active CLK edge after AVD# transition to V

IH

A14

A13

A12

Programmable

Wait State

101 = Data is valid on the 7th active CLK edge after AVD# transition to V (default)

IH

110 = Reserved

111 = Reserved

Note:Device will be in the default state upon power-up or hardware reset.

If DQ5 goes high during a program or erase operation,

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

writing the reset command returns the banks to the

read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

Autoselect Command Sequence

The reset command may be written between the

sequence cycles in an erase command sequence

before erasing begins. This resets the bank to which

the system was writing to the read mode. Once erasure

begins, however, the device ignores reset commands

until the operation is complete.

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

Table 16, “Command Definitions,” on page 40 shows

the address and data requirements. The autoselect

command sequence may be written to an address

within a bank that is either in the read or erase-sus-

pend-read mode. The autoselect command may not be

written while the device is actively programming or

erasing in the other bank.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins (prior to the third cycle).

This resets the bank to which the system was writing to

the read mode. If the program command sequence is

written to a bank that is in the Erase Suspend mode,

writing the reset command returns that bank to the

erase-suspend-read mode. Once programming

begins, however, the device ignores reset commands

until the operation is complete.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the

autoselect command. The bank then enters the

autoselect mode. No subsequent data will be made

available if the autoselect data is read in synchronous

mode. The system may read at any address within the

same bank any number of times without initiating

another autoselect command sequence. Read com-

mands to other banks will return data from the array.

The following table describes the address require-

ments for the various autoselect functions, and the

resulting data. BA represents the bank address, and

The reset command may be written between the

sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to the read mode. If a bank entered

the autoselect mode while in the Erase Suspend mode,

writing the reset command returns that bank to the

erase-suspend-read mode.

October 23, 2003

Am42BDS6408H

33

A D V A N C E I N F O R M A T I O N

SA represents the sector address. The device ID is

read in three cycles.

internally generated program pulses and verifies the

programmed cell margin. Table 16, “Command Defini-

tions,” on page 40 shows the address and data require-

ments for the program command sequence.

Description

Address

Read Data

Manufacturer

ID

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and addresses

are no longer latched. The system can determine the

status of the program operation by monitoring DQ7 or

DQ6/DQ2. Refer to the “Write Operation Status”

section on page 43 for information on these status bits.

(BA) + 00h

(BA) + 01h

(BA) + 0Eh

(BA) + 0Fh

0001h

Device ID,

Word 1

227Eh

221Eh

2201h

Device ID,

Word 2

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should be

reinitiated once that bank has returned to the read

mode, to ensure data integrity.

Device ID,

Word 3

Sector

Protection

Verification

0001 (locked),

0000 (unlocked)

(SA) + 02h

DQ15 - DQ8 = 0

DQ7: Factory Lock Bit

1 = Locked, 0 = Not Locked

DQ6: Customer Lock Bit

1 = Locked, 0 = Not Locked

DQ5: Handshake Bit

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed from

“0” back to a “1.” Attempting to do so may cause that

bank to set DQ5 = 1, or cause the DQ7 and DQ6 status

bit to indicate the operation was successful. However,

a succeeding read will show that the data is still “0.”

Only erase operations can convert a “0” to a “1.”

Indicator Bits (BA) + 03h

1 = Reduced Wait-state

Handshake,

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to prima-

rily program to a bank faster than using the standard

program command sequence. The unlock bypass

command sequence is initiated by first writing two

unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. The

device then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass

program command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

with the initial two unlock cycles required in the stan-

dard program command sequence, resulting in faster

total programming time. The host system may also ini-

tiate the chip erase and sector erase sequences in the

unlock bypass mode. The erase command sequences

are four cycles in length instead of six cycles. Table 16,

“Command Definitions,” on page 40 shows the require-

ments for the unlock bypass command sequences.

0 = Standard Handshake

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence

The SecSi Sector region provides a secured data area

containing a random, eight word electronic serial num-

ber (ESN). The system can access the SecSi Sector

region by issuing the three-cycle Enter SecSi Sector

command sequence. The device continues to access

the SecSi Sector region until the system issues the

four-cycle Exit SecSi Sector command sequence. The

Exit SecSi Sector command sequence returns the de-

vice to normal operation. The SecSi Sector is not ac-

cessible when the device is executing an Embedded

Program or embedded Erase algorithm. Table 16,

“Command Definitions,” on page 40 shows the address

and data requirements for both command sequences.

During the unlock bypass mode, only the Read, Unlock

Bypass Program, Unlock Bypass Sector Erase, Unlock

Bypass Chip Erase, and Unlock Bypass Reset com-

mands are valid. To exit the unlock bypass mode, the

system must issue the two-cycle unlock bypass reset

command sequence. The first cycle must contain the

bank address and the data 90h. The second cycle

need only contain the data 00h. The bank then returns

to the read mode.

Program Command Sequence

Programming is a four-bus-cycle operation. The

program command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program

algorithm. The system is not required to provide further

controls or timings. The device automatically provides

34

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

The device offers accelerated program operations

trols or timings during these operations. Table 16,

“Command Definitions,” on page 40 shows the address

and data requirements for the chip erase command

sequence.

through the ACC input. When the system asserts V_HH

on this input, the device automatically enters the

Unlock Bypass mode. The system may then write the

two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

ACC input to accelerate the operation.

When the Embedded Erase algorithm is complete, that

bank returns to the read mode and addresses are no

longer latched. The system can determine the status of

the erase operation by using DQ7 or DQ6/DQ2. Refer

to the “Write Operation Status” section on page 43 for

information on these status bits.

Figure 4, “Program Operation,” on page 35 illustrates

the algorithm for the program operation. Refer to the

Erase/Program Operations table in the AC Character-

istics section for parameters, and Figure 31, “Asyn-

chronous Program Operation Timings: AVD# Latched

Addresses,” on page 66 and Figure 33, “Synchronous

Program Operation Timings: WE# Latched Addresses,”

on page 68 for timing diagrams.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset

immediately terminates the erase operation. If that

occurs, the chip erase command sequence should be

reinitiated once that bank has returned to reading array

data, to ensure data integrity.

START

The host system may also initiate the chip erase

command sequence while the device is in the unlock

bypass mode. The command sequence is two cycles

cycles in length instead of six cycles. See Table 16,

“Command Definitions,” on page 40 for details on the

unlock bypass command sequences.

Write Program

Command Sequence

Figure 5, “Erase Operation,” on page 37 illustrates the

algorithm for the erase operation. Refer to the

Erase/Program Operations table in the AC Character-

istics section for parameters and timing diagrams.

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

No

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 16, “Command Defi-

nitions,” on page 40 shows the address and data

requirements for the sector erase command sequence.

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or

timings during these operations.

Note: See Table 16 for program command sequence.

Figure 4. Program Operation

After the command sequence is written, a sector erase

time-out of no less than 50 µs occurs. During the

time-out period, additional sector addresses and sector

erase commands may be written. Loading the sector

erase buffer may be done in any sequence, and the

number of sectors may be from one sector to all sec-

tors. The time between these additional cycles must be

less than 50 µs, otherwise erasure may begin. Any

sector erase address and command following the

exceeded time-out may or may not be accepted. It is

recommended that processor interrupts be disabled

during this time to ensure all commands are accepted.

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

October 23, 2003

Am42BDS6408H

35

A D V A N C E I N F O R M A T I O N

The interrupts can be re-enabled after the last Sector

this command. This command is valid only during the

sector erase operation, including the minimum 50 µs

time-out period during the sector erase command

sequence. The Erase Suspend command is ignored if

written during the chip erase operation or Embedded

Program algorithm.

Erase command is written. Any command other than

Sector Erase or Erase Suspend during the time-out

period resets that bank to the read mode. The system

must rewrite the command sequence and any addi-

tional addresses and commands.

The system can monitor DQ3 to determine if the sector

erase timer has timed out (See “DQ3: Sector Erase

Timer” section on page 46.) The time-out begins from

the rising edge of the final WE# pulse in the command

sequence.

When the Erase Suspend command is written during

the sector erase operation, the device requires a

maximum of 20 µs to suspend the erase operation.

However, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded Erase

operation is in progress, the system can read data from

the non-erasing bank. The system can determine the

status of the erase operation by reading DQ7 or

DQ6/DQ2 in the erasing bank. Refer to the “Write

Operation Status” section on page 43 for information

on these status bits.

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The

system can read data from or program data to any

sector not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at any

address within erase-suspended sectors produces

status information on DQ7–DQ0. The system can use

DQ7, or DQ6 and DQ2 together, to determine if a

sector is actively erasing or is erase-suspended. Refer

to the Figure , “Write Operation Status,” on page 43 for

information on these status bits.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. However, note that a hardware reset

immediately terminates the erase operation. If that

occurs, the sector erase command sequence should

be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard program operation. Refer to the

“Write Operation Status” section on page 43 for more

information.

The host system may also initiate the sector erase

command sequence while the device is in the unlock

bypass mode. The command sequence is four cycles

cycles in length instead of six cycles.

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. Refer to the

“Am42BDS6408H Boot Sector/Sector Block

Addresses for Protection/Unprotection” section on

page 16 and “Autoselect Command Sequence” section

on page 33 for details.

Figure 5, “Erase Operation,” on page 37 illustrates the

algorithm for the erase operation. Refer to the

Erase/Program Operations table in the Figure , “AC

Characteristics,” on page 65 for parameters and timing

diagrams.

Erase Suspend/Erase Resume Commands

To resume the sector erase operation, the system must

write the Erase Resume command. The bank address

of the erase-suspended bank is required when writing

this command. Further writes of the Resume command

The Erase Suspend command, B0h, allows the system

to interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. The bank address is required when writing

36

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

are ignored. Another Erase Suspend command can be from the factory. All 64-bit password combinations are

written after the chip has resumed erasing.

valid as a password.

Password Verify Command

START

The Password Verify Command is used to verify the

Password. The Password is verifiable only when the

Password Mode Locking Bit is not programmed. If the

Password Mode Locking Bit is programmed and the

user attempts to verify the Password, the device will al-

ways drive all F’s onto the DQ data bus.

Write Erase

Command Sequence

Also, the device will not operate in Simultaneous Oper-

ation when the Password Verify command is executed.

Only the password is returned regardless of the bank

address. The lower two address bits (A1–A0) are valid

during the Password Verify. Writing the Read/Reset

command returns the device back to normal operation.

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Password Protection Mode Locking Bit

Program Command

Yes

The Password Protection Mode Locking Bit Program

Command programs the Password Protection Mode

Locking Bit, which prevents further verifies or updates

to the Password. When the Password Protection Mode

Locking Bit is undergoing programming, Simultaneous

Operation is disabled. Once programmed, the Pass-

word Protection Mode Locking Bit cannot be erased! If

the Password Protection Mode Locking Bit is verified

as program without margin, the Password Protection

Mode Locking Bit Program command can be executed

to improve the program margin. Once the Password

Protection Mode Locking Bit is programmed, the Per-

sistent Sector Protection Locking Bit program circuitry

is disabled, thereby forcing the device to remain in the

Password Protection mode. Exiting the Mode Locking

Bit Program command is accomplished by writing the

Read/Reset command.

Erasure Completed

Notes:

1. See Table 16 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 5. Erase Operation

Password Program Command

The Password Program Command permits program-

ming the password that is used as part of the hard-

ware protection scheme. The actual password is

64-bits long. 4 Password Program commands are re-

quired to program the password. The user must enter

the unlock cycle, password program command (38h)

and the program address/data for each portion of the

password when programming. There are no provisions

for entering the 2-cycle unlock cycle, the password

program command, and all the password data. There

is no special addressing order required for program-

ming the password. Also, when the password is under-

going programming, Simultaneous Operation is

disabled. Read operations to any memory location will

return the programming status. Once programming is

complete, the user must issue a Read/Reset com-

mand to return the device to normal operation. Once

the Password is written and verified, the Password

Mode Locking Bit must be set in order to prevent verifi-

cation. The Password Program Command is only ca-

pable of programming “0”s. Programming a “1” after a

cell is programmed as a “0” results in a time-out by the

Embedded Program Algorithm™ with the cell remain-

ing as a “0”. The password is all F’s when shipped

Persistent Sector Protection Mode

Locking Bit Program Command

The Persistent Sector Protection Mode Locking Bit

Program Command programs the Persistent Sector

Protection Mode Locking Bit, which prevents the Pass-

word Mode Locking Bit from ever being programmed.

If the Persistent Sector Protection Mode Locking Bit is

verified as programmed without margin, the Persistent

Sector Protection Mode Locking Bit Program Com-

mand should be reissued to improve program margin.

By disabling the program circuitry of the Password

Mode Locking Bit, the device is forced to remain in the

Persistent Sector Protection mode of operation, once

this bit is set. Exiting the Persistent Protection Mode

Locking Bit Program command is accomplished by

writing the Read/Reset command. When the Persis-

tent Sector Protection Mode Locking Bit is undergoing

programming, Simultaneous Operation is disabled.

October 23, 2003

Am42BDS6408H

37

A D V A N C E I N F O R M A T I O N

Password Unlock command 4 times. A1 and A0 are

SecSi Sector Protection Bit Program

Command

used for matching. Writing the Password Unlock com-

mand is not address order specific. The lower address

A1–A0= 00, the next Password Unlock command is to

A1–A0= 01, then to A1–A0= 10, and finally to A1–A0=

11.

The SecSi Sector Protection Bit Program Command

programs the SecSi Sector Protection Bit, which pre-

vents the SecSi sector memory from being cleared. If

the SecSi Sector Protection Bit is verified as pro-

grammed without margin, the SecSi Sector Protection

Bit Program Command should be reissued to improve

program margin. Exiting the V_CC-level SecSi Sector

Protection Bit Program Command is accomplished by

writing the Read/Reset command.

Once the Password Unlock command is entered for all

four words, the RDY pin goes LOW indicating that the

device is busy. Approximately 1uSec is required for

each portion of the unlock. Once the first portion of the

password unlock completes (RDY is not driven and

DQ6 does not toggle when read), the Password Un-

lock command is issued again, only this time with the

next part of the password. Four Password Unlock com-

mands are required to successfully clear the PPB

Lock Bit. As with the first Password Unlock command,

the RDY signal goes LOW and reading the device re-

sults in the DQ6 pin toggling on successive read oper-

ations until complete. It is the responsibility of the

microprocessor to keep track of the number of Pass-

word Unlock commands, the order, and when to read

the PPB Lock bit to confirm successful password un-

lock. In order to relock the device into the Password

Mode, the PPB Lock Bit Set command can be re-is-

sued.

PPB Lock Bit Set Command

The PPB Lock Bit Set command is used to set the

PPB Lock bit if it is cleared either at reset or if the

Password Unlock command was successfully exe-

cuted. There is no PPB Lock Bit Clear command.

Once the PPB Lock Bit is set, it cannot be cleared un-

less the device is taken through a power-on clear or

the Password Unlock command is executed. Upon set-

ting the PPB Lock Bit, the PPBs are latched into the

DYBs. If the Password Mode Locking Bit is set, the

PPB Lock Bit status is reflected as set, even after a

power-on reset cycle. Exiting the PPB Lock Bit Set

command is accomplished by writing the Read/Reset

command, only while in the Persistent Sector Protec-

tion Mode.

PPB Program Command

The PPB Program command is used to program, or

set, a given PPB. Each PPB is individually pro-

grammed (but is bulk erased with the other PPBs).

The specific sector address (A21–A12) are written at

the same time as the program command 60h with A6

= 0. If the PPB Lock Bit is set and the corresponding

PPB is set for the sector, the PPB Program command

will not execute and the command will time-out without

programming the PPB.

DYB Write Command

The DYB Write command is used to set or clear a DYB

for a given sector. The high order address bits

(A21–A12) are issued at the same time as the code

01h or 00h on DQ7-DQ0. All other DQ data bus pins

are ignored during the data write cycle. The DYBs are

modifiable at any time, regardless of the state of the

PPB or PPB Lock Bit. The DYBs are cleared at

power-up or hardware reset. Exiting the DYB Write

command is accomplished by writing the Read/Reset

command.

After programming a PPB, two additional cycles are

needed to determine whether the PPB has been pro-

grammed with margin. If the PPB has been pro-

grammed without margin, the program command

should be reissued to improve the program margin.

Password Unlock Command

The Password Unlock command is used to clear the

PPB Lock Bit so that the PPBs can be unlocked for

modification, thereby allowing the PPBs to become ac-

cessible for modification. The exact password must be

entered in order for the unlocking function to occur.

This command cannot be issued any faster than 2 µs

at a time to prevent a hacker from running through the

all 64-bit combinations in an attempt to correctly match

a password. If the command is issued before the 2 µs

execution window for each portion of the unlock, the

command will be ignored.

The PPB Program command does not follow the Em-

bedded Program algorithm.

All PPB Erase Command

The All PPB Erase command is used to erase all

PPBs in bulk. There is no means for individually eras-

ing a specific PPB. Unlike the PPB program, no spe-

cific sector address is required. However, when the

PPB erase command is written (60h) and A6 = 1, all

Sector PPBs are erased in parallel. If the PPB Lock Bit

is set the ALL PPB Erase command will not execute

and the command will time-out without erasing the

PPBs. After erasing the PPBs, two additional cycles

are needed to determine whether the PPB has been

erased with margin. If the PPBs has been erased with-

The Password Unlock function is accomplished by

writing Password Unlock command and data to the de-

vice to perform the clearing of the PPB Lock Bit. The

password is 64 bits long, so the user must write the

38

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

out margin, the erase command should be reissued to bit, removing power or resetting the device will clear

improve the program margin.

the DYBs.

It is the responsibility of the user to preprogram all

PPBs prior to issuing the All PPB Erase command. If

the user attempts to erase a cleared PPB, over-era-

sure may occur making it difficult to program the PPB

at a later time. Also note that the total number of PPB

program/erase cycles is limited to 100 cycles. Cycling

the PPBs beyond 100 cycles is not guaranteed.

PPB Status Command

The programming of the PPB for a given sector can be

verified by writing a PPB status verify command to the

device.

PPB Lock Bit Status Command

The programming of the PPB Lock Bit for a given sec-

tor can be verified by writing a PPB Lock Bit status ver-

ify command to the device.

DYB Write Command

The DYB Write command is used for setting the DYB,

which is a volatile bit that is cleared at hardware reset.

There is one DYB per sector. If the PPB is set, the sec-

tor is protected regardless of the value of the DYB. If

the PPB is cleared, setting the DYB to a 1 protects the

sector from programs or erases. Since this is a volatile

DYB Status Command

The programming of the DYB for a given sector can be

verified by writing a DYB Status command to the de-

vice.

October 23, 2003

Am42BDS6408H

39

A D V A N C E I N F O R M A T I O N

Command Definitions

Table 16. Command Definitions

Bus Cycles (Notes 1–6)

First

Second

Third

Fourth

Fifth

Sixth

Seventh

Command Sequence

(Note 1)

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Asynchronous Read (Note 7)

Reset (Note 8)

1

RA

RD

F0

XXX

(BA)

555

(BA)

X00

Manufacturer ID

Device ID

4

6

4

555

AA 2AA

55

90

0001

227E

(BA)

555

(BA)

X01

(BA)

X0E

(BA)

X0F

221E

2201

(SA)

555

(SA)

X02

Sector Lock Verify (Note

10)

(Note

10)

(BA)

555

(BA)

X03

(Note

11)

Indicator Bits (Note 11)

Program

4

6

1

555

BA

AA 2AA

B0

55

555

A0

80

PA

555

Data

AA

Chip Erase

2AA

55

555

SA

10

30

Sector Erase

AA

Erase Suspend (Note 14)

Erase Resume (Note 15)

BA

30

(CR)

555

Set Configuration Register (Note 16)

3

555

AA 2AA

55

C0

20

CFI Query (Note 17)

Unlock Bypass Entry

1

3

55

98

555

AA

A0

2AA

PA

55

555

Unlock Bypass Program

(Notes 12, 13)

2

XX

PD

Unlock Bypass Sector

Erase (Notes 12, 13)

80

SA

30

10

Unlock

Bypass

Unlock Bypass Erase

Mode

XXX

(Notes 12, 13)

Unlock Bypass CFI

(Notes 12, 13)

1

2

XX

98

90

Unlock Bypass Reset

XXX

00

Sector Protection Command Definitions

SecSi Sector Entry

3

4

555

AA

2AA

55

555

88

90

SecSi Sector Exit

SecSi

XX

00

68

SecSi Protection Bit

Program (Notes 18, 19,

21)

Sector

(SA)

OW

(SA)

OW

RD

(0)

6

555

AA

2AA

55

555

60

48

OW

XX0

XX1

XX2

XX3

XX0

XX1

XX2

XX3

PD0

PD1

PD2

PD3

PD0

PD1

PD2

PD3

Password Program

(Notes 18, 23)

4

555

AA

2AA

55

555

38

Password

Protection

Password Verify

4

7

555

AA

2AA

55

555

C8

28

Password Unlock (Note

23)

XX0

PD0

XX1 PD1 XX2 PD2 XX3 PD3

40

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

Bus Cycles (Notes 1–6)

First

Second

Third

Fourth

Fifth

Sixth

Seventh

Command Sequence

(Note 1)

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

(SA)

+ WP

RD

(0)

PPB Program (Notes 18,

19, 21)

(SA)

+ WP

6

555

AA

2AA

55

555

60

68

60

48

40

XX

PPB

Command

s

RD

(0)

All PPB Erase (Notes

18, 19, 22, 24)

WP

(BA)

555

(SA)

X02

RD

(0)

PPB Status (Note 25)

PPB Lock Bit Set

4

555

AA

2AA

55

90

3

4

555

AA

2AA

55

555

78

58

PPB Lock

Bit

(BA)

555

RD

(1)

PPB Lock Bit Status

(Note 19)

SA

DYB Write

DYB Erase

4

555

AA

2AA

55

555

48

SA

X1

X0

DYB

(BA)

555

RD

(0)

DYB Status

4

6

4

555

AA

2AA

55

58

60

SA

PL

SL

PL

SL

RD

(0)

Password Protection Mode Locking

Bit Program (Notes 18, 19, 21)

555

68

PL

SL

48

PL

SL

RD

(0)

Persistent Protection Mode Locking

Bit Program (Notes 18, 19, 21)

RD

(0)

Password Protection Mode Locking

Bit Read (Notes 18, 19, 21)

RD

(0)

Persistent Protection Mode Locking

Bit Read (Notes 18, 19, 21)

Legend:

X = Don’t care

OW = Address (A7–A0) is (00011010).

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses

latch on the rising edge of the AVD# pulse or active edge of CLK which

ever comes first.

PD3–PD0 = Password Data. PD3–PD0 present four 16 bit

combinations that represent the 64-bit Password

PWA = Password Address. Address bits A1 and A0 are used to select

each 16-bit portion of the 64-bit entity.

PWD = Password Data.

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A21–A12 uniquely select any sector.

BA = Address of the bank (A21, A20, A19) that is being switched to

autoselect mode, is in bypass mode, or is being erased.

SLA = Address of the sector to be locked. Set sector address (SA) and

either A6 = 1 for unlocked or A6 = 0 for locked.

PL = Address (A7-A0) is (00001010)

RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1, if

unprotected, DQ0 = 0.

RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1, if

unprotected, DQ1 = 0.

SL = Address (A7-A0) is (00010010)

WD= Write Data. See “Configuration Register” definition for specific

write data

CR = Configuration Register address bits A19–A12.

WP = Address (A7-A0) is (00000010)

Notes:

1. See Table 1 for description of bus operations.

Suspend) when a bank is in the autoselect mode, or if DQ5 goes

high (while the bank is providing status information) or performing

sector lock/unlock.

2. All values are in hexadecimal.

3. Except for the following, all bus cycles are write cycle: read cycle,

fourth through sixth cycles of the Autoselect commands, fourth

cycle of the configuration register verify and password verify

commands, and any cycle reading at RD(0) and RD(1).

9. The fourth cycle of the autoselect command sequence is a read

cycle. The system must provide the bank address. See the

Autoselect Command Sequence section for more information.

10. The data is 0000h for an unlocked sector and 0001h for a locked

sector

4. Data bits DQ15–DQ8 are don’t care in command sequences,

except for RD, PD, WD, PWD, and PD3-PD0.

11. DQ15 - DQ8 = 0, DQ7: Factory Lock Bit (1 = Locked, 0 = Not

Locked), DQ6: Customer Lock Bit (1 = Locked, 0 = Not Locked),

DQ5: Handshake Bit (1 = Reduced wait-state Handshake, 0 =

Standard Handshake), DQ4 - DQ0 = 0

5. Unless otherwise noted, address bits A21–A12 are don’t cares.

6. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state.

The system must write the reset command to return the device to

reading array data.

12. The Unlock Bypass command sequence is required prior to this

command sequence.

7. No unlock or command cycles required when bank is reading

array data.

13. The Unlock Bypass Reset command is required to return to

reading array data when the bank is in the unlock bypass mode.

8. The Reset command is required to return to reading array data

(or to the erase-suspend-read mode if previously in Erase

October 23, 2003

Am42BDS6408H

41

A D V A N C E I N F O R M A T I O N

14. The system may read and program in non-erasing sectors, or

21. The fourth cycle programs the addressed locking bit. The fifth and

sixth cycles are used to validate whether the bit has been fully

programmed. If DQ0 (in the sixth cycle) reads 0, the program

command must be issued and verified again.

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation, and requires the bank address.

15. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

22. The fourth cycle erases all PPBs. The fifth and sixth cycles are

used to validate whether the bits have been fully erased. If DQ0

(in the sixth cycle) reads 1, the erase command must be issued

and verified again.

16. See “Set Configuration Register Command Sequence” for details.

17. Command is valid when device is ready to read array data or

when device is in autoselect mode.

23. The entire four bus-cycle sequence must be entered for each

portion of the password.

18. The Reset command returns the device to reading the array.

24. Before issuing the erase command, all PPBs should be

programmed in order to prevent over-erasure of PPBs.

19. Regardless of CLK and AVD# interaction or Control Register bit

15 setting, command mode verifies are always asynchronous

read operations.

25. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not

set.

20. ACC must be at V during the entire operation of this command

HH

42

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a program or erase operation: DQ2, DQ3,

DQ5, DQ6, and DQ7. Table 18, “Write Operation

Status,” on page 47 and the following subsections

describe the function of these bits. DQ7 and DQ6 each

offers a method for determining whether a program or

erase operation is complete or in progress.

invalid. Valid data on DQ7-DQ0 will appear on succes-

sive read cycles.

Table 18, “Write Operation Status,” on page 47 shows

the outputs for Data# Polling on DQ7. Figure 6, “Data#

Polling Algorithm,” on page 43 shows the Data# Polling

algorithm. Figure 37, “Data# Polling Timings

(During Embedded Algorithm),” on page 72 in the AC

Characteristics section shows the Data# Polling timing

diagram.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Program or Erase algo-

rithm is in progress or completed, or whether a bank is

in Erase Suspend. Data# Polling is valid after the rising

edge of the final WE# pulse in the command sequence.

START

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then that bank returns to the read

mode.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 100 µs, then

the bank returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the

selected sectors that are protected. However, if the

system reads DQ7 at an address within a protected

sector, the status may not be valid.

Yes

DQ7 = Data?

No

PASS

FAIL

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ6–DQ0 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ6-DQ0 may be still

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 6. Data# Polling Algorithm

October 23, 2003

Am42BDS6408H

43

A D V A N C E I N F O R M A T I O N

cause DQ6 to toggle. When the operation is complete,

RDY: Ready

DQ6 stops toggling.

The RDY is a dedicated output that, when the device is

configured in the Synchronous mode, indicates (when

at logic low) the system should wait 1 clock cycle before

expecting the next word of data. The RDY pin is only

controlled by CE#. Using the RDY Configuration

Command Sequence, RDY can be set so that a logic

low indicates the system should wait 2 clock cycles

before expecting valid data.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 toggles

for approximately 100 µs, then returns to reading array

data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are pro-

tected.

The following conditions cause the RDY output to be

low: during the initial access (in burst mode), and after

the boundary that occurs every 64 words beginning

with the 64th address, 3Fh.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase

Suspend mode, DQ6 stops toggling. However, the

system must also use DQ2 to determine which sectors

are erasing or erase-suspended. Alternatively, the

system can use DQ7 (see the subsection on DQ7:

Data# Polling).

When the device is configured in Asynchronous Mode,

the RDY is an open-drain output pin which indicates

whether an Embedded Algorithm is in progress or com-

pleted. The RDY status is valid after the rising edge of

the final WE# pulse in the command sequence.

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is in high imped-

ance (Ready), the device is in the read mode, the

standby mode, or in the erase-suspend-read mode.

Table 18, “Write Operation Status,” on page 47 shows

the outputs for RDY.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 ms after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded

Program algorithm is complete.

DQ6: Toggle Bit I

See the following for additional information: Figure 7,

“Toggle Bit Algorithm,” on page 45, “DQ6: Toggle Bit I”

on page 44, Figure 38, “Toggle Bit Timings

(During Embedded Algorithm),” on page 72 (toggle bit

timing diagram), and Table 17, “DQ6 and DQ2 Indica-

tions,” on page 46.

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address in the

same bank, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

Toggle Bit I on DQ6 requires either OE# or CE# to be

de-asserted and reasserted to show the change in

state.

During an Embedded Program or Erase algorithm

operation, successive read cycles to any address

44

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. But DQ2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. DQ6, by com-

parison, indicates whether the device is actively

erasing, or is in Erase Suspend, but cannot distinguish

which sectors are selected for erasure. Thus, both

status bits are required for sector and mode informa-

tion. Refer to Table 17, “DQ6 and DQ2 Indications,” on

page 46 to compare outputs for DQ2 and DQ6.

START

Read Byte

(DQ7-DQ0)

Address = VA

Read Byte

(DQ7-DQ0)

Address = VA

See the following for additional information: Figure 7,

“Toggle Bit Algorithm,” on page 45, “DQ6: Toggle Bit I”

on page 44, Figure 38, “Toggle Bit Timings

(During Embedded Algorithm),” on page 72, and

Table 17, “DQ6 and DQ2 Indications,” on page 46.

No

DQ6 = Toggle?

Yes

No

DQ5 = 1?

Yes

Read Byte Twice

(DQ7-DQ0)

Adrdess = VA

No

DQ6 = Toggle?

Yes

FAIL

PASS

Note:The system should recheck the toggle bit even if DQ5 =

“1” because the toggle bit may stop toggling as DQ5 changes

to “1.” See the subsections on DQ6 and DQ2 for more

information.

Figure 7. Toggle Bit Algorithm

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

October 23, 2003

Am42BDS6408H

45

A D V A N C E I N F O R M A T I O N

Table 17. DQ6 and DQ2 Indications

If device is

and the system reads

then DQ6

and DQ2

programming,

at any address,

toggles,

does not toggle.

at an address within a sector

selected for erasure,

toggles,

also toggles.

does not toggle.

toggles.

actively erasing,

at an address within sectors not

selected for erasure,

at an address within a sector

selected for erasure,

does not toggle,

returns array data,

toggles,

erase suspended,

at an address within sectors not

selected for erasure,

returns array data. The system can read

from any sector not selected for erasure.

programming in

erase suspend

at any address,

is not applicable.

Reading Toggle Bits DQ6/DQ2

DQ5: Exceeded Timing Limits

Refer to Figure 7, “Toggle Bit Algorithm,” on page 45 for

the following discussion. Whenever the system initially

begins reading toggle bit status, it must read DQ7–DQ0

at least twice in a row to determine whether a toggle bit

is toggling. Typically, the system would note and store

the value of the toggle bit after the first read. After the

second read, the system would compare the new value

of the toggle bit with the first. If the toggle bit is not tog-

gling, the device has completed the program or erase

operation. The system can read array data on

DQ7–DQ0 on the following read cycle.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1,” indicating that

the program or erase cycle was not successfully com-

pleted.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can change a

“0” back to a “1.” Under this condition, the device halts

the operation, and when the timing limit has been

exceeded, DQ5 produces a “1.”

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

device did not completed the operation successfully,

and the system must write the reset command to return

to reading array data.

Under both these conditions, the system must write the

reset command to return to the read mode (or to the

erase-suspend-read mode if a bank was previously in

the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional sectors

are selected for erasure, the entire time-out also

applies after each additional sector erase command.

When the time-out period is complete, DQ3 switches

from a “0” to a “1.” If the time between additional sector

erase commands from the system can be assumed to

be less than 50 µs, the system need not monitor DQ3.

See also “Sector Erase Command Sequence” on

page 35.

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to

determine the status of the operation (Figure 7, “Toggle

Bit Algorithm,” on page 45).

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all

further commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

46

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

device will accept additional sector erase commands.

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

To ensure the command has been accepted, the

system software should check the status of DQ3 prior

to and following each subsequent sector erase com-

Table 18 shows the status of DQ3 relative to the other

status bits.

Table 18. Write Operation Status

DQ7

(Note 2)

DQ5

(Note 1)

DQ2

(Note 2)

RDY (Note

5)

Status

DQ6

DQ3

N/A

1

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

High

Impedance

1

No toggle

0

N/A

Toggle

Suspended Sector

Erase-Suspend-

Read (Note 4)

Erase

Suspend

Mode

Non-Erase

High

Impedance

Data

0

Data

N/A

Data

N/A

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

0

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

4. The system may read either asynchronously or synchronously (burst) while in erase suspend.

5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This

is available in the Asynchronous mode only.

October 23, 2003

Am42BDS6408H

47

A D V A N C E I N F O R M A T I O N

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

+0.8 V

Voltage with Respect to Ground:

All Inputs and I/Os except

as noted below (Note 1). . . . . . . –0.5 V to V_IO+ 0.5 V

–0.5 V

–2.0 V

V_CC(Note 1). . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

V_IO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

A9, RESET#, ACC (Note 1) . . . . .–0.5 V to +12.5 V

Output Short Circuit Current (Note 3) . . . . . . 100 mA

20 ns

Notes:

Figure 8. Maximum Negative

Overshoot Waveform

1. Minimum DC voltage on input or I/Os is –0.5 V. During

voltage transitions, inputs or I/Os may undershoot V to

SS

–2.0 V for periods of up to 20 ns. See Figure 8. Maximum

DC voltage on input or I/Os is V + 0.5 V. During voltage

CC

transitions outputs may overshoot to V + 2.0 V for

periods up to 20 ns. See Figure 9.

CC

20 ns

V

2. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

CC

+2.0 V

V

CC

+0.5 V

3. Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; functional operation of the de-

vice at these or any other conditions above those indicated

in the operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating condi-

tions for extended periods may affect device reliability.

1.0 V

20 ns

Figure 9. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Supply Voltages

V

_CCSupply Voltages . . . . . . . . . . .+1.65 V to +1.95 V

. . . . . . . . . . . . . . . . . . . . . . . . . . V_CC>= V_IO- 100mV

_IOSupply Voltages: . . . . . . . . . . +1.65 V to +1.95 V

V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

48

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

DC CHARACTERISTICS

CMOS COMPATIBLE

Parameter Description

Test Conditions Note: 1 & 2

= V to V , V = V max

Min

Typ

Max

1

Unit

µA

I

Input Load Current

V

IN

LI

SS

CC CC

CC

I

Output Leakage Current

V

= V to V , V = V max

1

µA

LO

OUT

SS

CC CC

CC

CE# = V , OE# = V

,

IL

IH

WE# = V , burst length 54 MHz

= 8

9

8

17

mA

IH

CE# = V , OE# = V

,

IL

IH

WE# = V , burst length 54 MHz

15.5

IH

= 16

I

V

Active burst Read Current

CCB

CC

CE# = V , OE# = V

,

IL

IH

WE# = V , burst length 54 MHz

= Continuous

7

14

mA

µA

IH

CE# = V , OE# = V , WE# = V ,

IL

IH

50

200

burst length = 8

I

V

Non-active Output

OE# = V

IH

0.2

TBD

12

3.5

15

1

10

TBD

16

5

µA

mA

µA

IO1

IO

10 MHz

5 MHz

1 MHz

Active Asynchronous Read

CE# = V , OE# = V ,

IL IH

CC

I

CC1

Current (Note 3)

WE# = V

IH

I

V

Active Write Current (Note 4)

Standby Current (Note 5)

Reset Current

CE# = V , OE# = V , ACC = V

40

CC2

CC3

CC4

CC

IL

IH

CE# = RESET# = V

0.2 V

CC

RESET# = V CLK = V

1

µA

IL,

IL

Active Current

I

CE# = V , OE# = V

25

60

mA

CC5

CC6

IL

IH

(Read While Write)

I

V

Sleep Current

CE# = V , OE# = V

1

7

5

40

15

µA

mA

V

CC

IL

IH

V

ACC

Accelerated Program Current

(Note 6)

CE# = V , OE# = V

IL IH,

I

ACC

V

= 12.0 0.5 V

ACC

V

10

CC

V

= 1.8 V

= 1.5 V

= 1.8 V

= 1.5 V

–0.4

TBD

0.4

TBD

IO

V

Input Low Voltage

Input High Voltage

IL

V

– 0.4

V

+ 0.4

IO

V

IH

TBD

0.1

V

IO

V

Output Low Voltage

Output High Voltage

I

= 100 µA, V = V = V

IO CC CC min

OL

OH

V

= –100 µA, V = V = V

– 0.1

IO

OH

IO

CC

CC min

Voltage for Autoselect and

Temporary Sector Unprotect

V

= 1.8

CC

11.5

12.5

V

ID

V

Voltage for Accelerated Program

11.5

1.0

12.5

1.4

V

HH

V

Low V Lock-out Voltage

CC

LKO

Note:

1. Maximum I specifications are tested with V = V max.

CC

2. V = V

IO

CC

3. The I current listed is typically less than 2 mA/MHz, with OE# at V .

CC

IH

4. I active while Embedded Erase or Embedded Program is in progress.

CC

5. Device enters automatic sleep mode when addresses are stable for t

+ 60 ns. Typical sleep mode current is equal to I

.

ACC

CC3

6. Total current during accelerated programming is the sum of V

and V currents.

CC

ACC

October 23, 2003

Am42BDS6408H

49

A D V A N C E I N F O R M A T I O N

SRAM DC AND OPERATING CHARACTERISTICS

Parameter

Symbol

Parameter Description

Input Leakage Current

Test Conditions

= V to V

Min

–1.0

Typ

Max

1.0

Unit

µA

I

V

IN

LI

SS

CC

CE1#s = V , CE2s = V or OE# =

IH

IL

I

Output Leakage Current

1.0

µA

LO

V

or WE# = V , V = V to V

IH

IL IO SS CC

I

= 0 mA, CE1#s = V , CE2s =

IL

IO

I

Operating Power Supply Current

5

mA

CC

WE# = V , V = V or V

IH

IN

IH

IL

Cycle time = 1 µs, 100% duty,

= 0 mA, CE1#s ≤ 0.2 V,

I

IO

I

s

Average Operating Current

1

8

CC1

CC2

CE2 ≥ V – 0.2 V, V ≤ 0.2 V or

V

CC

IN

≥ V – 0.2 V

IN

CC

Cycle time = Min., I = 0 mA,

100% duty, CE1#s = V , CE2s =

IO

s

15

mA

IL

V

, V = V = or V

IH

OL

OH

IN IL IH

V

Output Low Voltage

Output High Voltage

I

= 0.1 mA

0.2

V

OL

V

= –0.1 mA

1.4

OH

CE1#s ≥ V – 0.2 V, CE2 ≥ V

CC

– 0.2 V (CE1#s controlled) or CE2

I

Standby Current (CMOS)

2

25

µA

SB1

≤ 0.2 V (CE2s controlled), CIOs =

V

or V , Other input = 0 ~ V

SS

CC CC

–0.2

(Note 2)

V

Input Low Voltage

Input High Voltage

0.4

V

IL

V

+0.

CC

V

1.4

2

IH

(Note 3)

Notes:

1. Typical values measured at V = 2.0 V, T = 25°C. Not 100% tested.

CC

A

2. Undershoot is –1.0 V when pulse width ≤ 20 ns.

3. Overshoot is V + 1.0 V when pulse width ≤ 20 ns.

CC

4. Overshoot and undershoot are sampled, not 100% tested.

50

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

TEST CONDITIONS

Table 19. Test Specifications

Test Condition

All Speed Options Unit

Output Load Capacitance, C

(including jig capacitance)

L

30

pF

Device

Under

Test

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

0.0–V

IO

C

L

Input timing measurement

reference levels

V

/2

V

IO

Output timing measurement

reference levels

V

/2

IO

Figure 10. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

SWITCHING WAVEFORMS

V_IO

All Inputs and Outputs

V_IO/2

Input

Measurement Level

Output

0.0 V

Figure 11. Input Waveforms and Measurement Levels

October 23, 2003

Am42BDS6408H

51

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

V

Power-up

CC

Parameter

Description

Test Setup

Min

Speed

50

Unit

µs

t

V

Setup Time

IO

VCS

CC

t

V

Min

50

µs

VIOS

t

RESET# Low Hold Time

Min

50

µs

RSTH

t_VCS

V_CC

t_VIOS

V_IO

t_RSTH

RESET#

Figure 12. V_CCPower-up Diagram

52

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

Synchronous/Burst Read (V = 1.8 V)

IO

Parameter

E6, E7,

E8, E9

(66 MHz)

D6, D7,

D8, D9

(54 MHz)

JEDEC Standard

Description

Unit

Latency (Even address in Reduced wait-state

Handshake mode)

t

Max

56

71

69

ns

IACC

Latency (Standard Handshake or Odd address in

Reduced wait-state Handshake mode

87.5

ns

t

Burst Access Time Valid Clock to Output Delay

Address Setup Time to CLK (Note 1)

Address Hold Time from CLK (Note 1)

Data Hold Time from Next Clock Cycle

Chip Enable to RDY Valid

Output Enable to Output Valid

Chip Enable to High Z

Max

Min

Max

Min

Max

Min

Max

Min

Max

11

4

13.5

5

ns

ms

BACC

t

ACS

ACH

BDH

t

6

7

t

3

4

t

11

8

13.5

10

5

CR

OE

t

CEZ

OEZ

CES

Output Enable to High Z

8

CE# Setup Time to CLK

4

t

RDY Setup Time to CLK

4

5

RDYS

RACC

t

Ready Access Time from CLK

Address Setup Time to AVD# (Note 1)

Address Hold Time to AVD# (Note 1)

CE# Setup Time to AVD#

AVD# Low to CLK

11

4

13.5

5

t

AAS

AAH

CAS

6

7

0

t

4

10

50

11

8

5

12

55

13.5

10

5

AVC

AVD

ACC

CKA

AVD# Pulse

t

Access Time

CLK to access resume

t

CLK to High Z

CKZ

OES

RCC

t

Output Enable Setup Time

Read cycle for continuous suspend

4

t

1

Notes:

1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.

2. Please contact AMD for availability of V = 1.5 V devices.

IO

October 23, 2003

Am42BDS6408H

53

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

t_CEZ

t_CES

7 cycles for initial access shown.

CE#

1

2

3

4

5

6

7

CLK

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

Addresses

Data

Aa

t_BACC

t_ACH

Hi-Z

t_IACC

t_ACC

Da

Da + 1

Da + n

t_OEZ

OE#

RDY

t_CR

t_RACC

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two

cycles to seven cycles.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode.

Figure 13. CLK Synchronous Burst Mode Read (rising active CLK)

t_CEZ

4 cycles for initial access shown.

t_CES

CE#

1

2

3

4

5

CLK

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

Aa

Addresses

Data

t_BACC

t_ACH

Hi-Z

t_IACC

Da

Da + 1

Da + n

t_ACC

t_OEZ

OE#

RDY

t_RACC

t_OE

t_CR

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active falling edge.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode.

Figure 14. CLK Synchronous Burst Mode Read (Falling Active Clock)

54

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

t_CEZ

7 cycles for initial access shown.

t_CAS

CE#

1

2

3

4

5

6

7

CLK

t_AVC

AVD#

t_AVD

t_AAS

t_BDH

Addresses

Data

Aa

t_BACC

t_AAH

Hi-Z

t_IACC

Da

Da + 1

Da + n

t_ACC

t_OEZ

OE#

RDY

t_RACC

t_CR

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active rising edge.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode.

Figure 15. Synchronous Burst Mode Read

7

cycles for initial access shown.

t_CES

CE#

CLK

1

2

3

4

5

6

7

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

A6

Addresses

Data

t_BACC

t_ACH

t_IACC

t_ACC

D6

D7

D0

D1

D5

D6

OE#

RDY

t_CR

t_RACC

t_OE

Hi-Z

t_RDYS

Note: Figure assumes 7 wait states for initial access and automatic detect synchronous read. D0–D7 in data waveform indicate

the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 7th address in

range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register command sequence

has been written with A18=1; device will output RDY with valid data.

Figure 16. 8-word Linear Burst with Wrap Around

October 23, 2003

Am42BDS6408H

55

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

t_CEZ

6

wait cycles for initial access shown.

t_CES

CE#

1

2

3

4

5

6

CLK

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

Aa

Addresses

t_BACC

t_ACH

Hi-Z

Data

t_IACC

D0

D1

D2

D3

Da + n

t_ACC

t_OEZ

t_RACC

OE#

t_CR

t_OE

Hi-Z

RDY

t_RDYS

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY one cycle before valid data.

Figure 17. Linear Burst with RDY Set One Cycle Before Data

56

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Suspend

Resume

x

x+2

x+3

x+4

x+6

x+7

x+8

x+1

x+5

CLK

AVD#

t

OES

Addresses

t

CKA

t

CKZ

OE#

Data

D(24)

D(20)

D(23)

D(22)

D(20)

D(21)

RDY

t

RACC

t

RACC

Note: Figure is for any even address other than 3Eh (or multiple thereof).

Figure 18. Reduced Wait-state Handshake Burst Suspend/Resume at an even address

Suspend

Resume

x+1

x

x+2

x+3

x+4

x+6

x+7

x+8

x+5

CLK

AVD#

t

OES

Addresses

t

CKA

t

CKZ

OE#

Data

D(27)

D(23)

D(25)

D(26)

D(25)

D(23)

D(24)

RDY

t

RACC

t

RACC

Note: Figure is for any odd address other than 3Fh (or multiple thereof).

Figure 19. Reduced Wait-state Handshake Burst Suspend/Resume at an odd address

October 23, 2003

Am42BDS6408H

57

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Resume

Suspend

x+1

x+2

x+3

x+4

x+5

x+7

x+8

x+9

x

x+6

x+10

CLK

AVD#

t

OES

t

OES

Addresses

OE#

t

CKA

t

CKZ

D(41)

D(42)

D(41)

D(3E)

D(41)

D(3E)

D(3F)

D(40)

D(3F)

D(41)

D(3F)

Data

RDY

t

RACC

Figure 20. Reduced Wait-state Handshake Burst Suspend/Resume at address 3Eh (or offset from 3Eh)

Resume

x+1

Suspend

x+2

x+3

x+4

x+5

x+7

x+8

x+9

x

x+6

x+10

CLK

AVD#

t

OES

t

OES

Addresses

OE#

t

CKA

t

CKZ

D(41)

D(43)

D(42)

D(3F)

RACC

D(41)

D(3F)

D(41)

D(40)

D(41)

D(3F)

Data

RDY

t

RACC

t

RACC

Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at address 3Fh (or offset from 3Fh by

a multiple of 64)

58

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Resume

x+1

Suspend

x

x+2

x+3

x+4

x+6

x+7

x+8

1

2

6

5

3

4

7

x+5

CLK

AVD#

t

OES

A(n)

Addresses

t

CKA

OE#

Data(1)

D(n)

D(n+2)

D(n+1)

3F

D(3F)

3F

D(40)

t

ACC

RDY(1)

t

RACC

D(n+2) D(n+3) D(n+4) D(n+5)

Data(2)

RDY(2)

D(n+1)

D(n)

D(n+6)

t

RACC

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) RDY goes low during the two-cycle latency during a boundary crossing.

2) RDY stays high when a burst sequence crosses no boundaries.

Figure 22. Standard Handshake Burst Suspend prior to Initial Access

Resume

Suspend

x

1

6

9

x+2

5

x+1

2

3

4

7

8

x+3

CLK

AVD#

t_OES

Addresses

OE#(1)

A(n)

t_CKA

t_CKZ

D(n)

D(n+1)

Data(1)

RDY(1)

t_ACC

t_RACC

OE#(2)

Data(2)

D(n+2)

D(n+1)

D(n)

D(n+1)

t_RACC

RDY(2)

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Burst suspend during the initial synchronous access

2) Burst suspend after one clock cycle following the initial synchronous access

Figure 23. Standard Handshake Burst Suspend at or after Inital Access

October 23, 2003

Am42BDS6408H

59

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Resume

x+1

Suspend

x

x+2

x+5

x+4

x+3

1

2

6

9

5

3

4

7

8

CLK

AVD#

t_OES

A(3D)

Addresses

t_CKA

OE#

Data

t_CKZ

D(3F)

D(3F) D(4D)

D(3D)

D(3E)

D(3F)

t_ACC

t_RACC

RDY

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

Figure 24. Standard Handshake Burst Suspend at address 3Fh (starting address 3Dh or earlier)

Resume

x+1

Suspend

5

x

1

2

3

6

7

x+2

x+3

4

x+4

x+5

x+6

8

CLK

AVD#

t_OES

A(3E)

Addresses(1)

t_OES

t_CKA

OE#

t_CKZ

D(40)

D(3F)

D(41)

D(42)

D(3E)

Data(1)

RDY(1)

t_ACC

t_RACC

Addresses(2)

A(3F)

Data(2)

RDY(2)

D(41)

D(3F)

t_RACC

D(40)

D(42)

D(43)

D(3F)

t

t_RACC

RACC

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Address is 3Eh or offset by a multiple of 64 (40h)

2) Address is 3Fh or offset by a multiple of 64 (40h)

Figure 25. Standard Handshake Burst Suspend at address 3Eh/3Fh (without a valid Initial Access)

60

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Suspend

8

Resume

x+1

5

1

2

3

6

7

4

9

x

x+2

x+3

x+4

x+5

x+6

CLK

AVD#

t

OES

A(3E)

Addresses(1)

OE#

t_OES

t

CKA

t

CKZ

D(40)

Data(1)

D(3F)

RACC

D(41)

D(42)

D(3E)

t

ACC

RDY(1)

(Even)

t

RACC

t

RACC

t

Addresses(2)

Data(2)

A(3F)

D(3F)

D(41)

D(42)

D(40)

D(43)

D(40)

RACC

RDY(2)

(Odd)

t

RACC

t

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Address 3Eh or offset by a multiple of 64 (40h)

2) Address is 3Fh or offset by a multiple of 64 (40h)

Figure 26. Standard Handshake Burst Suspend at address 3Eh/3Fh (with 1 Access CLK)

Resume

x+1

Suspend

x

x+2

x+3

x+4

x+6

x+7

x+8

1

6

5

2

3

4

7

x+5

CLK

t

RCC

AVD#

t

OES

A(n)

Addresses

OE#

t

CKA

Data(1)

RDY

D(n)

D(n+2)

D(n+1)

D(3F) D(3F)

D(3F)

D(40)

t

ACC

t

RACC

D(n)

???

Data(2)

CE#

???

t

RCC

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Device crosses a page boundary prior to t

RCC

2) Device neither crosses a page boundary nor latches a new address prior to t

RCC

Figure 27. Read Cycle for Continuous Suspend

October 23, 2003

Am42BDS6408H

61

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Asynchronous Mode Read (^V= 1.8 V)

IO

Parameter

E3, E4,

E8, E9

D6, D7,

D8, D9

JEDEC Standard Description

(66 MHz)

(54 MHz)

Unit

ns

t

Access Time from CE# Low

Asynchronous Access Time (Note 1)

AVD# Low Time

Max

Min

Max

Min

50

10

4

TBD

12

CE

t

ns

ACC

t

ns

AVDP

AAVDS

AAVDH

t

Address Setup Time to Rising Edge of AVD

Address Hold Time from Rising Edge of AVD

Output Enable to Output Valid

Read

5

ns

t

6

7

ns

t

11

13.5

ns

OE

0

ns

t

Output Enable Hold Time

Toggle and

OEH

Min

8

10

ns

Data# Polling

Output Enable to High Z (Note 2)

CE# Setup Time to AVD#

t

Max

Min

ns

OEZ

CAS

Notes:

1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#.

2. Not 100% tested.

62

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

CE#

t_OE

OE#

t_OEH

WE#

Data

t_CE

t_OEZ

Valid RD

t_ACC

RA

Addresses

AVD#

t_AAVDH

t_CAS

t_AVDP

t_AAVDS

Note: RA = Read Address, RD = Read Data.

Figure 28. Asynchronous Mode Read with Latched Addresses

CE#

OE#

t_OE

t_OEH

WE#

Data

t_CE

t_OEZ

Valid RD

t_ACC

RA

Addresses

AVD#

Note: RA = Read Address, RD = Read Data.

Figure 29. Asynchronous Mode Read

October 23, 2003

Am42BDS6408H

63

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

All Speed

Options

JEDEC

Std

Description

RESET# Pin Low (During Embedded Algorithms)

Unit

t

Max

20

µs

Ready

to Read Mode (See Note)

RESET# Pin Low (NOT During Embedded Algorithms)

to Read Mode (See Note)

500

ns

Ready

t

RESET# Pulse Width

Min

500

200

20

ns

µs

RP

t

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RH

t

RPD

Note: Not 100% tested.

CE#, OE#

t_RH

RESET#

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

CE#, OE#

RESET#

t_Ready

t_RP

Figure 30. Reset Timings

64

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase/Program Operations (V = 1.8 V)

IO

Parameter

E6, E7,

E8, E9

D6, D7,

D8, D9

JEDEC Standard Description

(66 MHz)

(54 MHz)

Unit

t

Write Cycle Time (Note 1)

Min

50

4

55

5

ns

AVAV

WC

Synchronous

Address Setup Time

(Notes 2, 3)

t

ns

AVWL

AS

Asynchronous

Synchronous

Asynchronous

0

6

7

Address Hold Time

(Notes 2, 3)

t

Min

WLAX

AH

20

10

20

12

45

t

AVD# Low Time

Data Setup Time

Data Hold Time

Min

Typ

ns

µs

AVDP

t

DVWH

DS

DH

t

0

WHDX

t

Read Recovery Time Before Write

CE# Setup Time to AVD#

GHWL

t

CAS

t

CE# Hold Time

WHEH

WLWH

WHWL

CH

t

Write Pulse Width

20

30

20

WP

t

Write Pulse Width High

WPH

t

Latency Between Read and Write Operations

Programming Operation (Note 4)

Accelerated Programming Operation (Note 4)

Sector Erase Operation (Notes 4, 5)

Chip Erase Operation (Notes 4, 5)

0

9

SR/W

t

WHWH1

4

0.4

54

500

1

t

Typ

sec

WHWH2

t

V

Rise and Fall Time

Min

ns

µs

ns

VID

ACC

t

V Setup Time (During Accelerated Programming)

ACC

VIDS

t

V Setup Time

CC

50

0

VCS

t

CE# Setup Time to WE#

ELWL

CS

t

AVD# Setup Time to WE#

4

6

4

5

7

5

AVSW

AVHW

t

AVD# Hold Time to WE#

t

Address Setup Time to CLK (Notes 2, 3)

Address Hold Time to CLK (Notes 2, 3)

AVD# Hold Time to CLK

ACS

ACH

t

AVHC

t

Clock Setup Time to WE#

5

CSW

Notes:

1. Not 100% tested.

2. Asynchronous mode allows the Asynchronous program operation only. Synchronous mode allows both Asynchronous and Synchronous program

operation.

3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#. In synchronous program

operation timing, addresses are latched on the first of either the falling edge of WE# or the active edge of CLK.

4. See the “Erase and Programming Performance” section for more information.

5. Does not include the preprogramming time.

October 23, 2003

Am42BDS6408H

65

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

V

IL

t_AVDP

AVD#

t_AH

t_AS

PA

VA

Addresses

Data

555h

In

Complete

A0h

PD

t_DS

t_DH

Progress

CE#

t_CH

OE#

WE#

t_WP

t_WHWH1

t_CS

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A21–A12 are don’t care during command sequence unlock cycles.

4. CLK can be either V or V .

IL

IH

5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.

Figure 31. Asynchronous Program Operation Timings: AVD# Latched Addresses

66

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

V

IL

t_AVSW

t_AVHW

AVD#

t_AVDP

t_AS

t_AH

Addresses

Data

555h

PA

VA

In

A0h

Complete

PD

Progress

t_DS

t_DH

CE#

t_CH

OE#

WE#

t_WP

t_WHWH1

t_CS

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A21–A12 are don’t care during command sequence unlock cycles.

4. CLK can be either V or V .

IL

IH

5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.

Figure 32. Asynchronous Program Operation Timings: WE# Latched Addresses

October 23, 2003

Am42BDS6408H

67

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

t_AVCH

Read Status Data

CLK

t_ACS

t_ACH

AVD#

t_AVDP

Addresses

555h

PA

VA

In

Data

Complete

A0h

PD

t_DS

t_DH

Progress

t_CAS

CE#

OE#

t_CH

t_CSW

t_WP

WE#

t_WHWH1

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A21–A12 are don’t care during command sequence unlock cycles.

4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.

5. Either CE# or AVD# is required to go from low to high in between programming command sequences.

6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The

Configuration Register must be set to the Synchronous Read Mode.

Figure 33. Synchronous Program Operation Timings: WE# Latched Addresses

68

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

t_AVCH

Read Status Data

CLK

t_AS

t_AH

AVD#

t_AVDP

Addresses

555h

PA

VA

In

Data

Complete

A0h

PD

t_DS

t_DH

Progress

t_CAS

CE#

t_CH

OE#

WE#

t_CSW

t_WP

t_WHWH1

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A21–A12 are don’t care during command sequence unlock cycles.

4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.

5. Either CE# or AVD# is required to go from low to high in between programming command sequences.

6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The

Configuration Register must be set to the Synchronous Read Mode.

Figure 34. Synchronous Program Operation Timings: CLK Latched Addresses

October 23, 2003

Am42BDS6408H

69

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

V

IL

t_AVDP

AVD#

t_AH

t_AS

SA

555h for

chip erase

VA

Addresses

Data

2AAh

10h for

chip erase

In

Complete

55h

30h

Progress

t_DS

t_DH

CE#

t_CH

OE#

WE#

t_WP

t_WHWH2

t_CS

t_WPH

t_WC

t_VCS

V_CC

Figure 35. Chip/Sector Erase Command Sequence

Notes:

1. SA is the sector address for Sector Erase.

2. Address bits A21–A12 are don’t cares during unlock cycles in the command sequence.

70

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

CE#

AVD#

WE#

Addresses

Data

PA

Don't Care

A0h

Don't Care

PD

Don't Care

OE#

t_VIDS

1 µs

V

ID

ACC

t_VID

V

or V

IH

IL

Note: Use setup and hold times from conventional program operation.

Figure 36. Accelerated Unlock Bypass Programming Timing

October 23, 2003

Am42BDS6408H

71

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

AVD#

t_CEZ

t_CE

CE#

t_OEZ

t_CH

t_OE

OE#

t_OEH

WE#

t_ACC

VA

Addresses

Data

VA

Status Data

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete,

and Data# Polling will output true data.

3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.

Figure 37. Data# Polling Timings (During Embedded Algorithm)

AVD#

t_CEZ

t_CE

CE#

t_OEZ

t_CH

t_OE

OE#

WE#

t_OEH

t_ACC

Addresses

Data

VA

Status Data

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete,

the toggle bits will stop toggling.

3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.

Figure 38. Toggle Bit Timings (During Embedded Algorithm)

72

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

CE#

CLK

AVD#

Addresses

OE#

VA

t_IACC

Data

Status Data

RDY

Notes:

1. The timings are similar to synchronous read timings.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the

toggle bits will stop toggling.

3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one

clock cycle before data.

Figure 39. Synchronous Data Polling Timings/Toggle Bit Timings

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 40. DQ2 vs. DQ6

October 23, 2003

Am42BDS6408H

73

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

ns

t

V

Rise and Fall Time (See Note)

HH

Min

500

250

VIDR

ID

t

V

ns

VHH

RESET# Setup Time for Temporary Sector

Unprotect

t

Min

4

µs

RSP

RESET# Hold Time from RDY High for

Temporary Sector Unprotect

t

RRB

Note: Not 100% tested.

V_ID

RESET#

V_ILor V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

RDY

t_RRB

t_RSP

Figure 41. Temporary Sector Unprotect Timing Diagram

74

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

V

ID

V

IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector Protect/Unprotect

Verify

40h

Data

60h

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 42. Sector/Sector Block Protect and

Unprotect Timing Diagram

October 23, 2003

Am42BDS6408H

75

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS)

Address boundary occurs every 64 words, beginning at address

00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.

C60

C61

3D

C62

3E

C63

3F

C63

3F

C63

3F

C64

40

C65

41

C66

42

C67

43

CLK

3C

Address (hex)

(stays high)

AVD#

RDY(1)

RDY(2)

t_RACC

latency

t_RACC

latency

Data

D60

D61

D62

D63

D64

D65

D66

D67

Notes:

1. RDY active with data (A18 = 0 in the Configuration Register).

2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing

a bank in the process of performing an erase or program.

4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle latency at

the boundary crossing.

Figure 43. Latency with Boundary Crossing

76

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Address boundary occurs every 64 words, beginning at address

00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.

C60

C61

3D

C62

3E

C63

3F

C63

3F

C63

3F

C64

40

CLK

3C

Address (hex)

(stays high)

AVD#

RDY(1)

RDY(2)

t_RACC

latency

t_RACC

latency

Data

Invalid

D60

D61

D62

D63

Read Status

OE#,

CE#

(stays low)

Notes:

1. RDY active with data (A18 = 0 in the Configuration Register).

2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a

bank in the process of performing an erase or program.

Figure 44. Latency with Boundary Crossing

into Program/Erase Bank

October 23, 2003

Am42BDS6408H

77

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Data

D0

D1

Rising edge of next clock cycle

following last wait state triggers

next burst data

AVD#

OE#

total number of clock cycles

following AVD# falling edge

1

2

0

3

1

4

5

6

4

7

5

CLK

2

3

number of clock cycles

programmed

Wait State Decoding Addresses:

A14, A13, A12 = “111” ⇒ Reserved

A14, A13, A12 = “110” ⇒ Reserved

A14, A13, A12 = “101” ⇒ 5 programmed, 7 total

A14, A13, A12 = “100” ⇒ 4 programmed, 6 total

A14, A13, A12 = “011” ⇒ 3 programmed, 5 total

A14, A13, A12 = “010” ⇒ 2 programmed, 4 total

A14, A13, A12 = “001” ⇒ 1 programmed, 3 total

A14, A13, A12 = “000” ⇒ 0 programmed, 2 total

Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.

Figure 45. Example of Wait States Insertion

78

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Last Cycle in

Program or

Sector Erase

Read status (at least two cycles) in same bank

and/or array data from other bank

Begin another

write or program

command sequence

Command Sequence

t_WC

t_RC

t_WC

CE#

OE#

t_OE

t_OEH

t_GHWL

WE#

Data

t_WPH

t_OEZ

t_WP

t_DS

t_ACC

t_OEH

t_DH

PD/30h

RD

AAh

t_SR/W

RA

Addresses

AVD#

PA/SA

t_AS

RA

555h

t_AH

Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking

the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information.

Figure 46. Back-to-Back Read/Write Cycle Timings

October 23, 2003

Am42BDS6408H

79

A D V A N C E I N F O R M A T I O N

SRAM AC CHARACTERISTICS

Read Cycle

Parameter

Symbol

E6, E7,

D6, D7

E8, E9,

D8, D9

Description

Unit

t

Read Cycle Time

Min

Max

Min

55

25

55

70

35

70

ns

RC

t

Address Access Time

AA

t

, t

Chip Enable to Output

CO1 CO2

t

Output Enable Access Time

OE

t

LB#s, UB#s to Access Time

BA

t

, t

Chip Enable (CE1#s Low and CE2s High) to Low-Z Output

UB#, LB# Enable to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

UB#s, LB#s Disable to High-Z Output

Output Disable to High-Z Output

Output Data Hold from Address Change

10

5

LZ1 LZ2

t

Min

BLZ

OLZ

t

Min

t

, t

Max

Min

25

10

HZ1 HZ2

t

BHZ

OHZ

t

OH

t_RC

Address

t_AA

t_OH

Data Valid

Data Out

Note: CE1#s = OE# = V , CE2s = WE# = V , UB#s and/or LB#s = V

IL

Previous Data Valid

IL

IH

Figure 47. SRAM Read Cycle—Address Controlled

80

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

SRAM AC CHARACTERISTICS

t_RC

Address

t_AA

t_CO1

t_OH

CE#1s

CE2s

t_CO2

t_OE

t_HZ

OE#

t_OLZ

t_BLZ

t_LZ

t_OHZ

Data Out

High-Z

Data Valid

Figure 48. SRAM Read Cycle

Notes:

1. WE# = V .

IH

2. t and t

are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output

HZ

OHZ

voltage levels.

3. At any given temperature and voltage condition, t (Max.) is less than t (Min.) both for a given device and from device to device

HZ

LZ

interconnection.

October 23, 2003

Am42BDS6408H

81

A D V A N C E I N F O R M A T I O N

SRAM AC CHARACTERISTICS

Write Cycle

Parameter

Symbol

E6, E7,

D6, D7

E8, E9,

D8, D9

Description

Unit

t

Write Cycle Time

Min

Max

Min

min

55

45

70

60

ns

WC

t

Chip Enable to End of Write

Address Setup Time

Cw

t

0

AS

AW

BW

WP

WR

t

Address Valid to End of Write

UB#s, LB#s to End of Write

Write Pulse Time

45

60

50

t

Write Recovery Time

0

t

Write to Output High-Z

ns

WHZ

20

30

0

t

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

ns

DW

t

DH

t

5

OW

t_WC

Address

CE1#s

CE2s

t_WR

t_CW

(See Note 1)

t_AW

t_CW

(See Note 1)

t_WP

(See Note 4)

WE#

t_AS

(See Note 3)

t_DH

t_DW

Data In

Data Out

High-Z

Data Valid

High-Z

t_WHZ

t_OW

Data Undefined

Notes:

1. WE# controlled.

2. t

3. t

is measured from CE1#s going low to the end of write.

is measured from the end of write to the address change. t

CW

applied in case a write ends as CE1#s or WE# going high.

WR

4. t is measured from the address valid to the beginning of write.

AS

5. A write occurs during the overlap (t ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

WP

asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A

write ends at the earliest transition when CE1#s goes high and WE# goes high. The t is measured from the beginning of write

WP

to the end of write.

Figure 49. SRAM Write Cycle—WE# Control

82

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

SRAM AC CHARACTERISTICS

t_WC

Address

t_AS(See Note 2 )

t_CW

t_WR(See Note 4)

(See Note 3)

CE1#s

t_AW

CE2s

t_BW

UB#s, LB#s

t_WP

(See Note 5)

WE#

t_DW

t_DH

Data Valid

Data In

Data Out

High-Z

Notes:

1. CE1#s controlled.

2. t

3. t

is measured from CE1#s going low to the end of write.

is measured from the end of write to the address change. t

CW

WR

applied in case a write ends as CE1#s or WE# going high.

WR

4. t is measured from the address valid to the beginning of write.

AS

5. A write occurs during the overlap (t ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

WP

asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A

write ends at the earliest transition when CE1#s goes high and WE# goes high. The t is measured from the beginning of write

WP

to the end of write.

Figure 50. SRAM Write Cycle—CE1#s Control

October 23, 2003

Am42BDS6408H

83

A D V A N C E I N F O R M A T I O N

SRAM AC CHARACTERISTICS

t_WC

Address

CE1#s

t_CW

(See Note 2)

t_WR(See Note 3)

t_AW

t_CW(See Note 2)

CE2s

t_BW

UB#s, LB#s

t_AS

t_WP

(See Note 4)

(See Note 5)

WE#

t_DW

t_DH

Data In

Data Out

Data Valid

High-Z

Notes:

1. UB#s and LB#s controlled.

2. t

3. t

is measured from CE1#s going low to the end of write.

is measured from the end of write to the address change. t

CW

applied in case a write ends as CE1#s or WE# going high.

WR

4. t is measured from the address valid to the beginning of write.

AS

5. A write occurs during the overlap (t ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

WP

asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A

write ends at the earliest transition when CE1#s goes high and WE# goes high. The t is measured from the beginning of write

WP

to the end of write.

Figure 51. SRAM Write Cycle—UB#s and LB#s Control

84

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

32 Kword

4 Kword

0.4

0.2

54

5

Sector Erase Time

s

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

s

µs

s

Excludes system level

overhead (Note 5)

Word Programming Time

9

4

210

120

114

50

Accelerated Word Programming Time

Chip Programming Time (Note 3)

Excludes system level

overhead (Note 5)

38

17

Accelerated Chip Programming Time

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 1.8 V V , 1 million cycles. Additionally,

CC

programming typicals assumes a checkerboard pattern.

2. Under worst case conditions of 90°C, V = 1.65 V, 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed.

4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 16, “Command Definitions,” on page 40 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1 million cycles.

BGA BALL CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

= 0

Typ

4.2

5.4

3.9

Max

5.0

6.5

4.7

Unit

pF

C

V

IN

C

Output Capacitance

Control Pin Capacitance

V

= 0

pF

OUT

C

V

= 0

pF

IN2

IN

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

October 23, 2003

Am42BDS6408H

85

A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS

TLB 089—89-ball Fine-Pitch Ball Grid Array (FBGA) 10 x 8 mm Package

A

D1

D

eD

0.15

(2X)

C

10

9

8

7

6

5

4

3

2

1

SE

7

E

B

E1

eE

J

H

G

F

E

D

C

B

A

K

INDEX MARK

10

PIN A1

CORNER

PIN A1

CORNER

7

SD

0.15

(2X)

C

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.20

0.08

C

A2

A

C

A1

6

89X

b

0.15

0.08

M

C

A B

M

NOTES:

PACKAGE

JEDEC

TLB089

N/A

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

10.00 mm x 8.00 mm

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

SYMBOL

MIN

NOM

---

MAX

1.20

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

---

PROFILE

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

0.20

0.81

---

BALL HEIGHT

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

A2

---

0.97

BODY THICKNESS

BODY SIZE

D

10.00 BSC.

8.00 BSC.

7.20 BSC.

10

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

E

BODY SIZE

D1

E1

MATRIX FOOTPRINT

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

MD

ME

n

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

10

89

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

φb

0.33

---

0.43

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

eE

0.80 BSC

0.40 BSC

BALL PITCH

eD

SD / SE

BALL PITCH

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

SOLDER BALL PLACEMENT

B10,C1,C10,D1,D10,G1,G10

H1,H10,J1,J10

DEPOPULATED SOLDER BALLS

9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3294\ 16-038.22a

Note: BSC is an ANSI standard for Basic Space Centering

86

Am42BDS6408H

October 23, 2003

A D V A N C E I N F O R M A T I O N

REVISION SUMMARY

Revision A (July 14, 2003)

Initial release.

Revision A+1 (July 15, 2003)

Corrected Ordering Information OPNs.

Revision A+2 (July 21, 2003)

Corrected typos in datasheet regarding package name.

Revision A+3 (October 23, 2003)

Corrected globally all pSRAM to SRAM. Remove 80

MHz option throughout.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

October 23, 2003

Am42BDS6408H

87


型号：	AM42BDS6408HE3IT
厂家：	SPANSION
描述：	Memory Circuit, 4MX16, CMOS, PBGA89, 10 X 8 MM, FBGA-89
文件：	总90页 (文件大小：1264K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM42BDS6408HE3IT [SPANSION]

相关型号：

AM42BDS6408HE4FS

AM42BDS6408HE4FT

AM42BDS6408HE4I

AM42BDS6408HE4IS

AM42BDS6408HE4IT

AM42BDS6408HE8FS

AM42BDS6408HE8FT

AM42BDS6408HE8I

AM42BDS6408HE8IS

AM42BDS6408HE8IT

AM42BDS6408HE9FS

AM42BDS6408HE9FT