AM49DL640BG30IT_技术文档

PRELIMINARY

Am49DL640BG

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous

Operation Flash Memory and 32 Mbit (512 K x 16-Bit) Pseudo Static RAM with Page Mode

DISTINCTIVE CHARACTERISTICS

■ 20 year data retention at 125°C

MCP Features

■ Power supply voltage of 2.7 to 3.3 volt

—

Reliable operation for the life of the system

SOFTWARE FEATURES

■ High performance

—

Access time as fast as 70 ns

■ Data Management Software (DMS)

■ Package

—

AMD-supplied software manages data programming,

enabling EEPROM emulation

—

73-Ball FBGA

—

Eases historical sector erase flash limitations

■ Operating Temperature

■ Supports Common Flash Memory Interface (CFI)

—

–40°C to +85°C

■ Program/Erase Suspend/Erase Resume

Flash Memory Features

—

Suspends program/erase operations to allow

programming/erasing in same bank

ARCHITECTURAL ADVANTAGES

■ Data# Polling and Toggle Bits

■ Simultaneous Read/Write operations

—

Provides a software method of detecting the status of

program or erase cycles

—

Data can be continuously read from one bank while

executing erase/program functions in another bank.

Zero latency between read and write operations

■ Unlock Bypass Program command

—

Reduces overall programming time when issuing multiple

program command sequences

■ Flexible Bank architecture

—

Read may occur in any of the three banks not being written

or erased.

HARDWARE FEATURES

—

Four banks may be grouped by customer to achieve desired

bank divisions.

■ Any combination of sectors can be erased

■ Ready/Busy# output (RY/BY#)

■ Manufactured on 0.17 µm process technology

—

Hardware method for detecting program or erase cycle

completion

■ SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector

—

Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number; verifiable

as factory locked through autoselect function. ExpressFlash

option allows entire sector to be available for

factory-secured data

■ Hardware reset pin (RESET#)

—

Hardware method of resetting the internal state machine to

the read mode

■ WP#/ACC input pin

—

Customer lockable: Sector is one-time programmable. Once

sector is locked, data cannot be changed.

—

Write protect (WP#) function protects sectors 0, 1, 140, and

141, regardless of sector protect status

—

Acceleration (ACC) function accelerates program timing

■ Zero Power Operation

Sophisticated power management circuits reduce power

consumed during inactive periods to nearly zero.

■ Boot sectors

■ Sector protection

—

Hardware method of locking a sector, either in-system or

using programming equipment, to prevent any program or

erase operation within that sector

Temporary Sector Unprotect allows changing data in

protected sectors in-system

—

Top and bottom boot sectors in the same device

—

■ Compatible with JEDEC standards

—

Pinout and software compatible with single-power-supply

flash standard

pSRAM Features

■ Power dissipation

PERFORMANCE CHARACTERISTICS

—

Operating: 40 mA maximum

Standby: 70 µA maximum

Deep power-down standby: 5 µA

■ High performance

—

Access time as fast as 70 ns

Program time: 4 µs/word typical utilizing Accelerate function

■ CE1s# and CE2s Chip Select

■ Ultra low power consumption (typical values)

■ Power down features using CE1s# and CE2s

■ Data retention supply voltage: 2.7 to 3.3 volt

■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)

■ 8-word page mode access

—

2 mA active read current at 1 MHz

10 mA active read current at 5 MHz

200 nA in standby or automatic sleep mode

■ Minimum 1 million write cycles guaranteed per sector

Publication# 26090 Rev: A Amendment/0

Issue Date: March 8, 2002

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

P R E L I M I N A R Y

GENERAL DESCRIPTION

Am29DL640G Features

Factory locked parts provide several options. The

SecSi Sector may store a secure, random 16 byte

ESN (Electronic Serial Number), customer code (pro-

grammed through AMD’s ExpressFlash service), or

both. Customer Lockable parts may utilize the SecSi

Sector as a one-time programmable area.

The Am29DL640G is a 64 megabit, 3.0 volt-only flash

memory device, organized as 4,194,304 words of 16

bits each or 8,388,608 bytes of 8 bits each. Word

mode data appears on DQ15–DQ0; byte mode data

appears on DQ7–DQ0. The device is designed to be

programmed in-system with the standard 3.0 volt V_CC

supply, and can also be programmed in standard

EPROM programmers.

DMS (Data Management Software) allows systems

to easily take advantage of the advanced architecture

of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS will also allow the

system software to be simplified, as it will perform all

functions necessary to modify data in file structures,

as opposed to single-byte modifications. To write or

update a particular piece of data (a phone number or

configuration data, for example), the user only needs

to state which piece of data is to be updated, and

where the updated data is located in the system. This

is an advantage compared to systems where

user-written software must keep track of the old data

location, status, logical to physical translation of the

data onto the Flash memory device (or memory de-

vices), and more. Using DMS, user-written software

does not need to interface with the Flash memory di-

rectly. Instead, the user's software accesses the Flash

memory by calling one of only six functions. AMD pro-

vides this software to simplify system design and soft-

ware integration efforts.

The device is available with an access time of 70 or 85

ns and is offered in a 73-ball FBGA package. Standard

control pins—chip enable (CE#f), write enable (WE#),

and output enable (OE#)—control normal read and

write operations, and avoid bus contention issues.

The device requires only a single 3.0 volt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation by dividing the memory

space into four banks, two 8 Mb banks with small and

large sectors, and two 24 Mb banks of large sectors

only. Sector addresses are fixed, system software can

be used to form user-defined bank groups.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

register using standard microprocessor write timings.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

During an Erase/Program operation, any of the three

non-busy banks may be read from. Note that only two

banks can operate simultaneously. The device can im-

prove overall system performance by allowing a host

system to program or erase in one bank, then

immediately and simultaneously read from the other

bank, with zero latency. This releases the system from

waiting for the completion of program or erase

operations.

The host system can detect whether a program or

erase operation is complete by using the device sta-

tus bits: RY/BY# pin, DQ7 (Data# Polling) and

DQ6/DQ2 (toggle bits). After a program or erase cycle

has been completed, the device automatically returns

to the read mode.

The Am29DL640G can be organized as both a top

and bottom boot sector configuration.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Bank

Megabits

Sector Sizes

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

Bank 1

8 Mb

Bank 2

Bank 3

24 Mb

Forty-eight 64 Kbyte/32 Kword

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

Bank 4

8 Mb

The SecSi™ (Secured Silicon) Sector is an extra

256 byte sector capable of being permanently locked

by AMD or customers. The SecSi Indicator Bit (DQ7)

is permanently set to a 1 if the part is factory locked,

and set to a 0 if customer lockable. This way, cus-

tomer lockable parts can never be used to replace a

factory locked part.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly re-

duced in both modes.

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Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

TABLE OF CONTENTS

Figure 4. Erase Operation.............................................................. 28

Table 12. Am29DL640G Command Definitions.............................. 29

Flash Write Operation Status . . . . . . . . . . . . . . . 30

DQ7: Data# Polling ................................................................. 30

Figure 5. Data# Polling Algorithm .................................................. 30

RY/BY#: Ready/Busy# ............................................................ 31

DQ6: Toggle Bit I .................................................................... 31

Figure 6. Toggle Bit Algorithm........................................................ 31

DQ2: Toggle Bit II ................................................................... 32

Reading Toggle Bits DQ6/DQ2 ............................................... 32

DQ5: Exceeded Timing Limits ................................................ 32

DQ3: Sector Erase Timer .......................................................32

Table 13. Write Operation Status ................................................... 33

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34

Figure 7. Maximum Negative Overshoot Waveform ...................... 34

Figure 8. Maximum Positive Overshoot Waveform........................ 34

Flash DC Characteristics . . . . . . . . . . . . . . . . . . 35

CMOS Compatible ..................................................................35

Figure 9. I_CC1Current vs. Time (Showing Active and

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5

Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7

Special Package Handling Instructions .................................... 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

MCP Device Bus Operations . . . . . . . . . . . . . . . .10

Table 1. Device Bus Operations—Flash Word Mode, CIOf = V_IH... 10

Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V_IL..... 11

Flash Device Bus Operations . . . . . . . . . . . . . . . 12

Word/Byte Configuration ........................................................ 12

Requirements for Reading Array Data ...................................12

Writing Commands/Command Sequences ............................ 12

Accelerated Program Operation .......................................... 12

Autoselect Functions ........................................................... 12

Simultaneous Read/Write Operations with Zero Latency ....... 12

Standby Mode ........................................................................ 13

Automatic Sleep Mode ........................................................... 13

RESET#: Hardware Reset Pin ............................................... 13

Output Disable Mode .............................................................. 13

Table 3. Am29DL640G Sector Architecture ....................................14

Table 4. Bank Address ....................................................................17

Table 5. SecSi Sector Addresses ...............................................17

Sector/Sector Block Protection and Unprotection .................. 18

Table 6. Am29DL640G Boot Sector/Sector Block Addresses for Pro-

tection/Unprotection ........................................................................18

Write Protect (WP#) ................................................................ 19

Table 7. WP#/ACC Modes ..............................................................19

Temporary Sector Unprotect .................................................. 19

Figure 1. Temporary Sector Unprotect Operation........................... 19

Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 20

SecSi™ (Secured Silicon) Sector

Automatic Sleep Currents)............................................................. 37

Figure 10. Typical I_CC1vs. Frequency............................................ 37

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 11. Test Setup.................................................................... 38

Figure 12. Input Waveforms and Measurement Levels ................. 38

pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 39

CE#s Timing ...........................................................................39

Figure 13. Timing Diagram for Alternating

Between Pseudo SRAM to Flash................................................... 39

Read-Only Operations ........................................................... 40

Figure 14. Read Operation Timings............................................... 40

Hardware Reset (RESET#) .................................................... 41

Figure 15. Reset Timings............................................................... 41

Word/Byte Configuration (CIOf) ..............................................42

Figure 16. CIOf Timings for Read Operations................................ 42

Figure 17. CIOf Timings for Write Operations................................ 42

Erase and Program Operations .............................................. 43

Figure 18. Program Operation Timings.......................................... 44

Figure 19. Accelerated Program Timing Diagram.......................... 44

Figure 20. Chip/Sector Erase Operation Timings .......................... 45

Figure 21. Back-to-back Read/Write Cycle Timings ...................... 46

Figure 22. Data# Polling Timings (During Embedded Algorithms). 46

Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 47

Figure 24. DQ2 vs. DQ6................................................................. 47

Temporary Sector Unprotect .................................................. 48

Figure 25. Temporary Sector Unprotect Timing Diagram .............. 48

Figure 26. Sector/Sector Block Protect and

Flash Memory Region ............................................................ 21

Hardware Data Protection ......................................................21

Low V_CCWrite Inhibit ........................................................... 21

Write Pulse “Glitch” Protection ............................................ 22

Logical Inhibit ...................................................................... 22

Power-Up Write Inhibit ......................................................... 22

Common Flash Memory Interface (CFI) . . . . . . .22

Table 8. CFI Query Identification String.......................................... 22

System Interface String................................................................... 23

Table 10. Device Geometry Definition ............................................ 23

Table 11. Primary Vendor-Specific Extended Query ...................... 24

Flash Command Definitions . . . . . . . . . . . . . . . . 25

Reading Array Data ................................................................ 25

Reset Command ..................................................................... 25

Autoselect Command Sequence ............................................ 25

Enter SecSi™ Sector/Exit SecSi Sector

Unprotect Timing Diagram ............................................................. 49

Alternate CE#f Controlled Erase and Program Operations .... 50

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)

Operation Timings.......................................................................... 51

Read Cycle ............................................................................. 52

Figure 28. Psuedo SRAM Read Cycle........................................... 52

Figure 29. Page Read Timing ........................................................ 53

Write Cycle .............................................................................54

Figure 30. Pseudo SRAM Write Cycle—WE# Control ................... 54

Figure 31. Pseudo SRAM Write Cycle—CE1#s Control................ 55

Figure 32. Pseudo SRAM Write Cycle—

Command Sequence .............................................................. 25

Byte/Word Program Command Sequence ............................. 26

Unlock Bypass Command Sequence ..................................26

Figure 3. Program Operation .......................................................... 27

Chip Erase Command Sequence ........................................... 27

Sector Erase Command Sequence ........................................ 27

Erase Suspend/Erase Resume Commands ........................... 28

UB#s and LB#s Control.................................................................. 56

Flash Erase And Programming Performance . . 57

March 8, 2002

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P R E L I M I N A R Y

pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 59

Latchup Characteristics . . . . . . . . . . . . . . . . . . . 57

Package Pin Capacitance . . . . . . . . . . . . . . . . . . 57

Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 57

pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 58

pSRAM Power on and Deep Power Down . . . . . 58

Figure 33. Deep Power-down Timing.............................................. 58

Figure 34. Power-on Timing............................................................ 58

Figure 35. Read Address Skew ..................................................... 59

Figure 36. Write Address Skew...................................................... 59

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 60

FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 60

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61

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Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

PRODUCT SELECTOR GUIDE

Part Number

Am49DL640BG

Flash Memory

Pseudo SRAM

Speed

Options

Standard Voltage Range:

V_CC= 2.7–3.3 V

70

85

70

30

70

25

85

35

85

30

Max Access Time, ns

Page Access Time (pSRAM), ns

CE#f Access, ns

N/A

70

N/A

85

OE# Access, ns

30

40

MCP BLOCK DIAGRAM

V_CC

f

V_SS

A21 to A0

RY/BY#

A21 to A0

A–1

WP#/ACC

RESET#

CE#f

64 MBit

Flash Memory

DQ15/A–1 to DQ0

CIOf

DQ15/A–1 to DQ0

V_CCs/V_CCQV_SS/V_SSQ

A20 to A0

32 MBit

Pseudo

SRAM

LB#s

DQ15/A–1 to DQ0

UB#s

WE#

OE#

CE1#s

CE2s

March 8, 2002

Am49DL640BG

5

P R E L I M I N A R Y

FLASH MEMORY BLOCK DIAGRAM

V

CC

SS

OE# BYTE#

Mux

Bank 1

Bank 1 Address

A21–A0

X-Decoder

Bank 2 Address

RY/BY#

Bank 2

X-Decoder

A21–A0

RESET#

STATE

CONTROL

&

Status

WE#

DQ15–DQ0

COMMAND

REGISTER

CE#

BYTE#

WP#/ACC

Control

Mux

DQ15–DQ0

X-Decoder

Bank 3

Bank 3 Address

Bank 4 Address

X-Decoder

Bank 4

A21–A0

Mux

6

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

CONNECTION DIAGRAM

73-Ball FBGA

Top View

Flash only

A1

A10

NC

Pseudo

SRAM only

B1

B5

NC

C5

B6

B10

NC

Shared

C1

C3

C4

C6

C7

C8

NC

A7

LB# WP#/ACC WE#

A8

A11

D2

A3

D3

A6

D4

D5

D6

D7

A19

E7

A9

D8

A12

E8

A13

F8

D9

A15

E9

A21

F9

NC

UB# RESET# CE2s

E5

E2

A2

E3

A5

E4

E6

A18 RY/BY# A20

F1

NC

G1

NC

F2

A1

F3

A4

F4

A17

G4

DQ1

F7

F10

A10

G7

DQ6

H7

A14

G8

NC

G2

A0

G3

G9 G10

V

SS

A16

NC

H2

CE#f

J2

H3

OE#

J3

H4

DQ9

J4

H5

DQ3

J5

H6

DQ4

J6

H8

H9

DQ13 DQ15/A-1 CIOf

J7

DQ12

K7

J8

DQ7

K8

J9

V

CC

f

V s

CC

CE1#s DQ0

DQ10

K4

V

SS

K3

K5

DQ11

L5

K6

NC

L6

NC

DQ8

DQ2

DQ5

DQ14

L1

NC

M1

NC

L10

NC

M10

NC

package and/or data integrity may be compromised if

the package body is exposed to temperatures above

150°C for prolonged periods of time.

Special Package Handling Instructions

Special handling is required for Flash Memory products

in molded packages (TSOP, SO, PDIP, PLCC). The

March 8, 2002

Am49DL640BG

7

P R E L I M I N A R Y

PIN DESCRIPTION

LOGIC SYMBOL

A20–A0

A21, A-1

DQ15–DQ0

CE#f

= 21 Address Inputs (Common)

21

= 2 Address Inputs (Flash)

= 16 Data Inputs/Outputs (Common)

= Chip Enable (Flash)

A20–A0

A21, A-1

SA

CE1#s

CE2s

= Chip Enable 1 (pSRAM)

= Chip Enable 2 (pSRAM)

= Output Enable (Common)

= Write Enable (Common)

= Ready/Busy Output

16 or 8

CE#f

DQ15–DQ0

OE#

CE1#s

CE2s

WE#

RY/BY#

UB#s

OE#

= Upper Byte Control (pSRAM)

= Lower Byte Control (pSRAM)

WE#

LB#s

WP#/ACC

RESET#

UB#s

CIOf

= I/O Configuration (Flash)

CIOf = V_IH= Word mode (x16),

CIOf = V_IL= Byte mode (x8)

LB#s

RESET#

= Hardware Reset Pin, Active Low

CIOf

WP#/ACC

= Hardware Write Protect/

Acceleration Pin (Flash)

V_CC

f

= Flash 3.0 volt-only single power sup-

ply (see Product Selector Guide for

speed options and voltage supply

tolerances)

V_CCs

= pSRAM Power Supply

V_SS

NC

= Device Ground (Common)

= Pin Not Connected Internally

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Am49DL640BG

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P R E L I M I N A R Y

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following:

Am49DL640

B

G

70

I

T

TAPE AND REEL

T

S

=

7 inches

13 inches

TEMPERATURE RANGE

Industrial (–40°C to +85°C)

I

=

SPEED OPTION

See “Product Selector Guide” on page 5.

PROCESS TECHNOLOGY

G

=

0.17 µm

PSEUDO SRAM DEVICE DENSITY

32 Mbits

B

=

AMD DEVICE NUMBER/DESCRIPTION

Am49DL640BG

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous

Operation Flash Memory and 32 Mbit (2 M x 16-Bit) Pseudo Static RAM with Page Mode

Valid Combinations

Order Number Package Marking

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult the local AMD sales office to confirm

availability of specific valid combinations and to check on newly re-

leased combinations.

Am49DL640BG70I

Am49DL640BG85I

T, S

M490000000

M490000001

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Am49DL640BG

9

P R E L I M I N A R Y

needed to execute the command. The contents of the

MCP DEVICE BUS OPERATIONS

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Tables 1-2 lists the device bus operations, the

inputs and control levels they require, and the result-

ing output. The following subsections describe each of

these operations in further detail.

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

Table 1. Device Bus Operations—Flash Word Mode, CIOf = V_IH

Operation

(Notes 1, 2)

WP#/ACC

(Note 4)

DQ7–

DQ0

DQ15–

DQ8

CE#f CE1#s CE2s OE# WE#

Address

LB#s UB#s RESET#

(Note 7)

(Note 8)

(Note 7)

(Note 8)

H

L

Read from

Flash

A_IN

D_OUT

L

H

L

X

H

L/H

H

L

A_IN

D_IN

Write to Flash

Standby

L

H

(Note 4)

V_CC

±

V_CC±

H

L

X

H

High-Z

0.3 V

V_CC

±

V_CC

±

Deep Power-down

Standby

0.3 V

H

X

Output Disable

L

H

L/H

High-Z

D_IN

High-Z

X

(Note 7)

H

L

Flash Hardware

Reset

X

L

X

H

X

L

X

L

(Note 8)

(Note 7)

(Note 8)

(Note 7)

H

L

Sector Protect

(Note 5)

SADD, A6 = L,

A1 = H, A0 = L

V_ID

Sector

Unprotect

(Note 5)

H

SADD, A6 = H,

A1 = H, A0 = L

V_ID

D_IN

L

H

X

L

X

(Note 6)

X

(Note 8)

(Note 7)

(Note 8)

H

L

H

L

Temporary

Sector

Unprotect

V_ID

D_IN

X

High-Z

D_OUT

High-Z

D_OUT

D_IN

D_OUT

L

H

L

A_IN

Read from pSRAM

Write to pSRAM

H

L

H

L

H

L

H

X

H

L

High-Z

D_IN

L

A_IN

D_IN

X

H

L

High-Z

D_IN

H

High-Z

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 11.5–12.5 V, V_HH= 9.0 ± 0.5 V, X = Don’t Care, SA = pSRAM Address Input, Byte Mode,

SADD = Flash Sector Address, A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Other operations except for those indicated in this column are

inhibited.

5. The sector protect and sector unprotect functions may also be

implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

2. Do not apply CE#f = V_IL, CE1#s = V_ILand CE2s = V_IHat the same

time.

6. If WP#/ACC = V_IL, the two outermost boot sectors remain

protected. If WP#/ACC = V_IH, the two outermost boot sector

protection depends on whether they were last protected or

unprotected using the method described in “Sector/Sector Block

Protection and Unprotection”. If WP#/ACC = V_HH,all sectors will

be unprotected.

3. Don’t care or open LB#s or UB#s.

4. If WP#/ACC = V_IL, the boot sectors will be protected. If WP#/ACC

= V_IHthe boot sectors protection will be removed.

If WP#/ACC = V_ACC(9V), the program time will be reduced by

40%.

7. Data will be retained in pSRAM.

8. Data will be lost in pSRAM.

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Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V_IL

Operation

(Notes 1, 2)

WP#/ACC

(Note 4)

DQ7–

DQ0

DQ15–

DQ8

CE#f CE1#s CE2s OE# WE#

Address

LB#s UB#s RESET#

(Note 7)

(Note 8)

(Note 7)

(Note 8)

H

L

Read from

Flash

A_IN

D_OUT

L

H

L

X

H

L/H

High-Z

H

L

A_IN

D_IN

Write to Flash

Standby

L

H

(Note 4)

V_CC

±

V_CC±

H

L

X

H

High-Z

0.3 V

V_CC

±

V_CC

±

Deep Power-down

Standby

0.3 V

H

X

Output Disable

L

H

L/H

High-Z

D_IN

High-Z

X

(Note 7)

H

L

Flash Hardware

Reset

X

L

X

H

X

L

X

L

(Note 8)

(Note 7)

(Note 8)

(Note 7)

H

L

Sector Protect

(Note 5)

SADD, A6 = L,

A1 = H, A0 = L

V_ID

Sector

Unprotect

(Note 5)

H

SADD, A6 = H,

A1 = H, A0 = L

V_ID

D_IN

L

H

X

L

X

(Note 6)

X

(Note 8)

(Note 7)

(Note 8)

H

L

H

L

Temporary

Sector

Unprotect

V_ID

D_IN

X

High-Z

D_OUT

High-Z

D_OUT

D_IN

D_OUT

L

H

L

A_IN

Read from pSRAM

Write to pSRAM

H

L

H

L

H

L

H

X

H

L

High-Z

D_IN

L

A_IN

D_IN

X

H

L

High-Z

D_IN

H

High-Z

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 11.5–12.5 V, V_HH= 9.0 ± 0.5 V, X = Don’t Care, SA = pSRAM Address Input, Byte Mode,

SADD = Flash Sector Address, A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Other operations except for those indicated in this column are

inhibited.

5. The sector protect and sector unprotect functions may also be

implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

2. Do not apply CE#f = V_IL, CE1#s = V_ILand CE2s = V_IHat the same

time.

6. If WP#/ACC = V_IL, the two outermost boot sectors remain

protected. If WP#/ACC = V_IH, the two outermost boot sector

protection depends on whether they were last protected or

unprotected using the method described in “Sector/Sector Block

Protection and Unprotection”. If WP#/ACC = V_HH,all sectors will

be unprotected.

3. Don’t care or open LB#s or UB#s.

4. If WP#/ACC = V_IL, the boot sectors will be protected. If WP#/ACC

= V_IHthe boot sectors protection will be removed.

If WP#/ACC = V_ACC(9V), the program time will be reduced by

40%.

7. Data will be retained in pSRAM.

8. Data will be lost in pSRAM.

March 8, 2002

Am49DL640BG

11

P R E L I M I N A R Y

An erase operation can erase one sector, multiple sec-

FLASH DEVICE BUS OPERATIONS

tors, or the entire device. Table 3 indicates the address

space that each sector occupies. Similarly, a “sector

address” is the address bits required to uniquely select

a sector. The “Flash Command Definitions” section

has details on erasing a sector or the entire chip, or

suspending/resuming the erase operation.

Word/Byte Configuration

The CIOf pin controls whether the device data I/O pins

operate in the byte or word configuration. If the CIOf

pin is set at logic ‘1’, the device is in word configura-

tion, DQ15–DQ0 are active and controlled by CE#f

and OE#.

The device address space is divided into four banks. A

“bank address” is the address bits required to uniquely

select a bank.

If the CIOf pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ7–DQ0 are

active and controlled by CE#f and OE#. The data I/O

pins DQ14–DQ8 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

I

_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The Flash

AC Characteristics section contains timing specifica-

tion tables and timing diagrams for write operations.

Requirements for Reading Array Data

Accelerated Program Operation

To read array data from the outputs, the system must

drive the CE#f and OE# pins to V_IL. CE#f is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V_IH. The CIOf pin determines

whether the device outputs array data in words or

bytes.

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. Each bank remains

enabled for read access until the command register

contents are altered.

V

_HHfrom the WP#/ACC pin returns the device to nor-

mal operation. Note that V_HHmust not be asserted on

WP#/ACC for operations other than accelerated pro-

gramming, or device damage may result. In addition,

the WP#/ACC pin must not be left floating or uncon-

nected; inconsistent behavior of the device may result.

See “Write Protect (WP#)” on page 19 for related in-

formation.

Refer to the Flash Read-Only Operations table for tim-

ing specifications and to Figure 14 for the timing dia-

gram. I_CC1in the DC Characteristics table represents

the active current specification for reading array data.

Autoselect Functions

Writing Commands/Command Sequences

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ15–DQ0. Standard read cycle timings apply in

this mode. Refer to the Sector/Sector Block Protection

and Unprotection and Autoselect Command Se-

quence sections for more information.

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE#f to V_IL, and OE# to V_IH.

For program operations, the CIOf pin determines

whether the device accepts program data in bytes or

words. Refer to “Flash Device Bus Operations” for

more information.

Simultaneous Read/Write Operations with

Zero Latency

The device features an Unlock Bypass mode to facil-

itate faster programming. Once a bank enters the Un-

lock Bypass mode, only two write cycles are required

to program a word or byte, instead of four. The

“Byte/Word Program Command Sequence” section

has details on programming data to the device using

both standard and Unlock Bypass command se-

quences.

This device is capable of reading data from one bank

of memory while programming or erasing in the other

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

within the same bank (except the sector being

erased). Figure 21 shows how read and write cycles

12

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

may be initiated for simultaneous operation with zero

RESET#: Hardware Reset Pin

latency. I_CC6f and I_CC7f in the table represent the cur-

rent specifications for read-while-program and

read-while-erase, respectively.

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE#f and RESET# pins are both held at V_CC± 0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE#f and RESET# are held at V_IH, but not

within V_CC± 0.3 V, the device will be in the standby

mode, but the standby current will be greater. The de-

vice requires standard access time (t_CE) for read ac-

cess when the device is in either of these standby

modes, before it is ready to read data.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS±0.3 V, the device

draws CMOS standby current (I_CC4f). If RESET# is

held at V_ILbut not within V_SS±0.3 V, the standby cur-

rent will be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The

system can thus monitor RY/BY# to determine

whether the reset operation is complete. If RESET# is

asserted when a program or erase operation is not ex-

ecuting (RY/BY# pin is “1”), the reset operation is com-

pleted within a time of t_READY(not during Embedded

Algorithms). The system can read data t_RHafter the

RESET# pin returns to V_IH.

I_CC3f in the table represents the standby current spec-

ification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t_ACC

+

30 ns. The automatic sleep mode is independent of

the CE#f, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

Refer to the pSRAM AC Characteristics tables for RE-

SET# parameters and to Figure 15 for the timing dia-

gram.

I_CC5f in the table represents the automatic sleep mode

current specification.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

March 8, 2002

Am49DL640BG

13

P R E L I M I N A R Y

Table 3. Am29DL640G Sector Architecture

Sector Address

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Bank

Sector

A21–A12

Address Range

SA0

SA1

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001xxx

0000010xxx

0000011xxx

0000100xxx

0000101xxx

0000110xxx

0000111xxx

0001000xxx

0001001xxx

0001010xxx

0001011xxx

0001100xxx

0001101xxx

0001111xxx

8/4

000000h–001FFFh

002000h–003FFFh

004000h–005FFFh

006000h–007FFFh

008000h–009FFFh

00A000h–00BFFFh

00C000h–00DFFFh

00E000h–00FFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

00000h–00FFFh

01000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–04FFFh

05000h–05FFFh

06000h–06FFFh

07000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

SA2

8/4

SA3

8/4

SA4

8/4

SA5

8/4

SA6

8/4

SA7

8/4

SA8

64/32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

Bank 1

14

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

Table 3. Am29DL640G Sector Architecture (Continued)

Sector Address

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Bank

Sector

A21–A12

Address Range

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

0010000xxx

0010001xxx

0010010xxx

0010011xxx

0010100xxx

0010101xxx

0010110xxx

0010111xxx

0011000xxx

0011001xxx

0011010xxx

0011011xxx

0011000xxx

0011101xxx

0011110xxx

0011111xxx

0100000xxx

0100001xxx

0100010xxx

0101011xxx

0100100xxx

0100101xxx

0100110xxx

0100111xxx

0101000xxx

0101001xxx

0101010xxx

0101011xxx

0101100xxx

0101101xxx

0101110xxx

0101111xxx

0110000xxx

0110001xxx

0110010xxx

0110011xxx

0100100xxx

0110101xxx

0110110xxx

0110111xxx

0111000xxx

0111001xxx

0111010xxx

0111011xxx

0111100xxx

0111101xxx

0111110xxx

0111111xxx

64/32

100000h–00FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

1A0000h–1AFFFFh

1B0000h–1BFFFFh

1C0000h–1CFFFFh

1D0000h–1DFFFFh

1E0000h–1EFFFFh

1F0000h–1FFFFFh

200000h–20FFFFh

210000h–21FFFFh

220000h–22FFFFh

230000h–23FFFFh

240000h–24FFFFh

250000h–25FFFFh

260000h–26FFFFh

270000h–27FFFFh

280000h–28FFFFh

290000h–29FFFFh

2A0000h–2AFFFFh

2B0000h–2BFFFFh

2C0000h–2CFFFFh

2D0000h–2DFFFFh

2E0000h–2EFFFFh

2F0000h–2FFFFFh

300000h–30FFFFh

310000h–31FFFFh

320000h–32FFFFh

330000h–33FFFFh

340000h–34FFFFh

350000h–35FFFFh

360000h–36FFFFh

370000h–37FFFFh

380000h–38FFFFh

390000h–39FFFFh

3A0000h–3AFFFFh

3B0000h–3BFFFFh

3C0000h–3CFFFFh

3D0000h–3DFFFFh

3E0000h–3EFFFFh

3F0000h–3FFFFFh

80000h–87FFFh

88000h–8FFFFh

90000h–97FFFh

98000h–9FFFFh

A0000h–A7FFFh

A8000h–AFFFFh

B0000h–B7FFFh

B8000h–BFFFFh

C0000h–C7FFFh

C8000h–CFFFFh

D0000h–D7FFFh

D8000h–DFFFFh

E0000h–E7FFFh

E8000h–EFFFFh

F0000h–F7FFFh

F8000h–FFFFFh

F9000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

Bank 2

March 8, 2002

Am49DL640BG

15

P R E L I M I N A R Y

Table 3. Am29DL640G Sector Architecture (Continued)

Sector Address

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Bank

Sector

A21–A12

Address Range

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

1000000xxx

1000001xxx

1000010xxx

1000011xxx

1000100xxx

1000101xxx

1000110xxx

1000111xxx

1001000xxx

1001001xxx

1001010xxx

1001011xxx

1001100xxx

1001101xxx

1001110xxx

1001111xxx

1010000xxx

1010001xxx

1010010xxx

1010011xxx

1010100xxx

1010101xxx

1010110xxx

1010111xxx

1011000xxx

1011001xxx

1011010xxx

1011011xxx

1011100xxx

1011101xxx

1011110xxx

1011111xxx

1100000xxx

1100001xxx

1100010xxx

1100011xxx

1100100xxx

1100101xxx

1100110xxx

1100111xxx

1101000xxx

1101001xxx

1101010xxx

1101011xxx

1101100xxx

1101101xxx

1101110xxx

1101111xxx

64/32

400000h–40FFFFh

410000h–41FFFFh

420000h–42FFFFh

430000h–43FFFFh

440000h–44FFFFh

450000h–45FFFFh

460000h–46FFFFh

470000h–47FFFFh

480000h–48FFFFh

490000h–49FFFFh

4A0000h–4AFFFFh

4B0000h–4BFFFFh

4C0000h–4CFFFFh

4D0000h–4DFFFFh

4E0000h–4EFFFFh

4F0000h–4FFFFFh

500000h–50FFFFh

510000h–51FFFFh

520000h–52FFFFh

530000h–53FFFFh

540000h–54FFFFh

550000h–55FFFFh

560000h–56FFFFh

570000h–57FFFFh

580000h–58FFFFh

590000h–59FFFFh

5A0000h–5AFFFFh

5B0000h–5BFFFFh

5C0000h–5CFFFFh

5D0000h–5DFFFFh

5E0000h–5EFFFFh

5F0000h–5FFFFFh

600000h–60FFFFh

610000h–61FFFFh

620000h–62FFFFh

630000h–63FFFFh

640000h–64FFFFh

650000h–65FFFFh

660000h–66FFFFh

670000h–67FFFFh

680000h–68FFFFh

690000h–69FFFFh

6A0000h–6AFFFFh

6B0000h–6BFFFFh

6C0000h–6CFFFFh

6D0000h–6DFFFFh

6E0000h–6EFFFFh

6F0000h–6FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–28FFFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2FFFFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

Bank 3

16

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

Table 3. Am29DL640G Sector Architecture (Continued)

Sector Address

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Bank

Sector

A21–A12

Address Range

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

1110000xxx

1110001xxx

1110010xxx

1110011xxx

1110100xxx

1110101xxx

1110110xxx

1110111xxx

1111000xxx

1111001xxx

1111010xxx

1111011xxx

1111100xxx

1111101xxx

1111110xxx

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

64/32

8/4

700000h–70FFFFh

710000h–71FFFFh

720000h–72FFFFh

730000h–73FFFFh

740000h–74FFFFh

750000h–75FFFFh

760000h–76FFFFh

770000h–77FFFFh

780000h–78FFFFh

790000h–79FFFFh

7A0000h–7AFFFFh

7B0000h–7BFFFFh

7C0000h–7CFFFFh

7D0000h–7DFFFFh

7E0000h–7EFFFFh

7F0000h–7F1FFFh

7F2000h–7F3FFFh

7F4000h–7F5FFFh

7F6000h–7F7FFFh

7F8000h–7F9FFFh

7FA000h–7FBFFFh

7FC000h–7FDFFFh

7FE000h–7FFFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3F8FFFh

3F9000h–3F9FFFh

3FA000h–3FAFFFh

3FB000h–3FBFFFh

3FC000h–3FCFFFh

3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

Bank 4

8/4

Note: The address range is A21:A-1 in byte mode (CIOf=V_IL) or A21:A0 in word mode (CIOf=V_IH).

Table 4. Bank Address

Bank

A21–A19

000

1

2

3

4

001, 010, 011

100, 101, 110

111

Table 5. SecSi Sector Addresses

(x8)

(x16)

Device

Am29DL640G

Sector Size

Address Range

256 bytes

000000h–0000FFh

00000h–0007Fh

March 8, 2002

Am49DL640BG

17

P R E L I M I N A R Y

Sector/Sector Block Protection and

Unprotection

Sector/

Sector Block Size

Sector

A21–A12

SA63–SA66

SA67–SA70

SA71–SA74

SA75–SA78

SA79–SA82

SA83–SA86

SA87–SA90

SA91–SA94

SA95–SA98

SA99–SA102

SA103–SA106

SA107–SA110

SA111–SA114

SA115–SA118

SA119–SA122

SA123–SA126

SA127–SA130

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

256 (4x64) Kbytes

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Table

6).

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both pro-

gram and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

Table 6. Am29DL640G Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector/

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

A21–A12

Sector Block Size

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

8 Kbytes

1111100XXX,

1111101XXX,

1111110XXX

8 Kbytes

SA131–SA133

192 (3x64) Kbytes

8 Kbytes

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111111

8 Kbytes

0000001XXX,

0000010XXX,

0000011XXX,

SA8–SA10

192 (3x64) Kbytes

SA11–SA14

SA15–SA18

SA19–SA22

SA23–SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51-SA54

SA55–SA58

SA59–SA62

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

256 (4x64) Kbytes

The primary method requires V_IDon the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 2 shows the algo-

rithms and Figure 26 shows the timing diagram. This

method uses standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sectors must

first be protected prior to the first sector unprotect write

cycle. Note that the sector unprotect algorithm unpro-

tects all sectors in parallel. All previously protected

sectors must be individually re-protected. To change

data in protected sectors efficiently, the temporary

sector unprotect function is available. See “Temporary

Sector Unprotect”.

18

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

The alternate method intended only for programming

Temporary Sector Unprotect

equipment requires V_IDon address pin A9 and OE#.

This method is compatible with programmer routines

written for earlier 3.0 volt-only AMD flash devices.

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Table

6).

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID. During this mode, formerly protected

sectors can be programmed or erased by selecting the

sector addresses. Once V_IDis removed from the RE-

SET# pin, all the previously protected sectors are

protected again. Figure 1 shows the algorithm, and

Figure 25 shows the timing diagrams, for this feature.

If the WP#/ACC pin is at V_IL, sectors 0, 1, 140, and

141 will remain protected during the Temporary sector

Unprotect mode.

It is possible to determine whether a sector is pro-

tected or unprotected. See the Sector/Sector Block

Protection and Unprotection section for details.

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting without using V_ID. This function is

one of two provided by the WP#/ACC pin.

If the system asserts V_ILon the WP#/ACC pin, the de-

vice disables program and erase functions in sectors

0, 1, 140, and 141, independently of whether those

sectors were protected or unprotected using the

method described in “Sector/Sector Block Protection

and Unprotection”.

START

If the system asserts V_IHon the WP#/ACC pin, the de-

vice reverts to whether sectors 0, 1, 140, and 141

were last set to be protected or unprotected. That is,

sector protection or unprotection for these sectors de-

pends on whether they were last protected or unpro-

tected using the method described in “Sector/Sector

Block Protection and Unprotection”.

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

Note that the WP#/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may

result.

RESET# = V_IH

Table 7. WP#/ACC Modes

Temporary Sector

Unprotect Completed

(Note 2)

Device

Mode

WP# Input

Voltage

Disables programming and erasing in

SA0, SA1, SA140, and SA141

V_IL

Enables programming and erasing in

SA0, SA1, SA140, and SA141

Notes:

V_IH

1. All protected sectors unprotected (If WP#/ACC = V_IL,

sectors 0, 1, 140, and 141 will remain protected).

Enables accelerated progamming (ACC).

See “Accelerated Program Operation” on

page 12.

V_HH

2. All previously protected sectors are protected once

again.

Figure 1. Temporary Sector Unprotect Operation

March 8, 2002

Am49DL640BG

19

P R E L I M I N A R Y

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 µs

unprotect address

No

First Write

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Cycle = 60h?

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protect/Unprotect Algorithms

20

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

Customers may opt to have their code programmed by

SecSi™ (Secured Silicon) Sector

AMD through the AMD ExpressFlash service. AMD

programs the customer’s code, with or without the ran-

dom ESN. The devices are then shipped from AMD’s

factory with the SecSi Sector permanently locked.

Contact an AMD representative for details on using

AMD’s ExpressFlash service.

Flash Memory Region

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 256 bytes in length, and

uses a SecSi Sector Indicator Bit (DQ7) to indicate

whether or not the SecSi Sector is locked when

shipped from the factory. This bit is permanently set at

the factory and cannot be changed, which prevents

cloning of a factory locked part. This ensures the secu-

rity of the ESN once the product is shipped to the field.

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

If the security feature is not required, the SecSi Sector

can be treated as an additional Flash memory space.

The SecSi Sector can be read any number of times,

but can be programmed and locked only once. Note

that the accelerated programming (ACC) and unlock

bypass functions are not available when programming

the SecSi Sector.

AMD offers the device with the SecSi Sector either

factory locked or customer lockable. The fac-

tory-locked version is always protected when shipped

from the factory, and has the SecSi (Secured Silicon)

Sector Indicator Bit permanently set to a “1.” The cus-

tomer-lockable version is shipped with the SecSi Sec-

tor unprotected, allowing customers to utilize the that

sector in any manner they choose. The customer-lock-

able version has the SecSi (Secured Silicon) Sector

Indicator Bit permanently set to a “0.” Thus, the SecSi

Sector Indicator Bit prevents customer-lockable de-

vices from being used to replace devices that are fac-

tory locked.

The SecSi Sector area can be protected using one of

the following procedures:

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, ex-

cept that RESET# may be at either V_IHor V_ID. This

allows in-system protection of the SecSi Sector Re-

gion without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

The system accesses the SecSi Sector Secure

through a command sequence (see “Enter SecSi™

Sector/Exit SecSi Sector Command Sequence”). After

the system has written the Enter SecSi Sector com-

mand sequence, it may read the SecSi Sector by

using the addresses normally occupied by the boot

sectors. This mode of operation continues until the

system issues the Exit SecSi Sector command se-

quence, or until power is removed from the device. On

power-up, or following a hardware reset, the device re-

verts to sending commands to the first 256 bytes of

Sector 0.

■ Write the three-cycle Enter SecSi Sector Secure

Region command sequence, and then use the alter-

nate method of sector protection described in the

“Sector/Sector Block Protection and Unprotection”

section.

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region com-

mand sequence to return to reading and writing the

remainder of the array.

The SecSi Sector lock must be used with caution

since, once locked, there is no procedure available for

unlocking the SecSi Sector area and none of the bits

in the SecSi Sector memory space can be modified in

any way.

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

In a factory locked device, the SecSi Sector is pro-

tected when the device is shipped from the factory.

The SecSi Sector cannot be modified in any way. The

device is preprogrammed with both a random number

and a secure ESN. The 8-word random number will at

addresses 000000h–000007h in word mode (or

000000h–00000Fh in byte mode). The secure ESN

will be programmed in the next 8 words at addresses

000008h–00000Fh (or 000010h–000020h in byte

mode). The device is available preprogrammed with

one of the following:

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 12 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

spurious system level signals during V_CCpower-up

and power-down transitions, or from system noise.

■ A random, secure ESN only

Low V_CCWrite Inhibit

■ Customer code through the ExpressFlash service

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

■ Both a random, secure ESN and customer code

through the ExpressFlash service.

March 8, 2002

Am49DL640BG

21

P R E L I M I N A R Y

power-up and power-down. The command register

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V_CCis greater than V_LKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when V_CCis

greater than V_LKO

.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The

system can read CFI information at the addresses

given in Tables 8–11. To terminate reading CFI data,

the system must write the reset command.The CFI

Query mode is not accessible when the device is exe-

cuting an Embedded Program or embedded Erase al-

gorithm.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#f

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE#f = V_IHor WE# = V_IH. To initiate a write cycle,

CE#f and WE# must be a logical zero while OE# is a

logical one.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 8–11. The

system must write the reset command to return the de-

vice to the autoselect mode.

Power-Up Write Inhibit

If WE# = CE#f = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the

World Wide Web at http://www.amd.com/prod-

ucts/nvd/overview/cfi.html. Alternatively, contact an

AMD representative for copies of these documents.

COMMON FLASH MEMORY INTERFACE

(CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

Table 8. CFI Query Identification String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

22

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

Table 9. System Interface String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

V_CCMin. (write/erase)

0027h

1Bh

1Ch

36h

38h

D7–D4: volt, D3–D0: 100 millivolt

V_CCMax. (write/erase)

0036h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V

_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 10. Device Geometry Definition

Addresses

(Word Mode)

(Byte Mode)

Data

Description

27h

4Eh

0017h

Device Size = 2^Nbyte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ch

58h

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

007Dh

0000h

0001h

Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

March 8, 2002

Am49DL640BG

23

P R E L I M I N A R Y

Table 11. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

(Byte Mode)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0033h

Major version number, ASCII (reflects modifications to the silicon)

Minor version number, ASCII (reflects modifications to the CFI table)

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

8Ah

0004h

Silicon Revision Number (Bits 7-2)

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

8Ch

8Eh

90h

0002h

0001h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

49h

92h

0004h

0077h

01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800

mode

Simultaneous Operation

00 = Not Supported, X = Number of Sectors (excluding Bank 1)

4Ah

4Bh

4Ch

94h

96h

98h

Burst Mode Type

00 = Not Supported, 01 = Supported

0000h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

9Ah

9Ch

0085h

0095h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom Boot

with Write Protect, 02h = Bottom Boot Device, 03h = Top Boot Device,

04h = Both Top and Bottom

4Fh

9Eh

0001h

Program Suspend

50h

57h

58h

59h

5Ah

5Bh

A0h

AEh

B0h

B2h

B4h

B6h

0001h

0004h

0017h

0030h

0017h

0 = Not supported, 1 = Supported

Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

Bank 1 Region Information

X = Number of Sectors in Bank 1

Bank 2 Region Information

X = Number of Sectors in Bank 2

Bank 3 Region Information

X = Number of Sectors in Bank 3

Bank 4 Region Information

X = Number of Sectors in Bank 4

24

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

FLASH COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 12 defines the valid register command

sequences. Writing incorrect address and data val-

ues or writing them in the improper sequence resets

the device to reading array data.

which the system was writing to the read mode. If the

program command sequence is written to a bank that

is in the Erase Suspend mode, writing the reset

command returns that bank to the erase-sus-

pend-read mode. Once programming begins, how-

ever, the device ignores reset commands until the

operation is complete.

All addresses are latched on the falling edge of WE#

or CE#f, whichever happens later. All data is latched

on the rising edge of WE# or CE#f, whichever hap-

pens first. Refer to the pSRAM AC Characteristics

section for timing diagrams.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If a bank

entered the autoselect mode while in the Erase Sus-

pend mode, writing the reset command returns that

bank to the erase-suspend-read mode.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the banks to the

read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read

data from any non-erase-suspended sector within the

same bank. The system can read array data using the

standard read timing, except that if it reads at an ad-

dress within erase-suspended sectors, the device out-

puts status data. After completing a programming

operation in the Erase Suspend mode, the system

may once again read array data with the same excep-

tion. See the Erase Suspend/Erase Resume Com-

mands section for more information.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

The autoselect command sequence may be written to

an address within a bank that is either in the read or

erase-suspend-read mode. The autoselect command

may not be written while the device is actively pro-

gramming or erasing in the other bank.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the au-

toselect command. The bank then enters the autose-

lect mode. The system may read any number of

autoselect codes without reinitiating the command se-

quence.

The system must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase opera-

tion, or if the bank is in the autoselect mode. See the

next section, Reset Command, for more information.

See also Requirements for Reading Array Data in the

section for more information. The Flash Read-Only

Operations table provides the read parameters, and

Figure 14 shows the timing diagram.

Table 12 shows the address and data requirements.

To determine sector protection information, the system

must write to the appropriate bank address (BA) and

sector address (SADD). Table 3 shows the address

range and bank number associated with each sector.

Reset Command

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure be-

gins, however, the device ignores reset commands

until the operation is complete.

The SecSi Sector region provides a secured data area

containing a random, sixteen-byte electronic serial

number (ESN). The system can access the SecSi

Sector region by issuing the three-cycle Enter SecSi

Sector command sequence. The device continues to

access the SecSi Sector region until the system is-

sues the four-cycle Exit SecSi Sector command se-

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the bank to

March 8, 2002

Am49DL640BG

25

P R E L I M I N A R Y

quence. The Exit SecSi Sector command sequence

Unlock Bypass Command Sequence

returns the device to normal operation. The SecSi

Sector is not accessible when the device is executing

an Embedded Program or embedded Erase algorithm.

Table 12 shows the address and data requirements for

both command sequences. See also “SecSi™ (Se-

cured Silicon) Sector Flash Memory Region” for further

information.

The unlock bypass feature allows the system to pro-

gram bytes or words to a bank faster than using the

standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write

cycle containing the unlock bypass command, 20h.

That bank then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

with the initial two unlock cycles required in the stan-

dard program command sequence, resulting in faster

total programming time. Table 12 shows the require-

ments for the command sequence.

Byte/Word Program Command Sequence

The system may program the device by word or byte,

depending on the state of the CIOf pin. Programming

is a four-bus-cycle operation. The program command

sequence is initiated by writing two unlock write cy-

cles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or

timings. The device automatically provides internally

generated program pulses and verifies the pro-

grammed cell margin. Table 12 shows the address

and data requirements for the byte program command

sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the bank

address and the data 90h. The second cycle need

only contain the data 00h. The bank then returns to

the read mode.

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. Refer to the Flash Write Oper-

ation Status section for information on these status

bits.

The device offers accelerated program operations

through the WP#/ACC pin. When the system asserts

V

_HHon the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at V_HHany operation

other than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin must not

be left floating or unconnected; inconsistent behavior

of the device may result.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once that bank has returned to the read

mode, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and

DQ6 status bits to indicate the operation was success-

ful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a

“0” to a “1.”

Figure 3 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 18 for timing diagrams.

26

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once that bank has returned to reading

array data, to ensure data integrity.

START

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 20 section for timing diagrams.

Write Program

Command Sequence

Data Poll

from System

Sector Erase Command Sequence

Embedded

Program

algorithm

in progress

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 12 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

Verify Data?

Yes

No

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

Increment Address

Last Address?

Yes

Programming

Completed

After the command sequence is written, a sector erase

time-out of 80 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 80

µs, otherwise erasure may begin. Any sector erase

address and command following the exceeded

time-out may or may not be accepted. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector

Erase command is written. Any command other than

Sector Erase or Erase Suspend during the

time-out period resets that bank to the read mode.

The system must rewrite the command sequence and

any additional addresses and commands.

Note: See Table 12 for program command sequence.

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 12

shows the address and data requirements for the chip

erase command sequence.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. Refer to the Flash Write Operation Status

section for information on these status bits.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing bank. The system can de-

termine the status of the erase operation by reading

March 8, 2002

Am49DL640BG

27

P R E L I M I N A R Y

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank.

Refer to the Flash Write Operation Status section for

information on these status bits.

Refer to the Flash Write Operation Status section for

more information.

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. The device

allows reading autoselect codes even at addresses

within erasing sectors, since the codes are not stored

in the memory array. When the device exits the au-

toselect mode, the device reverts to the Erase Sus-

pend mode, and is ready for another valid operation.

Refer to the Sector/Sector Block Protection and Un-

protection and Autoselect Command Sequence sec-

tions for details.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 20 section for timing diagrams.

To resume the sector erase operation, the system

must write the Erase Resume command (address bits

are don’t care). The bank address of the erase-sus-

pended bank is required when writing this command.

Further writes of the Resume command are ignored.

Another Erase Suspend command can be written after

the chip has resumed erasing.

Erase Suspend/Erase Resume

Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. The bank address is required when writing

this command. This command is valid only during the

sector erase operation, including the 80 µs time-out

period during the sector erase command sequence.

The Erase Suspend command is ignored if written dur-

ing the chip erase operation or Embedded Program

algorithm.

START

Write Erase

Command Sequence

(Notes 1, 2)

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation. Addresses are “don’t-cares” when

writing the Erase suspend command.

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors pro-

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

Refer to the Flash Write Operation Status section for

information on these status bits.

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 12 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard Byte Program operation.

Figure 4. Erase Operation

28

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

Table 12. Am29DL640G Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Addr

Sixth

Addr

Addr Data Addr Data

Data

Addr

Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

RD

F0

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

(BA)555

(BA)AAA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

Manufacturer ID

4

6

4

AA

55

90

(BA)X00

01

7E

AAA

555

(BA)X01

(BA)X02

(BA)X03

(BA)X06

(BA)X0E

(BA)X1C

(BA)X0F

(BA)X1E

Device ID (Note 9)

02

01

AAA

555

SecSi Sector Factory

Protect (Note 10)

80/00

AAA

(SADD)

X02

Word

Byte

555

2AA

555

(BA)555

(BA)AAA

Sector/Sector Block

Protect Verify

(Note 11)

4

AA

55

90

00/01

(SADD)

X04

AAA

Word

Byte

Word

Byte

Word

Byte

Word

Byte

555

AAA

555

AAA

555

AAA

555

AAA

XXX

BA

2AA

555

2AA

555

2AA

555

2AA

555

PA

555

AAA

555

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

3

4

3

AA

55

88

90

A0

20

XXX

PA

00

AAA

555

PD

AAA

555

Unlock Bypass

AAA

Unlock Bypass Program (Note 12)

Unlock Bypass Reset (Note 13)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

BA

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

Byte

6

AA

55

80

AA

55

10

30

AAA

Word

Sector Erase

Byte

SADD

AAA

Erase Suspend (Note 14)

Erase Resume (Note 15)

1

B0

30

BA

Word

CFI Query (Note 16)

Byte

55

1

98

AA

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE#f pulse, whichever happens first.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses

latch on the falling edge of the WE# or CE#f pulse, whichever happens

later.

SADD = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A21–A12 uniquely select any sector. Refer to

Table 3 for information on sector addresses.

BA = Address of the bank that is being switched to autoselect mode, is

in bypass mode, or is being erased. Address bits A21–A19 select a

bank. Refer to Table 4 for information on sector addresses.

Notes:

1. See Tables 1–2 for description of bus operations.

9. The device ID must be read across the fourth, fifth, and sixth

cycles.

2. All values are in hexadecimal.

10. The data is 80h for factory locked and 00h for not factory locked.

11. The data is 00h for an unprotected sector/sector block and 01h

for a protected sector/sector block.

12. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences,

except for RD and PD.

5. Unless otherwise noted, address bits A21–A12 are don’t cares for

unlock and command cycles, unless SADD or PA is required.

6. No unlock or command cycles required when bank is reading

array data.

13. The Unlock Bypass Reset command is required to return to the

read mode when the bank is in the unlock bypass mode.

14. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation, and requires the bank address.

15. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

16. Command is valid when device is ready to read array data or when

device is in autoselect mode.

7. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when a bank is in the autoselect mode, or if DQ5 goes high (while

the bank is providing status information).

8. The fourth cycle of the autoselect command sequence is a read

cycle. The system must provide the bank address to obtain the

manufacturer ID, device ID, or SecSi Sector factory protect

information. Data bits DQ15–DQ8 are don’t care. See the

Autoselect Command Sequence section for more information.

March 8, 2002

Am49DL640BG

29

P R E L I M I N A R Y

the status or valid data. Even if the device has com-

FLASH WRITE OPERATION STATUS

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ15–DQ0 may be still

invalid. Valid data on DQ15–DQ0 (or DQ7–DQ0 for

byte mode) will appear on successive read cycles.

The device provides several bits to determine the status of

a program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 13 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method

for determining whether a program or erase operation is

complete or in progress. The device also provides a hard-

ware-based output signal, RY/BY#, to determine whether

an Embedded Program or Erase operation is in progress or

has been completed.

Table 13 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm. Figure 22

in the pSRAM AC Characteristics section shows the

Data# Polling timing diagram.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether a bank is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the final

WE# pulse in the command sequence.

START

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, then that bank returns to the

read mode.

Yes

DQ7 = Data?

No

DQ5 = 1?

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Yes

Read DQ7–DQ0

Addr = VA

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then

the bank returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ15–DQ0 (or DQ7–DQ0 for byte mode) on the fol-

lowing read cycles. Just prior to the completion of an

Embedded Program or Erase operation, DQ7 may

change asynchronously with DQ15–DQ8 (DQ7–DQ0

in byte mode) while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

30

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

DQ6 also toggles during the erase-suspend-program

RY/BY#: Ready/Busy#

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

Table 13 shows the outputs for Toggle Bit I on DQ6.

Figure 6 shows the toggle bit algorithm. Figure 23 in

the “Flash AC Characteristics” section shows the tog-

gle bit timing diagrams. Figure 24 shows the differ-

ences between DQ2 and DQ6 in graphical form. See

also the subsection on DQ2: Toggle Bit II.

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or one of the banks is in the erase-sus-

pend-read mode.

START

Read Byte

(DQ7–DQ0)

Address =VA

Table 13 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

Read Byte

(DQ7–DQ0)

Address =VA

No

Toggle Bit

= Toggle?

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE#f to control the read cycles. When the operation is

complete, DQ6 stops toggling.

Yes

No

DQ5 = 1?

Yes

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are pro-

tected.

Read Byte Twice

(DQ7–DQ0)

Address = VA

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase Sus-

pend mode, DQ6 stops toggling. However, the system

must also use DQ2 to determine which sectors are

erasing or erase-suspended. Alternatively, the system

can use DQ7 (see the subsection on DQ7: Data# Poll-

ing).

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

Figure 6. Toggle Bit Algorithm

March 8, 2002

Am49DL640BG

31

P R E L I M I N A R Y

not gone high. The system may continue to monitor

DQ2: Toggle Bit II

the toggle bit and DQ5 through successive read cy-

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 6).

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ5: Exceeded Timing Limits

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE#f to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 13 to compare out-

puts for DQ2 and DQ6.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a “1,” indicating that the program

or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit

has been exceeded, DQ5 produces a “1.”

Figure 6 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the DQ6: Toggle Bit I subsection.

Figure 23 shows the toggle bit timing diagram. Figure

24 shows the differences between DQ2 and DQ6 in

graphical form.

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if a bank was previ-

ously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

Reading Toggle Bits DQ6/DQ2

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the time between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also the Sector Erase Command

Sequence section.

Refer to Figure 6 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ15–DQ0 (or DQ7–DQ0 for byte

mode) at least twice in a row to determine whether a

toggle bit is toggling. Typically, the system would note

and store the value of the toggle bit after the first read.

After the second read, the system would compare the

new value of the toggle bit with the first. If the toggle

bit is not toggling, the device has completed the pro-

gram or erase operation. The system can read array

data on DQ15–DQ0 (or DQ7–DQ0 for byte mode) on

the following read cycle.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

Table 13 shows the status of DQ3 relative to the other

status bits.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

32

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

Table 13. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

Erase-Suspend-

Read

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

March 8, 2002

Am49DL640BG

33

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C

20 ns

Ambient Temperature

with Power Applied . . . . . . . . . . . . . . –40°C to +85°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V_CCf, V_CCs (Note 1). . . . . . . . . . . .–0.5 V to +4.0 V

RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V

WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1). . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

20 ns

Figure 7. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

See Figure 7. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 8.

20 ns

V_CC

+2.0 V

2. Minimum DC input voltage on pins RESET#, and

WP#/ACC is –0.5 V. During voltage transitions,

WP#/ACC, and RESET# may overshoot V_SSto –2.0 V

for periods of up to 20 ns. See Figure 7. Maximum DC

input voltage on pin RESET# is +12.5 V which may

overshoot to +14.0 V for periods up to 20 ns. Maximum

DC input voltage on WP#/ACC is +9.5 V which may

overshoot to +12.0 V for periods up to 20 ns.

V_CC

+0.5 V

2.0 V

20 ns

Figure 8. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

V_CCf/V_CCs Supply Voltages

V_CCf/V_CCs for standard voltage range . .2.7 V to 3.3 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

34

Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

FLASH DC CHARACTERISTICS

CMOS Compatible

Parameter

Parameter Description

Symbol

Test Conditions

Min

Typ

Max

Unit

V_IN= V_SSto V_CC

V_CC= V_{CC max}

,

I_LI

Input Load Current

±1.0

35

µA

I_LIT

I_LO

RESET# Input Load Current

Output Leakage Current

V_CC= V_{CC max}; RESET# = 12.5 V

V

_OUT= V_SSto V_CC

_CC= V_{CC max}

,

±1.0

V_CC= V_{CC max}, WP#/ACC

= V_{ACC max}

I_LIA

ACC Input Leakage Current

35

µA

5 MHz

1 MHz

5 MHz

1 MHz

10

2

16

4

CE#f = V_IL, OE# = V_IH

Byte Mode

,

Flash V_CCActive Read Current

(Notes 1, 2)

I_CC1f

mA

10

2

16

4

CE#f = V_IL, OE# = V_IH

Word Mode

,

I_CC2

f

Flash V_CCActive Write Current (Notes 2, 3) CE#f = V_IL, OE# = V_IH, WE# = V_IL

15

30

mA

µA

V

_CCf = V_{CC max}, CE#f, RESET#,

I

_CC3f

Flash V_CCStandby Current (Note 2)

Flash V_CCReset Current (Note 2)

0.2

5

WP#/ACC = V_CCf ± 0.3 V

V_CCf = V_{CC max}, RESET# = V_SS± 0.3 V,

WP#/ACC = V_CCf ± 0.3 V

_CC4f

µA

Flash V_CCCurrent Automatic Sleep Mode V_CCf = V_{CC max}, V_IH= V_CC± 0.3 V;

_CC5f

(Notes 2, 4)

V_IL= V_SS± 0.3 V

Byte

Word

Byte

21

45

Flash V_CCActive Read-While-Program

Current (Notes 1, 2)

I

_CC6f

CE#f = V_IL, OE# = V_IH

mA

Flash V_CCActive Read-While-Erase

Current (Notes 1, 2)

I_CC7f

CE#f = V_IL, OE# = V_IH

Word

Flash V_CCActive

I_CC8f

Program-While-Erase-Suspended Current CE#f = V_IL, OE#f = V_IH

(Notes 2, 5)

17

35

mA

ACC pin

V_CCpin

5

10

30

mA

V

ACC Accelerated Program Current,

CE#f = V_IL, OE# = V_IH

Word or Byte

I_ACC

15

V_IL

V_IH

Input Low Voltage

Input High Voltage

–0.2

0.8

V

_CC+ 0.2

2.4

V

Voltage for WP#/ACC Program

Acceleration and Sector

Protection/Unprotection

V_HH

8.5

9.5

V

Voltage for Sector Protection, Autoselect

and Temporary Sector Unprotect

V_ID

V_OL

11.5

12.5

0.45

V

Output Low Voltage

I_OL= 4.0 mA, V_CCf = V_CCs = V_{CC min}

I_OH= –2.0 mA, V_CCf = V_CCs = V_{CC min}

I_OH= –100 µA, V_CC= V_{CC min}

0.85 x

V_CC

V_OH1

Output High Voltage

V

V_OH2

V_LKO

V_CC–0.4

Flash Low V_CCLock-Out Voltage (Note 5)

2.3

2.5

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at

V_IH

4. Automatic sleep mode enables the low power mode when

addresses remain stable for t_ACC+ 30 ns. Typical sleep mode

current is 200 nA.

.

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

5. Not 100% tested.

3. I_CCactive while Embedded Erase or Embedded Program is in

progress.

March 8, 2002

Am49DL640BG

35

P R E L I M I N A R Y

pSRAM DC & OPERATING CHARACTERISTICS

Parameter

Symbol

Parameter Description

Input Leakage Current

Output Leakage Current

Test Conditions

V_IN= V_SSto V_CC

Min

–1.0

Typ

Max

1.0

Unit

µA

I_LI

CE1#s = V_IH, CE2s = V_ILor OE# = V_IHor

WE# = V_IL, V_IO= V_SSto V_CC

I_LO

1.0

µA

Cycle time = Min., I_IO= 0 mA, 100% duty,

CE1#s = V_IL, CE2s = V_IH, V_IN= V_IL= or V_IH,

I

_CC1s

Operating Current

40

mA

t

_RC= Min.

Cycle time = Min., I_IO= 0 mA, 100% duty,

CE1#s = V_IL, CE2s = V_IH, V_IN= V_IL= or V_IH,

t_PC= Min.

Page Access Operating

Current

_CC2s

V_OL

25

Output Low Voltage

I_OL= 1.0 mA

0.4

V

V_OH

I_SB

Output High Voltage

Standby Current (CMOS)

I_OH= –0.5 mA

2

CE#1 = V_CCS– 0.2 V, CE2 = V_CCS– 0.2 V

70

5

µA

I_DSB

Deep Power-down Standby CE2 = 0.2 V

Input Low Voltage

–0.3

(Note 1)

V_IL

V_IH

0.4

V

V_CC

0.3

+

Input High Voltage

2.4

(Note 2)

Notes:

1. V_CC– 1.0 V for a 10 ns pulse width.

2. V_CC+ 1.0 V for a 10 ns pulse width.

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Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

FLASH DC CHARACTERISTICS

Zero-Power Flash

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

12

10

8

3.3 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I_CC1vs. Frequency

March 8, 2002

Am49DL640BG

37

P R E L I M I N A R Y

TEST CONDITIONS

Table 14. Test Specifications

3.3 V

Test Condition

70, 85

Unit

Output Load

1 TTL gate

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

pF

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

C

L

6.2 kΩ

0.0–3.0

Input timing measurement

reference levels

1.5

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

Figure 11. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Changing, State Unknown

Does Not Apply

Center Line is High Impedance State (High Z)

KS000010-PAL

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

Figure 12. Input Waveforms and Measurement Levels

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Am49DL640BG

March 8, 2002

P R E L I M I N A R Y

pSRAM AC CHARACTERISTICS

CE#s Timing

Parameter

Test Setup

AllSpeeds

Unit

JEDEC

Std

Description

—

t_CCR

CE#s Recover Time

—

Min

0

ns

CE#f

t_CCR

CE1#s

CE2s

t_CCR

Figure 13. Timing Diagram for Alternating

Between Pseudo SRAM to Flash

March 8, 2002

Am49DL640BG

39

P R E L I M I N A R Y

FLASH AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed

85

JEDEC

t_AVAV

Std. Description

Test Setup

70

30

Unit

ns

t_RC

t_ACC

t_CE

Read Cycle Time (Note 1)

Min

Max

85

40

35

t_AVQV

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

Address to Output Delay

CE#f, OE# = V_IL

OE# = V_IL

ns

Chip Enable to Output Delay

ns

t_OE

t_DF

Output Enable to Output Delay

ns

Chip Enable to Output High Z (Notes 1, 3)

Output Enable to Output High Z (Notes 1, 3)

ns

t_DF

30

0

ns

Output Hold Time From Addresses, CE#f or

OE#, Whichever Occurs First

t_AXQX

t_OH

Min

ns

Read

0

Output Enable Hold Time

(Note 1)

t_OEH

Toggle and

Data# Polling

10

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 14 for test specifications

3. Measurements performed by placing a 50Ω termination on the data pin with a bias of V_CC/2. The time from OE# high to the

data bus driven to V_CC/2 is taken as t_DF

.

t_RC

Addresses Stable

t_ACC

Addresses

CE#f

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 14. Read Operation Timings

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March 8, 2002

P R E L I M I N A R Y

FLASH AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

Max

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#f, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#f, OE#

RESET#

t_RP

Figure 15. Reset Timings

March 8, 2002

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41

P R E L I M I N A R Y

FLASH AC CHARACTERISTICS

Word/Byte Configuration (CIOf)

Parameter

Speed

JEDEC

Std

t_{ELFL/ ELFH}

t_FLQZ

t_FHQV

Description

70

85

Unit

ns

t

CE#f to CIOf Switching Low or High

CIOf Switching Low to Output HIGH Z

CIOf Switching High to Output Active

Max

Min

5

30

ns

70

85

ns

CE#f

OE#

CIOf

t_ELFL

Data Output

(DQ14–DQ0)

Data Output

(DQ7–DQ0)

CIOf

DQ0–DQ14

Switching

from word

to byte

Address

Input

DQ15

Output

mode

DQ15/A-1

t_FLQZ

t_ELFH

CIOf

Switching

from byte

to word

Data Output

(DQ7–DQ0)

Data Output

(DQ14–DQ0)

DQ0–DQ14

mode

Address

Input

DQ15

Output

DQ15/A-1

t_FHQV

Figure 16. CIOf Timings for Read Operations

CE#f

WE#

The falling edge of the last WE# signal

CIOf

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note: Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 17. CIOf Timings for Write Operations

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March 8, 2002

P R E L I M I N A R Y

FLASH AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

70

85

Unit

ns

Write Cycle Time (Note 1)

Min

70

85

t_AVWL

Address Setup Time

0

ns

t_ASO

t_AH

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

ns

t_WLAX

40

45

ns

Address Hold Time From CE#f or OE# high

during toggle bit polling

t_AHT

Min

0

ns

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

ns

Data Hold Time

0

t_OEPH

Output Enable High during toggle bit polling

20

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_WLEL

t_ELWL

t_EHWH

t_WHEH

t_WLWH

t_WHDL

t_WS

t_CS

t_WH

t_CH

WE# Setup Time (CE#f to WE#)

CE#f Setup Time

Min

Typ

0

ns

WE# Hold Time (CE#f to WE#)

CE#f Hold Time

t_WP

Write Pulse Width

30

35

t_WPH

t_SR/W

Write Pulse Width High

Latency Between Read and Write Operations

Byte

30

0

5

t_WHWH1

t_WHWH1Programming Operation (Note 2)

µs

Word

7

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

t_WHWH2

t_WHWH1

Typ

4

t_WHWH2Sector Erase Operation (Note 2)

Typ

Min

Max

0.4

50

0

sec

µs

t_VCS

t_RB

V_CCSetup Time (Note 1)

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ns

t_BUSY

90

ns

Notes:

1. Not 100% tested.

2. See the “Flash Erase And Programming Performance” section for more information.

March 8, 2002

Am49DL640BG

43

P R E L I M I N A R Y

FLASH AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#f

OE#

t_CH

t_GHWL

t_WHWH1

t_WP

WE#

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

Data

t_BUSY

t_RB

RY/BY#

V

_CCf

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 18. Program Operation Timings

V_HH

V_ILor V_IH

WP#/ACC

V_ILor V_IH

t_VHH

Figure 19. Accelerated Program Timing Diagram

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March 8, 2002

P R E L I M I N A R Y

FLASH AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

t_WC

VA

Addresses

CE#f

2AAh

SADD

555h for chip erase

t_AH

t_GHWL

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

t_VCS

V_CC

f

Notes:

1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”.

2. These waveforms are for the word mode.

Figure 20. Chip/Sector Erase Operation Timings

March 8, 2002

Am49DL640BG

45

P R E L I M I N A R Y

FLASH AC CHARACTERISTICS

t_WC

Valid PA

t_WC

t_RC

t_WC

Valid PA

Valid RA

Valid PA

Addresses

t_AH

t_CPH

t_ACC

t_CE

CE#f

t_CP

t_OE

OE#

t_OEH

t_GHWL

t_WP

WE#

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

Data

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE#f Controlled Write Cycles

Figure 21. Back-to-back Read/Write Cycle Timings

t_RC

Addresses

CE#f

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Status Data

True

Valid Data

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 22. Data# Polling Timings (During Embedded Algorithms)

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March 8, 2002

P R E L I M I N A R Y

FLASH AC CHARACTERISTICS

t_AHT

t_AS

Addresses

CE#f

t_AHT

t_ASO

t_CEPH

t_OEH

WE#

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

Figure 23. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to

toggle DQ2 and DQ6.

Figure 24. DQ2 vs. DQ6

March 8, 2002

Am49DL640BG

47

P R E L I M I N A R Y

FLASH AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

250

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#f

WE#

t_RRB

t_RSP

RY/BY#

Figure 25. Temporary Sector Unprotect Timing Diagram

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March 8, 2002

P R E L I M I N A R Y

FLASH AC CHARACTERISTICS

V

ID

IH

RESET#

SADD,

Valid*

Status

A6, A1, A0

Sector/Sector Block Protect or Unprotect

60h 60h

Verify

40h

Data

Sector/Sector Block Protect: 150 µs,

Sector/Sector Block Unprotect: 15 ms

1 µs

CE#f

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address.

Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram

March 8, 2002

Am49DL640BG

49

P R E L I M I N A R Y

FLASH AC CHARACTERISTICS

Alternate CE#f Controlled Erase and Program Operations

Parameter

Speed

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

70

85

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

70

85

t_AVWL

t_ELAX

t_DVEH

t_EHDX

0

ns

t_AH

t_DS

t_DH

40

45

ns

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE#f Pulse Width

CE#f Pulse Width High

40

45

t_CPH

30

5

Byte

Programming Operation

(Note 2)

t_WHWH1

µs

Word

7

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

t_WHWH2

Notes:

t_WHWH1

t_WHWH2

Typ

4

µs

Sector Erase Operation (Note 2)

0.4

sec

1. Not 100% tested.

2. See the “Flash Erase And Programming Performance” section for more information.

50

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March 8, 2002

P R E L I M I N A R Y

FLASH AC CHARACTERISTICS

555 for program

2AA for erase

PA for program

SADD for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_AS

t_AH

t_WH

WE#

t_GHEL

OE#

t_{WHWH1 or 2}

t_CP

CE#f

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

Data

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SADD = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. Waveforms are for the word mode.

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings

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51

P R E L I M I N A R Y

pSRAM AC CHARACTERISTICS

Read Cycle

Speed

Parameter

Description

Symbol

Unit

70

85

t_RC

t_ACC

t_CO

t_OE

Read Cycle Time

Min

ns

Address Access Time

Max

Min

Max

Min

Max

Min

Chip Enable Access Time

Output Enable Access Time

Data Byte Control Access Time

Chip Enable Low to Output Active

Output Enable Low to Output Active

Data Byte Control Low to Output Active

Chip Enable High to Output High-Z

Output Enable High to Output High-Z

Data Byte Control High to Output High-Z

Output Data Hold from Address Change

Page Mode Time

25

10

0

t_BA

t_COE

t_OEE

t_BE

0

t_OD

20

10

70

30

10

t_ODO

t_BD

t_OH

t_PM

t_PC

Page Mode Cycle Time

t_AA

Page Mode Address Access Time

Page Output Data Hold Time

t_AOH

t_RC

Addresses

A0 to A20

t_ACC

t_OH

t_CO

CE#1

Fixed High

CE2

OE#

t_OD

t_OE

t_ODO

WE#

t_BA

LB#, UB#

t_BE

t_OEE

t_BD

Indeterminate

High-Z

D_OUT

I/O1 to 16

Valid Data Out

t_COE

Notes:

1. t_OD,t_ODo, t_BD, and t_ODWare defined as the time at which

the outputs achieve the open circuit condition and are

not referenced to output voltage levels.

3. If CE#, LB#, or UB# goes low at the same time or after WE#

goes low, the outputs will remain at high impedance.

2. If CE#, LB#, or UB# goes low at the same time or before

WE# goes high, the outputs will remain at high impedance.

Figure 28. Psuedo SRAM Read Cycle

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P R E L I M I N A R Y

pSRAM AC CHARACTERISTICS

t_PM

Addresses

A0 to A2

t_RC

t_PC

Addresses

A3 to A20

CE#1

CE2

Fixed High

OE#

WE#

LB#, UB#

t_OD

t_OE

t_BA

t_BD

t_OH

D_OUT

t_ODO

t_OEE

t_AOH

t_BE

D_OUT

I/O1 to 16

D_OUT

t_COE

t_CO

t_AA

Maximum 8 words

t_AA

t_ACC

Figure 29. Page Read Timing

Notes:

1. t_OD,t_ODo, t_BD, and t_ODWare defined as the time at which

the outputs achieve the open circuit condition and are

not referenced to output voltage levels.

3. If CE#, LB#, or UB# goes low at the same time or after WE#

goes low, the outputs will remain at high impedance.

2. If CE#, LB#, or UB# goes low at the same time or before

WE# goes high, the outputs will remain at high impedance.

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P R E L I M I N A R Y

pSRAM AC CHARACTERISTICS

Write Cycle

Speed

Parameter

Description

Symbol

Unit

70

50

60

85

60

70

t_WC

t_WP

t_CW

t_BW

t_AS

Write Cycle Time

Min

ns

Write Pulse Time

Chip Enable to End of Write

Data Byte Control to End of Write

Address Setup Time

Min

Max

Min

0

t_WR

t_ODW

t_OEW

t_DS

Write Recovery Time

WE# Low to Write to Output High-Z

WE# High to Write to Output Active

Data Set-up Time

20

0

30

0

t_DH

Data Hold from Write Time

CE2 Hold Time

ns

µs

t_CH

300

t_WC

Addresses

A0 to A20

t_AS

t_WR

t_WP

WE#

t_CW

CE#1

CE2

t_CH

t_BW

LB#, UB#

t_ODW

t_OEW

(Note 3)

(Note 4)

High-Z

D_OUT

I/O1 to 16

t_DH

t_DS

D_IN

I/O1 to 16

(Note 1)

Valid Data In

Notes:

1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.

2. If OE# is high during the write cycle, the outputs will remain at high impedance.

3. If CE#1s, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.

4. If CE#1s, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.

Figure 30. Pseudo SRAM Write Cycle—WE# Control

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P R E L I M I N A R Y

pSRAM AC CHARACTERISTICS

t_WC

Addresses

A0 to A20

t_AS

t_WP

t_WR

WE#

t_CW

CE#1

t_CH

CE2

t_BW

LB#, UB#

t_BE

t_ODW

D_OUT

High-Z

I/O1 to 16

t_COE

t_DS

t_DH

D_IN

(Note 1)

I/O1 to 16

(Note 1)

Valid Data In

Notes:

1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.

2. If OE# is high during the write cycle, the outputs will remain at high impedance.

Figure 31. Pseudo SRAM Write Cycle—CE1#s Control

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P R E L I M I N A R Y

pSRAM AC CHARACTERISTICS

t_WC

Addresses

A0 to A20

t_AS

t_WP

t_WR

WE#

t_CW

CE#1

t_CH

CE2

t_BW

UB#, LB#

t_COE

t_ODW

t_BE

High-Z

D_OUT

I/O1 to 16

t_DS

Valid Data In

t_DH

D_IN

I/O1 to 16

(Note 1)

Notes:

1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.

2. If OE# is high during the write cycle, the outputs will remain at high impedance.

Figure 32. Pseudo SRAM Write Cycle—

UB#s and LB#s Control

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P R E L I M I N A R Y

FLASH ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

µs

Comments

Sector Erase Time

0.4

56

5

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

Byte Program Time

Accelerated Byte/Word Program Time

Word Program Time

150

120

210

126

84

4

µs

Excludes system level

overhead (Note 5)

7

µs

Byte Mode

Word Mode

42

28

Chip Program Time

(Note 3)

sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

12 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

PACKAGE PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

11

Max

14

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

V_OUT= 0

V_IN= 0

12

14

17

16

pF

Control Pin Capacitance

WP#/ACC Pin Capacitance

16

pF

C_IN3

V_IN= 0

20

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

FLASH DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

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P R E L I M I N A R Y

pSRAM DATA RETENTION

Parameter

Parameter Description

Symbol

Min

Typ

Max

3.3

70

Unit

V

Test Setup

V_DR

I_DR

V_CCfor Data Retention

Data Retention Current

CS1#s ≥ V_CC– 0.2 V (Note 1)

2.7

V_CC= 3.0 V, CE1#s ≥ V_CC– 0.2 V

(Note 1)

1.0

(Note 2)

µA

t_CS

t_CH

CE2 Setup Time

0

300

10

0

ns

µs

ms

ns

µs

CE2 Hold Time

t_DPD

t_CHC

t_CHP

CE2 Pulse Width

CE2 Hold from CE#1

CE2 Hold from Power On

30

Notes:

1. CE1#s ≥ V_CC– 0.2 V, CE2s ≥ V_CC– 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled).

2. Typical values are not 100% tested.

pSRAM POWER ON AND DEEP POWER DOWN

CE#1

t_DPD

CE#2

t_CH

Figure 33. Deep Power-down Timing

Note: Data cannot be retained during deep power-down standby mode.

V_{DD min}

V_DD

t_CHC

CE#1

t_CHP

t_CH

CE#2

Figure 34. Power-on Timing

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P R E L I M I N A R Y

pSRAM ADDRESS SKEW

over 10 µs

CE#1

WE#

Address

t_{RC min}

Figure 35. Read Address Skew

Note: If multiple invalid address cycles shorter than t_RCmin occur for a period greater than 10 µs, at least one valid address

cycle over t_{RC min}is required during that period.

over 10 µs

CE#1

t_{WP min}

WE#

Address

t_{WC min}

Figure 36. Write Address Skew

Note: If multiple invalid address cycles shorter than t_WCmin occur for a period greater than 10 µs, at least one valid address

cycle over t_{WC min}, in addition to t_{WP min}, is required during that period.

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59

P R E L I M I N A R Y

PHYSICAL DIMENSIONS

FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm

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P R E L I M I N A R Y

REVISION SUMMARY

Revision A (March 8, 2002)

Initial release.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

March 8, 2002

Am49DL640BG

61


型号：	AM49DL640BG30IT
厂家：	SPANSION
描述：	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 堆叠式多芯片封装（ MCP ）闪存和SRAM 闪存静态存储器
文件：	总62页 (文件大小：1041K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM49DL640BG30IT [SPANSION]

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