AM50DL9608GT85FS [SPANSION]
Memory Circuit, 4MX16, CMOS, PBGA73, 8 X 11.60 MM, FBGA-73;型号: | AM50DL9608GT85FS |
厂家: | SPANSION |
描述: | Memory Circuit, 4MX16, CMOS, PBGA73, 8 X 11.60 MM, FBGA-73 静态存储器 内存集成电路 |
文件: | 总67页 (文件大小:990K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
Am50DL9608G
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
64 Megabit (4 M x 16-Bit) and 32 Megabit (2 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories, and
8 Mbit (512 K x 16-Bit) Pseudo Static RAM
DISTINCTIVE CHARACTERISTICS
—
—
Access time as fast as 70 ns
Program time: 4 µs/word typical utilizing Accelerate function
MCP Features
■ Power supply voltage of 2.7 to 3.3 volt
■ Ultra low power consumption (typical values)
■ High performance
—
—
—
2 mA active read current at 1 MHz
10 mA active read current at 5 MHz
200 nA in standby or automatic sleep mode
—
Access time as fast as 70 ns
■ Package
■ Minimum 1 million write cycles guaranteed per sector
—
73-Ball FBGA
■ Operating Temperature
■ 20 year data retention at 125°C
—
–40°C to +85°C
—
Reliable operation for the life of the system
Flash Memory Features
SOFTWARE FEATURES
(Am29DL640G/Am29DL320G)
■ Supports Common Flash Memory Interface (CFI)
—
Features apply to Am29DL640G and Am29DL320G
independently.
■ Program/Erase Suspend/Erase Resume
—
Suspends program/erase operations to allow
programming/erasing in same bank
ARCHITECTURAL ADVANTAGES
■ Data# Polling and Toggle Bits
■ Simultaneous Read/Write operations
—
Provides a software method of detecting the status of
program or erase cycles
—
Data can be continuously read from one bank while
executing erase/program functions in another bank.
Zero latency between read and write operations
—
HARDWARE FEATURES
■ Flexible Bank architecture
■ Any combination of sectors can be erased
—
Read may occur in any of the three banks not being written
■ Ready/Busy# output (RY/BY#)
or erased.
—
Hardware method for detecting program or erase cycle
completion
—
Four banks may be grouped by customer to achieve desired
bank divisions.
■ Hardware reset pin (RESET#)
■ Manufactured on 0.17 µm process technology
—
Hardware method of resetting the internal state machine to
the read mode
■ SecSi™ (Secured Silicon) Sector
—
—
—
Extra 256 byte sector on Am29DL640G
Extra 256 byte sector on Am29DL320G
■ WP#/ACC input pin
—
Write protect (WP#) protects sectors 0, 1, 140, and 141 in
Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
Am29DL640G, and two outermost boot sectors in
Am29DL320G
—
Acceleration (ACC) function accelerates program timing
■ Sector protection
—
Customer lockable: Sector is one-time programmable. Once
sector is locked, data cannot be changed.
—
Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
■ Zero Power Operation
Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
■ Boot sectors
erase operation within that sector
Temporary Sector Unprotect allows changing data in
protected sectors in-system
—
—
Pseudo SRAM Features
—
Top and bottom boot sectors in Am29DL640G
■ Power dissipation
—
Top or bottom boot options in Am29DL320G
—
—
Operating: 30 mA maximum
Standby: 70 µA maximum
■ Compatible with JEDEC standards
—
Pinout and software compatible with single-power-supply
flash standard
■ CE1s# and CE2s Chip Select
■ Power down features using CE1s# and CE2s
■ Data retention supply voltage: 2.7 to 3.3 volt
■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
PERFORMANCE CHARACTERISTICS
■ High performance
Publication# 27025 Rev:A Amendment/+1
Issue Date: October 14, 2002
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice. 10/15/02
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am50DL9608G consists of two flash memory de-
vices (one 64-Mbit Am29DL640G and one 32-Mbit
Am29DL320G), and one 8 Mbit pseudo SRAM device.
Bottom boot configuration is shown in the following ta-
ble.
Bank
Bank 1
Bank 2
Bank 3
Megabits
4 Mb
Sector Sizes
Eight 32 Kword
Am29DL640G and Am29DL320G Features
12 Mb
12 Mb
Twenty-four 32 Kword
Twenty-four 32 Kword
Eight 4 Kword,
Am29DL640G is a 64 megabit, 3.0 volt-only flash
memory device, organized as 4,194,304 words. The
Am29DL320G is a 32 megabit, 3.0 volt-only flash
memory device, organized as 2,097,152 words. Word
mode data appears on DQ15–DQ0. The device is de-
signed to be programmed in-system with the standard
3.0 volt VCC supply, and can also be programmed in
standard EPROM programmers.
Bank 4
4 Mb
Seven 32 Kword
Available on Am29DL640G and Am29DL320G, the
SecSi™ (Secured Silicon) Sector is an extra 256
byte sector capable of being permanently locked by
AMD or customers. The Secure SectorSecSi Indica-
tor Bit (DQ7) is permanently set to a 1 if the part is
factory locked, and set to a 0 if customer lockable.
This way, customer lockable parts can never be used
to replace a factory locked part.
The device is available with an access time of 70 or 85
ns and is offered in a 73-ball FBGA package. Standard
control pins—chip enable (CE#fx), write enable
(WE#), and output enable (OE#)—control normal read
and write operations, and avoid bus contention issues.
Factory locked parts provide several options. The Se-
cure SectorSecSi Sector may store a secure, random
16 byte ESN (Electronic Serial Number), customer
code (programmed through AMD’s ExpressFlash ser-
vice), or both. Customer Lockable parts may utilize the
Secure SectorSecSi Sector as a one-time program-
mable area.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The AMD DMS (Data Management Software) man-
ages data programming, enables EEPROM emulation,
and eases historical sector erase flash limitations. For
more information on DMS or to obtain the software,
contact AMD or an authorized representative.
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into four banks. Sector addresses are fixed,
system software can be used to form user-defined
bank groups.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
During an Erase/Program operation, any of the three
non-busy banks may be read from. Note that only two
banks can operate simultaneously. The device can im-
prove overall system performance by allowing a host
system to program or erase in one bank, then
immediately and simultaneously read from the other
bank, with zero latency. This releases the system from
waiting for the completion of program or erase
operations.
The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
The Am29DL640G can be organized as both a top
and bottom boot sector configuration.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Bank
Megabits
Sector Sizes
Eight 4 Kword,
Fifteen 32 Kword
Bank 1
8 Mb
Bank 2
Bank 3
24 Mb
24 Mb
Forty-eight 32 Kword
Forty-eight 32 Kword
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
Eight 4 Kword,
Fifteen 32 Kword
Bank 4
8 Mb
The Am29DL320G can be organized as either a top or
bottom boot sector configuration. Top boot configura-
tion is shown in the following table.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re-
duced in both modes.
Bank
Megabits
Sector Sizes
Eight 4 Kword,
Seven 32 Kword
Bank 1
4 Mb
Bank 2
Bank 3
Bank 4
12 Mb
12 Mb
4 Mb
Twenty-four 32 Kword
Twenty-four 32 Kword
Eight 32 Kword
2
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
TABLE OF CONTENTS
Figure 3. Program Operation ......................................................... 35
Chip Erase Command Sequence ........................................... 35
Sector Erase Command Sequence ........................................35
Erase Suspend/Erase Resume Commands ...........................36
Figure 4. Erase Operation.............................................................. 36
Table 22. Am29DL640G and Am29DL320G Command Definitions 37
Flash Write Operation Status . . . . . . . . . . . . . . . 38
DQ7: Data# Polling .................................................................38
Figure 5. Data# Polling Algorithm .................................................. 38
DQ6: Toggle Bit I ....................................................................39
Figure 6. Toggle Bit Algorithm........................................................ 39
DQ2: Toggle Bit II ................................................................... 40
Reading Toggle Bits DQ6/DQ2 ...............................................40
DQ5: Exceeded Timing Limits ................................................ 40
DQ3: Sector Erase Timer ....................................................... 40
Table 23. Write Operation Status ................................................... 41
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 42
Figure 7. Maximum Negative Overshoot Waveform ...................... 42
Figure 8. Maximum Positive Overshoot Waveform........................ 42
Figure 9. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents)............................................................. 43
Figure 10. Typical ICC1 vs. Frequency............................................ 43
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 44
Pseudo SRAM DC and Operating Characteristics
45
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 11. Test Setup.................................................................... 46
Figure 12. Input Waveforms and Measurement Levels ................. 46
Flash AC Characteristics . . . . . . . . . . . . . . . . . . 47
Pseudo SRAM CE#s Timing ......................................................47
Figure 13. Timing Diagram for Alternating
Between Pseudo SRAM to Flash................................................... 47
Read-Only Operations .............................................................. 48
Figure 14. Read Operation Timings ............................................... 48
Hardware Reset (RESET#) ....................................................... 49
Figure 15. Reset Timings ............................................................... 49
Erase and Program Operations ................................................. 50
Figure 16. Program Operation Timings.......................................... 51
Figure 17. Accelerated Program Timing Diagram.......................... 51
Figure 18. Chip/Sector Erase Operation Timings .......................... 52
Figure 19. Back-to-back Read/Write Cycle Timings ...................... 53
Figure 20. Data# Polling Timings (During Embedded Algorithms). 53
Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 54
Figure 22. DQ2 vs. DQ6................................................................. 54
Temporary Sector Unprotect .....................................................55
Figure 23. Temporary Sector Unprotect Timing Diagram .............. 55
Figure 24. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 56
Alternate CE#f Controlled Erase and Program Operations ....... 57
Figure 25. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 58
Pseudo SRAM AC Characteristics . . . . . . . . . . . 59
Power Up Time .......................................................................... 59
Read Cycle ................................................................................59
Figure 26. Pseudo SRAM Read Cycle—Address Controlled......... 59
Read Cycle ................................................................................60
Figure 27. Pseudo SRAM Read Cycle........................................... 60
Write Cycle ................................................................................61
Figure 28. Pseudo SRAM Write Cycle—WE# Control................... 61
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations . . . . . . . . . . . . . . . . .9
Table 1. Device Bus Operations—Flash Word Mode .................... 10
Flash Device Bus Operations . . . . . . . . . . . . . . . 11
Requirements for Reading Array Data ...................................11
Writing Commands/Command Sequences ............................11
Simultaneous Read/Write Operations with Zero Latency .......11
Automatic Sleep Mode ...........................................................12
RESET#: Hardware Reset Pin ...............................................12
Output Disable Mode .............................................................. 12
Table 2. Am29DL640G Sector Architecture ....................................13
Table 3. Am29DL640G Bank Address ............................................16
Table 4. Am29DL640G SecSi Sector Addresses .......................16
Table 5. Am29DL320G Top Boot Sector Addresses .....................17
Am29DL320G Top Boot SecSiTM Sector Addresses Am29DL320G
TM
Top Boot SecSi Sector Addresses ............................................... 18
Table 7. Am29DL320G Bottom Boot Sector Addresses .................19
TM
Am29DL320G Bottom Boot SecSi Sector Addresses Am29DL320G
TM
Bottom Boot SecSi Sector Addresses.......................................... 20
Table 9. Am29DL640G Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................21
Table 10. Am29DL320G Top Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................22
Table 11. Am29DL320G Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................22
Write Protect (WP#) ................................................................23
Table 12. WP#/ACC Modes ............................................................23
Temporary Sector Unprotect ..................................................23
Figure 1. Temporary Sector Unprotect Operation........................... 24
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 25
SecSi™ (Secured Silicon) Sector
SectorFlash Memory Region .................................................26
Table 13. SecSi Sector Programming ................................................26
Hardware Data Protection ......................................................27
Common Flash Memory Interface (CFI) . . . . . . .27
Table 14. Am29DL640G CFI Query Identification String ................ 27
Am29DL640G System Interface String Am29DL640G System Inter-
face String....................................................................................... 28
Table 16. Am29DL640G Device Geometry Definition..................... 28
Table 17. Am29DL640G Primary Vendor-Specific Extended Query....
29
Table 18. Am29DL320G CFI Query Identification String ................ 30
Am29DL320G System Interface String Am29DL320G System Inter-
face String....................................................................................... 30
Table 20. Am29DL320G Device Geometry Definition..................... 31
Table 21. Am29DL320G Primary Vendor-Specific Extended Query....
32
Flash Command Definitions . . . . . . . . . . . . . . . . 33
Reading Array Data ................................................................33
Reset Command .....................................................................33
Autoselect Command Sequence ............................................33
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 33
Program Command Sequence ...............................................34
October 14, 2002
Am50DL9608G
3
P R E L I M I N A R Y
Figure 29. Pseudo SRAM Write Cycle—CE1#s Control................. 62
PSRAM Data Retention . . . . . . . . . . . . . . . . . . . . 65
Figure 31. CE1#s Controlled Data Retention Mode....................... 65
Figure 32. CE2s Controlled Data Retention Mode......................... 65
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 66
FTA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ................66
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 30. Pseudo SRAM Write Cycle—
UB#s and LB#s Control................................................................... 63
Flash Erase And Programming Performance . . . 64
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 64
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 64
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . 65
4
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Part Number
Am50DL9608G
Flash Memory (Am29DL640G, Am29DL320G)
Pseudo SRAM
Speed
Options
Standard Voltage Range:
VCC = 2.7–3.3 V
70
70
70
30
85
85
85
40
70
70
70
35
85
85
85
40
Max Access Time (ns)
CE#f Access (ns)
OE# Access (ns)
MCP BLOCK DIAGRAM
VCC
f
VSS
A21 to A0
RY/BY#
64 MBit
CE#f1
Flash Memory
#1
DQ15 to DQ0
VCC
f
VSSf
RY/BY#
A20 to A0
32 MBit
Flash Memory
#2
RESET#
WP#/ACC
CE#f2
VCCs
VSS
A18 to A0
8 MBit
pseudo
Static RAM
LB#s
UB#s
WE#
OE#
CE1#s
CE2s
DQ15 to DQ0
October 14, 2002
Am50DL9608G
5
P R E L I M I N A R Y
FLASH MEMORY BLOCK DIAGRAM
V
V
CC
SS
OE#
Mux
Bank 1
Bank 1 Address
A21*–A0
X-Decoder
Bank 2 Address
RY/BY#
Bank 2
X-Decoder
A21*–A0
RESET#
STATE
CONTROL
&
COMMAND
REGISTER
Status
WE#
CE#
DQ15–DQ0
WP#/ACC
Control
Mux
X-Decoder
Bank 3
Bank 3 Address
Bank 4 Address
X-Decoder
Bank 4
A21*–A0
Mux
* Addresses for Am29DL640G are A21–A0. Address for Am29DL320G are A20–A0.
6
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
CONNECTION DIAGRAM
73-Ball FBGA
Top View
Flash only
A1
A10
NC
NC
Pseudo
SRAM only
B1
B5
NC
C5
B6
B10
NC
NC
NC
Shared
C1
C3
C4
C6
C7
C8
NC
A7
LB# WP#/ACC WE#
A8
A11
D2
A3
D3
A6
D4
D5
D6
D7
A19
E7
A9
D8
A12
E8
A13
F8
D9
A15
E9
UB# RESET# CE2s
E5
E2
A2
E3
A5
E4
E6
A18 RY/BY# A20
A21
F9
F1
NC
G1
NC
F2
A1
F3
A4
F4
A17
G4
DQ1
F7
F10
A10
G7
DQ6
H7
A14
G8
NC
CE#f2
NC
G2
A0
G3
G9 G10
V
SS
A16
H9
NC
J9
NC
H2
CE#f1
J2
H3
OE#
J3
H4
DQ9
J4
H5
DQ3
J5
H6
DQ4
J6
H8
DQ13 DQ15
J7
DQ12
K7
J8
DQ7
K8
V
CC
f
V s
CC
CE1#s DQ0
DQ10
K4
V
SS
K3
K5
DQ11
L5
K6
NC
L6
NC
DQ8
DQ2
DQ5
DQ14
L1
NC
M1
NC
L10
NC
NC
M10
NC
integrity may be compromised if the package body is
exposed to temperatures above 150°C for prolonged
periods of time.
Special Package Handling Instructions
Special handling is required for Flash Memory products
in molded packages (BGA). The package and/or data
October 14, 2002
Am50DL9608G
7
P R E L I M I N A R Y
PIN DESCRIPTION
LOGIC SYMBOL
A18–A0
= 19 Address Inputs (Common)
19
A21–A19, A-1 = 4 Address Inputs (Flash)
A18–A0
DQ15–DQ0
= 16 Data Inputs/Outputs (Common)
A21–A19
CE#f1
= Flash Chip Enable 1
(Am29DL640G)
CE#f1
CE#f2
CE1#s
CE2s
16
CE#f2
= Flash Chip Enable 2
(Am29DL320G)
DQ15–DQ0
CE#1s
CE2s
= Pseudo SRAM Chip Enable 1
= Pseudo SRAM Chip Enable 2
= Output Enable (Common)
OE#
RY/BY#
OE#
WE#
WE#
= Write Enable (Common)
WP#/ACC
RESET#
UB#s
RY/BY#
UB#s
= Ready/Busy Output
= Upper Byte Control (Pseudo SRAM)
= Lower Byte Control (Pseudo SRAM)
= Hardware Reset Pin, Active Low
LB#s
LB#s
RESET#
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
VCC
f
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
VCC
VSS
NC
s
= Pseudo SRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
8
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am50DL960 70
8
G
T
I
T
TAPE AND REEL
T
S
=
=
7 inches
13 inches
TEMPERATURE RANGE
Industrial (–40°C to +85°C)
I
=
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT SECTOR ARCHITECTURE
T
B
=
=
Top Boot of Am29DL320G Flash
Bottom Boot of Am29DL320G Flash
PROCESS TECHNOLOGY
0.17 µm
G
=
PSEUDO SRAM DEVICE DENSITY
8 Mbits
8
=
AMD DEVICE NUMBER/DESCRIPTION
Am50DL9608G
Stacked Multi-Chip Package (MCP) Flash Memory and Pseudo SRAM
Am29DL640G 64 Megabit (8/4 M x 16-Bit) and
Am29DL320G 32 Megabit (4/2 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
and 8 Mbit (152 K x 16-Bit) Pseudo Static RAM
Valid Combinations
Valid Combinations
Order Number Package Marking
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
M500000010
M500000011
Am50DL9608GT70I
Am50DL9608GB70I
T, S
T, S
M500000012
M500000013
Am50DL9608GT85I
Am50DL9608GB85I
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables 1-2 lists the device bus operations, the
inputs and control levels they require, and the result-
ing output. The following subsections describe each of
these operations in further detail.
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
October 14, 2002
Am50DL9608G
9
P R E L I M I N A R Y
Table 1. Device Bus Operations—Flash Word Mode
CE#f1
CE#f2
(Note 7)
WP#/
ACC
(Note 4)
Operation
(Notes 1, 2)
CE1#s
(Note 8) (Note 8)
CE2s
DQ7– DQ15–
OE# WE# Addr. LB#s UB#s RESET#
DQ0
DQ8
H
X
H
X
H
X
X
L
X
L
X
L
Read from Flash
Write to Flash
Standby
L
L
L
H
X
H
L
AIN
AIN
X
X
X
X
X
X
X
H
L/H
(Note 4)
H
DOUT
DOUT
H
DIN
DIN
VCC
0.3 V
±
VCC ±
0.3 V
X
High-Z High-Z
High-Z High-Z
High-Z High-Z
H
H
H
H
X
X
L
X
L
Output Disable
L
L
H
H
L/H
X
H
X
H
X
L
Flash Hardware
Reset
X
L
X
X
X
X
X
X
L
L/H
X
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Protect
(Note 5)
H
L
X
VID
L/H
DIN
X
X
X
H
X
L
X
L
SADD,
A6 = H,
A1 = H,
A0 = L
Sector Unprotect
(Note 5)
L
X
H
H
X
L
L
X
H
X
X
X
X
VID
VID
H
(Note 6)
(Note 6)
X
DIN
H
X
X
L
Temporary Sector
Unprotect
X
DIN
High-Z
DOUT
L
H
L
L
L
DOUT
Read from Pseudo
SRAM
L
L
H
H
AIN
High-Z DOUT
DOUT High-Z
H
L
L
DIN
High-Z
DIN
DIN
DIN
Write to Pseudo
SRAM
H
X
L
AIN
H
L
L
H
X
H
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector
Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#fx = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
7. Only one flash device should be accessed at a time. For Am29DL640G flash access, CE#f1 = VIL, CE#f2 = VIH. For
Am29DL320G flash access, CE#f1 = VIH, CE#f2 = ViL.
8. CE#1s= VIL, CE2s= VIH, CE#f1=VIH and CE#f2=VIH when accessing pseudo SRAM.
10
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
FLASH DEVICE BUS OPERATIONS
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE#f and OE# pins to VIL. CE#f is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the WP#/ACC pin returns the device to nor-
mal operation. Note that VHH must not be asserted on
WP#/ACC for operations other than accelerated pro-
gramming, or device damage may result. In addition,
the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavior of the device may result.
See “Write Protect (WP#)” on page 23 for related in-
formation.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the AC Read-Only Operations table for timing
specifications and to Figure 14 for the timing diagram.
ICC1 in the DC Characteristics table represents the ac-
tive current specification for reading array data.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Refer to the Sector/Sector Block Protection
and Unprotection and Autoselect Command Se-
quence sections for more information.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE#f to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facil-
itate faster programming. Once a bank enters the Un-
lock Bypass mode, only two write cycles are required
to program a word or byte, instead of four. The
“Byte/Word Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command se-
quences.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased). Figure 19 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. ICC6f and ICC7f in the table represent the cur-
rent specifications for read-while-program and
read-while-erase, respectively.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies. Similarly, a “sector
address” is the address bits required to uniquely select
a sector. The “Flash Command Definitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
Standby Mode
The device address space is divided into four banks. A
“bank address” is the address bits required to uniquely
select a bank.
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The Flash
AC Characteristics section contains timing specifica-
tion tables and timing diagrams for write operations.
The device enters the CMOS standby mode when the
CE#f and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE#f and RESET# are held at VIH, but not
within VCC ± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The de-
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
October 14, 2002
Am50DL9608G
11
P R E L I M I N A R Y
vice requires standard access time (tCE) for read ac-
cess when the device is in either of these standby
modes, before it is ready to read data.
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4f). If RESET# is
held at VIL but not within VSS±0.3 V, the standby cur-
rent will be greater.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3f in the table represents the standby current speci-
fication.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of tREADY (not during Embedded
Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
this mode when addresses remain stable for tACC
+
30 ns. The automatic sleep mode is independent of
the CE#f, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
ICC5f in the table represents the automatic sleep mode
current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
Refer to the Flash AC Characteristics tables for RE-
SET# parameters and to Figure 15 for the timing dia-
gram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
12
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
Table 2. Am29DL640G Sector Architecture
Sector Address
Sector Size
(Kbytes/Kwords)
(x16)
Address Range
Bank
Sector
A21–A12
SA0
SA1
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
8/4
8/4
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
Bank 1
October 14, 2002
Am50DL9608G
13
P R E L I M I N A R Y
Table 2. Am29DL640G Sector Architecture (Continued)
Sector Address
Sector Size
(Kbytes/Kwords)
(x16)
Address Range
Bank
Sector
A21–A12
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
0011101xxx
0011110xxx
0011111xxx
0100000xxx
0100001xxx
0100010xxx
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
0101111xxx
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0100100xxx
0110101xxx
0110110xxx
0110111xxx
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
0111110xxx
0111111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
Bank 2
14
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
Table 2. Am29DL640G Sector Architecture (Continued)
Sector Address
Sector Size
(Kbytes/Kwords)
(x16)
Address Range
Bank
Sector
A21–A12
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
1000000xxx
1000001xxx
1000010xxx
1000011xxx
1000100xxx
1000101xxx
1000110xxx
1000111xxx
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
1010000xxx
1010001xxx
1010010xxx
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
1011101xxx
1011110xxx
1011111xxx
1100000xxx
1100001xxx
1100010xxx
1100011xxx
1100100xxx
1100101xxx
1100110xxx
1100111xxx
1101000xxx
1101001xxx
1101010xxx
1101011xxx
1101100xxx
1101101xxx
1101110xxx
1101111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
Bank 3
October 14, 2002
Am50DL9608G
15
P R E L I M I N A R Y
Table 2. Am29DL640G Sector Architecture (Continued)
Sector Address
Sector Size
(Kbytes/Kwords)
(x16)
Address Range
Bank
Sector
A21–A12
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
1110000xxx
1110001xxx
1110010xxx
1110011xxx
1110100xxx
1110101xxx
1110110xxx
1110111xxx
1111000xxx
1111001xxx
1111010xxx
1111011xxx
1111100xxx
1111101xxx
1111110xxx
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3F8FFFh
3F9000h–3F9FFFh
3FA000h–3FAFFFh
3FB000h–3FBFFFh
3FC000h–3FCFFFh
3FD000h–3FDFFFh
3FE000h–3FEFFFh
3FF000h–3FFFFFh
Bank 4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Note: The address range is A21:A0
Table 3. Am29DL640G Bank Address
Bank
A21–A19
000
1
2
3
4
001, 010, 011
100, 101, 110
111
Table 4. Am29DL640G SecSi Sector Addresses
(x16)
Device
Am29DL640G
Sector Size
Address Range
256 bytes
00000h–0007Fh
16
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
Table 5. Am29DL320G Top Boot Sector Addresses
Sector Address
Sector Size
(Kbytes/Kwords)
(x16)
Address Range
Sector
A20–A12
SA0
SA1
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–07FFFh
008000h–0FFFFh
010000h–17FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
October 14, 2002
Am50DL9608G
17
P R E L I M I N A R Y
Table 5. Am29DL320G Top Boot Sector Addresses (Continued)
Sector Address
Sector Size
(Kbytes/Kwords)
(x16)
Address Range
Sector
A20–A12
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
110000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1F8FFFh
1F9000h–1F9FFFh
1FA000h–1FAFFFh
1FB000h–1FBFFFh
1FC000h–1FCFFFh
1FD000h–1FDFFFh
1FE000h–1FEFFFh
1FF000h–1FFFFFh
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Note: The address range is A20:A0.
TM
Table 6. Am29DL320G Top Boot SecSi Sector Addresses
Sector Address
Sector Size
(x16)
Device
A20–A12
(Bytes/Words)
Address Range
Am29DL320GT
111111xxx
256/128
1FF000h–1FF07Fh
18
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
Table 7. Am29DL320G Bottom Boot Sector Addresses
Sector Address
Sector Size
(Kbytes/Kwords)
(x16)
Address Range
Sector
A20–A12
SA0
SA1
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
8/4
000000h–000FFFh
001000h–001FFFh
002000h–002FFFh
003000h–003FFFh
004000h–004FFFh
005000h–005FFFh
006000h–006FFFh
007000h–007FFFh
008000h–00FFFFh
010000h–017FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
8/4
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
011111xxx
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
October 14, 2002
Am50DL9608G
19
P R E L I M I N A R Y
Table 7. Am29DL320G Bottom Boot Sector Addresses (Continued)
Sector Address
Sector Size
(Kbytes/Kwords)
(x16)
Address Range
Sector
A20–A12
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
111000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
Note: The address range is A20:A0
TM
Table 8. Am29DL320G Bottom Boot SecSi Sector Addresses
Sector Address
Sector Size
(x16)
Device
A20–A12
(Bytes/Words)
Address Range
Am29DL320GB
000000xxx
256/128
00000h–00007Fh
20
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
Sector/Sector Block Protection and
Unprotection
Sector/
Sector Block Size
Sector
A21–A12
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
SA83–SA86
SA87–SA90
SA91–SA94
SA95–SA98
SA99–SA102
SA103–SA106
SA107–SA110
SA111–SA114
SA115–SA118
SA119–SA122
SA123–SA126
SA127–SA130
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table
9).
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods.
Table 9. Am29DL640G Boot Sector/Sector Block
Addresses for Protection/Unprotection
Sector/
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A21–A12
Sector Block Size
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
1111100XXX,
1111101XXX,
1111110XXX
0000001XXX,
0000010XXX,
0000011XXX,
SA131–SA133
192 (3x64) Kbytes
SA8–SA10
192 (3x64) Kbytes
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111101
1111111111
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
SA35-SA38
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
October 14, 2002
Am50DL9608G
21
P R E L I M I N A R Y
Table 10. Am29DL320G Top Boot Sector/Sector
Table 11. Am29DL320G Bottom Boot
Sector/Sector Block Addresses
for Protection/Unprotection
Block Addresses for Protection/Unprotection
Sector/
Sector
A20–A12
Sector Block Size
Sector/Sector Block
Size
Sector
A20–A12
SA0
000000XXX
64 Kbytes
SA70
111111XXX
64 Kbytes
000001XXX,
000010XXX
000011XXX
SA1-SA3
192 (3x64) Kbytes
111110XXX,
111101XXX,
111100XXX
SA69-SA67
192 (3x64) Kbytes
SA4-SA7
SA8-SA11
0001XXXXX
0010XXXXX
0011XXXXX
0100XXXXX
0101XXXXX
0110XXXXX
0111XXXXX
1000XXXXX
1001XXXXX
1010XXXXX
1011XXXXX
1100XXXXX
1101XXXXX
1110XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
SA66-SA63
SA62-SA59
SA58-SA55
SA54-SA51
SA50-SA47
SA46-SA43
SA42-SA39
SA38-SA35
SA34-SA31
SA30-SA27
SA26-SA23
SA22–SA19
SA18-SA15
SA14-SA11
1110XXXXX
1101XXXXX
1100XXXXX
1011XXXXX
1010XXXXX
1001XXXXX
1000XXXXX
0111XXXXX
0110XXXXX
0101XXXXX
0100XXXXX
0011XXXXX
0010XXXXX
0001XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
SA44-SA47
SA48-SA51
SA52-SA55
SA56-SA59
111100XXX,
111101XXX,
111110XXX
SA60-SA62
192 (3x64) Kbytes
000011XXX,
000010XXX,
000001XXX
SA10-SA8
192 (3x64) Kbytes
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
000000111
000000110
000000101
000000100
000000011
000000010
000000001
000000000
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
22
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
Sector protection/unprotection requires VID on the RE-
tected using the method described in “Sector/Sector
Block Protection and Unprotection”.
SET# pin only, and can be implemented either in-sys-
tem or via programming equipment. Figure 2 shows
the algorithms and Figure 24 shows the timing dia-
gram. This method uses standard microprocessor bus
cycle timing. For sector unprotect, all unprotected sec-
tors must first be protected prior to the first sector un-
protect write cycle. Note that the sector unprotect
algorithm unprotects all sectors in parallel. All previ-
ously protected sectors must be individually re-pro-
tected. To change data in protected sectors efficiently,
the temporary sector unprotect function is available.
See “Temporary Sector Unprotect”.
Note that the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may
result.
Table 12. WP#/ACC Modes
WP#
Input
Voltage
Am29DL640G
Am29DL320G
Disables programming
and erasing in SA0,
SA1, SA140, and
SA141
Disables programming
and erasing in SA0 and
SA1 or SA69 and SA70
VIL
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
Enables programming
and erasing in SA0,
SA1, SA140, and
SA141
Enables programming
and erasing in SA0 and
SA1 or SA60 and SA70
VIH
Enables accelerated programming (ACC). See
“Accelerated Program Operation” on page 11.
VHH
It is possible to determine whether a sector is pro-
tected or unprotected. See the Sector/Sector Block
Protection and Unprotection section for details.
Temporary Sector Unprotect
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table
9).
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting without using VID. This function is
one of two provided by the WP#/ACC pin.
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 23 shows the timing diagrams, for this feature.
If the WP#/ACC pin is at VIL while the Am29DL640G is
enabled, sectors 0, 1, 140, and 141 of that device will
remain protected during the Temporary sector Unpro-
tect mode. Similarly, If the WP#/ACC pin is at VIL while
the Am29DL320G is enabled, the two outermost boot
sectors (SA0 and 1 on bottom boot devices or SA69
and 70 on top boot devices) of that device will remain
protected during the Temporary sector Unprotect
mode.
If the system asserts VIL on the WP#/ACC pin while
the Am29DL640G is enabled (CE#f1), the device dis-
ables program and erase functions in sectors 0, 1,
140, and 141, independently of whether those sectors
were protected or unprotected using the method de-
scribed in “Sector/Sector Block Protection and Unpro-
tection”. Similarly, the two outermost boot sectors
(SA0 and 1 on bottom boot devices or SA69 and 70 on
top boot devices) on the Am29DL320G are protected
when VIL is asserted on the WP#/ACC pin while the
Am29DL320G is enabled (CE#f2).
If the system asserts VIH on the WP#/ACC pin, the de-
vice reverts to whether the aforementioned sectors
were last set to be protected or unprotected. That is,
sector protection or unprotection for these sectors de-
pends on whether they were last protected or unpro-
October 14, 2002
Am50DL9608G
23
P R E L I M I N A R Y
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected (If WP#/ACC = VIL,
the following sectors will remain protected: sectors 0, 1,
140, and 141 (Am29DL640G), sectors 0 and 1
(Am29DL320GB), or sectors 69 and 70
(Am29DL320GT).
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
24
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 µs
Wait 1 µs
unprotect address
No
First Write
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Figure 2. In-System Sector Protect/Unprotect Algorithms
October 14, 2002
Am50DL9608G
25
P R E L I M I N A R Y
Table 13. SecSi Sector Programming
SecSi™ (Secured Silicon) Sector
Device
Data
Word Mode
Byte Mode
SectorFlash Memory Region
Random
number
000000h–
000007h
000000h–
00000Fh
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the secu-
rity of the ESN once the product is shipped to the field.
Am29DL640G
8-byte
secure ESN
000008h–
00000Fh
000010h–
000020h
Am29DL320GB 16-byte secure
(Bottom boot) ESN
Am29DL320GT 16-byte secure
(Top boot) ESN
000000h–
000007h
000000h–
00000Fh
1FF000h–
1FF007Fh
3FE000h–
3FE0FFh
The device is available preprogrammed with one of the
following:
■ Random number and secure ESNs only
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unprotected, allowing customers to utilize the that
sector in any manner they choose. The customer-lock-
able version has the SecSi (Secured Silicon) Sector
Indicator Bit permanently set to a “0.” Thus, the SecSi
Sector Indicator Bit prevents customer-lockable de-
vices from being used to replace devices that are fac-
tory locked.
■ Customer code through the ExpressFlash service
■ Random number, secure ESNs, and customer code
through the ExpressFlash service.
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. AMD
programs the customer’s code, with or without the ran-
dom ESN. The devices are then shipped from AMD’s
factory with the SecSi Sector permanently locked.
Contact an AMD representative for details on using
AMD’s ExpressFlash service.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
The system accesses the SecSi Sector Secure Sector
through a command sequence (see “Enter SecSi™
Sector/Exit SecSi Sector Command Sequence”). After
the system has written the Enter SecSi Sector com-
mand sequence, it may read the SecSi Sector by
using the addresses normally occupied by the boot
sectors. This mode of operation continues until the
system issues the Exit SecSi Sector command se-
quence, or until power is removed from the device. On
power-up, or following a hardware reset, the device re-
verts to sending commands to the first 256 bytes of
Sector 0.
If the security feature is not required, the SecSi Sector
can be treated as an additional Flash memory space.
The SecSi Sector can be read any number of times,
but can be programmed and locked only once. Note
that the accelerated programming (ACC) and unlock
bypass functions are not available when programming
the SecSi Sector.
The SecSi Sector area can be protected using one of
the following procedures:
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RESET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector Re-
gion without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In a factory locked device, the SecSi Sector is pro-
tected when the device is shipped from the factory.
The SecSi Sector cannot be modified in any way. The
device is preprogrammed with both a random number
and secure ESNs. See Table 13 for address location
details.
■ Write the three-cycle Enter SecSi Sector Secure
Sector Region command sequence, and then use
the alternate method of sector protection described
in the “Sector/Sector Block Protection and Unpro-
tection” section.
Once the SecSi Sector is locked and verified, the sys-
tem must write the Exit SecSi Sector Region com-
mand sequence to return to reading and writing the
remainder of the array.
The SecSi Sector lock must be used with caution
since, once locked, there is no procedure available for
26
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
unlocking the SecSi Sector area and none of the bits
in the SecSi Sector memory space can be modified in
any way.
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE
(CFI)
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 22 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
Low VCC Write Inhibit
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The
system can read CFI information at the addresses
given in Tables 14–17. To terminate reading CFI data,
the system must write the reset command.The CFI
Query mode is not accessible when the device is exe-
cuting an Embedded Program or embedded Erase al-
gorithm.
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is
greater than VLKO
.
Write Pulse “Glitch” Protection
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 14–17. The
system must write the reset command to return the de-
vice to the autoselect mode.
Noise pulses of less than 5 ns (typical) on OE#, CE#f
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE#f = VIH or WE# = VIH. To initiate a write cycle,
CE#f and WE# must be a logical zero while OE# is a
logical one.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/prod-
ucts/nvd/overview/cfi.html. Alternatively, contact an
AMD representative for copies of these documents.
Power-Up Write Inhibit
If WE# = CE#f = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
Table 14. Am29DL640G CFI Query Identification String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
October 14, 2002
Am50DL9608G
27
P R E L I M I N A R Y
Table 15. Am29DL640G System Interface String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
V
CC Min. (write/erase)
1Bh
1Ch
36h
38h
0027h
D7–D4: volt, D3–D0: 100 millivolt
V
CC Max. (write/erase)
0036h
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
V
PP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 16. Am29DL640G Device Geometry Definition
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
27h
4Eh
0017h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
007Dh
0000h
0000h
0001h
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
28
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
Table 17. Am29DL640G Primary Vendor-Specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII (reflects modifications to the silicon)
Minor version number, ASCII (reflects modifications to the CFI table)
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
0004h
Silicon Revision Number (Bits 7-2)
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
8Ch
8Eh
90h
0002h
0001h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
49h
92h
0004h
01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800
mode
Simultaneous Operation
00 = Not Supported, X = Number of Sectors (excluding Bank 1)
4Ah
4Bh
4Ch
94h
96h
98h
0077h
0000h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
9Ah
9Ch
0085h
0095h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom Boot
with Write Protect, 02h = Bottom Boot Device, 03h = Top Boot Device,
04h = Both Top and Bottom
4Fh
9Eh
0001h
Program Suspend
50h
57h
58h
59h
5Ah
5Bh
A0h
AEh
B0h
B2h
B4h
B6h
0001h
0004h
0017h
0030h
0030h
0017h
0 = Not supported, 1 = Supported
Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
Bank 1 Region Information
X = Number of Sectors in Bank 1
Bank 2 Region Information
X = Number of Sectors in Bank 2
Bank 3 Region Information
X = Number of Sectors in Bank 3
Bank 4 Region Information
X = Number of Sectors in Bank 4
October 14, 2002
Am50DL9608G
29
P R E L I M I N A R Y
Table 18. Am29DL320G CFI Query Identification String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Table 19. Am29DL320G System Interface String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
1Ch
36h
38h
0027h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
V
PP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
30
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
Table 20. Am29DL320G Device Geometry Definition
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
27h
4Eh
0016h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0002h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
003Eh
0000h
0000h
0001h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
October 14, 2002
Am50DL9608G
31
P R E L I M I N A R Y
Table 21. Am29DL320G Primary Vendor-Specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Silicon Revision Number
00h = 0.23 µm, 01h = 0.17 µm
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
8Ah
8Ch
8Eh
90h
92h
94h
96h
98h
0001h
0002h
0001h
0001h
0004h
0038h
0000h
0000h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = 29LV800 mode
Simultaneous Operation
Number of Sectors (excluding Bank 1)
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
4Fh
9Ah
9Ch
9Eh
0085h
0095h
000Xh
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
32
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
FLASH COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 22 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
which the system was writing to the read mode. If the
program command sequence is written to a bank that
is in the Erase Suspend mode, writing the reset
command returns that bank to the erase-sus-
pend-read mode. Once programming begins, how-
ever, the device ignores reset commands until the
operation is complete.
All addresses are latched on the falling edge of WE#
or CE#f, whichever happens later. All data is latched
on the rising edge of WE# or CE#f, whichever hap-
pens first. Refer to the Flash AC Characteristics sec-
tion for timing diagrams.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If a bank
entered the autoselect mode while in the Erase Sus-
pend mode, writing the reset command returns that
bank to the erase-suspend-read mode.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to the
read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read
data from any non-erase-suspended sector within the
same bank. The system can read array data using the
standard read timing, except that if it reads at an ad-
dress within erase-suspended sectors, the device out-
puts status data. After completing a programming
operation in the Erase Suspend mode, the system
may once again read array data with the same excep-
tion. See the Erase Suspend/Erase Resume Com-
mands section for more information.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
The autoselect command sequence may be written to
an address within a bank that is either in the read or
erase-suspend-read mode. The autoselect command
may not be written while the device is actively pro-
gramming or erasing in the other bank.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the au-
toselect command. The bank then enters the autose-
lect mode. The system may read any number of
autoselect codes without reinitiating the command se-
quence.
The system must issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the
next section, Reset Command, for more information.
See also Requirements for Reading Array Data in the
section for more information. The Read-Only Opera-
tions table provides the read parameters, and Figure
14 shows the timing diagram.
Table 22 shows the address and data requirements.
To determine sector protection information, the system
must write to the appropriate bank address (BA) and
sector address (SADD). Table 2 shows the address
range and bank number associated with each sector.
Reset Command
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure be-
gins, however, the device ignores reset commands
until the operation is complete.
The SecSi Sector region provides a secured data area
containing a random, sixteen-byte electronic serial
number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi
Sector command sequence. The device continues to
access the SecSi Sector region until the system is-
sues the four-cycle Exit SecSi Sector command se-
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the bank to
October 14, 2002
Am50DL9608G
33
P R E L I M I N A R Y
quence. The Exit SecSi Sector command sequence
Unlock Bypass Command Sequence
returns the device to normal operation. The SecSi
Sector is not accessible when the device is executing
an Embedded Program or embedded Erase algorithm.
Table 22 shows the address and data requirements for
both command sequences. See also “SecSi™ (Se-
cured Silicon) Sector SectorFlash Memory Region” for
further information.
The unlock bypass feature allows the system to pro-
gram bytes or words to a bank faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
That bank then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 22 shows the require-
ments for the command sequence.
Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 22 shows the address
and data requirements for the byte program command
sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need
only contain the data 00h. The bank then returns to
the read mode.
When the Embedded Program algorithm is complete,
that bank then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the Flash Write Oper-
ation Status section for information on these status
bits.
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at VHH any operation
other than accelerated programming, or device dam-
age may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once that bank has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate the operation was success-
ful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 16 for timing diagrams.
34
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
START
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
Write Program
Command Sequence
Data Poll
from System
Sector Erase Command Sequence
Embedded
Program
algorithm
in progress
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 22 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
Verify Data?
Yes
No
No
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
Increment Address
Last Address?
Yes
Programming
Completed
After the command sequence is written, a sector erase
time-out of 80 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 80
µs, otherwise erasure may begin. Any sector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the
time-out period resets that bank to the read mode.
The system must rewrite the command sequence and
any additional addresses and commands.
Note: See Table 22 for program command sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 22
shows the address and data requirements for the chip
erase command sequence.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete,
that bank returns to the read mode and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. Refer to the Flash Write Operation Status
section for information on these status bits.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing bank. The system can de-
termine the status of the erase operation by reading
October 14, 2002
Am50DL9608G
35
P R E L I M I N A R Y
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank.
Refer to the Flash Write Operation Status section for
information on these status bits.
Refer to the Flash Write Operation Status section for
more information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. The device
allows reading autoselect codes even at addresses
within erasing sectors, since the codes are not stored
in the memory array. When the device exits the au-
toselect mode, the device reverts to the Erase Sus-
pend mode, and is ready for another valid operation.
Refer to the Sector/Sector Block Protection and Un-
protection and Autoselect Command Sequence sec-
tions for details.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once that bank has returned to
reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
To resume the sector erase operation, the system
must write the Erase Resume command (address bits
are don’t care). The bank address of the erase-sus-
pended bank is required when writing this command.
Further writes of the Resume command are ignored.
Another Erase Suspend command can be written after
the chip has resumed erasing.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. The bank address is required when writing
this command. This command is valid only during the
sector erase operation, including the 80 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase operation or Embedded Program
algorithm.
START
Write Erase
Command Sequence
(Notes 1, 2)
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation. Addresses are “don’t-cares” when
writing the Erase suspend command.
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Flash Write Operation Status section for
information on these status bits.
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 22 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
After an erase-suspended program operation is com-
plete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard Byte Program operation.
Figure 4. Erase Operation
36
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
Table 22. Am29DL640G and Am29DL320G Command Definitions
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Addr
Sixth
Addr Data
Addr Data Addr Data
Data
Addr
Data
Data
Read (Note 6)
Reset (Note 7)
1
1
RA
RD
F0
XXX
Manufacturer ID
Word
Word
Word
4
6
4
555
555
555
AA
AA
AA
2AA
2AA
2AA
55
55
55
(BA)555
(BA)555
(BA)555
90 (BA)X00
01
Device ID (Note 9)
90 (BA)X01 7E
90 (BA)X03 80/00
(BA)X0E 02/0A (BA)X0F 00/01
SecSi Sector Factory
Protect (Note 10)
Sector/Sector Block
Protect Verify
(Note 11)
(SADD)
X02
Word
4
555
AA
2AA
55
(BA)555
90
00/01
Enter SecSi Sector Region Word
3
4
4
3
555
555
555
555
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
555
88
90
A0
20
Exit SecSi Sector Region
Program
Word
Word
Word
XXX
PA
00
PD
Unlock Bypass
Unlock Bypass Program (Note 12)
Unlock Bypass Reset (Note 13)
2
2
6
6
1
1
XXX
BA
A0
90
PA
PD
00
55
55
XXX
2AA
2AA
Chip Erase
Word
Word
555
555
BA
AA
AA
B0
30
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
10
30
Sector Erase
SADD
Erase Suspend (Note 14)
Erase Resume (Note 15)
BA
CFI Query (Note 16)
Word
1
55
98
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE#f pulse, whichever happens first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE#f pulse, whichever happens
later.
SADD = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A21–A12 uniquely select any sector. Refer to
Table 2 for information on sector addresses.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased. Address bits A21–A19 select a
bank. Refer to Table 3 for information on sector addresses.
Notes:
1. See Tables 1 to 2 for description of bus operations.
Am29DL640G and Am29DL320G (top boot) and 00h for
Am29DL320G (bottom boot).
2. All values are in hexadecimal.
10. For Am29DL640G, the data is 80h for factory locked and 00h for
not factory locked. For Am29DL320G, they are 81H and 01h
respectively.
11. The data is 00h for an unprotected sector/sector block and 01h
for a protected sector/sector block.
12. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
13. The Unlock Bypass Reset command is required to return to the
read mode when the bank is in the unlock bypass mode.
14. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
16. Command is valid when device is ready to read array data or when
device is in autoselect mode.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
5. Unless otherwise noted, address bits A21–A12 are don’t cares for
unlock and command cycles, unless SADD or PA is required.
6. No unlock or command cycles required when bank is reading
array data.
7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high (while
the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. Data bits DQ15–DQ8 are don’t care. See the
Autoselect Command Sequence section for more information.
9. The device ID must be read across the fourth, fifth, and sixth
cycles. At address x0E, the data is 02h for Am29DL640G and
0Ah for Am29DL320G. At address x0F, the data is 01h for
October 14, 2002
Am50DL9608G
37
P R E L I M I N A R Y
FLASH WRITE OPERATION STATUS
The device provides several bits to determine the status of
a program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 23 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method
for determining whether a program or erase operation is
complete or in progress. The device also provides a hard-
ware-based output signal, RY/BY#, to determine whether
an Embedded Program or Erase operation is in progress or
has been completed.
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ15–DQ0 may be still
invalid. Valid data on DQ15–DQ0 (or DQ7–DQ0 for
byte mode) will appear on successive read cycles.
Table 23 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm. Figure 20
in the Flash AC Characteristics section shows the
Data# Polling timing diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether a bank is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the final
WE# pulse in the command sequence.
START
Read DQ7–DQ0
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 µs, then that bank returns to the
read mode.
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Yes
Read DQ7–DQ0
Addr = VA
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then
the bank returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
Yes
DQ7 = Data?
No
PASS
FAIL
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ15–DQ0 (or DQ7–DQ0 for byte mode) on the fol-
lowing read cycles. Just prior to the completion of an
Embedded Program or Erase operation, DQ7 may
change asynchronously with DQ15–DQ8 (DQ7–DQ0
in byte mode) while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 5. Data# Polling Algorithm
38
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
DQ6 also toggles during the erase-suspend-program
RY/BY#: Ready/Busy#
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
Table 23 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 21 in
the “Flash AC Characteristics” section shows the tog-
gle bit timing diagrams. Figure 22 shows the differ-
ences between DQ2 and DQ6 in graphical form. See
also the subsection on DQ2: Toggle Bit II.
pull-up resistor to VCC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or one of the banks is in the erase-sus-
pend-read mode.
START
Read Byte
(DQ7–DQ0)
Address =VA
Table 23 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
Read Byte
(DQ7–DQ0)
Address =VA
No
Toggle Bit
= Toggle?
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE#f to control the read cycles. When the operation is
complete, DQ6 stops toggling.
Yes
No
DQ5 = 1?
Yes
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are pro-
tected.
Read Byte Twice
(DQ7–DQ0)
Address = VA
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data# Poll-
ing).
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
Figure 6. Toggle Bit Algorithm
October 14, 2002
Am50DL9608G
39
P R E L I M I N A R Y
not gone high. The system may continue to monitor
DQ2: Toggle Bit II
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 6).
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ5: Exceeded Timing Limits
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE#f to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 23 to compare out-
puts for DQ2 and DQ6.
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 21 shows the toggle bit timing diagram. Figure
22 shows the differences between DQ2 and DQ6 in
graphical form.
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if a bank was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
Reading Toggle Bits DQ6/DQ2
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ15–DQ0 (or DQ7–DQ0 for byte
mode) at least twice in a row to determine whether a
toggle bit is toggling. Typically, the system would note
and store the value of the toggle bit after the first read.
After the second read, the system would compare the
new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the pro-
gram or erase operation. The system can read array
data on DQ15–DQ0 (or DQ7–DQ0 for byte mode) on
the following read cycle.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
Table 23 shows the status of DQ3 relative to the other
status bits.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
40
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
Table 23. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Erase-Suspend-
Read
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
1
No toggle
0
N/A
Toggle
1
Suspended Sector
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
October 14, 2002
Am50DL9608G
41
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C
20 ns
20 ns
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . –40°C to +85°C
+0.8 V
Voltage with Respect to Ground
–0.5 V
–2.0 V
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V
WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
20 ns
Figure 7. Maximum Negative
Overshoot Waveform
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 7. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 8.
20 ns
VCC
+2.0 V
2. Minimum DC input voltage on pins RESET#, and
WP#/ACC is –0.5 V. During voltage transitions,
WP#/ACC, and RESET# may overshoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 7. Maximum DC
input voltage on pin RESET# is +12.5 V which may
overshoot to +14.0 V for periods up to 20 ns. Maximum
DC input voltage on WP#/ACC is +9.5 V which may
overshoot to +12.0 V for periods up to 20 ns.
VCC
+0.5 V
2.0 V
20 ns
20 ns
Figure 8. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
V
CCf/VCCs Supply Voltages
VCCf/VCCs for standard voltage range . .2.7 V to 3.3 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
42
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
FLASH DC CHARACTERISTICS
Zero-Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12
10
8
3.3 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
4.
October 14, 2002
Am50DL9608G
43
P R E L I M I N A R Y
FLASH DC CHARACTERISTICS
CMOS Compatible
Parameter
Parameter Description
Symbol
Test Conditions
Min
Typ
Max
Unit
VIN = VSS to VCC
VCC = VCC max
,
ILI
Input Load Current
±1.0
35
µA
µA
µA
µA
ILIT
ILO
ILIA
RESET# Input Load Current
Output Leakage Current
ACC Input Leakage Current
VCC = VCC max; RESET# = 12.5 V
VOUT = VSS to VCC
VCC = VCC max
,
±1.0
VCC = VCC max, WP#/ACC = VACC max
35
16
4
5 MHz
1 MHz
10
2
Flash VCC Active Read Current
(Notes 1, 2)
ICC1
ICC2
f
f
CE#f = VIL, OE# = VIH, Word Mode
mA
Flash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH, WE# = VIL
15
30
mA
µA
VCCf = VCC max, CE#f, RESET#,
Flash VCC Standby Current (Note 2)
I
CC3f
0.2
0.2
0.2
21
5
5
WP#/ACC = VCCf ± 0.3 V
VCCf = VCC max, RESET# = VSS ± 0.3 V,
Flash VCC Reset Current (Note 2)
ICC4
ICC5
ICC6
ICC7
f
f
f
f
µA
µA
WP#/ACC = VCCf ± 0.3 V
Flash VCC Current Automatic Sleep Mode VCCf = VCC max, VIH = VCC ± 0.3 V;
5
(Notes 2, 4)
VIL = VSS ± 0.3 V
Flash VCC Active Read-While-Program
Current (Notes 1, 2)
CE#f = VIL, OE# = VIH
45
45
mA
mA
Flash VCC Active Read-While-Erase
Current (Notes 1, 2)
CE#f = VIL, OE# = VIH
21
Flash VCC Active
ICC8f
Program-While-Erase-Suspended Current CE#f = VIL, OE#f = VIH
(Notes 2, 5)
17
35
mA
VIL
VIH
Input Low Voltage
Input High Voltage
–0.2
0.8
V
V
V
CC + 0.2
2.4
Voltage for WP#/ACC Program
Acceleration and Sector
Protection/Unprotection
VHH
8.5
9.5
V
Voltage for Sector Protection, Autoselect
and Temporary Sector Unprotect
VID
VOL
11.5
12.5
0.45
V
V
Output Low Voltage
IOL = 4.0 mA, VCCf = VCCs = VCC min
OH = –2.0 mA, VCCf = VCCs = VCC min
IOH = –100 µA, VCC = VCC min
0.85 x
VCC
VOH1
I
Output High Voltage
V
V
VOH2
VLKO
VCC–0.4
Flash Low VCC Lock-Out Voltage (Note 5)
2.3
2.5
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at
VIH
4. Automatic sleep mode enables the low power mode when
addresses remain stable for tACC + 30 ns. Typical sleep mode
current is 200 nA.
.
2. Maximum ICC specifications are tested with VCC = VCCmax.
5. Not 100% tested.
3. ICC active while Embedded Erase or Embedded Program is in
progress.
44
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
PSEUDO SRAM DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Parameter Description
Input Leakage Current
Test Conditions
VIN = VSS to VCC
Min
–1.0
–1.0
Typ
Max
1.0
Unit
µA
ILI
CE1#s = VIH, CE2s = VIL or OE# =
VIH or WE# = VIL, VIO= VSS to VCC
ILO
Output Leakage Current
1.0
µA
Cycle time = 1 µs, 100% duty,
IIO = 0 mA, CE1#s ≤ 0.2 V,
CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or
ICC1
s
Average Operating Current
2
mA
mA
VIN ≥ VCC – 0.2 V
Cycle time = Min., IIO = 0 mA,
100% duty, CE1#s = VIL, CE2s =
VIH, VIN = VIL = or VIH
ICC2s
Average Operating Current
20
–0.2
(Note 3)
VIL
Input Low Voltage
Input High Voltage
0.4
V
V
VCC+0.2
(Note 2)
VIH
2.2
2.2
VOL
Output Low Voltage
Output High Voltage
IOL = 2.0 mA
0.4
0.3
70
V
V
VOH
ISB
IOH = –1.0 mA
CE1#s = VIH, CE2 = VIL, Other
inputs = VIH or VIL
Standby Current (TTL)
mA
CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC
0.2 V (CE1#s controlled) or CE2 ≤
0.2 V (CE2s controlled), CIOs =
VSS or VCC, Other input = 0 ~ VCC
–
ISB1
Standby Current (CMOS)
µA
Notes:
1. TA= –40° to 85°C, otherwise specified.
2. Overshoot: VCC+1.0V if pulse width ≤ 20 ns.
3. Undershoot: –1.0V if pulse width ≤ 20 ns.
4. Overshoot and undershoot are sampled, not 100% tested.
5. Stable power supply required 200 µs before devcie operation.
October 14, 2002
Am50DL9608G
45
P R E L I M I N A R Y
TEST CONDITIONS
Table 24. Test Specifications
3.3 V
Test Condition
70, 85
Unit
Output Load
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
0.0–3.0
Input timing measurement
reference levels
1.5
1.5
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
KS000010-PAL
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 12. Input Waveforms and Measurement Levels
46
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Pseudo SRAM CE#s Timing
Parameter
Test Setup
AllSpeeds
Unit
JEDEC
Std
Description
—
tCCR
CE#s Recover Time
—
Min
0
ns
CE#f
tCCR
tCCR
CE1#s
CE2s
tCCR
tCCR
Figure 13. Timing Diagram for Alternating
Between Pseudo SRAM to Flash
October 14, 2002
Am50DL9608G
47
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed
JEDEC
tAVAV
Std. Description
Test Setup
70
85
85
85
85
40
Unit
ns
tRC
Read Cycle Time (Note 1)
Min
Max
Max
Max
Max
Max
70
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tACC Address to Output Delay
CE#f, OE# = VIL
OE# = VIL
70
70
30
ns
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
ns
Output Enable to Output Delay
ns
Chip Enable to Output High Z (Notes 1, 3)
Output Enable to Output High Z (Notes 1, 3)
16
16
ns
ns
Output Hold Time From Addresses, CE#f or
OE#, Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold Time
tOEH
Toggle and
Data# Polling
(Note 1)
10
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 24 for test specifications
3. Measurements performed by placing a 50Ω termination on the data pin with a bias of VCC/2. The time from OE# high to the
data bus driven to VCC/2 is taken as tDF
.
tRC
Addresses Stable
tACC
Addresses
CE#f
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 14. Read Operation Timings
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Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
Max
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#f, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#f, OE#
RESET#
tRP
Figure 15. Reset Timings
October 14, 2002
Am50DL9608G
49
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed
JEDEC
tAVAV
Std
tWC
tAS
Description
70
85
Unit
ns
Write Cycle Time (Note 1)
Min
Min
Min
70
85
tAVWL
Address Setup Time
0
ns
tASO
Address Setup Time to OE# low during toggle bit polling
15
ns
Am29DL640G
Address Hold Time
40
45
tWLAX
tAH
tAHT
tDS
Min
Min
Min
45
45
ns
ns
ns
Am29DL320G
Address Hold Time From CE#f or OE# high
during toggle bit polling
0
Am29DL640G
40
35
tDVWH
tWHDX
Data Setup Time
Am29DL320G
tDH
Data Hold Time
Min
Min
0
ns
ns
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tWLEL
tELWL
tWS
tCS
WE# Setup Time (CE#f to WE#)
CE#f Setup Time
Min
Min
Min
Min
Min
Min
Min
Typ
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
µs
tEHWH
tWHEH
tWLWH
tWHDL
tWH
WE# Hold Time (CE#f to WE#)
CE#f Hold Time
tCH
tWP
Write Pulse Width
30
35
tWPH
tSR/W
Write Pulse Width High
30
0
Latency Between Read and Write Operations
tWHWH1
tWHWH1
tWHWH2
tWHWH1 Programming Operation (Note 2)
7
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
Typ
4
µs
tWHWH2 Sector Erase Operation (Note 2)
Typ
Min
Min
Max
0.4
50
0
sec
µs
tVCS
tRB
VCC Setup Time (Note 1)
Write Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
ns
tBUSY
90
ns
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
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Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#f
OE#
tCH
tGHWL
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
tBUSY
tRB
RY/BY#
VCC
f
tVCS
otes:
. PA = program address, PD = program data, DOUT is the true data at the program address.
. Illustration shows device in word mode.
Figure 16. Program Operation Timings
VHH
VIL or VIH
WP#/ACC
VIL or VIH
tVHH
tVHH
Figure 17. Accelerated Program Timing Diagram
October 14, 2002
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51
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
tWC
VA
Addresses
CE#f
2AAh
SADD
555h for chip erase
tAH
tGHWL
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
f
otes:
. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”.
.
These waveforms are for the word mode.
Figure 18. Chip/Sector Erase Operation Timings
52
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
tWC
Valid PA
tWC
tRC
tWC
Valid PA
Valid RA
Valid PA
Addresses
tAH
tCPH
tACC
tCE
CE#f
tCP
tOE
OE#
tOEH
tGHWL
tWP
WE#
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
Data
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE#f Controlled Write Cycles
Figure 19. Back-to-back Read/Write Cycle Timings
tRC
Addresses
CE#f
VA
tACC
tCE
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ6–DQ0
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 20. Data# Polling Timings (During Embedded Algorithms)
October 14, 2002
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53
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
tAHT
tAS
Addresses
CE#f
tAHT
tASO
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 21. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to
toggle DQ2 and DQ6.
Figure 22. DQ2 vs. DQ6
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Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
tVIDR
tVHH
Description
All Speed Options
Unit
ns
VID Rise and Fall Time (See Note)
VHH Rise and Fall Time (See Note)
Min
Min
500
250
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
Min
Min
4
4
µs
µs
RESET# Hold Time from RY/BY# High for
Temporary Sector Unprotect
tRRB
Note: Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#f
WE#
tRRB
tRSP
RY/BY#
Figure 23. Temporary Sector Unprotect Timing Diagram
October 14, 2002
Am50DL9608G
55
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
V
V
ID
IH
RESET#
SADD,
Valid*
Valid*
Valid*
Status
A6, A1, A0
Sector/Sector Block Protect or Unprotect
60h 60h
Verify
40h
Data
Sector/Sector Block Protect: 150 µs,
Sector/Sector Block Unprotect: 15 ms
1 µs
CE#f
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address.
Figure 24. Sector/Sector Block Protect and
Unprotect Timing Diagram
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October 14, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Alternate CE#f Controlled Erase and Program Operations
Parameter
Speed
70
JEDEC
tAVAV
Std
tWC
tAS
tAH
tDS
tDH
Description
85
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
70
85
tAVWL
tELAX
tDVEH
tEHDX
0
ns
40
40
45
45
ns
ns
0
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
0
0
ns
ns
ns
ns
CE#f Pulse Width
CE#f Pulse Width High
40
45
tCPH
30
7
Programming Operation
(Note 2)
tWHWH1
tWHWH1
Typ
µs
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
tWHWH2
Notes:
tWHWH1
tWHWH2
Typ
Typ
4
µs
Sector Erase Operation (Note 2)
0.4
sec
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
October 14, 2002
Am50DL9608G
57
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SADD for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#f
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SADD = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Figure 25. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings
58
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
PSEUDO SRAM AC CHARACTERISTICS
Power Up Time
When powering up the SRAM, maintain VCCs for 100 µs minimum with CE#1s at VIH.
Read Cycle
Speed
Parameter
Symbol
Description
Unit
70
85
85
85
85
40
85
tRC
tAA
CO1, tCO2
tOE
Read Cycle Time
Min
Max
Max
Max
Max
70
70
70
35
70
ns
ns
ns
ns
ns
Address Access Time
Chip Enable to Output
Output Enable Access Time
LB#s, UB#s to Access Time
t
tBA
Chip Enable (CE1#s Low and CE2s High) to Low-Z
Output
tLZ1, tLZ2
Min
5
ns
tBLZ
tOLZ
HZ1, tHZ2
tBHZ
UB#, LB# Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Min
Min
Max
Max
Max
Min
5
ns
ns
ns
ns
ns
ns
5
t
25
25
25
10
UB#s, LB#s Disable to High-Z Output
Output Disable to High-Z Output
Output Data Hold from Address Change
tOHZ
tOH
tRC
ddress
tAA
tOH
Data Valid
ata Out
Previous Data Valid
Notes:
1. CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL
2. Do not access device with cycle timing shorter than tRC for continuous periods < 10 µs.
Figure 26. Pseudo SRAM Read Cycle—Address Controlled
October 14, 2002
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59
P R E L I M I N A R Y
PSEUDO SRAM AC CHARACTERISTICS
Read Cycle
tRC
Address
tAA
tCO1
tOH
CE#1s
CE2s
tCO2
tOE
tHZ
OE#
tOLZ
tBLZ
tLZ
tOHZ
Data Out
High-Z
Data Valid
Notes:
1. WE# = VIH.
2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device
interconnection.
4. Do not access device with cycle timing shorter than tRC for continuous periods < 10 µs.
Figure 27. Pseudo SRAM Read Cycle
60
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
PSEUDO SRAM AC CHARACTERISTICS
Write Cycle
Speed
Parameter
Symbol
Description
Unit
70
70
55
85
85
70
tWC
tCw
tAS
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of Write
Address Setup Time
0
tAW
tBW
tWP
tWR
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
55
55
55
70
70
60
Write Recovery Time
0
0
tWHZ
Write to Output High-Z
ns
20
25
25
45
tDW
tDH
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
ns
ns
ns
0
5
tOW
tWC
Address
CE1#s
CE2s
tWR
tCW
(See Note 1)
tAW
tCW
(See Note 1)
tWP
(See Note 4)
WE#
tAS
(See Note 3)
tDH
tDW
Data In
Data Out
High-Z
Data Valid
High-Z
tWHZ
tOW
Data Undefined
Notes:
1. WE# controlled.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 28. Pseudo SRAM Write Cycle—WE# Control
October 14, 2002
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61
P R E L I M I N A R Y
PSEUDO SRAM AC CHARACTERISTICS
tWC
Address
tAS (See Note 2 )
tCW
tWR (See Note 4)
(See Note 3)
CE1#s
tAW
CE2s
tBW
UB#s, LB#s
tWP
(See Note 5)
WE#
tDW
tDH
Data Valid
Data In
Data Out
High-Z
High-Z
Notes:
1. CE1#s controlled.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low
when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation.
A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 29. Pseudo SRAM Write Cycle—CE1#s Control
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October 14, 2002
P R E L I M I N A R Y
PSEUDO SRAM AC CHARACTERISTICS
tWC
Address
CE1#s
tCW
(See Note 2)
tWR (See Note 3)
tAW
tCW (See Note 2)
CE2s
tBW
UB#s, LB#s
tAS
tWP
(See Note 4)
(See Note 5)
WE#
tDW
tDH
Data In
Data Out
Data Valid
High-Z
High-Z
Notes:
1. UB#s and LB#s controlled.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low
when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation.
A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 30. Pseudo SRAM Write Cycle—
UB#s and LB#s Control
October 14, 2002
Am50DL9608G
63
P R E L I M I N A R Y
FLASH ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1) Max (Note 2) Unit
Comments
Sector Erase Time
0.4
56
28
4
5
sec
Excludes 00h
programming
prior to erasure (Note 4)
Am29DL640G
Am29DL320G
Chip Erase Time
sec
Accelerated Word Program Time
Word Program Time
120
210
84
µs
µs
7
Excludes system level
overhead (Note 5)
Am29DL640G
Am29DL320G
28
14
Chip Program Time
(Note 3)
sec
42
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
22 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
+100 mA
V
CC Current
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
11
Max
14
Unit
pF
CIN
COUT
CIN2
Output Capacitance
VOUT = 0
VIN = 0
12
14
17
16
pF
Control Pin Capacitance
WP#/ACC Pin Capacitance
16
pF
CIN3
VIN = 0
20
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
64
Am50DL9608G
October 14, 2002
P R E L I M I N A R Y
FLASH DATA RETENTION
Parameter Description
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
PSRAM DATA RETENTION
Parameter
Parameter Description
Symbol
Min
Typ
Max
Unit
V
Test Setup
VDR
IDR
VCC for Data Retention
Data Retention Current
CS1#s ≥ VCC – 0.2 V (Note 1)
2.4
3.3
70
VCC = 1.8 V, CE1#s ≥ VCC – 0.2 V
(Note 1)
µA
tSDR
tRDR
Data Retention Set-Up Time
Recovery Time
0
ns
ns
See data retention waveforms
tRC
Notes:
1. CE1#s ≥ VCC – 0.2 V, CE2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled), CIOs = VSS or VCC
.
2. Typical values are not 100% tested.
Data Retention Mode
tRDR
tSDR
VCC
2.7V
2.2V
VDR
CE1#s ≥ VCC
-0.2 V
CE1#s
GND
Figure 31. CE1#s Controlled Data Retention Mode
Data Retention Mode
VCC
2.7 V
CE2s
tSDR
tRDR
VDR
<
CE2s
0.2 V
0.4 V
GND
Figure 32. CE2s Controlled Data Retention Mode
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P R E L I M I N A R Y
PHYSICAL DIMENSIONS
FTA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm
A
D1
D
eD
0.15
(2X)
C
10
9
8
7
6
5
4
3
2
1
SE
7
E
B
E1
eE
L
J
H
G
F
E
D
C
B
A
M
K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
6
73X
b
0.15
0.08
M
C
C
A B
M
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
PACKAGE
JEDEC
FTA 073
N/A
8.00 mm x 11.60 mm
PACKAGE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL
A
MIN.
NOM.
MAX.
e
---
---
1.40
0.35
1.11
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
A1
0.25
1.00
---
---
BALL HEIGHT
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
D
11.60 BSC.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
8.00 BSC.
8.80 BSC.
BODY SIZE
D1
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
7.20 BSC.
12
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MD
ME
n
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
10
MATRIX SIZE E DIRECTION
BALL COUNT
73
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ob
0.30
0.35
0.40
BALL DIAMETER
BALL PITCH
eE
0.80 BSC
0.80 BSC
0.40 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eD
BALL PITCH
SD/SE
SOLDER BALL PLACEMENT
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
A2,A3,A4,A5,A6,A7,A8,A9
B2,B3,B4,B7,B8,B9,C2,C9,C10
D1,D10,E1,E10,H1,H10,J1,J10
K1,K2,K9,K10,L2,L3,L4,L7,L8,L9
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALL
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTION OR OTHER MEANS.
3159\38.14A
66
Am50DL9608G
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P R E L I M I N A R Y
REVISION SUMMARY
Revision A (October 7, 2002)
Revision A+1 (October 14, 2002)
Initial release.
Flash DC Characteristics
Added CMOS compatible table.
Trademarks
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
October 14, 2002
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