MB3769APF-XXXE1 [SPANSION]
Switching Controller;
| 型号： | MB3769APF-XXXE1 |
| 厂家： | 
SPANSION |
| 描述： | Switching Controller 开关 光电二极管 |
| 文件： | 总33页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Spansion® Analog and Microcontroller
Products
The following document contains information on Spansion analog and microcontroller products. Although the
document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion
will continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal document improvements and are noted in the document revision
summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a
revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “MB”. To order these products, please use
only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory, analog, and
microcontroller products and solutions.
FUJITSU MICROELECTRONICS
DATA SHEET
DS04-27202-6Ea
ASSP
BIPOLAR
SWITCHING REGULATOR
CONTROLLER
MB3769A
■ DESCRIPTION
The Fujitsu Microelectronics MB3769A is a pulse-width-modulation controller which is applied to fixed frequency
pulse modulation technique. The MB3769A contains wide band width Op-Amp and high speed comparator to
construct very high speed switching regulator system up to 700 kHz. Output is suitable for power MOS FET drive
owing to adoption of totem pole output.
The MB3769A provides stand-by mode at low voltage power supply when it is applied in primary control system.
■ FEATURES
• High frequency oscillator (f = 1 kHz to 700 kHz)
• On-chip wide band frequency operation amplifier (BW = 8 MHz Typ)
• On-chip high speed comparator (td = 120 ns Typ)
• Internal reference voltage generator provides a stable reference supply (5 V ± 2%)
• Low power dissipation (1.5 mA Typ at standby mode, 8 mA Typ at operating mode)
• Output current ± 100 mA (± 600 mA at peak)
• High speed switching operation (tr = 60 ns, tf = 30 ns, CL = 1000 pF Typ)
• Adjustable Dead-time
• On-chip soft start and quick shut down functions
• Internal circuitry prohibits double pulse at dynamic current limit operation
• Under voltage lock out function (OFF to ON: 10 V Typ, ON to OFF: 8 V Typ)
• On-chip output shut down circuit with latch function at over voltage
• On-chip Zener diode (15 V)
• One type of package (SOP-16pin : 1 type)
■ APPLICATIONS
• Power supply module
• Industrial Equipment
• AC/DC Converter
etc.
Copyright©1994-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2006.5
MB3769A
■ PIN ASSIGNMENT
(TOP VIEW)
+IN (OP)
-IN (OP)
1
2
3
+IN (C)
-IN (C)
VREF
OVP
16
15
14
FB
DTC
4
5
6
7
8
13
12
11
10
9
VCC
CT
RT
VZ
GND
VL
VH
OUT
(FPT-16P-M06)
2
MB3769A
■ BLOCK DIAGRAM
Fig. 1 - MB3769A Block Diagram
Over Current Detection Comparator
-IN (C)
+IN (C)
15
16
-
S
R
Q
+
-
10
9
VH
+
+
+
+
+
1.85 V
PWM
Comp.
+
OUT
VREF
1.8 V
-
DTC
4
8
STB
VL
STB
FB
3
1
+IN (OP)
+
Error
Amp
-IN (OP)
OVP
-
2
Over Voltage Detector
13
+
-
S
R
Q
Power
off
2.5 V
1.5 V to 3.5 V
C T
5
6
Triangle Wave
+
-
R T
Oscillator
(2.5 V)
8/10 V
STB
V CC
12
15.4 V
5.0 + 0.1 V
-
Reference
Regulator
V Z
11
7
14
VREF
+
30 kΩ
GND
3
MB3769A
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min
Max
20
Power Supply Voltage
Output Current
VCC
IOUT
V
mA
V
120 (660*1)
Operation Amp Input Voltage
Power Dissipation : SOP
Storage Temperature
Vin (OP)
PD
VCC + 0.3 (≤ 20)
620*2
mW
°C
TSTG
-55
+125
*1 : Duty ≤ 5%
*2 : Ta = + 25 °C, SOP package is mounted on the epoxy board. (4 cm x 4 cm x 0.15 cm)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
4
MB3769A
■ RECOMMENDED OPERATING CONDITIONS
SOP package
Parameter
Symbol
Unit
Max
Min
12
-100
-600
-0.2
-
Typ
Power Supply Voltage
VCC
IOUT
15
18
+100
+600
VCC-3
0.3
V
mA
mA
V
Output Current (DC)
Output Current (Peak)
Operation Amp Input voltage
FB Sink Current
-
IOUT PEAK
VINOP
-
0 to VREF
ISINK
-
-
mA
mA
V
FB Source Current
ISOURCE
-
2
+
VINC
-0.3
-0.3
-
0 to 3
0 to 2
2
VCC
2.5
Comparator Input Voltage
-
VINC
V
Reference Section Output Current
Timing Resistor
IREF
RT
10
mA
kΩ
pF
kHz
mA
°C
9
18
50
Timing Capacitor
CT
100
1
680
100
-
106
Oscillator Frequency
fOSC
IZ
700
5
Zener Current
-
Operating Ambient Temperature: SOP
Ta
-30
+25
+75
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
5
MB3769A
■ ELECTRICAL CHARACTERISTICS
(VCC=15V, Ta=+25°C)
Value
Parameter
Symbol
Condition
Unit
Min
Typ
5.0
2
Max
5.1
15
Output Voltage
VREF
∆VRIN
∆VRLD
∆VRTEMP
ISC
IREF = 1 mA
12 V ≤ VCC ≤ 18 V
1 mA ≤ IREF ≤10 mA
-30 °C ≤ Ta ≤ +85 °C
VREF = 0 V
4.9
V
mV
Input Regulation
Load Regulation
Temp. Stability
-
-
Reference
Section
-1
-15
±750
-
mV
-
±200
40
µV/ °C
mA
Short Circuit Output Current
15
RT = 18 kΩ
CT = 680 pF
Oscillator Frequency
fOSC
90
100
110
kHz
Oscillator
Section
Voltage Stability
Temp. Stability
Input Bias Current
Max. Duty Cycle
Duty Cycle Set
0% Duty
∆fOSCIN
∆fOSC /∆T
ID
12 V ≤ VCC ≤ 18 V
-30 °C ≤ Ta ≤ +85 °C
-
-
-
±0.03
±2
-
%
%
-
-
2
10
85
55
µA
%
Dmax
Dset
Vd = 1.5 V
75
45
80
Vd = 0.5 VREF
50
%
Dead -time
Control
Section
VDO
VDM
VDH
-
-
-
3.5
1.85
-
3.8
V
V
V
Input
Cycle
Threshold
Voltage
Max. Duty
Cycle
1.55
4.5
-
-
VCC = 7 V,
IDTC = -0.3 mA
Discharge Voltage
Input Offset Voltage
Input Offset Current
Input Bias Current
VIO (OP)
IIO (OP)
IIR (OP)
VCM (OP)
Av (OP)
BW
V3 = 2.5 V
V3 = 2.5 V
-
-
±2
±30
-0.3
-
±10
mV
nA
µA
V
±300
V3 = 2.5 V
-1
-0.2
70
-
-
Common-Mode Input Voltage
Voltage Gain
12 V ≤ VCC ≤ 18 V
0.5 V ≤ V3 ≤ 4 V
Av = 0 dB
VCC -3
Error
Amplifier
Section
90
8
-
dB
MHz
V/µs
dB
V
Band Width
-
-
Slew Rate
SR
RL = 10 kΩ, Av = 0 dB
VIN = 0 V to 10 V
I3 = -2 mA
-
6
Common-Mode Rejection Rate
“H” Level Output Voltage
“L” Level Output Voltage
CMR
VOH
65
4.0
-
80
4.6
0.1
-
-
VOL
I3 = 0.3 mA
0.5
V
(Continued)
6
MB3769A
(Continued)
(VCC=15V, Ta=+25°C)
Value
Typ
±5
Parameter
Symbol
Condition
Unit
Max
Min
-
Input Offset Voltage
Input Bias Current
Common-Mode Input
VIO (C)
IIB (C)
VIN = 1 V
VIN = 1 V
±15
-
mV
-5
-1
µA
Current
VCM (C)
-
0
-
2.5
V
Comparator Voltage
Voltage Gain
AV (C)
td
-
-
200
120
3.5
-
250
3.8
-
V/V
ns
V
Response Time
50 mV over drive
-
-
PWM
Comparator
Section
0% Duty Cycle
VOPO
VOPM
VH
RT = 18 kΩ
CT = 680 pF
Max Duty Cycle
1.55
12.5
-
1.85
13.5
1.1
V
“H” Level Output Voltage
“L” Level Output Voltage
-
V
IOUT = -100 mA
IOUT = 100 mA
1.3
V
VL
Output
Section
CL = 1000 pF,
Rise Time
Fall Time
tr
tf
-
-
60
30
120
80
ns
ns
RL = ∞
CL = 1000 pF,
RL = ∞
Threshold Voltage
Input Current
VCC Reset
2.4
-1.0
2.0
9.2
7.2
2.5
-0.2
3.0
2.6
-
V
µA
V
VOVP
IIOVP
-
Over
Voltage
Detector
VIN = 0 V
4.5
10.8
8.8
VCC RST
VTHH
-
-
-
Under
Voltage
Out Stop
Off to On
10.0
8.0
V
On to Off
V
VTHL
RT = 18 kΩ
4 pin Open
Standby *
-
1.5
2.0
mA
ISTB
Supply
Current
Operating
ICC
VZ
IZ
RT = 18 kΩ
IZ = 1 mA
V11-7 = 1 V
-
-
-
8.0
12.0
mA
V
Zener Voltage
Zener Current
15.4
0.03
-
-
mA
* : VCC = 8V
7
MB3769A
Fig. 2 - MB3769A Test Circuit
1.0 V
15.0 V
OUTPUT
10 kΩ
16
15
14
13
12
11
VZ
10
9
+IN (C)
-IN (C)
VREF
OVP
VCC
VH
OUT
COMP
in
MB3769A
1000 pF
+IN (OP)
1
-IN (OP)
2
FB
3
DTC
CT
5
RT
6
GND
7
VL
8
4
680 pF
18 kΩ
VFB
VDTC
TEST INPUT
<tr, tf, td>
3.5 V Typ
Voltage at CT
1.5 V Typ
1.05 V
1.0 V
tr of COMP-in should
be within 20 ns.
COMP in
0.95 V
90%
50%
OUTPUT
10%
tr
tf
td
8
MB3769A
Fig. 3 - MB3769A Operating Timing
Quick Shutdown Operation
Soft Start Operation
Dead-Time
Input Voltage
3.5 V
1.85V
Triangle Wave
Form
1.5 V
Error Amp
Output
PWM Comparator
Output
Output Wave
Form
Comp. Current
-in Wave Form
Comp. Current
+in Wave Form
(1 V)
Comp. Current
Latch Output
2.5 V
Voltage at OVP
OVP Latch
(15 V)
10 V (Typ)
Power Supply
Voltage
8 V
(Typ)
3 V
0 V
Over Current Over Voltage
Detector Detector
Standby
Mode
Standby Mode
Over Voltage Detector
Latch OFF
9
MB3769A
■ FUNCTIONS
1. Error Amplifier
The error amplifier detects the output voltage of the switching regulator.
The error amplifier uses a high-speed operational amplifier with an 8 MHz bandwidth (typical) and 6 V/µs slew rate (typical).
For ease of use, the common mode input voltage ranges from -0.2 V to VCC-3 V. Figure 4 shows the equivalent circuit.
Fig. 4 - MB3769A Equivalent Circuit Differential Amp
VCC
VREF
To PWM
Comp.
-IN (OP)
150 Ω
+IN (OP)
700 µA
GND
Protection element
2. Overcurrent Detection Comparator
There are two methods for protection of the output transistor of this device from overcurrents; one restricts the transistor’s on-
time if an overcurrent that flows through the output transistor is detected from an average output current, and the other detects
an overcurrent in the external transistor (FET) and shuts the output down instantaneously. Using average output currents, the
peak current of the external transistor (FET) cannot be detected, so an output transistor with a large safe operation area (SOA)
margin is required.
For the method of detecting overcurrents in the external transistor (FET), the output transistor can be protected against a shorted
filter capacitor or power-on surge current.
The MB3769A uses dynamic current limiting to detect overcurrents in the output transistor (FET). A high-speed comparator
and flip-flop are built-in.
To detect overcurrents, compare the voltage at +IN(C) of current detection resistor connected the source of the output transistor
(FET), with the reference voltage (connected to -IN(C)) using a comparator. To prevent output oscillation during overcurrent, flip-
flop circuit protects against double pulses occurring within a cycle.
Theoutput ofovercurrent detector isORedwithothersignalsatthePWMcomparator. See the example“■ ApplicationExample”
for details on use.
Figure 5 shows the equivalent circuit of the over-current detection comparator.
10
MB3769A
Fig. 5 - MB3769A Equivalent Circuit Over Current Detection Comparator
VREF
To PWM
Comp.
-IN (C)
+IN (C)
Protection element
3. DTC: Dead Time Control (Soft-Start and Quick Shutdown)
The dead time control terminal and the error amplifier output are connected to the PWM comparator.
The maximum duty cycle for VDTC (voltage applied to pin 4) is obtained from the following formula (approximate value at low
frequency):
Duty Cycle = (3.5 - VDTC) x 50 (%) [0% ≤ duty cycle ≤ DMAX (80%)]
The dead time control terminal is used to provide soft start.
In Figure 6, the DTC terminal is connected to the VREF terminal through R and C. Because capacitor C does not charge
instantaneously when the power is turned on, the output transistor is kept turned off. The DTC input voltage and the output pulse
width increase gradually according to the RC time constant so that the control system operates safely.
Fig. 6 - MB3769A Soft Start Function
VREF
VREF
C
R
C
R1
R2
DTC
DTC
Soft Start
Soft Start + DTC
The quick shutdown function prevents soft start malfunction when the power is turned off and on quickly. After the power is shut
down, soft start is disabled because the DTC terminal has low electric potential from the beginning if the power is turned on
again before the capacitor is discharged. The MB3769A prevents this by turning on the discharge transistor to quickly discharge
the capacitor in the stand-by mode.
11
MB3769A
4. Triangular Wave Oscillator
The oscillation frequency is expressed by the following formula:
1
CT
RT
:µF
:kΩ
fOSC ~
[kHz]
0.8 x CT x RT + 0.0002 ms
For master/slave synchronized operation of several MB3769As, the CT and RT terminals of the master MB3769A are connected
in the usual way and the CT terminals of the master and slave device (s) are connected together. The slave MB3769A’s RT
terminal is connected to it’s VREF terminal to disable the slave’s oscillator. In this case, set 50/n kΩ (n is the number of master
and slave ICs) to the upper limit of RT so that internal bias currents do not stop the master oscillation.
Fig. 7 - MB3769A Synchronized Operation
master
slave
RT
RT
CT
VREF
CT
5. Overvoltage Detector
The overvoltage detection circuit shuts the system power down if the switching regulator’s output voltage is abnormal or if
abnormal voltage is appeared. The reference voltage is 2.5 V (VREF /2). The system power is shut down if the voltage at pin 13
rises above 2.5 V. The output is kept shut down by the latching circuit until the power supply is turned off (see Figure 3).
6. Stand-by Mode and Under-Voltage Lockout (UVLO)
Generally, VGS > 6 to 8 V is required to use power MOSFET for switching. UVLO is set so that output is on at VCC ≥ 10 V
(standard) when the power is turned on and is off at VCC ≤ 8 V (standard) when the power is turned off.
In the stand-by mode, the power supply current is limited to 2 mA or less when the output is inhibited by the UVLO circuit. When
the MB3769A is operated from the 100 VAC line, the power supply current is supplied through resistor R (Figure 8). That is, the
IC power supply current is supplied by the AC line through resistor R until operation starts. Current is then supplied from the
transformer tertiary winding, eliminating the need for a second power supply.
Two volts (typical) of hysteresis are provided for return from operation mode to stand-by mode not to return to stand-by mode
until output power is turned on or to avoid malfunction due to noise.
12
MB3769A
Fig. 8 - MB3769A Primary Control
R
C
MB3769A
7. Output Section
Because the OUT terminal (pin 9) carries a large current, the collector and emitter of the output transistor are brought out to the
VH and VL terminals. In principle, VH is connected to VCC and VL is connected to GND, but VH can be supplied from another
power supply (4 V to 18 V). Note that VL and GND should be connected as close to the IC package as possible. A capacitor of
0.1 µF or more is inserted between VH and VL (see Figure 9).
Fig. 9 - MB3769A Typical Connection Circuit Of Output
12
10
9
7
8
≥ 0.1 µF
13
MB3769A
■ APPLICATION EXAMPLE
Fig. 10 - MB3769A DC - DC Convertor
12 to 18 V
5 V
1 A
3.6 kΩ
2.4 kΩ
3.3kΩ
+IN (C) 16
IN (C) 15
VREF 14
OVP 13
1+IN (OP)
0.1 µF
10 kΩ
330 pF
2-IN (OP)
3FB
20 kΩ
100 kΩ
4DTC
5CT
MB3769A
VCC 12
VZ 11
6RT
VH 10
7GND
8VL
OUT 9
R
S
220 pF
C
10 kΩ
1 Ω
51 kΩ
18 kΩ
5.1kΩ
Overcurrent Protection Circuit
The waveform at the output FET source terminal is shown in Figure 11. The RC time constant must be chosen so that the voltage
glitch in the waveform does not cause erroneous overcurrent detection. This time constant is should be from 5 ns to 100 ns. A
detection current value depends on R or C because a waveform is weakened. To keep this glitch as small as possible, the
rectifiers on the transformer secondary winding must be the fast-recovery type.
Fig. 11 - MB3769A Output FET Source Point
Glitch
Point S waveform
14
MB3769A
Fig. 12 -Primary Control
100 VAC
R
-
+
-
+
+IN(OP) +IN(C)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
47 kΩ
-IN(OP) -IN(C)
FB
VREF
22
kΩ
4.7 µF
DTC
OVP
CT
VCC
VZ
RT
*: The resistance (22 Ω)
as an output current
limiter at pin 9 is
required when driving
the FET which is more
than 1000 pF (CGS).
GND
VH
*
22
Ω
VL
OUT
22
kΩ
15
kΩ
18
680
10 kΩ
kΩ
pF
Fig. 13 -Secondly Control
15 V
0 V
Secondly power supply
5.1 kΩ
12 V
39
kΩ
43
kΩ
1
2
3
4
5
6
7
8
+IN(C)
+IN(OP)
-IN(OP)
FB
16
15
14
13
12
11
1000
pF
10
27
kΩ kΩ
-IN(C)
VREF
51
kΩ
OVP
DTC
VCC
VZ
CT
RT
VH 10
GND
9
OUT
VL
680
pF
10
kΩ
18
kΩ
15
MB3769A
■ SHORT PROTECTION CIRCUIT
The system power can be shut down to protect the output against intermittent short-circuits or continuous
overloads. This protection circuit can be configured using the OVP input as shown in Figure 14.
Fig. 14 -Case I. (Over Protection Input)
Primary Mode
V0
(5V output)
15 kΩ
IN-B
PC1
OUT-B
8
PC2
3
4
8.2 kΩ
IN-A
500 Ω
HYS-A
MB3761
1
6
9
14
13
5
500 Ω
6.8 kΩ
MB3769A
20 kΩ
PC2
7
1 µF
10 kΩ
100 kΩ
PC1
Fig. 15 -Case II. (Over Protection Input)
Secondly Mode
V0 (5V output)
14
VREF
MB3769A
20 kΩ
15 kΩ
8
13
IN-B
IN-A
OUT-B
HYS-A
6
OVP
3
1
MB3761
8.2 kΩ
6.8 kΩ
2
1 µF
5
200 kΩ
16
MB3769A
■ HOW TO SYNCHRONIZE WITH OUTSIDE CLOCK
The MB3769A oscillator circuit is shown in Figure 16. CT charge and discharge currents are expressed by the following formula:
5 V
ICT = ±2 x I1 = ±
RT
Fig. 16 -Oscillator Circuit
VREF
500
Ω
500 Ω
1 kΩ
+
-
I1
S
R
3.5 V
2 x I1
2 x I1
Q
-
+
ICT
CT
RT
-
6
5
1.5 V
+
(4 x I1)
2.5 V
300
150Ω
Ω
This circuit shows that if the voltage at the CT terminal is set to 1.5 V or less, one oscillation cycle ends and the next cycle starts.
An example of an external synchronous clock circuit is shown in Figure 17.
Fig. 17 -Typical Connection of Synchronized Outside Clock Circuit
tcycle
ex. MB74HC04
5
VP
VP
tP
MB3769A
R(5.1 k Ω)
6
tcycle = 2.5 µs (fEXT = 400 kHz)
clamp circuit
(VL)
CT
tP
= 0.5 µs
RT
RT = 11 k Ω
The Figure 18 shows the CT terminal waveform.
Fig. 18 -Voltage Waveform at CT
VTH may be near 2.5 V. In this case, the maximum duty cycle is restricted
as shown in the formula below if tP’ = 0.
3.5 V
VTH
.
( 2.5 V)
.
1.85 V
VCT
(3.5 - 1.85) + (3.5 - VTH)
(3.5 - VL) + (3.5 - VTH)
Dmax=
≤ 59% (VL = 0 V: No clamp circuit)
VL
tP’
When VTH = 2.5 V, CT can be provided by followings.
1
(3.5 - VL) + (3.5 - VTH)
fOSC(3.5 - 1.5) x 2
tcycle - tP =
x
fOSC
17
MB3769A
1
fOSC ~
CT ~
0.8 x CT x RT
1
x
4
(tcycle - tP) [pF] (RT: kΩ, tcycle, tP: ns)
0.8 x RT
4.5 - VL
Make VL high for a large duty cycle for the clamp circuit. The circuits below can be used because the clamp voltage must be
much lower than 1.5 V.
Fig. 19 -Clamp Circuit
VREF
VREF
R1 (4.7 kΩ)
8
MB3761
5
(1.2 V)
3
4
(1.2 V)
820 Ω
0.1 µF
R2 (1.2 kΩ)
0.1 µF
A
B
In circuit A, R1 and R2 must be determined considering the effects of tP, R, or RT.
The transistor saturation voltage must be very small (<0.15 V) for any clamp circuit, so a transistor with a very small VCE (sat)
should be used.
18
MB3769A
■ SYNCHRONIZED OUTSIDE CLOCK CIRCUIT
Fig. 20
1.No Clamp Circuit (Connect with GND)
1 V
5 V
CT = 150 pF + Prove Capacitor (~ 15 pF)
RT = 11 kΩ
VP (5 V/div)
5 pin
MB74HC04
CT
CT (1 V/div)
VP
150 pF
5.1 kΩ
GND Level (CT)
OUT (10 V/div)
500 ns
10 V
Fig. 21
2.Clamp Circuit A (Dividing Resistor)
5 V
1 V
VP (5 V/div)
CT (1 V/div)
CT = 220 pF + Prove capacitor (~ 15 pF)
RT = 11 kΩ
5 pin
MB74HC04
CT
220 pF
VP
5.1 kΩ
GND Level (CT)
OUT (10 V/div)
VREF
4.7 kΩ
0.1
µF
1.2 kΩ
10 V
500 ns
Fig. 22
3.Clamp Circuit B (Apply MB3761)
5 V
1 V
CT = 220 pF + Prove capacitor (~ 15 pF)
RT = 11 kΩ
VP (5 V/div)
CT (1 V/div)
5 pin
MB74HC04
CT
220 pF
VP
5.1 kΩ
VREF
GND Level (CT)
OUT (10 V/div)
820 Ω
0.1 µF
8
3
MB3761
4
10 V
500 ns
5
19
MB3769A
Fig. 23 -Test Circuit
15 V (VCC)
12
10
1
14
15
16
2.4 kΩ
2.4 kΩ
2
3
4
5
MB3769A
2.5 V
9
OUT
6
7
8 13
11 kΩ
20
MB3769A
■ TYPICAL PERFORMANCE CHARACTERISTICS
Fig. 25 -Standby Current vs.
Operating Ambient Temperature
Fig. 24 -Power Supply Voltage vs.
Power Supply Current
2
1
VCC = 8 V
(Low Voltage stop of VCC)
OVP
operating
V13 = 5 V
10.0
8.0
Normal
operating
V13 = 0 V
OVP
operating
6.0
4.0
2.0
0.0
0.0
4.0
8.0
12.0 16.0
20.0
0
3
-30
+ 85
+ 0
+ 25
+ 50
Power Supply Voltage VCC (V)
Operating Ambient Temperature Ta (°C)
Fig. 26 -Reference Voltage
Fig. 27 -“L” level Output Voltage vs.
“L” level Output Current
5.1
5.0
VCC = 15 V
IREF = 1 mA
VCC = 15 V
Ta = +25 °C
±750 µV/C
2
1
0
0.2
0.4
0.6
0.8
4.9
0
“L” level Output Current IOL (mA)
-30
0
+ 25
+ 50
+ 85
Operating Ambient Temperature Ta (°C)
Fig. 28 -“H” level Output Voltage vs.
“H” level Output Current
5
4
VCC = 15 V
Ta = +25 °C
3
2
1
0
2
4
6
8
10
“H” level Output Current IOH (mA)
(Continued)
21
MB3769A
Fig. 30 -“H”, “L” level Output Voltage vs.
Oscillator Frequency
4
Fig. 29 -Oscillator Frequency vs. RT, CT
700
VH
500
400
VCC = 15 V
Ta = +25 °C
VH
VL
3
2
CT = 100 pF
300
200
VL
1
0
CT = 680 pF
CT = 220 pF
20 k
50 k 100 k 200 k
Frequency fOSC (Hz)
500 k 1 M
100
90
80
CT = 1000 pF
70
60
Fig. 32 -Oscillator Frequency vs.
Operating Ambient Temperature
VCC = 15 V
100 kHz
50
40
4
2
30
20
CT = 2200 pF
7 8 9 10 20
RT (kΩ), CT (pF)
300 kHz
500 kHz
0
30 40 50
70
60
-2
Target
fOSC = 100 kHz
±2 % typ
-4
-30
0
+ 25
+ 50
+ 85
Fig. 31 -Duty Cycle vs. Dead Time Control
Voltage
Operating Ambient Temperature Ta (°C)
100
VCC = 15 V
CT = 1000 pF
Ta = +25 °C
Fig. 33 -Dead Time Control Voltage vs.
Current(Standby Mode)
fOSC = 200 kHz
fOSC = 500 kHz
80
60
40
20
5.0
VCC = 7 V
Ta = +25 °C
4.0
3.0
2.0
1.0
0
0
1
2
3
4
5
0
-0.2 -0.4 -0.6 -0.8 -1.0 -1.2
Dead Time Control Current IDTC (mA)
Dead Time Control Voltage VDTC (V)
(Continued)
22
MB3769A
Fig. 34 -Gain/Phase vs. Frequency
(Set Gv = 60 dB)
Fig. 35 -Duty vs.
Operating Ambient Temperature
60
40
20
0
-180
-240
-300
-360
55
VCC = 15 V
Ta = +25 °C
VCC = 15 V
CL = 1000 pF
VDTC = 2.5 V
Phase
Gain
fOSC = 200 kHz
fOSC = 500 kHz
50
10 k
100 k
1 M
10 M
45
0
Frequency f (Hz)
-30
0
+ 25
+ 50
+ 85
Operating Ambient Temperature Ta (°C)
Fig. 36 -“L” level Output Voltage vs.
“L” level Output Current
VCC = 15 V
Ta = +25 °C
1.5
1.0
Fig. 38 -tr/tf of Output and td of Comparator
vs. Operating Ambient Temperature
160
VCC = 15 V
CL = 1000 pF
140
0.5
0
td
120
100
200
300
400
500
600
0
100
“L” level Output Current IOL (mA)
80
Fig. 37 -“H” level Output Voltage vs.
“H” level Output Current
tr
14.0
13.5
13.0
60
40
VCC = 15 V
Ta = +25 °C
tf
20
0
0
+ 25
+ 50
+ 85
-30
12.5
0
Operating Ambient Temperature Ta (°C)
0
100
200 300
400
500
600
“H” level Output Current IOH (mA)
(Continued)
23
MB3769A
(Continued)
Fig. 39 -OVP Latch Standby Power Supply Current
Fig. 40 -OVP Supply Voltage Reset vs.
Operating Ambient Temperature
vs. Operating Ambient Temperature
5
4
3
2
6
VCC = 8 V
4 pin open
13 pin = 3 V
5
4
3
1
0
2
0
+ 20 + 40 + 60 + 80 + 100
-40 -20
0
+ 20 + 40 + 60 + 80 + 100
-40 -20
0
Operating Ambient Temperature Ta (°C)
Operating Ambient Temperature Ta (°C)
24
MB3769A
■ NOTES ON USE
• Take account of common impedance when designing the earth line on a printed wiring board.
• Take measures against static electricity.
- For semiconductors, use antistatic or conductive containers.
- When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container.
- The work table, tools and measuring instruments must be grounded.
- The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series.
• Do not apply a negative voltage
- Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in
malfunction.
■ ORDERING INFORMATION
Part number
MB3769APF-■■■
MB3769APF-■■■E1
Package
Remarks
16-pin plastic SOP
(FPT-16P-M06)
Conventional version
16-pin plastic SOP
(FPT-16P-M06)
Lead Free version
■ RoHS Compliance Information of Lead (Pb) Free version
The LSI products of Fujitsu Microelectronics with “E1” are compliant with RoHS Directive , and has observed
the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB) , and polybro-
minated diphenyl ethers (PBDE) .
The product that conforms to this standard is added “E1” at the end of the part number.
■ MARKING FORMAT (Lead Free version)
MB3769A
XXXX XXX
SOP-16
E1
INDEX
Lead Free version
25
MB3769A
■ LABELING SAMPLE (Lead free version)
Lead free mark
JEITA logo JEDEC logo
MB123456P - 789 - GE1
(3N) 1MB123456P-789-GE1 1000
G
Pb
(3N)2 1561190005 107210
QC PASS
PCS
1,000
MB123456P - 789 - GE1
ASSEMBLED IN JAPAN
2006/03/01
MB123456P - 789 - GE1
1/1
1561190005
0605 - Z01A 1000
Lead Free version
26
MB3769A
■ MB3769APF-■■■E1 RECOMMENDEDCONDITIONSOFMOISTURE SENSITIVITY LEVEL
Item
Condition
IR (infrared reflow) , Manual soldering (partial heating method)
2 times
Mounting Method
Mounting times
Please use it within two years after
Before opening
Manufacture.
From opening to the 2nd
Less than 8 days
reflow
Storage period
When the storage period after
opening was exceeded
Please processes within 8 days
after baking (125 °C, 24H)
Storage conditions
5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
[Temperature Profile for FJ Standard IR Reflow]
(1) IR (infrared reflow)
H rank : 260 °C Max
260 °C
255 °C
170 °C
to
190 °C
(b)
(c)
(d)
(e)
RT
(a)
(d')
(a) Temperature Increase gradient : Average 1 °C/s to 4 °C/s
(b) Preliminary heating : Temperature 170 °C to 190 °C, 60s to 180s
(c) Temperature Increase gradient : Average 1 °C/s to 4 °C/s
(d) Actual heating
(d’)
: Temperature 260 °C Max; 255 °C or more, 10s or less
: Temperature 230 °C or more, 40s or less
or
Temperature 225 °C or more, 60s or less
or
Temperature 220 °C or more, 80s or less
(e) Cooling
: Natural cooling or forced cooling
Note : Temperature : the top of the package body
(2) Manual soldering (partial heating method)
Conditions : Temperature 400 °C Max
Times
: 5 s max/pin
27
MB3769A
■ PACKAGE DIMENSION
16-pin plastic SOP
Lead pitch
1.27 mm
5.3 × 10.15 mm
Gullwing
Package width
package length
×
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
2.25 mm MAX
0.20 g
Code
(Reference)
P-SOP16-5.3×10.15-1.27
(FPT-16P-M06)
16-pin plastic SOP
(FPT-16P-M06)
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
0.17 +–00..0043
*110.15 +–00..2205 .400 –+..000180
.007 +–..000021
16
9
2 5.30±0.30 7.80±0.40
(.209±.012) (.307±.016)
*
INDEX
Details of "A" part
2.00 +–00..1255
(Mounting height)
.079 –+..000160
0.25(.010)
"A"
1
8
1.27(.050)
0~8˚
0.47±0.08
(.019±.003)
M
0.13(.005)
0.50±0.20
(.020±.008)
0.10 +–00..0150
.004 +–..000024
0.60±0.15
(Stand off)
(.024±.006)
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002 FUJITSU LIMITED F16015S-c-4-7
28
MB3769A
MEMO
29
MB3769A
MEMO
30
MB3769A
MEMO
31
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE LTD.
151 Lorong Chuan, #05-08 New Tech Park,
Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm.3102, Bund Center, No.222 Yan An Road(E),
Shanghai 200002, China
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen,
Germany
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-
ing the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited Strategic Business Development Dept.
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