MB84VD22184FM [SPANSION]

SPANSION MCP

Data Sheet

TM

September 2003

TM

This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and

Fujitsu. Although the document is marked with the name of the company that originally developed the specification,

these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a SPANSION

revisions will occur when appropriate, and changes will be noted in a revision summary.

TM

product. Future routine

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these

products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about SPANSION

solutions.

TM

memory

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-50230-2E

Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM

CMOS

32M (×16) FLASH MEMORY &

4M (×16) STATIC RAM

MB84VD22184FM

-70

/MB84VD22194FM

-70

s

FEATURES

• Power Supply Voltage of 2.7 V to 3.1 V

• High Performance

70 ns maximum access time (Flash)

70 ns maximum access time (SRAM)

• Operating Temperature

–30

°C

to +85

°C

• Package 56-ball FBGA

(Continued)

s

PRODUCT LINE UP

Part No.

Supply Voltage(V)

Max Address Access Time (ns)

Max CE Access Time (ns)

Max OE Access Time (ns)

V

CC

f= 3.0V

70

70

30

VD22184FM / VD22194FM

+0.1 V

–0.3 V

V

CC

s= 3.0V

70

70

35

+0.1 V

–0.3 V

Note: Both V

CC

f and V

CC

s must be in recommended operation range when either part is being accessed.

s

PACKAGE

56-ball plastic FBGA

(BGA-56P-M03)

MB84VD22184FM/VD22194FM

-70

(Continued)

— FLASH MEMORY

• Simultaneous Read/Write Operations (Dual Bank)

Bank 1 : 8 Mbit (8 KB

×

8 and 64 KB

×

15)

Bank 2 : 24 Mbit (64 KB

×

48)

Host system can program or erase in one bank, and then read immediately and simultaneously from the other

bank with zero latency between read and write operations.

Read-while-erase

Read-while-program

• Minimum 100,000 Write/Erase Cycles

• Sector Erase Architecture

Eight 4K word and sixty-three 32K word sectors in word mode

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

MB84VD22184: Top sector

MB84VD22194: Bottom sector

• Embedded Erase

TM

* Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program

TM

* Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion

• Ready-Busy Output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic Sleep Mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low V

CC

f Write Inhibit

≤

2.5 V

• HiddenROM Region

256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC Input Pin

At V

IL

, allows protection of “outermost” 2

×

8 bytes on boot sectors, regardless of sector protection/unprotection

status.

At V

IH

, allows removal of boot sector protection

At V

ACC

, increases program performance

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

• Please refer to “MBM29DL34TF/BF” Datasheet in Detailed Function

— SRAM

• Power Dissipation

Operating : 40 mA Max

Standby : 10

µA

Max

• Power Down Features using CE1s and CE2s

• Data Retention Supply Voltage: 1.5 V to 3.1 V

• CE1s and CE2s Chip Select

• Byte Data Control: LB (DQ

7

to DQ

0

), UB (DQ

15

to DQ

8

)

*: Embedded Erase

TM

and Embedded Program

TM

are trademarks of Advanced Micro Devices, Inc.

2

MB84VD22184FM/VD22194FM

-70

s

PIN ASSIGNMENT

(Top View)

Marking side

B8

A

15

A7

A

11

A6

A

8

A5

WE

A4

B7

A

12

B6

A

19

B5

CE2s

B4

C8

N.C.

C7

A

13

C6

A

9

C5

A20

C4

RY/BY

C3

A

18

C2

A

5

C1

A

2

D8

N.C.

D7

A

14

D6

A

10

E8

A

16

E7

N.C.

E6

DQ

6

F8

N.C.

F7

DQ

15

F6

DQ

13

F5

DQ

4

F4

DQ

3

G8

Vss

G7

DQ

7

G6

DQ

12

G5

Vccs

G4

Vccf

G3

DQ

10

G2

DQ

0

G1

CE1s

H7

DQ

14

H6

DQ

5

H5

N.C.

H4

DQ

11

H3

DQ

2

H2

DQ

8

WP/ACC RESET

A3

LB

A2

A

7

B3

UB

B2

A

6

B1

A

3

D3

A

17

D2

A

4

D1

A

1

E3

DQ

1

E2

V

SS

E1

A

0

F3

DQ

9

F2

OE

F1

CEf

(BGA-56P-M03)

3

MB84VD22184FM/VD22194FM

-70

s

PIN DESCRIPTION

Pin Name

A

17

to A

0

A

20

to A

18

DQ

15

to DQ

0

CEf

CE1s

CE2s

OE

WE

RY/BY

UB

LB

RESET

WP/ACC

N.C.

V

SS

V

CC

f

V

CC

s

Function

Address Inputs (Common)

Address Inputs (Flash)

Data Inputs / Outputs (Common)

Chip Enable (Flash)

Chip Enable (SRAM)

Chip Enable (SRAM)

Output Enable (Common)

Write Enable (Common)

Ready/Busy Outputs (Flash) Open Drain

Output

Upper Byte Control (SRAM)

Lower Byte Control (SRAM)

Hardware Reset Pin / Sector Protection

Unlock (Flash)

Write Protect / Acceleration (Flash)

No Internal Connection

Device Ground (Common)

Device Power Supply (Flash)

Device Power Supply (SRAM)

Input/Output

I

I

I/O

I

I

I

I

I

O

I

I

I

I

—

Power

Power

Power

4