MB84VD22184FM中文资料_数据手册_规格书

TM

SPANSION MCP

Data Sheet

September 2003

This document specifies SPANSION^TMmemory products that are now offered by both Advanced Micro Devices and

Fujitsu. Although the document is marked with the name of the company that originally developed the specification,

these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a SPANSION^TMproduct. Future routine

revisions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these

products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about SPANSION^TMmemory

solutions.

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-50230-2E

Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM

CMOS

32M (×16) FLASH MEMORY &

4M (×16) STATIC RAM

MB84VD22184FM-70/MB84VD22194FM-70

■ FEATURES

• Power Supply Voltage of 2.7 V to 3.1 V

• High Performance

70 ns maximum access time (Flash)

70 ns maximum access time (SRAM)

• Operating Temperature

–30 °C to +85 °C

• Package 56-ball FBGA

(Continued)

■ PRODUCT LINE UP

Part No.

VD22184FM / VD22194FM

+0.1 V

–0.3 V

+0.1 V

–0.3 V

Supply Voltage(V)

V^CCf= 3.0V

V^CCs= 3.0V

Max Address Access Time (ns)

Max CE Access Time (ns)

Max OE Access Time (ns)

70

30

70

35

Note: Both VCCf and VCCs must be in recommended operation range when either part is being accessed.

■ PACKAGE

56-ball plastic FBGA

(BGA-56P-M03)

MB84VD22184FM/VD22194FM^-70

(Continued)

— FLASH MEMORY

• Simultaneous Read/Write Operations (Dual Bank)

Bank 1 : 8 Mbit (8 KB × 8 and 64 KB × 15)

Bank 2 : 24 Mbit (64 KB × 48)

Host system can program or erase in one bank, and then read immediately and simultaneously from the other

bank with zero latency between read and write operations.

Read-while-erase

Read-while-program

• Minimum 100,000 Write/Erase Cycles

• Sector Erase Architecture

Eight 4K word and sixty-three 32K word sectors in word mode

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

MB84VD22184: Top sector

MB84VD22194: Bottom sector

• Embedded Erase^TM* Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TM* Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion

• Ready-Busy Output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic Sleep Mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low V^CCf Write Inhibit ≤ 2.5 V

• HiddenROM Region

256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC Input Pin

At V^IL, allows protection of “outermost” 2 × 8 bytes on boot sectors, regardless of sector protection/unprotection

status.

At VIH, allows removal of boot sector protection

At VACC, increases program performance

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

• Please refer to “MBM29DL34TF/BF” Datasheet in Detailed Function

— SRAM

• Power Dissipation

Operating: 40 mA Max

Standby : 10 µA Max

• Power Down Features using CE1s and CE2s

• Data Retention Supply Voltage: 1.5 V to 3.1 V

• CE1s and CE2s Chip Select

• Byte Data Control: LB (DQ⁷to DQ⁰), UB (DQ¹⁵to DQ⁸)

*: Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

2

MB84VD22184FM/VD22194FM^-70

■ PIN ASSIGNMENT

(Top View)

Marking side

B8

C8

N.C.

C7

D8

N.C.

D7

E8

F8

N.C.

F7

G8

Vss

G7

A

15

A

16

A7

B7

E7

N.C.

E6

H7

DQ14

H6

A

11

A

12

A

13

A

14

DQ15

F6

DQ

7

A6

B6

C6

D6

G6

A

8

A

19

A

9

A

10

DQ

6

DQ13

F5

DQ12

G5

DQ5

A5

WE

A4

B5

C5

A20

C4

H5

N.C.

H4

CE2s

B4

DQ

4

3

9

Vccs

G4

F4

WP/ACC RESET RY/BY

DQ

F3

Vccf

G3

DQ11

H3

A3

LB

A2

B3

UB

B2

C3

D3

E3

A

18

A

17

DQ

1

DQ

F2

DQ10

G2

DQ

H2

DQ

2

C2

D2

E2

A

7

A

6

A

5

A

4

V

SS

OE

F1

DQ

0

8

B1

C1

D1

E1

G1

A

3

A

2

A

1

A

0

CEf

CE1s

(BGA-56P-M03)

3

MB84VD22184FM/VD22194FM^-70

■ PIN DESCRIPTION

Pin Name

A¹⁷to A0

A²⁰to A18

DQ¹⁵to DQ0

CEf

Function

Address Inputs (Common)

Address Inputs (Flash)

Data Inputs / Outputs (Common)

Chip Enable (Flash)

Input/Output

I

I/O

I

CE1s

Chip Enable (SRAM)

CE2s

Chip Enable (SRAM)

OE

Output Enable (Common)

Write Enable (Common)

WE

Ready/Busy Outputs (Flash) Open Drain

Output

RY/BY

O

UB

LB

Upper Byte Control (SRAM)

Lower Byte Control (SRAM)

I

Hardware Reset Pin / Sector Protection

Unlock (Flash)

RESET

I

WP/ACC

N.C.

Write Protect / Acceleration (Flash)

No Internal Connection

I

—

VSS

Device Ground (Common)

Device Power Supply (Flash)

Device Power Supply (SRAM)

Power

V^CCf

V^CCs

4

MB84VD22184FM/VD22194FM^-70

■ BLOCK DIAGRAM

V^CCf

V^SS

A²⁰to A⁰

RY/BY

A²⁰to A⁰

WP/ACC

RESET

CEf

32 M bit

Flash Memory

DQ¹⁵to DQ⁰

V^CCs

V^SS

A¹⁷to A⁰

DQ¹⁵to DQ⁰

4 M bit

Static RAM

LB

UB

WE

OE

CE1s

CE2s

5

MB84VD22184FM/VD22194FM^-70

■ DEVICE BUS OPERATIONS

• User Bus Operations

WP/

Operation *^1,*³

ACC

CEf CE1s CE2s OE WE LB UB DQ⁷to DQ⁰DQ¹⁵to DQ⁸RESET

5

*

H

X

L

Full Standby

H

L

X

High-Z

H

X

H

X

H

X

H

X

H

High-Z

L

H

Output Disable

H

X

H

X

H

X

L

X

L

X

L

H

L

H

L

X

High-Z

D^OUT

D^IN

High-Z

DOUT

DIN

Read from Flash *²

Write to Flash

L

H

X

L

H

L

H

L

D^OUT

High-Z

DOUT

D^IN

DOUT

High-Z

DIN

Read from SRAM

Write to SRAM

H

L

H

L

H

L

H

X

H

L

H

X

H

L

High-Z

DIN

H

High-Z

Temporary Sector

X

High-Z

X

High-Z

X

VID

L

X

L

Group Unprotection*⁴

H

X

L

Flash Hardware Reset

Boot Block Sector Write

Protection

X

Legend: L = V^IL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.

*1 : Other operations except for indicated this column are inhibited.

*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.

*4 : It is also used for the extended sector group protections.

*5 : WP/ACC = VIL; protection of boot sectors.

WP/ACC = VIH; removal of boot sectors protection.

WP/ACC = VACC (9V); Program time will reduce by 40%.

6

MB84VD22184FM/VD22194FM^-70

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

Min

–55

–30

Max

+125

Storage Temperature

Tstg

T^A

°C

V

Ambient Temperature with Power Applied

+85

V^CCf + 0.3

V^CCs + 0.4

+3.3

Voltage with Respect to Ground All pins

except RESET, WP/ACC *¹

VIN, VOUT

–0.3

V

VCCf/VCCs Supply *¹

RESET *²

VCCf, VCCs

VIN

–0.3

–0.5

V

+13.0

V

WP/ACC *³

VIN

+10.5

V

*1 : Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot

VSS to –1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf+0.3 V or

VCCs+0.4 V. During voltage transitions, input or I/O pins may overshoot to VCCf+1.0 V or VCCs + 1.0 V for periods

of up to 20 ns.

*2 : Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pins may undershoot

VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs)

does not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to

+14.0 V for periods of up to 20 ns.

*3 : Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot

Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may

overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Unit

Min

–30

+2.7

Max

+85

Ambient Temperature

V^CCf/VCCs Supply Voltages

T^A

°C

V

Vccf, Vccs

+3.1

Note: Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

7

MB84VD22184FM/VD22194FM^-70

■ ELECTRICAL CHARACTERISTICS

1. DC CHARACTERISTICS

Value

Typ

—

Parameter

Symbol

Test Conditions

Unit

Min

–1.0

Max

+1.0

Input Leakage Current

Output Leakage Current

I^LI

VIN = VSS to VCCf, VCCs

µA

ILO

VOUT = VSS to VCCf, VCCs

—

RESET Inputs Leakage

Current

VCCf= VCCf Max, VCCs= VCCs Max,

RESET = 12.5V

I^LIT

—

35

µA

tCYCLE = 5 MHz

CEf = VIL,

—

18

4

mA

Flash V^CCActive Current

(Read) *¹

ICC1f

OE = VIH

tCYCLE = 1 MHz

Flash VCC Active Current

(Program/Erase) *²

ICC2f

ICC3f

ICC4f

ICC5f

I^LIA

CEf = VIL, OE = VIH

—

30

48

35

20

mA

Flash V^CCActive Current

(Read-While-Program) *⁵

Flash V^CCActive Current

(Read-While-Erase) *⁵

Flash V^CCActive Current

(Erase-Suspend-Program)

ACC Input Leakage

Current

VCCf= VCCf Max, VCCs= VCCs Max,

WP/ACC = VACC Max

V^CCs = VCCs Max,

SRAM V^CCActive Current

Flash V^CCStandby Current

ICC1s

ICC2s

CE1s = VIL,

CE2s = V^IH

tCYCLE =10 MHz

—

40

mA

tCYCLE = 10 MHz

—

40

8

mA

CE1s = 0.2 V,

CE2s = VCCs – 0.2 V

t^CYCLE= 1 MHz

V^CCf = VCCf Max, CEf = VCCf ± 0.3 V

RESET = VCCf ± 0.3 V,

WP/ACC = VCCf± 0.3 V

ISB1f

ISB2f

—

5

µA

Flash VCC Standby Current

(RESET)

V^CCf = VCCf Max, RESET = VSS ± 0.3 V,

WP/ACC = VCCf± 0.3 V

V^CCf = VCCf Max, CEf = VSS ± 0.3 V

RESET = VCCf ± 0.3 V,

Flash V^CCCurrent

ISB3f

—

5

µA

(Automatic Sleep Mode) *³

WP/ACC = VCCf± 0.3 V

V^IN= VCCf± 0.3 V or VSS ± 0.3 V

CE1s > VCCs – 0.2 V, CE2s > VCCs – 0.2 V

LB = UB > VCCs–0.2 V or < 0.2V

SRAM V^CCStandby Current

ISB1s

—

10

µA

CE1s > VCCs – 0.2 V or < 0.2V,

SRAM VCC Standby Current ISB2s CE2s < 0.2 V

LB = UB > VCCs–0.2 V or < 0.2V

(Continued)

8

MB84VD22184FM/VD22194FM^-70

(Continued)

Value

Parameter

Symbol

Test Conditions

Unit

Min

–0.3

2.2

Typ

—

Max

0.5

Input Low Level

Input High Level

V^IL

V^IH

—

V

—

V^CC+0.3*⁶

Voltage for Sector

Protection, and Temporary

Sector Unprotection

(RESET) *⁴

VID

—

11.5

—

12.5

V

Voltage for Program

Acceleration (WP/ACC) *⁴

VACC

—

8.5

9.0

9.5

V

SRAM Output Low Level

SRAM Output High Level

Flash Output Low Level

Flash Output High Level

V^OL

V^OH

V^OL

V^OH

VCCs = VCCsMin, I^OL= 0.1 mA

VCCs = VCCsMin, I^OH= –0.1 mA

VCCf = VCCfMin, I^OL= 4.0 mA

VCCf = VCCfMin, I^OH= –0.1 mA

—

2.0

—

0.4

—

V

—

0.45

—

VCCs–0.4

Flash Low V^CCf Lock-Out

Voltage

V^LKO

—

2.3

—

2.5

V

*1 : The ICC current listed includes both the DC operating current and the frequency dependent component.

*2 : I^CCactive while Embedded Algorithm (program or erase) is in progress.

*3 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

*4 : Applicable for only VCCf applying.

*5 : Embedded Algorithm (program or erase) is in progress. (@5 MHz)

*6 : V^CCindicates lower of VCCf or VCCs.

9

MB84VD22184FM/VD22194FM^-70

2. AC CHARACTERISTICS

• CE Timing

Symbol

JEDEC Standard

Parameter

Test Setup

Min

Value

Unit

CE Recover Time

—

tCCR

—

0

ns

• Timing Diagram for alternating SRAM to Flash

CEf

t

CCR

tCCR

CE1s

CE2s

tCCR

• Flash Characteristics

Please refer to “■32M Flash Memory for MCP”.

• SRAM Characteristics,

Please refer to “■4M SRAM for MCP”.

10

MB84VD22184FM/VD22194FM^-70

■ 32 M FLASH MEMORY for MCP

1. Flexible Sector-erase Architecture on Flash Memory

• Eight 4 K words, and sixty three 32 K words.

• Individual-sector, multiple-sector, or bulk-erase capability.

1FFFFFh

SA70 : 8KB (4KW)

1FF000h

1FFFFFh

1F8000h

1F0000h

1E8000h

1E0000h

1D8000h

1D0000h

1C8000h

1C0000h

1B8000h

1B0000h

1A8000h

1A0000h

198000h

190000h

188000h

180000h

178000h

170000h

168000h

160000h

158000h

150000h

148000h

140000h

138000h

130000h

128000h

120000h

118000h

110000h

108000h

100000h

0F8000h

0F0000h

0E8000h

0E0000h

0D8000h

0D0000h

0C8000h

0C0000h

0B8000h

0B0000h

0A8000h

0A0000h

098000h

090000h

088000h

080000h

078000h

070000h

068000h

060000h

058000h

050000h

048000h

040000h

038000h

030000h

028000h

020000h

018000h

010000h

008000h

007000h

006000h

005000h

004000h

003000h

002000h

001000h

000000h

SA70 : 64KB (32KW)

SA69 : 64KB (32KW)

SA68 : 64KB (32KW)

SA67 : 64KB (32KW)

SA66 : 64KB (32KW)

SA65 : 64KB (32KW)

SA64 : 64KB (32KW)

SA63 : 64KB (32KW)

SA62 : 64KB (32KW)

SA61 : 64KB (32KW)

SA60 : 64KB (32KW)

SA59 : 64KB (32KW)

SA58 : 64KB (32KW)

SA57 : 64KB (32KW)

SA56 : 64KB (32KW)

SA55 : 64KB (32KW)

SA54 : 64KB (32KW)

SA53 : 64KB (32KW)

SA52 : 64KB (32KW)

SA51 : 64KB (32KW)

SA50 : 64KB (32KW)

SA49 : 64KB (32KW)

SA48 : 64KB (32KW)

SA47 : 64KB (32KW)

SA46 : 64KB (32KW)

SA45 : 64KB (32KW)

SA44 : 64KB (32KW)

SA43 : 64KB (32KW)

SA42 : 64KB (32KW)

SA41 : 64KB (32KW)

SA40 : 64KB (32KW)

SA39 : 64KB (32KW)

SA38 : 64KB (32KW)

SA37 : 64KB (32KW)

SA36 : 64KB (32KW)

SA35 : 64KB (32KW)

SA34 : 64KB (32KW)

SA33 : 64KB (32KW)

SA32 : 64KB (32KW)

SA31 : 64KB (32KW)

SA30 : 64KB (32KW)

SA29 : 64KB (32KW)

SA28 : 64KB (32KW)

SA27 : 64KB (32KW)

SA26 : 64KB (32KW)

SA25 : 64KB (32KW)

SA24 : 64KB (32KW)

SA23 : 64KB (32KW)

SA22 : 64KB (32KW)

SA21 : 64KB (32KW)

SA20 : 64KB (32KW)

SA19 : 64KB (32KW)

SA18 : 64KB (32KW)

SA17 : 64KB (32KW)

SA16 : 64KB (32KW)

SA15 : 64KB (32KW)

SA14 : 64KB (32KW)

SA13 : 64KB (32KW)

SA12 : 64KB (32KW)

SA11 : 64KB (32KW)

SA10 : 64KB (32KW)

SA9 : 64KB (32KW)

SA8 : 64KB (32KW)

SA7 : 8KB (4KW)

SA6 : 8KB (4KW)

SA5 : 8KB (4KW)

SA4 : 8KB (4KW)

SA3 : 8KB (4KW)

SA2 : 8KB (4KW)

SA1 : 8KB (4KW)

SA0 : 8KB (4KW)

SA69 : 8KB (4KW)

1FE000h

SA68 : 8KB (4KW)

1FD000h

SA67 : 8KB (4KW)

1FC000h

SA66 : 8KB (4KW)

1FB000h

SA65 : 8KB (4KW)

1FA000h

SA64 : 8KB (4KW)

1F9000h

SA63 : 8KB (4KW)

1F8000h

SA62 : 64KB (32KW)

1F0000h

SA61 : 64KB (32KW)

1E8000h

SA60 : 64KB (32KW)

1E0000h

SA59 : 64KB (32KW)

SA58 : 64KB (32KW)

1D8000h

1D0000h

Bank B

SA57 : 64KB (32KW)

1C8000h

SA56 : 64KB (32KW)

1C0000h

SA55 : 64KB (32KW)

1B8000h

SA54 : 64KB (32KW)

1B0000h

SA53 : 64KB (32KW)

1A8000h

SA52 : 64KB (32KW)

1A0000h

SA51 : 64KB (32KW)

198000h

SA50 : 64KB (32KW)

190000h

SA49 : 64KB (32KW)

188000h

SA48 : 64KB (32KW)

180000h

SA47 : 64KB (32KW)

178000h

SA46 : 64KB (32KW)

Bank B

170000h

168000h

160000h

158000h

150000h

148000h

140000h

138000h

130000h

128000h

120000h

118000h

110000h

108000h

100000h

0F8000h

0F0000h

0E8000h

0E0000h

0D8000h

0D0000h

0C8000h

0C0000h

0B8000h

0B0000h

0A8000h

0A0000h

098000h

090000h

088000h

080000h

078000h

070000h

068000h

060000h

058000h

050000h

048000h

040000h

038000h

030000h

028000h

020000h

018000h

010000h

008000h

000000h

SA45 : 64KB (32KW)

SA44 : 64KB (32KW)

SA43 : 64KB (32KW)

SA42 : 64KB (32KW)

SA41 : 64KB (32KW)

SA40 : 64KB (32KW)

SA39 : 64KB (32KW)

SA38 : 64KB (32KW)

SA37 : 64KB (32KW)

SA36 : 64KB (32KW)

SA35 : 64KB (32KW)

SA34 : 64KB (32KW)

SA33 : 64KB (32KW)

SA32 : 64KB (32KW)

SA31 : 64KB (32KW)

SA30 : 64KB (32KW)

SA29 : 64KB (32KW)

SA28 : 64KB (32KW)

SA27 : 64KB (32KW)

SA26 : 64KB (32KW)

SA25 : 64KB (32KW)

SA24 : 64KB (32KW)

SA23 : 64KB (32KW)

SA22 : 64KB (32KW)

SA21 : 64KB (32KW)

SA20 : 64KB (32KW)

SA19 : 64KB (32KW)

SA18 : 64KB (32KW)

SA17 : 64KB (32KW)

SA16 : 64KB (32KW)

SA15 : 64KB (32KW)

SA14 : 64KB (32KW)

SA13 : 64KB (32KW)

SA12 : 64KB (32KW)

SA11 : 64KB (32KW)

SA10 : 64KB (32KW)

SA9 : 64KB (32KW)

SA8 : 64KB (32KW)

SA7 : 64KB (32KW)

SA6 : 64KB (32KW)

SA5 : 64KB (32KW)

SA4 : 64KB (32KW)

SA3 : 64KB (32KW)

SA2 : 64KB (32KW)

SA1 : 64KB (32KW)

SA0 : 64KB (32KW)

Bank A

(Top Boot Block)

(Bottom Boot Block)

11

MB84VD22184FM/VD22194FM^-70

Sector Address Table (Top Boot Type)

Sector address

B

a

n

k

Bank

address

Sector size

(Kwords)

Sector

Address range

A²⁰

A¹⁹

0

1

A¹⁸

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

A¹³

X

A¹²

X

A¹¹

X

SA0

SA1

0

1

0

1

32

000000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

058000h to 05FFFFh

060000h to 067FFFh

068000h to 06FFFFh

070000h to 077FFFh

078000h to 07FFFFh

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

0A8000h to 0AFFFFh

0B0000h to 0B7FFFh

0B8000h to 0BFFFFh

0C0000h to 0C7FFFh

0C8000h to 0CFFFFh

0D0000h to 0D7FFFh

0D8000h to 0DFFFFh

0E0000h to 0E7FFFh

0E8000h to 0EFFFFh

0F0000h to 0F7FFFh

0F8000h to 0FFFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

B

a

n

k

B

(Continued)

12

MB84VD22184FM/VD22194FM^-70

(Continued)

Sector address

B

a

n

Bank

address

Sector size

Address range

(Kwords)

Sector

k

A²⁰

A¹⁹

0

1

A¹⁸

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

A¹¹

X

SA32

SA33

SA34

SA35

SA36

SA37

1

0

1

0

1

32

4

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

158000h to 15FFFFh

160000h to 167FFFh

168000h to 16FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

1A8000h to 1AFFFFh

1B0000h to 1B7FFFh

1B8000h to 1BFFFFh

1C0000h to 1C7FFFh

1C8000h to 1CFFFFh

1D0000h to 1D7FFFh

1D8000h to 1DFFFFh

1E0000h to 1E7FFFh

1E8000h to 1EFFFFh

1F0000h to 1F7FFFh

1F8000h to 1F8FFFh

1F9000h to 1F9FFFh

1FA000h to 1FAFFFh

1FB000h to 1FBFFFh

1FC000h to 1FCFFFh

1FD000h to 1FDFFFh

1FE000h to 1FEFFFh

1FF000h to 1FFFFFh

B

a

n

k

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

B

a

n

k

A

0

1

4

0

1

0

4

0

1

4

1

0

4

1

0

1

4

1

0

4

1

4

13

MB84VD22184FM/VD22194FM^-70

Sector Address Table (Bottom Boot Type)

Sector address

B

a

n

k

Bank

address

Sector size

(Kwords)

Sector

Address range

A²⁰

A¹⁹

1

0

A¹⁸

A¹⁷

1

0

1

0

1

0

1

0

A¹⁶

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A¹⁵

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A¹⁴

X

A¹³

X

A¹²

X

A¹¹

X

SA70

SA69

SA68

SA67

SA66

SA65

SA64

SA63

SA62

SA61

SA60

SA59

SA58

SA57

SA56

SA55

SA54

SA53

SA52

SA51

SA50

SA49

SA48

SA47

SA46

SA45

SA44

SA43

SA42

SA41

SA40

SA39

1

0

1

0

32

1F8000h to 1FFFFFh

1F0000h to 1F7FFFh

1E8000h to 1EFFFFh

1E0000h to 1E7FFFh

1D8000h to 1DFFFFh

1D0000h to 1D7FFFh

1C8000h to 1CFFFFh

1C0000h to 1C7FFFh

1B8000h to 1BFFFFh

1B0000h to 1B7FFFh

1A8000h to 1AFFFFh

1A0000h to 1A7FFFh

198000h to 19FFFFh

190000h to 197FFFh

188000h to 18FFFFh

180000h to 187FFFh

178000h to 17FFFFh

170000h to 177FFFh

168000h to 16FFFFh

160000h to 167FFFh

158000h to 15FFFFh

150000h to 157FFFh

148000h to 14FFFFh

140000h to 147FFFh

138000h to 13FFFFh

130000h to 137FFFh

128000h to 12FFFFh

120000h to 127FFFh

118000h to 11FFFFh

110000h to 117FFFh

108000h to 10FFFFh

100000h to 107FFFh

B

a

n

k

B

(Continued)

14

MB84VD22184FM/VD22194FM^-70

Sector address

B

a

n

k

Bank

address

Sector size

Address range

(Kwords)

Sector

A²⁰

A¹⁹

1

0

A¹⁸

A¹⁷

1

0

1

0

1

0

1

0

A¹⁶

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A¹⁵

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A¹⁴

X

1

A¹³

X

1

A¹²

X

1

A¹¹

X

SA38

SA37

SA36

SA35

SA34

SA33

SA32

SA31

SA30

SA29

SA28

SA27

SA26

SA25

SA24

SA23

SA22

SA21

SA20

SA19

SA18

SA17

SA16

SA15

SA14

SA13

SA12

SA11

SA10

SA9

0

1

0

1

0

32

4

0F8000h to 0FFFFFh

0F0000h to 0F7FFFh

0E8000h to 0EFFFFh

0E0000h to 0E7FFFh

0D8000h to 0DFFFFh

0D0000h to 0D7FFFh

0C8000h to 0CFFFFh

0C0000h to 0C7FFFh

0B8000h to 0BFFFFh

0B0000h to 0B7FFFh

0A8000h to 0AFFFFh

0A0000h to 0A7FFFh

098000h to 09FFFFh

090000h to 097FFFh

088000h to 08FFFFh

080000h to 087FFFh

078000h to 07FFFFh

070000h to 077FFFh

068000h to 06FFFFh

060000h to 067FFFh

058000h to 05FFFFh

050000h to 057FFFh

048000h to 04FFFFh

040000h to 047FFFh

038000h to 03FFFFh

030000h to 037FFFh

028000h to 02FFFFh

020000h to 027FFFh

018000h to 01FFFFh

010000h to 017FFFh

008000h to 00FFFFh

007000h to 007FFFh

006000h to 006FFFh

005000h to 005FFFh

004000h to 004FFFh

003000h to 003FFFh

002000h to 002FFFh

001000h to 001FFFh

000000h to 000FFFh

B

a

n

k

B

a

n

k

A

SA8

SA7

SA6

1

0

4

SA5

1

0

1

4

SA4

1

0

4

SA3

0

1

4

SA2

0

1

0

4

SA1

0

1

4

SA0

0

4

15

MB84VD22184FM/VD22194FM^-70

Sector Group Addresses Table (Top Boot Type)

Sector group

A²⁰

A¹⁹

A¹⁸

A¹⁷

A¹⁶

0

A¹⁵

0

A¹⁴

A¹³

A¹²

Sectors

SGA0

0

X

SA0

0

1

SGA1

0

1

0

X

SA1 to SA3

1

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

SGA8

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

X

0

X

SA4 to SA7

SA8 to SA11

SA12 to SA15

SA16 to SA19

SA20 to SA23

SA24 to SA27

SA28 to SA31

SA32 to SA35

SA36 to SA39

SA40 to SA43

SA44 to SA47

SA48 to SA51

SA52 to SA55

SA56 to SA59

SGA16

1

0

1

X

SA60 to SA62

1

0

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

1

16

MB84VD22184FM/VD22194FM^-70

Sector Group Addresses Table (Bottom Boot Type)

Sector group

SGA0

A²⁰

0

A¹⁹

0

A¹⁸

0

A¹⁷

0

A¹⁶

0

A¹⁵

0

A¹⁴

0

A¹³

0

A¹²

0

Sectors

SA0

SGA1

0

1

SA1

SGA2

0

1

0

SA2

SGA3

0

1

SA3

SGA4

0

1

0

SA4

SGA5

0

1

0

1

SA5

SGA6

0

1

0

SA6

SGA7

0

1

SA7

0

1

SGA8

0

1

0

X

SA8 to SA10

1

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

X

0

X

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SA35 to SA38

SA39 to SA42

SA43 to SA46

SA47 to SA50

SA51 to SA54

SA55 to SA58

SA59 to SA62

SA63 to SA66

SGA23

SGA24

1

0

1

X

SA67 to SA69

SA70

1

0

1

17

MB84VD22184FM/VD22194FM^-70

Sector Group Protection Verify Autoselect Codes Table (Top Boot Type)

Type

A²⁰to A¹²

BA

A⁶

L

A³

L

A²

L

A¹

L

A⁰

L

Code (HEX)

04h

Manufacture’s Code

Device Code

BA

L

H

L

2250h

01h*

Sector Group Protection

SA

L

H

Legend: L = V^IL, H = VIH. See DC Characteristics for voltage levels.

* : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

Expanded Autoselect Code Table (Top Boot Type)

DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Code

04h

Manufacture’s

Code

0

1

0

1

0

1

0

1

0

1

0

1

Device Code

2250h

01h

Sector Group

Protection

Sector Group Protection Verify Autoselect Codes Table (Bottom Boot Type)

Type

A²⁰to A¹²

BA

A⁶

L

A³

L

A²

L

A¹

L

A⁰

L

Code (HEX)

04h

Manufacture’s Code

Device Code

BA

L

H

L

2253h

01h*

Sector Group Protection

SA

L

H

Legend: L = V^IL, H = VIH. See DC Characteristics for voltage levels.

* : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

Expanded Autoselect Code Table (Bottom Boot Type)

DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Code

04h

Manufacture’s

Code

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Device Code

2253h

01h

Sector Group

Protection

18

MB84VD22184FM/VD22194FM^-70

Command Definitions Table

Fourth bus

read/write cy-

cle

Bus

write

cycles

req’d

First bus

Second bus

write cycle

Third bus

Fifth bus

Sixth bus

Command

sequence

write cycle

Addr. Data Addr. Data

Addr.

Data Addr. Data Addr. Data Addr. Data

Read/Reset*¹

1

3

XXXh F0h

555h

BA

AAh 2AAh

B0h

55h

555h

(BA)

555h

F0h

90h

A0h

RA

PA

RD

PD

Autoselect

3

4

1

Program

Suspend

Program

Resume

1

BA

30h

Chip Erase

Sector Erase

Erase Suspend

Erase Resume

Set to

Fast Mode

Fast

Program *²

Reset from Fast

Mode *²

6

1

555h

BA

AAh 2AAh

B0h

55h

555h

80h

555h

AAh 2AAh 55h

555h

SA

10h

30h

BA

30h

3

2

555h

AAh 2AAh

55h

PD

555h

20h

XXXh A0h

BA

PA

90h XXXh F0h*⁶

Extended

Sector Group

Protection *³

4

XXXh 60h

SPA

60h

SPA

40h

SPA

SD

(BA)

98h

55h

Query *⁴

1

3

4

HiddenROM

Entry

HiddenROM

Program *⁵

HiddenROM

Exit *⁵

555h

AAh 2AAh

55h

555h

88h

A0h

90h

(HRA)

PA

PD

(HRBA)

555h

XXXh

00h

(Continued)

19

MB84VD22184FM/VD22194FM^-70

(Continued)

*1 : Both of these reset commands are equivalent.

*2 : This command is valid during Fast Mode.

*3 : This command is valid while RESET = VID.

*4 : The valid address are A⁶to A0.

*5 : This command is valid during HiddenROM mode.

*6 : The date “00h” is also acceptable.

Notes: • Address bits A²⁰to A11 = X = “H” or “L” for all address commands except or Program Address (PA) , Sector

Address (SA) , Bank Address (BA) .

• Bus operations are defined in

“User Bus Operations Tables” (■DEVICE BUS OPERATION).

• RA = Address of the memory location to be read

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A²⁰, A19, A18, A17, A16, A15, A14, A13, and

A12 will uniquely select any sector.

BA = Bank Address (A20 to A18)

• RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.

• SPA = Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) = (0, 0, 0,

1, 0) .

SD = Sector group protection verify data. Output 01h at protected sector group addresses and output

00h at unprotected sector group addresses.

• HRA = Address of the HiddenROM area

Top Boot Type

Bottom Boot Type :

:

1FF000h to 1FF07Fh

000000h to 00007Fh

• HRBA = Bank Address of the HiddenROM area

Top Boot Type

: A²⁰= A¹⁹= A¹⁸= 1

Bottom Boot Type

: A²⁰= A¹⁹= A¹⁸= 0

• The system should generate the following address patterns :

Word Mode : 555h or 2AAh to addresses A10 to A0

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

• The command combinations not described in “Command Definitions Table” are illegal.

20

MB84VD22184FM/VD22194FM^-70

2. AC Characteristics

• Read Only Operations Characteristics

Symbol

Value*

Parameter

Test setup

Unit

JEDEC

t^AVAV

Standard

Min

70

Max

Read Cycle Time

tRC

—

ns

CEf = VIL

OE = VIL

Address to Output Delay

t^AVQV

tACC

70

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

tELQV

t^GLQV

t^EHQZ

t^GHQZ

tCE

tOE

tDF

OE = VIL

70

30

25

ns

—

Output Hold Time from Addresses,

CEf or OE, Whichever Occurs First

t^AXQX

—

tOH

—

0

ns

RESET Pin Low to Read Mode

tREADY

20

µs

* : Test Conditions:

Output Load:1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 0.5 × Vccf

Output: 0.5 × Vccf

21

MB84VD22184FM/VD22194FM^-70

• Write/Erase/Program Operations

Parameter

Symbol

JEDEC Standard

t^AVAV

Value

Typ

Unit

Min

70

0

Max

Write Cycle Time

tWC

tAS

ns

Address Setup Time

t^AVWL

Address Setup Time to OE Low During Toggle Bit

Polling

—

t^ASO

tAH

12

45

0

ns

Address Hold Time

tWLAX

—

Address Hold Time from CEf or OE High During

Toggle Bit Polling

t^AHT

Data Setup Time

Data Hold Time

t^DVWH

t^WHDX

tDS

tDH

30

0

ns

s

Read

0

Output Enable

Hold Time

—

t^OEH

Toggle and Data Polling

10

20

0

CEf High During Toggle Bit Polling

OE High During Toggle Bit Polling

Read Recover Time Before Write

CEf Setup Time

—

tCEPH

tOEPH

tGHWL

tGHEL

tCS

t^GHWL

t^GHEL

tELWL

tWLEL

tWHEH

tEHWH

t^WLWH

tELEH

t^WHWL

tEHEL

tWHWH2

—

0

WE Setup Time

tWS

0

CEf Hold Time

tCH

0

WE Hold Time

tWH

0

Write Pulse Width

tWP

35

25

CEf Pulse Width

tCP

Write Pulse Width High

CEf Pulse Width High

Sector Erase Operation *¹

tWPH

tCPH

tWHWH2

tVCS

tVIDR

tVACCR

tVLHT

tWPP

tOESP

tCSP

tRB

0.5

V^CCf Setup Time

Rise Time to V^ID*²

Voltage Transition Time *²

Write Pulse Width *²

OE Setup Time to WE Active *²

CEf Setup Time to WE Active *²

Recover Time from RY/BY

RESET Pulse Width

50

500

4

µs

ns

µs

ns

µs

—

100

4

—

4

—

tRP

500

200

RESET High Level Period before Read

Program/Erase Valid to RY/BY Delay

Delay Time from Embedded Output Enable

Erase Time-Out Time

—

tRH

—

tBUSY

t^EOE

t^TOW

t^SPD

90

70

—

50

Erase Suspend Transition Time

—

*1 : This does not include the preprogramming time.

*2 : This timing is for Sector Group Protection operation.

22

MB84VD22184FM/VD22194FM^-70

• Read Cycle (Flash)

tRC

Address Stable

Address

tACC

CEf

OE

tOE

t^DF

tOEH

WE

DQ

tCEf

High-Z

Output Valid

tRC

Address

CEf

Address Stable

tACC

tRH

tCEf

tRP

RESET

DQ

tOH

High-Z

Output Valid

23

MB84VD22184FM/VD22194FM^-70

• Write Cycle (WE control) (Flash)

3rd Bus Cycle

Data Polling

555h

PA

Address

CEf

tWC

tRC

tAS

tAH

tCH

tCS

tCEf

OE

tGHWL

tOE

tWHWH1

tWP

tWPH

WE

tOH

tDS

tDH

PD

DOUT

A0h

DQ7

DQ

Notes : • PA is address of the memory location to be programmed.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode.

24

MB84VD22184FM/VD22194FM^-70

• Write Cycle (CEf control) (Flash)

3rd Bus Cycle

Data Polling

Address

PA

555h

tWC

tAH

tAS

WE

tWS

tWH

OE

tGHEL

tWHWH1

tCP

tCPH

CEf

tDS

tDH

PD

D^OUT

DQ7

A0h

DQ

Notes : • PA is address of the memory location to be programmed.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode.

25

MB84VD22184FM/VD22194FM^-70

• AC Waveforms Chip/Sector Erase Operations (Flash)

SA*

2AAh

555h

2AAh

555h

Address

CEf

tWC

tAS

tAH

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

30h for Sector Erase

10h/

30h

AAh

55h

80h

55h

DQ

tVCS

VCCf

* : SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.

Note : These waveform are for the ×16 mode.

26

MB84VD22184FM/VD22194FM^-70

• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)

CEf

tCH

t^DF

tOE

OE

tOEH

WE

tCEf

*

High-Z

DQ7 =

Data Input

DQ⁷

Valid Data

tWHWH1 or 2

DQ

(DQ⁶to DQ⁰)

DQ⁸to DQ⁰

Valid Data

DQ6 to DQ0 = Output Flag

tBUSY

tEOE

RY/BY

* : DQ7 = Valid Data (The device has completed the Embedded operation.)

27

MB84VD22184FM/VD22194FM^-70

• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)

Address

tAHT

tASO

tAHT

tAS

CEf

tCEPH

WE

OE

tOEH

tOEPH

*

tOE

tCEf

tDH

Toggle

Data

Toggle

Data

Toggle

Data

Stop

Toggling

Output

Valid

DQ⁶/DQ²

RY/BY

Data

tBUSY

* : DQ6 stops toggling (The device has completed the Embedded operation).

28

MB84VD22184FM/VD22194FM^-70

• Back-to-back Read/Write Timing Diagram (Flash)

Read

Command

Read

Command

Read

t

RC

t

WC

t

RC

t

WC

t

RC

tRC

BA2

(555h)

BA2

(PA)

BA2

(PA)

Address

CEf

BA1

t

ACC

t

AS

t

AS

t

AH

t

AHT

t

CE

t

OE

t

CEPH

OE

WE

DQ

t

DF

t

GHWL

t

OEH

t

WP

t

DH

t

DS

tDF

Valid

Status

Output

Intput

Output

Intput

Output

(A0h)

(PD)

Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1: Address of Bank 1.

BA2: Address of Bank 2.

29

MB84VD22184FM/VD22194FM^-70

• RY/BY Timing Diagram during Write/Erase Operations (Flash)

CEf

Rising edge of the last write pulse

WE

Entire programming

or erase operations

RY/BY

tBUSY

• RESET, RY/BY Timing Diagram (Flash)

WE

RESET

tRP

tRB

RY/BY

tREADY

30

MB84VD22184FM/VD22194FM^-70

• Temporary Sector Unprotection (Flash)

V^CCf

t^VIDR

t^VCS

t^VLHT

V^ID

3V

RESET

CEf

WE

t^VLHT

Program or Erase Command Sequence

RY/BY

Unprotection Period

31

MB84VD22184FM/VD22194FM^-70

• Extended Sector Group Protection (Flash)

VCCf

tVCS

RESET

Address

A0

tVLHT

tVIDR

tWC

SGAx

SGAy

A1

A6

CEf

OE

TIME-OUT

tWP

WE

Data

60h

40h

01h

60h

tOE

SGAx : Sector Group Address to be protected

SGAy : Next Group Sector Address to be protected

TIME-OUT : Time-Out window = 250 µs (Min)

32

MB84VD22184FM/VD22194FM^-70

• Accelerated Program (Flash)

VCCf

tVACCR

tVCS

tVLHT

VACC

3 V

WP/ACC

CEf

WE

tVLHT

Program Command Sequence

RY/BY

Acceleration period

33

MB84VD22184FM/VD22194FM^-70

3. Erase and Programming Performance

Limits

Parameter

Unit

Comments

Min

Typ

Max

Excludes programming time

prior to erasure

Sector Erase Time

0.5

2.0

s

Excludes system-level

overhead

Word Programming Time

6.0

100

50

µs

Excludes system-level

overhead

Chip Programming Time

Program/Erase Cycle

12.6

s

100,000

cycle

34

MB84VD22184FM/VD22194FM^-70

■ 4 M SRAM for MCP

1. AC Characteristics

• Read Cycle (SRAM)

Value

Parameter

Symbol

Unit

Min

70

—

5

Max

—

Read Cycle Time

t^RC

t^AA

ns

Address Access Time

70

35

70

—

Chip Enable (CE1s) Access Time

Chip Enable (CE2s) Access Time

Output Enable Access Time

tCO1

tCO2

t^OE

LB, UB to Output Valid

tBA

Chip Enable (CE1s Low and CE2s High) to Output Active

Output Enable Low to Output Active

UB, LB Enable Low to Output Active

Chip Enable (CE1s High or CE2s Low) to Output High-Z

Output Enable High to Output High-Z

UB, LB Output Enable to Output High-Z

Output Data Hold Time

tCOE

tOEE

tBE

0

—

0

—

tOD

—

10

25

—

tODO

tBD

t^OH

Note: Test Conditions– Output Load:1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to V^CCs

Timing measurement reference level

Input: 0.5×VCCs

Output: 0.5×VCCs

35

MB84VD22184FM/VD22194FM^-70

• Read Cycle (SRAM)

t^RC

Address

t^AA

t^OH

t^CO1

CE1s

t^COE

t^OD

t^CO2

CE2s

t^OD

t^OE

OE

t^ODO

t^OEE

LB, UB

t^BA

t^BD

t^BE

t^COE

DQ

Valid Data Output

Note: WE remains HIGH for the read cycle.

36

MB84VD22184FM/VD22194FM^-70

• Write Cycle (SRAM)

Parameter

Value

Symbol

Unit

Min

70

50

55

0

Max

—

25

—

Write Cycle Time

t^WC

tWP

t^CW

t^AW

tBW

t^AS

ns

Write Pulse Width

Chip Enable to End of Write

Address valid to End of Write

UB, LB to End of Write

Address Setup Time

Write Recovery Time

WE Low to Output High-Z

WE High to Output Active

Data Setup Time

t^WR

tODW

tOEW

tDS

0

—

0

30

0

Data Hold Time

t^DH

37

MB84VD22184FM/VD22194FM^-70

• Write Cycle *¹(WE control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

t^AW

t^CW

CE1s

CE2s

t^CW

t^BW

LB, UB

t^OEW

t^ODW

D^OUT

*2

*4

*3

*4

t^DS

t^DH

D^IN

Valid Data Input

*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.

*2 : If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output

will remain at high impedance.

*3 : If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output

will remain at high impedance.

*4 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity

must not be applied.

38

MB84VD22184FM/VD22194FM^-70

• Write Cycle *¹(CE1s control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

t^AW

t^CW

CE1s

CE2s

t^CW

t^BW

LB, UB

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

D^IN

*2

Valid Data Input

*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

39

MB84VD22184FM/VD22194FM^-70

• Write Cycle *¹(CE2s Control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

t^CW

CE1s

CE2s

t^AW

t^CW

t^BW

LB, UB

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

D^IN

*2

Valid Data Input

*2

*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

40

MB84VD22184FM/VD22194FM^-70

• Write Cycle *¹(LB, UB Control) (SRAM)

t^WC

Address

WE

t^WP

t^WR

t^CW

CE1s

CE2s

t^CW

t^AW

t^BW

t^AS

LB, UB

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

*2

Valid Data Input

*2

D^IN

*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

41

MB84VD22184FM/VD22194FM^-70

2. Data Retention Characteristics (SRAM)

Parameter

Value

Typ

—

Symbol

Unit

Min

1.5

—

Max

3.1

10

Data Retention Supply Voltage

V^DH

IDDS2

tCDR

t^R

V

Standby Current

V^DH= 3.0 V

—

µA

ns

Chip Deselect to Data Retention Mode Time

Recovery Time

0

—

tRC

—

Note : t^RC: Read cycle time

• CE1s Controlled Data Retention Mode *¹

V^CCs

Data Retention Mode

2.7 V

*2

V^IH

V^DH

V^CCs – 0.2 V

t^CDR

t^R

CE1s

GND

*1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs–0.2 V or Vss

to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to

Vccs+0.3 V.

*2 : When CE1s is operating at the VIH Min level, the standby current is given by ISB1s during the transition

of VCCs from VCCs Max to VIH Min level.

• CE2s Controlled Data Retention Mode *

V^CCs

Data Retention Mode

2.7 V

V^DH

V^IH

t^CDR

t^R

CE2s

GND

V^IL

0.2 V

* : In CE2s controlled data retention mode, input and input/output pins can be used between

–0.3 V to Vccs+0.3V.

42

MB84VD22184FM/VD22194FM^-70

■ PIN CAPACITANCE

Value

Parameter

Symbol

Test Setup

Unit

Typ

11

Max

14

Input Capacitance

C^IN

VIN = 0

pF

Output Capacitance

C^OUT

C^IN2

CIN3

VOUT = 0

VIN = 0

12

16

Control Pin Capacitance

WP/ACC Pin Capacitance

14

16

21.5

26

Note : Test conditions TA = + 25°C, f = 1.0 MHz

■ HANDLING OF PACKAGE

Please handle this package carefully since the sides of package create acute angles.

■ CAUTION

• The high voltage (VID) cannot apply to address pins and control pins except RESET.

Exception is when autoselect and sector group protect function are used, then the high voltage (VID) can be

applied to RESET.

• Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group

Protection” command.

43

MB84VD22184FM/VD22194FM^-70

■ ORDERING INFORMATION

MB84VD2218

4

FM

-70

PBS

PACKAGE TYPE

PBS = 56-ball FBGA

SPEED OPTION

See Product Selector Guide

Device Revision

Bank Architecture

4 = 8Mbit / 24Mbit (Fixed Bank)

DEVICE NUMBER/DESCRIPTION

32Mega-bit (2M × 16-bit) Dual Operation Flash Memory

3.0 V-only Read, Program, and Erase

4Mega-bit (256K × 16-bit) SRAM

BOOT CODE SECTOR ARCHITECTURE

84VD2218 = Top sector

84VD2219 = Bottom sector

44

MB84VD22184FM/VD22194FM^-70

■ PACKAGE DIMENSION

56-ball plastic FBGA

(BGA-56P-M03)

1.2(.047)

9.00±0.10(.354±.004)

(Mounting height)

MAX.

5.60(.220)

0.30±0.10

(.012±.004)

0.80

(.031)

(Stand off)

8

7

6

5

4

3

2

1

7.00±0.10

(.276±.004)

5.60(.220)

0.80

(.031)

K

J

H

G

F

E

D C B A

INDEX-MARK AREA

+0.10

56-ø0.45 –0.05

M

0.08(.003)

+.004

56-ø.018

–.002

0.10(.004)

C

2002 FUJITSU LIMITED BGA560030Sc-1-1

Dimensions in mm (inches)

Note: The values in parentheses are reference values.

45

MB84VD22184FM/VD22194FM^-70

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0311

FUJITSU LIMITED Printed in Japan

型号	制造商	描述	价格	文档
MB84VD22184FM-70	SPANSION	32M (X16) FLASH MEMORY & 4M (X16) STATIC RAM	获取价格
MB84VD22184FM-70PBS	SPANSION	32M (x16) FLASH MEMORY AND 4M (x16) STATIC RAM	获取价格
MB84VD2218XEC	FUJITSU	32M (x 8/x16) FLASH MEMORY & 4M (x 8/x16) STATIC RAM	获取价格
MB84VD2218XEG	FUJITSU	32M (x 8/x16) FLASH MEMORY & 4M (x 8/x16) STATIC RAM	获取价格
MB84VD22190FA-70PBS-E1	SPANSION	Memory Circuit, 2MX16, CMOS, PBGA59, PLASTIC, FBGA-59	获取价格
MB84VD22191EC	FUJITSU	32M (x 8/x16) FLASH MEMORY & 4M (x 8/x16) STATIC RAM	获取价格
MB84VD22191EC-90	FUJITSU	32M (x 8/x16) FLASH MEMORY & 4M (x 8/x16) STATIC RAM	获取价格
MB84VD22191EC-90-PBS	FUJITSU	32M (x 8/x16) FLASH MEMORY & 4M (x 8/x16) STATIC RAM	获取价格
MB84VD22191EE	FUJITSU	32M (x 8/x16) FLASH MEMORY & 4M (x 8/x16) STATIC RAM	获取价格
MB84VD22191EE-90	FUJITSU	32M (x 8/x16) FLASH MEMORY & 4M (x 8/x16) STATIC RAM	获取价格

MB84VD22184FM

MB84VD22184FM 概述

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