MB90548PFF [SPANSION]
Microcontroller, 16-Bit, MROM, 16MHz, CMOS, PQFP100, PLASTIC, LQFP-100;
| 型号： | MB90548PFF |
| 厂家： | 
SPANSION |
| 描述： | Microcontroller, 16-Bit, MROM, 16MHz, CMOS, PQFP100, PLASTIC, LQFP-100 时钟 控制器 微控制器 微控制器和处理器 外围集成电路 |
| 文件： | 总73页 (文件大小：1539K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13703-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LXMB90540/545Series
MB90543/F543/549/F549/V540
■ DESCRIPTION
The MB90540/545 series with FULL-CAN and FLASH ROM is specially designed for automotive and industrial ap-
plications. Its main features are two on board CAN Interfaces (one for MB90V545 series), which conform to V2.0
Part A and Part B, supporting very flexible message buffering. Thus, offering more functions than a normal full CAN
approach. In the new 0.5µm Technology Fujitsu now also offer FLASH-ROM. An internal voltage booster substitutes
the necessity of a second programming voltage.
An on board voltage regulator provides 3V to the internal MCU core. This constitutes a major advantage in terms of
EMI and power consumption.
The internal PLL clock frequency multiplier, provides an internal 62.5 nsec instruction cycle time with an external 4
MHz clock.
Further more it features 4 channels Output Capture Units and 8 channels Input Capture Units with a 16-bit free run-
ning timer. Two UARTs constitute additional functionality for communication purposes.
The external bus interface allows full use to be made of the 16MByte address space.
■ FEATURES
• 16-bit core CPU : 4MHz external clock (16 MHz internal, 62.5 nsec instr. cycle time)
• 32 kHz Subsystem Clock
• New 0.5 µm CMOS Process Technology
• Internal voltage regulator supports 3V MCU core, offering low EMI and low power consumption figures
• FULL-CAN interfaces (MB90540 series : 2 interf., MB90545 series : 1 interf.); conform to Version 2.0 Part A
and Part B, flexible message buffering (mailbox and FIFO buffering can be mixed)
(Continued)
■ PACKAGE
100-pin Plastic QFP
100-pin Plastic LQFP
(FPT-100P-M06)
(FPT-100P-M05)
MB90540/545 Series
(Continued)
• Powerful interrupt functions (8 progr. priority levels; 8 external interrupts)
• EI2OS - Automatic transfer function indep.of CPU
• 18-bit Time-base counter
• Watchdog Timer
• 2 full duplex UARTs; UART0 supports 10.4 KBaud (USA standard), UART 1 also for serial transfer with clock
(SCI) programmable
• Serial I/O: 1ch for synchronous data transfer
• A/D Converter: 8 ch. analog inputs (Resolution 10 bits or 8 bits)
• 16-bit reload timer * 2ch
• ICU (Input capture) 16bit * 8 ch
• OCU (Output capture) 16bit * 4ch
• 16-bit Programmable Pulse Generator 4ch
• External bus interface
• Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different
addressing modes; barrel shift; variety of pointers)
• 4-byte instruction execution queue
• signed multiply (16bit*16bit) and divide (32bit/16bit) instructions available
• Program Patch Function
• Fast Interrupt processing
• Low Power Consumption - 10 different power saving modes: (Sleep, Stop, CPU intermittent mode, Hardware
standby,...)
• Package: 100-pin plastic QFP
Controller Area Network (CAN) - License of Robert Bosch GmbH
2
MB90540/545 Series
■ PRODUCT LINEUP
The following table provides a quick outlook of the MB90540/545 Series
Features
CPU
MB90V540
MB90F543/F549
MB90543/549
F2MC-16LX CPU
On-chip PLL clock multiplier ( × 1, × 2, × 3, × 4, 1/2 when PLL stop)
Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL × 4)
System clock
Boot-block
Flash memory 128 K/256 Kbytes
ROM
RAM
External
8 Kbytes
Mask ROM 128 K/256 Kbytes
6 Kbytes
6 Kbytes
0.5 µm CMOS with on-chip volt-
0.5 µm CMOS with on- age regulator for internal power
chip voltage regulator
0.5 µm CMOS with on-chip volt-
supply + Flash memory On-chip age regulator for internal power
Technology
for internal power supply charge pump for programming
voltage
supply
Operating
voltage range
5 V±10 %
Temperature
range
− 40 to 85 °C
Package
PGA-256
QFP100
Full duplex double buffer
Supports asynchronous/synchronous (with start/stop bit) transfer
Baud rate: 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500K/1M/2Mbps (synchronous) at System clock = 16 MHz
UART0
Full duplex double buffer
Asynchronous (start-stop synchronized) and CLK-synchronous communication
Baud rate: 1202/2404/4808/9615/31250 bps (asynchronous)
62.5K/12K/250K/500K/1 Mbps (synchronous) at 6,8,10,12,16 MHz
UART1(SCI)
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and negative-edge clock synchronization
Baud rate : 31.25K/62.5K/125K/500K/1Mbps at System clock = 16MHz
Serial IO
10-bit or 8-bit resolution
A/D Converter
8 input channels
Conversion time: 26.3 µs (per one channel)
16-bit Reload
Timer
(2 channels)
Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function
Signals an interrupt when overflow
16-bit IO Timer
16-bit
Supports Timer Clear when a match with Output Compare(Channel 0)
Operation clock freq.: fsys/22, fsys/24, fsys/26, fsys/28(fsys = System clock freq.)
Signals an interrupt when a match with 16-bit IO Timer
Output Compare Four 16-bit compare registers
(4 channels) A pair of compare registers can be used to generate an output signal
(Continued)
3
MB90540/545 Series
(Continued)
Features
MB90V540
MB90F543/F549
MB90543/549
16-bit
Input Capture
(8 channels)
Rising edge, falling edge or rising & falling edge sensitive
Four 16-bit Capture registers
Signals an interrupt upon external event
Supports 8-bit and 16-bit operation modes
Eight 8-bit reload counters
Eight 8-bit reload registers for L pulse width
Eight 8-bit reload registers for H pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
8/16-bit
Programmable
Pulse Generator
(4 channels)
4 output pins
Operation clock freq.: fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128µs@fosc=4MHz
(fsys = System clock frequency, fosc = Oscillation clock frequency)
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
CAN Interface
540 series:
2 channels
Flexible configuration of acceptance filtering:
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1Mbps
545 series:
1 channel
32 kHz Subclock Sub-clock for low power operation
External Interrupt
Can be programmed edge sensitive or level sensitive
(8 channels)
Virtually all external pins can be used as general purpose IO
All push-pull outputs and schmitt trigger inputs
IO Ports
Bit-wise programmable as input/output or peripheral signal
Supports automatic programming,
1
Embedded AlgorithmTM
*
Write/Erase/Erase-Suspend/
Resume commands
A flag indicating completion of the
algorithm
Number of erase cycles: 10,000
times
Data retention time: 10 years
Flash Writer from Minato Electron-
ics Inc.
Flash Memory
Boot block configuration
Erase can be performed on each
block
Block protection with external pro-
gramming voltage
Flash Security Feature:
protects the content of the
Flash memory
*1: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
4
MB90540/545 Series
■ PIN ASSIGNMENT
(Top view)
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P20/A16
P21/A17
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
X0A
X1A
PA0
2
3
4
RST
5
P97/RX1
P96/TX1
P95/RX0
P94/TX0
P93/INT3
P92/INT2
P91/INT1
P90/INT0
P87/TOT1
P86/TIN1
P85/OUT1
P84/OUT0
P83/PPG3
P82/PPG2
P81/PPG1
P80/PPG0
P77/OUT3/IN7
P76/OUT2/IN6
P75/IN5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Vss
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SOT0
P41/SCK0
P42/SIN0
P43/SIN1
P44/SCK1
Vcc
P45/SOT1
P46/SOT2
P47/SCK2
C
P74/IN4
P73/IN3
P72/IN2
P71/IN1
P50/SIN2
P51/INT4
P52/INT5
P70/IN0
HST
MD2
(FPT-100P-M06)
5
MB90540/545 Series
■ PIN DESCRIPTION
No.
Pin name
Circuit type
Function
High speed oscillator input pins
82
83
X0
X1
A
(Oscillation)
80
79
X0A
X1A
A
Low speed oscillator input pins
(Oscillation)
77
52
RST
HST
B
C
External reset request input
Hardware standby input
General I/O port with programmable pullup. This function is enabled
in the single-chip mode.
P00 to P07
AD00 to AD07
P10 to P17
AD08 to AD15
P20 to P27
A16 to A23
P30
85 to 92
93 to 100
1 to 8
9
I
I
I/O pins for 8 lower bits of the external address/data bus. This func-
tion is enabled when the external bus is enabled.
General I/O port with programmable pullup. This function is enabled
in the single-chip mode.
I/O pins for 8 higher bits of the external address/data bus. This func-
tion is enabled when the external bus is enabled.
General I/O port with programmable pullup. This function is enabled
in the single-chip mode.
H
I
Output pins for A16 to A23 ot the external address bus. This function
is enabled when the external bus is enabled.
General I/O port with programmable pullup. This function is enabled
in the single-chip mode.
Address latch enable output pin. This function is enabled when the
external bus is enabled.
ALE
General I/O port with programmable pullup. This function is enabled
in the single-chip mode.
P31
10
I
Read strobe output pin for the data bus. This function is enabled
when the external bus is enabled.
RD
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when the WR/WRL pin output is disabled.
P32
WRL
Write strobe output pin for the data bus. This function is enabled
when both the external bus and the WR/WRL pin output are en-
abled. WRL is used to write-strobe 8 lower bits of the data bus in
16-bit access while WR is used to write-strobe 8 bits of the data bus
in 8-bit access.
12
13
I
I
WR
P33
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or external bus 8-bit mode or when WRH pin
output is disabled.
Write strobe output pin for the 8 higher bits of the data bus. This
function is enabled when the external bus is enabled, when the ex-
ternal bus 16-bit mode is selected, and when the WRH output pin is
enabled.
WRH
6
MB90540/545 Series
No.
Pin name
Circuit type
Function
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when hold function is disabled.
P34
14
I
Hold request input pin. This function is enabled when both the ex-
ternal bus and the hold function are enabled.
HRQ
P35
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when hold function is disabled.
15
16
I
I
Hold acknowledge output pin. This function is enabled when both
the external bus and the hold function are enabled.
HAK
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when the external ready function is dis-
abled.
P36
Ready input pin. This function is enabled when both the external
bus and the external ready function are enabled.
RDY
P37
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when the clock output is disabled.
17
18
19
20
21
22
24
H
G
G
G
G
G
G
CLK output pin. This function is enabled when both the external bus
and CLK output are enabled.
CLK
P40
General I/O port. This function is enabled when UART0 disables se-
rial data output.
Serial data output pin for UART0. This function is enabled when
UART0 enables serial data output.
SOT0
P41
General I/O port. This function is enabled when UART0 disables
clock output.
Clock I/O pin for UART0. This function is enabled when UART0 en-
ables clock output.
SCK0
P42
General I/O port. This function is always enabled.
Serial data input pin for UART0. While UART0 is operating for input,
the input of the pin is used as required. Except when the function is
intentionally used, output from the other functions must be stopped.
SIN0
P43
General I/O port. This function is always enabled.
Serial data input pin for UART1. While UART1 is operating for input,
the input of the pin is used as required. Except when the function is
intentionally used, output from the other functions must be stopped.
SIN1
General I/O port. This function is enabled when UART1 disables
clock output.
P44
SCK1
P45
Clock pulse input/output pin for UART1. This function is enabled
when UART1 enables clock output.
General I/O port. This function is enabled when UART1 disables se-
rial data output.
Serial data output pin for UART1. This function is enabled when
UART1 enables serial data output.
SOT1
7
MB90540/545 Series
No.
Pin name
Circuit type
Function
General I/O port. This function is enabled when the Serial IO dis-
ables serial data output.
P46
25
G
Serial data output pin for the Serial IO. This function is enabled
when the Serial IO enables serial data output.
SOT2
P47
General I/O port. This function is enabled when the Serial IO dis-
ables clock output.
26
28
G
D
Clock pulse input/output pin for the Serial IO. This function is en-
abled when the Serial IO enables clock output.
SCK2
P50
General I/O port. This function is always enabled.
Serial data input pin for the Serial IO. While the Serial IO is operat-
ing for input, the input of the pin is used as required. Except when
the function is intentionally used, output from the other functions
must be stopped.
SIN2
P51 to P54
INT4 to INT7
P55
General I/O port. This function is always enabled.
External interrupt request input pins for INT4 to INT7. While external
interrupt is allowed, the input of the pin is used as required. Except
when the function is intentionally used, output from the other func-
tions must be stopped.
29 to 32
D
D
General I/O port. This function is always enabled.
Trigger input pin for the A/D converter. While the A/D converter is
operating for input, the input of the pin is used as required. Except
when the function is intentionally used, output from the other func-
tions must be stopped.
33
ADTG
General I/O port. The function is enabled when the analog input en-
able register specifies port.
P60 to P63
AN0 to AN3
P64 to P67
38 to 41
43 to 46
E
E
Analog input pins for the A/D converter. This function is enabled
when the analog input enable register specifies AD.
General I/O port. The function is enabled when the analog input en-
able register specifies port.
Analog input pins for the A/D converter. This function is enabled
when the analog input enable register specifies AD.
AN4 to AN7
P56
General I/O port. This function is always enabled.
Event input pin for the reload timers 0. While the reload timer is op-
erating for input, the input of the pin is used as required. Except
when the function is intentionally used, output from the other
functions must be stopped.
47
48
D
D
TIN0
General I/O port. This function is enabled when the reload
timers 0 disables output.
P57
Output pin for the reload timers 0. This function is enabled when the
reload timers 0 enables output.
TOT0
8
MB90540/545 Series
No.
Pin name
Circuit type
Function
P70 to P75
General I/O ports. This function is always enabled.
Data sample input pins for input captures ICU0 to ICU5. While the
ICU is for input, the input of the pin is used as required. Except when
the function is intentionally used, output from the other functions
must be stopped.
53 to 58
D
IN0 to IN5
General I/O ports. This function is enabled when the OCU disables
waveform output.
P76 to P77
Waveform output pins for output compares OCU2 and OCU3. This
function is enabled when the OCU enables waveform output.
OUT2 to OUT3
59 to 60
D
Data sample input pin for input captures ICU6 and ICU7. While the
ICU is for input, the input of the pin is used as required. Except when
the function is intentionally used, output from the other functions
must be stopped.
IN6 to IN7
General I/O ports. This function is enabled when PPG disables
waveform output.
P80 to P83
PPG0 to PPG3
P84 to P85
61 to 64
65 to 66
D
D
Output pins for PPGs. This function is enabled when PPG enables
waveform output.
General I/O ports. This function is enabled when the OCU disables
waveform output.
Waveform output pins for output compares OCU0 and OCU1. This
function is enabled when the OCU enables waveform output.
OUT0 to OUT1
P86
General I/O port. This function is always enabled.
Event input pin for the reload timers 1. While the reload timer is op-
erating for input, the input of the pin is used as required. Except
when the function is intentionally used, output from the other
functions must be stopped.
67
68
D
D
D
TIN1
P87
General I/O port. This function is enabled when the reload
timers 0 disables output.
Output pin for the reload timers 1 This function is enabled when the
reload timers 1 enables output.
TOT1
P90 to P93
General I/O port. This function is always enabled.
External interrupt request input pins for INT0 to INT3. While external
interrupt is allowed, the input of the pin is used as required. Except
when the function is intentionally used, output from the other func-
tions must be stopped.
69 to 72
INT0 to INT3
P94
General I/O port. This function is enabled when CAN0 disables out-
put.
73
74
D
D
TX Output pin for CAN0. This function is enabled when CAN0 en-
ables output.
TX0
P95
RX0
General I/O port. This function is always enabled.
RX input pin for CAN0 Interface. When the CAN function is used,
output from the other functions must be stopped.
9
MB90540/545 Series
No.
Pin name
Circuit type
Function
General I/O port. This function is enabled when CAN1 disables out-
put.
P96
75
D
TX Output pin for CAN1. This function is enabled when CAN1 en-
ables output (only MB90540 series).
TX1
P97
General I/O port. This function is always enabled.
RX input pin for CAN1 Interface. When the CAN function is used,
output from the other functions must be stopped (only MB90540 se-
ries).
76
D
D
RX1
PA0
78
34
37
35
36
General I/O port. This function is always enabled.
Power supply for the A/D Converter. This power supply must be
Power supply turned on or off while a voltage higher than or equal to AVcc is ap-
plied to Vcc.
AVCC
AVSS
AVR+
AVR-
Power supply Dedicated ground pin for the A/D Converter
Reference voltage input for the A/D Converter. This power supply
Power supply must be turned on or off while a voltage higher than or equal to
AVR+ is applied to AVcc.
Power supply Lower reference voltage input for the A/D Converter
49
50
MD0
MD1
Input pins for specifying the operating mode. The pins must be di-
rectly connected to Vcc or Vss.
C
Input pin for specifying the operating mode. The pin must be directly
connected to Vcc or Vss.
51
MD2
F
This is the power supply stabilization capacitor pin. It should be con-
nected externally to an 0.1 µF ceramic capacitor.
27
C
23; 84
VCC
VSS
Power supply Power supply for digital circuits
11; 42
81
Power supply Ground for digital circuits
10
MB90540/545 Series
■ I/O CIRCUIT TYPE
Circuit type
Diagram
Remarks
• Oscillation feedback resistor:
1 MΩ approx.
X1
X0
A
Standby control signal
• Hysteresis input with pull-up
Resistor: 50 kΩ approx.
R
B
C
R
R
HYS
HYS
• Hysteresis input
• CMOS output
• Hysteresis input
VCC
P-ch
N-ch
D
R
HYS
11
MB90540/545 Series
Circuit type
Diagram
VCC
P-ch
Remarks
• CMOS output
• Hysteresis input
• Analog input
N-ch
E
Analog input
HYS
R
• Hysteresis input
• Pull-down Resistor: 50 kΩ approx.
(except FLASH devices)
R
HYS
F
R
• CMOS output
• Hysteresis input
VCC
• TTL input (FLASH devices only)
P-ch
N-ch
G
R
R
HYS
TTL
T
12
MB90540/545 Series
Circuit type
Diagram
Remarks
• CMOS output
• Hysteresis input
• Programmable pullup resistor:
50 kΩ approx.
VCC
CNTL
VCC
P-ch
N-ch
H
R
HYS
• CMOS output
• Hysteresis input
• TTL input (FLASH devices only)
• Programmable pullup resistor:
50 kΩ approx.
VCC
CNTL
VCC
P-ch
N-ch
I
R
HYS
TTL
R
T
13
MB90540/545 Series
■ HANDLING DEVICES
(1) Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than Vcc or lower than Vss is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between Vcc and Vss.
• The AVcc power supply is applied before the Vcc voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
(2) Handling unused input pins
Do not leave unused input pins open, as doing so may cause misoperation of the device. Use a pull-up or pull-
down resistor.
(3) Using external clock
To use external clock, drive the X0 and X1 pins in reverse phase.
Below is a diagram of how to use external clock.
MB90540/545 Series
X0
X1
Using external clock
(4) Power supply pins (Vcc/Vss)
Ensure that all Vcc-level power supply pins are at the same potential. In addition, ensure the same for all Vss-
level power supply pins. (See the figure below.) If there are more than one Vcc or Vss system, the device may
operate incorrectly even within the guaranteed operating range.
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90540/545
Series
Vcc
Vss
Vcc
Vss
(5) Pull-up/down resistors
TheMB90540/545Seriesdoesnotsupportinternalpull-up/downresistors(exceptPort0-Port3:pull-upresistors).
Use external components where needed.
14
MB90540/545 Series
(6) Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand
area for stabilizing the operation.
(7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply(AVCC, AVR+ , AVR− ) and analog inputs (AN0 to AN7) after
turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage not exceed AVR + or AVCC (turning on/off the analog and digital power supplies simultaneously
is acceptable).
(8) Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR+ = VSS.
(9) N.C. Pin
The N.C. (internally connected) pin must be opened for use.
(10) Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more ms (0.2 V to 2.7 V).
(11) Initialization
In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers
turning on the power again.
(12) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions
In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”), the value of the corre-
sponding bank register (DTB, ADB, USB, SSB) is set in “00h”.
If the values of the corresponding bank register (DTB,ADB,USB,SSB) are setting other than “00h”, the remainder
by the execution result of the instruction is not stored in the register of the instruction operand.
15
MB90540/545 Series
■ BLOCK DIAGRAM
X0,X1
X0A,X1A
RSTX
Clock
16LX
CPU
Controller
HSTX
IO Timer
RAM 6 KB
Input
Capture
8 ch.
IN[5:0]
IN[7:6]/OUT[3:2]
ROM 128 KB
/256 KB
Output
Compare
4 ch.
OUT[1:0]
Prescaler
UART0
8/16-bit
PPG
4 ch.
SOT0
SCK0
SIN0
PPG[3:0]
RX[1:0]*
TX[1:0]*
CAN
Controller
Prescaler
SOT1
SCK1
SIN1
UART1
(SCI)
16-bit Reload
Timer 2 ch.
TIN[1:0]
TOT[1:0]
Prescaler
Serial I/O
AD[15:00]
A[23:16]
ALE
SCK2
SOT2
SIN2
RD
External
Bus
Interface
WRL
AVCC
AVSS
AN[7:0]
AVR+
AVR-
WRH
HRQ
10-bit ADC
8 ch.
HAK
RDY
CLK
ADTG
External
Interrupt
INT[7:0]
16
MB90540/545 Series
■ MEMORY SPACE
The memory space of the MB90540/545 Series is shown below
MB90V540
MB90543/F543
MB90549/F549
FFFFFFH
FFFFFFH
FFFFFFH
ROM
ROM
ROM
(FF bank)
(FF bank)
(FF bank)
FF0000H
FEFFFFH
FF0000H
FEFFFFH
FF0000H
FEFFFFH
ROM
ROM
ROM
(FE bank)
(FE bank)
(FE bank)
FE0000H
FDFFFFH
FE0000H
FE0000H
FDFFFFH
ROM
ROM
(FD bank)
(FD bank)
FD0000H
FCFFFFH
FD0000H
FCFFFFH
ROM
External
ROM
(FC bank)
(FC bank)
FC0000H
FC0000H
External
External
00FFFFH
ROM
(Image of FF
bank)
00FFFFH
ROM
(Image of FF
bank)
00FFFFH
ROM
(Image of FF
bank)
004000H
003FFFH
004000H
003FFFH
004000H
003FFFH
Peripheral
External
Peripheral
External
Peripheral
External
003900H
003900H
002000H
0018FFH
003900H
002000H
0018FFH
0020FFH
001FF5H
001FF0H
ROM correction
RAM 8K
RAM 6K
RAM 6K
000100H
000100H
000100H
External
External
External
0000BFH
000000H
0000BFH
000000H
0000BFH
000000H
Peripheral
Peripheral
Peripheral
Memory space map
The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler
effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far spec-
ification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF4000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH
is visible only in bank FF.
17
MB90540/545 Series
■ I/O MAP
Address
00H
Register
Abbreviation Access
Pripheral
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
_ _ _ _ _ _ _XB
Port 0 data register
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 8 data register
Port 9 data register
Port A data register
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH to 0FH
10H
Reserved
Port 0 direction register
Port 1 direction register
Port 2 direction register
Port 3 direction register
Port 4 direction register
Port 5 direction register
Port 6 direction register
Port 7 direction register
Port 8 direction register
Port 9 direction register
Port A direction register
Analog Input Enable
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
ADER
PUCR0
PUCR1
PUCR2
PUCR3
UMC0
USR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port 6, A/D
Port 0
Port 1
Port 2
Port 3
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
_ _ _ _ _ _ _0B
1 1 1 1 1 1 1 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 1 0 0B
0 0 0 1 0 0 0 0B
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
Port 0 Pullup control register
Port 1 Pullup control register
Port 2 Pullup control register
Port 3 Pullup control register
Serial Mode Control Register 0
Status Register 0
21H
UART0
UIDR0/
UODR0
22H
23H
Input/Output Data Register 0
Rate and Data Register 0
R/W
R/W
XXXXXXXXB
URD0
0 0 0 0 0 0 0XB
(Continued)
18
MB90540/545 Series
Address
24H
Register
Abbreviation Access
Peripheral
Initial value
0 0 0 0 0 0 0 0B
0 0 0 0 0 1 0 0B
Serial Mode Register 1
Serial Control Register 1
SMR1
SCR1
R/W
R/W
25H
SIDR1/
SODR1
26H
Input/Output Data Register 1
R/W
XXXXXXXXB
UART1
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
Serial Status Register 1
UART1 Prescaler Control Register
Edge Selector
SSR1
U1CDCR
SES1
R/W
R/W
R/W
0 0 0 0 1_0 0B
0_ _ _1 1 1 1B
_ _ _ _ _ _ _0B
Reserved
Serial IO Prescaler
Serial Mode Control
SCDCR
SMCS
SMCS
SDR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0_ _ _1 1 1 1B
_ _ _ _0 0 0 0B
0 0 0 0 0 0 1 0B
XXXXXXXXB
Serial Mode Control
Serial IO
Serial Data
Edge Selector
SES2
_ _ _ _ _ _ _0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
External Interrupt Enable
External Interrupt Request
External Interrupt Level
External Interrupt Level
A/D Control Status 0
A/D Control Status 1
A/D Data 0
ENIR
EIRR
External Interrupt
A/D Converter
ELVR
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
ELVR
ADCS0
ADCS1
ADCR0
ADCR1
PPGC0
PPGC1
PPG01
A/D Data 1
R/W
R/W
R/W
R/W
0 0 0 0 1 _ XXB
0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
PPG0 operation mode control register
PPG1 operation mode control register
PPG0 and PPG1 clock select register
16-bit Programable
Pulse
Generator 0/1
Reserved
PPG2 operation mode control register
PPG3 operation mode control register
PPG2 and PPG3 clock select register
PPGC2
PPGC3
PPG23
R/W
R/W
R/W
0 _ 0 0 0 _ _1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
16-bit Programable
Pulse
Generator 2/3
Reserved
PPG4 operation mode control register
PPG5 operation mode control register
PPG4 and PPG5 clock select register
PPGC4
PPGC5
PPG45
R/W
R/W
R/W
0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
16-bit Programable
Pulse
Generator 4/5
Reserved
PPG6 operation mode control register
PPG7 operation mode control register
PPG6 and PPG7 clock select register
PPGC6
PPGC7
PPG67
R/W
R/W
R/W
0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
(Continued)
16-bit Programable
Pulse
Generator 6/7
19
MB90540/545 Series
Address
47H to 4BH
4CH
Register
Abbreviation Access
Peripheral
Initial value
Reserved
Input Capture Control Status 0/1
Input Capture Control Status 2/3
Input Capture Control Status 4/5
Input Capture Control Status 6/7
Timer Control Status 0
ICS01
ICS23
R/W
R/W
R/W
R/W
R/W
R/W
Input Capture 0/1 0 0 0 0 0 0 0 0B
Input Capture 2/3 0 0 0 0 0 0 0 0B
Input Capture 4/5 0 0 0 0 0 0 0 0B
Input Capture 6/7 0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
4DH
4EH
ICS45
4FH
ICS67
50H
TMCSR0
TMCSR0
51H
Timer Control Status 0
_ _ _ _ 0 0 0 0B
16-bit Reload
TMR0/
TMRLR0
52H
53H
Timer 0/Reload 0
Timer 0/Reload 0
R/W
R/W
XXXXXXXXB
Timer 0
TMR0/
TMRLR0
XXXXXXXXB
54H
55H
Timer Control Status 1
Timer Control Status 1
TMCSR1
TMCSR1
R/W
R/W
0 0 0 0 0 0 0 0B
_ _ _ _ 0 0 0 0B
16-bit Reload
TMR1/
TMRLR1
56H
57H
Timer 1/Reload 1
Timer 1/Reload 1
R/W
R/W
XXXXXXXXB
Timer 1
TMR1/
TMRLR1
XXXXXXXXB
58H
59H
Output Compare Control Status 0
Output Compare Control Status 1
Output Compare Control Status 2
Output Compare Control Status 3
OCS0
OCS1
OCS2
OCS3
R/W
R/W
R/W
R/W
0 0 0 0 _ _ 0 0B
_ _ _0 0 0 0 0B
0 0 0 0 _ _ 0 0B
_ _ _ 0 0 0 0 0B
Output Compare
0/1
5AH
Output Compare
2/3
5BH
5CH to 6BH
6CH
Reserved
Timer Data
Timer Data
Timer Control
ROM Mirror
TCDT
TCDT
TCCS
ROMM
R/W
R/W
R/W
R/W
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
_ _ _ _ _ _ _ 1B
6DH
I/O Timer
6EH
6FH
ROM Mirror
70H to 7FH
80H to 8F H
90H to 9D H
9EH
Reserved for CAN 0 Interface . Refer to “CAN Controller Hardware Manual”
Reserved for CAN 1 Interface . Refer to “CAN Controller Hardware Manual”
Reserved
ROM Correction Control Status
Delayed Interrupt/release
PACSR
DIRR
R/W
R/W
ROM Correction 0 0 0 0 0 0 0 0B
Delayed Interrupt _ _ _ _ _ _ _ 0B
9FH
Low Power
0 0 0 1 1 0 0 0B
Controller
A0H
Low-power Mode
Clock Selector
LPMCR
CKSCR
R/W
R/W
Low Power
1 1 1 1 1 1 0 0B
Controller
A1H
A2H to A4H
Reserved
(Continued)
20
MB90540/545 Series
(Continued)
Address
Register
Abbreviation Access
Peripheral
Initial value
0 0 1 1 _ _ 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 _B
A5H
A6H
Automatic ready function select reg.
External address output control reg.
Bus control signal select register
Watchdog Control
ARSR
HACR
ECSR
WDTC
TBTC
WTC
W
W
External Memory
Access
A7H
W
A8H
R/W
R/W
R/W
Watchdog Timer XXXXX 1 1 1B
Time Base Timer 1 - - 0 0 1 0 0B
A9H
Time Base Timer Control
AAH
Watch timer control register
Watch Timer
1 X 0 0 0 0 0 0B
ABH to ADH
Reserved
FMCS
Reserved
Flash Control Status
(Flash only, otherwise reserved)
AEH
R/W
Flash Memory 0 0 0 X 0 _ _ 0B
AFH
B0H
Interrupt control register 00
Interrupt control register 01
Interrupt control register 02
Interrupt control register 03
Interrupt control register 04
Interrupt control register 05
Interrupt control register 06
Interrupt control register 07
Interrupt control register 08
Interrupt control register 09
Interrupt control register 10
Interrupt control register 11
Interrupt control register 12
Interrupt control register 13
Interrupt control register 14
Interrupt control register 15
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
B1H
B2H
B3H
B4H
B5H
B6H
B7H
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
Interrupt
controller
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
COH to FFH
External
Address
1FF0H
1FF1H
1FF2H
1FF3H
1FF4H
1FF5H
Register
Abbreviation Access
Peripheral
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ROM Correction Address 0
ROM Correction Address 1
ROM Correction Address 2
ROM Correction Address 3
ROM Correction Address 4
ROM Correction Address 5
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
R/W
R/W
R/W
R/W
R/W
R/W
ROM Correction
21
MB90540/545 Series
Address
3900H
3901H
3902H
3903H
3904H
3905H
3906H
3907H
3908H
3909H
390AH
390BH
390CH
390DH
390EH
390FH
3910H to 3917H
3918H
3919H
391AH
391BH
391CH
391DH
391EH
391FH
3920H
3921H
3922H
3923H
3924H
3925H
3926H
3927H
Register
Reload L
Reload H
Reload L
Reload H
Reload L
Reload H
Reload L
Reload H
Reload L
Reload H
Reload L
Reload H
Reload L
Reload H
Reload L
Reload H
Abbreviation Access
Peripheral
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
PRLL0
PRLH0
PRLL1
PRLH1
PRLL2
PRLH2
PRLL3
PRLH3
PRLL4
PRLH4
PRLL5
PRLH5
PRLL6
PRLH6
PRLL7
PRLH7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16-bit Program-
able Pulse
Generator 0/1
16-bit Program-
able Pulse
Generator 2/3
16-bit Program-
able Pulse
Generator 4/5
16-bit Program-
able Pulse
Generator 6/7
Reserved
Input Capture 0
Input Capture 0
Input Capture 1
Input Capture 1
Input Capture 2
Input Capture 2
Input Capture 3
Input Capture 3
Input Capture 4
Input Capture 4
Input Capture 5
Input Capture 5
Input Capture 6
Input Capture 6
Input Capture 7
Input Capture 7
IPCP0
IPCP0
IPCP1
IPCP1
IPCP2
IPCP2
IPCP3
IPCP3
IPCP4
IPCP4
IPCP5
IPCP5
IPCP6
IPCP6
IPCP7
IPCP7
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
Input Captue 0/1
Input Captue 2/3
Input Captue 4/5
Input Captue 6/7
22
MB90540/545 Series
(Continued)
Address
Register
Abbreviation Access
Peripheral
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
3928H
3929H
Output Compare 0
Output Compare 0
Output Compare 1
Output Compare 1
Output Compare 2
Output Compare 2
Output Compare 3
Output Compare 3
OCCP0
OCCP0
OCCP1
OCCP1
OCCP2
OCCP2
OCCP3
OCCP3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Compare
0/1
392AH
392BH
392CH
392DH
Output Compare
2/3
392EH
392FH
3930H to 39FFH
3A00H to 3AFFH
3B00H to 3BFFH
3C00H to 3CFFH
3D00H to 3DFFH
3E00H to 3FFFH
Reserved
Reserved for CAN 0 Interface. Refer to “CAN Controller Hardware Manual”
Reserved for CAN 0 Interface. Refer to “CAN Controller Hardware Manual”
Reserved for CAN 1 Interface. Refer to “CAN Controller Hardware Manual”
Reserved for CAN 1 Interface. Refer to “CAN Controller Hardware Manual”
Reserved
Note Initial value of “_” represents unused bit, “X” represents unknown value.
Addressesintherange0000H to00FFH, whicharenotlistedinthetable, arereservedfortheprimaryfunctions
of the MCU. A read access to these reserved addresses results reading “X” and any write access should
not be performed.
23
MB90540/545 Series
■ CAN CONTROLLER
The MB90540 series contains two CAN controller (CAN0 and CAN1), the MB90545 series contains only one
(CAN0 ). The Evaluation Chip MB90V540 also has two CAN controller.
The CAN controller has the following features:
• Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats
• Supports transmitting of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as 1D acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbits/s to 1 Mbits/s (when input clock is at 16 MHz)
List of Control Registers
Address
Register
Abbreviation
BVALR
TREQR
TCANR
TCR
Access
R/W
R/W
W
Initial Value
CAN0
CAN1
000070H
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
Message buffer valid register
Transmit request register
Transmit cancel register
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
Transmit complete register
Receive complete register
Remote request receiving register
Receive overrun register
R/W
R/W
R/W
R/W
R/W
RCR
RRTRR
ROVRR
RIER
Receive interrupt enable register
24
MB90540/545 Series
List of Control Registers
Register Abbreviation Access
Address
Initial Value
CAN0
CAN1
003B00H
003B01H
003B02H
003B03H
003B04H
003B05H
003B06H
003B07H
003B08H
003B09H
003B0AH
003B0BH
003B0CH
003B0DH
003B0EH
003B0FH
003B10H
003B11H
003B12H
003B13H
003B14H
003B15H
003B16H
003B17H
003B18H
003B19H
003B1AH
003B1BH
003D00H
003D01H
003D02H
003D03H
003D04H
003D05H
003D06H
003D07H
003D08H
003D09H
003D0AH
003D0BH
003D0CH
003D0DH
003D0EH
003D0FH
003D10H
003D11H
003D12H
003D13H
003D14H
003D15H
003D16H
003D17H
003D18H
003D19H
003D1AH
003D1BH
Control status register
Last event indicator register
Receive/transmit error counter
Bit timing register
CSR
LEIR
R/W, R
R/W
R
00---000 0----0-1B
-------- 000-0000B
RTEC
BTR
00000000 00000000B
-1111111 11111111B
XXXXXXXX XXXXXXXXB
00000000 00000000B
XXXXXXXX XXXXXXXXB
00000000 00000000B
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
IDE register
IDER
Transmit RTR register
TRTRR
RFWTR
TIER
Remote frame receive waiting
register
Transmit interrupt enable reg-
ister
Acceptance mask select regis-
ter
AMSR
AMR0
AMR1
R/W
R/W
R/W
Acceptance mask register 0
Acceptance mask register 1
25
MB90540/545 Series
List of Message Buffers (ID Registers) (1)
Address
Register
Abbreviation Access
Initial Value
CAN0
CAN1
003A00H
to
003C00H
to
XXXXXXXXB
to
General-purpose RAM
R/W
003A1FH
003C1FH
XXXXXXXXB
003A20H
003A21H
003A22H
003A23H
003A24H
003A25H
003A26H
003A27H
003A28H
003A29H
003A2AH
003A2BH
003A2CH
003A2DH
003A2EH
003A2FH
003A30H
003A31H
003A32H
003A33H
003A34H
003A35H
003A36H
003A37H
003A38H
003A39H
003A3AH
003A3BH
003C20H
003C21H
003C22H
003C23H
003C24H
003C25H
003C26H
003C27H
003C28H
003C29H
003C2AH
003C2BH
003C2CH
003C2DH
003C2EH
003C2FH
003C30H
003C31H
003C32H
003C33H
003C34H
003C35H
003C36H
003C37H
003C38H
003C39H
003C3AH
003C3BH
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
ID register 0
ID register 1
ID register 2
ID register 3
ID register 4
ID register 5
ID register 6
IDR0
IDR1
IDR2
IDR3
IDR4
IDR5
IDR6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
26
MB90540/545 Series
List of Message Buffers (ID Registers) (2)
Register Abbreviation Access
Address
Initial Value
CAN0
CAN1
003A3CH
003A3DH
003A3EH
003A3FH
003A40H
003A41H
003A42H
003A43H
003A44H
003A45H
003A46H
003A47H
003A48H
003A49H
003A4AH
003A4BH
003A4CH
003A4DH
003A4EH
003A4FH
003A50H
003A51H
003A52H
003A53H
003A54H
003A55H
003A56H
003A57H
003A58H
003A59H
003A5AH
003A5BH
003A5CH
003A5DH
003A5EH
003A5FH
003C3CH
003C3DH
003C3EH
003C3FH
003C40H
003C41H
003C42H
003C43H
003C44H
003C45H
003C46H
003C47H
003C48H
003C49H
003C4AH
003C4BH
003C4CH
003C4DH
003C4EH
003C4FH
003C50H
003C51H
003C52H
003C53H
003C54H
003C55H
003C56H
003C57H
003C58H
003C59H
003C5AH
003C5BH
003C5CH
003C5DH
003C5EH
003C5FH
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
ID register 7
IDR7
IDR8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ID register 8
ID register 9
ID register 10
ID register 11
ID register 12
ID register 13
ID register 14
ID register 15
IDR9
IDR10
IDR11
IDR12
IDR13
IDR14
IDR15
27
MB90540/545 Series
List of Message Buffers (DLC Registers and Data Registers) (1)
Register Abbreviation Access
Address
Initial Value
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
CAN0
CAN1
003A60H
003A61H
003A62H
003A63H
003A64H
003A65H
003A66H
003A67H
003A68H
003A69H
003A6AH
003A6BH
003A6CH
003A6DH
003A6EH
003A6FH
003C60H
003C61H
003C62H
003C63H
003C64H
003C65H
003C66H
003C67H
003C68H
003C69H
003C6AH
003C6BH
003C6CH
003C6DH
003C6EH
003C6FH
DLC register 0
DLCR0
DLCR1
DLCR2
DLCR3
DLCR4
DLCR5
DLCR6
DLCR7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DLC register 1
DLC register 2
DLC register 3
DLC register 4
DLC register 5
DLC register 6
DLC register 7
28
MB90540/545 Series
List of Message Buffers (DLC Registers and Data Registers) (2)
Register Abbreviation Access
Address
Initial Value
----XXXX
CAN0
CAN1
003A70H
003A71H
003A72H
003A73H
003A74H
003A75H
003A76H
003A77H
003A78H
003A79H
003A7AH
003A7BH
003A7CH
003A7DH
003A7EH
003A7FH
003C70H
003C71H
003C72H
003C73H
003C74H
003C75H
003C76H
003C77H
003C78H
003C79H
003C7AH
003C7BH
003C7CH
003C7DH
003C7EH
003C7FH
DLC register 8
DLCR8
DLCR9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DLC register 9
DLC register 10
DLC register 11
DLC register 12
DLC register 13
DLC register 14
DLC register 15
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
DLCR10
DLCR11
DLCR12
DLCR13
DLCR14
DLCR15
003A80H
to
003A87H
003C80H
to
003C87H
XXXXXXXXB
to
XXXXXXXXB
Data register 0 (8 bytes)
Data register 1 (8 bytes)
Data register 2 (8 bytes)
Data register 3 (8 bytes)
Data register 4 (8 bytes)
Data register 5 (8 bytes)
Data register 6 (8 bytes)
DTR0
DTR1
DTR2
DTR3
DTR4
DTR5
DTR6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
003A88H
to
003A8FH
003C88H
to
003C8FH
XXXXXXXXB
to
XXXXXXXXB
003A90H
to
003A97H
003C90H
to
003C97H
XXXXXXXXB
to
XXXXXXXXB
003A98H
to
003A9FH
003C98H
to
003C9FH
XXXXXXXXB
to
XXXXXXXXB
003AA0H
to
003AA7H
003CA0H
to
003CA7H
XXXXXXXXB
to
XXXXXXXXB
003AA8H
to
003AAFH
003CA8H
to
003CAFH
XXXXXXXXB
to
XXXXXXXXB
003AB0H
to
003CB0H
to
XXXXXXXXB
to
003AB7H
003CB7H
XXXXXXXXB
29
MB90540/545 Series
List of Message Buffers (DLC Registers and Data Registers) (3)
Address
Register
Abbreviation Access
Initial Value
CAN0
CAN1
003AB8H
to
003ABFH
003CB8H
to
003CBFH
XXXXXXXXB
to
XXXXXXXXB
Data register 7 (8 bytes)
DTR7
DTR8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
003AC0H
to
003AC7H
003CC0H
to
003CC7H
XXXXXXXXB
to
XXXXXXXXB
Data register 8 (8 bytes)
Data register 9 (8 bytes)
Data register 10 (8 bytes)
Data register 11 (8 bytes)
Data register 12 (8 bytes)
Data register 13 (8 bytes)
Data register 14 (8 bytes)
Data register 15 (8 bytes)
003AC8H
to
003ACFH
003CC8H
to
003CCFH
XXXXXXXXB
to
XXXXXXXXB
DTR9
003AD0H
to
003AD7H
003CD0H
to
003CD7H
XXXXXXXXB
to
XXXXXXXXB
DTR10
DTR11
DTR12
DTR13
DTR14
DTR15
003AD8H
to
003ADFH
003CD8H
to
003CDFH
XXXXXXXXB
to
XXXXXXXXB
003AE0H
to
003AE7H
003CE0H
to
003CE7H
XXXXXXXXB
to
XXXXXXXXB
003AE8H
to
003AEFH
003CE8H
to
003CEFH
XXXXXXXXB
to
XXXXXXXXB
003AF0H
to
003AF7H
003CF0H
to
003CF7H
XXXXXXXXB
to
XXXXXXXXB
003AF8H
to
003CF8H
to
XXXXXXXXB
to
003AFFH
003CFFH
XXXXXXXXB
30
MB90540/545 Series
■ INTERRUPT MAP
Interrupt vector
Number Address
Interrupt control register
I2OS
clear
Interrupt cause
Number
Address
Reset
N/A
N/A
N/A
N/A
N/A
N/A
N/A
*1
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
#37
#38
#39
#40
#41
#42
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
INT9 instruction
Exception
CAN 0 RX
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
0000BEH
0000BFH
CAN 0 TX/NS
CAN 1 RX
CAN 1 TX/NS
External Interrupt INT0/INT1
Time Base Timer
16-bit Reload Timer 0
A/D Converter
N/A
*1
*1
I/O Timer
N/A
*1
External Interrupt INT2/INT3
Serial I/O
*1
PPG 0/1
N/A
*1
Input Capture 0
External Interrupt INT4/INT5
Input Capture 1
PPG 2/3
*1
*1
N/A
*1
External Interrupt INT6/INT7
Watch Timer
N/A
N/A
*1
PPG 4/5
Input Capture 2/3
PPG 6/7
N/A
*1
Output Compare 0
Output Compare 1
Input Capture 4/5
Output Compare 2/3 - Input Capture 6/7
16-bit Reload Timer 1
UART 0 RX
*1
*1
*1
*1
*2
UART 0 TX
*1
UART 1 RX
*2
UART 1 TX
*1
Flash Memory
N/A
N/A
Delayed interrupt
31
MB90540/545 Series
*1: The interrupt request flag is cleared by the I2OS interrupt clear signal.
*2: The interrupt request flag is cleared by the I2OS interrupt clear signal. A stop request is available.
N/A:The interrupt request flag is not cleared by the I2OS interrupt clear signal.
Note: For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags
are cleared by the I2OS interrupt clear signal.
Note: At the end of I2OS, the I2OS clear signal will be asserted for all the interrupt flags assigned to the same
interrupt number. If one interrupt flag starts the I2OS and in the meantime another interrupt flag is set by
hardware event, the later event is lost because the flag is cleared by the I2OS clear signal caused by the first
event. So it is recommended not to use the I2OS for this interrupt number.
Note: If I2OS is enabled, I2OS is initiated when one of the two interrupt signals in the same interrupt control register
(ICR) is asserted. This means that different interrupt sources share the same I2OS Descriptor which should
be unique for each interrupt source. For this reason, when one interrupt source uses the I2OS, the other
interrupt should be disabled.
32
MB90540/545 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0V)
Value
Min. Max.
Parameter
Symbol
Units
Remarks
VCC
AVCC
AVR±
VI
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
Power supply voltage
VCC = AVCC
AVCC ≥ AVR ±, AVR+ ≥ AVR–
*1
V
Input voltage
V
*2
*2
Output voltage
VO
V
Clamp Current
ICLAMP
IOL
− 2.0
2.0
15
4
mA
mA
"L" level max. output current
"L" level avg. output current
IOLAV
mA Average value over a period of 100ms
"L" level max. overall output
current
∑IOL
100
50
mA
"L" level avg. overall output
current
∑IOLAV
mA Average value over a period of 100ms
"H" level max. output current
"H" level avg. output current
IOH
−15
−4
mA
IOHAV
mA Average value over a period of 100ms
"H" level max. overall output
current
∑IOH
−100
−50
mA
"H" level avg. overall output
current
∑IOHAV
mA Average value over a period of 100ms
500
400
mW MB90F543/F549
Power consumption
PD
mW MB90543/549
Operating temperature
Storage temperature
TA
−40
−55
+85
°C
°C
TSTG
+150
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*2: VI and VO should not exceed VCC + 0.3V. VI should not exceed the specified ratings. However if the maximum
current to/from a input is limited by some means with external components, the II rating supercedes the VI rating.
33
MB90540/545 Series
2. Recommended Conditions
(VSS = AVSS = 0V)
Remarks
Value
Typ.
5.0
Parameter
Power supply voltage
Input H voltage
Symbol
Units
Min.
4.5
Max.
5.5
VCC
VIHS
VIHM
VILS
VILM
V
V
V
V
V
0.8 VCC
VCC − 0.3
VSS − 0.3
VSS − 0.3
VCC + 0.3
VCC + 0.3
0.2 VCC
VSS + 0.3
CMOS hysteresis input pin
MD input pin
CMOS hysteresis input pin
MD input pin
Input L voltage
Use a ceramic capacitor or capacitor
of better AC characteristics. Capaci-
tor at the VCC should be greater than
this capacitor.
Smooth capacitor
CS
TA
0.022
0.1
1.0
µF
°C
Operating temperature
−40
+85
• C Pin Connection Diagram
C
CS
34
MB90540/545 Series
3. DC Characteristics
Parameter Symbol Pin
(VCC = 5.0 V±10%, VSS = AVSS = 0V, TA = −40 °C to +85 °C)
Value
Condition
Units
Remarks
Min.
Typ.
Max.
All
output
pins
Output H
voltage
VCC = 4.5V,
IOH = −4.0mA
VCC –
0.5
VOH
—
—
V
All
output
pins
Output L
voltage
VCC = 4.5V,
IOL = 4.0mA
VOL
—
—
—
0.4
5
V
Input leak
current
VCC = 5.5V,
VSS < VI < VCC
IIL
–5
µA
VCC = 5.0 V±10%,
Internal frequency: 16 MHz,
At normal operating
—
—
—
—
—
—
—
—
—
—
TBD
45
TBD
60
mA MB90543/549
mA MB90F543/F549
mA MB90543/549
mA MB90F543/F549
mA MB90543/549
mA MB90F543/F549
µA MB90543/549
µA MB90F543/F549
µA MB90543/549
µA MB90F543/F549
ICC
VCC = 5.0V±10%,
Internal frequency: 16 MHz,
At sleep
TBD
13
TBD
22
ICCS
VCC = 5.0V,
Internal frequency: 8 kHz,
At sub operation
TBD
0.2
TBD
1
ICCL
Power
supply
current*
VCC = 5.0V,
Internal frequency: 8 kHz,
At sub sleep
TBD
10
TBD
50
VCC
ICCLS
VCC = 5.0V,
Internal frequency: 8 kHz,
At watch mode
TBD
10
TBD
50
ICCT
ICCH1
ICCH2
—
—
—
TBD
5
TBD
20
µA MB90543/549
µA MB90F543/F549
µA MB90543/549
VCC = 5.0 V±10%,
At stop, TA = 25°C
VCC = 5.0 V±10%,
At hardware standby mode,
TA = 25°C
TBD
TBD
—
50
100
µA MB90F543/F549
Other
than
AVCC,
AVSS,
AVR+,
AVR−,
C,
Input
capacity
CIN
—
—
10
80
pF
VCC,
VSS
*: Current values are tentative. They are subject to change without notice according to improvements in the
characteristics. The power supply current testing conditions are when using the external clock.
35
MB90540/545 Series
4. AC Characteristics
(1) Clock Timing
(VCC = 5.0 V±10%, VSS = AVSS = 0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Pin
Units
Remarks
Min.
3
Typ.
—
Max.
16
fC
X0, X1
X0A, X1A
X0, X1
MHz
kHz
ns
Oscillation frequency
Oscillation cycle time
fCL
—
32.768
—
—
tCYL
tLCYL
62.5
—
333
—
X0A, X1A
30.5
µs
Frequency deviation with
PLL *
∆f
—
—
—
5
%
PWH, PWL
X0
10
—
—
—
—
ns
Input clock pulse width
Duty ratio is about 30 to 70%.
PWLH,PWLL
X0A
15.2
µs
Input clock rise and fall
time
tCR, tCF
X0
—
—
5
ns When using external clock
fCP
fLCP
tCP
—
—
—
—
1.5
—
—
16
—
MHz When using main clock
kHz When using sub-clock
ns When using main clock
µs When using sub-clock
Machine clock frequency
Machine clock cycle time
8.192
—
62.5
—
666
—
tLCP
122.1
* : Frequency deviation indicates the maximum frequency difference from the target frequency when using a
multiplied clock.
+α
α
------
y fO
requenc
Central f
∆f =
× 100%
fo
−α
• Clock Timing
tCYL
0.8 VCC
0.2 VCC
X0
PWH
PWL
tCF
tLCYL
tCR
0.8 VCC
0.2 VCC
X0A
PWLH
PWLL
tCF
tCR
36
MB90540/545 Series
• Guaranteed operation range
Guaranteed operation range for MB90F543/F549
5.5
4.5
Power supply voltage
VCC (V)
3.3
3.0
Guaranteed operation range of
MB90543/549 and MB90V540
Guaranteed PLL operation range
1.5
3
8
12
16
Machine clock fCP (MHz)
• Ocsillation clock frequency and Machine clock frequency
×1
×4
×3
×2
16
12
Machine clock
fCP (MHz)
9
8
×1/2
(PLL off)
4
3
4
8
16
Oscillation clock fC (MHz)
AC characteristics are set to the measured reference voltage values below.
• Output signal waveform
• Input signal waveform
Hysteresis Input Pin
Output Pin
2.4 V
0.8 V
0.8 VCC
0.2 VCC
37
MB90540/545 Series
(2) Clock Output Timing
(VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Cycle time
Symbol
Pin
Condition
Units
Remarks
Min. Max.
tCYC
62.5
20
—
—
ns
ns
CLK
VCC = 5 V±10%
CLK ↑
CLK ↓
tCHCL
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
(3) Reset and Hardware Standby Input
(VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Pin
Units
Remarks
Min.
16 tCP
16 tCP
Max.
—
Reset input time
Hardware standby input time
tRSTL
tHSTL
RST
HST
ns
ns
—
“tcp” represents one cycle time of the machine clock.
Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm.
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
38
MB90540/545 Series
(4) Power On Reset
Parameter
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin
Condition
Units
Remarks
Min. Max.
Power on rise time
Power off time
tR
VCC
VCC
0.05
50
30
—
ms
—
tOFF
ms Due to repetitive operation
tR
3.5 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If you change the power supply voltage too rapidly, a power on reset may occur.
We recommend that you startup smoothly by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below. Perform
while not using the PLL clock. However, if voltage drops are within 1 mV/sec, you
can operate while using the PLL clock.
VCC
TBD
VSS
We recommend a rise of
50 mV/ms maximum.
Holds RAM data
39
MB90540/545 Series
(5) Bus Timing (Read)
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = −40 °C to +85 °C)
Value
Parameter
ALE pulse width
Symbol
Pin
Condition
Units Remarks
Min.
Max.
tLHLL
ALE
tCP/2 − 20
ns
ALE,
A23 to A16,
AD15 to
AD00
Valid address
ALE ↓ time
tAVLL
tCP/2 − 20
—
ns
ALE, AD15
to AD00
ALE ↓
Address valid time
tLLAX
tCP/2 − 15
tCP − 15
—
—
ns
ns
A23 toA16,
AD15 to
AD00, RD
Valid address
Valid address
RD pulse width
RD ↓ time
tAVRL
A23 to A16,
AD15 to
AD00
Valid data
input
tAVDV
—
5 tCP/2 − 60 ns
ns
3 tCP/2 − 60 ns
—
tRLRH
tRLDV
RD
3 tCP/2 − 20
—
RD, AD15 to
AD00
RD ↓
Valid data input
Data hold time
—
RD, AD15 to
AD00
RD ↑
RD ↓
RD ↑
tRHDX
tRHLH
tRHAX
0
—
—
—
ns
ns
ns
ALE ↑ time
RD, ALE
tCP/2 − 15
tCP/2 − 10
RD, A23 to
A16
Address valid time
A23 to A16,
AD15 to
Valid address
CLK ↑ time
tAVCH
tCP/2 − 20
—
ns
AD00, CLK
RD ↓
CLK ↑ time
RD ↓ time
tRLCH
tLLRL
RD, CLK
ALE, RD
tCP/2 − 20
tCP/2 − 15
—
—
ns
ns
ALE ↓
40
MB90540/545 Series
• Bus Timing (Read)
tRLCH
2.4 V
tAVCH
2.4 V
CLK
tLLAX
tAVLL
tRHLH
2.4 V
2.4 V
0.8 V
2.4 V
ALE
RD
tLHLL
tAVRL
tRLRH
2.4 V
0.8 V
tLLRL
tRHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tRLDV
tRHDX
tAVDV
2.4 V
0.8 V
0.8 VCC
0.2 VCC
2.4 V
0.8 V
0.8 VCC
0.2 VCC
AD15 to AD00
Address
Read data
41
MB90540/545 Series
(6) Bus Timing (Write)
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Pin
Condition
Units Remarks
Min.
Max.
A23 to A16,
AD15 to AD00,
WR
Valid address
WR ↓ time
tAVWL
tCP – 15
—
ns
WR pulse width
Valid data output
tWLWH
tDVWH
tWHDX
tWHAX
WR
3 tCP/2 – 20
3 tCP/2 – 20
—
—
ns
ns
AD15 to AD00,
WR
WR ↑ time
—
AD15 to AD00,
WR
WR ↑
WR ↑
Data hold time
20
—
—
ns
ns
A23 to A16,
WR
Address valid time
tCP/2 – 10
WR ↑
WR ↓
ALE ↑ time
CLK ↑ time
tWHLH
tWLCH
WR, ALE
WR, CLK
tCP/2 – 15
tCP/2 – 20
—
—
ns
ns
• Bus Timing (Write)
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tDVWH
tWHDX
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
AD15 to AD00
Address
Write data
42
MB90540/545 Series
(7) Ready Input Timing
Parameter
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin
Condition
Units
Remarks
Min.
45
Max.
—
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
ns
ns
—
0
—
Note: If the RDY setup time is insufficient, use the auto-ready function.
• Ready Input Timing
2.4 V
CLK
ALE
RD/WR
tRYHS
0.8 VCC
tRYHH
0.8 VCC
RDY
no WAIT is used.
RDY
0.2 VCC
When WAIT is used
(1 cycle).
43
MB90540/545 Series
(8) Hold Timing
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Pin
Condition
Units
Remarks
Min.
30
Max.
tCP
Pin floating
HAK ↑ time
HAK ↓ time
tXHAL
tHAHV
HAK
HAK
ns
ns
—
Pin valid time
tCP
2 tCP
Note: There is more than 1 cycle from when HRQ reads in until the HAK is changed.
• Hold Timing
2.4 V
HAK
0.8 V
tHAHV
2.4 V
0.8 V
tXHAL
High impedance
2.4 V
0.8 V
Each pin
(9) UART0/1, Serial I/O Timing
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = –40 °C to +85 °C)
Value
Parameter
Symbol
Pin Symbol
Condition
Units Remarks
Min. Max.
Serial clock cycle time
tSCYC
tSLOV
tIVSH
tSHIX
SCK0 to SCK2
8 tCP
—
ns
ns
SCK0 to SCK2,
SOT0 to SOT2
SCK ↓
SOT delay time
SCK ↑
–80
80
Internal clock opera-
tion output pins are
CL = 80 pF + 1 TTL.
SCK0 to SCK2,
SIN0 to SIN2
Valid SIN
SCK ↑
100
60
—
—
ns
ns
SCK0 to SCK2,
SIN0 to SIN2
Valid SIN hold time
Serial clock "H" pulse width
Serial clock "L" pulse width
tSHSL
tSLSH
SCK0 to SCK2
SCK0 to SCK2
4 tCP
4 tCP
—
—
ns
ns
SCK0 to SCK2,
SOT0 to SOT2
SCK ↓
SOT delay time
SCK ↑
tSLOV
tIVSH
tSHIX
External clock oper-
ation output pins are
CL = 80 pF + 1 TTL.
—
60
60
150
—
ns
ns
ns
SCK0 to SCK2,
SIN0 to SIN2
Valid SIN
SCK0 to SCK2,
SIN0 to SIN2
SCK ↑
Valid SIN hold time
—
Note:
1. AC characteristic in CLK synchronized mode.
2. CL is load capacity value of pins when testing.
3. tCP is the machine cycle (Unit: ns).
44
MB90540/545 Series
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• External Shift Clock Mode
tSLSH
tSHSL
0.8 VCC 0.8 VCC
SCK
0.2 VCC 0.2 VCC
tSLOV
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
45
MB90540/545 Series
(10) Timer Related Resource Input Timing
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Pin
Condition
Units Remarks
Min.
Max.
tTIWH
tTIWL
TIN0, TIN1
IN0 to IN7
Input pulse width
—
4 tCP
—
ns
• Timer Input Timing
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tTIWH
tTIWL
(11) Timer Related Resource Output Timing
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Pin
Condition
Units
Remarks
Min.
Max.
TOT0 to TOT1,
PPG0 to PPG3
CLK ↑
TOUT change time
tTO
—
30
—
ns
• Timer Output Timing
2.4 V
CLK
2.4 V
0.8 V
TOUT
tTO
46
MB90540/545 Series
(12) Trigger Input Timing
(VCC = 4.5 to 5.5 V, VSS = 0 V, TA = –40 °C to +85 °C)
Value
Parameter
Symbol
Pin
Condition
Units
Remarks
Min.
Max.
tTRGH
tTRGL
INT0 to
INT7, ADTG
Input pulse width
—
5 tCP
—
ns
• Trigger Input Timing
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tTRGH
tTRGL
47
MB90540/545 Series
5. A/D Converter
( VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0 V,3.0 V ≤ AVR+ − AVR−, TA = −40 °C to +85 °C)
Rated Value
Typ.
Parameter
Resolution
Symbol
Pin
Units Remarks
Min.
—
Max.
10
—
—
—
—
—
—
bit
Conversion error
—
—
—
—
±5.0
±2.5
±1.9
LSB
LSB
LSB
Nonlinearity error
—
—
Differential nonlinearity error
Zero reading voltage
Full scale reading voltage
Conversion time
—
—
VOT
VFST
—
AN0 to AN7 AVR− − 3.5 AVR- + 0.5 AVR− + 4.5 mV
AN0 to AN7 AVR+ − 6.5 AVR+ − 1.5 AVR+ + 1.5 mV
—
—
—
352tCP
64tCP
—
—
ns
ns
Sampling time
—
—
—
Analog port input current
Analog input voltage range
IAIN
VAIN
—
AN0 to AN7
AN0 to AN7
AVR+
−10
10
µA
AVR−
—
AVR+
V
AVR− + 2.7
—
AVCC
V
Reference voltage range
Power supply current
—
AVR−
0
—
—
AVR+ − 2.7
V
IA
AVCC
5
—
5
mA
µA *1
µA
IAH
IR
AVCC
—
—
AVR+
200
—
400
—
600
5
Reference voltage current
IRH
—
AVR+
µA *1
LSB
Offset between input channels
AN0 to AN7
—
—
4
*1: When not operating A/D converter, this is the current (VCC = AVCC = AVR+ = 5.0 V) when the CPU is stopped.
48
MB90540/545 Series
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00
0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual
conversion characteristics
Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error:The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF
0.5 LSB
3FE
3FD
Actual conversion
value
{1 LSB × (N – 1) + 0.5 LSB}
004
003
002
001
VNT
(mesured value)
Actual conversion
characteristics
Theoretical
characteristics
0.5 LSB
Analog input
AVR −
AVR +
AVR + – AVR −
VNT – {1 LSB × (N – 1) + 0.5 LSB}
1 LSB = (Theoretical value)
[V]
Total error for digital output N
[LSB]
=
1024
1 LSB
VNT: Voltage at a transition of digital output from (N – 1) to N
VOT (Theoretical value) = AVR − + 0.5 LSB[V]
VFST (Theoretical value) = AVR + – 1.5 LSB[V]
(Continued)
49
MB90540/545 Series
(Continued)
Linearity error
Differential linearity error
Theoretical characteristics
3FF
Actual conversion
3FE
3FD
value
N + 1
Actual conversion value
{1 LSB × (N – 1)+ VOT}
VFST
(mesured value)
N
VNT
004
003
002
001
V(N + 1)T
Actual conversion
characteristics
(mesured value)
N – 1
N – 2
VNT (mesured value)
Theoretical
Actual conversion
value
characteristics
VOT (mesured value)
Analog input
AVR −
AVR +
AVR −
Analog input
AVR +
Linearity error of
digital output N
VNT – {1 LSB × (N – 1) + VOT}
[LSB]
=
1 LSB
Differential linearity error
of digital N
V(N + 1)T – VNT
1 LSB
– 1 LSB [LSB]
=
VFST – VOT
1 LSB
[V]
=
1022
VOT: Voltage at transition of digital output from “000H” to “001H”
VFST: Voltage at transition of digital output from “3FEH” to “3FFH”
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions.
Output impedance values of the external circuit of 15 kΩ or lower are recommended.
When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor
value is recommended to minimized the effect of voltage distribution between the external capacitor and internal
capacitor.
When the output impedance of the external circuit is too high, the sampling period for analog voltages may not
be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz).
• Equipment of analog input circuit model
C0
Analog input
Comparator
C1
Note: Listed values must be considered as standards.
• Error
The smaller the | AVR + − AVR− |, the greater the error would become relatively.
50
MB90540/545 Series
■ INSTRUCTIONS (340 INSTRUCTIONS)
Table 1 Explanation of Items in Tables of Instructions
Meaning
Mnemonic Upper-case letters and symbols: Represented as they appear in assembler.
Lower-case letters: Replaced when described in assembler.
Item
Numbers after lower-case letters:Indicate the bit width within the instruction code.
#
~
Indicates the number of bytes.
Indicates the number of cycles.
m: When branching
n : When not branching
See Table 4 for details about meanings of other letters in items.
RG
B
Indicates the number of accesses to the register during execution of the instruction.
It is used calculate a correction value for intermittent operation of CPU.
Indicates the correction value for calculating the number of actual cycles during execution of the
instruction. (Table 5)
The number of actual cycles during execution of the instruction is the correction value summed
with the value in the “~” column.
Operation
LH
Indicates the operation of instruction.
Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.
Z : Transfers “0”.
X : Extends with a sign before transferring.
– : Transfers nothing.
AH
Indicates special operations involving the upper 16 bits in the accumulator.
* : Transfers from AL to AH.
– : No transfer.
Z : Transfers 00H to AH.
X : Transfers 00H or FFH to AH by signing and extending AL.
I
S
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),
N (negative), Z (zero), V (overflow), and C (carry).
* : Changes due to execution of instruction.
– : No change.
T
S : Set by execution of instruction.
N
R : Reset by execution of instruction.
Z
V
C
RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that
reads data from memory, etc., processes the data, and then writes the result to memory.)
* : Instruction is a read-modify-write instruction.
– : Instruction is not a read-modify-write instruction.
Note: A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
• Number of execution cycles
The number of cycles required for instruction execution is acquired by adding the number of cycles for each
instruction, a corrective value depending on the condition, and the number of cycles required for program fetch.
Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal
ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution
cycles is increased.
For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data
bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased.
When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external
bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles
specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number
of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the
number of times access is done × the number of cycles suspended as the corrective value to the number of
ordinary execution cycles.
51
MB90540/545 Series
Table 2 Explanation of Symbols in Tables of Instructions
Meaning
Symbol
A
32-bit accumulator
The bit length varies according to the instruction.
Byte : Lower 8 bits of AL
Word : 16 bits of AL
Long : 32 bits of AL and AH
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
PC
Stack pointer (USP or SSP)
Program counter
PCB
DTB
ADB
SSB
USB
SPB
DPR
brg1
brg2
Ri
Program bank register
Data bank register
Additional data bank register
System stack bank register
User stack bank register
Current stack bank register (SSB or USB)
Direct page register
DTB, ADB, SSB, USB, DPR, PCB, SPB
DTB, ADB, SSB, USB, DPR, SPB
R0, R1, R2, R3, R4, R5, R6, R7
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RW0, RW1, RW2, RW3
RWi
RWj
RLi
RL0, RL1, RL2, RL3
dir
Compact direct addressing
addr16
addr24
ad24 0 to 15
ad24 16 to 23
Direct addressing
Physical direct addressing
Bit 0 to bit 15 of addr24
Bit 16 to bit 23 of addr24
io
I/O area (000000H to 0000FFH)
imm4
imm8
4-bit immediate data
8-bit immediate data
imm16
imm32
ext (imm8)
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
disp8
disp16
8-bit displacement
16-bit displacement
bp
Bit offset
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
rel
Bit address
PC relative addressing
ear
eam
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
rlst
Register list
52
MB90540/545 Series
Table 3 Effective Address Fields
Address format
RL0 Register direct
Number of bytes in address
extension *
Code
Notation
00
01
02
03
04
05
06
07
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
(RL0)
RL1 “ea” corresponds to byte, word, and
(RL1) long-word types, starting from the left
RL2
(RL2)
RL3
—
(RL3)
08
09
0A
0B
@RW0
Register indirect
@RW1
@RW2
@RW3
0
0
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
1
2
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
Note : The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)
column in the tables of instructions.
53
MB90540/545 Series
Table 4 Number of Execution Cycles for Each Type of Addressing
(a)
Number of register accesses
for each type of addressing
Code
Operand
Number of execution cycles
for each type of addressing
Ri
RWi
RLi
00 to 07
Listed in tables of instructions Listed in tables of instructions
08 to 0B
0C to 0F
10 to 17
18 to 1B
@RWj
2
4
2
2
1
2
1
1
@RWj +
@RWi + disp8
@RWj + disp16
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Note : “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.
Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles
(b) byte
(c) word
(d) long
Operand
Cycles
Access
Cycles
Access
Cycles
Access
Internal register
+0
1
+0
1
+0
2
Internal memory even address
Internal memory odd address
+0
+0
1
1
+0
+2
1
2
+0
+4
2
4
Even address on external data bus (16 bits)
Odd address on external data bus (16 bits)
+1
+1
1
1
+1
+4
1
2
+2
+8
2
4
External data bus (8 bits)
+1
1
+4
2
+8
4
Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)
in the tables of instructions.
• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
Instruction
Internal memory
Byte boundary
Word boundary
—
—
+3
+2
+3
—
External data bus (16 bits)
External data bus (8 bits)
Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
• Because instruction execution is not slowed down by all program fetches in actuality, these correction
values should be used for “worst case” calculations.
54
MB90540/545 Series
Table 7 Transfer Instructions (Byte) [41 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
2
3
1
2
3
4
2
2
0
0
1
1
0
0
0
0
2
0
(b) byte (A) ← (dir)
(b) byte (A) ← (addr16)
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
byte (A) ← (Ri)
byte (A) ← (ear)
2+ 3+ (a)
(b) byte (A) ← (eam)
(b) byte (A) ← (io)
2
2
2
3
1
3
2
3
10
1
0
byte (A) ← imm8
(b) byte (A) ← ((A))
(b) byte (A) ← ((RLi)+disp8) Z
MOVN A, #imm4
0
byte (A) ← imm4
Z
– R
MOVX A, dir
MOVX A, addr16
MOVX A, Ri
MOVX A, ear
MOVX A, eam
MOVX A, io
MOVX A, #imm8
MOVX A, @A
MOVX A,@RWi+disp8
MOVX A, @RLi+disp8
2
3
2
2
3
4
2
2
0
0
1
1
0
0
0
0
1
2
(b) byte (A) ← (dir)
(b) byte (A) ← (addr16)
X
X
X
X
X
X
X
X
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
byte (A) ← (Ri)
byte (A) ← (ear)
2+ 3+ (a)
(b) byte (A) ← (eam)
(b) byte (A) ← (io)
2
2
2
2
3
3
2
3
5
10
0
byte (A) ← imm8
(b) byte (A) ← ((A))
(b) byte (A) ← ((RWi)+disp8) X
(b) byte (A) ← ((RLi)+disp8) X
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
Ri, ear
Ri, eam
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
@AL, AH
2
3
1
2
3
4
2
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
(b) byte (dir) ← (A)
(b) byte (addr16) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
byte (Ri) ← (A)
byte (ear) ← (A)
2+ 3+ (a)
(b) byte (eam) ← (A)
(b) byte (io) ← (A)
(b) byte ((RLi) +disp8) ← (A) –
2
3
2
3
10
3
0
byte (Ri) ← (ear)
(b) byte (Ri) ← (eam)
byte (ear) ← (Ri)
(b) byte (eam) ← (Ri)
byte (Ri) ← imm8
–
–
–
–
–
–
–
–
–
2+ 4+ (a)
2
2+ 5+ (a)
2
3
3
3
4
0
2
5
5
2
0
(b) byte (io) ← imm8
(b) byte (dir) ← imm8
0
byte (ear) ← imm8
3+ 4+ (a)
(b) byte (eam) ← imm8
/MOV @A, T
2
2
3
0
(b) byte ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
XCH
XCH
XCH
XCH
A, ear
4
2
0
4
2
0
byte (A) ↔ (ear)
2× (b) byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
2× (b) byte (Ri) ↔ (eam)
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A, eam
Ri, ear
Ri, eam
2+ 5+ (a)
2
2+ 9+ (a)
7
0
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
55
MB90540/545 Series
Table 8 Transfer Instructions (Word/Long Word) [38 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
MOVW A, dir
MOVW A, addr16
MOVW A, SP
MOVW A, RWi
MOVW A, ear
MOVW A, eam
MOVW A, io
MOVW A, @A
#
~
B
Operation
2
3
1
1
2
3
4
1
2
2
0
0
0
1
1
0
0
0
0
1
2
(c) word (A) ← (dir)
(c) word (A) ← (addr16)
0
0
0
(c) word (A) ← (eam)
(c) word (A) ← (io)
(c) word (A) ← ((A))
0
(c)
(c)
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
2+ 3+ (a)
2
2
3
2
3
3
3
2
5
10
MOVW A, #imm16
MOVW A,@RWi+disp8
MOVW A, @RLi+disp8
word (A) ← imm16
word (A) ← ((RWi) +disp8)
word (A) ← ((RLi) +disp8)
MOVW dir, A
MOVW addr16, A
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi+disp8,A
MOVW @RLi+disp8, A
MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16
MOVW @AL, AH
/MOVW@A, T
2
3
1
1
2
3
4
1
2
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
(c) word (dir) ← (A)
(c) word (addr16) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
2+ 3+ (a)
(c) word (eam) ← (A)
(c) word (io) ← (A)
2
2
3
2
3
5
10
3
word ((RWi) +disp8) ← (A)
word ((RLi) +disp8) ← (A)
(c)
(c)
(0) word (RWi) ← (ear)
(c) word (RWi) ← (eam)
2+ 4+ (a)
2
2+ 5+ (a)
3
4
4
4
0
word (ear) ← (RWi)
(c) word (eam) ← (RWi)
word (RWi) ← imm16
(c) word (io) ← imm16
word (ear) ← imm16
2
5
2
0
0
4+ 4+ (a)
(c) word (eam) ← imm16
2
3
4
0
(c) word ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
XCHW A, ear
2
2
0
4
2
0
word (A) ↔ (ear)
2× (c) word (A) ↔ (eam)
word (RWi) ↔ (ear)
2× (c) word (RWi) ↔ (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
XCHW A, eam
XCHW RWi, ear
XCHW RWi, eam
2+ 5+ (a)
2
2+ 9+ (a)
7
0
MOVL A, ear
MOVL A, eam
MOVL A, #imm32
2
4
2
0
0
0
long (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
2+ 5+ (a)
5
(d) long (A) ← (eam)
0
3
long (A) ← imm32
long (ear) ← (A)
MOVL ear, A
MOVL eam, A
2
4
2
0
0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
2+ 5+ (a)
(d) long (eam) ← (A)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
56
MB90540/545 Series
Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
ADD A,#imm8
#
~
B
Operation
2
2
2
2
5
3
0
0
1
0
2
0
0
1
0
0
0
0
1
0
2
0
0
1
0
0
0
byte (A) ← (A) +imm8
Z
Z
Z
Z
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
ADD
ADD
ADD
ADD
ADD
ADDC
A, dir
A, ear
A, eam
ear, A
eam, A
A
(b) byte (A) ← (A) +(dir)
byte (A) ← (A) +(ear)
(b) byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
2× (b) byte (eam) ← (eam) + (A)
0
2+ 4+ (a)
2
2+ 5+ (a)
1
2
3
0
2
3
0
0
byte (A) ← (AH) + (AL) + (C) Z
byte (A) ← (A) + (ear) + (C)
ADDC A, ear
ADDC A, eam
ADDDC A
Z
2+ 4+ (a)
(b) byte (A) ← (A) + (eam) + (C) Z
byte (A) ← (AH) + (AL) + (C) (decimal)
1
2
2
2
3
2
5
3
0
0
Z
Z
Z
Z
Z
–
–
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
byte (A) ← (A) –imm8
(b) byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
(b) byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
2× (b) byte (eam) ← (eam) – (A)
0
2+ 4+ (a)
2
2+ 5+ (a)
1
2
2+ 4+ (a)
1
3
0
2
3
0
0
byte (A) ← (AH) – (AL) – (C) Z
byte (A) ← (A) – (ear) – (C)
–
–
–
–
SUBC A, ear
SUBC A, eam
SUBDC A
Z
(b) byte (A) ← (A) – (eam) – (C) Z
byte (A) ← (AH) – (AL) – (C) (decimal)
3
0
Z
ADDW A
1
2
2
3
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
0
0
word (A) ← (AH) + (AL)
word (A) ← (A) +(ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
*
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCWA, ear
ADDCWA, eam
SUBW A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
2+ 4+ (a)
3
2
2+ 5+ (a)
2
2+ 4+ (a)
1
2
2+ 4+ (a)
3
2
(c) word (A) ← (A) +(eam)
0
0
2
3
word (A) ← (A) +imm16
word (ear) ← (ear) + (A)
2× (c) word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
3
0
(c) word (A) ← (A) + (eam) + (C) –
0
0
(c) word (A) ← (A) – (eam)
0
0
2
3
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
–
–
–
–
–
–
–
2
3
word (A) ← (A) –imm16
word (ear) ← (ear) – (A)
2+ 5+ (a)
2
2+ 4+ (a)
2× (c) word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
3
0
–
–
(c) word (A) ← (A) – (eam) – (C) –
ADDL A, ear
2
6
2
0
0
2
0
0
0
long (A) ← (A) + (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
ADDL A, eam
ADDL A, #imm32
SUBL A, ear
SUBL A, eam
SUBL A, #imm32
2+ 7+ (a)
5
2
2+ 7+ (a)
5
(d) long (A) ← (A) + (eam)
0
0
4
6
long (A) ← (A) +imm32
long (A) ← (A) – (ear)
(d) long (A) ← (A) – (eam)
long (A) ← (A) –imm32
4
0
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
57
MB90540/545 Series
Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
INC
INC
ear
eam
2
2
2
0
0
byte (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 5+ (a)
2× (b) byte (eam) ← (eam) +1
DEC
DEC
ear
eam
2
3
2
0
0
byte (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 5+ (a)
2× (b) byte (eam) ← (eam) –1
INCW ear
INCW eam
2
3
2
0
0
word (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 5+ (a)
2× (c) word (eam) ← (eam) +1
DECW ear
DECW eam
2
3
2
0
0
word (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 5+ (a)
2× (c) word (eam) ← (eam) –1
INCL ear
INCL eam
2
7
4
0
0
long (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 9+ (a)
2× (d) long (eam) ← (eam) +1
DECL ear
DECL eam
2
7
4
0
0
long (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 9+ (a)
2× (d) long (eam) ← (eam) –1
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
CMP
A
1
2
1
2
0
1
0
0
0
0
byte (AH) – (AL)
byte (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMP
CMP
CMP
A, ear
A, eam
A, #imm8
2+ 3+ (a)
2
(b) byte (A) ← (eam)
0
2
byte (A) ← imm8
CMPW A
1
2
1
2
0
1
0
0
0
0
word (AH) – (AL)
word (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW A, ear
CMPW A, eam
CMPW A, #imm16
2+ 3+ (a)
3
(c) word (A) ← (eam)
0
2
word (A) ← imm16
CMPL A, ear
CMPL A, eam
CMPL A, #imm32
2
6
2
0
0
0
word (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
2+ 7+ (a)
5
(d) word (A) ← (eam)
word (A) ← imm32
3
0
Note:Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
58
MB90540/545 Series
Table 12 Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
#
~
B
Operation
1
DIVU
A
1
0
0 word (AH) /byte (AL)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
Quotient → byte (AL) Remainder → byte (AH)
2
DIVU
DIVU
A, ear
2
1
0
1
0
0 word (A)/byte (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
Quotient → byte (A) Remainder → byte (ear)
6
3
A, eam 2+
word (A)/byte (eam)
Quotient → byte (A) Remainder → byte (eam)
*
*
4
DIVUW A, ear
2
long (A)/word (ear)
Quotient → word (A) Remainder → word (ear)
0
*
7
5
DIVUW A, eam 2+
long (A)/word (eam)
Quotient → word (A) Remainder → word (ear)
*
*
8
MULU
MULU A, ear
MULU A, eam 2+
A
1
2
0
1
0
byte (AH) *byte (AL) → word (A)
byte (A) *byte (ear) → word (A)
byte (A) *byte (eam) → word (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
(b)
*
9
*
10
*
MULUW A
MULUW A, ear
MULUW A, eam 2+
1
2
11
12
13
0
1
0
word (AH) *word (AL) → long (A)
word (A) *word (ear) → long (A)
word (A) *word (eam) → long (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
(c)
*
*
*
*1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally.
*2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally.
*3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.
*4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally.
*5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.
*6: (b) when the result is zero or when an overflow occurs, and 2 × (b) normally.
*7: (c) when the result is zero or when an overflow occurs, and 2 × (c) normally.
*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not zero.
*9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero.
*10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.
*11: 3 when word (AH) is zero, and 11 when word (AH) is not zero.
*12: 4 when word (ear) is zero, and 12 when word (ear) is not zero.
*13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
59
MB90540/545 Series
Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
DIV
A
2
*1
0
0
word (AH) /byte (AL)
Quotient → byte (AL)
Remainder → byte (AH)
word (A)/byte (ear)
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
DIV
A, ear
2
*2
1
0
1
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
Quotient → byte (A)
Remainder → byte (ear)
DIV
A, eam 2 + *3
*6 word (A)/byte (eam)
Quotient → byte (A)
Remainder → byte (eam)
long (A)/word (ear)
DIVW
DIVW
A, ear
2
*4
0
Quotient → word (A)
Remainder → word (ear)
A, eam 2+ *5
*7 long (A)/word (eam)
Quotient → word (A)
Remainder → word (eam)
MULU
MULU
MULU
MULUW A
MULUW A, ear
A
A, ear
A, eam 2 + *10
2
2
*8
*9
0
1
0
0
1
0
0
0
byte (AH) *byte (AL) → word (A)
byte (A) *byte (ear) → word (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(b) byte (A) *byte (eam) → word (A)
0
0
2
2
*11
*12
word (AH) *word (AL) → long (A)
word (A) *word (ear) → long (A)
MULUW A, eam 2 + *13
(c) word (A) *word (eam) → long (A)
*1: Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation.
*2: Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation.
*3: Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.
*4: Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation.
Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation.
*5: Positive dividend:Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for
normal operation.
Negative dividend:Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for
normal operation.
*6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation.
*7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10: Setto4+(a)whenbyte(eam)iszero, 13+(a)whentheresultispositive, and14+(a)whentheresultisnegative.
*11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is
negative.
Notes: • When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes
two values because of detection before and after an operation.
• When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.
• For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes”
and “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
60
MB90540/545 Series
Table 14 Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
AND A, #imm8
#
~
B
Operation
2
2
2
3
0
1
0
2
0
0
0
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
AND
AND
AND
AND
A, ear
A, eam
ear, A
2+ 4+ (a)
2
2+ 5+ (a)
(b) byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
3
0
eam, A
2× (b) byte (eam) ← (eam) and (A) –
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
2
2
2
3
0
1
0
2
0
0
0
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
2+ 4+ (a)
2
2+ 5+ (a)
(b) byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
2× (b) byte (eam) ← (eam) or (A)
3
0
eam, A
XOR A, #imm8
XOR A, ear
XOR A, eam
XOR ear, A
XOR eam, A
2
2
2
3
0
1
0
2
0
0
0
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
2+ 4+ (a)
2
2+ 5+ (a)
(b) byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
3
0
2× (b) byte (eam) ← (eam) xor (A) –
NOT
NOT
NOT
A
ear
eam
1
2
2
3
0
2
0
0
0
byte (A) ← not (A)
byte (ear) ← not (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
2+ 5+ (a)
2× (b) byte (eam) ← not (eam)
ANDW A
1
3
2
2
2
3
0
0
1
0
2
0
0
0
0
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ANDW A, #imm16
ANDW A, ear
ANDW A, eam
ANDW ear, A
ANDW eam, A
2+ 4+ (a)
2
2+ 5+ (a)
(c) word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
2× (c) word (eam) ← (eam) and (A)
3
0
ORW
A
1
3
2
2
2
3
0
0
1
0
2
0
0
0
0
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ORW A, #imm16
ORW A, ear
ORW A, eam
ORW ear, A
2+ 4+ (a)
2
2+ 5+ (a)
(c) word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
2× (c) word (eam) ← (eam) or (A)
3
0
ORW eam, A
XORW A
1
3
2
2
2
3
0
0
1
0
2
0
0
0
0
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
XORW A, #imm16
XORW A, ear
XORW A, eam
XORW ear, A
XORW eam, A
2+ 4+ (a)
2
2+ 5+ (a)
(c) word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
2× (c) word (eam) ← (eam) xor (A)
3
0
NOTW A
NOTW ear
NOTW eam
1
2
2
3
0
2
0
0
0
word (A) ← not (A)
word (ear) ← not (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
2+ 5+ (a)
2× (c) word (eam) ← not (eam)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
61
MB90540/545 Series
Table 15 Logical 2 Instructions (Long Word) [6 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
ANDL A, ear
ANDL A, eam
2
6
2
0
0
long (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 7+ (a)
(d) long (A) ← (A) and (eam)
ORL
ORL
A, ear
A, eam
2
6
2
0
0
long (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 7+ (a)
(d) long (A) ← (A) or (eam)
XORL A, ea
XORL A, eam
2
6
2
0
0
long (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 7+ (a)
(d) long (A) ← (A) xor (eam)
Table 16 Sign Inversion Instructions (Byte/Word) [6 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
NEG
A
1
2
0
0
byte (A) ← 0 – (A)
X
–
–
–
–
*
*
*
*
–
NEG ear
NEG eam
2
3
2
0
0
byte (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
2+ 5+ (a)
2× (b) byte (eam) ← 0 – (eam)
NEGW A
1
2
0
0
word (A) ← 0 – (A)
–
–
–
–
–
*
*
*
*
–
NEGW ear
NEGW eam
2
3
2
0
0
word (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
2+ 5+ (a)
2× (c) word (eam) ← 0 – (eam)
Table 17 Normalize Instruction (Long Word) [1 Instruction]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
RG
B
Operation
1
NRML A, R0
2
1
0
long (A) ← Shift until first digit is “1” –
byte (R0) ← Current shift count
–
–
–
–
–
*
–
–
–
*
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
62
MB90540/545 Series
Table 18 Shift Instructions (Byte/Word/Long Word) [18 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
RORC A
#
~
B
Operation
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
2
2
2
2
0
0
0
0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
ROLC A
RORC ear
RORC eam
ROLC ear
ROLC eam
byte (ear) ← Right rotation with carry
byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry
2
2+
2
3
2
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
–
*
–
*
5+ (a)
0 2× (b)
2
0 2× (b)
0
3
2+
5+ (a)
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
ASR A, R0
LSR A, R0
LSL A, R0
1
2
2
2
1
1
1
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
1
*
1
*
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
ASRW A
LSRW A/SHRW A
LSLW A/SHLW A
1
1
1
2
2
2
0
0
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
R
*
*
*
*
–
–
–
*
*
*
–
–
–
1
word (A) ← Arithmetic right barrel shift (A,
R0)
ASRW A, R0
LSRW A, R0
LSLW A, R0
2
2
2
1
1
1
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
1
*
1
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
*
2
ASRL A, R0
LSRL A, R0
LSLL A, R0
long (A) ← Arithmetic right shift (A, R0)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
2
2
2
1
1
1
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
2
*
2
*
*1: 6 when R0 is 0, 5 + (R0) in all other cases.
*2: 6 when R0 is 0, 6 + (R0) in all other cases.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
63
MB90540/545 Series
Table 19 Branch 1 Instructions [31 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
1
BZ/BEQ
BNZ/BNE rel
BC/BLO
BNC/BHS rel
rel
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1
Branch when ((V) xor (N)) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
rel
1
1
BN
BP
BV
BNV
BT
BNT
BLT
BGE
BLE
BGT
BLS
BHI
BRA
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
1
1
1
1
1
1
1
1
1
1
1
1
*
JMP
JMP
JMP
JMP
@A
1
3
2
2
3
3
0
0
1
0
2
0
0
0
0
0
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
addr16
@ear
@eam
2+ 4+ (a)
2
2+ 6+ (a)
4
(c) word (PC) ← (eam)
0
(d)
0
JMPP @ear *3
JMPP @eam *3
JMPP addr24
word (PC) ← (ear), (PCB) ← (ear +2)
5
word (PC) ← (eam), (PCB) ← (eam +2)
4
word (PC) ← ad24 0 to 15,
(PCB) ← ad24 16 to 23
CALL @ear *4
CALL @eam *4
CALL addr16 *5
CALLV #vct4 *5
CALLP @ear *6
2
6
1
0
0
0
2
(c) word (PC) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2+ 7+ (a)
2× (c) word (PC) ← (eam)
(c) word (PC) ← addr16
2× (c) Vector call instruction
2× (c) word (PC) ← (ear) 0 to 15,
3
1
2
6
7
10
(PCB) ← (ear) 16 to 23
2
CALLP @eam *6
CALLP addr24 *7
2+ 11+ (a)
10
0
0
word (PC) ← (eam) 0 to 15,
(PCB) ← (eam) 16 to 23
word (PC) ← addr0 to 15,
(PCB) ← addr16 to 23
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
4
2× (c)
*1: 4 when branching, 3 when not branching.
*2: (b) + 3 × (c)
*3: Read (word) branch address.
*4: W: Save (word) to stack; R: read (word) branch address.
*5: Save (word) to stack.
*6: W: Save (long word) to W stack; R: read (long word) R branch address.
*7: Save (long word) to stack.
Note:Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
64
MB90540/545 Series
Table 20 Branch 2 Instructions [19 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
1
Branch when byte (A) ≠ imm8
Branch when word (A) ≠ imm16
CBNE A, #imm8, rel
CWBNE A, #imm16, rel
3
4
0
0
0
0
–
–
– – – – *
– – – – *
*
*
*
*
*
*
–
–
*
*
1
2
Branch when byte (ear) ≠ imm8
Branch when byte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
Branch when word (eam) ≠ imm16
CBNE ear, #imm8, rel
4
4+
5
*
*
*
*
1
0
1
0
0
(b)
0
–
–
–
–
– – – – *
– – – – *
– – – – *
– – – – *
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CBNE
eam, #imm8, rel*10
3
4
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel*10
3
5+
(c)
5
DBNZ ear, rel
DBNZ eam, rel
3
2
2
0
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
–
–
– – – – *
– – – – *
*
*
* –
* –
–
*
*
6
*
3+
2× (b) Branch when byte (eam) =
(eam) – 1, and (eam) ≠ 0
5
DWBNZ ear, rel
DWBNZ eam, rel
3
*
2
2
0
Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
–
–
– – – – *
– – – – *
*
*
* –
* –
–
*
6
3+
2× (c) Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
*
INT
INT
INTP
INT9
RETI
#vct8
addr16
addr24
8× (c)
6× (c)
6× (c)
8× (c)
2
3
4
1
1
0
0
0
0
0
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
–
–
–
–
–
– R S – – – – –
– R S – – – – –
– R S – – – – –
– R S – – – – –
–
–
–
–
–
20
16
17
20
15
7
*
–
*
*
*
*
*
*
*
LINK
#local8
(c)
(c)
2
0
At constant entry, save old
frame pointer to stack, set
new frame pointer, and
allocate local pointer area
At constant entry, retrieve old
frame pointer from stack.
–
– – – – – – – –
–
6
UNLINK
1
0
–
– – – – – – – –
–
5
RET *8
(c)
(d)
1
1
0
0
Return from subroutine
Return from subroutine
–
–
– – – – – – – –
– – – – – – – –
–
–
4
6
RETP *9
*1: 5 when branching, 4 when not branching
*2: 13 when branching, 12 when not branching
*3: 7 + (a) when branching, 6 + (a) when not branching
*4: 8 when branching, 7 when not branching
*5: 7 when branching, 6 when not branching
*6: 8 + (a) when branching, 7 + (a) when not branching
*7: Set to 3 × (b) + 2 × (c) when an interrupt request occurs, and 6 × (c) for return.
*8: Retrieve (word) from stack
*9: Retrieve (long word) from stack
*10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
65
MB90540/545 Series
Table 21 Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
#
~
B
Operation
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
1
1
1
2
4
4
4
0
0
0
(c)
(c)
(c)
–
–
–
–
–
–
–
–
– – – – – – –
– – – – – – –
– – – – – – –
– – – – – – –
–
–
–
–
3
5
4
*
*
*
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)), (SP) ← (SP) +2n
POPW A
1
1
1
2
–
–
–
–
*
– – – – – – –
– – – – – – –
–
–
–
–
3
3
4
0
0
0
(c)
(c)
(c)
POPW AH
POPW PS
POPW rlst
–
–
–
*
*
*
*
*
*
*
2
5
4
– – – – – – –
*
*
*
JCTX @A
1
Context switch instruction
–
–
*
*
*
*
*
*
*
–
14
0
6× (c)
AND CCR, #imm8
OR CCR, #imm8
2
2
byte (CCR) ← (CCR) and imm8 –
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
3
3
0
0
0
0
byte (CCR) ← (CCR) or imm8
–
MOV RP, #imm8
MOV ILM, #imm8
2
2
byte (RP) ←imm8
byte (ILM) ←imm8
–
–
–
–
– – – – – – –
– – – – – – –
–
–
2
2
0
0
0
0
MOVEA RWi, ear
MOVEA RWi, eam 2+
MOVEA A, ear
MOVEA A, eam
2
word (RWi) ←ear
word (RWi) ←eam
word(A) ←ear
–
–
–
–
–
–
*
– – – – – – –
– – – – – – –
– – – – – – –
– – – – – – –
–
–
–
–
3
1
1
0
0
0
0
0
0
2+ (a)
1
1+ (a)
2
2+
word (A) ←eam
*
ADDSP #imm8
ADDSP #imm16
2
3
word (SP) ← (SP) +ext (imm8)
word (SP) ← (SP) +imm16
–
–
–
–
– – – – – – –
– – – – – – –
–
–
3
3
0
0
0
0
1
MOV
MOV
A, brgl
brg2, A
2
2
byte (A) ← (brgl)
byte (brg2) ← (A)
Z
–
*
–
– – –
– – –
*
*
*
*
– –
– –
–
–
0
0
0
0
*
1
NOP
ADB
DTB
PCB
SPB
NCC
CMR
1
1
1
1
1
1
1
No operation
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – – – – –
– – – – – – –
– – – – – – –
– – – – – – –
– – – – – – –
– – – – – – –
– – – – – – –
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR : 2 states
*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count × (c), or push count × (c)
*5: Pop count or push count.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
66
MB90540/545 Series
Table 22 Bit Manipulation Instructions [21 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
5
5
4
0
0
0
(b) byte (A) ← (dir:bp) b
(b) byte (A) ← (addr16:bp) b
(b) byte (A) ← (io:bp) b
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
7
7
6
0
0
0
2× (b) bit (dir:bp) b ← (A)
2× (b) bit (addr16:bp) b ← (A)
2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
SETB dir:bp
SETB addr16:bp
SETB io:bp
3
4
3
7
7
7
0
0
0
2× (b) bit (dir:bp) b ← 1
2× (b) bit (addr16:bp) b ← 1
2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
3
4
3
7
7
7
0
0
0
2× (b) bit (dir:bp) b ← 0
2× (b) bit (addr16:bp) b ← 0
2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
1
BBC dir:bp, rel
BBC addr16:bp, rel
BBC io:bp, rel
4
5
4
0
0
0
(b) Branch when (dir:bp) b = 0
(b) Branch when (addr16:bp) b = 0
(b) Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
1
2
1
BBS dir:bp, rel
BBS addr16:bp, rel
BBS io:bp, rel
4
5
4
0
0
0
(b) Branch when (dir:bp) b = 1
(b) Branch when (addr16:bp) b = 1
(b) Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
1
2
3
Branch when (addr16:bp) b = 1, bit = 1
SBBS addr16:bp, rel
WBTS io:bp
5
3
3
0
0
0
2× (b)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
*
*
5
4
Wait until (io:bp) b = 1
Wait until (io:bp) b = 0
–
–
–
–
*
*
*
4
5
WBTC io:bp
*
*1: 8 when branching, 7 when not branching
*2: 7 when branching, 6 when not branching
*3: 10 when condition is satisfied, 9 when not satisfied
*4: Undefined count
*5: Until condition is satisfied
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 23 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
SWAP
SWAPW
EXT
EXTW
ZEXT
ZEXTW
#
~
B
Operation
1
1
1
1
1
1
3
2
1
2
1
1
0
0
0
0
0
0
0 byte (A) 0 to 7 ↔ (A) 8 to 15
0 word (AH) ↔ (AL)
0 byte sign extension
0 word sign extension
0 byte zero extension
0 word zero extension
–
–
X
–
Z
–
–
*
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
67
MB90540/545 Series
Table 24 String Instructions [10 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
2
5
3
Byte transfer @AH+ ← @AL+, counter = RW0
Byte transfer @AH– ← @AL–, counter = RW0
MOVS/MOVSI
MOVSD
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
2
5
3
*
*
1
5
4
Byte retrieval (@AH+) – AL, counter = RW0
Byte retrieval (@AH–) – AL, counter = RW0
SCEQ/SCEQI
SCEQD
2
2
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
*
*
*
*
1
5
4
*
*
5
3
Byte filling @AH+ ← AL, counter = RW0
FISL/FILSI
2
–
–
–
–
–
*
*
–
–
–
6m +6
*
*
2
8
6
Word transfer @AH+ ← @AL+, counter = RW0
Word transfer @AH– ← @AL–, counter = RW0
MOVSW/MOVSWI 2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
2
8
6
MOVSWD
2
*
*
1
8
7
Word retrieval (@AH+) – AL, counter = RW0
Word retrieval (@AH–) – AL, counter = RW0
SCWEQ/SCWEQI
SCWEQD
2
2
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
*
*
*
*
1
8
7
*
*
8
6
Word filling @AH+ ← AL, counter = RW0
FILSW/FILSWI
2
–
–
–
–
–
*
*
–
–
–
6m +6
*
*
m: RW0 value (counter value)
n: Loop count
*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs
*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case
*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) sepa-
rately for each.
*4: (b) × n
*5: 2 × (RW0)
*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c)
separately for each.
*7: (c) × n
*8: 2 × (RW0)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
MB90540/545 Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB90543PF
MB90F543PF
MB90548PF
MB90F548PF
100-pin Plastic QFP
(FPT-100P-M06)
MB90543PFF
MB90F543PFF
MB90548PFF
MB90F548PFF
100-pin Plastic LQFP
(FPT-100P-M05)
256-pin Ceramic PGA
(PGA-256C-A01)
MB90V540CR
For evaluation
69
MB90540/545 Series
■ PACKAGE DIMENSIONS
100-pin Plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
3.35(.132)MAX
(Mounting height)
20.00±0.20(.787±.008)
0.05(.002)MIN
(STAND OFF)
80
51
81
50
12.35(.486)
14.00±0.20 17.90±0.40
(.551±.008) (.705±.016)
16.30±0.40
(.642±.016)
REF
INDEX
31
100
"A"
1
30
LEAD No.
0.65(.0256)TYP
0.30±0.10
(.012±.004)
0.15±0.05(.006±.002)
Details of "B" part
M
0.13(.005)
Details of "A" part
0.25(.010)
0.30(.012)
"B"
0.10(.004)
0
10°
0.18(.007)MAX
0.53(.021)MAX
18.85(.742)REF
0.80±0.20
(.031±.008)
22.30±0.40(.878±.016)
C
1994 FUJITSU LIMITED F100008-3C-2
Dimensions in mm (inches)
70
MB90540/545 Series
100-pin Plastic LQFP
(FPT-100P-M05)
1.50 –+00..1200
16.00±0.20(.630±.008)SQ
(Mouting height)
.059 –+..000048
75
51
14.00±0.10(.551±.004)SQ
76
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
0.15(.006)
100
26
0.15(.006)MAX
0.40(.016)MAX
"B"
1
25
LEAD No.
"A"
0.50(.0197)TYP
0.18 –+00..0038
0.127 +–00..0025
.005 +–..000012
M
Details of "B" part
0.08(.003)
.007 –+..000013
0.10±0.10
(.004±.004)
(STAND OFF)
0.50±0.20(.020±.008)
0.10(.004)
0~10°
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches)
71
MB90540/545 Series
250-pin Ceramic PGA
(PGA-256C-A01)
C0.51 (.020) TYP
(3 PLCS)
0.20 ± 0.05
(.0079 ± .002)
22.86 (.900)
REF
1.27 (.050) TYP
INDEX AREA
+ 0.30
– 0.10
+ .012
)
– .004
1.50
(.059
C1.02 (.040) TYP
EXTRA INDEX PIN
25.10 ± 0.30 SQ
(.988 ± .012)
6.35 (.250) MAX
C
1994 FUJITSU LIMITED R256001SC-5-3
Dimensions in mm (inches)
72
MB90540/545 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
measurement equipment, personal or household devices, etc.).
CAUTION:
Fax: (408) 922-9179
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
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Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
http://www.fmap.com.sg/
F9909
FUJITSU LIMITED Printed in Japan
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