MB90F867ESPMC [SPANSION]
Microcontroller, 16-Bit, FLASH, 24MHz, CMOS, PQFP100, 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-100;型号: | MB90F867ESPMC |
厂家: | SPANSION |
描述: | Microcontroller, 16-Bit, FLASH, 24MHz, CMOS, PQFP100, 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-100 时钟 微控制器 外围集成电路 |
文件: | 总73页 (文件大小:2307K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Spansion® Analog and Microcontroller
Products
The following document contains information on Spansion analog and microcontroller products. Although the
document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion
will continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal document improvements and are noted in the document revision
summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a
revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “MB”. To order these products, please use
only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory, analog, and
microcontroller products and solutions.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13748-5E
16-bit Microcontroller
CMOS
F2MC-16LX MB90860E Series
MB90867E(S)/F867E(S)/V340E-101/V340E-102
■ DESCRIPTION
The MB90860E series with integrated Flash ROM is a general-purpose Fujitsu 16-bit microcontroller designed
for automotive and other industrial applications. By utilizing new 0.35 µm CMOS technology, Fujitsu Microelec-
tronics now offers a 128KBytes of on-chip Flash ROM program memory.
Furthermore, the 3 V power supply of the internal MCU core is supplied by an internal regulator circuit, making
this a vastly superior product in terms of reliability and power consumption.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• CPU
• Optimal instruction suitable for controller applications
- Wide range of data types (bit, byte, word, and long word)
- Wide range of addressing modes (23 types)
- Enhanced multiplication and division instructions, and enhanced RETI instruction
- Enhanced high-precision calculations using a 32-bit accumulator
• Instruction set level support for high level languages (C language) and multitask
- Equipped with a system stack pointer
- A variety of enhanced pointer indirect instructions
- Barrel shift instructions
• Increased processing speed
- 4-byte instruction queue
(Continued)
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in
system development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2006-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.9
MB90860E Series
(Continued)
• Serial interface
• LIN-UART : 4 channels
- Equipped with full-duplex double buffer
- Clock-asynchronous and clock-synchronous serial transmission are available
• I2C interface : 2 channels
- Up to 400 kbps transfer rate
• Interrupt controller
• Powerful interrupt function with 8 levels and 34 sources
• Supports up to 16 external interrupts
• CPU-independent automatic data transfer function
- Expanded intelligent I/O service function (EI2OS) : up to 16 channels
• I/O ports
• General-purpose input/output ports (CMOS output)
- 80 ports (devices without an S suffix in the part number - devices that support a sub clock)
- 82 ports (devices with an S suffix in the part number - devices that do not support a sub clock)
• 8/10-bit A/D converter : 24 channels
• Resolution is selectable between 8-bit and 10-bit.
• Can be activated by an external trigger.
• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)
• Address match detection (program patch) function
• Address match detection for 6 address pointers
• Timers
• Time-base timer, watch timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 16 channels or 16-bit × 8 channels
• 16-bit reload timer : 4 channels
• 16-bit I/O timer
- 16-bit free run timer : 2 channel (FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16-bit input capture (ICU) : 8 channels
- 16-bit output compare (OCU) : 8 channels
• Low power consumption (standby) modes
• Sleep mode (a mode where the CPU operating clock stops)
• Time-base timer mode (a mode where only the oscillator clock, sub clock, time-base timer, and watch timer
operate)
• Watch mode (a mode where only the sub clock and watch timer operate)
• Stop mode (a mode where the oscillator clock and sub clock stop)
• CPU blocking operation mode
• Clock modulator
• Technology
• 0.35 µm CMOS technology
2
DS07-13748-5E
MB90860E Series
■ PRODUCT LINEUP
Part Number
MB90867E(S)
MB90F867E(S)
MB90V340E-101/102
Parameter
CPU
F2MC-16LX CPU
Type
MASK ROM product
Flash memory product
Evaluation product
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)
System clock
MASK ROM
128 Kbytes
Flash memory
128 Kbytes
ROM
RAM
External
30 Kbytes
Yes
6 Kbytes
6 Kbytes
Dedicated power
supply for emulator*
⎯
0.35 µm CMOS with on-chip
0.35 µm CMOS with on-chip
voltage regulator for internal
power supply
voltage regulator for internal
0.35 µm CMOS with on-
Technology
power supply + Flash memory chip voltage regulator for
with on-chip charge pump for internal power supply
programming voltage
3.5 V to 5.5 V : during normal operation (not using A/D converter)
4.0 V to 5.5 V : when using A/D converter/Flash programming
4.5 V to 5.5 V : when using external bus
Operating
voltage range
5 V 10%
Temperature range
Package
−40 °C to +105 °C
QFP-100, LQFP-100
4 channels
⎯
PGA-299
5 channels
Wide range of baud rate settings using a dedicated baud rate generator (reload timer)
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality can operate as either master or slave LIN device
LIN-UART
I2C (400 kbps)
2 channels
24 channels
8/10-bit
A/D converter
10-bit or 8-bit resolution
Conversion time : Min 3 µs include sample time (per one channel)
16-bit reload timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
Supports External Event Count function
Generates an interrupt on overflow
Supports Timer Clear when a match with Output Compare (ch.0, ch.4)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock freq.)
Free run Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3
Free run Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit
free run timer
(2 channels)
16-bit output
compare
(8 channels)
Generates an interrupt when the 16-bit free run timer matches the output compare register.
Multiple compare registers can be used to generate an output signal.
16-bit input capture Captures the value of the 16-bit free run timer and generates an interrupt when triggered
(8 channels)
by a pin input (rising edge, falling edge, or both rising and falling edges).
(Continued)
DS07-13748-5E
3
MB90860E Series
(Continued)
Part Number
MB90867E(S)
MB90F867E(S)
MB90V340E-101/102
Parameter
8 channels (16-bit) or 16 channels (8-bit)
8-bit reload counter × 16
8-bit reload registers for lower part × 16
8-bit reload registers for upper part × 16
8/16-bit
programmable pulse
generator
Supports 8-bit and 16-bit operating modes
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
an 8-bit prescaler plus an 8-bit reload counter
(8 channels)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
CAN interface
⎯
3 channels
External interrupt
(16 channels)
Can be triggered by rising edge, falling edge, or H/L level inputs, external interrupts can
by used by expanded intelligent I/O services (EI2OS) and DMA
D/A converter
⎯
2 channels
Sub clock (maximum
100 kHz)
Only for MB90V340E-
102
Devices without 'S' suffix in the part number
Virtually all external pins can be used as general-purpose I/O ports
All push-pull outputs
Bitwise configurable as input/output or peripheral signal
Configurable in blocks of 8 pins as CMOS schmitt trigger or automotive inputs
Configurable as TTL input levels for an external bus (only applies to the 32 external bus
pins)
I/O ports
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
Equipped with a flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Flash memory
Data retention time : 20 years
Boot block configuration
⎯
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
* : Configured by the jumper switch (TOOL VCC) when the emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual for details.
4
DS07-13748-5E
MB90860E Series
■ PIN ASSIGNMENTS
• MB90V340E-101/102
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
P14/AD12/SCK3
Vcc
Vss
QFP - 100
X1
X0
P15/AD13/SIN4
P16/AD14/SOT4
P17/AD15/SCK4
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
AVRL
AVRH
AVcc
P57/AN15/DA01
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(FPT-100P-M06)
* : X0A, X1A : MB90V340E-102
P40, P41 : MB90V340E-101
This pin assignment is for using MB90V340E-101/102 via probecable as MB90860E.
(Continued)
DS07-13748-5E
5
MB90860E Series
(Continued)
(TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
MD1
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MD2
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
LQFP - 100
Vss
X1
X0
P15/AD13/SIN4
P16/AD14/SOT4
P17/AD15/SCK4
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
AVRL
AVRH
AVcc
P57/AN15/DA01
P56/AN14/DA00
P55/AN13
P25/A21/IN1
P54/AN12/TOT3
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
(FPT-100P-M20)
* : X0A, X1A : MB90V340E-102
P40, P41 : MB90V340E-101
This pin assignment is for using MB90V340E-101/102 via probecable as MB90860E.
6
DS07-13748-5E
MB90860E Series
• MB90867E(S)/MB90F867E(S)
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
QFP - 100
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
AVss
AVRL
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
AVRH
AVcc
P57/AN15
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(FPT-100P-M06)
* : X0A, X1A : MB90867E, MB90F867E
P40, P41 : MB90867ES/MB90F867ES
(Continued)
DS07-13748-5E
7
MB90860E Series
(Continued)
(TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MD1
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
MD2
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
LQFP - 100
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
AVRL
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
P25/A21/IN1
AVRH
AVcc
P57/AN15
P56/AN14
P55/AN13
P54/AN12/TOT3
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
(FPT-100P-M20)
* : X0A, X1A : MB90867E, MB90F867E
P40, P41 : MB90867ES, MB90F867ES
8
DS07-13748-5E
MB90860E Series
■ PIN DESCRIPTION
Pin No.
I/O
Pin name Circuit
type*3
Function
QFP100*1 LQFP100*2
General-purpose I/O pins. It is possible to select whether or not a
pull-up resistance is used by configuring a register. In external
bus mode, each pin is enabled as a general-purpose I/O port
when the corresponding bit in the external address output control
register (HACR) is 1.
P24 to P27
1 to 4
99 to 2
G
External address bus output pins. When the corresponding bits in
the external address output control register (HACR) are 0, the
pins are enabled as high address output pins (A20 to A23).
A20 to A23
IN0 to IN3
P30
Trigger input pins for input captures 0 to 3.
General-purpose I/O pin. It is possible to select whether or not a
pull-up resistance is used by configuring a register. This function
is enabled in single-chip mode.
5
6
3
4
G
G
Address latch enable output pin. This function is enabled when
the external bus is enabled.
ALE
IN4
Trigger input pin for input capture 4.
General-purpose I/O pin. It is possible to select whether or not a
pull-up resistance is used by configuring a register. This function
is enabled in single-chip mode.
P31
External read strobe output pin. This function is enabled when the
external bus is enabled.
RD
IN5
Trigger input pin for input capture 5.
General-purpose I/O pin. It is possible to select whether or not a
pull-up resistance is used by configuring a register. This function
is enabled either in single-chip mode or when the WR/WRL pin
output disabled.
P32
Write strobe output pin for the external data bus. This function is
enabled when both the external bus and the WR/WRL pin output
are enabled. WRL is used as a write strobe output for the lower 8
bits of the data bus in 16-bit access while WR is used as the write
strobe for the 8 bits of the data bus in 8-bit access.
7
5
G
WR / WRL
INT10R
P33
External interrupt request input pin (sub) .
General-purpose I/O pin. It is possible to select whether or not a
pull-up resistance is used by configuring a register. This function
is enabled either in single-chip mode or when the WRH pin output
disabled.
8
6
G
Write strobe output pin for the upper 8 bits of the external data
bus. This function is enabled when the external bus is enabled,
and the external bus is in 16-bit mode, and the WRH output pin is
enabled.
WRH
(Continued)
DS07-13748-5E
9
MB90860E Series
Pin No.
I/O
Circuit
Pin name
Function
QFP100*1 LQFP100*2
type*3
General-purpose I/O pin. It is possible to select whether or not
a pull-up resistance is used by configuring a register. This
function is enabled either in single-chip mode or when the hold
function is disabled.
P34
9
7
8
9
G
G
G
G
Hold request input pin. This function is enabled when both the
external bus and the hold function are enabled.
HRQ
OUT4
Waveform output pin for output compare 4.
General-purpose I/O pin. It is possible to select whether or not
a pull-up resistance is used by configuring a register. This
function is enabled either in single-chip mode or when the hold
function is disabled.
P35
10
11
Hold acknowledge output pin. This function is enabled when
both the external bus and the hold function are enabled.
HAK
OUT5
Waveform output pin for output compare 5.
General-purpose I/O pin. It is possible to select whether or not
a pull-up resistance is used by configuring a register. This
function is enabled either in single-chip mode or when the
external ready function is disabled.
P36
External ready input pin. This function is enabled when both the
external bus and the external ready function are enabled.
RDY
OUT6
Waveform output pin for output compare 6.
General-purpose I/O pin. It is possible to select whether or not
a pull-up resistance is used by configuring a register. This
function is enabled either in single-chip mode or when clock
output is disabled.
P37
12
10
Clock output pin. This function is enabled when both the
external bus and clock output are enabled.
CLK
OUT7
Waveform output pin for output compare 7.
General-purpose I/O pins (devices with an “S” suffix in the part
number).
P40, P41
F
B
13, 14
11, 12
Input pins for sub-clock (devices without an "S" suffix in the part
number).
X0A , X1A
15
16
13
14
VCC
VSS
⎯
⎯
Power (3.5 V to 5.5 V) input pin.
GND pin.
This is the power supply stabilization capacitor pin. It should be
connected to a ceramic capacitor with a capacitance of 0.1 µF
or higher.
17
18
15
16
C
K
P42
IN6
General-purpose I/O pin.
F
Trigger input pin for input capture 6.
External interrupt request input pin (sub) .
(Continued)
INT9R
10
DS07-13748-5E
MB90860E Series
Pin No.
I/O
Circuit
Pin name
Function
QFP100*1 LQFP100*2
type*3
P43
IN7
General-purpose I/O pin.
19
20
17
18
F
Trigger input pin for input capture 7.
General-purpose I/O pin.
Serial data I/O pin for I2C 0.
P44
SDA0
FRCK0
P45
H
Input pin for 16-bit free run timer 0.
General-purpose I/O pin.
21
19
SCL0
FRCK1
P46
H
Serial clock I/O pin for I2C 0.
Input pin for 16-bit free run timer 1.
General-purpose I/O pin.
22
23
20
21
H
H
SDA1
P47
Serial data I/O pin for I2C 1.
General-purpose I/O pin.
Serial clock I/O pin for I2C 1.
SCL1
P50
General-purpose I/O pin.
24
25
26
27
22
23
24
25
AN8
O
I
Analog input pin for the A/D converter.
Serial data input pin for UART2.
General-purpose I/O pin.
SIN2
P51
AN9
Analog input pin for the A/D converter.
Serial data output pin for UART2.
General-purpose I/O pin.
SOT2
P52
AN10
SCK2
P53
I
Analog input pin for the A/D converter.
Clock I/O pin for UART2.
General-purpose I/O pin.
AN11
TIN3
I
Analog input pin for the A/D converter.
Event input pin for reload timer 3.
General-purpose I/O pin.
P54
28
29
26
27
AN12
TOT3
P55
I
I
Analog input pin for the A/D converter.
Output pin for reload timer 3.
General-purpose I/O pin.
AN13
P56, P57
AN14, AN15
AVCC
Analog input pin for the A/D converter.
General-purpose I/O pins.
30, 31
32
28, 29
30
J
Analog input pin for the A/D converter.
Analog power input pin for the A/D converter.
K
(Continued)
DS07-13748-5E
11
MB90860E Series
Pin No.
I/O
Pin name
Circuit
Function
QFP100*1 LQFP100*2
type*3
Reference voltage input pin for the A/D converter. This
power supply must be turned on or off while a voltage
higher than or equal to AVRH is applied to AVCC.
33
31
AVRH
L
34
35
32
33
AVRL
AVSS
K
K
Lower reference voltage input pin for the A/D converter.
Analog GND pin for the A/D converter.
General-purpose I/O pins.
P60 to P67
AN0 to AN7
Analog input pins for the A/D converter.
36 to 43
34 to 41
I
PPG0, 2, 4, 6, 8,
A, C, E
PPG output pins.
44
42
VSS
P70 to P75
AN16 to AN21
INT0 to INT5
MD2
⎯
GND pin.
General-purpose I/O pins.
45 to 50
43 to 48
I
Analog input pins for the A/D converter.
External interrupt request input pins.
Input pin for specifying the operating mode.
Input pins for specifying the operating mode.
Reset input.
51
52, 53
54
49
50, 51
52
D
C
E
MD1, MD0
RST
P76, P77
AN22, AN23
INT6, INT7
P80
General-purpose I/O pins.
55, 56
53, 54
I
Analog input pins for the A/D converter.
External interrupt request input pins.
General-purpose I/O pin.
TIN0
Event input pin for reload timer 0.
Trigger input pin for the A/D converter.
External interrupt request input pin (sub) .
General-purpose I/O pin.
57
55
F
ADTG
INT12R
P81
TOT0
Output pin for reload timer 0.
58
56
F
CKOT
Output pin for the clock monitor.
External interrupt request input pin (sub) .
General-purpose I/O pin.
INT13R
P82
SIN0
Serial data input pin for UART0.
Event input pin for reload timer 2.
External interrupt request input pin (sub) .
General-purpose I/O pin.
59
60
57
58
M
F
TIN2
INT14R
P83
SOT0
Serial data output pin for UART0.
TOT2
Output pin for reload timer 2.
(Continued)
12
DS07-13748-5E
MB90860E Series
Pin No.
I/O
Pin name
Circuit
Function
QFP100*1 LQFP100*2
type*3
P84
SCK0
General-purpose I/O pin.
61
59
F
Clock I/O pin for UART0.
External interrupt request input pin (sub) .
General-purpose I/O pin.
Serial data input pin for UART1.
General-purpose I/O pin.
Serial data output pin for UART1.
General-purpose I/O pin.
Clock I/O pin for UART1.
Power (3.5 V to 5.5 V) input pins.
GND pins.
INT15R
P85
62
63
64
60
61
62
M
F
SIN1
P86
SOT1
P87
F
SCK1
65
66
63
64
VCC
⎯
⎯
VSS
P90 to P93
PPG1, 3, 5, 7
P94 to P97
General-purpose I/O pins.
PPG output pins.
67 to 70
65 to 68
F
General-purpose I/O pins.
71 to 74
69 to 72
F
Waveform output pins for output compare 0 to 3. This
function is enabled when waveform output is enabled.
OUT0 to OUT3
PA0
INT8R
PA1
General-purpose I/O pin.
75
76
73
74
F
F
External interrupt request input pin (sub) .
General-purpose I/O pin.
General-purpose I/O pins. It is possible to select whether
or not a pull-up resistance is used by configuring a regis-
ter. This function is enabled in single-chip mode.
P00 to P07
77 to 84
75 to 82
G
G
I/O pins for the lower 8 bits of the external address/data
bus. This function is enabled when the external bus is en-
abled.
AD00 to AD07
INT8 to INT15
P10
External interrupt request input pins.
General-purpose I/O pin. It is possible to select whether
or not a pull-up resistance is used by configuring a regis-
ter. This function is enabled in single-chip mode.
85
83
I/O pin for the external address/data bus.
This function is enabled when the external bus is
enabled.
AD08
TIN1
Event input pin for reload timer 1.
(Continued)
DS07-13748-5E
13
MB90860E Series
Pin No.
I/O
Circuit
Pin name
Function
QFP100*1
LQFP100*2
type*3
General-purpose I/O pin. It is possible to select whether or not
a pull-up resistance is used by configuring a register. This
function is enabled in single-chip mode.
P11
86
84
G
N
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
AD09
TOT1
Output pin for reload timer 1.
General-purpose I/O pin. It is possible to select whether or not
a pull-up resistance is used by configuring a register. This
function is enabled in single-chip mode.
P12
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
87
85
AD10
SIN3
Serial data input pin for UART3.
INT11R
External interrupt request input pin (sub) .
General-purpose I/O pin. It is possible to select whether or not
a pull-up resistance is used by configuring a register. This
function is enabled in single-chip mode.
P13
88
89
86
87
G
G
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
AD11
SOT3
Serial data output pin for UART3.
General-purpose I/O pin. It is possible to select whether or not
a pull-up resistance is used by configuring a register. This
function is enabled in single-chip mode.
P14
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
AD12
SCK3
VCC
VSS
X1
Clock I/O pin for UART3.
Power (3.5 V to 5.5 V) input pin.
GND pin.
90
91
92
93
88
89
90
91
⎯
⎯
Main clock output pin.
Main clock input pin.
A
X0
General-purpose I/O pin. It is possible to select whether or not
a pull-up resistance is used by configuring a register. This
function is enabled in single-chip mode.
P15
AD13
P16
94
95
92
93
G
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
General-purpose I/O pin. It is possible to select whether or not
a pull-up resistance is used by configuring a register. This
function is enabled in single-chip mode.
G
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
AD14
(Continued)
14
DS07-13748-5E
MB90860E Series
(Continued)
Pin No.
I/O
Circuit
Pin name
Function
QFP100*1 LQFP100*2
type*3
General-purpose I/O pin. It is possible to select wheth-
er or not a pull-up resistance is used by configuring a
register. This function is enabled in single-chip mode.
P17
96
94
G
I/O pin for the external address/data bus. This function
is enabled when the external bus is enabled.
AD15
General-purpose I/O pins. It is possible to select
whether or not a pull-up resistance is used by
configuring a register. In external bus mode, each pin
is enabled as a general-purpose I/O port when the
corresponding bit in the external address output control
register (HACR) is 1.
P20 to P23
97 to 100
95 to 98
G
Output pins of the external address bus. When the
corresponding bit in the external address output control
register (HACR) is 0, the pins are enabled as high
address output pins (A16 to A19).
A16 to A19
PPG9, B, D, F
PPG output pins.
*1 : FPT-100P-M06
*2 : FPT-100P-M20
*3 : Refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types.
DS07-13748-5E
15
MB90860E Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Oscillator circuit
High-speed oscillator feedback
resistance = approx. 1 MΩ
X1
X0
Xout
Standby control signal
B
Oscillator circuit
X1A
X0A
Xout
Low-speed oscillator feedback
resistance = approx. 10 MΩ
Standby control signal
C
D
• Mask ROM and evaluation device:
CMOS hysteresis input pin
• Flash memory device:
CMOS input pin
R
CMOS
hysteresis
input
• Mask ROM and evaluation device:
CMOS hysteresis input pin
Pull-down resistor value: approx. 50 kΩ
• Flash memory device:
CMOS input pin
R
CMOS
hysteresis
input
Pull-down
resistor
No pull-down
E
CMOS hysteresis input pin
Pull-up resistor value: approx. 50 kΩ
Pull-up
resistor
R
CMOS
hysteresis
input
(Continued)
16
DS07-13748-5E
MB90860E Series
Type
Circuit
Remarks
F
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input (with input shut-
down in standby mode)
• Automotive input (with input shutdown in
standby mode)
P-ch
N-ch
Pout
Nout
R
CMOS
hysteresis input
Automotive input
Standby control for
input shutdown
G
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input (with input shut-
down in standby mode)
• Automotive input (with input shutdown in
standby mode)
Pull-up control
Pout
P-ch
P-ch
• TTL input (with input shutdown in standby
mode)
N-ch
Nout
• Programmable pull-up resistor: 50 kΩ
approx.
R
CMOS
hysteresis input
Automotive input
TTL input
Standby control for
input shutdown
H
• CMOS level output (IOL = 3 mA, IOH = −3 mA)
• CMOS hysteresis input (with input shut-
down in standby mode)
• Automotive input (with input shutdown in
standby mode)
P-ch
N-ch
Pout
Nout
R
CMOS
hysteresis input
Automotive input
Standby control for
input shutdown
(Continued)
DS07-13748-5E
17
MB90860E Series
Type
Circuit
Remarks
I
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input (with input shut-
down in standby mode)
• Automotive input (with input shutdown in
standby mode)
P-ch
N-ch
Pout
Nout
• A/D converter analog input
R
CMOS
hysteresis input
Automotive input
Standby control for
input shutdown
Analog input
J
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• D/A analog output
• CMOS hysteresis input (with input shut-
down in standby mode)
• Automotive input (with input shutdown in
standby mode)
• A/D converter analog input
P-ch
N-ch
Pout
Nout
R
CMOS
hysteresis input
Automotive input
Standby control for
input shutdown
Analog input
Analog output
K
Power supply input protection circuit
P-ch
N-ch
L
• A/D converter reference voltage power
supply input pin with protection circuit
• Flash devices do not have a protection
circuit against VCC for pin AVRH
ANE
AVR
P-ch
N-ch
ANE
(Continued)
18
DS07-13748-5E
MB90860E Series
(Continued)
Type
Circuit
Remarks
M
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS input (with input shutdown in stand-
by mode)
• Automotive input (with input shutdown in
standby mode)
P-ch
N-ch
Pout
Nout
R
CMOS input
Automotive input
Standby control for
input shutdown
N
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS input (with input shutdown in stand-
by mode)
Pull-up control
P-ch
• Automotive input (with input shutdown in
standby mode)
• TTL input (with input shutdown in standby
mode)
P-ch
Pout
Nout
N-ch
Programmable pull-up registor:50 kΩ
approx
R
CMOS input
Automotive input
TTL input
Standby control for
input shutdown
O
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS input (with input shutdown in stand-
by mode)
• Automotive input (with input shutdown in
standby mode)
P-ch
N-ch
Pout
Nout
• A/D converter analog input
R
CMOS input
Automotive input
Standby control for
input shutdown
Analog input
DS07-13748-5E
19
MB90860E Series
■ HANDLING DEVICES
1. Preventing latch-up
Latch-up may occur in a CMOS IC under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
Therefore, be very careful not to apply analog power-supply voltages in excess of the digital power-supply
voltages.
2. Handling unused pins
Leaving unused input pins open may cause malfunctions or permanent damages. Unused input pins must
therefore be connected to a pull-up or pull-down resistor, with a resistance of 2 kΩ or more.
Unused bidirectional pins should be set to the output state and can then be left open, or set to the input state
and handled as described above.
3. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power
supply and ground externally. Connect VCC and VSS pins to the device from the current supply source at a
low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS pins in the vicinity of VCC and VSS pins of the device.
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90860E
Series
Vcc
Vss
Vcc
Vss
4. Mode pins (MD0 to MD2)
Connect the mode pins directly to the VCC or VSS pins. To prevent the device unintentionally entering test mode
due to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to VCC or VSS
pins and to provide a low-impedance connection.
20
DS07-13748-5E
MB90860E Series
5. Sequence for turning on the A/D converter power supply and analog inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23)
after turning on the digital power supply (VCC) .
Turn off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make
sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies
simultaneously is acceptable) .
6. Handling A/D converter pins when the A/D converter is not used
When the A/D converter is not used, connect the pins such that AVCC = VCC, AVSS = AVRH = AVRL = VSS.
7. Crystal oscillator circuit
Noise near the X0, X1, X0A, and X1A pins can cause the device to malfunction. Design the printed circuit board
such that the crystal oscillators (or ceramic oscillators) are as close to the X0 and X1 pins, and X0A and X1A
pins as possible, and that the bypass capacitor to ground is as close to the device as possible. Furthermore, try
as much as possible to prevent the wiring for these components from crossing over the wiring of other circuitry.
It is highly recommended that the printed circuit board artwork is designed such that the X0, X1 pins and X0A,
X1A pins are surrounded by ground plane, as this is expected to produce more stable operation.
Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this
device.
8. Pull-up/down resistors
The MB90860E series does not support internal pull-up/down resistors (however, port 0 to port 3 have built-in
pull-up resistors). Use external components where needed.
9. Using external clock
To use an external clock, drive the X0 pin and leave the X1 pin open.
MB90860E Series
X0
Open
X1
10. Precautions when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, connect the X0A pin to a pull-down resistance and leave
the X1A pin open.
11. Precautions when operating in PLL clock mode
In the MB90860E series, if the oscillator is disconnected or the clock input is stopped while operating in PLL
mode, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit
contained in the PLL. However, operation under these circumstances is not guaranteed.
12. Precautions when turning the power on
To prevent the internal regulator circuit from malfunctioning, ensure that the time over which the voltage rises
when the power is turned on is 50 or more µs (0.2 V to 2.7 V)
DS07-13748-5E
21
MB90860E Series
13. Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operating range. Therefore, the VCC supply voltage should be stabilized.
As a reference, stabilize the supply voltage by meeting the following standards.
• VCC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the
standard VCC supply voltage
• The coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
14. Initialization
The device has internal registers that are only initialized by a power-on reset only. To initialize these registers,
turn on the power again.
15. Port 0 to port 3 output during power-on (external bus mode)
In external bus mode, the outputs of Port 0 to Port 3 may be indeterminate regardless of the reset input.
1/2VCC
VCC
Port 0 to Port 3
Port 0 to Port 3 outputs = Hi-Z
Port 0 to Port 3 outputs
might be indeterminate
16. Flash security function
The security bit is located in the flash memory area. If protection code 01H is written to the security bit, the
security function is applied to the flash memory.
Therefore do not write 01H to this address if you do not use the security function.
Please refer to following table for the address of the security bit.
Flash memory size
Address of security bit
MB90F867E(S)
Embedded 1 Mbit Flash Memory
FE0001H
17. Serial communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of
receiving wrong data due to the noise.
22
DS07-13748-5E
MB90860E Series
■ BLOCK DIAGRAMS
• MB90V340E-101/102
X0,X1
X0A,X1A*
Clock
16LX
CPU
RST
Controller
Free run
FRCK0
Timer 0
RAM
30 Kbytes
Input
Capture
8 channels
IN7 to IN0
OUT7 to OUT0
FRCK1
Output
Compare
8 channels
Prescaler
5 channels
Free run
Timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
Controller
3 channels
LIN-UART
5 channels
RX2 to RX0
TX2 to TX0
16-bit Reload
Timer
4 channels
AVCC
TIN3 to TIN0
AVSS
TOT3 to TOT0
8/10-bit
ADC
24 channels
AN23 to AN0
AVRH
AD15 to AD00
A23 to A16
ALE
AVRL
ADTG
RD
10-bit
DAC
2 channels
External
Bus
Interface
WR/WRL
WRH
DA01, DA00
HRQ
HAK
8/16-bit
PPG
16/8 channels
PPGF to PPG0
RDY
CLK
I2C
Interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
External
Interrupt
16 channels
INT7 to INT0
DMAC
Clock
CKOT
Monitor
* : Only in the MB90V340E-102
DS07-13748-5E
23
MB90860E Series
• MB90867E(S), MB90F867E(S)
X0,X1
Clock
16LX
CPU
X0A,X1A*
Controller
RST
Free run
Timer 0
FRCK0
RAM
6 Kbytes
Input
Capture
IN7 to IN0
8 channels
ROM/Flash
128 Kbytes
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler
4 channels
Free run
Timer 1
SOT3 to SOT0
LIN-UART
SCK3 to SCK0
4 channels
SIN3 to SIN0
AVCC
16-bit Reload
Timer
4 channels
TIN3 to TIN0
AVSS
AN23 to AN0
TOT3 to TOT0
8/10-bit
ADC
24 channels
AD15 to AD00
A23 to A16
ALE
AVRH
AVRL
ADTG
RD
External
Bus
Interface
WR/WRL
WRH
8/16-bit
PPG
16/8 channels
HRQ
PPGF to PPG0
HAK
RDY
CLK
I2C
Interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
External
Interrupt
16 channels
INT7 to INT0
DMAC
Clock
Monitor
CKOT
* : Only for devices without an 'S' suffix in the part number
24
DS07-13748-5E
MB90860E Series
■ MEMORY MAP
MB90867E(S)
MB90F867E(S)
MB90V340E-101/102
000000
H
000000
H
Peripherals
Peripherals
0000EF
H
0000EF
H
External access area
External access area
000100
H
000100
H
RAM 6 Kbytes
0018FF
H
RAM 30 Kbytes
0078FF
H
007900
H
007900
H
Peripherals
Peripherals
007FFF
H
007FFF
H
008000
H
008000
H
ROM
(image of FF bank)
ROM (image
of FF bank)
00FFFF
H
00FFFFH
External access area
ROM (F8 bank)
F80000
H
F8FFFF
H
F90000
H
ROM (F9 bank)
ROM (FA bank)
ROM (FB bank)
ROM (FC bank)
ROM (FD bank)
ROM (FE bank)
ROM (FF bank)
F9FFFF
H
H
FA0000
FAFFFF
FB0000
H
H
External
access area
FBFFFF
FC0000
H
H
FCFFFF
H
H
FD0000
FDFFFF
FE0000
H
H
FE0000
H
ROM (FE bank)
ROM (FF bank)
FEFFFF
FF0000
H
H
FEFFFF
FF0000
H
H
FFFFFF
H
FFFFFF
H
: No access
Note : An image of the FF bank ROM data is visible in the upper part of bank 00. This makes it possible to use the
C compiler small memory model. Because the lower 16 bits of addresses in the 00 bank and the FF bank
are the same, tables in ROM can be referenced without using the far specifier in the pointer declarations.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and therefore, the entire image is not visible in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
DS07-13748-5E
25
MB90860E Series
■ I/O MAP
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
000000H Port 0 Data Register
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
ADER5
ADER6
ADER7
ILSR0
ILSR1
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
11111111B
11111111B
11111111B
XXXXXXXXB
XXXX0XXXB
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000100B
000001H Port 1 Data Register
000002H Port 2 Data Register
Port 2
000003H Port 3 Data Register
Port 3
000004H Port 4 Data Register
Port 4
000005H Port 5 Data Register
Port 5
000006H Port 6 Data Register
Port 6
000007H Port 7 Data Register
Port 7
000008H Port 8 Data Register
Port 8
000009H Port 9 Data Register
Port 9
00000AH Port A Data Register
Port A
Port 5, A/D
Port 6, A/D
Port 7, A/D
Ports
00000BH Port 5 Analog Input Enable Register
00000CH Port 6 Analog Input Enable Register
00000DH Port 7 Analog Input Enable Register
00000EH Input Level Select Register 0
00000FH Input Level Select Register 1
000010H Port 0 Direction Register
000011H Port 1 Direction Register
000012H Port 2 Direction Register
000013H Port 3 Direction Register
000014H Port 4 Direction Register
000015H Port 5 Direction Register
000016H Port 6 Direction Register
000017H Port 7 Direction Register
000018H Port 8 Direction Register
000019H Port 9 Direction Register
00001AH Port A Direction Register
00001BH
Ports
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Reserved
00001CH Port 0 Pull-up Control Register
00001DH Port 1 Pull-up Control Register
00001EH Port 2 Pull-up Control Register
00001FH Port 3 Pull-up Control Register
PUCR0
PUCR1
PUCR2
PUCR3
R/W
R/W
Port 0
Port 1
Port 2
Port 3
00000000B
00000000B
00000000B
00000000B
R/W
W, R/W
(Continued)
26
DS07-13748-5E
MB90860E Series
Abbrevia-
tion
Address
Register
Access Resource name Initial value
000020H Serial Mode Register 0
000021H Serial Control Register 0
SMR0
SCR0
W,R/W
W,R/W
00000000B
00000000B
RDR0/
TDR0
000022H Receive/Transmit Data Register 0
R/W
00000000B
00001000B
000000XXB
000023H Serial Status Register 0
SSR0
R,R/W
UART0
Extended Communication Control
Register 0
R,W,
R/W
000024H
ECCR0
000025H Extended Status/Control Register 0
000026H Baud Rate Generator Register 00
000027H Baud Rate Generator Register 01
000028H Serial Mode Register 1
ESCR0
BGR00
BGR01
SMR1
R/W
R/W
00000100B
00000000B
00000000B
00000000B
00000000B
R/W
W,R/W
W,R/W
000029H Serial Control Register 1
SCR1
RDR1/
TDR1
00002AH Receive/Transmit Data Register 1
00002BH Serial Status Register 1
R/W
00000000B
00001000B
000000XXB
SSR1
R,R/W
UART1
Extended Communication Control
R,W,
R/W
00002CH
ECCR1
Register 1
00002DH Extended Status/Control Register 1
00002EH Baud Rate Generator Register 10
00002FH Baud Rate Generator Register 11
000030H PPG 0 Operation Mode Control Register
000031H PPG 1 Operation Mode Control Register
000032H PPG 0/PPG 1 Count Clock Select Register
000033H
ESCR1
BGR10
BGR11
PPGC0
PPGC1
PPG01
Reserved
PPGC2
PPGC3
PPG23
Reserved
PPGC4
PPGC5
PPG45
R/W
R/W
00000100B
00000000B
00000000B
0X000XX1B
0X000001B
000000X0B
R/W
W,R/W
W,R/W
R/W
16-bit PPG 0/1
16-bit PPG 2/3
16-bit PPG 4/5
000034H PPG 2 Operation Mode Control Register
000035H PPG 3 Operation Mode Control Register
000036H PPG 2/PPG 3 Count Clock Select Register
000037H
W,R/W
W,R/W
R/W
0X000XX1B
0X000001B
000000X0B
000038H PPG 4 Operation Mode Control Register
000039H PPG 5 Operation Mode Control Register
00003AH PPG 4/PPG 5 Clock Select Register
W,R/W
W,R/W
R/W
0X000XX1B
0X000001B
000000X0B
Address Match
Detection 1
00003BH Address Detect Control Register 1
PACSR1
R/W
00000000B
00003CH PPG 6 Operation Mode Control Register
00003DH PPG 7 Operation Mode Control Register
00003EH PPG 6/PPG 7 Count Clock Control Register
00003FH
PPGC6
PPGC7
PPG67
W,R/W
W,R/W
R/W
0X000XX1B
0X000001B
000000X0B
16-bit PPG 6/7
Reserved
(Continued)
DS07-13748-5E
27
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
000040H PPG 8 Operation Mode Control Register
000041H PPG 9 Operation Mode Control Register
PPGC8
PPGC9
W,R/W
W,R/W
0X000XX1B
0X000001B
16-bit PPG 8/9
PPG 8/PPG 9 Count Clock Control
000042H
Register
PPG89
R/W
000000X0B
000043H
Reserved
000044H PPG A Operation Mode Control Register PPGCA
000045H PPG B Operation Mode Control Register PPGCB
PPG A/PPG B Count Clock Select
W,R/W
W,R/W
0X000XX1B
0X000001B
16-bit PPG A/B
16-bit PPG C/D
16-bit PPG E/F
000046H
PPGAB
R/W
000000X0B
Register
000047H
Reserved
000048H PPG C Operation Mode Control Register PPGCC
000049H PPG D Operation Mode Control Register PPGCD
PPG C/PPG D Count Clock Select
W,R/W
W,R/W
0X000XX1B
0X000001B
00004AH
PPGCD
R/W
000000X0B
Register
00004BH
Reserved
00004CH PPG E Operation Mode Control Register PPGCE
00004DH PPG F Operation Mode Control Register PPGCF
PPG E/PPG F Count Clock Select
W,R/W
W,R/W
0X000XX1B
0X000001B
00004EH
PPGEF
R/W
000000X0B
Register
00004FH
Reserved
ICS01
ICE01
ICS23
ICE23
ICS45
ICE45
ICS67
ICE67
OCS0
OCS1
OCS2
OCS3
OCS4
OCS5
OCS6
OCS7
000050H Input Capture Control Status 0/1
000051H Input Capture Edge 0/1
R/W
R/W, R
R/W
R
00000000B
XXX0X0XXB
00000000B
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
XXX000XXB
0000XX00B
0XX00000B
0000XX00B
0XX00000B
0000XX00B
0XX00000B
0000XX00B
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
000052H Input Capture Control Status 2/3
000053H Input Capture Edge 2/3
000054H Input Capture Control Status 4/5
000055H Input Capture Edge 4/5
R/W
R
000056H Input Capture Control Status 6/7
000057H Input Capture Edge 6/7
R/W
R/W, R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000058H Output Compare Control Status 0
000059H Output Compare Control Status 1
00005AH Output Compare Control Status 2
00005BH Output Compare Control Status 3
00005CH Output Compare Control Status 4
00005DH Output Compare Control Status 5
00005EH Output Compare Control Status 6
00005FH Output Compare Control Status 7
0XX00000B
(Continued)
28
DS07-13748-5E
MB90860E Series
Abbrevia-
tion
Address
Register
Access Resource name Initial value
000060H Timer Control Status 0
000061H Timer Control Status 0
000062H Timer Control Status 1
000063H Timer Control Status 1
000064H Timer Control Status 2
000065H Timer Control Status 2
000066H Timer Control Status 3
000067H Timer Control Status 3
000068H A/D Control Status 0
000069H A/D Control Status 1
00006AH A/D Data 0
TMCSR0
TMCSR0
TMCSR1
TMCSR1
TMCSR2
TMCSR2
TMCSR3
TMCSR3
ADCS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXX0000B
000XXXX0B
0000000XB
00000000B
XXXXXX00B
00000000B
00000000B
16-bit Reload
Timer 0
16-bit Reload
Timer 1
16-bit Reload
Timer 2
16-bit Reload
Timer 3
ADCS1
ADCR0
A/D Converter
ROM Mirror
00006BH A/D Data 1
ADCR1
R
00006CH ADC Setting 0
ADSR0
R/W
R/W
00006DH ADC Setting 1
ADSR1
00006EH
Reserved
ROMM
00006FH ROM Mirror Function Select
W
XXXXXXX1B
000070H
to
Reserved
00009AH
DMA Descriptor Channel Selection
00009BH
Register
DCSR
R/W
00000000B
DMA
00009CH DMA Status L Register
00009DH DMA Status H Register
DSRL
DSRH
R/W
R/W
00000000B
00000000B
Address Match
Detection 0
00009EH Address Detect Control Register 0
PACSR0
DIRR
R/W
R/W
00000000B
Delayed Interrupt Source Generate/
00009FH
Delayed Interrupt XXXXXXX0B
Release Register
Low Power
00011000B
0000A0H Low-power Mode Control Register
0000A1H Clock Selection Register
LPMCR
CKSCR
Reserved
W,R/W
R,R/W
Control Circuit
Low Power
11111100B
Control Circuit
0000A2H,
0000A3H
0000A4H DMA Stop Status Register
DSSR
ARSR
HACR
ECSR
R/W
W
DMA
00000000B
0011XX00B
00000000B
0000A5H Automatic Ready Function Select Register
0000A6H External Address Output Control Register
0000A7H Bus Control Signal Selection Register
External Memory
Access
W
W
0000000XB
(Continued)
DS07-13748-5E
29
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
0000A8H Watchdog Control Register
0000A9H Time Base Timer Control Register
0000AAH Watch Timer Control Register
0000ABH
WDTC
TBTC
WTC
R,W
Watchdog Timer
Time Base Timer
Watch Timer
XXXXX111B
1XX00100B
1X001000B
W,R/W
R,R/W
Reserved
0000ACH DMA Enable L Register
0000ADH DMA Enable H Register
DERL
DERH
R/W
R/W
00000000B
00000000B
DMA
Flash Control Status Register
0000AEH (Flash Devices only.
Otherwise reserved)
FMCS
R,R/W
Flash Memory
000X0000B
0000AFH
Reserved
0000B0H Interrupt Control Register 00
0000B1H Interrupt Control Register 01
0000B2H Interrupt Control Register 02
0000B3H Interrupt Control Register 03
0000B4H Interrupt Control Register 04
0000B5H Interrupt Control Register 05
0000B6H Interrupt Control Register 06
0000B7H Interrupt Control Register 07
0000B8H Interrupt Control Register 08
0000B9H Interrupt Control Register 09
0000BAH Interrupt Control Register 10
0000BBH Interrupt Control Register 11
0000BCH Interrupt Control Register 12
0000BDH Interrupt Control Register 13
0000BEH Interrupt Control Register 14
0000BFH Interrupt Control Register 15
0000C0H D/A Converter Data 0 Register
0000C1H D/A Converter Data 1 Register
0000C2H D/A Control 0 Register
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
DAT0
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
R/W
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
XXXXXXXXB
XXXXXXXXB
XXXXXXX0B
XXXXXXX0B
Interrupt Control
DAT1
R/W
D/A Converter
DACR0
DACR1
R/W
0000C3H D/A Control 1 Register
R/W
0000C4H,
0000C5H
Reserved
0000C6H External Interrupt Enable 0
0000C7H External Interrupt Source 0
0000C8H External Interrupt Level Setting 0
0000C9H External Interrupt Level Setting 0
ENIR0
EIRR0
ELVR0
ELVR0
R/W
R/W
R/W
R/W
00000000B
XXXXXXXXB
00000000B
00000000B
(Continued)
External Interrupt 0
30
DS07-13748-5E
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
0000CAH External Interrupt Enable 1
ENIR1
EIRR1
ELVR1
ELVR1
EISSR
PSCCR
BAPL
R/W
R/W
R/W
R/W
R/W
W
00000000B
XXXXXXXXB
00000000B
0000CBH External Interrupt Source 1
0000CCH External Interrupt Level Setting 1
0000CDH External Interrupt Level Setting 1
0000CEH External Interrupt Source Select
0000CFH PLL/Sub Clock Control Register
0000D0H DMA Buffer Address Pointer L Register
0000D1H DMA Buffer Address Pointer M Register
0000D2H DMA Buffer Address Pointer H Register
0000D3H DMA Control Register
External Interrupt 1
PLL
00000000B
00000000B
XXXX0000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
R/W
R/W
R/W
BAPM
BAPH
DMACS
I/O Register Address Pointer L
DMA
0000D4H
Register
IOAL
IOAH
R/W
R/W
XXXXXXXXB
XXXXXXXXB
I/O Register Address Pointer H
0000D5H
Register
0000D6H Data Counter L Register
0000D7H Data Counter H Register
0000D8H Serial Mode Register 2
0000D9H Serial Control Register 2
DCTL
DCTH
SMR2
SCR2
R/W
R/W
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
W,R/W
W,R/W
RDR2/
TDR2
0000DAH Receive/Transmit Data Register 2
R/W
00000000B
00001000B
000000XXB
0000DBH Serial Status Register 2
SSR2
R,R/W
UART2
Extended Communication Control
Register 2
R,W,
R/W
0000DCH
ECCR2
0000DDH Extended Status Control Register 2
0000DEH Baud Rate Generator Register 20
0000DFH Baud Rate Generator Register 21
ESCR2
BGR20
BGR21
R/W
R/W
R/W
00000100B
00000000B
00000000B
0000E0H
to
External area
0000FFH
007900H Reload Register L0
007901H Reload Register H0
007902H Reload Register L1
007903H Reload Register H1
007904H Reload Register L2
007905H Reload Register H2
007906H Reload Register L3
007907H Reload Register H3
PRLL0
PRLH0
PRLL1
PRLH1
PRLL2
PRLH2
PRLL3
PRLH3
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16-bit PPG 0/1
16-bit PPG 2/3
DS07-13748-5E
31
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
007908H Reload Register L4
007909H Reload Register H4
00790AH Reload Register L5
00790BH Reload Register H5
00790CH Reload Register L6
00790DH Reload Register H6
00790EH Reload Register L7
00790FH Reload Register H7
007910H Reload Register L8
007911H Reload Register H8
007912H Reload Register L9
007913H Reload Register H9
007914H Reload Register LA
007915H Reload Register HA
007916H Reload Register LB
007917H Reload Register HB
007918H Reload Register LC
007919H Reload Register HC
00791AH Reload Register LD
00791BH Reload Register HD
00791CH Reload Register LE
00791DH Reload Register HE
00791EH Reload Register LF
00791FH Reload Register HF
007920H Input Capture 0
PRLL4
PRLH4
PRLL5
PRLH5
PRLL6
PRLH6
PRLL7
PRLH7
PRLL8
PRLH8
PRLL9
PRLH9
PRLLA
PRLHA
PRLLB
PRLHB
PRLLC
PRLHC
PRLLD
PRLHD
PRLLE
PRLHE
PRLLF
PRLHF
IPCP0
IPCP0
IPCP1
IPCP1
IPCP2
IPCP2
IPCP3
IPCP3
IPCP4
IPCP4
IPCP5
IPCP5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
16-bit PPG 4/5
16-bit PPG 6/7
16-bit PPG 8/9
16-bit PPG A/B
16-bit PPG C/D
16-bit PPG E/F
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
007921H Input Capture 0
R
007922H Input Capture 1
R
007923H Input Capture 1
R
007924H Input Capture 2
R
007925H Input Capture 2
R
007926H Input Capture 3
R
007927H Input Capture 3
R
007928H Input Capture 4
R
007929H Input Capture 4
R
00792AH Input Capture 5
R
00792BH Input Capture 5
R
32
DS07-13748-5E
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
00792CH Input Capture 6
00792DH Input Capture 6
00792EH Input Capture 7
00792FH Input Capture 7
IPCP6
IPCP6
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
R
Input Capture 6/7
IPCP7
R
IPCP7
R
007930H Output Compare 0
007931H Output Compare 0
007932H Output Compare 1
007933H Output Compare 1
007934H Output Compare 2
007935H Output Compare 2
007936H Output Compare 3
007937H Output Compare 3
007938H Output Compare 4
007939H Output Compare 4
00793AH Output Compare 5
00793BH Output Compare 5
00793CH Output Compare 6
00793DH Output Compare 6
00793EH Output Compare 7
00793FH Output Compare 7
007940H Timer Data 0
OCCP0
OCCP0
OCCP1
OCCP1
OCCP2
OCCP2
OCCP3
OCCP3
OCCP4
OCCP4
OCCP5
OCCP5
OCCP6
OCCP6
OCCP7
OCCP7
TCDT0
TCDT0
TCCSL0
TCCSH0
TCDT1
TCDT1
TCCSL1
TCCSH1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
Free-run Timer 0
007941H Timer Data 0
00000000B
007942H Timer Control Status 0
007943H Timer Control Status 0
007944H Timer Data 1
00000000B
0XXXXXXXB
00000000B
007945H Timer Data 1
00000000B
Free-run Timer 1
007946H Timer Control Status 1
007947H Timer Control Status 1
00000000B
0XXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
007948H
TMR0/
TMRLR0
16-bit Reload
Timer 0
Timer 0/Reload 0
007949H
00794AH
TMR1/
TMRLR1
16-bit Reload
Timer 1
Timer 1/Reload 1
00794BH
00794CH
TMR2/
TMRLR2
16-bit Reload
Timer 2
Timer 2/Reload 2
00794DH
00794EH
TMR3/
TMRLR3
16-bit Reload
Timer 3
Timer 3/Reload 3
00794FH
DS07-13748-5E
33
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
007950H Serial Mode Register 3
007951H Serial Control Register 3
SMR3
SCR3
W,R/W
W,R/W
00000000B
00000000B
RDR3/
TDR3
007952H Receive/Transmit Data Register 3
R/W
00000000B
00001000B
000000XXB
007953H Serial Status Register 3
SSR3
R,R/W
UART3
Extended Communication Control
Register 3
R,W,
R/W
007954H
ECCR3
007955H Extended Status Control Register
007956H Baud Rate Generator Register 30
007957H Baud Rate Generator Register 31
007958H Serial Mode Register 4
ESCR3
BGR30
BGR31
SMR4
R/W
R/W
00000100B
00000000B
00000000B
00000000B
00000000B
R/W
W,R/W
W,R/W
007959H Serial Control Register 4
SCR4
RDR4/
TDR4
00795AH Receive/Transmit Data Register 4
00795BH Serial Status Register 4
R/W
00000000B
00001000B
000000XXB
SSR4
R,R/W
UART4
Extended Communication Control
R,W,
R/W
00795CH
ECCR4
Register 4
00795DH Extended Status Control Register
00795EH Baud Rate Generator Register 40
00795FH Baud Rate Generator Register 41
ESCR4
BGR40
BGR41
R/W
R/W
R/W
00000100B
00000000B
00000000B
007960H
to
Reserved
00796BH
00796CH Clock Output Enable Register
CLKR
R/W
Clock Monitor
XXXX0000B
00796DH
to
Reserved
00796FH
007970H I2C Bus Status Register 0
007971H I2C bus Control Register 0
IBSR0
IBCR0
ITBAL0
ITBAH0
ITMKL0
ITMKH0
ISBA0
R
W,R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
11111111B
00111111B
00000000B
01111111B
00000000B
007972H
I2C 10-bit Slave Address Register 0
007973H
007974H
I2C Interface 0
I2C 10-bit Slave Address Mask
Register 0
007975H
007976H I2C 7-bit Slave Address Register 0
007977H I2C 7-bit Slave Address Mask Register 0
007978H I2C Data Register 0
ISMK0
IDAR0
007979H,
00797AH
Reserved
(Continued)
34
DS07-13748-5E
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
00797BH I2C Clock Control Register 0
ICCR0
R/W
I2C Interface 0
00011111B
00797CH
to
Reserved
00797FH
007980H I2C Bus Status Register 1
007981H I2C Bus Control Register 1
IBSR1
IBCR1
ITBAL1
ITBAH1
ITMKL1
ITMKH1
ISBA1
R
W,R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
11111111B
00111111B
00000000B
01111111B
00000000B
007982H
I2C 10-bit Slave Address Register 1
007983H
007984H
I2C Interface 1
I2C 10-bit Slave Address Mask
Register 1
007985H
007986H I2C 7-bit Slave Address Register 1
007987H I2C 7-bit Slave Address Mask Register 1
007988H I2C Data Register 1
ISMK1
IDAR1
007989H,
00798AH
Reserved
00798BH I2C Clock Control Register 1
ICCR1
R/W
I2C Interface 1
Clock Modulator
00011111B
0001X000B
00798CH
to
0079C1H
Reserved
CMCR
Reserved
0079C2H Clock Modulator Control Register
R, R/W
0079C3H
to
0079DFH
0079E0H Detect Address Setting 0
0079E1H Detect Address Setting 0
0079E2H Detect Address Setting 0
0079E3H Detect Address Setting 1
0079E4H Detect Address Setting 1
0079E5H Detect Address Setting 1
0079E6H Detect Address Setting 2
0079E7H Detect Address Setting 2
0079E8H Detect Address Setting 2
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
PADR2
PADR2
PADR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 0
0079E9H
to
Reserved
0079EFH
(Continued)
DS07-13748-5E
35
MB90860E Series
(Continued)
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
0079F0H Detect Address Setting 3
0079F1H Detect Address Setting 3
0079F2H Detect Address Setting 3
0079F3H Detect Address Setting 4
0079F4H Detect Address Setting 4
0079F5H Detect Address Setting 4
0079F6H Detect Address Setting 5
0079F7H Detect Address Setting 5
0079F8H Detect Address Setting 5
PADR3
PADR3
PADR3
PADR4
PADR4
PADR4
PADR5
PADR5
PADR5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 1
0079F9H
to
Reserved
007FFFH
Notes : • Initial value of “X” represents undefined value.
• Do not write to the reserved areas in the I/O map. Reading from reserved addresses will return undefined
values.
36
DS07-13748-5E
MB90860E Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt control
Interrupt vector
EI2OS
clear
DMA ch
number
register
Interrupt source
Number
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
Address
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
Number
Address
Reset
N
N
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
⎯
⎯
⎯
⎯
⎯
⎯
INT9 instruction
Exception
N
(Reserved)
N
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
(Reserved)
N
Input Capture 6
Y1
Y1
N
Input Capture 7
I2C0
(Reserved)
N
16-bit Reload Timer 0
16-bit Reload Timer 1
16-bit Reload Timer 2
16-bit Reload Timer 3
PPG 0/1/4/5
Y1
Y1
Y1
Y1
N
1
2
⎯
⎯
⎯
⎯
⎯
⎯
3
PPG 2/3/6/7
N
PPG 8/9/C/D
N
PPG A/B/E/F
N
Time Base Timer
External Interrupt 0 to 3, 8 to 11
Watch Timer
N
Y1
N
⎯
4
External Interrupt 4 to 7, 12 to 15
8/10-bit A/D Converter
Free-run Timer 0, Free-run Timer 1
Input Capture 4/5, I2C1
Output Compare 0/1/4/5
Input Capture 0 to 3
Output Compare 2/3/6/7
UART 0 Reception
UART 0 Transmission
Y1
Y1
N
5
⎯
6
Y1
Y1
Y1
Y1
Y2
Y1
7
8
9
10
11
UART 1 Reception /
UART 3 Reception
Y2
Y1
12
13
#37
#38
FFFF68H
FFFF64H
ICR13
0000BDH
UART 1 Transmission /
UART 3 Transmission
(Continued)
DS07-13748-5E
37
MB90860E Series
(Continued)
Interrupt control
register
Interrupt vector
Number Address
EI2OS
clear
DMA ch
number
Interrupt source
Number
Address
UART 2 Reception /
UART 4 Reception
Y2
Y1
14
15
#39
#40
FFFF60H
FFFF5CH
ICR14
0000BEH
UART 2 Transmission /
UART 4 Transmission
Flash Memory
N
N
⎯
⎯
#41
#42
FFFF58H
FFFF54H
ICR15
0000BFH
Delayed interrupt
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • Peripheral resources that share an ICR register have the same interrupt level.
• When two peripheral resources share an ICR register, only one can use Extended Intelligent I/O Service
at a time.
• When either of the two peripheral resources sharing an ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.
38
DS07-13748-5E
MB90860E Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
AVCC
VCC = AVCC*2
Power supply voltage*1
AVRH,
AVRL
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH ≥ AVRL
VSS − 0.3 VSS + 6.0
V
Input voltage*1
Output voltage*1
VI
VO
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
*3
*3
Maximum clamp current
ICLAMP
Σ|ICLAMP|
IOL
−4.0
⎯
+4.0
40
mA *5
mA *5
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mW
Total maximum clamp current
“L” level maximum output current
“L” level average output current
“L” level maximum overall output current
“L” level average overall output current
“H” level maximum output current
“H” level average output current
“H” level maximum overall output current
“H” level average overall output current
Power consumption
⎯
15
IOLAV
ΣIOL
⎯
4
⎯
100
50
ΣIOLAV
IOH
⎯
⎯
−15
−4
IOHAV
ΣIOH
ΣIOHAV
PD
⎯
⎯
−100
−50
340
+105
+150
⎯
⎯
Operating temperature
TA
−40
−55
°C
Storage temperature
TSTG
°C
*1 : This parameter is based on VSS = AVSS = 0 V.
*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3 : VI and VO must not exceed VCC + 0.3 V. VI must not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means using external components, the ICLAMP rating supersedes the
VI rating.
*4 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0, and PA1
(Continued)
DS07-13748-5E
39
MB90860E Series
(Continued)
*5 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47,
P50 to P57 (evaluation device : P50 to P55) , P60 to P67, P70 to P77, P80 to P87,
P90 to P97, PA0, and PA1
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied by placing a limiting resistance between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed the rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , power may
be supplied through the +B pin, resulting in incomplete operation of the microcontroller.
• Note that if the +B input is applied during power-on, the power supplied via the +B pin may result in the
supply voltage being insufficient to activate the power-on reset.
• Care must be taken not to leave +B input pins open.
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
N-ch
+B input (0 V to 16 V)
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
40
DS07-13748-5E
MB90860E Series
2. Recommended Operating Conditions
(VSS = AVSS = 0 V)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
4.0
5.0
5.5
V
V
During normal operation
During normal operation, when not
using the A/D converter and not
Flash programming.
3.5
5.0
5.5
VCC,
AVCC
Power supply voltage
4.5
3.0
5.0
5.5
5.5
V
V
When using an external bus
⎯
Maintains RAM data in stop mode
Use a ceramic capacitor or a
capacitor with similar AC
characteristics. The bypass
capacitor used on the VCC pin
should have a greater capacitance
than this capacitor.
Smoothing capacitor
CS
TA
0.1
⎯
⎯
1.0
µF
°C
Operating temperature
−40
+105
• C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-13748-5E
41
MB90860E Series
3. DC Characteristics
Sym-
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Pin
Condition
Unit
Remarks
bol
Min
Typ
Max
Port inputs if CMOS
hysteresis input levels
are selected (except
P12, P44, P45, P46,
P47, P50, P82, P85)
VIHS
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
Port inputs if
automotive input levels
are selected
VIHA
VIHT
VIHS
⎯
⎯
⎯
⎯
⎯
⎯
0.8 VCC
2.0
⎯
⎯
⎯
VCC + 0.3
VCC + 0.3
VCC + 0.3
V
V
V
Input H
voltage
(At VCC =
5 V 10%)
Port inputs if TTL input
levels are selected
P12, P50, P82, P85
inputs if CMOS input
levels are selected
0.7 VCC
P44, P45, P46, P47 in-
putsifCMOShysteresis
input levels are selected
VIHI
⎯
⎯
0.7 VCC
⎯
VCC + 0.3
V
RST input pin (CMOS
hysteresis)
VIHR
VIHM
⎯
⎯
⎯
⎯
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
VCC − 0.3
MD input pin
Port inputs if CMOS
hysteresis input levels
are selected (except
P12, P44, P45, P46,
P47, P50, P82, P85)
VILS
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
Port inputs if
automotive input levels
are selected
VILA
VILT
VILS
⎯
⎯
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
VSS − 0.3
⎯
⎯
⎯
0.5 VCC
0.8
V
V
V
Input L
voltage
(At VCC =
5 V 10%)
Port inputs if TTL
input levels are selected
P12, P50, P82, P85
inputs if CMOS input
levels are selected
0.3 VCC
P44, P45, P46, P47 in-
putsifCMOShysteresis
input levels are selected
VILI
⎯
⎯
VSS − 0.3
⎯
0.3 VCC
V
RST input pin (CMOS
hysteresis)
VILR
VILM
VOH
⎯
⎯
Normal
outputs
I2Ccurrent VCC = 4.5 V,
outputs
⎯
⎯
VSS − 0.3
VSS − 0.3
VCC − 0.5
⎯
⎯
⎯
0.2 VCC
VSS + 0.3
⎯
V
V
V
MD input pin
Output H
voltage
VCC = 4.5 V,
IOH = −4.0 mA
Output H
voltage
VOHI
VOL
VOLI
VCC − 0.5
⎯
⎯
⎯
⎯
V
V
V
IOH = −3.0 mA
VCC = 4.5 V,
IOL = 4.0 mA
Output L
voltage
Normal
outputs
I2Ccurrent VCC = 4.5 V,
outputs
⎯
⎯
0.4
0.4
Output L
voltage
IOL = 3.0 mA
(Continued)
42
DS07-13748-5E
MB90860E Series
(Continued)
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit Remarks
Min Typ Max
Input leak current
IIL
⎯
VCC = 5.5 V, VSS < VI < VCC
−1
⎯
+ 1
µA
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
Pull-up
resistance
RUP
⎯
⎯
25
50
100 kΩ
Except
Pull-down
resistance
RDOWN
MD2
25
⎯
⎯
⎯
⎯
⎯
50
55
70
75
25
0.3
100 kΩ Flash
devices
VCC = 5.0 V,
Internal frequency : 24 MHz,
during normal operation.
70
85
90
35
0.8
mA
mA
mA
mA
mA
VCC = 5.0 V,
Flash
devices
ICC
Internal frequency : 24 MHz,
when writing FLASH memory.
VCC = 5.0 V,
Flash
devices
Internal frequency : 24 MHz,
when erasing FLASH memory.
VCC = 5.0 V,
ICCS
Internal frequency : 24 MHz,
in Sleep mode.
VCC = 5.0 V,
ICTS
Internal frequency : 2 MHz,
in Main Timer mode
VCC = 5.0 V,
Internal frequency : 24 MHz,
in PLL Timer mode,
Power supply
current*
VCC
ICTSPLL6
⎯
⎯
⎯
4
7
mA
external frequency = 4 MHz
VCC = 5.0 V
Internal frequency : 8 kHz,
during sub operation
TA = +25°C
ICCL
70
20
140 µA
VCC = 5.0 V
Internal frequency : 8 kHz,
during sub sleep
TA = +25°C
ICCLS
50
µA
VCC = 5.0 V
Internal frequency : 8 kHz,
in watch mode
TA = +25°C
VCC = 5.0 V,
in Stop mode,
TA = +25°C
ICCT
ICCH
CIN
⎯
⎯
⎯
10
7
35
25
15
µA
µA
pF
Other than C,
AVCC, AVSS,
AVRH,AVRL,
VCC, VSS
Input capacitance
⎯
5
* : Power supply currents were measured under test conditions using an external clock.
DS07-13748-5E
43
MB90860E Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
1/2 (at PLL stop)
When using an oscillator circuit
3
⎯
16
MHz
MHz
MHz
MHz
MHz
MHz
PLL multiplied by 1
When using an oscillator circuit*
4
4
⎯
⎯
⎯
⎯
16
12
8
PLL multiplied by 2
When using an oscillator circuit*
fC
X0, X1
PLL multiplied by 3
When using an oscillator circuit*
Clock frequency
4
PLL multiplied by 4
When using an oscillator circuit*
4
6
PLL multiplied by 6
When using an oscillator circuit*
⎯
⎯
⎯
4
3
⎯
24
MHz When using an external clock
kHz
fCL
X0A, X1A
X0, X1
32.768 100
62.5
⎯
⎯
30.5
⎯
333
333
⎯
⎯
⎯
ns When using an oscillator circuit
tCYL
Clock cycle time
X0, X1
X0A, X1A
X0
41.67
10
ns When using an external clock
tCYLL
µs
ns
PWH, PWL
PWHL, PWLL
10
Input clock
pulse width
Duty ratio is about 30% to 70%.
µs
X0A
5
15.2
Input clock rise and
fall time
tCR, tCF
X0
⎯
⎯
5
ns When using external clock
Internal operating
clock frequency
(machine clock)
fCP
fCPL
tCP
⎯
⎯
⎯
⎯
1.5
⎯
⎯
24
50
MHz When using main clock
kHz When using sub clock
ns When using main clock
µs When using sub clock
8.192
⎯
Internal operating
clock cycle time
(machine clock)
41.67
20
666
⎯
tCPL
122.1
* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within the range as
mentioned in “Relation between the external clock frequency and machine clock frequency”.
• Clock Timing
t
CYL
0.8 VCC
0.2 VCC
X0
P
WH
PWL
t
CF
tCR
tCYLL
0.8 VCC
0.2 VCC
X0A
P
WHL
PWLL
t
CF
tCR
44
DS07-13748-5E
MB90860E Series
• Guaranteed PLL operation range
Guaranteed operation range
5.5
4.0
Guaranteed A/D Converter
operation range
3.5
Guaranteed PLL operation range
1.5
24
4
Machine clock fCP (MHz)
Guaranteed operation range of MB90860E series
Guaranteed oscillation frequency range
× 2
× 1
× 6 × 4
× 3
24
16
12
× 1/2
(PLL off)
8
4.0
1.5
12
16
3
8
4
24
External clock fC (MHz) *
* : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 16 MHz
DS07-13748-5E
45
MB90860E Series
(2) Reset Standby Input
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0.0 V)
Value
Min
Parameter Symbol
Pin
Unit
Remarks
Max
500
⎯
ns
During normal operation
In Stop mode, Sub Clock
mode, Sub Sleep mode
and Watch mode
Reset input
tRSTL
Oscillation time of oscillator*
RST
⎯
⎯
µs
µs
time
+ 100 µs
100
In Time Timer mode
* : The oscillation time of the oscillator is the time it takes for the amplitude to reach 90%. In crystal oscillators, the
oscillation time is between several ms and to tens of ms. In crystal oscillators, the oscillation time is between
hundreds of µs to several ms. For an external clock, the oscillation time is 0 ms.
During normal operation:
tRSTL
RST
0.2 VCC
0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode, Power-on:
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
46
DS07-13748-5E
MB90860E Series
(3) Power On Reset
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0.0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
0.05
1
Max
30
Power on rise time
Power off time
tR
VCC
VCC
ms
⎯
tOFF
⎯
ms Waiting time until power-on
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If you change the power supply voltage too rapidly, a power on reset may occur. If the
power supply voltage is varied while the device is operating, it is recommended that
variation be limited such that the supply voltage rises smoothly as shown in the
following diagram. The supply voltage should be changed while the PLL clock is not
being used. However, the device can be operated while the PLL is being used if the
rate of change is less than 1 V/s.
VCC
We recommend a rise of
50 mV/ms maximum.
3 V
Holds RAM data
VSS
(4) Clock Output Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Parameter
Symbol
Pin
CLK
CLK
Condition
Unit
Remarks
Min
62.5
41.67
20
Max
⎯
ns
ns
ns
ns
fCP = 16 MHz
Cycle time
tCYC
⎯
⎯
⎯
fCP = 24 MHz
fCP = 16 MHz
fCP = 24 MHz
⎯
CLK ↑ → CLK ↓
tCHCL
13
⎯
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
DS07-13748-5E
47
MB90860E Series
(5) Bus Timing (Read)
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Sym-
Parameter
bol
Pin
Condition
Unit
Min
Max
ALE pulse width
tLHLL ALE
tCP/2 − 10
⎯
ns
ns
ns
ns
ALE, A23 to A16,
AD15 to AD00
Valid address → ALE ↓ time
ALE ↓ → Address valid time
Valid address → RD ↓ time
tAVLL
tCP/2 − 20
tCP/2 − 15
tCP − 15
⎯
⎯
⎯
tLLAX ALE, AD15 to AD00
A23 to A16,
tAVRL
AD15 to AD00, RD
A23 to A16,
AD15 to AD00
Valid address → Valid data input tAVDV
⎯
5 tCP/2 − 60
ns
RD pulse width
tRLRH RD
3 tCP/2 − 20
⎯
⎯
ns
ns
ns
ns
ns
⎯
RD ↓ → Valid data input
RD ↑ → Data hold time
RD ↑ → ALE ↑ time
tRLDV RD, AD15 to AD00
tRHDX RD, AD15 to AD00
tRHLH RD, ALE
3 tCP/2 − 50
0
⎯
⎯
⎯
tCP/2 − 15
tCP/2 − 10
RD ↑ → Address valid time
tRHAX RD, A23 to A16
A23 to A16,
tAVCH
Valid address → CLK ↑ time
tCP/2 − 16
⎯
ns
AD15 to AD00, CLK
RD ↓ → CLK ↑ time
ALE ↓ → RD ↓ time
tRLCH RD, CLK
tLLRL ALE, RD
tCP/2 − 15
tCP/2 − 15
⎯
⎯
ns
ns
tRLCH
tAVCH
2.4 V
2.4 V
CLK
ALE
RD
tLLAX
tAVLL
tRHLH
2.4 V
2.4 V
0.8 V
2.4 V
tLHLL
tAVRL
tRLRH
2.4 V
0.8 V
tLLRL
tRHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tRLDV
tRHDX
tAVDV
2.4 V
0.8 V
VIH
VIL
2.4 V
0.8 V
VIH
VIL
AD15 to AD00
Address
Read data
48
DS07-13748-5E
MB90860E Series
(6) Bus Timing (Write)
Parameter
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Symbol
Pin
Condition
Unit
Min
Max
A23 to A16,
AD15 to AD00,
WR
Valid address → WR ↓ time
tAVWL
tCP−15
⎯
ns
WR pulse width
tWLWH
tDVWH
WR
3 tCP/2 − 20
3 tCP/2 − 20
⎯
⎯
ns
ns
AD15 to AD00,
WR
Valid data output → WR ↑ time
⎯
AD15 to AD00,
WR
WR ↑ → Data hold time
tWHDX
15
⎯
ns
WR ↑ → Address valid time
WR ↑ → ALE ↑ time
tWHAX
tWHLH
tWLCH
A23 to A16, WR
WR, ALE
tCP/2 − 10
tCP/2 − 15
tCP/2 − 15
⎯
⎯
⎯
ns
ns
ns
WR ↓ → CLK ↑ time
WR, CLK
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tDVWH
tWHDX
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
AD15 to AD00
Address
Write data
DS07-13748-5E
49
MB90860E Series
(7) Ready Input Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Rated Value
Sym-
Parameter
bol
Pin
Condition
Units
Remarks
Min
45
32
0
Max
⎯
ns fCP = 16 MHz
ns fCP = 24 MHz
ns
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
⎯
⎯
⎯
Note : If the RDY setup time is insufficient, use the auto-ready function.
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHH
VIH
VIH
RDY
When WAIT is not used.
RDY
VIL
When WAIT is used.
50
DS07-13748-5E
MB90860E Series
(8) Hold Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Parameter
Symbol
Pin
Condition
Units
Min
30
Max
tCP
Pin floating → HAK ↓ time
HAK ↑ time → Pin valid time
tXHAL
tHAHV
HAK
HAK
ns
ns
⎯
tCP
2 tCP
Note : It takes at least one machine clock cycle from when an HRQ is accepted until HAK changes.
2.4 V
HAK
0.8 V
tHAHV
tXHAL
High-Z
2.4 V
0.8 V
2.4 V
0.8 V
Each pin
DS07-13748-5E
51
MB90860E Series
(9) LIN-UART0/1/2/3
• Bit setting: ESCR:SCES = 0, ECCR:SCDE = 0
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
tIVSHI
tSHIXI
SCK0 to SCK3
5 tCP
⎯
ns
ns
SCK0 to SCK3
SOT0 to SOT3
SCK ↓ → SOT delay time
−50
+50
⎯
Internal shift clock
mode output pins are
CL = 80 pF + 1 TTL.
SCK0 to SCK3
SIN0 to SIN3
Valid SIN → SCK ↑
tCP + 80
0
ns
ns
SCK0 to SCK3
SIN0 to SIN3
SCK ↑ → Valid SIN hold time
⎯
Serial clock “L” pulse width
Serial clock “H” pulse width
tSHSL
tSLSH
SCK0 to SCK3
SCK0 to SCK3
3 tCP - tR
tCP + 10
⎯
⎯
ns
ns
SCK0 to SCK3
SOT0 to SOT3
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLOVE
tIVSHE
tSHIXE
⎯
30
2 tCP + 60 ns
External shift clock
mode output pins are
CL = 80 pF + 1 TTL.
SCK0 to SCK3
SIN0 to SIN3
⎯
⎯
ns
ns
SCK0, SCK1,
SIN0 to SIN3
SCK ↑ → Valid SIN hold time
tCP + 30
SCK fall time
SCK rise time
tF
tR
SCK0 to SCK3
SCK0 to SCK3
⎯
⎯
10
10
ns
ns
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK0 to SCK3
0.8 V
0.8 V
tSLOVI
2.4 V
0.8 V
SOT0 to SOT3
SIN0 to SIN3
tIVSHI
tSHIXI
VIH
VIL
VIH
VIL
52
DS07-13748-5E
MB90860E Series
• External Shift Clock Mode
t
SLSH
t
SHSL
VIH
VIH
SCK0 to SCK3
VIL
VIL
tSLOVE
tF
t
R
2.4 V
0.8 V
SOT0 to SOT3
SIN0 to SIN3
t
IVSHE
tSHIXE
V
V
IH
IL
V
IH
IL
V
• Bit setting: ESCR:SCES = 1, ECCR:SCDE = 0
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK3
5 tCP
⎯
ns
ns
SCK0 to SCK3
SOT0 to SOT3
SCK ↑ → SOT delay time
tSHOVI
−50
tCP + 80
0
+50
⎯
Internal shift clock
mode output pins are
CL = 80 pF + 1 TTL.
SCK0 to SCK3
SIN0 to SIN3
Valid SIN → SCK ↓
tIVSLI
tSLIXI
ns
ns
SCK0 to SCK3
SIN0 to SIN3
SCK ↓ → Valid SIN hold time
⎯
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
SCK0 to SCK3
SCK0 to SCK3
3 tCP - tR
tCP + 10
⎯
⎯
ns
ns
SCK0 to SCK3
SOT0 to SOT3
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
tSHOVE
tIVSLE
tSLIXE
⎯
30
2 tCP + 60
ns
ns
ns
External shift clock
mode output pins are
CL = 80 pF + 1 TTL.
SCK0 to SCK3
SIN0 to SIN3
⎯
⎯
SCK0 to SCK3
SIN0 to SIN3
SCK ↓ → Valid SIN hold time
tCP + 30
SCK fall time
SCK rise time
tF
SCK0 to SCK3
SCK0 to SCK3
⎯
⎯
10
10
ns
ns
tR
Notes : • CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
DS07-13748-5E
53
MB90860E Series
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK0 to SCK3
SOT0 to SOT3
0.8 V
t
SHOVI
2.4 V
0.8 V
t
IVSLI
t
SLIXI
V
V
IH
IL
V
IH
IL
SIN0 to SIN3
V
• External Shift Clock Mode
t
SHSL
t
SLSH
V
IH
V
IH
SCK0 to SCK3
V
IL
VIL
t
SHOVE
t
R
t
F
2.4 V
0.8 V
SOT0 to SOT3
SIN0 to SIN3
t
IVSLE
tSLIXE
V
V
IH
IL
V
V
IH
IL
54
DS07-13748-5E
MB90860E Series
• Bit setting: ESCR:SCES = 0, ECCR:SCDE = 1
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK3
5 tCP
⎯
ns
ns
SCK0 to SCK3
SOT0 to SOT3
SCK ↑ → SOT delay time
tSHOVI
−50
tCP + 80
0
+50
⎯
SCK0 to SCK3 Internal clock operation
SIN0 to SIN3 output pins are
Valid SIN → SCK ↓
tIVSLI
tSLIXI
tSOVLI
ns
ns
ns
C = 80 pF + 1 TTL.
L
SCK0 to SCK3
SIN0 to SIN3
SCK ↓ → Valid SIN hold time
SOT → SCK ↓ delay time
⎯
SCK0 to SCK3
SOT0 to SOT3
3 tCP − 70
⎯
Notes : • CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
tSCYC
2.4 V
SCK0 to SCK3
0.8 V
0.8 V
tSHOVI
tSOVLI
2.4 V
0.8 V
2.4 V
0.8 V
SOT0 to SOT3
SIN0 to SIN3
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
DS07-13748-5E
55
MB90860E Series
• Bit setting: ESCR:SCES = 1, ECCR:SCDE = 1
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
SCK0 to SCK3
5 tCP
⎯
ns
ns
SCK0 to SCK3
SOT0 to SOT3
SCK ↓ → SOT delay time
−50
+50
⎯
SCK0 to SCK3 Internalclockoperation
SIN0 to SIN3 output pins are
Valid SIN → SCK ↑
tIVSHI
tSHIXI
tSOVHI
tCP + 80
0
ns
ns
ns
C = 80 pF + 1 TTL.
L
SCK0 to SCK3
SIN0 to SIN3
SCK ↑ → Valid SIN hold time
SOT → SCK ↑ delay time
⎯
SCK0 to SCK3
SOT0 to SOT3
3 tCP − 70
⎯
Notes : • CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
t
SCYC
2.4 V
2.4 V
SCK0 to SCK3
SOT0 to SOT3
0.8 V
t
SLOVI
t
SOVHI
2.4 V
2.4 V
0.8 V
0.8 V
t
IVSHI
tSHIXI
V
V
IH
IL
V
V
IH
IL
SIN0 to SIN3
56
DS07-13748-5E
MB90860E Series
(10) Trigger Input Timing
Parameter
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Symbol
Pin
Condition
Unit
Min
Max
INT0 to INT15,
INT8R to INT15R,
ADTG
tTRGH
tTRGL
Input pulse width
⎯
5 tCP
⎯
ns
VIH
VIH
INT0 to INT15,
INT8R to INT15R,
ADTG
VIL
VIL
tTRGH
tTRGL
DS07-13748-5E
57
MB90860E Series
(11) Timer Related Resource Input Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
tTIWH
tTIWL
TIN0 to TIN3,
IN0 to IN7
Input pulse width
⎯
4 tCP
⎯
ns
VIH
VIH
VIL
VIL
TIN0 to TIN3,
IN0 to IN7
tTIWH
tTIWL
(12) Timer Related Resource Output Timing
(TA = –40°C to +105°C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0.0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
TOT0 to TOT3,
PPG0 to PPGF
CLK ↑ → TOUT change time
tTO
⎯
30
⎯
ns
2.4 V
CLK
2.4 V
0.8 V
TOT0 to TOT3,
PPG0 to PPGF
tTO
58
DS07-13748-5E
MB90860E Series
(13) I2C Timing
(TA = –40°C to +105°C, VCC = 5.0 V 10%, VSS = 0.0 V)
Fast-mode*1
Standard-mode
Parameter
Symbol
Condition
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDA ↓ → SCL ↓
tHDSTA
4.0
⎯
0.6
⎯
µs
“L” width of the SCL clock
“H” width of the SCL clock
tLOW
tHIGH
4.7
4.0
⎯
⎯
1.3
0.6
⎯
⎯
µs
µs
Set-up time for a repeated START condition
SCL ↑ → SDA ↓
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUS
4.7
0
⎯
3.45*3
⎯
0.6
0
⎯
0.9*4
⎯
µs
µs
ns
µs
µs
R = 1.7 kΩ,
C = 50 pF*2
Data hold time
SCL ↓ → SDA ↓ ↑
Data set-up time
SDA ↓ ↑ → SCL ↑
250
4.0
4.7
100
0.6
1.3
Set-up time for STOP condition
SCL ↑ → SDA ↑
⎯
⎯
Bus free time between a STOP and START
condition
⎯
⎯
*1 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
*2 : R,C : Pull-up resistance and load capacitance of the SCL and SDA lines.
*3 : The maximum tHDDAT must be satisfied if the device does not extend the “L” width (tLOW) of the SCL signal.
*4 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
SDA
tBUS
tSUDAT
tHDSTA
tLOW
SCL
tHIGH
tHDSTA
tHDDAT
tSUSTA
tSUSTO
DS07-13748-5E
59
MB90860E Series
5. A/D Converter
(TA
= −40 °C to +105 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
⎯
Typ
⎯
Max
10
Resolution
⎯
⎯
⎯
⎯
⎯
⎯
bit
Total error
⎯
⎯
3.0
2.5
LSB
LSB
Nonlinearity error
⎯
⎯
Differential
nonlinearity error
⎯
⎯
⎯
⎯
1.9
LSB
V
Zero reading
voltage
AVRL −
1.5 × LSB
AVRL +
0.5 × LSB
AVRL +
2.5 × LSB
VOT
VFST
AN0 to AN23
AN0 to AN23
Full scale reading
voltage
AVRH −
3.5 × LSB
AVRH −
1.5 × LSB
AVRH +
0.5 × LSB
V
1.0
2.0
0.5
1.2
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
Compare time
Sampling time
⎯
⎯
⎯
⎯
⎯
⎯
16500
µs
µs
∞
Analog port input
current
IAIN
AN0 to AN23
AN0 to AN23
−0.3
⎯
⎯
+0.3
µA
Analog input
voltage
VAIN
AVRL
AVRH
V
⎯
⎯
IA
AVRH
AVRL
AVCC
AVRL + 2.7
⎯
⎯
AVCC
V
V
Reference
voltage
0
AVRH − 2.7
⎯
⎯
⎯
⎯
3.5
⎯
7.5
5
mA
µA
µA
µA
Power supply
current
IAH
IR
AVCC
*
*
AVRH
AVRH
600
⎯
900
5
Reference
voltage current
IRH
Variationbetween
input channels
⎯
AN0 to AN23
⎯
⎯
4
LSB
* : This is the current when the A/D converter is not being operated, and the CPU is stopped (VCC = AVCC = AVRH
= 5.0 V) .
Note : The relative error increases as AVRH − AVRL becomes smaller.
60
DS07-13748-5E
MB90860E Series
6. Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Non linearity
error
: Deviation of the actual conversion characteristics from a line that connects the zero transition
point ( “00 0000 0000” ← → “00 0000 0001” ) to the full-scale transition point ( “11 1111 1110”
← → “11 1111 1111” ) .
Differential
linearity error
: Deviation from the ideal value of the input voltage required to change the output code by
LSB.
Total error
: Difference between the actual value and the ideal value. The total error includes zero transi-
tion error, full-scale transition error, and linear error.
Total error
3FFH
1.5 LSB
3FEH
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
001H
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
Total error of digital output “N” =
1 LSB (Ideal value) =
1 LSB
AVRH − AVRL
[V]
1024
N : A/D converter digital output value
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : The voltage at which the digital output changes from (N − 1) H to NH.
(Continued)
DS07-13748-5E
61
MB90860E Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FF
3FE
3FD
H
H
H
Actual conversion
characteristics
N + 1
H
H
H
H
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT
}
V
FST (actual
measurement
value)
N
V
NT (actual
measurement value)
004
003
002
001
H
H
H
H
V
(N + 1) T
(actual measurement
Actual conversion
characteristics
N − 1
N − 2
value)
V
NT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
V
OT (actual measurement value)
Analog input
AVRL
AVRH
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
Non linearity error of digital output N =
1 LSB
V (N+1) T − VNT
−1 LSB [LSB]
1 LSB
Differential linearity error of digital output N =
VFST − VOT
[V]
1 LSB =
1022
N : A/D converter digital output value
VOT : The voltage at which the digital output changes from “000H” to “001H.”
VFST : The voltage at which the digital output changes from “3FEH” to “3FFH.”
62
DS07-13748-5E
MB90860E Series
7. Notes on A/D Converter Unit
Use the device such that the output impedance of the external circuits attached to the analog inputs satisfy the
following conditions.
• It is recommended that the output impedance of external circuits are approx. 1.5 kΩ or lower
(4.0 V ≤ AVCC ≤ 5.5 V, sampling period = 0.5 µs)
• If an external capacitor is used, in consideration of the capacitive voltage division effect between the external
capacitor and the internal on-chip capacitor, it is recommended that the capacitance of the external capacitor
is several thousand times greater than the internal capacitor.
• If the output impedance of the external circuit is too high, the sampling period for the analog voltage may be
insufficient.
• Analog input circuit model
R
Analog input
Comparator
C
4.5 V ≤ AVCC ≤ 5.5 V : R=: 2.52 kΩ, C=: 10.7 pF
4.0 V ≤ AVCC < 4.5 V : R=: 13.6 kΩ, C=: 10.7 pF
Note : The values shown in this figure are reference values.
8. Flash Memory Program/Erase Characteristics
Value
Parameter
Conditions
Unit
Remarks
Min
Typ
Max
Excludes programming
prior to erasure
Sector erase time
Chip erase time
⎯
1
15
s
s
TA = +25 °C
VCC = 5.0 V
Excludes programming
prior to erasure
⎯
⎯
9
⎯
3600
⎯
Word (16-bit width)
programming time
Except for the over head
time of the system
16
⎯
⎯
µs
Number of program/
erase cycles
⎯
10000
20
cycle
Year
Average
TA = +85 °C
Flash data retention time
⎯
*
* : This value is the result of evaluating the reliability of the technology (using Arrhenius equation to translate high
temperature measurements into normalized value at +85 °C) .
DS07-13748-5E
63
MB90860E Series
■ EXAMPLE CHARACTERISTICS
• MB90F867E, MB90F867ES
ICC − VCC
ICCL − VCC
TA = +25 °C, operating on external clock
TA = +25 °C, operating on external clock
f = Internal operation frequency
f = Internal operation frequency
100
90
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 8 kHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICCS − VCC
ICCLS − VCC
TA = +25 °C, operating on external clock
f = Internal operation frequency
TA = +25 °C, operating on external clock
f = Internal operation frequency
35
50
45
40
35
30
25
20
15
10
5
30
25
20
15
10
5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 8 kHz
f = 4 MHz
f = 2 MHz
0
0
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
VCC (V)
5.5
6.5
ICTS − VCC
ICCT − VCC
TA = +25 °C, operating on external clock
f = Internal operation frequency
TA = +25 °C, operating on external clock
f = Internal operation frequency
400
350
300
250
200
150
100
50
20
18
16
14
12
10
8
6
4
2
0
f = 2 MHz
f = 8 kHz
0
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
VCC (V)
5.5
6.5
ICTSPLL6 − VCC
ICCH − VCC
TA = +25 °C, operating on external clock
f = Internal operation frequency
TA = +25 °C, when stopped
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
f = 24 MHz
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
VCC (V)
5.5
6.5
64
DS07-13748-5E
MB90860E Series
• MB90867E, MB90867ES
ICC − VCC
TA = +25 °C, operating on external clock
f = Internal operation frequency
ICCL − VCC
TA = +25 °C, operating on external clock
f = Internal operation frequency
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 8 kHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
2.5
2.5
2.5
3.5
3.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
3.5
3.5
3.5
4.5
VCC (V)
5.5
6.5
ICCS − VCC
ICCLS − VCC
TA = +25 °C, operating on external clock
f = Internal operation frequency
TA = +25 °C, operating on external clock
f = Internal operation frequency
50
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 8 kHz
f = 4 MHz
f = 2 MHz
0
0
2.5
4.5
VCC (V)
5.5
6.5
4.5
5.5
6.5
VCC (V)
ICTS − VCC
ICCT − VCC
TA = +25 °C, operating on external clock
f = Internal operation frequency
TA = +25 °C, operating on external clock
f = Internal operation frequency
20
18
16
14
12
10
8
6
4
2
0
400
350
300
250
200
150
100
50
f = 2 MHz
f = 8 kHz
0
2.5
4.5
VCC (V)
5.5
6.5
4.5
VCC (V)
5.5
6.5
ICTSPLL6 − VCC
ICCH − VCC
TA = +25 °C, operating on external clock
f = Internal operation frequency
TA = +25 °C, when stopped
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
f = 24 MHz
2.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
DS07-13748-5E
65
MB90860E Series
• I/O characteristics
(VCC−VOH) − IOH
VOL − IOL
TA = +25 °C, VCC = 4.5 V
TA = +25 °C, VCC = 4.5 V
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
IOH (mA)
Automotive VIN − VCC
CMOS VIN − VCC
UART-SIN pin, other than I2C pin
TA = +25 °C
TA = +25 °C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
VIHA
VILA
VIHS
VILS
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VCC (V)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VCC (V)
TTL VIN − VCC
CMOS VIN − VCC
UART-SIN pin, I2C pin
TA = +25 °C
TA = +25 °C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5
2.3
2.0
1.8
1.5
1.3
1.0
0.8
0.5
0.3
0.0
VIHS
VILS
VIHT
VILT
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VCC (V)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VCC (V)
66
DS07-13748-5E
MB90860E Series
■ ORDERING INFORMATION
Part number
MB90F867EPF
Package
Remarks
100-pin plastic QFP
(FPT-100P-M06)
MB90F867ESPF
MB90F867EPMC
MB90F867ESPMC
MB90867EPF
Flash memory product
100-pin plastic LQFP
(FPT-100P-M20)
100-pin plastic QFP
(FPT-100P-M06)
MB90867ESPF
MASK ROM product
Evaluation product
MB90867EPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90867ESPMC
MB90V340E-101CR
MB90V340E-102CR
299-pin ceramic PGA
(PGA-299C-A01)
DS07-13748-5E
67
MB90860E Series
■ PACKAGE DIMENSIONS
100-pin plastic QFP
Lead pitch
0.65 mm
14.00 × 20.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
P-QFP100-14×20-0.65
Code
(Reference)
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90 0.40(.941 .016)
*
20.00 0.20(.787 .008)
80
51
81
50
0.10(.004)
17.90 0.40
(.705 .016)
*
14.00 0.20
(.551 .008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 +–00..2305
.118 +–..000184
(Mounting height)
0~8
˚
1
30
0.65(.026)
0.32 0.05
(.013 .002)
0.17 0.06
(.007 .002)
M
0.13(.005)
0.25 0.20
(.010 .008)
(Stand off)
0.80 0.20
(.031 .008)
"A"
0.88 0.15
(.035 .006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2002-2008 FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6
2002 FUJITSU LIMITED F100008S-c-5-5
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
68
DS07-13748-5E
MB90860E Series
(Continued)
100-pin plastic LQFP
Lead pitch
0.50 mm
14.0 mm × 14.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00 0.20(.630 .008)SQ
*
14.00 0.10(.551 .004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +0.20
–
0.10 .059 +.008
–.004
INDEX
(Mounting height)
0.10 0.10
(.004 .004)
(Stand off)
100
26
0°~8
°
"A"
0.50 0.20
(.020 .008
0.25(.010)
)
1
25
0.60 0.15
(.024 .006)
0.50(.020)
0.20 0.05
(.008 .002)
0.145 0.055
(.0057 .0022)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2005 -2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-3-3
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13748-5E
69
MB90860E Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
Changed the package.
FPT-100P-M05 → FPT-100P-M20
⎯
⎯
■ ELECTRICAL CHARACTERISTICS Changed the items for “Zero reading voltage” and “Full scale
60
67
69
5. A/D Converter
reading voltage”.
■ ORDERING INFORMATION
Changed the part numbers;
MB90867EPFV → MB90367EPMC
MB90867ESPFV → MB90867ESPMC
MB90F867EPFV → MB90F867EPMC
MB90F867ESPFV → MB90F867ESPMC
MB90V340E-101 → MB90V340E-101CR
MB90V340E-102 → MB90V340E-102CR
■ PACKAGE DIMENSIONS
Changed the package's figure.
FPT-100P-M05 → FPT-100P-M20
The vertical lines marked in the left side of the page show the changes.
70
DS07-13748-5E
MB90860E Series
MEMO
DS07-13748-5E
71
MB90860E Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE LTD.
151 Lorong Chuan, #05-08 New Tech Park,
Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm.3102, Bund Center, No.222 Yan An Road(E),
Shanghai 200002, China
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen,
Germany
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-
ing the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited Business & Media Promotion Dept.
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