MB90F952MDPFV [SPANSION]
Microcontroller, 16-Bit, FLASH, 32MHz, CMOS, PQFP100, 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-100;
| 型号： | MB90F952MDPFV |
| 厂家： | 
SPANSION |
| 描述： | Microcontroller, 16-Bit, FLASH, 32MHz, CMOS, PQFP100, 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-100 时钟 微控制器 外围集成电路 |
| 文件： | 总88页 (文件大小：2708K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13752-2E
16-bit Microcontroller
CMOS
F2MC-16LX MB90950 Series
MB90F952JD(S)/F952MD(S)/
MB90V950JA(S)/V950MA(S)
■ DESCRIPTION
The MB90950-series with up to 2 FULL-CAN* interfaces and Flash ROM is especially designed for automotive
and other industrial applications. Its main feature are the on-board CAN Interfaces, which conform to V2.0 Part
A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a
normal FULL-CAN approach. With the new 0.18 µm CMOS technology, Fujitsu now offers on-chip Flash ROM
program memory up to 512 Kbytes.
The power to the MCU core (1.8 V) is supplied by a built-in regulator circuit, giving these microcontrollers superior
performance in terms of power consumption and tolerance to EMI.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.11
MB90950 Series
■ FEATURES
• CPU
• Instruction system best suited to controller
- Wide choice of data types (bit, byte, word, and long word)
- Wide choice of addressing modes (23 types)
- Enhanced functionality with signed multiply and divide instructions and the RETI instruction
- Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
- Employing system stack pointer
- Various enhanced pointer indirect instructions
- Barrel shift instructions
• Increased processing speed
4-byte instruction queue
• Serial interface
• UART (LIN/SCI) : up to 7 channels
- Equipped with full-duplex double buffer
- Clock-asynchronous or clock-synchronous serial transmission is available
• I2C interface : up to 2 channels
Up to 400 kbps transfer rate
• Interrupt controller
• Powerful 8-level, 34-condition interrupt feature
• Up to 16 external interrupts are supported
• Automatic data transfer function independent of CPU
Expanded intelligent I/O service function (EI2OS) : up to 16 channels
• I/O ports
• General-purpose input/output port (CMOS output)
- 80 ports (for devices without an S suffix in the part number - i.e. devices that support the sub clock)
- 82 ports (for devices with an S suffix in the part number - i.e. devices that do not support the sub clock)
• 8/10-bit A/D converter : 24 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 µs (at 32-MHz machine clock, including sampling time)
• 8-bit D/A converter : 2 channels
• Program patch function
Detects address matches against 6 address pointers
• Timer
• Time-base timer, watch timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 16 channels, or 16-bit × 8 channels
• 16-bit reload timer : 4 channels
• 16-bit input/output timer
- 16-bit free-run timer : 2 channels
(FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16-bit input capture: (ICU): 8 channels
- 16-bit output compare: (OCU): 8 channels
2
DS07-13752-2E
MB90950 Series
• FULL-CAN controller*
• Up to 2 channels
• Compliant with Ver2.0A and Ver2.0B CAN specifications
• 16 built-in message buffers
• CAN wake-up function
• Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Timebase timer mode (a mode where only the oscillation clock, sub clock, timebase timer and watch timer
operate)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU intermittent operation mode
• Technology
0.18 µm CMOS technology
* : Controller Area Network (CAN) - License of Robert Bosch GmbH.
DS07-13752-2E
3
MB90950 Series
■ PRODUCT LINEUP
Part Number
MB90V950JA(S),
MB90F952JD(S)
MB90F952MD(S)
MB90V950MA(S)
Parameter
Type
Evaluation products
Flash memory products
F2MC-16LX CPU
CPU
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, ×8, 1/2 when PLL stops)
Minimum instruction execution time : 31.25 ns (4 MHz osc. PLL × 8)
System clock
ROM
RAM
External
256 Kbytes
16 Kbytes
30 Kbytes
Emulator-specific
power supply*1
Yes
⎯
FPGA data*2
Adaptor board*2
Rev 050617
⎯
⎯
MB2147-20 Rev.04C or later
MB90V950JA(S) only
Clock supervisor
Yes
Yes
No
No
Clock calibration
unit
MB90V950JA(S) only
No
Low-voltage/CPU
operation detection
reset
(MB90V590JA(S):
CPU operation detection
reset only)
Yes
No
0.18 µm CMOS with built-in power supply regulator +
Flash memory with Charge pump for
programming voltage
0.35 µm CMOS with built-in
power supply regulator
Technology
3.0 V to 5.5 V : When normal operating
4.0 V to 5.5 V : When Flash programming
4.5 V to 5.5 V : When using the external bus
Operating
voltage range
5 V 10%
Operating ambient
temperature
⎯
−40 °C to +105 °C
Package
PGA-299
QFP-100, LQFP-100
7 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
UART
I2C (400 kbps)
A/D Converter
2 channels
24 input channels
10-bit or 8-bit resolution
Conversion time : Min 3 µs include sample time (per one channel)
16-bit Reload Timer Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
(4 channels) Supports External Event Count function
(Continued)
4
DS07-13752-2E
MB90950 Series
Part Number
Parameter
MB90V950JA(S),
MB90V950MA(S)
MB90F952JD(S)
MB90F952MD(S)
Generates an interrupt signal on overflow
Supports Timer Clear when the output compare finds a match
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU 4/5/6/7
16-bit I/O Timer
(2 channels)
16-bit Output
Compare
Generates an interrupt signal when one of the 16-bit I/O timer matches the output compare
register
(8 channels)
A pair of compare registers can be used to generate an output signal.
16-bit Input Capture Holds free-run timer on rising edge, falling edge or rising & falling edge
(8 channels)
Signals an interrupt upon external event
8 channels (16-bit) /16 channels (8-bit)
Sixteen 8-bit reload counters
Sixteen 8-bit reload registers for L pulse width
8/16-bit
Sixteen 8-bit reload registers for H pulse width
Programmable
Pulse Generator
Supports 8-bit and 16-bit operation modes
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
Operating clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
3 channels
2 channels
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission in response to Remote Frames
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
CAN Interface
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
External Interrupt
(16 channels)
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded intelligent I/O services (EI2OS) and DMA
D/A converter
2 channels
Devices with sub clock : devices without an S suffix in the
Sub clock
Only for MB90V950JA,
part number
(maximum 100 kHz) MB90V950MA
Devices without sub clock : devices with an S suffix in the
part number
Virtually all external pins can be used as general purpose I/O port
All ports are push-pull outputs
I/O Ports
Bit-wise settable as input/output or peripheral signal
Can be configured 8 as CMOS schmitt trigger/ automotive inputs (in blocks of 8 pins)
TTL input level settable for external bus (32-pin only for external bus)
(Continued)
DS07-13752-2E
5
MB90950 Series
(Continued)
Part Number
MB90V950JA(S),
MB90V950MA(S)
MB90F952JD(S)
MB90F952MD(S)
Parameter
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10000 cycles
Data retention time : 20 years
Flash Memory
⎯
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the
Flash
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual for details.
*2 : Customers considering the use of other FPGA data and the adaptor boards should consult with sales repre-
sentatives.
6
DS07-13752-2E
MB90950 Series
■ PIN ASSIGNMENTS
• MB90F952JD(S), MB90F952MD(S)
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
QFP - 100
Vss
X1
X0
P15/AD13/SIN4
P16/AD14/SOT4
P17/AD15/SCK4
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
AVss
AVRL
AVRH
AVcc
P57/AN15/DA1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(FPT-100P-M06)
* : X0A, X1A : devices without an S suffix in the part number
P40, P41 : devices with an S suffix in the part number
(Continued)
DS07-13752-2E
7
MB90950 Series
(Continued)
(TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MD1
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
MD2
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
LQFP - 100
Vss
X1
X0
P15/AD13/SIN4
P16/AD14/SOT4
P17/AD15/SCK4
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
AVRL
AVRH
AVcc
P57/AN15/DA1
P56/AN14/DA0
P55/AN13
P25/A21/IN1
P54/AN12/TOT3
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
(FPT-100P-M20)
* : X0A, X1A : devices without an S suffix in the part number
P40, P41 : devices with an S suffix in the part number
8
DS07-13752-2E
MB90950 Series
■ PIN DESCRIPTION
Pin No.
I/O
Pin name
Circuit
Function
LQFP100*1
QFP100*2
type*3
90
91
52
92
93
54
X1
X0
Oscillation output pin
Oscillation input pin
Reset input
A
E
RST
General purpose I/O port
P00 to P07
The register can be set to select whether to use a pull-
up resistor. This function is enabled in single-chip mode.
AD00
to
AD07
I/O pins for 8 lower bits of the external address/data bus.
This function is enabled when the external bus is
enabled.
75 to 82
77 to 84
G
INT8
to
External interrupt request input pins for INT8 to INT15.
INT15
General purpose I/O port
P10
The register can be set to select whether to use a pull-
up resistor. This function is enabled in single-chip mode.
83
84
85
86
G
G
I/O pin of the external address/data bus (AD08). This
function is enabled when the external bus is enabled.
AD08
TIN1
Event input pin for the reload timer1
General purpose I/O port
The register can be set to select whether to use a pull-
up resistor. This function is enabled in single-chip mode.
P11
I/O pin of the external address/data bus (AD09). This
function is enabled when the external bus is enabled.
AD09
TOT1
Output pin for the reload timer1
General purpose I/O port
P12
The register can be set to select whether to use a pull-
up resistor. This function is enabled in single-chip mode.
I/O pin of the external address/data bus (AD10). This
function is enabled when the external bus is enabled.
85
86
87
88
N
G
AD10
SIN3
Serial data input pin for UART3
INT11R
External interrupt request input pin (Sub) for INT11
General purpose I/O port
The register can be set to select whether to use a pull-
up resistor. This function is enabled in single-chip mode.
P13
I/O pin of the external address/data bus (AD11). This
function is enabled when the external bus is enabled.
AD11
SOT3
Serial data output pin for UART3
(Continued)
DS07-13752-2E
9
MB90950 Series
Pin No.
I/O
Circuit
Pin name
Function
General purpose I/O port
LQFP100*1
QFP100*2
type*3
P14
The register can be set to select whether to use a pull-
up resistor. This function is enabled in single-chip mode.
87
89
G
N
G
G
I/O pin of the external address/data bus (AD12). This
function is enabled when the external bus is enabled.
AD12
SCK3
Clock I/O pin for UART3
General purpose I/O port
The register can be set to select whether to use a pull-
up resistor. This function is enabled in single-chip mode.
P15
92
93
94
94
95
96
I/O pin of the external address/data bus (AD13). This
function is enabled when the external bus is enabled.
AD13
SIN4
Serial data input pin for UART4
General purpose I/O port
The register can be set to select whether to use a pull-
up resistor. This function is enabled in single-chip mode.
P16
I/O pin of the external address/data bus (AD14). This
function is enabled when the external bus is enabled.
AD14
SOT4
Serial data output pin for UART4
General purpose I/O port
The register can be set to select whether to use a pull-
up resistor. This function is enabled in single-chip mode.
P17
I/O pin of the external address/data bus (AD15). This
function is enabled when the external bus is enabled.
AD15
SCK4
Clock I/O pin for UART4
General purpose I/O ports
The register can be set to select whether to use a pull-
up resistor.In external bus mode, the pin is enabled as a
general-purpose I/O port when the corresponding bit in
the external address output control register (HACR) is 1.
P20 to P23
A16 to A19 for output pins of the external address/data
bus. When the corresponding bit in the external address
output control register (HACR) is 0, the pins are enabled
as high address output pins (A16 to A19).
95 to 98
97 to 100
G
A16 to A19
PPG9,
PPGB,
PPGD,
PPGF
Output pins for PPGs
(Continued)
10
DS07-13752-2E
MB90950 Series
Pin No.
I/O
Circuit
Pin name
Function
LQFP100*1
QFP100*2
type*3
General purpose I/O ports
The register can be set to select whether to use a pull-up
resistor. In external bus mode, the pin is enabled as a
general-purpose I/O port when the corresponding bit in the
external address output control register (HACR) is 1.
P24 to P27
99, 100, 1, 2
1 to 4
G
A20 to A23 for output pins of the external address/data
bus. When the corresponding bit in the external address
output control register (HACR) is 0, the pins are enabled as
high address output pins (A20 to A23).
A20 to A23
IN0 to IN3
P30
Data sample input pins for input capture ICU0 to ICU3.
General purpose I/O port
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
3
4
5
6
G
G
Address latch enable output pin. This function is enabled
when the external bus is enabled.
ALE
IN4
Data sample input pin for input capture ICU4.
General purpose I/O port
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
P31
External read strobe output pin for data bus. This function
is enabled when the external bus is enabled.
RD
IN5
Data sample input pin for input capture ICU5.
General purpose I/O port
The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode
or when the WR/WRL pin output is disabled.
P32
Write strobe output pin for the external data bus. This
function is enabled when both the external bus and the
WR/WRL pin output are enabled. WRL is used to
write-strobe 8 lower bits of the data bus in 16-bit access
while WR is used to write-strobe 8 bits of the data bus in
8-bit access.
5
7
G
WRL/
WR
INT10R
P33
External interrupt request input pin (Sub) for INT10.
General purpose I/O port
The register can be set to select whether to use a pull-up resistor.
This function is enabled either in single-chip mode or when
the WRH pin output is disabled.
6
8
G
Write strobe output pin for the upper 8 bits of the external
data bus. This function is enabled when the external bus is
enabled, when the external bus 16-bit mode is selected,
and when the WRH output pin is enabled.
WRH
(Continued)
DS07-13752-2E
11
MB90950 Series
Pin No.
I/O
Circuit
Pin name
Function
General purpose I/O port
LQFP100*1
QFP100*2
type*3
The register can be set to select whether to use a pull-up
resistor.This function is enabled either in single-chip
mode or when the hold function is disabled.
P34
7
9
G
G
Hold request input pin. This function is enabled when both
the external bus and the hold function are enabled.
HRQ
OUT4
Waveform output pin for output compare OCU4.
General purpose I/O port
The register can be set to select whether to use a pull-up
resistor.This function is enabled either in single-chip
mode or when the hold function is disabled.
P35
8
9
10
Hold acknowledge output pin. This function is enabled
when both the external bus and the hold function are
enabled.
HAK
OUT5
Waveform output pin for output compare OCU5.
General purpose I/O port
The register can be set to select whether to use a pull-up resis-
tor. This function is enabled either in single-chip mode or
when the external ready function is disabled.
P36
11
G
G
Ready input pin. This function is enabled when both the
external bus and the external ready function are enabled.
RDY
OUT6
Waveform output pin for output compare OCU6.
General purpose I/O port
The register can be set to select whether to use a pull-up
resistor.This function is enabled either in single-chip
mode or when the clock output is disabled.
P37
10
12
Clock output pin. This function is enabled when both the
external bus and clock output are enabled.
CLK
OUT7
Waveform output pin for output compare OCU7.
General purpose I/O ports
(devices with an S suffix in the part number)
P40, P41
F
B
11, 12
13, 14
Oscillation pins for sub clock
(devices without an S suffix in the part number)
X0A, X1A
P42
IN6
General purpose I/O port
Data sample input pin for input capture ICU6.
RX input pin for CAN1 Interface
16
17
18
19
F
F
RX1
INT9R
P43
External interrupt request input pin (Sub) for INT9.
General purpose I/O port
IN7
Data sample input pin for input capture ICU7.
TX Output pin for CAN1
TX1
(Continued)
12
DS07-13752-2E
MB90950 Series
Pin No.
I/O
Circuit
Pin name
Function
LQFP100*1
QFP100*2
type*3
P44
SDA0
FRCK0
P45
General purpose I/O port
Serial data I/O pin for I2C 0
18
19
20
H
H
Input pin for the 16-bit I/O Timer 0
General purpose I/O port
Serial clock I/O pin for I2C 0
21
SCL0
FRCK1
P46
Input pin for the 16-bit I/O Timer1
General purpose I/O port
Serial data I/O pin for I2C 1
20
21
22
23
H
H
SDA1
P47
General purpose I/O port
Serial clock I/O pin for I2C 1
SCL1
P50
General purpose I/O port
22
23
24
25
24
25
26
27
AN8
O
I
Analog input pin for the A/D converter
Serial data input pin for UART2
General purpose I/O port
SIN2
P51
AN9
Analog input pin for the A/D converter
Serial data output pin for UART2
General purpose I/O port
SOT2
P52
AN10
SCK2
P53
I
Analog input pin for the A/D converter
Clock I/O pin for UART2
General purpose I/O port
AN11
TIN3
I
Analog input pin for the A/D converter
Event input pin for the reload timer3
General purpose I/O port
P54
26
27
28
29
AN12
TOT3
P55
I
I
Analog input pin for the A/D converter
Output pin for the reload timer3
General purpose I/O port
AN13
P56, P57
AN14, AN15
DA0,DA1
Analog input pin for the A/D converter
General purpose I/O ports
28, 29
30, 31
J
Analog input pins for the A/D converter
Analog output pins for the D/A converter
(Continued)
DS07-13752-2E
13
MB90950 Series
Pin No.
I/O
Circuit
Pin name
Function
General purpose I/O ports
LQFP100*1
QFP100*2
type*3
P60 to P67
AN0 to AN7
Analog input pins for the A/D converter
PPG0,
PPG2,
PPG4,
PPG6,
PPG8,
PPGA,
PPGC,
PPGE
34 to 41
36 to 43
I
Output pins for PPGs
P70 to P77
General purpose I/O port
AN16
to
AN23
43 to 48,
53, 54
45 to 50,
55, 56
I
Analog input pins for the A/D converter
INT0 to INT7
P80
External interrupt request input pins for INT0 to INT7
General purpose I/O port
TIN0
Event input pin for the reload timer0
Trigger input pin for the A/D converter
External interrupt request input pin (sub) for INT12
General purpose I/O port
55
56
57
57
58
59
F
F
ADTG
INT12R
P81
TOT0
CKOT
INT13R
P82
Output pin for the reload timer0
Output pin for the clock monitor
External interrupt request input pin (sub) for INT13
General purpose I/O port
SIN0
Serial data input pin for UART0
Event input pin for the reload timer2
External interrupt request input pin (sub) for INT14
General purpose I/O port
M
TIN2
INT14R
P83
58
59
60
61
SOT0
TOT2
P84
F
F
Serial data output pin for UART0
Output pin for the reload timer2
General purpose I/O port
SCK0
INT15R
P85
Clock I/O pin for UART0
External interrupt request input pin (sub) for INT15
General purpose I/O port
60
61
62
63
M
F
SIN1
Serial data input pin for UART1
General purpose I/O port
P86
SOT1
Serial data output pin for UART1
(Continued)
14
DS07-13752-2E
MB90950 Series
Pin No.
I/O
Pin
name
Circuit
Function
LQFP100*1
QFP100*2
type*3
P87
SCK1
P90
General purpose I/O port
62
65
64
F
Clock I/O pin for UART1
General purpose I/O port
Output pin for PPGs
67
68
PPG1
SIN5
P91
M
Serial data input pin for UART5
General purpose I/O port
Output pin for PPGs
66
PPG3
SOT5
P92
F
Serial data output pin for UART5
General purpose I/O port
Output pin for PPGs
67
68
69
70
PPG5
SCK5
P93
F
F
Clock I/O pin for UART5
General purpose I/O port
Output pin for PPGs
PPG7
P94
General purpose I/O port
Waveform output pin for output compare for OCU0. This
function is enabled when the waveform output is enabled.
69
70
71
72
OUT0
M
F
SIN6
P95
Serial data input pin for UART6
General purpose I/O port
Waveform output pin for output compare for OCU1.This
function is enabled when the waveform output is enabled.
OUT1
SOT6
P96
Serial data output pin for UART6
General purpose I/O port
Waveform output pin for output compare for OCU2. This
function is enabled when the waveform output is enabled.
71
72
73
74
OUT2
F
F
SCK6
P97
Clock I/O pin for UART6
General purpose I/O port
Waveform output pin for output compare for OCU3. This
function is enabled when the waveform output is enabled.
OUT3
PA0
General purpose I/O port
RX input pin for CAN0 Interface. Outputs generated by
other functions must be stopped when using the CAN
functions.
73
75
RX0
F
INT8R
PA1
External interrupt request input pin (Sub) for INT8
General purpose I/O port
74
30
76
32
F
K
TX0
TX Output pin for CAN0
AVCC
VCC power input pin for the Analog circuit
(Continued)
DS07-13752-2E
15
MB90950 Series
(Continued)
Pin No.
I/O
Pin
name
Circuit
Function
LQFP100*1
QFP100*2
type*3
Reference voltage input pin for the A/D Converter. This
power supply must be turned on or off while a voltage
higher than or equal to AVRH is applied to AVCC.
31
33
AVRH
L
32
33
34
35
AVRL
AVSS
K
K
Lower reference voltage input pin for the A/D Converter
VSS power input pin for the Analog circuit
MD1,
MD0
50, 51
52, 53
C
Input pins for specifying the operating mode
49
51
MD2
VCC
D
Input pin for specifying the operating mode
Power (3.5 V to 5.5 V) input pins
Power (0 V) input pins
13, 63, 88
15, 65, 90
⎯
⎯
14, 42, 64, 89 16, 44, 66, 91
VSS
This is the power supply stabilization capacitor. This pin
should be connected to a ceramic capacitor with a
capacitance greater than or equal to 0.1 µF.
15
17
C
K
*1 : FPT-100P-M20
*2 : FPT-100P-M06
*3 : For I/O circuit type, refer to “■ I/O CIRCUIT TYPES”.
16
DS07-13752-2E
MB90950 Series
■ I/O CIRCUIT TYPES
Type
Circuit
Remarks
A
Oscillation circuit
X1
High-speed oscillation feedback
resistor = approx. 1 MΩ
(Flash memory product)
X out
X0
Standby control signal
Oscillation circuit
X1
X0
High-speed oscillation feedback
resistor = approx. 1 MΩ
(Evaluation product)
X out
Standby control signal
B
Oscillation circuit
X1A
Low-speed oscillation feedback
resistor = approx. 10 MΩ
Xout
X0A
Standby control signal
C
Evaluation products:
CMOS hysteresis input
Flash memory products:
CMOS input pin
R
CMOS hysteresis
inputs
D
Evaluation products:
• CMOS hysteresis input
• Pull-down resistor value: approx. 50 kΩ
Flash memory products:
• CMOS input
R
CMOS hysteresis
inputs
Pull-down
Resistor
• No pull-down
(Continued)
DS07-13752-2E
17
MB90950 Series
Type
Circuit
Remarks
E
• CMOS hysteresis input
• Pull-up resistor value: approx. 50 kΩ
Pull-up
Resistor
R
CMOS hysteresis
inputs
F
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
• Automotive input
(with function to disconnect input during
standby)
P-ch
Pout
Nout
N-ch
R
CMOS hysteresis
input
Automotive input
Standby control for
input shutdown
G
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
Pull-up control
P-ch
P-ch
Pout
Nout
N-ch
• Automotive input
(with function to disconnect input during
standby)
• TTL input
R
CMOS hysteresis
input
(with function to disconnect input during
standby)
Automotive input
• Programmable pull-up resistor: 50 kΩ
approx.
TTL input
Standby control for
input shutdown
(Continued)
18
DS07-13752-2E
MB90950 Series
Type
Circuit
Remarks
H
• CMOS level output
(IOL = 3 mA, IOH = −3 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
P-ch
N-ch
Pout
Nout
R
• Automotive input (with function to
disconnect input during standby)
• CMOS hysteresis input
(VIH 0.7 VCC VIL 0.3 VCC)
CMOS hysteresis
input
Automotive input
(with function to disconnect input during
standby)
Standby control for
input shutdown
I
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
• Automotive input
(with function to disconnect input during
standby)
P-ch
N-ch
Pout
Nout
R
CMOS hysteresis
input
• A/D converter analog input
Automotive input
Standby control for
input shutdown
Analog input
J
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• D/A analog output
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
P-ch
N-ch
Pout
Nout
R
CMOS hysteresis
input
• Automotive input
(with function to disconnect input during
standby)
• A/D converter analog input
• D/A converter analog output
Automotive input
Standby control for
input shutdown
Analog input
Analog output
(Continued)
DS07-13752-2E
19
MB90950 Series
Type
Circuit
Remarks
K
Power supply input protection circuit
P-ch
N-ch
L
A/D converter reference voltage power
supply input pin, with the protection circuit
Flash memory devices do not have
a protection circuit against VCC for
pin AVRH
ANE
AVR
P-ch
N-ch
ANE
M
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
P-ch
N-ch
Pout
Nout
R
• Automotive input
(with function to disconnect input during
standby)
CMOS input
• CMOS hysteresis input
(VIH 0.7 VCC VIL 0.3 VCC)
(with function to disconnect input during
standby)
Automotive input
Standby control for
input shutdown
N
• CMOS level output
Pull-up control
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
P-ch
P-ch
Pout
Nout
N-ch
• Automotive input
(with function to disconnect input during
standby)
• TTL input
R
CMOS hysteresis input
(with function to disconnect input during
standby)
• CMOS hysteresis input
(VIH 0.7 VCC VIL 0.3 VCC)
(with function to disconnect input during
standby)
Automotive input
CMOS hysteresis input
TTL input
• Programmable pull-up resistor: 50 kΩ
approx
Standby control for
input shutdown
(Continued)
20
DS07-13752-2E
MB90950 Series
(Continued)
Type
Circuit
Remarks
O
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
• Automotive input
(with function to disconnect input during
standby)
P-ch
N-ch
Pout
Nout
R
CMOS hysteresis input
• CMOS hysteresis input
(VIH 0.7 VCC VIL 0.3 VCC)
(with function to disconnect input during
standby)
Automotive input
CMOS hysteresis input
Standby control for
input shutdown
• A/D converter analog input
Analog input
DS07-13752-2E
21
MB90950 Series
■ HANDLING DEVICES
• Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage.
• Handling unused pins
Leaving unused input pins open may result in misbehavior or latch-up and possible permanent damage to the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
• Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, that are designed to be set to the same potential are connected the
inside of the device to prevent malfunctions such as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally. Connect VCC and VSS pins to the device from the current supply source at a low imped-
ance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS pins in the vicinity of VCC and VSS pins of the device
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90950
Series
Vcc
Vss
Vcc
Vss
• Mode Pins (MD0 to MD2)
Connect the mode pins directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due
to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to VCC or VSS pins
and to provide a low-impedance connection.
22
DS07-13752-2E
MB90950 Series
• Sequence for Turning On the Power Supply to the A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23)
after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simulta-
neously is acceptable).
• Pin connection when A/D converter is not used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
• Crystal Oscillator Circuit
The X0, X1 pins and X0A, X1A pins may be possible causes of abnormal operation. Make sure to provide bypass
capacitors via the shortest distance from X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic oscillator)
and ground lines, and make sure, to the utmost effort, that the oscillation circuit lines do not cross the lines of
other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and
X0A, X1A pins with a ground area for stabilizing the operation.
For each of the mass-production products, request an oscillator evaluation from the manufacturer of the oscillator
you are using.
• Pull-up/down resistors
The MB90950 Series does not support internal pull-up/down resistors (except for the pull-up resistors built into
ports 0 to 3). Use external components where needed.
• Using external clock
To use an external clock, drive the X0A pin and leave the X1A pin open. The high-speed oscillator pins (X0, X1)
can not be used for external clock inputs.
MB90950 Series
X0A
Open
X1A
• Precautions when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the
X1A pin open.
• Notes on operation in PLL clock mode
If PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when
there is no external oscillator or the external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
• Notes on Power-On
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during power-on to 50 µs
or more (0.2 V to 2.7 V) .
DS07-13752-2E
23
MB90950 Series
• Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operating range. Therefore, the VCC supply voltage should be stabilized.
Stabilize the power supply voltage as follows as a standard level of stabilization.
• VCC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the
standard VCC supply voltage
• The coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
• Initialization
Inthedevice, thereareinternalregisterswhichareinitializedonlybyapower-onreset. Toinitializetheseregisters,
turn on the power again.
• Port 0 to Port 3 Output During Power-on (External-bus Mode)
As shown below, when the power is turned on in External-Bus mode, there is a possibility that output signal of
Port 0 to Port 3 might be unstable irrespective of the reset input.
1/2VCC
VCC
Port0 to Port3
Port0 to Port3 outputs
might be unstable
Port0 to Port3 outputs = Hi-Z
• Notes on Using the CAN Function
To use the CAN function, please set the DIRECT bit of the CAN Direct Mode Register (CDMR) to 1.
If the DIRECT bit is set to ’0’ (initial value) only MB90V950JA(S) and MB90V950MA(S), wait states will be
performed when accessing CAN registers.
Note : Please refer to the Hardware Manual of the MB90950 series for detail of CAN Direct Mode Register.
• Flash Security Function
A security bit is located in the area of the Flash memory.
If protection code 01H is written in the security bit, the Flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Refer to following table for the address of the security bit.
Flash memory size
Address of the security bit
MB90F952JD(S), MB90F952MD(S)
Embedded 2 Mbits Flash Memory
FC0001H
24
DS07-13752-2E
MB90950 Series
■ BLOCK DIAGRAMS
MB90V950JA(S),MB90V950MA(S)
X0,X1
X0A,X1A*1
Clock
16LX
CPU
RST
Controller
CR
Clock
calibration
unit
I/O Timer 0
FRCK0
oscillation
circuit*2
Input
Capture
8 channels
CPU Operation
IN7 to IN0
detection circuit*2
RAM
30 Kbytes
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler
7 channels
I/O Timer 1
SOT6 to SOT0
SCK6 to SCK0
SIN6 to SIN0
CAN
Controller
3 channels
UART
7 channels
RX2 to RX0
TX2 to TX0
16-bit
Reload Timer
4 channels
AVCC
TIN3 to TIN0
AVSS
TOT3 to TOT0
8/10-bit
A/D converter
24 channels
AN23 to AN0
AVRH
AD15 to AD00
A23 to A16
ALE
AVRL
ADTG
RD
8-bit
D/A converter
2 channels
External
Bus
Interface
WR/WRL
WRH
DA01, DA00
HRQ
HAK
8/16-bit
PPG
16 channels
PPGF to PPG0
RDY
CLK
I2C
Interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
DTP/External
Interrupt
16 channels
INT7 to INT0
DMAC
Clock
CKOT
Monitor
*1 : Only for MB90V950JA,MB90V950MA
*2 : Only for MB90V950JA(S)
DS07-13752-2E
25
MB90950 Series
MB90F952JD(S), MB90F952MD(S)
X0,X1
X0A,X1A*1
Clock
16LX
CPU
Controller
RST
CR
Clock
calibration
unit
I/O Timer 0
FRCK0
oscillation
circuit*2
Low voltage detection circuit
Input
Capture
CPU operation detection circuit*2
IN7 to IN0
8 channels
RAM
16 Kbytes
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Flash
256 Kbytes
+32 Kbytes
I/O Timer 1
Prescaler
7 channels
CAN
RX0, RX1
TX0, TX1
Controller
2 channels
SOT6 to SOT0
UART
7 channels
SCK6 to SCK0
SIN6 to SIN0
16-bit
Reload Timer
4 channels
TIN3 to TIN0
AVCC
TOT3 to TOT0
AVSS
8/10-bit
AN15 to AN0
AN23 to AN16
AVRH
A/D converter
AD15 to AD00
A23 to A16
ALE
16/24
channels
AVRL
RD
ADTG
External
Bus
Interface
WR/WRL
WRH
8-bit
D/A converter
2 channels
DA01, DA00
HRQ
HAK
8/16-bit
PPG
16 channels
RDY
PPGF to PPG0
CLK
I2C
Interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
DTP/External
Interrupt
16 channels
INT7 to INT0
DMAC
Clock
CKOT
Monitor
*1 : Only for devices without an S suffix in the part number
*2 : Only for devices with a J suffix in the part number
26
DS07-13752-2E
MB90950 Series
■ MEMORY MAP
MB90V950JA(S),
MB90V950MA(S)
MB90F952JD(S),
MB90F952MD(S)
FFFFFF
FF0000
H
FFFFFF
H
ROM (FF bank)
ROM (FF bank)
FEFFFFH
H
FF0000
FEFFFFH
H
ROM (FE bank)
ROM (FD bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
FE0000
H
FE0000
FDFFFFH
H
FDFFFF
H
FD0000
FCFFFFH
H
FD0000
FCFFFFH
H
ROM (FC bank)
ROM (FB bank)
FC0000
H
FC0000
H
FBFFFF
H
FB0000
H
H
FAFFFF
F77FFF
H
ROM (FA bank)
ROM (F9 bank)
ROM (Satellite)
FA0000
F9FFFFH
H
F70000
F6FFFFH
H
F90000
H
External access
area
F8FFFF
H
ROM (F8 bank)
F80000
H
External access area
00FFFF
H
00FFFF
H
ROM
ROM
(image of FF bank)
(image of FF bank)
008000
H
H
008000
H
H
007FFF
007FFF
Peripheral
Peripheral
007900
0078FF
H
H
007900
H
003FFF
H
RAM 30 Kbytes
RAM 16 Kbytes
000100
H
000100
H
H
External access area
External access area
0000EF
H
H
0000EF
Peripheral
Peripheral
000000
H
000000
: Not accessible
Note: An image of the data in the FF bank of ROM is visible in the upper part of bank 00, which makes it possible
for the C compiler to use the small memory model. The lower 16 bits of addresses in the FF bank are the
same as the lower 16 bits of addresses in the 00 bank so that tables stored in the ROM can be accessed
without using the far specifier in the pointer declaration.
For example, when the address 00C000H is accessed, the data at FFC000H in ROM is actually accessed.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
Asaresult, theimagebetweenFF8000H andFFFFFFH isvisibleinbank00, whiletheimagebetweenFF0000H
and FF7FFFH is visible only in bank FF.
DS07-13752-2E
27
MB90950 Series
■ I/O MAP
Address
Register
Abbreviation Access Resource name Initial value
000000H Port 0 Data Register
000001H Port 1 Data Register
000002H Port 2 Data Register
000003H Port 3 Data Register
000004H Port 4 Data Register
000005H Port 5 Data Register
000006H Port 6 Data Register
000007H Port 7 Data Register
000008H Port 8 Data Register
000009H Port 9 Data Register
00000AH Port A Data Register
00000BH Analog Input Enable Register 5
00000CH Analog Input Enable Register 6
00000DH Analog Input Enable Register 7
00000EH Input Level Select Register 0
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
ADER5
ADER6
ADER7
ILSR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
111111XXB
11111111B
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port 5, A/D
Port 6, A/D
Port 7, A/D
Port 0 to 7
11111111B
11111111B
XXXXXXXXB
Port 0 to 3,
8 to A
00000FH Input Level Select Register 1
ILSR1
R/W
XXXX0XXXB
000010H Port 0 Direction Register
000011H Port 1 Direction Register
000012H Port 2 Direction Register
000013H Port 3 Direction Register
000014H Port 4 Direction Register
000015H Port 5 Direction Register
000016H Port 6 Direction Register
000017H Port 7 Direction Register
000018H Port 8 Direction Register
000019H Port 9 Direction Register
00001AH Port A Direction Register
00001BH
DDR0
DDR1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000100B
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
Reserved
PUCR0
PUCR1
PUCR2
PUCR3
00001CH Port 0 Pull-up Control Register
00001DH Port 1 Pull-up Control Register
00001EH Port 2 Pull-up Control Register
00001FH Port 3 Pull-up Control Register
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
00000000B
00000000B
00000000B
00000000B
(Continued)
28
DS07-13752-2E
MB90950 Series
Abbrevia-
tion
Address
Register
Access Resource name Initial value
000020H Serial Mode Register 0
000021H Serial Control Register 0
SMR0
SCR0
W, R/W
W, R/W
00000000B
00000000B
RDR0/
TDR0
00000000B/
11111111B
000022H Reception/Transmission Data Register 0
000023H Serial Status Register 0
R/W
SSR0
R, R/W
00001000B
UART0
Extended Communication Control
R, W,
R/W
000024H
ECCR0
000000XXB
Register 0
000025H Extended Status/Control Register 0
000026H Baud Rate Generator Register 00
000027H Baud Rate Generator Register 01
000028H Serial Mode Register 1
ESCR0
BGR00
BGR01
SMR1
R/W
00000X00B
00000000B
00000000B
00000000B
00000000B
R, R/W
R, R/W
W, R/W
W, R/W
000029H Serial Control Register 1
SCR1
RDR1/
TDR1
00000000B/
11111111B
00002AH Reception/Transmission Data Register 0
00002BH Serial Status Register 1
R/W
SSR1
R, R/W
00001000B
UART1
Extended Communication Control
R, W,
R/W
00002CH
ECCR1
000000XXB
Register 1
00002DH Extended Status/Control Register 1
00002EH Baud Rate Generator Register 10
00002FH Baud Rate Generator Register 11
000030H PPG0 Operation Mode Control Register
000031H PPG1 Operation Mode Control Register
000032H PPG0/PPG1 Count Clock Select Register
000033H
ESCR1
BGR10
BGR11
PPGC0
PPGC1
PPG01
Reserved
PPGC2
PPGC3
PPG23
Reserved
PPGC4
PPGC5
PPG45
R/W
00000X00B
00000000B
00000000B
01000111B
01000001B
00000010B
R, R/W
R, R/W
W, R/W
W, R/W
R/W
16-bit
PPG0/PPG1
000034H PPG2 Operation Mode Control Register
000035H PPG3 Operation Mode Control Register
000036H PPG2/PPG3 Count Clock Select Register
000037H
W, R/W
W, R/W
R/W
01000111B
01000001B
00000010B
16-bit
PPG2/PPG3
000038H PPG4 Operation Mode Control Register
000039H PPG5 Operation Mode Control Register
00003AH PPG4/PPG5 Clock Select Register
W, R/W
W, R/W
R/W
01000111B
01000001B
00000010B
16-bit
PPG4/PPG5
Address Match
Detection 1
00003BH Address Detect Control Register 1
PACSR1
R/W
11000000B
00003CH PPG6 Operation Mode Control Register
00003DH PPG7 Operation Mode Control Register
00003EH PPG6/PPG7 Count Clock Select Register
00003FH
PPGC6
PPGC7
PPG67
W, R/W
W, R/W
R/W
01000111B
01000001B
00000010B
16-bit
PPG6/PPG7
Reserved
(Continued)
DS07-13752-2E
29
MB90950 Series
Abbrevia-
tion
Address
Register
Access Resource name Initial value
000040H PPG8 Operation Mode Control Register
000041H PPG9 Operation Mode Control Register
000042H PPG8/PPG9 Count Clock Select Register
000043H
PPGC8
PPGC9
PPG89
Reserved
PPGCA
PPGCB
PPGAB
Reserved
PPGCC
PPGCD
PPGCD
Reserved
PPGCE
PPGCF
PPGEF
Reserved
ICS01
W, R/W
W, R/W
R/W
01000111B
01000001B
00000010B
16-bit
PPG8/PPG9
000044H PPGA Operation Mode Control Register
000045H PPGB Operation Mode Control Register
000046H PPGA/PPGB Count Clock Select Register
000047H
W, R/W
W, R/W
R/W
01000111B
01000001B
00000010B
16-bit
PPGA/PPGB
000048H PPGC Operation Mode Control Register
000049H PPGD Operation Mode Control Register
00004AH PPGC/PPGD Count Clock Select Register
00004BH
W, R/W
W, R/W
R/W
01000111B
01000001B
00000010B
16-bit
PPGC/PPGD
00004CH PPGE Operation Mode Control Register
00004DH PPGF Operation Mode Control Register
00004EH PPGE/PPGF Count Clock Select Register
00004FH
W, R/W
W, R/W
R/W
01000111B
01000001B
00000010B
16-bit
PPGE/PPGF
000050H Input Capture Control Status 0/1
000051H Input Capture Edge 0/1
R/W
R/W, R
R/W
R
00000000B
111010XXB
00000000B
111111XXB
00000000B
111100XXB
00000000B
111000XXB
00001100B
01100000B
00001100B
01100000B
00001100B
01100000B
00001100B
01100000B
00000000B
11110000B
00000000B
11110000B
(Continued)
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
ICE01
000052H Input Capture Control Status 2/3
000053H Input Capture Edge 2/3
ICS23
ICE23
000054H Input Capture Control Status 4/5
000055H Input Capture Edge 4/5
ICS45
R/W
R
ICE45
000056H Input Capture Control Status 6/7
000057H Input Capture Edge 6/7
ICS67
R/W
R/W, R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICE67
000058H Output Compare Control Status 0
000059H Output Compare Control Status 1
00005AH Output Compare Control Status 2
00005BH Output Compare Control Status 3
00005CH Output Compare Control Status 4
00005DH Output Compare Control Status 5
00005EH Output Compare Control Status 6
00005FH Output Compare Control Status 7
000060H Timer Control Status 0
OCS0
Output Compare
0/1
OCS1
OCS2
Output Compare
2/3
OCS3
OCS4
Output Compare
4/5
OCS5
OCS6
Output Compare
6/7
OCS7
TMCSR0
TMCSR0
TMCSR1
TMCSR1
16-bit reload
timer 0
000061H Timer Control Status 0
000062H Timer Control Status 1
16-bit reload
timer 1
000063H Timer Control Status 1
30
DS07-13752-2E
MB90950 Series
Abbrevia-
tion
Address
Register
Access Resource name Initial value
000064H Timer Control Status 2
000065H Timer Control Status 2
000066H Timer Control Status 3
000067H Timer Control Status 3
000068H A/D Control Status 0
000069H A/D Control Status 1
00006AH A/D Data 0
TMCSR2
TMCSR2
TMCSR3
TMCSR3
ADCS0
ADCS1
ADCR0
ADCR1
ADSR0
ADSR1
R/W
R/W
R/W
R/W
R/W
R/W
R
00000000B
11110000B
00000000B
11110000B
00011110B
00000001B
00000000B
11111100B
00000000B
00000000B
16-bit reload
timer 2
16-bit reload
timer 3
A/D Converter
00006BH A/D Data 1
R
00006CH ADC Setting 0
R/W
R/W
00006DH ADC Setting 1
Low Voltage/CPU
Operation
Detection Reset
Low Voltage/CPU OPeration Detection Re-
set Control Register
00006EH
LVRC
R/W
W
00111000B
11111101B
00006FH ROM Mirror Function Setting
ROMM
ROM Mirror
000070H
to
00008FH
Reserved for CAN Controller
Reserved
000090H
to
00009AH
DMA Descriptor Channel Specified
00009BH
Register
DCSR
R/W
00000000B
DMA
00009CH DMA Status Register L
00009DH DMA Status Register H
DSRL
DSRH
R/W
R/W
00000000B
00000000B
Address Match
Detection 0
00009EH Address Detect Control Register 0
PACSR0
R/W
11000000B
Delayed Interrupt
Generation
Module
Delayed Interrupt Trigger/Release
00009FH
Register
DIRR
R/W
11111110B
Low Power
Control Circuit
0000A0H Low-power Mode Control Register
0000A1H Clock Selection Register
LPMCR
CKSCR
W, R/W
R, R/W
00011000B
11111100B
Low Power
Control Circuit
0000A2H,
0000A3H
Reserved
DSSR
0000A4H DMA Stop Status Register
R/W
W
DMA
00000000B
00111100B
Automatic Ready Function Select
0000A5H
Register
ARSR
External Memory
Access
External Address Output Control
0000A6H
Register
HACR
ECSR
W
W
00000000B
0000A7H Bus Control Signal Selection Register
00000001B
(Continued)
DS07-13752-2E
31
MB90950 Series
Abbrevia-
tion
Address
Register
Access Resource name Initial value
0000A8H Watchdog Control Register
0000A9H Time Base Timer Control Register
WDTC
R, W
Watchdog Timer X1XXX111B
Time Base
11100100B
Timer
TBTC
W, R/W
R, R/W
0000AAH Watch Timer Control Register
0000ABH
WTC
Reserved
DERL
Watch Timer
1X001000B
0000ACH DMA Enable Register L
0000ADH DMA Enable Register H
R/W
R/W
00000000B
00000000B
DMA
DERH
Flash Control Status Register
0000AEH
FMCS
R, R/W
Flash Memory
000X0000B
(Flash memory devices only)
0000AFH
Reserved
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
DAT0
0000B0H Interrupt Control Register 00
0000B1H Interrupt Control Register 01
0000B2H Interrupt Control Register 02
0000B3H Interrupt Control Register 03
0000B4H Interrupt Control Register 04
0000B5H Interrupt Control Register 05
0000B6H Interrupt Control Register 06
0000B7H Interrupt Control Register 07
0000B8H Interrupt Control Register 08
0000B9H Interrupt Control Register 09
0000BAH Interrupt Control Register 10
0000BBH Interrupt Control Register 11
0000BCH Interrupt Control Register 12
0000BDH Interrupt Control Register 13
0000BEH Interrupt Control Register 14
0000BFH Interrupt Control Register 15
0000C0H D/A Converter Data 0
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
R/W
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
Interrupt Control
0000C1H D/A Converter Data 1
DAT1
R/W
D/A Converter
0000C2H D/A Control 0
DACR0
DACR1
R/W
0000C3H D/A Control 1
R/W
0000C4H,
0000C5H
Reserved
0000C6H External Interrupt Enable 0
0000C7H External Interrupt Source 0
0000C8H Detection Level Setting 0
0000C9H Detection Level Setting 0
ENIR0
EIRR0
ELVR0
ELVR0
R/W
R/W
R/W
R/W
00000000B
XXXXXXXXB
00000000B
00000000B
(Continued)
DTP/External
Interrupt 0
32
DS07-13752-2E
MB90950 Series
Abbrevia-
tion
Address
Register
Access Resource name Initial value
0000CAH External Interrupt Enable 1
0000CBH External Interrupt Source 1
0000CCH Detection Level Setting 1
ENIR1
EIRR1
ELVR1
ELVR1
EISSR
PSCCR
BAPL
R/W
R/W
R/W
R/W
R/W
W
00000000B
XXXXXXXXB
00000000B
DTP/External
Interrupt 1
0000CDH Detection Level Setting 1
00000000B
0000CEH External Interrupt Source Select
0000CFH PLL/Sub clock Control Register
0000D0H DMA Buffer Address Pointer L Register
0000D1H DMA Buffer Address Pointer M Register
0000D2H DMA Buffer Address Pointer H Register
0000D3H DMA Control Register
00000000B
PLL
11110000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W, R/W
W, R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
BAPM
BAPH
DMACS
IOAL
DMA
0000D4H I/O Register Address Pointer L Register
0000D5H I/O Register Address Pointer H Register
0000D6H Data Counter L Register
IOAH
DCTL
0000D7H Data Counter H Register
DCTH
SMR2
SCR2
0000D8H Serial Mode Register 2
0000D9H Serial Control Register 2
00000000B
Reception/Transmission Data
Register 2
RDR2/
TDR2
00000000B/
11111111B
0000DAH
R/W
0000DBH Serial Status Register 2
SSR2
R, R/W
00001000B
UART2
Extended Communication Control
R, W,
R/W
0000DCH
ECCR2
000000XXB
Register 2
0000DDH Extended Status Control Register 2
0000DEH Baud Rate Generator Register 20
0000DFH Baud Rate Generator Register 21
0000E0H
ESCR2
BGR20
BGR21
R/W
00000X00B
00000000B
00000000B
R, R/W
R, R/W
to
Reserved for CAN Controller 2. Refer to “■ CAN CONTROLLERS”
0000EFH
0000F0H
to
External
0000FFH
007900H Reload Register L0
007901H Reload Register H0
007902H Reload Register L1
007903H Reload Register H1
007904H Reload Register L2
007905H Reload Register H2
007906H Reload Register L3
007907H Reload Register H3
PRLL0
PRLH0
PRLL1
PRLH1
PRLL2
PRLH2
PRLL3
PRLH3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
16-bit
PPG0/PPG1
16-bit
PPG2/PPG3
DS07-13752-2E
33
MB90950 Series
Address
Register
Abbreviation Access
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
007908H Reload Register L4
007909H Reload Register H4
00790AH Reload Register L5
00790BH Reload Register H5
00790CH Reload Register L6
00790DH Reload Register H6
00790EH Reload Register L7
00790FH Reload Register H7
007910H Reload Register L8
007911H Reload Register H8
007912H Reload Register L9
007913H Reload Register H9
007914H Reload Register LA
007915H Reload Register HA
007916H Reload Register LB
007917H Reload Register HB
007918H Reload Register LC
007919H Reload Register HC
00791AH Reload Register LD
00791BH Reload Register HD
00791CH Reload Register LE
00791DH Reload Register HE
00791EH Reload Register LF
00791FH Reload Register HF
007920H Input Capture 0
PRLL4
PRLH4
PRLL5
PRLH5
PRLL6
PRLH6
PRLL7
PRLH7
PRLL8
PRLH8
PRLL9
PRLH9
PRLLA
PRLHA
PRLLB
PRLHB
PRLLC
PRLHC
PRLLD
PRLHD
PRLLE
PRLHE
PRLLF
PRLHF
IPCP0
IPCP0
IPCP1
IPCP1
IPCP2
IPCP2
IPCP3
IPCP3
IPCP4
IPCP4
IPCP5
IPCP5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
16-bit
PPG4/PPG5
16-bit
PPG6/PPG7
16-bit
PPG8/PPG9
16-bit
PPGA/PPGB
16-bit
PPGC/PPGD
16-bit
PPGE/PPGF
007921H Input Capture 0
R
00000000B
Input Capture 0/1*
Input Capture 2/3*
Input Capture 4/5*
007922H Input Capture 1
R
00000000B
007923H Input Capture 1
R
00000000B
007924H Input Capture 2
R
00000000B
007925H Input Capture 2
R
00000000B
007926H Input Capture 3
R
00000000B
007927H Input Capture 3
R
00000000B
007928H Input Capture 4
R
00000000B
007929H Input Capture 4
R
00000000B
00792AH Input Capture 5
R
00000000B
00792BH Input Capture 5
R
00000000B
* : The Initial values of MB90V950JA(S) and MB90V950MA(S) are XXXXXXXXB.
34
(Continued)
DS07-13752-2E
MB90950 Series
Address
Register
Abbreviation Access
Resource name
Initial value
00000000B
00792CH Input Capture 6
00792DH Input Capture 6
00792EH Input Capture 7
00792FH Input Capture 7
007930H Output Compare 0
007931H Output Compare 0
007932H Output Compare 1
007933H Output Compare 1
007934H Output Compare 2
007935H Output Compare 2
007936H Output Compare 3
007937H Output Compare 3
007938H Output Compare 4
007939H Output Compare 4
00793AH Output Compare 5
00793BH Output Compare 5
00793CH Output Compare 6
00793DH Output Compare 6
00793EH Output Compare 7
00793FH Output Compare 7
007940H Timer Data 0
IPCP6
IPCP6
R
R
00000000B
Input Capture 6/7*
IPCP7
R
00000000B
IPCP7
R
00000000B
OCCP0
OCCP0
OCCP1
OCCP1
OCCP2
OCCP2
OCCP3
OCCP3
OCCP4
OCCP4
OCCP5
OCCP5
OCCP6
OCCP6
OCCP7
OCCP7
TCDT0
TCDT0
TCCSL0
TCCSH0
TCDT1
TCDT1
TCCSL1
TCCSH1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
I/O Timer 0
007941H Timer Data 0
00000000B
007942H Timer Control Status 0
007943H Timer Control Status 0
007944H Timer Data 1
00000000B
01100000B
00000000B
007945H Timer Data 1
00000000B
I/O Timer 1
007946H Timer Control Status 1
007947H Timer Control Status 1
00000000B
01100000B
007948H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
TMR0/
TMRLR0
16-bit Reload
Timer 0
Timer 0/Reload 0
007949H
00794AH
TMR1/
TMRLR1
16-bit Reload
Timer 1
Timer 1/Reload 1
00794BH
00794CH
TMR2/
TMRLR2
16-bit Reload
Timer 2
Timer 2/Reload 2
00794DH
00794EH
TMR3/
TMRLR3
16-bit Reload
Timer 3
Timer 3/Reload 3
00794FH
* : The Initial values of MB90V950JA(S) and MB90V950MA(S) are XXXXXXXXB.
DS07-13752-2E
(Continued)
35
MB90950 Series
Address
Register
Abbreviation Access
Resource name
Initial value
00000000B
00000000B
007950H Serial Mode Register 3
007951H Serial Control Register 3
SMR3
SCR3
W, R/W
W, R/W
Reception/Transmission Data
Register 3
00000000B/
11111111B
007952H
RDR3/TDR3
SSR3
R/W
007953H Serial Status Register 3
R, R/W
00001000B
UART3
Extended Communication Control
Register 3
R, W,
R/W
007954H
ECCR3
000000XXB
007955H Extended Status Control Register 3
007956H Baud Rate Generator Register 30
007957H Baud Rate Generator Register 31
007958H Serial Mode Register 4
ESCR3
BGR30
BGR31
SMR4
R/W
00000X00B
00000000B
00000000B
00000000B
00000000B
R, R/W
R, R/W
W, R/W
W, R/W
007959H Serial Control Register 4
SCR4
Reception/Transmission Data
Register 4
00000000B/
11111111B
00795AH
RDR4/TDR4
SSR4
R/W
00795BH Serial Status Register 4
R, R/W
00001000B
UART4
Extended Communication Control
Register 4
R, W,
R/W
00795CH
ECCR4
000000XXB
00795DH Extended Status Control Register 4
00795EH Baud Rate Generator Register 40
00795FH Baud Rate Generator Register 41
007960H Clock Supervisor Control Register
ESCR4
BGR40
BGR41
CSVCR
R/W
R, R/W
R, R/W
R/W
00000X00B
00000000B
00000000B
00011100B
Clock Supervisor
Clock Monitor
007961H
to
00796BH
Reserved
00796CH Clock Output Enable Register
00796DH
CLKR
Reserved
R/W
11110000 B
00796EH CAN Direct Mode Register
00796FH CAN Switch Register
007970H I2C Bus Status Register 0
007971H I2C Bus Control Register 0
CDMR
CANSWR
IBSR0
R/W
R/W
R
CAN Clock Sync
CAN 0/1
11111110 B
11111100 B
00000000B
00000000B
00000000B
00000000B
11111111B
00111111B
00000000B
IBCR0
W, R/W
R/W
R/W
R/W
R/W
R/W
007972H
ITBAL0
ITBAH0
ITMKL0
ITMKH0
ISBA0
I2C 10-bit Slave Address Register 0
007973H
I2C 10-bit Slave Address Mask
Register 0
007974H
I2C Interface0
007975H
007976H I2C 7-bit Slave Address Register 0
I2C 7-bit Slave Address Mask
Register 0
007978H I2C Data Register 0
007977H
ISMK0
IDAR0
R/W
R/W
01111111B
00000000B
007979H,
00797AH
Reserved
(Continued)
36
DS07-13752-2E
MB90950 Series
Abbrevia-
tion
Address
Register
Access Resource name Initial value
00797BH I2C Clock Control Register 0
ICCR0
R/W
I2C Interface 0
00011111B
00797CH
to
Reserved
00797FH
007980H I2C Bus Status Register 1
007981H I2C Bus Control Register 1
IBSR1
IBCR1
ITBAL1
ITBAH1
ITMKL1
ITMKH1
ISBA1
R
W, R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
11111111B
00111111B
00000000B
01111111B
00000000B
007982H
I2C 10-bit Slave Address Register 1
007983H
007984H
I2C Interface 1
I2C 10-bit Slave Address Mask
Register 1
007985H
007986H I2C 7-bit Slave Address Register 1
007987H I2C 7-bit Slave Address Mask Register 1
007988H I2C Data Register 1
ISMK1
IDAR1
007989H,
00798AH
Reserved
ICCR1
00798BH I2C Clock Control Register 1
R/W
I2C Interface1
00011111B
00798CH
to
Reserved
00798FH
007990H Serial Mode Register 5
007991H Serial Control Register 5
SMR5
SCR5
W, R/W
W, R/W
00000000B
00000000B
RDR5/
TDR5
00000000B/
11111111B
007992H Reception/Transmission Data Register 5
R/W
007993H Serial Status Register 5
SSR5
R, R/W
00001000B
UART5
Extended Communication Control
R, W,
R/W
007994H
ECCR5
000000XXB
Register 5
007995H Extended Status Control Register 5
007996H Baud Rate Generator Register 50
007997H Baud Rate Generator Register 51
007998H Serial Mode Register 6
ESCR5
BGR50
BGR51
SMR6
R/W
00000X00B
00000000B
00000000B
00000000B
00000000B
R, R/W
R, R/W
W, R/W
W, R/W
007999H Serial Control Register 6
SCR6
RDR6/
TDR6
00000000B/
11111111B
00799AH Reception/Transmission Data Register 6
00799BH Serial Status Register 6
R/W
SSR6
R, R/W
00001000B
UART6
Extended Communication Control
R, W,
R/W
00799CH
ECCR6
000000XXB
Register 6
00799DH Extended Status Control Register 6
00799EH Baud Rate Generator Register 60
00799FH Baud Rate Generator Register 61
ESCR6
BGR60
BGR61
R/W
00000X00B
00000000B
00000000B
(Continued)
R, R/W
R, R/W
DS07-13752-2E
37
MB90950 Series
Abbrevia-
tion
Address
Register
Access Resource name Initial value
0079A0H UART Input Level Setting Register
0079A1H
ILSR2
R/W
UART
11111100B
Reserved
FWR0
0079A2H Flash Write Control Register 0
0079A3H Flash Write Control Register 1
R/W
R/W
Flash
Flash
00000000B
00000000B
FWR1
0079A4H
to
0079B1H
Reserved
LVRS
Low Voltage/
CPU Operation
Detection Reset
Low Voltage/CPU Operation Detection
Setting Register
0079B2H
R/W
10000111B
0079B3H
to
Reserved
0079B7H
0079B8H Clock Calibration Unit Control
0079B9H CR Oscillation Trimming Setting
CUCR
CRTR
R/W
R/W
R/W
R/W
R
00000000B
11110111B
01010000B
11000011B
00000000B
00000000B
00000000B
00000000B
0079BAH
CUTDL
CUTDH
CUTR1L
CUTR1H
CUTR2L
CUTR2H
CR Oscillation Timer Data Register
0079BBH
Clock Calibration
Unit
0079BCH
Main Timer Data Register 1
0079BDH
R
0079BEH
R
Main Timer Data Register 2
0079BFH
R
0079C0H
to
Reserved
0079DFH
0079E0H Detect Address Setting 0
0079E1H Detect Address Setting 0
0079E2H Detect Address Setting 0
0079E3H Detect Address Setting 1
0079E4H Detect Address Setting 1
0079E5H Detect Address Setting 1
0079E6H Detect Address Setting 2
0079E7H Detect Address Setting 2
0079E8H Detect Address Setting 2
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
PADR2
PADR2
PADR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 0
Address Match
Detection 0
XXXXXXXXB
(Continued)
38
DS07-13752-2E
MB90950 Series
(Continued)
Abbrevia-
tion
Address
Register
Access Resource name Initial value
0079E9H
to
Reserved
0079EFH
0079F0H Detect Address Setting 3
0079F1H Detect Address Setting 3
0079F2H Detect Address Setting 3
0079F3H Detect Address Setting 4
0079F4H Detect Address Setting 4
0079F5H Detect Address Setting 4
0079F6H Detect Address Setting 5
0079F7H Detect Address Setting 5
0079F8H Detect Address Setting 5
PADR3
PADR3
PADR3
PADR4
PADR4
PADR4
PADR5
PADR5
PADR5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 1
0079F9H
to
Reserved
0079FFH
007A00H
to
Reserved for CAN Controller 0. Refer to “■ CAN CONTROLLERS”
Reserved for CAN Controller 0. Refer to “■ CAN CONTROLLERS”
Reserved for CAN Controller 1. Refer to “■ CAN CONTROLLERS”
Reserved for CAN Controller 1. Refer to “■ CAN CONTROLLERS”
Reserved for CAN Controller 2. Refer to “■ CAN CONTROLLERS”
Reserved for CAN Controller 2. Refer to “■ CAN CONTROLLERS”
007AFFH
007B00H
to
007BFFH
007C00H
to
007CFFH
007D00H
to
007DFFH
007E00H
to
007EFFH
007F00H
to
007FFFH
Notes : • Initial value of “X” represents unknown value.
• Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results in reading “X”.
DS07-13752-2E
39
MB90950 Series
■ CAN CONTROLLERS
The CAN controller has the following features:
• Conforms to CAN Specification Version 2.0 Part A and B
• Supports transmission/reception in standard frame and extended frame formats
• Supports transmission of data frames by receiving remote frames
• 16 transmission/reception message buffers
• 29-bit ID and 8-byte data
• Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
• Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz)
• List of Control Registers (1)
Address
Register
Abbreviation Access
Initial Value
CAN0
CAN1
CAN2
000070H
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
0000E0H
0000E1H
0000E2H
0000E3H
0000E4H
0000E5H
0000E6H
0000E7H
0000E8H
0000E9H
0000EAH
0000EBH
0000ECH
0000EDH
0000EEH
0000EFH
Message Buffer
Valid Register
00000000B
00000000B
BVALR
TREQR
TCANR
TCR
R/W
R/W
W
Transmit Request
Register
00000000B
00000000B
Transmit Cancel
Register
00000000B
00000000B
Transmission
Complete Register
00000000B
00000000B
R/W
R/W
R/W
R/W
R/W
Receive Complete
Register
00000000B
00000000B
RCR
Remote Request
Receiving Register
00000000B
00000000B
RRTRR
ROVRR
RIER
Receive Overrun
Register
00000000B
00000000B
Reception Interrupt
Enable Register
00000000B
00000000B
40
DS07-13752-2E
MB90950 Series
• List of Control Registers (2)
Address
Register
Abbreviation Access
Initial Value
CAN0
CAN1
CAN2
007B00H
007B01H
007B02H
007B03H
007B04H
007B05H
007B06H
007B07H
007B08H
007B09H
007B0AH
007B0BH
007B0CH
007D00H
007D01H
007D02H
007D03H
007D04H
007D05H
007D06H
007D07H
007D08H
007D09H
007D0AH
007D0BH
007D0CH
007F00H
007F01H
007F02H
007F03H
007F04H
007F05H
007F06H
007F07H
007F08H
007F09H
007F0AH
007F0BH
007F0CH
Control Status
Register
R/W, W
R/W, R
0XXXX0X1B
00XXX000B
CSR
LEIR
Last Event
Indicator Register
000X0000B
XXXXXXXXB
R/W
R
Receive And Transmit
Error Counter
00000000B
00000000B
RTEC
BTR
Bit Timing
Register
11111111B
X1111111B
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
IDE Register
IDER
TRTRR
Transmit RTR
Register
00000000B
00000000B
Remote Frame
Receive Waiting
Register
XXXXXXXXB
XXXXXXXXB
RFWTR
TIER
R/W
R/W
007B0DH
007D0DH
007F0DH
007B0EH
007B0FH
007B10H
007B11H
007B12H
007B13H
007B14H
007B15H
007B16H
007B17H
007B18H
007B19H
007B1AH
007B1BH
007D0EH
007D0FH
007D10H
007D11H
007D12H
007D13H
007D14H
007D15H
007D16H
007D17H
007D18H
007D19H
007D1AH
007D1BH
007F0EH
007F0FH
007F10H
007F11H
007F12H
007F13H
007F14H
007F15H
007F16H
007F17H
007F18H
007F19H
007F1AH
007F1BH
Transmit Interrupt
Enable Register
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
Acceptance Mask
Select Register
AMSR
AMR0
AMR1
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Acceptance Mask
Register 0
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Acceptance Mask
Register 1
XXXXXXXXB
XXXXXXXXB
DS07-13752-2E
41
MB90950 Series
• List of Message Buffers (ID Registers) (1)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
CAN2
007A00H
to
007A1FH
007C00H
to
007C1FH
007E00H
to
007E1FH
XXXXXXXXB
to
XXXXXXXXB
General-
Purpose Ram
⎯
R/W
007A20H
007A21H
007A22H
007A23H
007A24H
007A25H
007A26H
007A27H
007A28H
007A29H
007A2AH
007A2BH
007A2CH
007A2DH
007A2EH
007A2FH
007A30H
007A31H
007A32H
007A33H
007A34H
007A35H
007A36H
007A37H
007A38H
007A39H
007A3AH
007A3BH
007A3CH
007A3DH
007A3EH
007A3FH
007C20H
007C21H
007C22H
007C23H
007C24H
007C25H
007C26H
007C27H
007C28H
007C29H
007C2AH
007C2BH
007C2CH
007C2DH
007C2EH
007C2FH
007C30H
007C31H
007C32H
007C33H
007C34H
007C35H
007C36H
007C37H
007C38H
007C39H
007C3AH
007C3BH
007C3CH
007C3DH
007C3EH
007C3FH
007E20H
007E21H
007E22H
007E23H
007E24H
007E25H
007E26H
007E27H
007E28H
007E29H
007E2AH
007E2BH
007E2CH
007E2DH
007E2EH
007E2FH
007E30H
007E31H
007E32H
007E33H
007E34H
007E35H
007E36H
007E37H
007E38H
007E39H
007E3AH
007E3BH
007E3CH
007E3DH
007E3EH
007E3FH
XXXXXXXXB
XXXXXXXXB
ID Register 0
ID Register 1
ID Register 2
ID Register 3
ID Register 4
ID Register 5
ID Register 6
ID Register 7
IDR0
IDR1
IDR2
IDR3
IDR4
IDR5
IDR6
IDR7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
42
DS07-13752-2E
MB90950 Series
• List of Message Buffers (ID Registers) (2)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
CAN2
007A40H
007A41H
007A42H
007A43H
007A44H
007A45H
007A46H
007A47H
007A48H
007A49H
007A4AH
007A4BH
007A4CH
007A4DH
007A4EH
007A4FH
007A50H
007A51H
007A52H
007A53H
007A54H
007A55H
007A56H
007A57H
007A58H
007A59H
007A5AH
007A5BH
007A5CH
007A5DH
007A5EH
007A5FH
007C40H
007C41H
007C42H
007C43H
007C44H
007C45H
007C46H
007C47H
007C48H
007C49H
007C4AH
007C4BH
007C4CH
007C4DH
007C4EH
007C4FH
007C50H
007C51H
007C52H
007C53H
007C54H
007C55H
007C56H
007C57H
007C58H
007C59H
007C5AH
007C5BH
007C5CH
007C5DH
007C5EH
007C5FH
007E40H
007E41H
007E42H
007E43H
007E44H
007E45H
007E46H
007E47H
007E48H
007E49H
007E4AH
007E4BH
007E4CH
007E4DH
007E4EH
007E4FH
007E50H
007E51H
007E52H
007E53H
007E54H
007E55H
007E56H
007E57H
007E58H
007E59H
007E5AH
007E5BH
007E5CH
007E5DH
007E5EH
007E5FH
XXXXXXXXB
XXXXXXXXB
ID Register 8
IDR8
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 9
ID Register 10
ID Register 11
ID Register 12
ID Register 13
ID Register 14
ID Register 15
IDR9
IDR10
IDR11
IDR12
IDR13
IDR14
IDR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
DS07-13752-2E
43
MB90950 Series
• List of Message Buffers (DLC Registers and Data Registers) (1)
Address
Register
Abbreviation
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
CAN0
CAN1
CAN2
007A60H
007A61H
007A62H
007A63H
007A64H
007A65H
007A66H
007A67H
007A68H
007A69H
007A6AH
007A6BH
007A6CH
007A6DH
007A6EH
007A6FH
007A70H
007A71H
007A72H
007A73H
007A74H
007A75H
007A76H
007A77H
007A78H
007A79H
007A7AH
007A7BH
007A7CH
007A7DH
007A7EH
007A7FH
007C60H
007C61H
007C62H
007C63H
007C64H
007C65H
007C66H
007C67H
007C68H
007C69H
007C6AH
007C6BH
007C6CH
007C6DH
007C6EH
007C6FH
007C70H
007C71H
007C72H
007C73H
007C74H
007C75H
007C76H
007C77H
007C78H
007C79H
007C7AH
007C7BH
007C7CH
007C7DH
007C7EH
007C7FH
007E60H
007E61H
007E62H
007E63H
007E64H
007E65H
007E66H
007E67H
007E68H
007E69H
007E6AH
007E6BH
007E6CH
007E6DH
007E6EH
007E6FH
007E70H
007E71H
007E72H
007E73H
007E74H
007E75H
007E76H
007E77H
007E78H
007E79H
007E7AH
007E7BH
007E7CH
007E7DH
007E7EH
007E7FH
DLC Register 0
DLC Register 1
DLC Register 2
DLC Register 3
DLC Register 4
DLC Register 5
DLC Register 6
DLC Register 7
DLC Register 8
DLC Register 9
DLC Register 10
DLC Register 11
DLC Register 12
DLC Register 13
DLC Register 14
DLC Register 15
DLCR0
DLCR1
DLCR2
DLCR3
DLCR4
DLCR5
DLCR6
DLCR7
DLCR8
DLCR9
DLCR10
DLCR11
DLCR12
DLCR13
DLCR14
DLCR15
44
DS07-13752-2E
MB90950 Series
• List of Message Buffers (DLC Registers and Data Registers) (2)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
CAN2
007A80H
to
007A87H
007C80H
to
007C87H
007E80H
to
007E87H
XXXXXXXXB
to
XXXXXXXXB
Data Register 0
(8 bytes)
DTR0
DTR1
DTR2
DTR3
DTR4
DTR5
DTR6
DTR7
DTR8
DTR9
DTR10
DTR11
DTR12
DTR13
R/W
007A88H
to
007A8FH
007C88H
to
007C8FH
007E88H
to
007E8FH
XXXXXXXXB
to
XXXXXXXXB
Data Register 1
(8 bytes)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
007A90H
to
007A97H
007C90H
to
007C97H
007E90H
to
007E97H
XXXXXXXXB
to
XXXXXXXXB
Data Register 2
(8 bytes)
007A98H
to
007A9FH
007C98H
to
007C9FH
007E98H
to
007E9FH
XXXXXXXXB
to
XXXXXXXXB
Data Register 3
(8 bytes)
007AA0H
to
007AA7H
007CA0H
to
007CA7H
007EA0H
to
007EA7H
XXXXXXXXB
to
XXXXXXXXB
Data Register 4
(8 bytes)
007AA8H
to
007AAFH
007CA8H
to
007CAFH
007EA8H
to
007EAFH
XXXXXXXXB
to
XXXXXXXXB
Data Register 5
(8 bytes)
007AB0H
to
007AB7H
007CB0H
to
007CB7H
007EB0H
to
007EB7H
XXXXXXXXB
to
XXXXXXXXB
Data Register 6
(8 bytes)
007AB8H
to
007ABFH
007CB8H
to
007CBFH
007EB8H
to
007EBFH
XXXXXXXXB
to
XXXXXXXXB
Data Register 7
(8 bytes)
007AC0H
to
007AC7H
007CC0H
to
007CC7H
007EC0H
to
007EC7H
XXXXXXXXB
to
XXXXXXXXB
Data Register 8
(8 bytes)
007AC8H
to
007ACFH
007CC8H
to
007CCFH
007EC8H
to
007ECFH
XXXXXXXXB
to
XXXXXXXXB
Data Register 9
(8 bytes)
007AD0H
to
007AD7H
007CD0H
to
007CD7H
007ED0H
to
007ED7H
XXXXXXXXB
to
XXXXXXXXB
Data Register 10
(8 bytes)
007AD8H
to
007ADFH
007CD8H
to
007CDFH
007ED8H
to
007EDFH
XXXXXXXXB
to
XXXXXXXXB
Data Register 11
(8 bytes)
007AE0H
to
007AE7H
007CE0H
to
007CE7H
007EE0H
to
007EE7H
XXXXXXXXB
to
XXXXXXXXB
Data Register 12
(8 bytes)
007AE8H
to
007AEFH
007CE8H
to
007CEFH
007EE8H
to
007EEFH
XXXXXXXXB
to
XXXXXXXXB
Data Register 13
(8 bytes)
DS07-13752-2E
45
MB90950 Series
• List of Message Buffers (DLC Registers and Data Registers) (3)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
CAN2
007AF0H
to
007AF7H
007CF0H
to
007CF7H
007EF0H
to
007EF7H
XXXXXXXXB
to
XXXXXXXXB
Data Register 14
(8 bytes)
DTR14
DTR15
R/W
007AF8H
to
007AFFH
007CF8H
to
007CFFH
007EF8H
to
007EFFH
XXXXXXXXB
to
XXXXXXXXB
Data Register 15
(8 bytes)
R/W
46
DS07-13752-2E
MB90950 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt control
DMA
channel
number
Interrupt vector
Number Address
EI2OS
Support
register
Interrupt cause
Number
Address
Reset
N
N
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
#37
#38
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
⎯
⎯
⎯
⎯
⎯
⎯
INT9 instruction
Exception
N
CAN0 RX
N
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
CAN0 TX/NS
N
CAN1 RX/Input Capture 6
CAN1 TX/NS/Input Capture 7
CAN2 RX / I2C0
Y1
Y1
N
CAN2 TX/NS/Clock Calibration Unit
16-bit Reload Timer 0
16-bit Reload Timer 1
16-bit Reload Timer 2
16-bit Reload Timer 3
PPG0/PPG1/PPG4/PPG5
PPG2/PPG3/PPG6/PPG7
PPG8/PPG9/PPGC/PPGD
PPGA/PPGB/PPGE/PPGF
Time Base Timer
N
Y1
Y1
Y1
Y1
N
1
2
⎯
⎯
⎯
⎯
⎯
⎯
3
N
N
N
N
External Interrupt 0 to 3, 8 to 11
Watch Timer
Y1
N
⎯
4
External Interrupt 4 to 7, 12 to 15
A/D Converter
Y1
Y1
N
5
I/O Timer 0 / I/O Timer 1
Input Capture 4/5 / I2C1
Output Compare 0/1/4/5
Input Capture 0 to 3
⎯
6
Y1
Y1
Y1
Y1
Y2
Y1
Y2
Y1
7
8
Output Compare 2/3/6/7
UART0 RX
9
10
11
12
13
UART0 TX
UART1 RX/UART3 RX/UART5 RX
UART1 TX/UART3 TX/UART5 TX
0000BDH
(Continued)
DS07-13752-2E
47
MB90950 Series
(Continued)
Interrupt control
register
DMA
channel
number
Interrupt vector
Number Address
EI2OS
Support
Interrupt cause
Number
Address
UART2 RX/UART4 RX/UART6 RX
UART2 TX/UART4 TX/UART6 TX
Flash Memory
Y2
Y1
N
14
15
⎯
⎯
#39
#40
#41
#42
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
ICR14
0000BEH
ICR15
0000BFH
Delayed Interrupt
N
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service
at a time.
• When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.
48
DS07-13752-2E
MB90950 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS − 0.3
VSS + 6.0
VSS + 6.0
V
V
AVCC
VCC = AVCC*2
Power supply voltage*1
AVRH,
AVRL
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH ≥ AVRL
VSS − 0.3
VSS + 6.0
V
Input voltage*1
Output voltage*1
VI
VO
VSS − 0.3
VSS − 0.3
−4.0
VSS + 6.0
VSS + 6.0
+4.0
V
V
*3
*3
*5
Maximum Clamp Current
ICLAMP
mA
Total Maximum Clamp
Current
Σ|ICLAMP|
IOL
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
40
15
mA
mA
mA
mA
mA
mA
mA
mA
mA
*5
*4
*4
*4
*4
*4
*4
*4
*4
“L” level maximum output
current
“L” level average output
current
IOLAV
ΣIOL
4
“L” level maximum overall
output current
100
50
“L” level average overall
output current
ΣIOLAV
IOH
“H” level maximum output
current
−15
−4
“H” level average output
current
IOHAV
ΣIOH
“H” level maximum overall
output current
−100
−50
“H” level average overall
output current
ΣIOHAV
Power consumption
Operating temperature
Storage temperature
PD
⎯
430
mW
°C
−40
−40
−55
+105
+125
+150
TA
°C
*6
TSTG
°C
*1: This parameter is based on VSS = AVSS = 0 V
*2: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI
rating.
*4: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0, PA1
(Continued)
DS07-13752-2E
49
MB90950 Series
(Continued)
*5: • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47,
P50 to P55, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA1
• Use within recommended operating conditions.
• Use with DC voltage (current)
• The +B signal should always be applied by using a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied, the input current to
the microcontroller pin does not exceed the rated value, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
*6 : If used exceeding TA = + 105 °C, please consult with us due to the restricted reliability.
It is ensured to write/erase data to the Flash memory between TA = − 40 °C and + 105 °C.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
50
DS07-13752-2E
MB90950 Series
2. Recommended Operating Conditions
Condi-
(VSS = AVSS = 0 V)
Value
Typ
5.0
Parameter
Symbol
Unit
Remarks
tions
Min
3.0
4.5
3.0
Max
5.5
5.5
V
V
V
Under normal operation
Power supply
voltage
VCC,
AVCC
⎯
5.0
When External bus is used.
Maintains RAM data in stop mode
⎯
5.5
Use a ceramic capacitor or capacitor
of better AC characteristics. Capaci-
tor at the VCC should be greater than
this capacitor.
Smoothing
capacitor
CS
TA
⎯
⎯
0.1
⎯
1.0
µF
°C
−40
−40
⎯
⎯
+105
+125
MB90F952JD(S), MB90F952MD(S)
*
Operating
temperature
* : If used exceeding TA = + 105 °C, please consult with us due to the restricted reliability.
It is ensured to write/erase data to the Flash memory between TA = − 40 °C and + 105 °C.
C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
DS07-13752-2E
51
MB90950 Series
3. DC Characteristics
Sym-
Value
Typ
Parameter
Pin name
Conditions
Unit
Remarks
bol
Min
Max
Port inputs if CMOS
hysteresis input levels
are selected
VIHS
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
Port inputs if
Automotive input levels
are selected
VIHA
⎯
⎯
⎯
⎯
0.8 VCC
2.0
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
Port inputs if TTL input
levels are selected
VIHT
Input H
voltage
(At VCC =
5 V 10%)
P12,P15,
P44 to P47,
P50,P82,
P85,P90,
P94
Port inputs if
CMOS hysteresis input
levels are selected
VIHS
⎯
⎯
0.7 VCC
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
RST input pin
(CMOS hysteresis)
VIHR
RST
V
VIHM MD0 to MD2
⎯
⎯
VCC − 0.3
0.8 VCC
⎯
⎯
VCC + 0.3
V
V
MD input pin
VIHXA
X0A, X1A
⎯
Port inputs if
CMOS hysteresis input
levels are selected
VILS
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
Port inputs if
Automotive input levels
are selected
VILA
VILT
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
⎯
⎯
0.5 VCC
0.8
V
V
Port inputs if TTL input
levels are selected
Input L
voltage
(At VCC =
5 V 10%)
P12,P15,
P44 to P47,
P50,P82,
P85,P90,
P94
Port inputs if
CMOS hysteresis input
levels are selected
VILS
⎯
⎯
VSS − 0.3
⎯
⎯
0.3 VCC
0.2 VCC
V
RST input pin
(CMOS hysteresis)
VILR
RST
VSS − 0.3
V
VILM MD0 to MD2
⎯
⎯
VSS − 0.3
⎯
⎯
VSS + 0.3
0.2 VCC
V
V
MD input pin
VILXA
X0A, X1A
⎯
Output H
voltage
Normal
outputs
VCC = 4.5 V,
VOH
VCC − 0.5
VCC − 0.5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
V
V
V
V
IOH = −4.0 mA
Output H
voltage
VCC = 4.5 V,
IOH = −3.0 mA
VCC = 4.5 V,
IOL = 4.0 mA
VCC = 4.5 V,
IOL = 3.0 mA
VOHI I2C outputs
Output L
voltage
Normal
VOL
0.4
0.4
outputs
Output L
voltage
VOLI I2C outputs
⎯
(Continued)
52
DS07-13752-2E
MB90950 Series
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Remarks
Min Typ Max
Input leak
current
IIL
⎯
VCC = 5.5 V, VSS < VI < VCC
−1
⎯
+1
µA
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
Pull-up
resistance
RUP
⎯
⎯
25
50
100 kΩ
Except
Pull-down
resistance
RDOWN
MD2
25
50
40
100 kΩ Flash memory de-
vices
VCC = 5.0 V,
Internal frequency : 32 MHz,
At normal operation.
⎯
50
65
23
mA
mA
ICC
VCC = 5.0 V,
Internal frequency : 32 MHz,
At writing Flash memory/eras-
ing.
MB90F952JD(S),
MB90F952MD(S)
⎯
⎯
50
13
VCC = 5.0 V,
ICCS
Internal frequency : 32 MHz,
In Sleep mode.
mA
mA
VCC = 5.0 V,
⎯
⎯
0.4
0.3
1.0
0.9
MB90F952JD(S)
MB90F952MD(S)
Power
supply
current*
ICTS
Internal frequency : 2 MHz,
In Main Timer mode
VCC
VCC = 5.0 V,
ICTSPLL
Internal frequency : 32 MHz,
In PLL Timer mode,
external frequency = 4 MHz
⎯
4
7
mA
µA
µA
6
VCC = 5.0 V
⎯
⎯
130
68
330
200
MB90F952JD
MB90F952MD
Internal frequency : 8 kHz,
In sub operation
TA = +25°C
ICCL
VCC = 5.0 V
Internal frequency : 12.5 kHz,
In CR sub operation
TA = +25°C
⎯
170
400
MB90F952JDS
(Continued)
DS07-13752-2E
53
MB90950 Series
(Continued)
Value
Sym-
Parameter
Pin name
Conditions
VCC = 5.0 V
Internal frequency : 8 kHz,
In sub sleep
Unit
Remarks
MB90F952JD
MB90F952MD
bol
Min Typ Max
⎯
100
230
µA
⎯
40
130
TA = +25°C
ICCLS
VCC = 5.0 V
Internal frequency : 12.5 kHz,
In CR sub sleep
TA = +25°C
µA
µA
⎯
130
250
MB90F952JDS
⎯
⎯
95
35
210
110
MB90F952JD
MB90F952MD
VCC = 5.0 V
Internal frequency : 8 kHz,
In watch mode
TA = +25°C
Power
supply
current*
VCC
ICCT
VCC = 5.0 V
Internal frequency : 12.5 kHz,
In CR watch mode
TA = +25°C
⎯
130
250 µA MB90F952JDS
⎯
⎯
70
25
170
100
MB90F952JD(S)
MB90F952MD(S)
VCC = 5.0 V,
In Stop mode,
TA = +25°C
ICCH
µA
Other than C,
AVCC, AVSS,
AVRH, AVRL,
VCC, VSS
Input
capacitance
CIN
⎯
⎯
5
15
pF
* : The power supply current is measured with an external clock.
54
DS07-13752-2E
MB90950 Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 32 MHz, VSS = AVSS = 0 V)
Value
Sym-
Parameter
Condi-
tions
Pin name
Unit
Remarks
bol
Min
Typ Max
1/2 multiplied (PLL stopped)
When using an oscillation circuit
3
16
PLL multiplied by 1
When using an oscillation circuit
4
4
4
4
4
4
16
16
PLL multiplied by 2
When using an oscillation circuit
PLL multiplied by 3
When using an oscillation circuit
fC
X0, X1
⎯
⎯
10
8
MHz
Clock
frequency
PLL multiplied by 4
When using an oscillation circuit
PLL multiplied by 6
When using an oscillation circuit
5
PLL multiplied by 8
When using an oscillation circuit
4
fCL
tCYL
tCYLL
X0A, X1A
X0, X1
⎯
⎯
⎯
—
62.5
10
32.768 100
kHz
ns
⎯
333
—
When using an oscillation circuit
Clock cycle time
X0A, X1A
30.5
µs
Input clock pulse
width
PWHL,
PWLL
X0A
⎯
5
15.2
⎯
µs
Duty ratio is about 30% to 70%.
Internaloperating
clock frequency
(machine clock)
fCP
fCPL
tCP
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1.5
⎯
⎯
32
MHz When using main clock
kHz When using sub clock
8.192 50
Internaloperating
clock cycle time
(machine clock)
31.25
20
⎯
666
ns
When using main clock
When using sub clock
tCPL
122.1
⎯
µs
Internal
CR oscillation
frequency
When trimming with the clock
calibration unit
fCCR
⎯
⎯
85
100
115
kHz
DS07-13752-2E
55
MB90950 Series
• External clock input timing
t
CYLL
V
IHXA
ILXA
X0A
V
PWHL
PWLL
t
CF
tCR
• When oscillation circuit is used
tCYL
Amplitude:
It varies depending on the
external resistance, power
rating and the different kind of
device.
X0, X1
Reference values: 1 V to 2.5 V
Note: The amplitude of MB90V950JA(S) and MB90V950MA(S) are the same as VCC.
56
DS07-13752-2E
MB90950 Series
• Guaranteed PLL operation range
Guaranteed operation range
5.5
3.0
Guaranteed operation range
1.5
4
32
Internal clock fCP (MHz)
Note: When the power supply voltage is lower than the setting voltage of low voltage detection,
MB90F952JD(S) are reset.
Internal clock fCP ⎯ External clock fC
Guaranteed oscillation frequency range
× 8
× 6
× 4
× 3
× 2
× 1
32
24
×1/2
(PLL off)
16
12
8
4.0
1.5
3
4
8
12
24
16
32
External clock fC (MHz)*
* : When using a crystal oscillator or ceramic oscillator, the maximum oscillation clock frequency is 16 MHz
DS07-13752-2E
57
MB90950 Series
(2) Reset Standby Input
Value
Min
Pin Condi-
name tions
Parameter Symbol
Unit
Remarks
Max
500
⎯
ns
Under normal operation
In Stop mode, Sub Clock
mode, Sub Sleep mode
and Watch mode
Reset input
tRSTL
Oscillation time of oscillator*
RST
⎯
⎯
⎯
µs
µs
time
+ 100 µs
100
In Time Base Timer mode
* : The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. For
crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is
between several hundred µs and several ms, and for an external clock, the time is 0 ms.
• Under normal operation:
tRSTL
RST
VILR
VILR
• In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:
tRSTL
RST
VILR
VILR
90% of
amplitude
X0
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
58
DS07-13752-2E
MB90950 Series
(3) Power On Reset
Value
Pin
Parameter
Symbol
Conditions
Unit
ms
Remarks
name
Min
Max
30
Power on rise time
Power off time
tR
VCC
VCC
0.05
1
⎯
tOFF
⎯
ms Due to repetitive operation
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If you change the power supply voltage too rapidly, a power on reset may occur.
We recommend that you startup smoothly by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below. Perform
while not using the PLL clock. However, if voltage drops are within 1 V/s, you can
operate while using the PLL clock.
VCC
We recommend a rise of
50 mV/ms maximum.
3 V
Holds RAM data
VSS
(4) Clock Output Timing
Value
Pin
Parameter
Cycle time
CLK ↑ → CLK ↓
Symbol
Conditions
Unit
Remarks
name
Min
Max
⎯
tCYC
CLK
CLK
⎯
⎯
tcp*
ns
ns
ns
tcp* / 2 − 15
tcp* / 2 − 20
tcp* / 2 + 15
tcp* / 2 + 20
fCP = 25 MHz
fCP = 16 MHz
tCHCL
* : tcp is the Internal clock cycle time. Refer to “ (1) Clock Timing”.
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
DS07-13752-2E
59
MB90950 Series
(5) Bus Timing (Read)
Value
Condi-
tions
Parameter
Symbol Pin name
Unit
Remarks
Min
Max
16MHz < fcp ≤
tcp*/ 2 − 15
tcp*/ 2 − 20
⎯
ns
ns
25 MHz
ALE pulse width
tLHLL
ALE
⎯
8 MHz < fcp ≤
16 MHz
⎯
tcp*/ 2 − 35
tcp*/ 2 − 17
tcp*/ 2 − 40
⎯
⎯
⎯
ns
ns
ns
fcp ≤ 8 MHz
fcp ≤ 8 MHz
Address,
ALE
Valid address →
ALE ↓ time
tAVLL
tLLAX
tAVRL
⎯
ALE ,
Address
ALE ↓ →
Address valid time
⎯
⎯
tcp*/ 2 − 15
tcp* − 25
⎯
⎯
ns
ns
RD ,
Address
Valid address →
RD ↓ time
⎯
⎯
tcp* / 2 − 55
tcp* / 2 − 80
ns
ns
Address/
Data
Valid address →
tAVDV
tRLRH
tRLDV
⎯
⎯
⎯
Valid data input
fcp ≤ 8 MHz
3 tcp* / 2 −
16 MHz < fcp ≤
25 MHz
⎯
⎯
ns
ns
25
RD pulse width
RD
3 tcp* / 2 −
8 MHz < fcp ≤
16 MHz
20
3 tcp* / 2 − 55
3 tcp* / 2 − 80
ns
ns
RD ,
Data
RD ↓ →
Valid data input
fcp ≤ 8 MHz
RD ↑ →
RD ,
Data
tRHDX
tRHLH
tRHAX
tAVCH
tRLCH
tLLRL
⎯
⎯
⎯
⎯
⎯
⎯
0
⎯
⎯
⎯
⎯
⎯
⎯
ns
ns
ns
ns
ns
ns
Data hold time
RD ↓ →
ALE ↑ time
RD , ALE
tcp* / 2 − 15
tcp* / 2 − 10
tcp* / 2 − 17
tcp* / 2 − 17
tcp* / 2 − 15
RD ↑ →
Address valid time
Address,
RD
Address
CLK
Valid address →
CLK ↑ time
RD ↓ →
CLK ↑ time
RD,CLK
RD,ALE
ALE ↓ →
RD ↓ time
* : tcp is the Internal cycle time. Refer to “(1) Clock Timing”.
60
DS07-13752-2E
MB90950 Series
tRLCH
tAVCH
2.4 V
2.4 V
CLK
ALE
RD
tLLAX
tAVLL
tLHLL
tRHLH
2.4 V
2.4 V
0.8 V
2.4 V
tAVRL
tRLRH
2.4 V
0.8 V
tLLRL
tRHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tRLDV
tRHDX
tAVDV
2.4 V
0.8 V
VIHT
VILT
2.4 V
0.8 V
VIHT
VILT
AD15 to AD00
Address
Read data
DS07-13752-2E
61
MB90950 Series
(6) Bus Timing (Write)
Value
Condi-
tions
Parameter
Symbol Pin name
Unit
Remarks
Min
Max
Address,
WR
Valid address →
WR ↓ time
tAVWL
tWLWH
tDVWH
⎯
⎯
⎯
tcp* − 15
3 tcp* / 2 − 25
3 tcp* / 2 − 20
3 tcp* / 2 − 15
10
⎯
ns
ns
ns
ns
ns
ns
16 MHz < fcp ≤
⎯
⎯
⎯
⎯
25 MHz
WRL,
WRH
WR pulse width
8 MHz < fcp ≤
16 MHz
Data,
WR
Valid data output →
WR ↑ time
16 MHz < fcp ≤
25 MHz
WR ,
Data
WR ↑ →
Data hold time
tWHDX
⎯
8 MHz < fcp ≤
16 MHz
20
30
⎯
⎯
⎯
ns fcp ≤ 8 MHz
WR ↑ → A
ddress valid time
WR ,
Address
tWHAX
tWHLH
tWLCH
⎯
⎯
⎯
tcp* / 2 − 10
ns
WR ↑ →
ALE ↑ time
WR , ALE
WR , CLK
tcp* / 2 − 15
tcp* / 2 − 17
⎯
⎯
ns
ns
WR ↓ →
CLK ↑ time
*: tcp is the Internal operating clock cycle time. Refer to “(1) Clock Timing”.
62
DS07-13752-2E
MB90950 Series
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
tAVWL
2.4 V
2.4 V
0.8 V
tWHDX
A23 to A16
0.8 V
tDVWH
Write data
2.4 V
2.4 V
2.4 V
Address
AD15 to AD00
0.8 V
0.8 V
0.8 V
DS07-13752-2E
63
MB90950 Series
(7) Ready Input Timing
Rated Value
Sym-
Test
Parameter
Pin name
Unit
Remarks
bol
Condition
Min
Max
⎯
35
70
0
ns
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
⎯
⎯
ns fCP = 8 MHz
⎯
ns
Note : If the RDY setup time is insufficient, use the auto-ready function.
2.4 V
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHH
RDY
When WAIT
is not used.
VIHT
VIHT
RDY
When WAIT
is used.
(1 cycle)
VILT
VILT
tRYHS
64
DS07-13752-2E
MB90950 Series
(8) Hold Timing
Value
Unit
Parameter
Symbol
Pin name
Conditions
Min
30
Max
tCP*
Pin floating → HAK ↓ time
tXHAL
tHAHV
HAK
HAK
ns
ns
⎯
HAK ↓ → time → Pin valid time
tCP*
2 tCP*
* : tcp is the Internal operating clock cycle time. Refer to “(1) Clock Timing”.
Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed.
2.4 V
HAK
0.8 V
tHAHV
tXHAL
Hi-Z
2.4 V
0.8 V
2.4 V
0.8 V
Each pin
DS07-13752-2E
65
MB90950 Series
(9) UART0/1/2/3/4
ESCR : SCES = 0, ECCR : SCDE = 0
Value
Parameter
Symbol
Conditions
Unit
Min
5 tcp*
− 50
Max
⎯
Serial clock cycle time
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK↑ → SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK↑ → SIN hold time
SCK fall time
tSCYC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal shift clock
operation
CL = 80 pF + 1
TTL.
tSLOVI
+ 50
⎯
t
IVSHI
SHIXI
SLSH
SHSL
tcp* + 80
0
t
⎯
t
t
3 tcp* − t
tcp* + 10
⎯
R
⎯
⎯
External shift clock
operation
CL = 80 pF + 1
TTL.
tSLOVE
2 tcp* + 60
tIVSHE
30
⎯
⎯
10
10
tSHIXE
tcp* + 30
⎯
tF
SCK rise time
tR
⎯
*: tcp indicates the machine clock time
t
SCYC
2.4 V
SCK
0.8 V
t
SLOVI
2.4 V
SOT
SIN
0.8 V
t
IVSHI
tSHIXI
V
IH
VIL
Internal Clock Shift Operation
66
DS07-13752-2E
MB90950 Series
tSHSL
tSLSH
VIH
SCK
SOT
V
IL
tR
t
SLOVE
t
F
2.4V
0.8V
tIVSHE
tSHIXE
VIH
SIN
VIL
External Clock Shift Operation
DS07-13752-2E
67
MB90950 Series
ESCR : SCES = 1, ECCR : SCDE = 0
Parameter
Value
Symbol
Conditions
Unit
Min
5 tcp*
− 50
Max
⎯
Serial clock cycle time
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
SCK fall time
tSCYC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal shift clock
operation
CL = 80 pF + 1
TTL.
tSHOVI
+ 50
⎯
tIVSLI
tcp* + 80
0
tSLIXI
⎯
tSHSL
3 tcp* − t
R
⎯
tSLSH
tcp* + 10
⎯
External shift clock
operation
CL = 80 pF + 1
TTL.
t
SHOVE
⎯
30
2 tcp* + 60
tIVSLE
⎯
⎯
10
10
tSLIXE
tcp* + 30
⎯
tF
SCK rise time
tR
⎯
*: tcp indicates the machine clock time
tSCYC
2.4 V
SCK
0.8 V
t
SHOVI
2.4 V
0.8 V
SOT
SIN
t
IVSLI
t
SLIXI
V
IH
IL
V
Internal Clock Shift Operation
68
DS07-13752-2E
MB90950 Series
tSLSH
tSHSL
VIH
SCK
SOT
SIN
V
IL
t
SHOVE
t
F
t
R
2.4 V
0.8 V
t
IVSLE
t
SLIXE
VIH
VIL
External Clock Shift Operation
DS07-13752-2E
69
MB90950 Series
ESCR : SCES = 0, ECCR : SCDE = 1
Parameter
Value
Symbol
Conditions
Unit
Min
5 tcp*
− 50
Max
⎯
Serial clock cycle time
t
SCYC
ns
ns
ns
ns
ns
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
SOT → SCK ↓ delay time
tSHOVI
+ 50
⎯
Internal shift clock
operation
CL = 80 pF + 1
TTL.
tIVSLI
tcp* + 80
0
tSLIXI
⎯
tSOVLI
3 tcp* − 70
⎯
*: tcp indicates the machine clock time
t
SCYC
2.4 V
SCK
0.8 V
0.8 V
tSHOVI
t
SOVLI
2.4 V
2.4 V
0.8 V
SOT
SIN
0.8 V
tIVSLI
tSLIXI
V
V
IH
IL
V
V
IH
IL
70
DS07-13752-2E
MB90950 Series
ESCR : SCES = 1, ECCR : SCDE = 1
Parameter
Value
Unit
Symbol
Conditions
Min
5 tcp*
− 50
Max
Serial clock cycle time
tSCYC
⎯
ns
ns
ns
ns
ns
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
tSLOVI
+ 50
⎯
Internal clock
operation
CL = 80 pF + 1
TTL.
t
IVSHI
SHIXI
SOVHI
tcp* + 80
0
t
⎯
t
3 tcp* − 70
⎯
*: tcp indicates the machine clock time
tSCYC
2.4 V
2.4 V
SCK
0.8 V
tSLOM
tSOVHI
2.4 V
2.4 V
SOT
SIN
0.8 V
0.8 V
tIVSHI
tSHIXI
V
IH
V
IH
V
IL
V
IL
(10) Trigger Input Timing
Parameter
Value
Symbol
Pin name
Conditions
Unit
Min
Max
INT0 to INT15,
INT8R to INT15R,
ADTG
tTRGH
tTRGL
Input pulse width
⎯
5 tCP
⎯
ns
VIH
VIH
INT0 to INT15,
INT8R to INT15R,
ADTG
VIL
VIL
tTRGH
tTRGL
DS07-13752-2E
71
MB90950 Series
(11) Timer Related Resource Input Timing
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
tTIWH
tTIWL
TIN0 to TIN3,
IN0 to IN7
Input pulse width
⎯
4 tCP
⎯
ns
VIH
VIH
VIL
VIL
TIN0 to TIN3,
IN0 to IN7
tTIWH
tTIWL
(12) Timer Related Resource Output Timing
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
30
Max
TOT0 to TOT3,
PPG0 to PPGF
CLK ↑ → TOUT change time
tTO
⎯
⎯
ns
2.4 V
CLK
2.4 V
0.8 V
TOT0 to TOT3,
PPG0 to PPGF
tTO
72
DS07-13752-2E
MB90950 Series
(13) Low voltage detection
Value
Typ
Pin
Condi-
tions
Parameter
Symbol
Unit
Remarks
name
Min
3.8
Max
4.2
Detection voltage
initial value
VDL
VCC
VCC
⎯
⎯
4.0
173
⎯
V
During voltage drop
Hysteresis width
VHYS
169
− 0.1
177
+ 0.1
mV During voltage rise
dV/dt at low voltage
V/µs
reset
Power supply
voltage change
rate
dV/dt at standard
value of low voltage
detection/release
voltage
dV/dt
VCC
⎯
− 0.004
⎯
⎯
+ 0.004 V/µs
Detection delay
time
When | dV/dt | ≤
0.004 V/µs
td
⎯
⎯
⎯
3.2
µs
Note: Thepowersupplyvoltagechangerateisat0.004V/µs<|dv/dt|<0.1V/µs,aresetmaybegeneratedorreleased
after the power supply voltage is passed the detection voltage range.
Internal reset
VCC
dV
dt
VHYS
VDL
td
td
DS07-13752-2E
73
MB90950 Series
(14) I2C Timing
Fast-mode*1
Standard-mode
Parameter
Symbol Conditions
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDA↓ → SCL ↓
tHDSTA
4.0
⎯
0.6
⎯
µs
“L” width of the SCL clock
“H” width of the SCL clock
tLOW
4.7
4.0
⎯
⎯
1.3
0.6
⎯
⎯
µs
µs
tHIGH
Set-up time (repeated) START condition
SCL ↑ → SDA ↓
tSUSTA
4.7
0
⎯
3.45*3
⎯
0.6
0
⎯
0.9*4
⎯
µs
µs
ns
µs
µs
R = 1.7 kΩ,
C = 50 pF*2
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
Data set-up time
SDA ↓ ↑ → SCL ↑
tSUDAT
tSUSTO
tBUS
250
4.0
4.7
100
0.6
1.3
Set-up time for STOP condition
SCL ↑ → SDA ↑
⎯
⎯
Bus free time between a STOP and START
condition
⎯
⎯
*1: For use at over 100 kHz, set the machine clock to at least 6 MHz.
*2: R,C: Pull-up resistor and load capacitor of the SCL and SDA lines.
*3: The maximum tHDDAT meets the requirement that it does not extend the “L” width (tLOW) of the SCL signal.
*4: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
SDA
tBUS
tSUDAT
tHDSTA
tLOW
SCL
tHIGH
tHDSTA
tHDDAT
tSUSTA
tSUSTO
74
DS07-13752-2E
MB90950 Series
5. A/D Converter
(3.0 V ≤ AVRH − AVRL)
Value
Typ
⎯
Pin
Condi-
tions
Parameter
Symbol
Unit
Remarks
name
Min
⎯
Max
10
Resolution
Total error
⎯
⎯
⎯
⎯
⎯
⎯
bit
⎯
⎯
3.0
LSB
Nonlinearity
error
⎯
⎯
⎯
⎯
⎯
2.5
LSB
Differential
nonlinearity
error
⎯
⎯
⎯
⎯
⎯
1.9
LSB
AN0
to
AN23
Zero reading
voltage
AVRL −
AVRL +
AVRL +
VOT
⎯
⎯
V
V
1.5 LSB
0.5 LSB
2.5 LSB
AN0
to
AN23
Full scale
reading voltage
AVRH −
3.5 LSB
AVRH −
1.5 LSB
AVRH +
0.5 LSB
VFST
0.66
2.2
0.4
4.5 V ≤ AVCC ≤ 5.5 V
3.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
3.0 V ≤ AVCC < 4.5 V
Compare time
Sampling time
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
16500
µs
µs
∞
1.0
AN0
to
AN23
Analog port
input current
IAIN
⎯
⎯
−0.3
⎯
⎯
+0.3
µA
AN0
to
AN23
Analog input
voltage range
VAIN
AVRL
AVRH
V
⎯
⎯
IA
AVRH
AVRL
AVCC
⎯
⎯
⎯
⎯
⎯
⎯
AVRL + 2.7
⎯
⎯
AVCC
V
V
Reference
voltage range
0
AVRH − 2.7
⎯
⎯
⎯
⎯
3.5
⎯
7.5
5
mA
µA
µA
µA
Power supply
current
IAH
IR
AVCC
*
*
AVRH
AVRH
600
⎯
900
5
Reference
voltage current
IRH
Offset between
input channels
AN0 to
AN23
⎯
⎯
⎯
⎯
4
LSB
*: If the A/D convertor is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVRH = 5.0 V) .
Note: The accuracy gets worse as |AVRH − AVRL| becomes smaller.
DS07-13752-2E
75
MB90950 Series
6. Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by the A/D converter.
Non linearity
error
: The deviation between the actual conversion characteristics and a line that joins the
zero-transition line ( “00 0000 0000” ← → “00 0000 0001” ) to the full-scale transition line
( “11 1111 1110” ← → “11 1111 1111” ) .
Differential
linearity error
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an
ideal value.
Total error
: Difference between the actual value and the ideal value. The total error includes zero
transition error, full-scale transition error, and linear error.
Total error
3FFH
1.5 LSB
3FEH
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
001H
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
Total error of digital output “N” =
1 LSB (Ideal value) =
1 LSB
AVRH − AVRL
[V]
1024
N : Value of the digital output from the A/D converter
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which the digital output transitions from (N − 1) to N.
(Continued)
76
DS07-13752-2E
MB90950 Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FFH
3FEH
3FDH
Actual conversion
characteristics
(N + 1)H
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
VFST (actual
measurement
value)
NH
VNT (actual
measurement value)
004H
003H
002H
001H
V (N + 1) T
(actual measurement
value)
Actual conversion
characteristics
(N − 1)H
(N − 2)H
VNT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
VOT (actual measurement value)
Analog input
AVRL
AVRH
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
Non linearity error of digital output N =
1 LSB
V (N+1) T − VNT
−1 LSB [LSB]
1 LSB
Differential linearity error of digital output N =
1 LSB =
VFST − VOT
[V]
1022
N
: Value of the digital output from the A/D converter
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
DS07-13752-2E
77
MB90950 Series
7. Notes on A/D Converter Section
Use the device with external circuits of the following output impedance for analog inputs :
Recommended output impedance of external circuits are : Approx. 4.2 kΩ or lower (4.5 V ≤ AVCC ≤ 5.5 V,
sampling period = 0.4 µs)
If an external capacitor is used, in consideration of the capacitive voltage dividing effect between the external
capacitor and the internal on-chip capacitor, it is recommended that the capacitance of the external capacitor
be several thousand times greater than the capacitance of the internal capacitor.
If the output impedance of the external circuit is too high, a sampling period for an analog voltage may be
insufficient.
• Analog input circuit model
R
Analog input
Comparator
C
MB90F952JD(S)/F952MD(S) 4.5 V ≤ AVCC ≤ 5.5 V : R=: 4.1 kΩ, C=: 8.5 pF
3.0 V ≤ AVCC < 4.5 V : R=: 10.33 kΩ, C=: 8.5 pF
MB90V950JA(S)/V950MA(S) 4.5 V ≤ AVCC ≤ 5.5 V : R=: 2.52 kΩ, C=: 10.7 pF
Note : Use the values in the figure only as a guideline.
78
DS07-13752-2E
MB90950 Series
• The relationship between external impedance and minimum sampling time
• At 4.5 V ≤ AVCC ≤ 5.5 V
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
MB90F952MD(S),
MB90F952JD(S)
100
MB90F952MD(S),
MB90F952JD(S)
20
18
16
14
12
10
8
90
80
70
60
50
40
30
MB90V950JA(S),MB90V950MA(S)
6
MB90V950JA(S),MB90V950MA(S)
4
20
2
10
0
0
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9 10
Minimum sampling time [µs]
Minimum sampling time [µs]
Minimum sampling time [µs] (4.5 V ≤ AVCC ≤ 5.5 V)
External impedance [kΩ]
5
10
50
MB90F952MD(S),MB90F952JD(S)
MB90V950JA(S),MB90V950MA(S)
0.54
0.56
0.84
0.94
3.22
3.93
• At 3.0 V ≤ AVCC < 4.5 V
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
MB90F952MD(S),
MB90F952JD(S)
MB90F952MD(S),
MB90F952JD(S)
20
18
16
14
12
10
8
100
90
80
70
60
50
40
30
6
MB90V950JA(S),MB90V950MA(S)
4
20
MB90V950JA(S),MB90V950MA(S)
2
10
0
0
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9 10
Minimum sampling time [µs]
Minimum sampling time [µs]
Minimum sampling time [µs] (3.0 V ≤ AVCC<4.5 V)
External impedance [kΩ]
5
10
50
MB90F952MD(S),MB90F952JD(S)
MB90V950JA(S),MB90V950MA(S)
0.91
1.39
1.21
1.77
3.59
4.76
• About errors
As | AVR − AVSS | becomes smaller, values of relative errors grow larger.
DS07-13752-2E
79
MB90950 Series
8. Flash Memory Program/Erase Characteristics
Value
Parameter
Sector erase time
Chip erase time
Conditions
Unit
Remarks
Min
Typ
Max
Excludes programming
prior to erasure
⎯
0.9
3.6
s
⎯
⎯
7.2
3.6
28.8
14.4
s
s
Main Flash
Satellite Flash
⎯
Word (16-bit width)
programming time
Except for the overhead
time of the system
⎯
⎯
15
23
240
370
µs
µs
Word (16-bit width)
programming time
Except for the overhead
time of the system
TA> +85 °C
TA ≤ +85 °C
10000
⎯
⎯
⎯
⎯
cycle
cycle
Program/Erase cycle
100000
Flash Data Retention
Time
Average
TA = +85 °C
20
⎯
⎯
year
*
* : The value was converted into the normalized temperature at +85ÅãC from the results of evaluating the reliability
of the technology.
9. D/A Converter
Value
Pin
name
Parameter Symbol
Conditions
Unit
Remarks
Min
Typ
Max
Resolution
⎯
⎯
⎯
⎯
⎯
⎯
8
⎯
bit
Non linearity
error
⎯
⎯
-0.5
⎯
+0.5
LSB
⎯
⎯
0.773
2.490
0.787
2.535
1.078
3.474
CL = 20 pF
Conversion
time
⎯
µs
CL = 100 pF
Output
impedance
DA0,
DA1
RO
⎯
3.19
3.50
4.80
kΩ
IA
AVCC
AVCC
⎯
⎯
⎯
⎯
476
920
5
µA
µA
Power supply
current
IAH
⎯
80
DS07-13752-2E
MB90950 Series
■ ORDERING INFORMATION
Part number
MB90F952JDPF
Package
Remarks
MB90F952JDSPF
MB90F952MDPF
100-pin plastic QFP
(FPT-100P-M06)
MB90F952MDSPF
MB90F952JDPFV
MB90F952JDSPFV
MB90F952MDPFV
MB90F952MDSPFV
MB90V950MACR-ES
MB90V950MASCR-ES
MB90V950JACR-ES
MB90V950JASCR-ES
100-pin plastic LQFP
(FPT-100P-M20)
299-pin ceramic PGA
(PGA-299C-A01)
For evaluation
DS07-13752-2E
81
MB90950 Series
■ PACKAGE DIMENSIONS
100-pin plastic QFP
Lead pitch
0.65 mm
14.00 × 20.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
P-QFP100-14×20-0.65
Code
(Reference)
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90 0.40(.941 .016)
*
20.00 0.20(.787 .008)
80
51
81
50
0.10(.004)
17.90 0.40
(.705 .016)
*
14.00 0.20
(.551 .008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 –+00..2305
.118 +–..000184
(Mounting height)
0~8
˚
1
30
0.65(.026)
0.32 0.05
(.013 .002)
0.17 0.06
(.007 .002)
M
0.13(.005)
0.25 0.20
(.010 .008)
(Stand off)
0.80 0.20
(.031 .008)
"A"
0.88 0.15
(.035 .006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2002-2008 FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6
2002 FUJITSU LIMITED F100008S-c-5-5
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
82
DS07-13752-2E
MB90950 Series
(Continued)
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Gullwing
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00 0.20(.630 .008)SQ
*
14.00 0.10(.551 .004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +0.20
–
0.10 .059 +.008
–.004
INDEX
(Mounting height)
0.10 0.10
(.004 .004)
(Stand off)
100
26
0°~8
°
"A"
0.50 0.20
(.020 .008
0.25(.010)
)
1
25
0.60 0.15
(.024 .006)
0.50(.020)
0.20 0.05
(.008 .002)
0.145 0.055
(.0057 .0022)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2005 -2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-3-3
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13752-2E
83
MB90950 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
Changed the part numbers.
(MB90F952JB(S) → MB90F952JD(S))
(MB90F952MB(S) → MB90F952MD(S))
(MB90V340F-101/102/103/104 →
MB90V950JA(S),MB90V950MA(S))
⎯
⎯
■ PRODUCT LINEUP
Changed the Clock supervisor of MB90V950JA(S),
MB90V950MA(S)
(No → MB90V950JA(S) only)
Changed the Clock calibrationunit of MB90V950JA(S),
MB90V950MA(S)
(No → MB90V950JA(S) only)
4
Changed the Low-voltage/CPU operation detectionreset of
MB90V950JA(S), MB90V950MA(S)
(No → No
(MB90V590JA(S): CPU operation detectionreset only))
Changed the UART of MB90V950JA(S), MB90V950MA(S)
(5 channels → 7 channels)
■ PIN DESCRIPTION
■ I/O CIRCUIT TYPES
Changed the function of pin names DA0, DA1.
(Analog input pins for the D/A converter → Analog output pins for
the D/A converter)
13
17
Changed the type A.
Changed the remarks of type C and D.
(MASK ROM and evaluation products → Evaluation products)
Changed the Circuit of Type N
20
23
(TTL input → CMOS hysteresis input)
(CMOS hysteresis input → TTL input)
■ HANDLING DEVICES
■ BLOCK DIAGRAMS
Changed the “ • Using external clock”.
Changed the arrow of X0, X1.
Changed the arrow of X0A, X1A.
25, 26
32, 33
Changed as follows the BLOCK DIAGRAMS.
• MB90V950JA(S), MB90V950MA(S)
• MB90F952JD(S), MB90F952MD(S)
■ I/O MAP
Changed the resource names.
(External Interrupt 0→ DTP/External Interrupt 0)
(External Interrupt 1→ DTP/External Interrupt 1)
■ ELECTRICAL CHARACTERISTICS Changed the “Operating temperature”.
1. Absolute Maximum Ratings
49
51
2. Recommended Operating
Conditions
(Continued)
84
DS07-13752-2E
MB90950 Series
Page
Section
Change Results
3. DC Characteristics
• Deleted the row of VIHX of Input H voltage.
• Deleted the row of VILX of Input L voltage.
Changed the pin name of input H voltage (VIHR)
(⎯ → RST)
Changed the pin name of input H voltage (VIHM)
(⎯ → MD0 to MD2)
52
Changed the pin name of input L voltage (VIHR)
(⎯ → RST)
Changed the pin name of input L voltage (VIHM)
(⎯ → MD0 to MD2)
Changed the conditions of Power supply current (ICCL).
(Internal frequency : 12.5 kHz,In CR sub operation → Internal
frequency : 8 kHz,In sub operation)
53
(Internal frequency : 8 kHz,In sub opoferation → Internal fre-
quency : 12.5 kHz,In CR sub operation )
Changed the item of ICC to power supply current.
Added the items ICCL,ICCLS and ICCT.
53, 54
55
■ ELECTRICAL CHARACTERISTICS Changed the items in the table.
4. AC Characteristics
(1) Clock Timing
Changed the figure and title.
Clock timing → External clock input timing
Added the figure of “• When oscillation circuit is used”.
56
57
Changed as follows is Internal clock fCP (MHz) of “Guaranteed
PLL operation range”.
(24 → 32)
(10) Trigger Input Timing
Changed the pin name.
(INT0R to INT15R → INT8R to INT15R)
71
78
7. Notes on A/D Converter Section
Changed the "• Analog input circuit model".
8. Flash Memory Program/Erase
Characteristics
Deleted the “ TA = + 25 °C VCC = 5.0 V” in Conditions.
Changed the value of Chip erase time.
Changed the value and condition of “Program/Erase cycle”,
“Flash Data Retention Time” and the table footnote.
80
9. D/A Converter
Changed the minimum value of Output impedance.
(3.44 → 3.19)
Changed the maximum value of Power supply current.
(0.1 → 5)
(Continued)
DS07-13752-2E
85
MB90950 Series
(Continued)
Page
Section
Change Results
Changed the part numbers:
■ ORDERING INFORMATION
(MB90F952JBPF → MD90F952JDPF)
(MB90F952JBSPF → MD90F952JDSPF)
(MB90F952MBPF → MD90F952MDPF)
(MB90F952MBSPF → MD90F952MDSPF)
(MB90F952JBPFV → MD90F952JDPFV)
(MB90F952JBSPFV → MD90F952JDSPFV)
(MB90F952MBPFV → MD90F952MDPFV)
(MB90F952MBSPFV → MD90F952MDSPFV)
(MB90V950MA → MB90V950MACR-ES)
(MB90V950MA → MB90V950MASCR-ES)
(MB90V950JA → MB90V950JACR-ES)
(MB90V950JAS → MB90V950JASCR-ES)
81
The vertical lines marked in the left side of the page show the changes.
86
DS07-13752-2E
MB90950 Series
MEMO
DS07-13752-2E
87
MB90950 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
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1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
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Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
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Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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