MB95D108BWPMC [SPANSION]
Microcontroller, CMOS;
| 型号： | MB95D108BWPMC |
| 厂家： | 
SPANSION |
| 描述： | Microcontroller, CMOS 微控制器 外围集成电路 |
| 文件： | 总81页 (文件大小：2938K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Spansion® Analog and Microcontroller
Products
The following document contains information on Spansion analog and microcontroller products. Although the
document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion
will continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal document improvements and are noted in the document revision
summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a
revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “MB”. To order these products, please use
only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory, analog, and
microcontroller products and solutions.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-12617-3E
8-bit Microcontrollers
CMOS
F2MC-8FX MB95100B Series
MB95107B/F108BS/F108BW/D108BS/D108BW/
MB95FV100D-101
■ DESCRIPTION
The MB95100B series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURE
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product)
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2006-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.3
MB95100B Series
(Continued)
• Timer
• 8/16-bit compound timer × 2 channels
Can be used to interval timer, PWC timer, PWM timer and input capture.
• 16-bit reload timer × 1 channel
• 8/16-bit PPG × 2 channels
• 16-bit PPG × 2 channels
• Timebase timer × 1 channel
• Watch prescaler (for dual clock product) × 1 channel
• FRAM
2 K bytes FRAM is loaded (MB95D108BS/MB95D108BW only)
• LIN-UART × 1 channel
• LIN function, clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
• UART/SIO × 1 channel
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
• I2C × 1 channel
Built-in wake-up function
• External interrupt × 12channels
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter × 12channels
8-bit or 10-bit resolution can be selected.
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode (for dual clock product)
• Timebase timer mode
• I/O port
• The number of maximum ports
• Single clock product : 55 ports
• Dual clock product : 53 ports
• Port configuration
• General-purpose I/O ports (N-ch open drain)
Other than MB95D108BS/MB95D108BW
MB95D108BS/MB95D108BW
• General-purpose I/O ports (CMOS)
Single clock product
: 6 ports
: 4 ports
: 49 ports
: 47 ports
Dual clock product
2
DS07-12617-3E
MB95100B Series
■ PRODUCT LINEUP
Part number
MB95F108BS/
MB95F108BW
MB95D108BS/
MB95D108BW
MB95107B
Parameter
MASK ROM
product
Flash memory
product
Flash memory
product
Type
ROM capacity
RAM capacity
FRAM capacity
Reset output
48 K bytes
60 K bytes
2 K bytes
60 K bytes
No
2 K bytes
No
Selectable
Single/Dual clock*1
Clock system
Single/Dual clock*2
Single/Dual clock*2
Low voltage
detection reset
No
Number of basic instructions
Instruction bit length
Instruction length
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
CPU functions
Data bit length
Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)
Interrupt processing time : 0.6 μs (at machine clock frequency 16.25 MHz)
General purpose • Single clock product : 55 ports (N-ch open drain *4 : 4/6 ports, CMOS : 49 ports)
I/O ports
• Dual clock product : 53 ports (N-ch open drain *4 : 4/6 ports, CMOS : 47 ports)
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Reset generated cycle
Timebase timer
(1 channel)
Watchdog timer
Wild register
At main oscillation clock 10 MHz
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
: Min 105 ms
Capable of replacing 3 bytes of ROM data
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
I2C
(1 channel)
Data transfer capable in UART/SIO
Full duplex double buffer, Variable data length (5/6/7/8-bit), built-in baud rate generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
UART/SIO
(1 channel)
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN functions available as the LIN master or LIN slave.
LIN-UART
(1 channel)
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
(12 channels)
(Continued)
DS07-12617-3E
3
MB95100B Series
(Continued)
Part number
MB95F108BS/
MB95F108BW
MB95D108BS/
MB95D108BW
MB95107B
Parameter
Two clock modes and two counter operating modes can be selected. Square wave form
16-bit reload timer output
(1 channel)
Count clock : 7 internal clocks and external clock can be selected.
Counter operating mode : reload mode or one-shot mode can be selected.
Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer × 1
channel”.
Built-in timer function, PWC function, PWM function, capture function and square
wave form output
8/16-bitcompound
timer (2 channels)
Count clock : 7 internal clocks and external clock can be selected.
PWM mode or one-shot mode can be selected.
Counter operating clock : 8 selectable clock sources
Support for external trigger start
16-bit PPG
(2 channels)
Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1
channel”.
Counter operating clock : 8 selectable clock sources
8/16-bit PPG
(2 channels)
Watch counter
(for dual clock
product)
Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting
clock source 1 second and setting counter value to 60)
Watch prescaler
(for dual clock
product)
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
(1 channel)
External interrupt Interrupt by edge detection (rising, falling, or both edges can be selected.)
(12 channels)
Flash memory
Standby mode
Can be used to recover from standby modes.
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Data retention time : 20 years
Erase can be performed on each block
Boot block configuration
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
Sleep, stop, watch (for dual clock product), and timebase timer
*1 : Specify clock mode when ordering MASK ROM.
*2 : MB95F108BS/MB95D108BS is single clock and MB95F108BW/MB95D108BW is dual clock.
*3 : For details of option, refer to “■ MASK OPTION”.
*4 : MB95D108BS/D108BW contain 4 general-purpose I/O ports for N-ch open drain. Port number other than
MB95D108BS/D108BW has 6 general-purpose I/O ports for N-ch open drain.
Note : Part number of the evaluation products in MB95100B series is MB95FV100D-101. When using it, the MCU
board (MB2146-301A-E) is required.
4
DS07-12617-3E
MB95100B Series
■ SELECT OF OSCILLATION STABILIZATION WAIT TIME (MASK ROM PRODUCT ONLY)
For the MASK ROM product, you can set the mask option when ordering MASK ROM to select the initial value
of main clock oscillation stabilization wait time from among the following four values.
Note that the evaluation and Flash memory products are fixed their initial value of main clock oscillation stabili-
zation wait time at the maximum value.
Select of oscillation stabilization wait time
Remarks
(22 − 2) /FCH
(212 − 2) /FCH
(213 − 2) /FCH
(214 − 2) /FCH
0.5 μs (at main oscillation clock 4 MHz)
Approx. 1.02 ms (at main oscillation clock 4 MHz)
Approx. 2.05 ms (at main oscillation clock 4 MHz)
Approx. 4.10 ms (at main oscillation clock 4 MHz)
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95F108BS/
MB95107B
MB95D108BS/
MB95D108BW
MB95FV100D-101
MB95F108BW
Package
FPT-64P-M24
FPT-64P-M23
BGA-96P-M04
BGA-224P-M08
: Available
: Unavailable
DS07-12617-3E
5
MB95100B Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on Using Evaluation Products
The evaluation product has not only the functions of the MB95100B series but also those of other products to
support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for
peripheral resources not used by the MB95100B series are therefore access-barred. Read/write access to these
access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in
unexpected malfunctions of hardware or software.
Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are
used, the address may be read or written unexpectedly).
Also, as the read values of prohibited addresses on the evaluation product are different to the values on the
Flash memory and MASK ROM products, do not use these values in the program.
The evaluation product do not support the functions of some bits in single-byte registers. Read/write access to
these bits does not cause hardware malfunctions. The evaluation, Flash memory, and MASK ROM products are
designed to behave completely the same way in terms of hardware and software.
• Difference of Memory Spaces
If the amount of memory on the evaluation product is different from that of the Flash memory or MASK ROM
product, carefully check the difference in the amount of memory from the model to be actually used when
developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current Consumption
The current consumption of Flash memory product is greater than for MASK ROM product.
For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage are different among the evaluation, Flash memory, and MASK ROM products.
For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Difference between RST and MOD pins
The input type of RST and MOD pins is CMOS input on the Flash memory product. The RST and MOD pins
are hysteresis inputs on the MASK ROM product. A pull - down resistor is provided for the MOD pin of the MASK
ROM product.
6
DS07-12617-3E
MB95100B Series
■ PIN ASSIGNMENT
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AVcc
AVR
P64/EC1
P63/TO11
P62/TO10
P61/PPG11
P60/PPG10
P53/TRG1
P52/PPG1
P51/SDA0
P50/SCL0
P24/EC0
P23/TO01
PE3/INT13
PE2/INT12
PE1/INT11
PE0/INT10
P83
*2
P82
P81
LQFP-64
*2
P80
P71/TI0
P70/TO0
MOD
X0
P22/TO00
P21/PPG01
P20/PPG00
P14/PPG0
P13/TRG0/ADTG
X1
Vss
(FPT-64P-M03, FPT-64P-M09)
*1 : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
*2 : P50 and P51 cannot be used in MB95D108BS and MB95D108BW.
DS07-12617-3E
7
MB95100B Series
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
AVss
NC
P32
P31
P33
P65
NC
NC
P30
PE3
PE0
P83
NC
NC
P34
P35
P66
NC
NC
NC
P36
NC
NC
P40
NC
P42
P43
P41
P67
NC
A
B
C
D
E
F
G
H
J
AVR
PE1
P82
P81
P71
X0
P63
NC
AVcc
PE2
NC
P64
NC
P37
NC
P62
P61
NC
P53
P51
P50
P23
P20
NC
P60
P52
P24
P22
P14
NC
P80
P70
MOD
Vss
FBGA-96
NC
NC
PG2/
X1A*1
P21
NC
PG1/
X1
NC
PG0
Vcc
P01
P00
NC
P04
P06
P05
NC
P10
P07
X0A*1
NC/
NC
PSEL*2
NC
NC
P03
P13
P11
K
L
NC
P12
RSTX
NC
NC
P02
(BGA-96P-M04)
*1 : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
*2 : This pin becomes NC in Mask ROM product, and PSEL in flash memory product.
Connect to VCC in MB95F108BS and connect to VSS in MB95F108BW.
8
DS07-12617-3E
MB95100B Series
■ PIN DESCRIPTION
Pin no.
I/O
circuit
Pin name
Function
LQFP64*1
FBGA96*2
type*3
1
2
C2
C1
C3
D2
D1
D3
E3
E1
F1
F2
AVCC
AVR
⎯
⎯
A/D converter power supply pin
A/D converter reference input pin
3
PE3/INT13
PE2/INT12
PE1/INT11
PE0/INT10
P83
4
General-purpose I/O port
The pins are shared with the external interrupt input.
P
5
6
7
8
P82
O
H
General-purpose I/O port
9
P81
10
P80
General-purpose I/O port.
The pin is shared with 16 - bit reload timer ch.0 input.
11
12
G1
G2
P71/TI0
General-purpose I/O port.
The pin is shared with 16 - bit reload timer ch.0 output.
P70/TO0
13
14
15
16
17
18
H2
H1
J1
MOD
X0
B
A
An operating mode designation pin
Main clock input oscillation pin
Main clock input/output oscillation pin
Power supply pin (GND)
X1
J2
VSS
⎯
⎯
H
L3
K3
VCC
PG0
Power supply pin
General-purpose I/O port.
Single-system product is general-purpose port (PG2).
Dual-system product is sub clock input/output oscillation
pin (32 kHz).
19
20
H3
J4
PG2/X1A
PG1/X0A
H/A
B’
Single-system product is general-purpose port (PG1).
Dual-system product is sub clock input oscillation pin
(32 kHz).
21
22
23
24
25
26
27
28
29
L5
K5
J5
L6
K6
J7
L7
K7
L8
RST
Reset pin
P00/INT00
P01/INT01
P02/INT02
P03/INT03
P04/INT04
P05/INT05
P06/INT06
P07/INT07
General-purpose I/O port.
The pins are shared with external interrupt input. Large
current port.
C
G
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data input.
30
K8
P10/UI0
(Continued)
DS07-12617-3E
9
MB95100B Series
Pin no.
I/O
circuit
Pin name
Function
General-purpose I/O port.
LQFP64*1
FBGA96*2
type*3
31
L9
P11/UO0
The pin is shared with UART/SIO ch.0 data output.
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 clock I/O.
32
33
34
L11
K9
P12/UCK0
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 trigger input
(TRG0) and A/D converter trigger input (ADTG).
P13/TRG0/
ADTG
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 output.
J10
P14/PPG0
H
35
36
37
J11
H9
P20/PPG00
P21/PPG01
P22/TO00
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch.0 output.
H10
General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch.0
output.
38
H11
P23/TO01
General-purpose I/O port.
39
G10
P24/EC0
The pin is shared with 8/16-bit compound timer ch.0
clock input.
General-purpose I/O port (Except MB95D108BS and
MB95D108BW).
40
41
G11
F11
P50/SCL0
P51/SDA0
The pin is shared with I2C ch.0 clock I/O.
I
General-purpose I/O port (Except MB95D108BS and
MB95D108BW).
The pin is shared with I2C ch.0 data I/O.
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.1 output.
42
43
F10
E11
P52/PPG1
P53/TRG1
H
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.1 trigger input.
44
45
46
E10
E9
P60/PPG10
P61/PPG11
P62/TO10
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch.1 output.
D9
General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch.1
output.
47
C11
P63/TO11
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.1
clock input.
K
48
C10
P64/EC1
General-purpose I/O port.
The pin is shared with LIN-UART clock I/O.
49
50
A11
A10
P65/SCK
P66/SOT
General-purpose I/O port.
The pin is shared with LIN-UART data output.
(Continued)
10
DS07-12617-3E
MB95100B Series
(Continued)
Pin no.
I/O
circuit
Pin name
Function
LQFP64*1
FBGA96*2
type*3
General-purpose I/O port.
The pin is shared with LIN-UART data input.
51
A9
P67/SIN
L
52
53
54
55
56
57
58
59
60
61
62
63
64
B8
A8
C8
A7
C7
A6
C5
B5
C4
A4
B4
B3
A1
P43/AN11
P42/AN10
P41/AN09
P40/AN08
P37/AN07
P36/AN06
P35/AN05
P34/AN04
P33/AN03
P32/AN02
P31/AN01
P30/AN00
AVSS
General-purpose I/O port.
The pins are shared with A/D converter analog input.
J
⎯
⎯
A/D converter power supply pin (GND)
Internally connected pins for MASK ROM products.
Be sure to leave it open.
Connect VCC in MB95F108BS, and VSS in MB95F108BW
for the Flash memory products.
⎯
K2
NC/PSEL
A2, A3, A5,
B1, B2,
B6,B7, B9,
B10,B11,
C6, C9,D10,
D11,E2, F3,
F9,G3, G9,
J3,J6, J8,
J9,K1, K4,
K10,K11,
L1, L2,L4,
L10
Internally connected pins.
Be sure to leave it open.
⎯
NC
⎯
*1 : FPT-64P-M24, FPT-64P-M23
*2 : BGA-96P-M04
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
DS07-12617-3E
11
MB95100B Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Oscillation circuit
A
• High-speed side
Feedback resistance value : approx. 1 MΩ
• Low-speed side
X1 (X1A)
X0 (X0A)
Clock
input
N-ch
Feedback resistance : approx. 24 MΩ
(Evaluation product : approx. 10 MΩ)
Dumping resistance : approx. 144 kΩ
(Evaluation product : without dumping
resistance)
Standby control
B
• Only for input
Mode input
Reset input
Hysteresis input onlyfor MASK ROM product
With pull-down resistor only for MASK ROM
product
R
B’
C
Hysteresis input only for MASK ROM product
• CMOS output
P-ch
N-ch
• Hysteresis input
Digital output
Digital output
Hysteresis
input
Standby control
External interrupt
enable
G
• CMOS output
• CMOS input
• Hysteresis input
• With pull-up control
R
P-ch
Pull-up control
P-ch
N-ch
Digital output
Digital output
CMOS input
Hysteresis
input
Standby control
H
• CMOS output
• Hysteresis input
• With pull-up control
R
P-ch
Pull-up control
P-ch
N-ch
Digital output
Digital output
Hysteresis
input
Standby control
(Continued)
12
DS07-12617-3E
MB95100B Series
Type
Circuit
Remarks
I
• N-ch open drain output
• CMOS input
• Hysteresis input
• P-ch transistor is existed in MB95D108BS
and MB95D108BW.
P-ch
N-ch
Digital output
CMOS input
Hysteresis
input
Standby control
J
• CMOS output
• Hysteresis input
• Analog input
R
P-ch
Pull-up control
P-ch
N-ch
• With pull-up control
Digital output
Digital output
Analog input
Hysteresis
input
A/D control
Standby control
K
• CMOS output
• Hysteresis input
P-ch
N-ch
Digital output
Digital output
Hysteresis
input
Standby control
L
• CMOS output
• CMOS input
• Hysteresis input
P-ch
N-ch
Digital output
Digital output
CMOS input
Hysteresis
input
Standby control
Standby control
O
• N-ch open drain output
• Hysteresis input
Digital output
N-ch
Hysteresis
input
(Continued)
DS07-12617-3E
13
MB95100B Series
(Continued)
Type
Circuit
Remarks
P
• CMOS output
• Hysteresis input
• With pull-up control
R
P-ch
Pull-up control
Digital output
P-ch
N-ch
Digital output
Hysteresis
input
Standby control
External
interrupt control
14
DS07-12617-3E
MB95100B Series
■ HANDLING DEVICES
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
and VSS pins.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
Also, take care to prevent the analog power supply voltage (AVCC , AVR) and analog input voltage from exceeding
the digital power supply voltage (VCC) when the analog system power supply is turned on or off.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range
of the VCC power-supply voltage.
For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range
(50/60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient
variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from sub clock mode or stop mode.
• Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
DS07-12617-3E
15
MB95100B Series
■ PIN CONNECTION
• Treatment of Unused Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent
damage.
Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/
output pins may be set to output mode and left open, or set to input mode and treated the same as unused input
pins. If there is an unused output pin, make it open.
• Treatment of Power Supply Pins on A/D Converter
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 μF ceramic capacitor
as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS pins
near this device.
• Mode Pin (MOD)
Connect the MOD pin directly to VCC or VSS pins.
To prevent the device unintentionally entering the test mode due to noise, lay out the printed circuit board so as
to minimize the distance from the MOD pin to VCC or VSS pins and to provide a low-impedance connection.
• Analog Power Supply
Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00
to AN11 pins.
• Precautions for Use of FRAM
When the device is connected to I2C external pins (SCL0 and SDA0) , the device with the same slave addresses
(1010000B to 1010111B) as built-in FRAM cannot be used.
When built-in FRAM is used without connecting the device to I2C external pins, external pull-up resistor (1.1 kΩ
or more) should be connected to SCL0 and SDA0 pins.
P50 and P51 cannot be used in MB95D108BS and MB95D108BW.
16
DS07-12617-3E
MB95100B Series
■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL
PROGRAMMER
• Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
TEF110-108F35AP
Parallel programmers
FPT-64P-M24
FPT-64P-M23
BGA-96P-M04
AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)
AF9723+AF9834 (Ver 02.08E or more)
TEF110-108F36AP
TEF110-95F108-BGL
Note : For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector Configuration
The individual sectors of Flash memory correspond to addresses used for CPU access and programming by
the parallel programmer as follows:
Flash memory
CPU address
1000H
Programmer address*
71000H
SA1 (4K bytes)
1FFFH
2000H
71FFFH
72000H
SA2 (4K bytes)
SA3 (4K bytes)
SA4 (16K bytes)
SA5 (16K bytes)
SA6 (4K bytes)
SA7 (4K bytes)
SA8 (4K bytes)
SA9 (4K bytes)
2FFFH
3000H
72FFFH
73000H
3FFFH
4000H
73FFFH
74000H
7FFFH
8000H
77FFFH
78000H
BFFFH
C000H
7BFFFH
7C000H
CFFFH
D000H
7CFFFH
7D000H
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash
memory.
• Programming Method
1) Set the type code of the parallel programmer to 17226.
2) Load program data to parallel programmer addresses 71000H to 7FFFFH.
3) Programmed by parallel programmer
DS07-12617-3E
17
MB95100B Series
■ BLOCK DIAGRAM
F2MC-8FX CPU
RST
Reset control
Clock control
ROM
RAM
X0,X1
PG2/X1A*1
PG1/X0A*1
PG0
Interrupt control
Wild register
Watch prescaler
Watch counter
P00/INT00 to P07/INT07
P52/PPG1
P53/TRG1
External interrupt ch.0 to ch.7
16-bit PPG ch.1
P10/UI0
P11/UO0
P12/UCK0
UART/SIO
P60/PPG10
P61/PPG11
8/16-bit PPG ch.1
P13/TRG0/ADTG
P14/PPG0
P62/TO10
P63/TO11
P64/EC1
16-bit PPG ch.0
8/16-bit compound
timer ch.1
P20/PPG00
P21/PPG01
8/16-bit PPG ch.0
P65/SCK
P66/SOT
P67/SIN
LIN-UART
P22/TO00
P23/TO01
P24/EC0
8/16-bit compound
timer ch.0
P70/TO0
P71/TI0
16-bit reload timer
P30/AN00 to P37/AN07
P40/AN08 to P43/AN11
P80 to P83
8/10-bit A/D
converter
AVCC
AVSS
AVR
PE0/INT10 to PE3/INT13
External interrupt ch.8 to ch.11
P50/SCL0*2
P51/SDA0*2
I2C
FRAM*3
Port
Port
Other pins
MOD, VCC, VSS
*1 : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
*2 : P50 and P51 cannot be used in MB95D108BS, and MB95D108BW.
*3 : MB95D108BS and MB95D108BW only
18
DS07-12617-3E
MB95100B Series
■ CPU CORE
1. Memory space
Memory space of the MB95100B series is 64 Kbytes and consists of I/O area, data area, and program area.
The memory space includes special-purpose areas such as the general-purpose registers and vector table.
Memory map of the MB95100B series is shown below.
• Memory Map
MB95F108BS
MB95F108BW
MB95D108BS
MB95D108BW
MB95107B
I/O
MB95FV100D-101
I/O
0000H
0000H
0000H
I/O
0080H
0100H
0200H
0080H
0100H
0200H
0080H
0100H
0200H
RAM 2 Kbytes
Register
RAM 2 Kbytes
Register
RAM 3.75 Kbytes
Register
0880H
0F80H
0880H
0F80H
Access
prohibited
Access
prohibited
0F80H
1000H
Extended I/O
Extended I/O
Extended I/O
1000H
1000H
Access
prohibited
Flash
Flash
memory
60 Kbytes
memory
60 Kbytes
4000H
FFFFH
MASK ROM
48 Kbytes
FFFFH
FFFFH
DS07-12617-3E
19
MB95100B Series
2. Register
The MB95100B series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as follows:
Program counter (PC)
: A 16-bit register to indicate locations where instructions are stored
Accumulator (A)
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower 1 byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower 1 byte is used.
Index register (IX)
Extra pointer (EP)
Stack pointer (SP)
Program status (PS)
: A 16-bit register for index modification
: A 16-bit pointer to point to a memory address
: A 16-bit register to indicate a stack area
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register
Initial Value
16-bit
FFFDH
0000H
0000H
0000H
0000H
0000H
0030H
: Program counter
: Accumulator
PC
A
T
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.)
• Structure of the program status
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R4
R3
R2
R1
R0 DP2 DP1 DP0
H
I
IL1
IL0
N
Z
PS
C
V
RP
DP
CCR
20
DS07-12617-3E
MB95100B Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP upper
OP code lower
"0" "0" "0" "0" "0" "0" "0" "1"
R4 R3 R2 R1 R0 b2
b1
b0
Generated address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
0000H to 007FH (without mapping)
0080H to 00FFH (without mapping)
0100H to 017FH
XXXB (no effect to mapping)
0000H to 007FH
000B (initial value)
001B
010B
011B
100B
101B
110B
111B
0180H to 01FFH
0200H to 027FH
0080H to 00FFH
0280H to 02FFH
0300H to 037FH
0380H to 03FFH
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
I flag
Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
:
:
:
Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is cleared to “0” when reset.
IL1, IL0
Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
IL1
0
IL0
0
Interrupt level
Priority
0
1
2
3
High
0
1
1
0
Low = no interruption
1
1
N flag
Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
:
Z flag : Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
V flag
Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
:
C flag
Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
:
DS07-12617-3E
21
MB95100B Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8-
register. Up to a total of 32 banks can be used on the MB95100B series. The bank currently in use is specified
by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)
to general-purpose register 7 (R7).
• Register Bank Configuration
8-bit
1F8H
This address = 0100H + 8 × (RP)
R0
Address 100H
R0
R1
R1
R2
R3
R4
R5
R6
R7
R0
R1
R2
R3
R4
R5
R6
R7
R2
R3
R4
R5
R6
R7
1FFH
Bank 31
107H
32 banks
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
Bank 0
Memory area
22
DS07-12617-3E
MB95100B Series
■ FRAM
• Slave address of FRAM
FRAM operates as one of the slave devices connected to the I2C, and the I2C is used to read from or write to FRAM.
When data is transferred by the I2C, the slave address of FRAM is shown below.
Slave address (7 bits)
R/W bit
(1 bit)
Slave ID (4 bits)
Page select bit* (3 bits)
000B : page 0
001B : page 1
010B : page 2
011B : page 3
100B : page 4
101B : page 5
110B : page 6
111B : page 7
0 : at write
1 : at read
1
0
1
0
* : Page select bit : Set the value corresponding to the accessed page
• Memory configuration of FRAM
The capacitance of the built-in FRAM is 2 Kbytes. The memory configuration of FRAM consists of 8 pages as
follows. The capacitance of each page is 256 bytes.
Page
Address
00H to FFH
00H to FFH
00H to FFH
00H to FFH
00H to FFH
00H to FFH
00H to FFH
00H to FFH
Capacitance
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
0
1
2
3
4
5
6
7
DS07-12617-3E
23
MB95100B Series
• Single byte write
Start Condition
Address & Data
MSB LSB
Stop Condition
LSB
Microcontroller
MSB
LSB
Slave Address 0
MSB
S
A
Address
A
Data Byte
A
P
FRAM
Acknowledge
• Compound byte write
Start Condition
MSB
Address & Data
MSB LSB
Stop Condition
LSB
Microcontroller
LSB
MSB
LSB
MSB
S
Slave Address 0
A
Address
A
Data Byte
A
Data Byte
A P
FRAM
Acknowledge
• Current address read
Start Condition
No Acknowledge
Address
Stop Condition
Microcontroller
MSB
LSB
MSB
LSB
Slave Address 1
Data Byte
S
A
1
P
FRAM
Acknowledge
Data
• Continuous address read
Start Condition
Address
No Acknowledge
Acknowledge
LSB MSB
Stop Condition
Microcontroller
MSB
LSB
MSB
LSB
Slave Address 1
Data Byte
Data Byte
S
A
A
1 P
FRAM
Acknowledge
Data
• Select (random) read
Start Condition
Address
MSB
No Acknowledge
Start Condition
Address
Acknowledge
Stop
Condition
Microcontroller
FRAM
MSB
LSB MSB
LSB
LSB MSB
LSB MSB
LSB
A
A S
A
A
Data Byte 1 P
Slave Address 1
Data Byte
S
Slave Address 0
Address
Data
Acknowledge
Notes : • When the device is connected to I2C external pins (SCL0 and SDA0) , the device with the same addresses
(1010000B to 1010111B) as built-in FRAM cannot be used.
• When FRAM is used without connecting the device built into the pull-up resistor to I2C external pins,
external pull-up resistor (1.1 kΩ or more) should be connected to SCL0 and SDA0 pins.
• P50 and P51 cannot be used in MB95D108BS and MB95D108BW.
24
DS07-12617-3E
MB95100B Series
■ I/O MAP
Register
abbreviation
Address
Register name
R/W
Initial value
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
0010H
0011H
0012H
0013H
0014H
0015H
0016H
0017H
0018H
0019H
001AH
001BH
PDR0
DDR0
PDR1
DDR1
⎯
Port 0 data register
Port 0 direction register
Port 1 data register
R/W
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
00000000B
⎯
Port 1 direction register
(Disabled)
WATR
PLLC
SYCC
STBC
RSRR
TBTC
WPCR
WDTC
⎯
Oscillation stabilization wait time setting register
PLL control register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⎯
11111111B
00000000B
1010X011B
00000000B
XXXXXXXXB
00000000B
00000000B
00000000B
⎯
System clock control register
Standby control register
Reset source register
Timebase timer control register
Watch prescaler control register
Watchdog timer control register
(Disabled)
PDR2
DDR2
PDR3
DDR3
PDR4
DDR4
PDR5
DDR5
PDR6
DDR6
PDR7
DDR7
PDR8
DDR8
Port 2 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Port 2 direction register
Port 3 data register
Port 3 direction register
Port 4 data register
Port 4 direction register
Port 5 data register
Port 5 direction register
Port 6 data register
Port 6 direction register
Port 7 data register
Port 7 direction register
Port 8 data register
Port 8 direction register
001CH
to
0025H
⎯
(Disabled)
⎯
⎯
0026H
0027H
PDRE
DDRE
Port E data register
R/W
R/W
00000000B
00000000B
Port E direction register
0028H,
0029H
⎯
(Disabled)
⎯
⎯
002AH
PDRG
Port G data register
R/W
00000000B
(Continued)
DS07-12617-3E
25
MB95100B Series
Register
Address
Register name
R/W Initial value
abbreviation
002BH
002CH
002DH
002EH
002FH
0030H
0031H
0032H
0033H
0034H
0035H
0036H
0037H
0038H
0039H
003AH
003BH
003CH
003DH
003EH
003FH
DDRG
⎯
Port G direction register
(Disabled)
R/W
⎯
00000000B
⎯
PUL1
Port 1 pull - up register
R/W
R/W
R/W
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
⎯
PUL2
Port 2 pull - up register
PUL3
Port 3 pull - up register
PUL4
Port 4 pull - up register
PUL5
Port 5 pull - up register
PUL7
Port 7 pull - up register
⎯
(Disabled)
PULE
Port E pull - up register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
PULG
T01CR1
T00CR1
T11CR1
T10CR1
PC01
Port G pull - up register
8/16-bit compound timer 01 control status register 1 ch.0
8/16-bit compound timer 00 control status register 1 ch.0
8/16-bit compound timer 11 control status register 1 ch.1
8/16-bit compound timer 10 control status register 1 ch.1
8/16-bit PPG1 control register ch.0
8/16-bit PPG0 control register ch.0
8/16-bit PPG1 control register ch.1
8/16-bit PPG0 control register ch.1
16-bit reload timer control status register (Upper byte) ch.0
16-bit reload timer control status register (Lower byte) ch.0
PC00
PC11
PC10
TMCSRH0
TMCSRL0
0040H,
0041H
⎯
(Disabled)
⎯
⎯
0042H
0043H
0044H
0045H
PCNTH0
PCNTL0
PCNTH1
PCNTL1
16-bit PPG control status register (Upper byte) ch.0
16-bit PPG control status register (Lower byte) ch.0
16-bit PPG control status register (Upper byte) ch.1
16-bit PPG control status register (Lower byte) ch.1
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
0046H,
0047H
⎯
(Disabled)
⎯
⎯
0048H
0049H
004AH
004BH
004CH
004DH
EIC00
EIC10
EIC20
EIC30
EIC01
EIC11
External interrupt circuit control register ch.0/ch.1
External interrupt circuit control register ch.2/ch.3
External interrupt circuit control register ch.4/ch.5
External interrupt circuit control register ch.6/ch.7
External interrupt circuit control register ch.8/ch.9
External interrupt circuit control register ch.10/ch.11
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
(Continued)
26
DS07-12617-3E
MB95100B Series
Register
abbreviation
Address
Register name
R/W Initial value
004EH,
004FH
⎯
(Disabled)
⎯
⎯
0050H
0051H
0052H
0053H
0054H
0055H
0056H
0057H
0058H
0059H
005AH
SCR
SMR
LIN-UART serial control register
LIN-UART serial mode register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
00000000B
00000000B
00001000B
00000000B
00000100B
000000XXB
00000000B
00100000B
00000001B
00000000B
00000000B
SSR
LIN-UART serial status register
RDR/TDR
ESCR
ECCR
SMC10
SMC20
SSR0
LIN-UART reception/transmission data register
LIN-UART extended status control register
LIN-UART extended communication control register
UART/SIO serial mode control register 1 ch.0
UART/SIO serial mode control register 2 ch.0
UART/SIO serial status register ch.0
TDR0
UART/SIO serial output data register ch.0
UART/SIO serial input data register ch.0
RDR0
005BH
to
005FH
⎯
(Disabled)
⎯
⎯
0060H
0061H
0062H
0063H
0064H
0065H
IBCR00
IBCR10
IBSR0
IDDR0
IAAR0
ICCR0
I2C bus control register 0 ch.0
I2C bus control register 1 ch.0
I2C bus status register ch.0
I2C data register ch.0
R/W
R/W
R
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
R/W
R/W
R/W
I2C address register ch.0
I2C clock control register ch.0
0066H
to
006BH
⎯
(Disabled)
⎯
⎯
006CH
006DH
006EH
006FH
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
ADC1
ADC2
ADDH
ADDL
WCSR
⎯
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register (Upper byte)
8/10-bit A/D converter data register (Lower byte)
Watch counter status register
R/W
R/W
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
00000000B
00000000B
⎯
(Disabled)
FSR
Flash memory status register
R/W
R/W
R/W
⎯
000X0000B
00000000B
00000000B
⎯
SWRE0
SWRE1
⎯
Flash memory sector writing control register 0
Flash memory sector writing control register 1
(Disabled)
WREN
WROR
Wild register address compare enable register
Wild register data test setting register
R/W
R/W
00000000B
00000000B
(Continued)
DS07-12617-3E
27
MB95100B Series
Register
Address
Register name
R/W Initial value
abbreviation
Mirror of register bank pointer (RP) and
direct bank pointer (DP)
0078H
⎯
⎯
⎯
0079H
007AH
007BH
007CH
007DH
007EH
007FH
0F80H
0F81H
0F82H
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
ILR0
ILR1
Interrupt level setting register 0
Interrupt level setting register 1
R/W
R/W
R/W
R/W
R/W
R/W
⎯
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
⎯
ILR2
Interrupt level setting register 2
ILR3
Interrupt level setting register 3
ILR4
Interrupt level setting register 4
ILR5
Interrupt level setting register 5
⎯
(Disabled)
WRARH0
WRARL0
WRDR0
WRARH1
WRARL1
WRDR1
WRARH2
WRARL2
WRDR2
Wild register address setting register (Upper byte) ch.0
Wild register address setting register (Lower byte) ch.0
Wild register data setting register ch.0
Wild register address setting register (Upper byte) ch.1
Wild register address setting register (Lower byte) ch.1
Wild register data setting register ch.1
Wild register address setting register (Upper byte) ch.2
Wild register address setting register (Lower byte) ch.2
Wild register data setting register ch.2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
0F89H
to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
0F93H
0F94H
0F95H
T01CR0
T00CR0
T01DR
T00DR
8/16-bit compound timer 01 control status register 0 ch.0
8/16-bit compound timer 00 control status register 0 ch.0
8/16-bit compound timer 01 data register ch.0
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
8/16-bit compound timer 00 data register ch.0
8/16-bit compound timer 00/01 timer mode control register
ch.0
0F96H
TMCR0
R/W
00000000B
0F97H
0F98H
0F99H
0F9AH
T11CR0
T10CR0
T11DR
T10DR
8/16-bit compound timer 11 control status register 0 ch.1
8/16-bit compound timer 10 control status register 0 ch.1
8/16-bit compound timer 11 data register ch.1
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
8/16-bit compound timer 10 data register ch.1
8/16-bit compound timer 10/11 timer mode control register
ch.1
0F9BH
TMCR1
R/W
00000000B
0F9CH
0F9DH
0F9EH
0F9FH
PPS01
PPS00
PDS01
PDS00
8/16-bit PPG1 cycle setting buffer register ch.0
8/16-bit PPG0 cycle setting buffer register ch.0
8/16-bit PPG1 duty setting buffer register ch.0
8/16-bit PPG0 duty setting buffer register ch.0
R/W
R/W
R/W
R/W
11111111B
11111111B
11111111B
11111111B
(Continued)
28
DS07-12617-3E
MB95100B Series
Register
abbreviation
Address
Register name
R/W Initial value
0FA0H
0FA1H
0FA2H
0FA3H
0FA4H
0FA5H
PPS11
PPS10
PDS11
PDS10
PPGS
REVC
8/16-bit PPG1 cycle setting buffer register ch.1
8/16-bit PPG0 cycle setting buffer register ch.1
8/16-bit PPG1 duty setting buffer register ch.1
8/16-bit PPG0 duty setting buffer register ch.1
8/16-bit PPG start register
R/W
R/W
R/W
R/W
R/W
R/W
11111111B
11111111B
11111111B
11111111B
00000000B
00000000B
8/16-bit PPG output inversion register
TMRH0/
TMRLRH0
16-bit timer register (Upper byte) ch.0/
16-bit reload register (Upper byte) ch.0
0FA6H
0FA7H
R/W
R/W
⎯
00000000B
00000000B
⎯
TMRL0/
TMRLRL0
16-bit timer register (Lower byte) ch.0/
16-bit reload register (Lower byte) ch.0
0FA8H,
0FA9H
⎯
(Disabled)
0FAAH
0FABH
0FACH
0FADH
0FAEH
0FAFH
0FB0H
0FB1H
0FB2H
0FB3H
0FB4H
0FB5H
PDCRH0
PDCRL0
PCSRH0
PCSRL0
PDUTH0
PDUTL0
PDCRH1
PDCRL1
PCSRH1
PCSRL1
PDUTH1
PDUTL1
16-bit PPG down counter register (Upper byte) ch.0
16-bit PPG down counter register (Lower byte) ch.0
16-bit PPG cycle setting buffer register (Upper byte) ch.0
16-bit PPG cycle setting buffer register (Lower byte) ch.0
16-bit PPG duty setting buffer register (Upper byte) ch.0
16-bit PPG duty setting buffer register (Lower byte) ch.0
16-bit PPG down counter register (Upper byte) ch.1
16-bit PPG down counter register (Lower byte) ch.1
16-bit PPG cycle setting buffer register (Upper byte) ch.1
16-bit PPG cycle setting buffer register (Lower byte) ch.1
16-bit PPG duty setting buffer register (Upper byte) ch.1
16-bit PPG duty setting buffer register (Lower byte) ch.1
R
00000000B
00000000B
11111111B
11111111B
11111111B
11111111B
00000000B
00000000B
11111111B
11111111B
11111111B
11111111B
R
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
0FB6H
to
0FBBH
⎯
(Disabled)
⎯
⎯
0FBCH
0FBDH
BGR1
BGR0
LIN-UART baud rate generator register 1
LIN-UART baud rate generator register 0
R/W
R/W
00000000B
00000000B
UART/SIO dedicated baud rate generator
prescaler select register ch.0
0FBEH
0FBFH
PSSR0
BRSR0
⎯
R/W
R/W
⎯
00000000B
00000000B
UART/SIO dedicated baud rate generator baud rate
setting register ch.0
0FC0H,
0FC1H
(Disabled)
⎯
0FC2H
0FC3H
AIDRH
AIDRL
A/D input disable register (Upper byte)
A/D input disable register (Lower byte)
R/W
R/W
00000000B
00000000B
(Continued)
DS07-12617-3E
29
MB95100B Series
(Continued)
Register
Address
Register name
R/W Initial value
abbreviation
0FC4H
to
0FE2H
⎯
WCDR
⎯
(Disabled)
Watch counter data register
(Disabled)
⎯
R/W
⎯
⎯
00111111B
⎯
0FE3H
0FE4H
to
0FEDH
0FEEH
0FEFH
ILSR
Input level select register
R/W
R/W
00000000B
01000000B
WICR
Interrupt pin control register
0FF0H
to
0FFFH
⎯
(Disabled)
⎯
⎯
• R/W access symbols
R/W : Readable/Writable
R
: Read only
: Write only
W
• Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
30
DS07-12617-3E
MB95100B Series
■ INTERRUPT SOURCE TABLE
Vector table address
Same level
Bit name of
Interrupt
request
number
priority order
Interrupt source
interrupt level
(atsimultaneous
setting register
occurrence)
Upper
FFFAH
FFF8H
FFF6H
FFF4H
Lower
FFFBH
FFF9H
FFF7H
FFF5H
External interrupt ch.0
External interrupt ch.4
External interrupt ch.1
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
UART/SIO ch.0
High
IRQ0
IRQ1
IRQ2
IRQ3
L00 [1 : 0]
L01 [1 : 0]
L02 [1 : 0]
L03 [1 : 0]
IRQ4
IRQ5
FFF2H
FFF0H
FFEEH
FFECH
FFEAH
FFE8H
FFE6H
FFE4H
FFE2H
FFE0H
FFDEH
FFDCH
FFDAH
FFD8H
FFD6H
FFD4H
FFD2H
FFF3H
FFF1H
FFEFH
FFEDH
FFEBH
FFE9H
FFE7H
FFE5H
FFE3H
FFE1H
FFDFH
FFDDH
FFDBH
FFD9H
FFD7H
FFD5H
FFD3H
L04 [1 : 0]
L05 [1 : 0]
L06 [1 : 0]
L07 [1 : 0]
L08 [1 : 0]
L09 [1 : 0]
L10 [1 : 0]
L11 [1 : 0]
L12 [1 : 0]
L13 [1 : 0]
L14 [1 : 0]
L15 [1 : 0]
L16 [1 : 0]
L17 [1 : 0]
L18 [1 : 0]
L19 [1 : 0]
L20 [1 : 0]
8/16-bit compound timer ch.0 (Lower)
8/16-bit compound timer ch.0 (Upper)
LIN-UART (reception)
LIN-UART (transmission)
8/16-bit PPG ch.1 (Lower)
8/16-bit PPG ch.1 (Upper)
16-bit reload timer ch.0
8/16-bit PPG ch.0 (Upper)
8/16-bit PPG ch.0 (Lower)
8/16-bit compound timer ch.1 (Upper)
16-bit PPG ch.0
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
IRQ20
I2C ch.0
16-bit PPG ch.1
8/10-bit A/D converter
Timebase timer
Watch timer/Watch counter
External interrupt ch.8
External interrupt ch.9
External interrupt ch.10
External interrupt ch.11
8/16-bit compound timer ch.1 (Lower)
Flash memory
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
L22 [1 : 0]
IRQ22
IRQ23
FFCEH
FFCCH
FFCFH
FFCDH
L23 [1 : 0]
Low
DS07-12617-3E
31
MB95100B Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Power supply voltage*1
Input voltage*1
Symbol
Unit
Remarks
Min
Max
VCC
AVCC
VSS − 0.3
VSS + 4.0
*2
*2
V
AVR
VI1
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
− 2.0
VSS + 4.0
VSS + 4.0
VSS + 6.0
VSS + 4.0
+ 2.0
Other than P80 to P83*3
V
V
VI2
P80 to P83
*3
Output voltage*1
VO
Maximum clamp current
ICLAMP
mA Applicable to pins*4
Total maximum clamp
current
Σ|ICLAMP|
⎯
⎯
20
mA Applicable to pins*4
IOL1
IOL2
15
15
Other than P00 to P07
“L” level maximum
output current
mA
P00 to P07
Other than P00 to P07
Average output current =
operating current × operating ratio
IOLAV1
4
(1 pin)
“L” level average
current
⎯
mA
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
IOLAV2
12
“L” level total maximum
output current
ΣIOL
⎯
⎯
100
50
mA
Total average output current =
mA operating current × operating ratio
(Total of pins)
“L” level total average
output current
ΣIOLAV
IOH1
IOH2
− 15
− 15
Other than P00 to P07
“H” level maximum
output current
⎯
mA
P00 to P07
Other than P00 to P07
Average output current =
operating current × operating ratio
IOHAV1
− 4
− 8
(1 pin)
“H” level average
current
⎯
mA
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
IOHAV2
“H” level total maximum
output current
ΣIOH
⎯
⎯
− 100
− 50
mA
Total average output current =
mA operating current × operating ratio
(Total of pins)
“H” level total average
output current
ΣIOHAV
(Continued)
32
DS07-12617-3E
MB95100B Series
(Continued)
Parameter
Rating
Symbol
Unit
Remarks
Min
⎯
Max
320
Power consumption
Pd
TA
mW
Operating temperature
− 40
+ 85
°C
MB95107B, MB95F108BS,
MB95F108BW
− 55
− 40
+ 150
+ 125
Storage temperature
TSTG
°C
MB95D108BS, MB95D108BW
*1 : The parameter is based on AVSS = VSS = 0.0 V.
*2 : Apply equal potential to AVCC and VCC. AVR should not exceed AVCC + 0.3 V.
*3 : VI1 and Vo should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage. However, if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI1 rating.
*4 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53, P70, P71,
PE0 to PE3, PG0
• Use within recommended operating conditions.
• Use at DC voltage (current).
• The + B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affects
other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
Vcc
Limiting
P-ch
resistance
+ B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-12617-3E
33
MB95100B Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Parameter
Symbol
Condition
Unit
Remarks
Min
Max
At normal operating,
1.8*
3.3
Flash memory product,
TA = −10 °C to +85 °C
At normal operating,
MASK ROM product,
TA = −10 °C to +85 °C
1.8*
2.0*
2.0*
3.6
3.3
3.6
At normal operating,
Flash memory product,
TA = −40 °C to +85 °C
At normal operating,
MASK ROM product,
TA = −40 °C to +85 °C
Power supply
voltage
VCC,
AVCC
At normal operating,
Flash memory product,
At FRAM access,
V
2.7
2.7
3.3
3.6
⎯
TA = −40 °C to +85 °C
At normal operating,
MASK ROM product,
At FRAM access,
TA = −40 °C to +85 °C
MB95FV100D-101
TA = + 5 °C to +35 °C
2.6
1.5
1.5
3.6
3.3
3.6
Retain status in stop mode,
Flash memory product
Retain status in stop mode,
MASK ROM product
A/D converter
reference input
voltage
AVR
TA
1.8
AVCC
V
Operating temperature
− 40
+ 85
°C
* : The values vary with the operating frequency.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
34
DS07-12617-3E
MB95100B Series
3. DC Characteristics
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
Parameter
bol
Pin name
Condition
Unit
Remarks
Min
Typ
Max
At selecting CMOS
input level
VIH1 P10, P67
*1
0.7 VCC
⎯
VCC + 0.3
V
At selecting CMOS
input level
MB95F108BS,
MB95F108BW,
MB95107B,
⎯
⎯
VSS + 5.5
VCC + 0.3
VIH2 P50, P51
⎯
0.7 VCC
V
MB95FV100D-101
At selecting CMOS
input level
MB95D108BS,
MB95D108BW
P00 to P07,
P10 to P14,
P20 to P24,
P30 to P37,
P40 to P43,
VIHS1 P52, P53,
P60 to P67,
P70, P71,
*1
0.8 VCC
⎯
VCC + 0.3
V
Hysteresis input
Hysteresis input
“H” level input
voltage
PE0 to PE3,
PG0, PG1*2,
PG2*2
VIHS2 P80 to P83
*1
0.8 VCC
0.8 VCC
⎯
⎯
VSS + 5.5
VSS + 5.5
V
V
Hysteresis input
MB95F108BS,
MB95F108BW,
MB95107B,
VIHS3 P50, P51
⎯
MB95FV100D-101
Hysteresis input
MB95D108BS,
MB95D108BW
⎯
⎯
⎯
VSS + 5.0
VCC + 0.3
VCC + 0.3
CMOS input
(Flash memory
product)
⎯
⎯
0.7 VCC
0.8 VCC
V
V
VIHM RST, MOD
Hysteresis input
(MASK ROM
product)
(Continued)
DS07-12617-3E
35
MB95100B Series
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Remarks
Min
Typ
Max
At selecting CMOS
input level
(Hysteresis input)
P10, P50, P51,
P67
VIL
*1
VSS − 0.3
⎯
0.3 VCC
V
P00 to P07,
P10 to P14,
P20 to P24,
P30 to P37,
P40 to P43,
P50 to P53,
P60 to P67,
P70, P71,
P80 to P83,
PE0 to PE3,
PG0, PG1*2,
PG2*2
VILS
*1
VSS − 0.3
⎯
0.2 VCC
V
Hysteresis input
“L” level input
voltage
CMOS input
(Flash memory
product)
⎯
⎯
VSS − 0.3
VSS − 0.3
⎯
⎯
0.3 VCC
0.2 VCC
V
V
VILM RST, MOD
Hysteresis input
(MASK ROM
product)
Input leakage
current (Hi-Z
output leakage
current)
Port other than
P50, P51,
P80 to P83
When the pull-up is
prohibition setting
ILI
0.0 V < VI < VCC
− 5
⎯
+ 5
μA
Output pin other
than P00 to P07
VOH1
IOH = − 4.0 mA
IOH = − 8.0 mA
IOL = 4.0 mA
2.4
2.4
⎯
⎯
⎯
⎯
⎯
⎯
V
V
V
V
“H” level output
voltage
VOH2 P00 to P07
Output pin other
VOL1
0.4
“L” level output
voltage
than P00 to P07
VOL2 P00 to P07
VD1 P80 to P83
IOL = 12 mA
⎯
⎯
⎯
0.4
⎯
VSS − 0.3
VSS + 5.5
Open-drain
output
application
voltage
MB95F108BS,
MB95F108BW,
MB95107B
VSS + 5.5
VCC + 0.3
5
V
VD2 P50, P51
⎯
VSS − 0.3
⎯
⎯
MB95D108BS,
MB95D108BW
Open-drain
output leakage
current
P50, P51,
ILIOD
0.0 V < VI <
VSS + 5.5 V
⎯
μA
P80 to P83
(Continued)
36
DS07-12617-3E
MB95100B Series
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
P10 to P14,
Condition
Unit
Remarks
Min
Typ
Max
P20 to P24,
P30 to P37,
P40 to P43,
P52, P53,
When the pull-up is
permission setting
Pull-up resistor RPULL
VI = 0.0 V
25
50
100
kΩ
P70, P71,
PE0 to PE3,
PG0, PG1*2, PG2*2
Pull-down
resistor
MASK ROM
product
RMOD MOD
VI = VCC
25
50
5
100
15
kΩ
Input
capacitance
Other than AVCC,
CIN
f = 1 MHz
⎯
pF
AVSS, AVR, VCC, VSS
MB95F108BS,
MB95F108BW
⎯
11.0 14.0 mA (at other than Flash
memory writing and
FCH = 20 MHz
FMP = 10 MHz
Main clock mode
(divided by 2)
erasing)
MB95F108BS,
MB95F108BW
(at Flash memory
writing and erasing)
⎯
⎯
30.0 35.0 mA
7.3
10.0 mA MB95107B
MB95F108BS,
MB95F108BW
⎯
17.6 22.4 mA (at other than Flash
memory writing and
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
Power supply
current*3
VCC (External clock
operation)
erasing)
ICC
MB95F108BS,
MB95F108BW
(at Flash memory
writing and erasing)
⎯
⎯
38.1 44.9 mA
11.7 16.0 mA MB95107B
MB95D108BS,
MB95D108BW
11.1 15.0 mA (at other than Flash
memory writing and
FCH = 20 MHz
FMP = 10 MHz
Main clock mode
(divided by 2)
When FRAM
read and write
(fSCL = 400 kHz)
⎯
⎯
erasing)
MB95D108BS,
MB95D108BW
(at Flash memory
write and erase)
30
35
mA
(Continued)
DS07-12617-3E
37
MB95100B Series
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Remarks
Min
Typ
Max
MB95D108BS,
MB95D108BW
17.7 22.5 mA (at other than Flash
memory writing and
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
When FRAM read
and write
⎯
erasing)
ICC
MB95D108BS,
MB95D108BW
(at Flash memory
write and erase)
⎯
⎯
⎯
38.1 44.9 mA
(fSCL = 400 kHz)
FCH = 20 MHz
FMP = 10 MHz
Main Sleep mode
(divided by 2)
4.5
7.2
6.0
9.6
mA
mA
ICCS
FCH = 32 MHz
FMP = 16 MHz
Main Sleep mode
(divided by 2)
FCL = 32 kHz
FMPL = 16 kHz
Sub clock mode
(divided by 2) ,
TA = + 25 °C
Power supply
current*3
VCC (External
clock operation)
ICCL
⎯
⎯
25
7
35
15
μA
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2) ,
TA = + 25 °C
ICCLS
μA
μA
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
Flash memory
product
⎯
⎯
⎯
⎯
⎯
⎯
2
1
10
5
ICCT
μA MASK ROM product
FCH = 4 MHz
Flash memory
product
10
6.7
14
mA
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
10.0 mA MASK ROM product
ICCMPLL
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
Flash memory
product
16.0 22.4 mA
10.8 16.0 mA MASK ROM product
(Continued)
38
DS07-12617-3E
MB95100B Series
(Continued)
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Remarks
Min Typ Max
FCL = 32 kHz
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
ICCSPLL
⎯
⎯
190
0.4
250
0.5
μA
VCC (External
clock operation)
FCH = 10 MHz
Timebase timer
mode
ICTS
mA
TA = + 25 °C
Power supply
current*3
Sub stop mode
TA = + 25 °C
ICCH
⎯
⎯
1
5
μA
FCH = 10 MHz
At operatingof A/D
conversion
IA
1.3
2.2
mA
AVCC
FCH = 10 MHz
At stopping of A/D
conversion
IAH
⎯
1
5
μA
TA = + 25 °C
*1 : P10, P50, P51, and P67 can switch the input level to either the “CMOS input level” or “hysteresis input level”.
The switching of the input level can be set by the input level selection register (ILSR).
*2 : Single clock product only
*3 : Power supply current is regulated by external clock.
• Refer to “4. AC Characteristics (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
DS07-12617-3E
39
MB95100B Series
4. AC Characteristics
(1) Clock Timing
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name Condition
Unit
Remarks
Min
Typ
Max
When using main
oscillation circuit
1.00
⎯
16.25 MHz
1.00
3.00
3.00
3.00
3.00
⎯
⎯
⎯
⎯
⎯
32.50 MHz When using external clock
10.00 MHz Main PLL multiplied by 1
8.13 MHz Main PLL multiplied by 2
6.50 MHz Main PLL multiplied by 2.5
4.06 MHz Main PLL multiplied by 4
When using sub
FCH
X0, X1
Clock frequency
⎯
32.768
⎯
kHz
oscillation circuit
When using sub PLL
Flash memory product :
FCL X0A, X1A
⎯
32.768
⎯
kHz VCC = 2.3 V to 3.3 V
MASK ROM product :
VCC = 2.3 V to 3.6 V
⎯
When using main
oscillation circuit
61.5
30.8
⎯
⎯
1000 ns
tHCYL
X0, X1
1000 ns When using external clock
When using sub
Clock cycle time
tLCYL X0A, X1A
⎯
30.5
⎯
μs oscillation circuit,
When using external clock
tWH1
tWL1
X0
61.5
⎯
⎯
15.2
⎯
⎯
⎯
10
ns
When using external
clock, duty ratio is about
30% to 70%.
Input clock pulse width
tWH2
X0A
tWL2
μs
Input clock rise time
and fall time
tCR
X0, X0A
tCF
⎯
ns When using external clock
40
DS07-12617-3E
MB95100B Series
• Input wave form for using external clock (main clock)
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock Input port external connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0
X1
X0
X1
Open
FCH
C2
FCH
C1
• Input wave form for using external clock (sub clock)
tLCYL
tWH2
tWL2
tCR
tCF
0.8 VCC 0.8 VCC
X0A
0.1 VCC
0.1 VCC
0.1 VCC
• Figure of sub clock input port external connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0A
X1A
X0A
X1A
Open
FCL
C2
FCL
C1
DS07-12617-3E
41
MB95100B Series
(2) Source Clock/Machine Clock
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Typ
Sym- Pin
Parameter
Unit
Remarks
bol name
Min
Max
When using main clock
61.5
⎯
⎯
2000
ns Min : FCH = 8.125 MHz, PLL multiplied by 2
Source clock cycle
time*1
(Clock before setting
division)
Max : FCH = 1 MHz, divided by 2
tSCLK
⎯
When using sub clock
7.6
61.0
μs Min : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
FSP
⎯
⎯
0.5
⎯
⎯
16.25 MHz When using main clock
131.072 kHz When using sub clock
When using main clock
Source clock
frequency
FSPL
16.384
61.5
7.6
⎯
⎯
32000
ns Min : FSP = 16.25 MHz, no division
Machine clock cycle
time*2
(Minimuminstruction
execution time)
Max : FSP = 0.5 MHz, divided by 16
tMCLK
⎯
When using sub clock
976.5
μs Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
FMP
0.031
1.024
⎯
⎯
16.250 MHz When using main clock
131.072 kHz When using sub clock
Machine clock
frequency
⎯
FMPL
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selectionbit (SYCC: DIV1 andDIV0) , anditbecomes
the machine clock. Further, the source clock can be selected as follow.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follow.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
42
DS07-12617-3E
MB95100B Series
• Outline of clock generation block
FCH
Divided by 2
(main oscillation)
Main PLL
× 1
× 2
× 2.5
× 4
Division
circuit
SCLK
× 1
MCLK
(machine clock)
(source clock)
× 1/4
× 1/8
× 1/16
FCL
Divided by 2
(sub oscillation)
Clock mode select bit
(SYCC: SCS1, SCS0)
Sub PLL
× 2
× 3
× 4
DS07-12617-3E
43
MB95100B Series
• Operating voltage - Operating frequency (When TA = − 10 °C to + 85 °C)
• MB95107B
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
FRAM operating guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.6
3.6
2.7
2.3
1.8
1.8
0.5 MHz 3 MHz 5 MHz
16.25 MHz
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
PLL operation guarantee range
Source clock frequency (FSPL)
Main clock operation guarantee range
Source clock frequency (FSP)
• MB95F108BS, MB95F108BW, MB95D108BS, MB95D108BW
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
FRAM operating guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.3
3.3
2.7
2.3
1.8
1.8
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz
7.5 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSPL)
44
DS07-12617-3E
MB95100B Series
• Operating voltage - Operating frequency (When TA = − 40 °C to + 85 °C)
• MB95107B
Sub PLL operation guarantee range
FRAM operating guarantee range
Main clock mode and main PLL mode
operation guarantee range
Sub clock mode and watch mode
operation guarantee range
3.6
3.6
2.7
2.3
1.8
1.8
0.5 MHz 3 MHz 5 MHz
16.25 MHz
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
PLL operation guarantee range
Source clock frequency (FSPL)
Main clock operation guarantee range
Source clock frequency (FSP)
• MB95F108BS, MB95F108BW, MB95D108BS, MB95D108BW
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
FRAM operating guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.3
3.3
2.7
2.3
2.0
2.0
0.5 MHz 3 MHz 5 MHz
16.25 MHz
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSPL)
DS07-12617-3E
45
MB95100B Series
• Operating voltage - Operating frequency (TA = + 5 °C to + 35 °C)
• MB95FV100D-101
FRAM, Main clock mode and main PLL
mode operation guarantee range
Sub PLL, Sub clock mode and watch
mode operation guarantee range
3.6
3.6
3.3
2.6
2.6
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSPL)
46
DS07-12617-3E
MB95100B Series
• Main PLL operation frequency
[MHz]
16.25
16
15
× 4
12
10
× 2.5
× 1
× 2
7.5
6
5
3
[MHz]
10
0
3
4 4.062
5
6.4 6.5
8
8.125
Machine clock frequency (FMP)
DS07-12617-3E
47
MB95100B Series
(3) External Reset
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin
name
Condi-
tion
Parameter
Symbol
Unit
Remarks
Min
Max
2 tMCLK*1
⎯
ns At normal operating
At stop mode,
RST
Oscillation time of oscillator*2
sub clock mode,
sub sleep mode,
“L” level
pulse width
tRSTL
RST
⎯
⎯
ns
+ 2 tMCLK*1
and watch mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the
oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between
hundreds of μs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operating
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
2 tMCLK
Oscillation time
of oscillator
Oscillation stabilization wait time
Execute instruction
Internal reset
48
DS07-12617-3E
MB95100B Series
(4) Power-on Reset
Parameter
(AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin
name
Symbol
Condition
Unit
Remarks
Min
Max
Power supply rising time
Power supply cutoff time
tR
⎯
36
ms
ms
VCC
⎯
Waiting time until
power-on
tOFF
1
⎯
Note : The power supply must be turned on within the selected oscillation stabilization time.
tR
tOFF
1.5 V
0.2 V
0.2 V
0.2 V
VCC
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 20 mV/ms as shown below.
VCC
Limiting the slope of rising within
20 mV/ms is recommended.
1.5 V
Hold Condition in stop mode
VSS
DS07-12617-3E
49
MB95100B Series
(5) Peripheral Input Timing
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
Pin name
Condition
Unit
Min
Max
Peripheral input
“H” pulse width
INT00 to INT07,
INT10 to INT13,
EC0, EC1, TI0, TRG0/ADTG,
TRG1
tILIH
tIHIL
2 tMCLK*
⎯
ns
ns
⎯
Peripheral input
“L” pulse width
2 tMCLK*
⎯
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIH
tIHIL
INT00 to INT07,
0.8 VCC 0.8 VCC
INT10 to INT13, EC0, EC1,
TI0, TRG0/ADTG, TRG1
0.2 VCC
0.2 VCC
50
DS07-12617-3E
MB95100B Series
(6) UART/SIO, Serial I/O Timing
Parameter
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Symbol
Pin name
Condition
Unit
Min
Max
⎯
Serial clock cycle time
UCK ↓ → UO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
UCK0
UCK0, UO0
UCK0, UI0
UCK0, UI0
UCK0
4 tMCLK*
− 190
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1TTL.
+ 190
⎯
Valid UI → UCK ↑
2 tMCLK*
2 tMCLK*
4 tMCLK*
4 tMCLK*
0
UCK ↑ → valid UI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
UCK ↓ → UO time
⎯
⎯
UCK0
⎯
External clock
UCK0, UO0 operation output pin :
190
⎯
CL = 80 pF + 1TTL.
Valid UI → UCK ↑
UCK0, UI0
2 tMCLK*
2 tMCLK*
UCK ↑ → valid UI hold time
UCK0, UI0
⎯
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
t
SCYC
2.4 V
UCK0
0.8 V
0.8 V
t
SLOV
UO0
UI0
2.4 V
0.8 V
t
IVSH
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
UCK0
t
SHSL
t
SLSH
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
t
SLOV
UO0
UI0
2.4 V
0.8 V
t
IVSH
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
DS07-12617-3E
51
MB95100B Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Min
5 tMCLK*3
−95
Max
Serial clock cycle time
SCK ↑→ SOT delay time
Valid SIN→SCK↑
tSCYC
SCK
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
tSLOVI SCK, SOT
+ 95
tIVSHI
tSHIXI
tSLSH
tSHSL
SCK, SIN
SCK, SIN
SCK
tMCLK*3 + 190
⎯
SCK↑→ valid SIN hold time
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK ↓→SOT delay time
Valid SIN→SCK↑
0
3 tMCLK*3 − tR
tMCLK*3 + 95
⎯
⎯
⎯
SCK
⎯
tSLOVE SCK, SOT
2 tMCLK*3 + 95
External clock
tIVSHE SCK, SIN operationoutputpin:
190
⎯
⎯
10
10
CL = 80 pF + 1 TTL.
SCK↑→ valid SIN hold time
SCK fall time
tSHIXE SCK, SIN
tMCLK*3 + 95
⎯
tF
SCK
SCK
SCK rise time
tR
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
52
DS07-12617-3E
MB95100B Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
tSLOVI
0.8 V
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
0.8 VCC
SCK
SOT
SIN
0.2 VCC
0.2 VCC
tR
tF
tSLOVE
2.4 V
0.8 V
tIVSHE
tSHIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
DS07-12617-3E
53
MB95100B Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Min
5 tMCLK*3
−95
Max
Serial clock cycle time
SCK↑→ SOT delay time
Valid SIN→SCK↓
tSCYC
tSHOVI
tIVSLI
tSLIXI
tSHSL
tSLSH
SCK
SCK, SOT
SCK, SIN
SCK, SIN
SCK
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
+ 95
tMCLK*3 + 190
⎯
SCK↓→ valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK↑ →SOT delay time
Valid SIN→SCK↓
0
3 tMCLK*3 − tR
tMCLK*3 + 95
⎯
⎯
⎯
SCK
⎯
tSHOVE SCK, SOT
2 tMCLK*3 + 95
External clock
tIVSLE
tSLIXE
tF
SCK, SIN operation output pin :
190
⎯
⎯
10
10
CL = 80 pF + 1 TTL.
SCK↓→ valid SIN hold time
SCK fall time
SCK, SIN
tMCLK*3 + 95
⎯
SCK
SCK
SCK rise time
tR
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
54
DS07-12617-3E
MB95100B Series
• Internal shift clock mode
tSCYC
2.4 V
2.4 V
SCK
0.8 V
tSHOVI
2.4 V
SOT
SIN
0.8 V
tSLIXI
tIVSLI
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
tSLSH
SCK
0.8 VCC
0.8 VCC
0.2 VCC
tR
0.2 VCC
0.2 VCC
tF
tSHOVE
2.4 V
0.8 V
SOT
SIN
tIVSLE
tSLIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
DS07-12617-3E
55
MB95100B Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Min
Max
⎯
Serial clock cycle time
SCK↑→ SOT delay time
Valid SIN→SCK↓
tSCYC
tSHOVI
tIVSLI
SCK
5 tMCLK*3
ns
ns
ns
ns
ns
SCK, SOT
−95
+ 95
⎯
Internal clock
SCK, SIN operation output pin : tMCLK*3 + 190
CL = 80 pF + 1 TTL.
SCK↓→ valid SIN hold time
SOT→SCK↓ delay time
tSLIXI
SCK, SIN
SCK, SOT
0
⎯
4 tMCLK*3
tSOVLI
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
t
SCYC
2.4 V
SCK
0.8 V
0.8 V
t
SHOVI
t
SOVLI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
tSLIXI
tIVSLI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
56
DS07-12617-3E
MB95100B Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Min
Max
⎯
Serial clock cycle time
SCK↓→SOT delay time
Valid SIN→SCK↑
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSOVHI
SCK
5 tMCLK*3
ns
ns
ns
ns
ns
SCK, SOT
−95
+ 95
⎯
Internal clock
SCK, SIN operating output pin : tMCLK*3 + 190
CL = 80 pF + 1 TTL.
SCK↑ → valid SIN hold time
SOT→SCK↑ delay time
SCK, SIN
SCK, SOT
0
⎯
4 tMCLK*3
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
2.4 V
SCK
0.8 V
tSOVHI
tSLOVI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
tIVSHI
tSHIXI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
DS07-12617-3E
57
MB95100B Series
(8) I2C Timing
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol Pin name Condition Standard-mode
Fast-mode
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
SCL0
0
100
0
400
kHz
(Repeat) Start condition hold
time SDA ↓ → SCL ↓
SCL0
SDA0
tHD;STA
4.0
⎯
0.6
⎯
μs
SCL clock “L” width
SCL clock “H” width
tLOW
tHIGH
SCL0
SCL0
4.7
4.0
⎯
⎯
1.3
0.6
⎯
⎯
μs
μs
(Repeat) Start condition set-
up time SCL ↑ → SDA ↓
SCL0
SDA0
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
4.7
0
⎯
3.45*2
⎯
0.6
0
⎯
0.9*3
⎯
μs
μs
μs
μs
μs
R = 1.7 kΩ,
C = 50 pF*1
Data hold time SCL ↓ → SDA
↓ ↑
SCL0
SDA0
Data setup time SDA ↓ ↑ →
SCL ↑
SCL0
SDA0
0.25
4
0.1
0.6
1.3
Stop condition setup time SCL
↑ → SDA ↑
SCL0
SDA0
⎯
⎯
Bus free time between stop
condition and start condition
SCL0
SDA0
4.7
⎯
⎯
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.
*3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement
tSU;DAT ≥ 250 ns must then be met.
tWAKEUP
SDA0
tHD;STA
tHD;DAT
tHIGH
tBUF
tLOW
SCL0
tSU;STO
tHD;STA
tSU;DAT
tSU;STA
58
DS07-12617-3E
MB95100B Series
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value*2
Sym- Pin
bol name
Condi-
tion
Parameter
Unit
Remarks
Min
Max
SCL clock
“L” width
tLOW
tHIGH
SCL0
SCL0
(2 + nm / 2) tMCLK − 20
⎯
ns Master mode
SCL clock
“H” width
(nm / 2) tMCLK − 20
(nm / 2 ) tMCLK + 20
(−1 + nm) tMCLK + 20
ns Master mode
Master mode
Maximum value is
applied when m,
ns n = 1, 8.
Startcondition
hold time
SCL0
SDA0
(−1 + nm / 2) tMCLK − 20
tHD;STA
Otherwise, the
minimum value is
applied.
Stopcondition
setup time
SCL0
SDA0
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20
tSU;STO
ns Master mode
ns Master mode
Startcondition
setup time
SCL0
SDA0
tSU;STA
Bus free time
between stop
condition and
start condition
SCL0
SDA0
(2 nm + 4) tMCLK − 20
3 tMCLK − 20
⎯
⎯
tBUF
ns
SCL0
SDA0
Data hold time tHD;DAT
ns Master mode
R = 1.7 kΩ,
C = 50 pF*1
Master mode
When assuming
that “L” of SCL is not
extended, the
Data setup
tSU;DAT
SCL0
SDA0
minimum value is
applied to first bit of
(−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20
ns
time
continuous data.
Otherwise,
the maximum value
is applied.
Minimum value is
applied to interrupt
at 9th SCL↓.
Maximum value is
applied to interrupt
at 8th SCL↓.
Setup time
between
clearing
interrupt and
SCL rising
(nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
tSU;INT SCL0
ns
SCL clock “L”
width
4 tMCLK − 20
4 tMCLK − 20
⎯
⎯
tLOW
tHIGH
SCL0
SCL0
ns At reception
ns At reception
SCL clock “H”
width
Undetected when 1
ns tMCLK is used at
reception
Startcondition
detection
SCL0
SDA0
2 tMCLK − 20
⎯
tHD;STA
(Continued)
DS07-12617-3E
59
MB95100B Series
(Continued)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value*2
Sym-
bol
Pin
name
Condi-
tion
Parameter
Unit
Remarks
Min
Max
Undetected when 1
ns tMCLK is used at
reception
Stop condition
detection
SCL0
SDA0
tSU;STO
2 tMCLK − 20
⎯
Undetected when 1
ns tMCLK is used at
reception
Restart condition
detection condition
SCL0
SDA0
2 tMCLK − 20
⎯
tSU;STA
SCL0
SDA0
2 tMCLK − 20
2 tMCLK − 20
tLOW − 3 tMCLK − 20
0
⎯
⎯
⎯
⎯
⎯
Bus free time
tBUF
ns At reception
SCL0
SDA0
At slave transmission
mode
Data hold time
Data setup time
Data hold time
Data setup time
tHD;DAT
tSU;DAT
tHD;DAT
tSU;DAT
ns
R = 1.7 kΩ,
C = 50 pF*1
SCL0
SDA0
At slave transmission
mode
ns
SCL0
SDA0
ns At reception
ns At reception
SCL0
SDA0
tMCLK − 20
Oscillationstabilization
wait time +
SDA↓→SCL↑
(at wakeup function)
SCL0
SDA0
⎯
tWAKEUP
ns
2 tMCLK − 20
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : • Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR) .
• n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR) .
• Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of
ICCR0 register.
• Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
• Fast-mode :
: 0.9 MHz < tMCLK ≤ 10 MHz
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
(m, n) = (1, 22) , (5, 4)
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 4 MHz
: 3.3 MHz < tMCLK ≤ 8 MHz
: 3.3 MHz < tMCLK ≤ 10 MHz
60
DS07-12617-3E
MB95100B Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVCC = VCC = 1.8 V to 3.3 V [Flash memory product], AVCC = VCC = 1.8 V to 3.6 V [MASK ROM product],
AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym- Condi-
Parameter
Unit
Remarks
bol
tion
Min
⎯
Typ
⎯
Max
10
Resolution
Total error
bit
− 3.0
− 2.5
⎯
+ 3.0
+ 2.5
LSB
LSB
⎯
Linearity error
⎯
Differential
linear error
− 1.9
⎯
+ 1.9
LSB
Flashmemoryproduct:
2.7 V ≤ AVCC ≤ 3.3 V
MASK ROM product :
2.7 V ≤ AVCC ≤ 3.6 V
AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
AVSS − 0.5 LSB AVSS + 1.5 LSB AVSS + 3.5 LSB
AVR − 3.5 LSB AVR − 1.5 LSB AVR + 0.5 LSB
AVR − 2.5 LSB AVR − 0.5 LSB AVR + 1.5 LSB
V
V
Zerotransition
voltage
VOT
VFST
⎯
1.8 V ≤ AVCC < 2.7 V
Flashmemoryproduct:
2.7 V ≤ AVCC ≤ 3.3 V
MASK ROM product :
2.7 V ≤ AVCC ≤ 3.6 V
Full-scale
transition
voltage
V
V
1.8 V ≤ AVCC < 2.7 V
Flashmemoryproduct:
2.7 V ≤ AVCC ≤ 3.3 V
MASK ROM product :
2.7 V ≤ AVCC ≤ 3.6 V
1.3
20
⎯
⎯
140
140
μs
Compare time
Sampling time
⎯
μs 1.8 V ≤ AVCC < 2.7 V
Flashmemoryproduct:
2.7 V ≤ AVCC ≤ 3.3 V
MASK ROM product :
2.7 V ≤ AVCC ≤ 3.6 V ex-
ternal impedance < at
1.8 kΩ
0.4
30
⎯
∞
μs
⎯
1.8 V ≤ AVCC < 2.7 V
μs external impedance <
at 14.8 kΩ
⎯
∞
Analog input
current
IAIN
VAIN
⎯
−0.3
AVSS
⎯
⎯
+ 0.3
AVR
AVCC
600
5
μA
Analog input
voltage
V
Reference
voltage
AVSS + 1.8
⎯
⎯
V
AVR pin
AVR pin,
During A/D operation
IR
400
⎯
μA
μA
Reference
voltage
supply current
AVR pin,
At stop mode
IRH
⎯
DS07-12617-3E
61
MB95100B Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• Analog input equivalent circuit
R
Analog input pin
Comparator
C
During sampling : ON
R
C
2.7 V ≤ AVCC ≤ 3.6 V
1.8 V ≤ AVCC < 2.7 V
1.7 kΩ (Max)
84 kΩ (Max)
14.5 pF (Max)
25.2 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
AVCC ≥ 2.7 V
AVCC ≥ 2.7 V
100
20
90
80
70
60
18
16
14
12
10
8
AVCC ≥ 1.8 V
50
40
30
20
10
0
6
4
2
0
0
5
10 15 20 25 30 35 40
0
1
2
3
4
Minimum sampling time [μs]
Minimum sampling time [μs]
• About errors
As |AVR − AVSS| becomes smaller, values of relative errors grow larger.
62
DS07-12617-3E
MB95100B Series
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FEH
3FDH
3FFH
3FEH
3FDH
Actual conversion
characteristic
1.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
001H
004H
003H
002H
001H
VNT
VOT
Actual conversion
characteristic
1 LSB
0.5 LSB
Ideal characteristics
AVSS
AVSS
AVR
AVR
Analog input
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
AVR − AVSS
1024
Total error of
digital output N
=
1 LSB =
(V)
[LSB]
1 LSB
N
: A/D converter digital output value
VNT : A voltage at which digital output transits from (N - 1)H to NH.
(Continued)
DS07-12617-3E
63
MB95100B Series
(Continued)
Full-scale transition error
Zero transition error
Ideal
004H
characteristics
Actual conversion
characteristic
3FFH
3FEH
3FDH
3FCH
Actual conversion
characteristic
003H
Ideal
characteristics
002H
VFST
(measurement
value)
Actual conversion
characteristic
001H
Actual conversion
characteristic
VOT (measurement value)
AVSS
AVR
AVSS
AVR
Analog input
Analog input
Linearity error
Differential linear error
Actual conversion
characteristic
Ideal characteristics
3FFH
3FEH
3FDH
(N+1)H
NH
Actual conversion
characteristic
{1 LSB × N + VOT}
V (N+1)T
VFST
(measurement
value)
VNT
004H
003H
002H
001H
(N-1)H
(N-2)H
VNT
Actual conversion
characteristic
Actual conversion
characteristic
Ideal characteristics
VOT (measurement value)
AVSS
AVR
AVSS
AVR
Analog input
Analog input
VNT − {1 LSB × N + VOT}
V (N + 1) T − VNT
Linear error in
digital output N
Differential linear error
in digital output N
=
=
− 1
1 LSB
1 LSB
N
: A/D converter digital output value
VNT : A voltage at which digital output transits from (N - 1) H to NH.
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVR − 1.5 LSB [V]
64
DS07-12617-3E
MB95100B Series
6. Flash Memory Program/Erase Characteristics
Value
Parameter
Unit
Remarks
Min
Typ
Max
Sector erase time
(4K bytes sector)
⎯
0.2*1
3.0*2
s
s
Excludes 00H programming prior erasure.
Excludes 00H programming prior erasure.
Sector erase time
(16K bytes sector)
⎯
0.5*1
12.0*2
Byte programming time
Program/erase cycle
⎯
32
3600
μs Excludes system-level overhead.
cycle
10000
⎯
⎯
Power supply voltage at
program/erase
2.7
⎯
⎯
3.3
V
Flash memory data retention
time
20*3
⎯
year Average TA = +85 °C
*1 : TA = + 25 °C, VCC = 3.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 2.7 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
7. FRAM Program Characteristics
Value
Parameter
Unit
Remarks
Min
Typ
Max
Read/write cycle*
1010
⎯
⎯
cycle
V
Power supply voltage at
read/write
2.7
10
⎯
⎯
3.6
Data retention time
⎯
year TA = 0 °C to +55 °C
* : Number of data read/write
DS07-12617-3E
65
MB95100B Series
■ EXAMPLE CHARACTERISTICS
• MB95F108BS/MB95F108BW power supply current temperature
ICC-VCC
ICC-TA
TA = + 25 °C
VCC = 3.3 V FMP = 10, 16 MHz (divided by 2)
FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode, at external clock operating
Main clock mode, at external clock operating
20
16
12
8
20
18
16
14
12
10
8
FMP=16[MHz]
FMP=10[MHz]
FMP=16[MHz]
FMP=10[MHz]
FMP=8[MHz]
6
4
FMP=4[MHz]
FMP=2[MHz]
4
2
0
0
1.5
2
2.5
3
3.5
4
-50 -35 -20 -5 +10 +25 +40 +55 +70 +85 +100
VCC [V]
TA [ °C]
ICCS-VCC
ICCS-TA
TA = + 25 °C
VCC = 3.3 V FMP = 10, 16 MHz (divided by 2)
FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode, at external clock operating
Main clock mode, at external clock operating
12
10
8
12
10
8
FMP=16[MHz]
FMP=10[MHz]
FMP=16[MHz]
6
6
FMP=10[MHz]
FMP=8[MHz]
4
4
2
2
FMP=4[MHz]
FMP=2[MHz]
0
0
-50 -35 -20 -5 +10 +25 +40 +55 +70 +85 +100
1.5
2
2.5
3
3.5
4
VCC [V]
TA [ °C]
(Continued)
66
DS07-12617-3E
MB95100B Series
ICCMPLL-VCC
ICCMPLL-TA
TA = + 25 °C
VCC = 3.3 V FMP = 10, 16 MHz (multiplied by 2.5)
FMP = 2, 4, 8, 10, 16 MHz (multiplied by 2.5)
Main PLL mode, at external clock operating
Main PLL mode, at external clock operating
20
20
16
12
8
FMP=16[MHz]
FMP=10[MHz]
16
12
8
FMP=16[MHz]
FMP=10[MHz]
FMP=8[MHz]
FMP=4[MHz]
FMP=2[MHz]
4
4
0
1.5
2
2.5
3
3.5
4
0
-50 -35 -20 -5 +10 +25 +40 +55 +70 +85 +100
VCC [V]
ICCL-VCC
TA [ °C]
ICCL-TA
TA = + 25 °C FMPL = 16 kHz (divided by 2)
VCC = 3.3 V FMPL = 16 kHz (divided by 2)
Sub clock mode, at external clock operating
Sub clock mode, at external clock operating
50
50
40
30
20
10
0
40
30
20
10
0
1.5
2
2.5
VCC [V]
3
3.5
4
-50 -35 -20 -5 +10 +25 +40 +55 +70 +85 +100
TA [ °C]
(Continued)
DS07-12617-3E
67
MB95100B Series
ICCLS-VCC
ICCLS-TA
TA = + 25 °C FMPL = 16 kHz (divided by 2)
VCC = 3.3 V FMPL = 16 kHz (divided by 2)
Sub sleep mode, at external clock operating
Sub sleep mode, at external clock operating
15
12
9
15
12
9
6
6
3
3
0
0
1.5
2
2.5
3
3.5
4
-50 -35 -20 -5 +10 +25 +40 +55 +70 +85 +100
VCC [V]
TA [ °C]
ICCT-VCC
ICCT-TA
TA = + 25 °C FMPL = 16 kHz (divided by 2)
VCC = 3.3 V FMPL = 16 kHz (divided by 2)
Clock mode, at external clock operating
Clock mode, at external clock operating
5
4
3
2
1
0
5
4
3
2
1
0
1.5
2
2.5
3
3.5
4
-50 -35 -20 -5 +10 +25 +40 +55 +70 +85 +100
TA [ °C]
VCC [V]
ICCSPLL-VCC
TA = + 25 °C FMPL = 128 kHz (4í¸î{)
Sub PLL mode, at external clock operating
ICCSPLL-TA
VCC = 3.3 V FMPL = 16 kHz (divided by 2)
Sub PLL mode, at external clock operating
500
500
400
300
200
100
0
400
300
200
100
0
1.5
2
2.5
VCC [V]
3
3.5
4
-50 -35 -20 -5 +10 +25 +40 +55 +70 +85 +100
TA [ °C]
(Continued)
68
DS07-12617-3E
MB95100B Series
ICTS-VCC
ICTS-TA
TA = + 25 °C
VCC = 3.3 V FMP = 10, 16 MHz (divided by 2)
FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode, at external clock operating
Time-base timer mode, at external clock operating
1.4
1.2
1.4
1.2
FMP=16[MHZ]
1
1
0.8
0.6
0.4
0.2
0
FMP=16[MHZ]
0.8
FMP=10[MHZ]
FMP=10[MHZ]
0.6
0.4
0.2
FMP=8[MHZ]
FMP=4[MHZ]
FMP=2[MHZ]
0
-50 -35 -20 -5 +10 +25 +40 +55 +70 +85 +100
1.5
2
2.5
VCC [V]
ICCH-VCC
TA = + 25 °C FMP = stop
Sub stop mode, at external clock stopping
3
3.5
4
TA [ °C]
ICCH-TA
VCC = 5.5 V FMP = stop
Sub stop mode, at external clock stopping
3
2.4
1.8
1.2
0.6
0
3
2.4
1.8
1.2
0.6
1.5
2
2.5
VCC [V]
3
3.5
4
0
-50 -35 -20 -5 +10 +25 +40 +55 +70 +85 +100
TA [ °C]
(Continued)
DS07-12617-3E
69
MB95100B Series
(Continued)
IA-AVCC
IA-TA
TA = + 25 °C FMP = 5 MHz
Operating of A/D conversion,
at external clock operating
AVCC = 3.3 V FMP = 5 MHz
Operating of A/D conversion,
at external clock operating
3
2.4
1.8
1.2
0.6
0
3
2.4
1.8
1.2
0.6
0
1.5
2
2.5
3
3.5
4
-50 -35 -20 -5 +10 +25 +40 +55 +70 +85 +100
AVCC [V]
IR-AVCC
TA = + 25 °C FMP = 5 MHz
Stopping A/D conversion,
at external clock operating
TA [ °C]
IR-TA
AVCC = 3.3 V FMP = 5 MHz
Stopping A/D conversion,
at external clock operating
1
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
1.5
2
2.5
3
3.5
4
-50 -35 -20 -5 +10 +25 +40 +55 +70 +85 +100
AVCC [V]
TA [ °C]
70
DS07-12617-3E
MB95100B Series
• MB95F108BS/MB95F108BW input voltage characteristics
VIH1-VCC - VIL-VCC
TA = + 25°C
VIHS1-VCC - VILS-VCC
TA = + 25°C
3
2
1
0
3
VIH1
VIL
VIHS1
VILS
2
1
0
1.5
1.8
2.1
2.4
2.7
3
3.3
3.6
1.5
1.8
2.1
2.4
2.7
3
3.3
3.6
VCC[V]
VCC[V]
DS07-12617-3E
71
MB95100B Series
• MB95F108BS/MB95F108BW output voltage characteristics
(VCC-VOH1)-IOH
TA= + 25°C
VOL1-IOL
TA= + 25°C
1.2
1
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC=2.5[V]
VCC=2.0[V]
VCC=1.8[V]
VCC=2.5[V]
V
CC=2.0[V]
V
CC=3.0[V]
CC=3.3[V]
VCC=3.0[V]
VCC=3.3[V]
VCC=1.8[V]
0.8
0.6
0.4
0.2
0
V
0
-2
-4
-6
-8
-10
0
2
4
6
8
10
IOH [mA]
IOL [mA]
(VCC-VOH2)-IOH
VOL2-IOL
TA= + 25°C
TA= + 25°C
0.6
0.5
0.4
0.3
0.2
0.1
0
1
V
CC=2.0[V]
0.8
0.6
0.4
0.2
0
V
CC=1.8[V]
V
CC=2.5[V]
VCC=1.8[V]
VCC=2.0[V]
VCC=2.5[V]
VCC=3.0[V]
VCC=3.3[V]
V
V
CC=3.0[V]
CC=3.3[V]
0
-3
-6
-9
-12
-15
0
3
6
9
12
15
I
OH [mA]
IOL [mA]
72
DS07-12617-3E
MB95100B Series
• MB95F108BS/MB95F108BW pull-up characteristics
RPULL-VCC
TA= + 25°C
300
240
180
120
60
0
1.2
1.6
2
2.4
CC[V]
2.8
3.2
3.6
V
DS07-12617-3E
73
MB95100B Series
■ MASK OPTION
MB95F108BS
MB95D108BS
MB95F108BW
MB95D108BW
Part number
No.
MB95107B
MB95FV100D-101
Specify when
ordering MASK
Specifying procedure
Setting disabled Setting disabled Setting disabled
Clock mode select*1
• Single-system clock mode
• Dual-system clock mode
FRAM*1
• With load of FRAM
• Without load of FRAM
Low voltage detection reset*2
• With low voltage detection
reset
• Without low voltage
detection reset
Changing by the
switch on MCU
board
Single-system
clock mode
Dual-system
clock mode
1
2
Selectable
No
Specify by
part number
Specify by
part number
No
No
No
3
4
5
No
No
No
No
No
No
Clock supervisor*2
• With clock supervisor
• Without clock supervisor
Selection of oscillation
stabilization wait time
Selectable
Fixed to oscillation Fixed to oscillation Fixed to oscillation
1 : (22 − 2) /FCH
stabilization wait stabilization wait
stabilization wait
time of
• Selectable the initial value 2 : (212 − 2) /FCH
time of
(214 − 2) /FCH
time of
(214 − 2) /FCH
of main clock oscillation
stabilization wait time
3 : (213 − 2) /FCH
4 : (214 − 2) /FCH
(214 − 2) /FCH
*1 : Refer to table below about clock mode select and load of FRAM.
*2 : Low voltage detection reset and clock supervisor are options of 5-V products.
Part number
Clock mode select
Single-system
Dual-system
Load of FRAM
No
No
MB95107B
MB95F108BS
MB95D108BS
MB95F108BW
MB95D108BW
No
Single-system
Dual-system
Yes
No
Yes
No
Single-system
Dual-system
MB95FV100D-101
No
74
DS07-12617-3E
MB95100B Series
■ ORDERING INFORMATION
Part number
Package
MB95107BPMC1
MB95F108BSPMC1
MB95F108BWPMC1
MB95D108BSPMC1
MB95D108BWPMC1
64-pin plastic LQFP
(FPT-64P-M24)
MB95107BPMC
MB95F108BSPMC
MB95F108BWPMC
MB95D108BSPMC
MB95D108BWPMC
64-pin plastic LQFP
(FPT-64P-M23)
MB95107BBGL
MB95F108BSBGL
MB95F108BWBGL
96-pin plastic FBGA
(BGA-96P-M04)
MCU board
224-pin plastic PFBGA
MB2146-301A-E
(MB95FV100D-101PBT)
(
)
(BGA-224P-M08)
DS07-12617-3E
75
MB95100B Series
■ PACKAGE DIMENSIONS
64-pin plastic LQFP
Lead pitch
0.50 mm
10.0 × 10.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.32 g
Code
(Reference)
(FPT-64P-M24)
P-LFQFP64-10×10-0.50
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*
10.00±0.10(.394±.004)SQ
0.145±0.055
(.006±.002)
48
33
49
32
Details of "A" part
0.08(.003)
1.50 +–00..1200
(Mounting height)
.059 +–..000048
INDEX
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
64
17
"A"
0.25(.010)
0.50±0.20
(.020±.008)
1
16
LEAD No.
0.60±0.15
(.024±.006)
0.50(.020)
0.20±0.05
(.008±.002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2005-2008 FUJITSU MICROELECTRONICS LIMITED F64036S-c-1-2
2005 FUJITSU LIMITED F64036S-c-1-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
76
DS07-12617-3E
MB95100B Series
64-pin plastic LQFP
Lead pitch
0.65 mm
12.0 × 12.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
1.70 mm MAX
P-LFQFP64-12×12-0.65
Code
(Reference)
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
*12.00±0.10(.472±.004)SQ
0.145±0.055
(.0057±.0022)
48
33
49
32
0.10(.004)
Details of "A" part
1.50 –+00..1200
(Mounting height)
.059 –+..000048
0.25(.010)
INDEX
0~8˚
64
17
0.50±0.20
(.020±.008)
0.10±0.10
(.004±.004)
(Stand off)
"A"
1
16
0.60±0.15
(.024±.006)
0.65(.026)
0.32±0.05
(.013±.002)
M
0.13(.005)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2003-2008 FUJITSU MICROELECTRONICS LIMITED F64034S-c-1-2
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS07-12617-3E
77
MB95100B Series
(Continued)
96-pin plastic FBGA
Lead pitch
0.50 mm
6.00 mm × 6.00 mm
Ball
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.30 mm MAX
0.075 g
(BGA-96P-M04)
96-pin plastic FBGA
(BGA-96P-M04)
5.00(.197)
REF
6.00±0.10(.236±.004)
0.20(.008)
S B
0.50
(.020)
TYP
B
11
10
9
8
A
7
6.00±0.10
(.236±.004)
5.00(.197)
REF
6
5
4
0.50(.020)
TYP
3
2
1
L
K
J
H
G
F
E
D
C
B A
(INDEX AREA)
INDEX
0.20(.008)
S A
96-ø0.30±0.10
(96-ø.012±.004)
M
ø0.05(.002)
S A B
S
1.15±0.15
(.045±.006)
(SEATED HEIGHT)
0.10(.004)
S
0.25±0.10
(.010±.004)
(STAND OFF)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2007-2008 FUJITSU MICROELECTRONICS LIMITED B96004S-c-1-2
2007 FUJITSU LIMITED B96004S-c-1-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
78
DS07-12617-3E
MB95100B Series
■ MAIN CHANGES IN THIS EDITION
Page
4
Section
■ PRODUCT LINEUP
Change Results
Changed the Note.
(MB2146-301A → MB2146-301A-E)
15
■ HANDLING DEVICES
Added the item of “• Serial communication”.
■ ORDERING INFORMATION
Changed the part number.
(MB2146-301A → MB2146-301A-E)
75
The vertical lines marked in the left side of the page show the changes.
DS07-12617-3E
79
MB95100B Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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