MB95F128NBPFV_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12610-1E

8-bit Proprietary Microcontrollers

CMOS

F²MC-8FX MB95120MB series

MB95F124MB/F124NB/F126MB/F126NB/F128MB/F128NB/

MB95FV100D-103

■ DESCRIPTION

The MB95120MB series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,

the microcontrollers contain a variety of peripheral functions.

Note : F²MC is the abbreviation of FUJITSU Flexible Microcontroller.

■ FEATURE

• F²MC-8FX CPU core

Instruction set optimized for controllers

• Multiplication and division instructions

• 16-bit arithmetic operations

• Bit test branch instruction

• Bit manipulation instructions etc.

• Clock

• Main clock

• Main PLL clock

• Sub clock

• Sub PLL clock

(Continued)

Be sure to refer to the “Check Sheet” for the latest cautions on development.

“Check Sheet” is seen at the following support page

URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system

development.

MB95120MB Series

(Continued)

• Timer

• 8/16-bit compound timer × 2 channels

• 16-bit reload timer

• 8/16-bit PPG × 2 channels

• 16-bit PPG × 2 channels

• Timebase timer

• Watch prescaler

• LIN-UART

• Full duplex double buffer

• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

• UART/SIO

• Full duplex double buffer

• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

• I²C*

• Built-in wake-up function

• External interrupt

• Interrupt by edge detection (rising, falling, or both edges can be selected)

• Can be used to recover from low-power consumption (standby) modes.

• 8/10-bit A/D converter

• 8-bit or 10-bit resolution can be selected

• LCD controller (LCDC)

• 40 SEG × 4 COM (Max 160 pixels)

• With blinking function

• Low-power consumption (standby) mode

• Stop mode

• Sleep mode

• Watch mode

• Timebase timer mode

• I/O port

• The number of maximum ports : Max 87

• Port configuration

• General-purpose I/O ports (N-ch open drain) : 2 ports

• General-purpose I/O ports (CMOS)

: 85 ports

• Programmable input voltage levels of port

Automotive input level / CMOS input level / hysteresis input level

• Flash memory security function

Protects the content of Flash memory (Flash memory device only)

* : Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use, these

components in an I²C system provided that the system conforms to the I²C Standard Specification as defined

by Philips.

2

MB95120MB Series

■ PRODUCT LINEUP

Part number*¹

MB95F124MB/

MB95F126MB/

MB95F128MB

MB95F124NB/

MB95F126NB/

MB95F128NB

Parameter

Type

Flash memory product

ROM capacity*²

RAM capacity*²

Reset output

Clock system

60 Kbytes (Max)

2 Kbytes (Max)

Yes

Dual clock

Low voltage

detection reset

No

Yes

Number of basic instructions

Instruction bit length

Instruction length

: 136

: 8 bits

: 1 to 3 bytes

: 1, 8, and 16 bits

CPU functions

Data bit length

Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)

Interrupt processing time : 0.6 µs (at machine clock frequency 16.25 MHz)

General-purpose I/O port (N-ch open drain)

General-purpose I/O port (CMOS)

Programmable input voltage levels of port :

: 2 ports

: 85 ports

Ports (Max 87 ports)

Automotive input level / CMOS input level / hysteresis input level

Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)

Reset generated cycle

Timebase timer

Watchdog timer

Wild register

At main oscillation clock 10 MHz

At sub oscillation clock 32.768 kHz

: Min 105 ms

: Min 250 ms

Capable of replacing 3 bytes of ROM data

Master/slave sending and receiving

Bus error function and arbitration function

Detecting transmitting direction function

I²C

Start condition repeated generation and detection functions

Built-in wake-up function

Data transfer capable in UART/SIO

Full duplex double buffer

Variable data length (5/6/7/8-bit), built-in baud rate generator

NRZ type transfer format, error detected function

LSB-first or MSB-first can be selected.

UART/SIO

LIN-UART

Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

Dedicated reload timer allowing a wide range of communication speeds to be set.

Full duplex double buffer.

Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

LIN functions available as the LIN master or LIN slave.

8/10-bit A/D converter

(12 channels)

8-bit or 10-bit resolution can be selected.

(Continued)

3

MB95120MB Series

(Continued)

Part number*¹

MB95F124MB/

MB95F126MB/

MB95F128MB

MB95F124NB/

MB95F126NB/

MB95F128NB

Parameter

COM output

SEG output

LCD drive power supply (bias) pin

40 SEG × 4 COM

Duty LCD mode

: 4 (Max)

: 40 (Max)

: 4 (Max)

LCD controller

(LCDC)

: 160 pixels can be displayed.

With blinking function

Built-in division resistance for LCD drive

Two clock modes and two counter operating modes can be selected.

Square waveform output

Count clock : 7 internal clocks and external clock can be selected.

Counter operating mode : reload mode or one-shot mode can be selected.

16-bit reload timer

Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer × 1

channel”.

Built-in timer function, PWC function, PWM function, capture function and square

waveform output

8/16-bitcompound

timer (2 channels)

Count clock : 7 internal clocks and external clock can be selected.

PWM mode or one-shot mode can be selected.

Counter operating clock : Eight selectable clock sources

Support for external trigger start

16-bit PPG

(2 channels)

Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1

channel”.

Counter operating clock : Eight selectable clock sources

8/16-bit PPG

(2 channels)

Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)

Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting

clock source 1 second and setting counter value to 60)

Watch counter

Watch prescaler

4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)

External interrupt Interrupt by edge detection (rising, falling, or both edges can be selected.)

(12 channels)

Flash memory

Standby mode

Can be used to recover from standby modes.

Supports automatic programming, Embedded Algorithm^TM

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Number of write/erase cycles (Minimum) : 10000 times

Data retention time : 20 years

Erase can be performed on each block

Block protection with external programming voltage

Flash Security Feature for protecting the content of the Flash

*

4

Sleep, stop, watch, and timebase timer

*1 : MASK ROM products are currently under consideration.

*2 : For ROM capacitance and RAM capacitance, refer to “1. Memory space” in “■ CPU CORE”.

*3 : For details of option, refer to “■ MASK OPTION”.

*4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

Note : Part number of evaluation device in MB95120MB series is MB95FV100D-103. When using it, the MCU board

(MB2146-303A) is required.

4

MB95120MB Series

■ OSCILLATION STABILIZATION WAIT TIME

The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum

value is shown as follows.

Oscillation stabilization wait time

Remarks

(2¹⁴−2) /F^CH

Approx. 4.10 ms (at main oscillation clock 4 MHz)

■ PACKAGES AND CORRESPONDING PRODUCTS

MB95F124MB/F124NB/

Part number

MB95F126MB/F126NB/

MB95FV100D-103

MB95F128MB/F128NB

Package

FPT-100P-M05

FPT-100P-M06

BGA-224P-M08

: Available

: Unavailable

5

MB95120MB Series

■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS

• Notes on Using Evaluation Products

The Evaluation product has not only the functions of the MB95120MB series but also those of other products

to support software development for multiple series and models of the F²MC-8FX family. The I/O addresses for

peripheral resources not used by the MB95120MB series are therefore access-barred. Read/write access to

these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting

in unexpected malfunctions of hardware or software.

Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are

used, the address may be read or written unexpectedly).

Note that the values read from barred addresses are different between the Evaluation product and the Flash

memory product. Therefore, the data must not be used for software processing.

The Evaluation product do not support the functions of some bits in single-byte registers. Read/write access to

these bits does not cause hardware malfunctions. The Evaluation, and Flash memory product are designed to

behave completely the same way in terms of hardware and software.

• Difference of Memory Spaces

If the amount of memory on the Evaluation product is different from that of the Flash memory product, carefully

check the difference in the amount of memory from the model to be actually used when developing software.

For details of memory space, refer to “■ CPU CORE”.

• Current Consumption

For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.

• Package

For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS”

and “■ PACKAGE DIMENSIONS”.

• Operating voltage

The operating voltage are different between the Evaluation and Flash memory products.

For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”.

6

MB95120MB Series

■ PIN ASSIGNMENT

(TOP VIEW)

100999897969594939291908988878685848382818079787776

VSS

C

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PC5/SEG13

PC6/SEG14

PC7/SEG15

PD0/SEG16

PD1/SEG17

PD2/SEG18

PD3/SEG19

PD4/SEG20

PD5/SEG21

PD6/SEG22

PD7/SEG23

PE0/SEG24

PE1/SEG25

PE2/SEG26

PE3/SEG27

PE4/SEG28/INT10

PE5/SEG29/INT11

PE6/SEG30/INT12

PE7/SEG31/INT13

P60/SEG32/PPG10

P61/SEG33/PPG11

MOD

P00/INT00

P01/INT01

P02/INT02

P03/INT03

P04/INT04

P05/INT05

P06/INT06

P07/INT07

P10/UI0

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P11/UO0

P12/UCK0

P13/TRG0/ADTG

P14/PPG0

P20/PPG00

P21/PPG01

P22/TO00

P23/TO01

P24/EC0

P50/SCL0

P51/SDA0

P52/PPG1

AVR

X0

X1

VSS

AVCC

26272829303132333435363738394041424344454647484950

(FPT-100P-M05)

(Continued)

7

MB95120MB Series

(Continued)

(TOP VIEW)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

P91/V2

P90/V3

PC4/SEG12

VCC

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VCC

VSS

C

PC5/SEG13

PC6/SEG14

PC7/SEG15

PD0/SEG16

PD1/SEG17

PD2/SEG18

PD3/SEG19

PD4/SEG20

PD5/SEG21

PD6/SEG22

PD7/SEG23

PE0/SEG24

PE1/SEG25

PE2/SEG26

PE3/SEG27

PE4/SEG28/INT10

PE5/SEG29/INT11

PE6/SEG30/INT12

PE7/SEG31/INT13

P60/SEG32/PPG10

P61/SEG33/PPG11

MOD

P00/INT00

P01/INT01

P02/INT02

P03/INT03

P04/INT04

P05/INT05

P06/INT06

P07/INT07

P10/UI0

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P11/UO0

P12/UCK0

P13/TRG0/ADTG

P14/PPG0

P20/PPG00

P21/PPG01

P22/TO00

P23/TO01

P24/EC0

P50/SCL0

P51/SDA0

P52/PPG1

AVR

X0

X1

V^SS

X1A

X0A

RST

AV^CC

AVSS

P30/AN00

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

(FPT-100P-M06)

8

MB95120MB Series

■ PIN DESCRIPTION

Pin no.

I/O

Pin name

circuit

Function

LQFP *¹

QFP *²

type*³

1

2

4

5

V^SS

⎯

Power supply pin (GND)

C

Capacitor connection pin

3

6

P00/INT00

P01/INT01

P02/INT02

P03/INT03

P04/INT04

P05/INT05

P06/INT06

P07/INT07

4

7

5

8

General-purpose I/O port

6

9

C

The pins are shared with external interrupt input. Large

current port.

7

10

11

12

13

8

9

10

General-purpose I/O port

The pin is shared with UART/SIO ch.0 data input.

11

12

13

14

15

16

P10/UI0

P11/UO0

P12/UCK0

G

H

General-purpose I/O port

The pin is shared with UART/SIO ch.0 data output.

General-purpose I/O port

The pin is shared with UART/SIO ch.0 clock I/O.

General-purpose I/O port

The pin is shared with 16-bit PPG ch.0 trigger input (TRG0)

and A/D trigger input (ADTG).

P13/TRG0/

ADTG

14

17

General-purpose I/O port

The pin is shared with 16-bit PPG ch.0 output.

15

18

P14/PPG0

16

17

18

19

20

21

P20/PPG00

P21/PPG01

P22/TO00

General-purpose I/O port

The pins are shared with 8/16-bit PPG ch.0 output.

General-purpose I/O port

The pins are shared with 8/16-bit compound timer ch.0 out-

put.

H

19

22

P23/TO01

General-purpose I/O port

20

23

P24/EC0

The pin is shared with 8/16-bit compound timer ch.0 clock

input.

General-purpose I/O port

21

22

23

24

25

26

P50/SCL0

P51/SDA0

P52/PPG1

The pin is shared with I²C ch.0 clock I/O.

I

General-purpose I/O port

The pin is shared with I²C ch.0 data I/O.

General-purpose I/O port

The pin is shared with 16-bit PPG ch.1 output.

H

24

25

27

28

AVR

AV^CC

⎯

A/D converter reference input pin

A/D converter power supply pin

(Continued)

9

MB95120MB Series

Pin no.

I/O

Pin name

circuit

Function

LQFP *¹

QFP *²

type*³

26

27

28

29

30

31

32

33

34

35

36

37

38

29

30

31

32

33

34

35

36

37

38

39

40

41

AV^SS

⎯

A/D converter power supply pin (GND)

P30/AN00

P31/AN01

P32/AN02

P33/AN03

P34/AN04

P35/AN05

P36/AN06

P37/AN07

P40/AN08

P41/AN09

P42/AN10

P43/AN11

General-purpose I/O port

The pins are shared with A/D converter analog input.

J

General-purpose I/O port

The pins are shared with A/D converter analog input.

J

General-purpose I/O port

The pin is shared with 16 - bit PPG ch.1 trigger input.

39

40

41

42

43

44

P53/TRG1

P70/TO0

P71/TI0

H

General-purpose I/O port

The pin is shared with 16 - bit reload timer ch.0 output.

General-purpose I/O port

The pin is shared with 16 - bit reload timer ch.0 input.

General-purpose I/O port

The pin is shared with LIN-UART data input (SIN) and LCDC

SEG output (SEG39) .

P67/SEG39/

SIN

42

43

44

45

46

47

48

N

General-purpose I/O port

The pin is shared with LIN-UART data output (SOT) and

LCDC SEG output (SEG38) .

P66/SEG38/

SOT

General-purpose I/O port

The pins are shared with LIN-UART clock I/O (SCK) and

LCDC SEG output (SEG37) .

P65/SEG37/

SCK

M

General-purpose I/O port

The pins are shared with 8/16-bit compound timer ch.1 clock

input (EC1) and LCDC SEG output (SEG36) .

P64/SEG36/

EC1

P63/SEG35/

TO11

46

47

49

50

General-purpose I/O port

The pins are shared with 8/16-bit compound timer ch.1 out-

put (TO10, TO11) and LCDC SEG output (SEG34, SEG35) .

P62/SEG34/

TO10

48

49

50

51

52

53

54

RST

X0A

X1A

V^SS

B'

A

Reset pin

Sub clock oscillation pin (32 kHz)

⎯

Power supply pin (GND)

(Continued)

10

MB95120MB Series

Pin no.

I/O

circuit

Pin name

Function

LQFP *¹

QFP *²

type*³

52

53

54

55

56

57

X1

X0

A

B

Main clock oscillation pin

MOD

An operating mode designation pin

P61/SEG33/

PPG11

55

56

57

58

59

60

58

59

60

61

62

63

General-purpose I/O port

The pins are shared with 8/16-bit PPG ch.1 output (PPG10,

PPG11) and LCDC SEG output (SEG32, SEG33) .

M

P60/SEG32/

PPG10

PE7/SEG31/

INIT13

PE6/SEG30/

INIT12

General-purpose I/O port

The pins are shared with external interrupt input (INIT10 to

INIT13) and LCDC SEG output (SEG28 to SEG31) .

Q

PE5/SEG29/

INIT11

PE4/SEG28/

INIT10

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

PE3/SEG27

PE2/SEG26

PE1/SEG25

PE0/SEG24

PD7/SEG23

PD6/SEG22

PD5/SEG21

PD4/SEG20

PD3/SEG19

PD2/SEG18

PD1/SEG17

PD0/SEG16

PC7/SEG15

PC6/SEG14

PC5/SEG13

V^CC

General-purpose I/O port

The pins are shared with LCDC SEG output.

M

General-purpose I/O port

The pins are shared with LCDC SEG output.

M

General-purpose I/O port

The pins are shared with LCDC SEG output.

M

⎯

Power supply pin

(Continued)

11

MB95120MB Series

(Continued)

Pin no.

I/O

Pin name

circuit

Function

LQFP *¹

QFP *²

type*³

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

1

PC4/SEG12

PC3/SEG11

PC2/SEG10

PC1/SEG09

PC0/SEG08

PB7/SEG07

PB6/SEG06

PB5/SEG05

PB4/SEG04

PB3/SEG03

PB2/SEG02

PB1/SEG01

PB0/SEG00

PA3/COM3

PA2/COM2

PA1/COM1

PA0/COM0

P95

General-purpose I/O port

The pins are shared with LCDC SEG output.

M

General-purpose I/O port

The pins are shared with LCDC SEG output.

M

General-purpose I/O port

The pins are shared with LCDC COM output.

M

General-purpose I/O port

P94

P93/V0

General-purpose I/O port

The pins are shared with power supply pins for LCDC

drive.

P92/V1

R

P91/V2

2

P90/V3

3

V^CC

⎯

Power supply pin

*1 : FPT-100P-M05

*2 : FPT-100P-M06

*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.

12

MB95120MB Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillation circuit

• High-speed side

Feedback resistance : approx. 1 MΩ

• Low-speed side

X1 (X1A)

Clock input

N-ch

A

X0 (X0A)

Feedback resistance : approx. 10 MΩ

Standby control

• Only for input

• Hysteresis input

B

Mode input

Reset input

• Reset output

• Hysteresis input

B’

Reset output

N-ch

• CMOS output

• Hysteresis input

• Automotive input

P-ch

Digital output

N-ch

C

Hysteresis input

Automotive input

Standby control

External interrupt

enable

• CMOS output

• CMOS input

R

P-ch

Pull-up control

• Hysteresis input

• With pull-up control

• Automotive input

P-ch

Digital output

G

N-ch

CMOS input

Hysteresis input

Automotive input

Standby control

(Continued)

13

MB95120MB Series

Type

Circuit

Remarks

• CMOS output

• Hysteresis input

• With pull-up control

• Automotive input

R

P-ch

Pull-up control

Digital output

P-ch

H

Digital output

N-ch

Hysteresis input

Automotive input

Standby control

• N-ch open drain output

• CMOS input

• Hysteresis input

• Automotive input

Digital output

CMOS input

N-ch

I

Hysteresis input

Automotive input

Standby control

• CMOS output

• Hysteresis input

• Analog input

R

P-ch

Pull-up control

• With pull-up control

• Automotive input

P-ch

Digital output

N-ch

J

Analog input

Hysteresis input

Automotive input

A/D control

Standby control

• CMOS output

• LCD output

• Hysteresis input

• Automotive input

P-ch

Digital output

N-ch

M

LCD output

Hysteresis input

Automotive input

LCD control

Standby control

(Continued)

14

MB95120MB Series

(Continued)

Type

Circuit

Remarks

• CMOS output

• LCD output

• CMOS input

• Hysteresis input

• Automotive input

P-ch

Digital output

N-ch

N

LCD output

CMOS input

Hysteresis input

Automotive input

LCD control

Standby control

• CMOS output

• LCD output

• Hysteresis input

• Automotive input

P-ch

N-ch

Digital output

Q

LCD output

Hysteresis input

Automotive input

LCD control

Standby control

External

interrupt control

• CMOS output

• LCD power supply

• Hysteresis input

• Automotive input

P-ch

N-ch

Digital output

LCD built-in division

resistance I/O

R

Hysteresis input

Automotive input

LCD control

Standby control

15

MB95120MB Series

■ HANDLING DEVICES

• Preventing Latch-up

Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.

Latch-up may occur on CMOS ICs if voltage higher than V^CCor lower than V^SSis applied to input and output pins

other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between V^CC

pin and V^SSpin.

When latch-up occurs, power supply current increases rapidly and might thermally damage elements.

Also, take care to prevent the analog power supply voltage (AV^CC, AVR) and analog input voltage from exceeding

the digital power supply voltage (V^CC) when the analog system power supply is turned on or off.

• Stable Supply Voltage

Supply voltage should be stabilized.

A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range

of the V^CCpower-supply voltage.

For stabilization, in principle, keep the variation in V^CCripple (p-p value) in a commercial frequency range

(50/60 Hz) not to exceed 10% of the standard V^CCvalue and suppress the voltage variation so that the transient

variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.

• Precautions for Use of External Clock

Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up

from sub clock mode or stop mode.

■ PIN CONNECTION

• Treatment of Unused Pin

Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent

damage.

Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/

output pins may be set to output mode and left open, or set to input mode and treated the same as unused input

pins. If there is unused output pin, make it open.

• Treatment of Power Supply Pins on A/D Converter

Connect to be AV^CC= V^CCand AV^SS= AVR = V^SSeven if the A/D converter is not in use.

Noise riding on the AV^CCpin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor

as a bypass capacitor between AV^CCand AV^SSpins in the vicinity of this device.

• Power Supply Pins

In products with multiple V^CCor V^SSpins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply

and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals

caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V^CCand V^SSpins of this device at the low impedance.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between V^CCand V^SSnear

this device.

16

MB95120MB Series

• Mode Pin (MOD)

Connect the mode pin directly to V^CCor V^SSpins.

To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to

minimize the distance from the mode pins to V^CCor V^SSpins and to provide a low-impedance connection.

Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of V^CCpin

must have a capacitance value higher than C^S. For connection of smoothing capacitor C^S, refer to the diagram

below.

• C pin connection diagram

C

CS

• Analog Power Supply

Always set the same potential to AV^CCand V^CCpins. When V^CC> AV^CC, the current may flow through the AN00

to AN11 pins.

17

MB95120MB Series

■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL

PROGRAMMER

• Supported Parallel Programmers and Adapters

The following table lists supported parallel programmers and adapters.

Package

Applicable adapter model

Parallel programmers

AF9708 (Ver 02.35G or more)

AF9709/B (Ver 02.35G or more)

AF9723+AF9834 (Ver 02.08E or more)

FPT-100P-M05

TEF110-95F128HSPFV

FPT-100P-M06

TEF110-95F128HSPF

Note : For information on applicable adapter models and parallel programmers, contact the following:

Flash Support Group, Inc. TEL: +81-53-428-8380

• Sector Configuration

The individual sectors of Flash memory correspond to addresses used for CPU access and programming by

the parallel programmer as follows:

• MB95F128MB/F128NB (60 Kbytes)

Flash memory

CPU address

Programmer address*

71000^H

1000^H

SA1 (4 Kbytes)

1FFF^H

2000^H

71FFF^H

72000^H

SA2 (4 Kbytes)

SA3 (4 Kbytes)

SA4 (16 Kbytes)

SA5 (16 Kbytes)

SA6 (4 Kbytes)

SA7 (4 Kbytes)

SA8 (4 Kbytes)

SA9 (4 Kbytes)

2FFF^H

3000^H

72FFF^H

73000^H

3FFF^H

4000^H

73FFF^H

74000^H

7FFF^H

8000^H

77FFF^H

78000^H

BFFF^H

C000^H

7BFFF^H

7C000^H

CFFF^H

D000^H

7CFFF^H

7D000^H

DFFF^H

E000^H

7DFFF^H

7E000^H

EFFF^H

F000^H

7EFFF^H

7F000^H

FFFF^H

7FFFF^H

*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer

programs data into Flash memory.

These programmer addresses are used for the parallel programmer to program or erase data in Flash

memory.

18

MB95120MB Series

• MB95F126MB/F126NB (32 Kbytes)

Flash memory

CPU address

Programmer address*

78000^H

8000^H

SA5 (16 Kbytes)

BFFF^H

C000^H

7BFFF^H

7C000^H

SA6 (4 Kbytes)

SA7 (4 Kbytes)

SA8 (4 Kbytes)

SA9 (4 Kbytes)

CFFF^H

D000^H

7CFFF^H

7D000^H

DFFF^H

E000^H

7DFFF^H

7E000^H

EFFF^H

F000^H

7EFFF^H

7F000^H

FFFF^H

7FFFF^H

*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer

programs data into Flash memory.

These programmer addresses are used for the parallel programmer to program or erase data in Flash

memory.

• MB95F124MB/F124NB (16 Kbytes)

Flash memory

CPU address

Programmer address*

7C000^H

C000^H

SA6 (4 Kbytes)

CFFF^H

D000^H

7CFFF^H

7D000^H

SA7 (4 Kbytes)

SA8 (4 Kbytes)

SA9 (4 Kbytes)

DFFF^H

E000^H

7DFFF^H

7E000^H

EFFF^H

F000^H

7EFFF^H

7F000^H

FFFF^H

7FFFF^H

*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer

programs data into Flash memory.

These programmer addresses are used for the parallel programmer to program or erase data in Flash

memory.

• Programming Method

1) Set the type code of the parallel programmer to 17222.

2) Load program data to programmer addresses 71000^Hto 7FFFF^H.

3) Programmed by parallel programmer

19

MB95120MB Series

■ BLOCK DIAGRAM

F²MC-8FX CPU

RST

ROM

RAM

Reset control

X0,X1

Clock control

X0A/X1A

Interrupt control

Wild register

Watch prescaler

Watch counter

P60/SEG32/PPG10

P61/SEG33/PPG11

P00/INT00 to P07/INT07

External interrupt ch.0 to ch.7

8/16-bit PPG ch.1

P10/UI0

P11/UO0

P12/UCK0

P62/SEG34/TO10

P63/SEG35/TO11

P64/SEG36/EC1

UART/SIO

8/16-bit compound

timer ch.1

P13/TRG0/ADTG

P14/PPG0

16-bit PPG ch.0

P65/SEG37/SCK

P66/SEG38/SOT

P67/SEG39/SIN

LIN-UART

P20/PPG00

P21/PPG01

8/16-bit PPG ch.0

P70/TO0

P71/TI0

16-bit reload timer

P22/TO00

P23/TO01

P24/EC0

8/16-bit compound

timer ch.0

P90/V3 to P93/V0

P94, P95

P30/AN00 to P37/AN07

PA0/COM0 to PA3/COM3

PB0/SEG00 to PB7/SEG07

PC0/SEG08 to PC7/SEG15

PD0/SEG16 to PD7/SEG23

PE0/SEG24 to PE3/SEG27

PE4/SEG28/INT10

P40/AN08 to P43/AN11

8/10-bit A/D

converter

AV^CC

AVSS

AVR

LCDC

P50/SCL0

P51/SDA0

I ²C

PE5/SEG29/INT11

PE6/SEG30/INT12

P52/PPG1

P53/TRG1

External interrupt ch.8 to ch.11

PE7/SEG31/INT13

16-bit PPG ch.1

Port

Other pins

MOD, V^CC, C

20

MB95120MB Series

■ CPU CORE

1. Memory space

Memory space of the MB95120MB series is 64 Kbytes and consists of I/O area, data area, and program area.

The memory space includes special - purpose areas such as the general - purpose registers and vector table.

Memory map of the MB95120MB series is shown below.

• Memory Map

MB95F124MB/F124NB

MB95F126MB/F126NB

MB95F128MB/F128NB

MB95FV100D-103

I/O

0000H

0000^H

I/O

0080H

0100H

0200H

0080H

0100H

0200H

RAM 2 Kbytes

Register

RAM 3.75 Kbytes

Register

Address #1

0F80^H

Access

prohibited

0F80H

1000H

Extended I/O

Address #2

Flash memory

60 Kbytes

FFFF^H

FFFFH

Flash memory

RAM

Address #1

Address #2

MB95F124MB

MB95F124NB

MB95F126MB

MB95F126NB

MB95F128MB

MB95F128NB

16 Kbytes

512 bytes

1 Kbyte

0280^H

0480^H

0880^H

C000^H

32 Kbytes

60 Kbytes

8000^H

1000^H

2 Kbytes

21

MB95120MB Series

2. Register

The MB95120MB series has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The dedicated registers are as follows:

Program counter (PC)

: A 16-bit register to indicate locations where instructions are stored.

Accumulator (A)

: A 16-bit register for temporary storage of arithmetic operations. In the case of

an 8-bit data processing instruction, the lower 1 byte is used.

Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.

In the case of an 8-bit data processing instruction, the lower 1 byte is used.

Index register (IX)

Extra pointer (EP)

Stack pointer (SP)

Program status (PS)

: A 16-bit register for index modification

: A 16-bit pointer to point to a memory address.

: A 16-bit register to indicate a stack area.

: A 16-bit register for storing a register bank pointer, a direct bank pointer, and

a condition code register

Initial Value

16-bit

FFFD^H

0000^H

0030^H

: Program counter

: Accumulator

PC

A

T

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer

(DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.)

• Structure of the program status

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

R4

R3

R2

R1

R0 DP2 DP1 DP0

H

I

IL1

IL0

N

Z

PS

C

V

RP

DP

CCR

22

MB95120MB Series

The RP indicates the address of the register bank currently being used. The relationship between the content

of RP and the real address conforms to the conversion rule illustrated below:

• Rule for Conversion of Actual Addresses in the General-purpose Register Area

RP upper

OP code lower

"0" "0" "0" "0" "0" "0" "0" "1"

R4 R3 R2 R1 R0 b2

b1

b0

Generated address

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct

addresses to 0080^Hto 00FF^H.

Direct bank pointer (DP2 to DP0)

Specified address area

Mapping area

0000^Hto 007F^H(without mapping)

0080^Hto 00FF^H(without mapping)

0100^Hto 017F^H

XXX^B(no effect to mapping)

0000^Hto 007F^H

000^B(initial value)

001^B

010^B

011^B

100^B

101^B

110^B

111^B

0180^Hto 01FF^H

0200^Hto 027F^H

0080^Hto 00FF^H

0280^Hto 02FF^H

0300^Hto 037F^H

0380^Hto 03FF^H

0400^Hto 047F^H

The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that

control CPU operations at interrupt.

H flag

I flag

Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.

Cleared to “0” otherwise. This flag is for decimal adjustment instructions.

:

Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.

The flag is cleared to “0” when reset.

IL1, IL0

Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level

is higher than the value indicated by these bits.

IL1

0

IL0

0

Interrupt level

Priority

0

1

2

3

High

0

1

0

Low = no interruption

1

N flag

Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the

bit is set to “0”.

:

Z flag

V flag

Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.

Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”

otherwise.

C flag

Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared

to “0” otherwise. Set to the shift-out value in the case of a shift instruction.

:

23

MB95120MB Series

The following general-purpose registers are provided:

General-purpose registers: 8-bit data storage registers

The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8-

registers. Up to a total of 32 banks can be used on the MB95120MB series. The bank currently in use is indicated

by the register bank pointer (RP).8-register. Up to a total of 32 banks can be used on the MB95120MB series.

The bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates

the general-purpose register 0 (R0) to general-purpose register 7 (R7).

• Register Bank Configuration

8-bit

1F8_H

This address = 0100H + 8 × (RP)

Address 100_H

R0

R1

R0

R1

R0

R1

R2

R3

R4

R5

R6

R7

R2

R3

R4

R5

R6

R7

R2

R3

R4

R5

R6

R7

1FF_H

Bank 31

107_H

32 banks

32 banks (RAM area)

The number of banks is

limited by the usable RAM

capacitance.

Bank 0

Memory area

24

MB95120MB Series

■ I/O MAP

Register

abbreviation

Address

Register name

R/W

Initial value

0000^H

0001^H

0002^H

0003^H

0004^H

0005^H

0006^H

0007^H

0008^H

0009^H

000A^H

000B^H

000C^H

000D^H

000E^H

000F^H

0010^H

0011^H

0012^H

0013^H

0014^H

0015^H

0016^H

0017^H

0018^H

0019^H

PDR0

DDR0

PDR1

DDR1

⎯

Port 0 data register

Port 0 direction register

Port 1 data register

R/W

⎯

00000000^B

⎯

Port 1 direction register

(Disabled)

WATR

PLLC

SYCC

STBC

RSRR

TBTC

WPCR

WDTC

⎯

Oscillation stabilization wait time setting register

PLL control register

R/W

R

11111111^B

00000000^B

1010X011^B

00000000^B

XXXXXXXX^B

00000000^B

⎯

System clock control register

Standby control register

Reset source register

Timebase timer control register

Watch prescaler control register

Watchdog timer control register

(Disabled)

R/W

⎯

PDR2

DDR2

PDR3

DDR3

PDR4

DDR4

PDR5

DDR5

PDR6

DDR6

PDR7

DDR7

Port 2 data register

R/W

00000000^B

Port 2 direction register

Port 3 data register

Port 3 direction register

Port 4 data register

Port 4 direction register

Port 5 data register

Port 5 direction register

Port 6 data register

Port 6 direction register

Port 7 data register

Port 7 direction register

001A^H,

001B^H

⎯

(Disabled)

⎯

001C^H

001D^H

001E^H

001F^H

0020^H

0021^H

0022^H

PDR9

DDR9

PDRA

DDRA

PDRB

DDRB

PDRC

Port 9 data register

Port 9 direction register

Port A data register

R/W

00000000^B

(Continued)

Port A direction register

Port B data register

Port B direction register

Port C data register

25

MB95120MB Series

Register

Address

Register name

R/W

Initial value

abbreviation

0023^H

0024^H

0025^H

0026^H

0027^H

DDRC

PDRD

DDRD

PDRE

DDRE

Port C direction register

Port D data register

R/W

00000000^B

Port D direction register

Port E data register

Port E direction register

0028^H

to

002C^H

⎯

(Disabled)

⎯

002D^H

002E^H

002F^H

0030^H

0031^H

0032^H

PUL1

PUL2

PUL3

PUL4

PUL5

PUL7

Port 1 pull-up register

Port 2 pull-up register

Port 3 pull-up register

Port 4 pull-up register

Port 5 pull-up register

Port 7 pull-up register

R/W

00000000^B

0033^H

to

0035^H

⎯

(Disabled)

⎯

0036^H

0037^H

0038^H

0039^H

003A^H

003B^H

003C^H

003D^H

003E^H

003F^H

T01CR1

T00CR1

T11CR1

T10CR1

PC01

8/16-bit compound timer 01 control status register 1 ch.0

8/16-bit compound timer 00 control status register 1 ch.0

8/16-bit compound timer 11 control status register 1 ch.1

8/16-bit compound timer 10 control status register 1 ch.1

8/16-bit PPG1 control register ch.0

R/W

00000000^B

PC00

8/16-bit PPG0 control register ch.0

PC11

8/16-bit PPG1 control register ch.1

PC10

8/16-bit PPG0 control register ch.1

TMCSRH0

TMCSRL0

16-bit reload timer control status register (upper byte) ch.0 R/W

16-bit reload timer control status register (lower byte) ch.0

R/W

0040^H,

0041^H

⎯

(Disabled)

⎯

0042^H

0043^H

0044^H

0045^H

PCNTH0

PCNTL0

PCNTH1

PCNTL1

16-bit PPG status control register (upper byte) ch.0

16-bit PPG status control register (lower byte) ch.0

16-bit PPG status control register (upper byte) ch.1

16-bit PPG status control register (lower byte) ch.1

R/W

00000000^B

0046^H,

0047^H

⎯

(Disabled)

⎯

0048^H

0049^H

EIC00

EIC10

External interrupt circuit control register ch.0/ch.1

External interrupt circuit control register ch.2/ch.3

R/W

00000000^B

(Continued)

26

MB95120MB Series

Register

abbreviation

Address

Register name

R/W Initial value

004A^H

004B^H

004C^H

004D^H

EIC20

EIC30

EIC01

EIC11

External interrupt circuit control register ch.4/ch.5

External interrupt circuit control register ch.6/ch.7

External interrupt circuit control register ch.8/ch.9

External interrupt circuit control register ch.10/ch.11

R/W

00000000^B

004E^H,

004F^H

⎯

(Disabled)

⎯

0050^H

0051^H

0052^H

0053^H

0054^H

0055^H

0056^H

0057^H

0058^H

0059^H

005A^H

SCR

SMR

LIN-UART serial control register

LIN-UART serial mode register

R/W

R

00000000^B

00001000^B

00000000^B

00000100^B

000000XX^B

00000000^B

00100000^B

00000001^B

00000000^B

SSR

LIN-UART serial status register

RDR/TDR

ESCR

ECCR

SMC10

SMC20

SSR0

LIN-UART reception/transmission data register

LIN-UART extended status control register

LIN-UART extended communication control register

UART/SIO serial mode control register 1 ch.0

UART/SIO serial mode control register 2 ch.0

UART/SIO serial status register ch.0

TDR0

UART/SIO serial output data register ch.0

UART/SIO serial input data register ch.0

RDR0

005B^H

to

005F^H

⎯

(Disabled)

⎯

0060^H

0061^H

0062^H

0063^H

0064^H

0065^H

IBCR00

IBCR10

IBSR0

IDDR0

IAAR0

ICCR0

I²C bus control register 0 ch.0

I²C bus control register 1 ch.0

I²C bus status register ch.0

I²C data register ch.0

R/W

R

00000000^B

R/W

I²C address register ch.0

I²C clock control register ch.0

0066^H

to

006B^H

⎯

(Disabled)

⎯

006C^H

006D^H

006E^H

006F^H

0070^H

0071^H

0072^H

ADC1

ADC2

ADDH

ADDL

WCSR

⎯

8/10-bit A/D converter control register 1

8/10-bit A/D converter control register 2

8/10-bit A/D converter data register (upper byte)

8/10-bit A/D converter data register (lower byte)

Watch counter status register

R/W

⎯

00000000^B

⎯

(Disabled)

FSR

Flash memory status register

R/W

000X0000^B

(Continued)

27

MB95120MB Series

Register

Address

Register name

R/W Initial value

abbreviation

0073^H

0074^H

0075^H

0076^H

0077^H

SWRE0

SWRE1

⎯

Flash memory sector writing control register 0

Flash memory sector writing control register 1

(Disabled)

R/W

⎯

00000000^B

⎯

WREN

WROR

Wild register address compare enable register

Wild register data test setting register

R/W

00000000^B

Register bank pointer (RP) ,

Mirror of direct bank pointer (DP)

0078^H

⎯

0079^H

007A^H

007B^H

007C^H

007D^H

007E^H

007F^H

0F80^H

0F81^H

0F82^H

0F83^H

0F84^H

0F85^H

0F86^H

0F87^H

0F88^H

ILR0

ILR1

Interrupt level setting register 0

Interrupt level setting register 1

R/W

⎯

11111111^B

⎯

ILR2

Interrupt level setting register 2

ILR3

Interrupt level setting register 3

ILR4

Interrupt level setting register 4

ILR5

Interrupt level setting register 5

⎯

(Disabled)

WRARH0

WRARL0

WRDR0

WRARH1

WRARL1

WRDR1

WRARH2

WRARL2

WRDR2

Wild register address setting register (upper byte) ch.0

Wild register address setting register (lower byte) ch.0

Wild register data setting register ch.0

Wild register address setting register (upper byte) ch.1

Wild register address setting register (lower byte) ch.1

Wild register data setting register ch.1

Wild register address setting register (upper byte) ch.2

Wild register address setting register (lower byte) ch.2

Wild register data setting register ch.2

R/W

00000000^B

0F89^H

to

0F91^H

⎯

(Disabled)

⎯

0F92^H

0F93^H

0F94^H

0F95^H

T01CR0

T00CR0

T01DR

T00DR

8/16-bit compound timer 01 control status register 0 ch.0

8/16-bit compound timer 00 control status register 0 ch.0

8/16-bit compound timer 01 data register ch.0

R/W

00000000^B

8/16-bit compound timer 00 data register ch.0

8/16-bit compound timer 00/01 timer mode control register

ch.0

0F96^H

TMCR0

R/W

00000000^B

0F97^H

0F98^H

0F99^H

0F9A^H

T11CR0

T10CR0

T11DR

T10DR

8/16-bit compound timer 11 control status register 0 ch.1

8/16-bit compound timer 10 control status register 0 ch.1

8/16-bit compound timer 11 data register ch.1

R/W

00000000^B

8/16-bit compound timer 10 data register ch.1

00000000^B

(Continued)

28

MB95120MB Series

Register

abbreviation

Address

Register name

R/W Initial value

8/16-bit compound timer 10/11 timer mode control register

ch.1

0F9B^H

TMCR1

R/W

00000000^B

0F9C^H

0F9D^H

0F9E^H

0F9F^H

0FA0^H

0FA1^H

0FA2^H

0FA3^H

0FA4^H

0FA5^H

PPS01

PPS00

PDS01

PDS00

PPS11

PPS10

PDS11

PDS10

PPGS

8/16-bit PPG1 cycle setting buffer register ch.0

8/16-bit PPG0 cycle setting buffer register ch.0

8/16-bit PPG1 duty setting buffer register ch.0

8/16-bit PPG0 duty setting buffer register ch.0

8/16-bit PPG1 cycle setting buffer register ch.1

8/16-bit PPG0 cycle setting buffer register ch.1

8/16-bit PPG1 duty setting buffer register ch.1

8/16-bit PPG0 duty setting buffer register ch.1

8/16-bit PPG start register

R/W

11111111^B

00000000^B

REVC

8/16-bit PPG output inversion register

TMRH0/

TMRLRH0

0FA6^H

0FA7^H

16-bit reload timer timer/reload register (upper byte) ch.0

16-bit reload timer timer/reload register (lower byte) ch.0

(Disabled)

R/W

⎯

00000000^B

⎯

TMRL0/

TMRLRL0

0FA8^H,

0FA9^H

⎯

0FAA^H

0FAB^H

0FAC^H

0FAD^H

0FAE^H

0FAF^H

0FB0^H

0FB1^H

0FB2^H

0FB3^H

0FB4^H

0FB5^H

PDCRH0

PDCRL0

PCSRH0

PCSRL0

PDUTH0

PDUTL0

PDCRH1

PDCRL1

PCSRH1

PCSRL1

PDUTH1

PDUTL1

16-bit PPG down counter register (upper byte) ch.0

16-bit PPG down counter register (lower byte) ch.0

16-bit PPG cycle setting buffer register (upper byte) ch.0

16-bit PPG cycle setting buffer register (lower byte) ch.0

16-bit PPG duty setting buffer register (upper byte) ch.0

16-bit PPG duty setting buffer register (lower byte) ch.0

16-bit PPG down counter register (upper byte) ch.1

16-bit PPG down counter register (lower byte) ch.1

16-bit PPG cycle setting buffer register (upper byte) ch.1

16-bit PPG cycle setting buffer register (lower byte) ch.1

16-bit PPG duty setting buffer register (upper byte) ch.1

16-bit PPG duty setting buffer register (lower byte) ch.1

R

00000000^B

11111111^B

00000000^B

11111111^B

R

R/W

R

R/W

0FB6^H

to

0FBB^H

⎯

(Disabled)

⎯

0FBC^H

0FBD^H

BGR1

BGR0

LIN-UART baud rate generator register 1

LIN-UART baud rate generator register 0

R/W

00000000^B

UART/SIO dedicated baud rate generator

prescaler select register ch.0

0FBE^H

PSSR0

R/W

00000000^B

(Continued)

29

MB95120MB Series

(Continued)

Register

Address

Register name

R/W Initial value

abbreviation

UART/SIO dedicated baud rate generator

baud rate setting register ch.0

0FBF^H

BRSR0

R/W

00000000^B

0FC0^H,

0FC1^H

⎯

(Disabled)

⎯

0FC2^H

0FC3^H

0FC4^H

0FC5^H

0FC6^H

0FC7^H

0FC8^H

0FC9^H

0FCA^H

0FCB^H

0FCC^H

AIDRH

AIDRL

A/D input disable register (upper byte)

A/D input disable register (lower byte)

LCDC control register

R/W

00000000^B

00010000^B

00110000^B

00000000^B

LCDCC

LCDCE1

LCDCE2

LCDCE3

LCDCE4

LCDCE5

LCDCE6

LCDCB1

LCDCB2

LCDC enable register 1

LCDC enable register 2

LCDC enable register 3

LCDC enable register 4

LCDC enable register 5

LCDC enable register 6

LCDC blinking setting register 1

LCDC blinking setting register 2

0FCD^H

to

LCDRAM

LCDC display RAM

R/W

00000000^B

0FE0^H

0FE1^H,

0FE2^H

⎯

WCDR

⎯

(Disabled)

Watch counter data register

(Disabled)

⎯

R/W

⎯

00111111^B

⎯

0FE3^H

0FE4^H,

0FE5^H

0FE6^H

0FE7^H

ILSR3

ILSR2

Input level select register 3

Input level select register 2

R/W

00000000^B

0FE8^H

to

0FED^H

⎯

(Disabled)

⎯

0FEE^H

0FEF^H

ILSR

Input level select register

R/W

00000000^B

01000000^B

WICR

Interrupt pin select circuit control register

0FF0^H

to

0FFF^H

⎯

(Disabled)

⎯

30

MB95120MB Series

• R/W access symbols

R/W : Readable/Writable

R

: Read only

: Write only

W

• Initial value symbols

0

: The initial value of this bit is “0”.

1

: The initial value of this bit is “1”.

X

: The initial value of this bit is undefined.

Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.

31

MB95120MB Series

■ INTERRUPT SOURCE TABLE

Vector table address

Same level

priority order

(atsimultaneous

occurrence)

Interrupt

request

number

Bit name of

interrupt level

setting register

Interrupt source

Upper

FFFA^H

FFF8^H

FFF6^H

FFF4^H

Lower

FFFB^H

FFF9^H

FFF7^H

FFF5^H

External interrupt ch.0

High

IRQ0

IRQ1

IRQ2

IRQ3

L00 [1 : 0]

L01 [1 : 0]

L02 [1 : 0]

L03 [1 : 0]

External interrupt ch.4

External interrupt ch.1

External interrupt ch.5

External interrupt ch.2

External interrupt ch.6

External interrupt ch.3

External interrupt ch.7

UART/SIO ch.0

IRQ4

IRQ5

FFF2^H

FFF0^H

FFEE^H

FFEC^H

FFEA^H

FFE8^H

FFE6^H

FFE4^H

FFE2^H

FFE0^H

FFDE^H

FFDC^H

FFDA^H

FFD8^H

FFD6^H

FFD4^H

FFD2^H

FFF3^H

FFF1^H

FFEF^H

FFED^H

FFEB^H

FFE9^H

FFE7^H

FFE5^H

FFE3^H

FFE1^H

FFDF^H

FFDD^H

FFDB^H

FFD9^H

FFD7^H

FFD5^H

FFD3^H

L04 [1 : 0]

L05 [1 : 0]

L06 [1 : 0]

L07 [1 : 0]

L08 [1 : 0]

L09 [1 : 0]

L10 [1 : 0]

L11 [1 : 0]

L12 [1 : 0]

L13 [1 : 0]

L14 [1 : 0]

L15 [1 : 0]

L16 [1 : 0]

L17 [1 : 0]

L18 [1 : 0]

L19 [1 : 0]

L20 [1 : 0]

8/16-bit compound timer ch.0 (Lower)

8/16-bit compound timer ch.0 (Upper)

LIN-UART (reception)

LIN-UART (transmission)

8/16-bit PPG ch.1 (Lower)

8/16-bit PPG ch.1 (Upper)

16-bit reload timer ch.0

8/16-bit PPG ch.0 (Upper)

8/16-bit PPG ch.0 (Lower)

8/16-bit compound timer ch.1 (Upper)

16-bit PPG ch.0

IRQ6

IRQ7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

IRQ16

IRQ17

IRQ18

IRQ19

IRQ20

I²C ch.0

16-bit PPG ch.1

8/10-bit A/D converter

Timebase timer

Watch timer/counter

External interrupt ch.8

External interrupt ch.9

External interrupt ch.10

External interrupt ch.11

8/16-bit compound timer ch.1 (Lower)

Flash memory

IRQ21

FFD0^H

FFD1^H

L21 [1 : 0]

IRQ22

IRQ23

FFCE^H

FFCC^H

FFCF^H

FFCD^H

L22 [1 : 0]

L23 [1 : 0]

Low

32

MB95120MB Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

Vcc

AVcc

Vss − 0.3

V^SS− 0.3

Vss + 6.0

V^SS+ 6.0

*2

*3

Power supply voltage*¹

V

AVR

Powersupplyvoltagefor

LCD

V0 to V3

Input voltage*¹

V^I

V^O

Vss − 0.3

− 2.0

Vss + 6.0

+ 2.0

*4

V

Output voltage*¹

Maximum clamp current

I^CLAMP

mA Applicable to pins*⁵

Total maximum clamp

current

Σ|I^CLAMP|

⎯

20

mA Applicable to pins*⁵

I^OL1

I^OL2

15

Other than P00 to P07

“L” level maximum

output current

mA

P00 to P07

Other than P00 to P07

Average output current =

operating current × operating ratio

I^OLAV1

4

(1 pin)

“L” level average

current

⎯

mA

P00 to P07

Average output current =

operating current × operating ratio

(1 pin)

I^OLAV2

12

“L” level total maximum

output current

ΣI^OL

⎯

100

50

mA

Total average output current =

mA operating current × operating ratio

(Total of pins)

“L” level total average

output current

ΣI^OLAV

I^OH1

I^OH2

− 15

Other than P00 to P07

“H” level maximum

output current

⎯

mA

P00 to P07

Other than P00 to P07

Average output current =

operating current × operating ratio

I^OHAV1

− 4

− 8

(1 pin)

“H” level average

current

⎯

mA

P00 to P07

Average output current =

operating current × operating ratio

(1 pin)

I^OHAV2

“H” level total maximum

output current

ΣI^OH

⎯

− 100

− 50

mA

Total average output current =

mA operating current × operating ratio

(Total of pins)

“H” level total average

output current

ΣI^OHAV

(Continued)

33

MB95120MB Series

(Continued)

Rating

Parameter

Symbol

Unit

Remarks

Min

⎯

Max

320

Power consumption

Operating temperature

Storage temperature

Pd

T^A

mW

°C

− 40

− 55

+ 85

+ 150

Tstg

°C

*1 : The parameter is based on AV^SS= V^SS= 0.0 V.

*2 : Apply equal potential to AVcc and Vcc. AVR should not exceed AVcc + 0.3 V.

*3 : V0 to V3 should not exceed V^CC+ 0.3 V.

*4 : V^Iand Vo should not exceed V^CC+ 0.3 V. V^Imust not exceed the rating voltage. However, if the maximum current

to/from an input is limited by some means with external components, the I^CLAMPrating supersedes the V^Irating.

*5 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53

• Use within recommended operating conditions.

• Use at DC voltage (current).

• +B signal is an input signal that exceeds V^CCvoltage. The + B signal should always be applied a limiting

resistance placed between the + B signal and the microcontroller.

• The value of the limiting resistance should be set so that when the + B signal is applied the input current

to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this affects

other devices.

• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power

supply is provided from the pins, so that incomplete operation may result.

• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the

resulting power supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the + B input pin open.

• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept

+B signal input.

• Sample recommended circuits :

• Input/Output Equivalent circuits

Protective diode

Vcc

Limiting

P-ch

resistance

+ B input (0 V to 16 V)

N-ch

R

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

34

MB95120MB Series

2. Recommended Operating Conditions

(AV^SS= V^SS= 0.0 V)

Value

Con-

dition

Parameter Symbol

Pin name

Unit

Remarks

Min

Max

In normal

operating

⎯

2.5*^1,*²

5.5*¹

Other than

MB95FV100D

-103

Hold

condition in

STOP mode

⎯

2.3

5.5

Power supply

voltage

V^CC,

AV^CC

V

In normal

operating

2.7

MB95FV100D

-103

Hold

condition in

STOP mode

2.3

The range of liquid crystal

power supply: without up-

conversion (The optimal

value depends on liquid

crystal display elements

used.)

Power supply

voltage for

LCD

V0 to

V3

⎯

V^SS

V^CC

V

P10 (selectable at UI) ,

P67 (selectable at SIN)

V^IH1

V^IH2

V^IHA

⎯

0.7 V^CCV^CC+ 0.3

0.7 V^CCV^SS+ 5.5

0.8 V^CCV^CC+ 0.3

V

Hysteresis input

(When selecting CMOS

input level)

P50, P51

(selectable at I²C)

Port inputs if Automotive

input levels are selected

⎯

P00 to P07,

P10 to P14,

P20 to P24,

P30 to P37,

P40 to P43,

P52, P53,

“H” level input

voltage

P60 to P67,

P70, P71,

V^IHS1

⎯

0.8 V^CCV^CC+ 0.3

V

Hysteresis input

P90 to P95,

PA0 to PA3,

PB0 to PB7,

PC0 to PC7,

PD0 to PD7,

PE0 to PE7

V^IHS2

V^IHM

P50, P51

⎯

0.8 V^CCV^SS+ 5.5

0.8 V^CCV^CC+ 0.3

V

RST, MOD

Hysteresis input

P10 (selectable at UI) ,

P50, P51

(selectable at I²C)

P67 (selectable at SIN)

Hysteresis input

(When selecting CMOS

input level)

“L” level input

voltage

V^IL

⎯

V^SS− 0.3 0.3 V^CC

V

(Continued)

35

MB95120MB Series

(Continued)

Value

Min Max

Condi-

tion

Parameter

Symbol Pin name

Unit

Remarks

Port inputs if Automotive input

levels are selected

V^ILA

⎯

V^SS− 0.3 0.5 V^CC

V

P00 to P07,

P10 to P14,

P20 to P24,

P30 to P37,

P40 to P43,

P50 to P53,

P60 to P67,

P70, P71,

“L” level input voltage

V^ILS

⎯

V^SS− 0.3 0.2 V^CC

V

Hysteresis input

P90 to P95,

PA0 to PA3,

PB0 to PB7,

PC0 to PC7,

PD0 to PD7,

PE0 to PE7

V^ILM

AVR

C^S

RST, MOD

⎯

V^SS− 0.3 0.2 V^CC

V

Hysteresis input

A/D converter

reference input voltage

⎯

4.0

0.1

AV^CC

1.0

Smoothing capacitor

µF *3

Other than MB95FV100D-

103

°C MB95FV100D-103

− 40

+ 5

+ 85

+ 35

°C

Operating temperature

T^A

⎯

*1 : The values vary with the operating frequency, machine clock or analog guarantee range.

*2 : The value is 2.9 V when the low voltage detection reset is used.

*3 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of V^CC

pin must have a capacitor value higher than C^S. For connection of smoothing capacitor C^S, refer to the diagram

below.

• C pin connection diagram

C

CS

36

MB95120MB Series

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

37

MB95120MB Series

3. DC Characteristics

Sym-

(V^CC= AV^CC= 5.0 V 10%, AV^SS= V^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Parameter

Pin name

Conditions

Unit

Remarks

bol

Min

Typ

Max

⎯

Output pin other

than P00 to P07

V^OH1

I^OH= − 4.0 mA V^cc− 0.5

I^OH= − 8.0 mA V^cc− 0.5

⎯

V

“H” level output

voltage

V^OH2P00 to P07

⎯

Output pin other

V^OL1thanP00toP07, I^OL= 4.0 mA

⎯

0.4

V

“L” level output

voltage

RST

V^OL2P00 to P07

I^OL= 12 mA

Open-drain

output

application

voltage

V^D1P50, P51

⎯

V^SS− 0.3

⎯

V^SS+ 5.5

V

Input leakage

current (Hi-Z

output leakage

current)

Port other than

P50, P51

When the pull-up

prohibition setting

I^LI

0.0 V < V^I< V^CC

− 5

⎯

+ 5

µA

Open-drain

output leakage I^LIODP72, P73,

current

P50, P51,

0.0 V < V^I<

V^SS+ 5.5 V

⎯

5

P80 to P83

P10 to P14,

P20 to P24,

P30 to P37,

P40 to P43,

P52, P53,

When the pull-up

permission setting

Pull-up resistor R^PULL

V^I= 0.0 V

25

50

5

100

15

kΩ

P70, P71

Other than

AV^CC, AV^SS,

AVR, V^CC, V^SS

Input

C^IN

f = 1 MHz

⎯

pF

capacitance

At other than Flash

mA memory writing and

erasing

F^CH= 20 MHz

F^MP= 10 MHz

Main clock

mode

⎯

9.5

12.5

35.0

20.0

42.5

At Flash memory

mA

30.0

15.2

35.7

V^CC

(divided by 2)

writing and erasing

Power supply

current*

I^CC(External clock

operation)

At other than Flash

mA memory writing and

erasing

F^CH= 32 MHz

F^MP= 16 MHz

Main clock

mode

At Flash memory

mA

(divided by 2)

writing and erasing

(Continued)

38

MB95120MB Series

(V^CC= AV^CC= 5.0 V 10%, AV^SS= V^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Remarks

Min

Typ

Max

F^CH= 20 MHz

F^MP= 10 MHz

Main Sleep mode

(divided by 2)

⎯

4.5

7.5

mA

I^CCS

F^CH= 32 MHz

F^MP= 16 MHz

Main Sleep mode

(divided by 2)

⎯

7.2

45

12.0

100

81

mA

µA

F^CL= 32 kHz

F^MPL= 16 kHz

sub clock mode

(divided by 2)

I^CCL

I^CCLS

I^CCT

F^CL= 32 kHz

F^MPL= 16 kHz

Sub sleep mode

(divided by 2)

10

µA

F^CL= 32 kHz

Watch mode

Main stop mode

T^A= + 25 °C

4.6

9.3

14.9

27.0

12.5

20.0

µA

V^CC

F^CH= 4 MHz

Power supply

current*

(External clock

operation)

F^MP= 10 MHz

Main PLL mode

(multiplied by 2.5)

mA

I^CCMPLL

F^CH= 6.4 MHz

F^MP= 16 MHz

Main PLL mode

(multiplied by 2.5)

F^CL= 32 kHz

F^MPL= 128 kHz

Sub PLL mode

(multiplied by 4) ,

T^A= + 25 °C

I^CCSPLL

⎯

160

400

µA

F^CH= 10 MHz

Timebase timer

mode

0.40

1.10

mA

T^A= + 25 °C

I^CTS

F^CH= 16 MHz

Timebase timer

mode

⎯

0.64

3.5

1.76

20

mA

T^A= + 25 °C

Sub stop mode

T^A= + 25 °C

I^CCH

µA

(Continued)

39

MB95120MB Series

(Continued)

(V^CC= AV^CC= 5.0 V, AV^SS= V^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit Remarks

Min

Typ

Max

F^CH= 16 MHz

At operating of A/D

conversion

I^A

⎯

2.4

4.7

mA

Power supply

current*

AV^CC

F^CH= 16 MHz

At stopping of A/D

conversion

I^AH

⎯

1

5

µA

T^A= + 25 °C

LCD internal

division

resistance

R^LCD

⎯

Between V3 and V^SS

⎯

300

⎯

5

kΩ

µA

COM0 to

COM3 output

impedance

R^VCOM

COM0 to COM3 V1 to V3 = 3.6 V

SEG00 to

SEG39 output R^VSEGSEG00 to SEG39

impedance

⎯

7

V0 to V3,

LCD leak

I^LCDLCOM0 to COM3

current

− 1

⎯

+ 1

SEG00 to SEG39

* : • The power-supply current is determined by the external clock. When both low voltage detection option is

selected, the power-supply current will be a value of adding current consumption of the low voltage detection

circuit (I^LVD) to the specified value.

• Refer to “4. AC characteristics (1) Clock Timing” for F^CHand F^CL.

• Refer to “4. AC characteristics (2) Source Clock/Machine Clock” for F^MPand F^MPL.

40

MB95120MB Series

4. AC Characteristics

(1) Clock Timing

(V^CC= 2.5 V to 5.5 V, AV^SS= V^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym-

bol

Condi-

tions

Parameter

Pin name

Unit

Remarks

Min

Typ

Max

When using main

oscillation circuit

1.00

⎯

16.25 MHz

1.00

3.00

⎯

32.50 MHz When using external clock

16.25 MHz Main PLL multiplied by 1

8.13 MHz Main PLL multiplied by 2

6.50 MHz Main PLL multiplied by 2.5

When using sub

F^CH

X0, X1

Clock frequency

⎯

32.768

⎯

kHz

ns

oscillation circuit

F^CL

X0A, X1A

X0, X1

When using sub PLL

V^CC= 2.3 V to 3.6 V

⎯

When using main oscilla-

tion circuit

61.5

30.8

⎯

1000

⎯

t^HCYL

Clock cycle time

ns When using external clock

When using sub oscilla-

tion circuit

t^LCYLX0A, X1A

30.5

µs

t^WH1

t^WL1

X0

61.5

⎯

15.2

⎯

5

ns

When using external clock

Duty ratio is about 30% to

70%.

Input clock pulse width

t^WH2

X0A

t^WL2

µs

Input clock rise time and

fall time

t^CR

X0, X0A

t^CF

⎯

ns When using external clock

41

MB95120MB Series

tHCYL

tWH1

tWL1

tCR

tCF

0.8 VCC 0.8 VCC

X0

0.2 VCC

• Figure of Main Clock Input Port External Connection

When using a crystal or

ceramic oscillator

When using external clock

Microcontroller

X0

X1

X0

X1

Open

F^CH

C2

F^CH

C1

tLCYL

tWH2

tWL2

tCR

tCF

0.8 VCC 0.8 VCC

X0A

0.2 VCC

• Figure of Sub clock Input Port External Connection

When using a crystal or

ceramic oscillator

When using external clock

Microcontroller

X0A

X1A

X0A

X1A

Open

F^CL

C2

F^CL

C1

42

MB95120MB Series

(2) Source Clock/Machine Clock

(V^CC= 5.0 V 10%, AV^SS= V^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym-

bol name

Parameter

Unit

Remarks

Min

Typ

Max

When using main clock

Min : F^CH= 16.25 MHz,

PLL multiplied by 1

61.5

⎯

2000

ns

Source clock cycle time*¹

(Clock before setting

division)

Max : F^CH= 1 MHz, divided by 2

t^SCLK

⎯

When using sub clock

Min : F^CL= 32 kHz,

PLL multiplied by 4

7.6

⎯

61.0

µs

Max : F^CL= 32 kHz, divided by 2

F^SP

⎯

0.50

⎯

16.25 MHz When using main clock

131.072 kHz When using sub clock

When using main clock

Source clock frequency

F^SPL

16.384

61.5

7.6

⎯

32000

ns Min : F^SP= 16.25 MHz, no division

Machine clock cycle time*²

(Minimum instruction

execution time)

Max : F^SP= 0.5 MHz, divided by 16

t^MCLK

⎯

When using sub clock

µs Min : F^SPL= 131 kHz, no division

Max : F^SPL= 16 kHz, divided by 16

976.5

F^MP

0.031

1.024

⎯

16.250 MHz When using main clock

131.072 kHz When using sub clock

Machine clock frequency

⎯

F^MPL

*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This

source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes

the machine clock. Further, the source clock can be selected as follows.

• Main clock divided by 2

• PLL multiplication of main clock (select from 1, 2, 2.5 multiplication)

• Sub clock divided by 2

• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)

*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.

• Source clock (no division)

• Source clock divided by 4

• Source clock divided by 8

• Source clock divided by 16

• Outline of clock generation block

FCH

Divided by 2

(main oscillation)

Main PLL

× 1

× 2

× 2.5

Division

circuit

× 1

SCLK

(source clock)

MCLK

(machine clock)

× 1/4

× 1/8

FCL

Divided by 2

× 1/16

(sub oscillation)

Clock mode select bit

(SYCC: SCS1, SCS0)

Sub PLL

× 2

× 3

× 4

43

MB95120MB Series

• Operating voltage - Operating frequency (T^A= − 40 °C to + 85 °C)

• MB95F124MB/F124NB/MB95F126MB/F126NB/MB95F128MB/F128NB

Main clock mode and main PLL mode

operation guarantee range

Sub PLL, sub clock mode and watch

mode operation guarantee range

5.5

3.5

2.45

0.5 MHz 3 MHz

10 MHz

16.25 MHz

16.384 kHz

32 kHz

131.072 kHz

PLL operation guarantee range

Main clock operation guarantee range

Source clock frequency (F^SP)

PLL operation guarantee range

Source clock frequency (F^SPL)

• Operating voltage - Operating frequency (T^A= + 5 °C to + 35 °C)

• MB95FV100D-103

Sub PLL, sub clock mode and

watch mode operation guarantee range

Main clock mode and main PLL mode

operation guarantee range

5.5

3.5

2.7

0.5MHz 3 MHz

10 MHz

16.25 MHz

16.384 kHz

32 kHz

131.072 kHz

PLL operation guarantee range

Main clock operation guarantee range

Source clock frequency (F^SP)

Source clock frequency (F^SPL)

44

MB95120MB Series

• Main PLL operation frequency

10 MHz

9 MHz

× 2.5

8 MHz

7.5 MHz

× 2

7 MHz

× 1

6 MHz

5 MHz

4 MHz

3 MHz

3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz 10 MHz

Main clock frequency (F^MP)

45

MB95120MB Series

(3) External Reset

(V^CC= 5.0 V 10%, AV^SS= V^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Parameter

Symbol

Unit

Remarks

Min

Max

2 t^MCLK*¹

⎯

ns At normal operating

RST “L” level pulse

width

Oscillation time of oscillator*²

At stop mode, sub clock mode,

sub sleep mode, and watch mode

t^RSTL

⎯

+ 100

µs

100

At timebase timer mode

*1 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

*2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the

oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between

hundreds of µs and several ms. In the external clock, the oscillation time is 0 ms.

• At normal operating

tRSTL

RST

0.2 VCC

• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on

tRSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal

operating

clock

100 µs

Oscillation stabilization wait time

Oscillation time

of oscillator

Execute instruction

Internal reset

46

MB95120MB Series

(4) Power-on Reset

Parameter

(AV^SS= V^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Symbol

Conditions

Unit

Remarks

Min

Max

Power supply rising time

Power supply cutoff time

t^R

⎯

50

ms

Waiting time until

power-on

t^OFF

1

⎯

t

R

tOFF

2.5 V

0.2 V

VCC

Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power

supply voltages during operation, set the slope of rising within 30 mV/ms as shown below.

VCC

Limiting the slope of rising within

30 mV/ms is recommended.

2.3 V

Hold Condition in stop mode

VSS

47

MB95120MB Series

(5) Peripheral Input Timing

(V^CC= 5.0 V 10%, AV^SS= V^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Parameter

Symbol

Pin name

Unit Remarks

Min

Max

Peripheral input “H” pulse

width

INT00 to INT07,

INT10 to INT13,

EC0, EC1, TI0, TRG0/ADTG,

TRG1

t^ILIH

2 t^MCLK*

⎯

ns

Peripheral input “L” pulse

width

t^IHIL

2 t^MCLK*

⎯

* : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

tILIH

tIHIL

INT00 to INT07,

0.8 VCC 0.8 VCC

INT10 to INT13, EC0, EC1,

TI0, TRG0/ADTG, TRG1

0.2 VCC

48

MB95120MB Series

(6) UART/SIO, Serial I/O Timing

(V^CC= 5.0 V 10%, AV^SS= V^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Remarks

Parameter

Symbol Pin name

Conditions

Unit

Min

Max

⎯

Serial clock cycle time

UCK ↓ → UO time

t^SCYC

t^SLOV

t^IVSH

t^SHIX

t^SHSL

t^SLSH

t^SLOV

t^IVSH

t^SHIX

UCK0

UCK0, UO0

UCK0, UI0

UCK0

4 t^MCLK*

− 190

ns

Internal clock

operationoutputpin:

C^L= 80 pF + 1TTL.

+190

⎯

Valid UI → UCK ↑

2 t^MCLK*

4 t^MCLK*

0

UCK ↑ → valid UI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

UCK ↓ → UO time

⎯

UCK0

⎯

External clock

UCK0, UO0 operationoutputpin:

190

⎯

C^L= 80 pF + 1TTL.

Valid UI → UCK ↑

UCK0, UI0

2 t^MCLK*

UCK ↑ → valid UI hold time

UCK0, UI0

⎯

* : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

• Internal shift clock mode

tSCYC

2.4 V

UCK0

0.8 V

tSLOV

UO0

UI0

2.4 V

0.8 V

tIVSH

tSHIX

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

• External shift clock mode

UCK0

tSLSH

tSHSL

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tSLOV

UO0

UI0

2.4 V

0.8 V

tIVSH

tSHIX

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

49

MB95120MB Series

(7) LIN-UART Timing

Sampling at the rising edge of sampling clock*¹and prohibited serial clock delay*²

(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)

(V^CC= 5.0 V 10%, AV^SS= V^SS= 0.0 V, T^A= −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

5 t^MCLK*³

−95

Max

Serial clock cycle time

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SCYC

SCK

⎯

ns

Internal clock

operation output pin :

C^L= 80 pF + 1 TTL.

t^SLOVISCK, SOT

+95

t^IVSHI

t^SHIXI

t^SLSH

t^SHSL

SCK, SIN

SCK

t^MCLK*³+ 190

⎯

SCK ↑ → valid SIN hold time

Serial clock “L” pulse width

Serial clock “H” pulse width

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

0

3 t^MCLK*³− t^R

t^MCLK*³+ 95

⎯

SCK

⎯

t^SLOVESCK, SOT

2 t^MCLK*³+ 95

External clock

t^IVSHESCK, SIN operationoutputpin:

190

⎯

10

C^L= 80 pF + 1 TTL.

SCK ↑ → valid SIN hold time

SCK fall time

t^SHIXESCK, SIN

t^MCLK*³+ 95

⎯

t^F

SCK

SCK rise time

t^R

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

50

MB95120MB Series

• Internal shift clock mode

SCK

t

SCYC

2.4 V

0.8 V

t

SLOVI

2.4 V

0.8 V

SOT

SIN

t

IVSHI

tSHIXI

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

• External shift clock mode

SCK

t

SLSH

t

SHSL

0.8 VCC

0.2 VCC

SLOVE

0.2 VCC

t

R

t

F

t

2.4 V

0.8 V

SOT

SIN

t

SHIXE

t

IVSHE

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

51

MB95120MB Series

Sampling at the falling edge of sampling clock*¹and prohibited serial clock delay*²

(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)

(V^CC= 5.0 V 10%, AV^SS= V^SS= 0.0 V, T^A= −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

5 t^MCLK*³

−95

Max

Serial clock cycle time

SCK ↑ → SOT delay time

Valid SIN → SCK ↓

t^SCYC

t^SHOVI

t^IVSLI

t^SLIXI

t^SHSL

t^SLSH

SCK

SCK, SOT

SCK, SIN

SCK

⎯

ns

Internal clock

operation output pin :

C^L= 80 pF + 1 TTL.

+95

t^MCLK*³+ 190

⎯

SCK ↓ → valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK ↑ → SOT delay time

Valid SIN → SCK ↓

0

3 t^MCLK*³− t^R

t^MCLK*³+ 95

⎯

SCK

⎯

t^SHOVESCK, SOT

2 t^MCLK*³+ 95

External clock

t^IVSLE

t^SLIXE

t^F

SCK, SIN operation output pin :

190

⎯

10

C^L= 80 pF + 1 TTL.

SCK ↓ → valid SIN hold time

SCK fall time

SCK, SIN

t^MCLK*³+ 95

⎯

SCK

SCK rise time

t^R

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

52

MB95120MB Series

• Internal shift clock mode

SCK

t

SCYC

2.4 V

0.8 V

t

SHOVI

2.4 V

0.8 V

SOT

SIN

t

IVSLI

t

SLIXI

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

• External shift clock mode

SCK

t

SHSL

t

SLSH

0.8 VCC

0.2 VCC

t

F

t

R

t

SHOVE

2.4 V

0.8 V

SOT

SIN

t

SLIXE

t

IVSLE

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

53

MB95120MB Series

Sampling at the rising edge of sampling clock*¹and enabled serial clock delay*²

(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)

(V^CC= 5.0 V 10%, AV^SS= V^SS= 0.0 V, T^A= −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

5 t^MCLK*³

−95

Max

⎯

Serial clock cycle time

SCK ↑ → SOT delay time

Valid SIN → SCK ↓

tSCYC

t^SHOVI

t^IVSLI

SCK

ns

SCK, SOT

+95

⎯

Internal clock

SCK, SIN operation output pin : t^MCLK*³+ 190

C^L= 80 pF + 1 TTL.

SCK ↓ → valid SIN hold time

SOT → SCK ↓ delay time

t^SLIXI

SCK, SIN

SCK, SOT

0

⎯

4 t^MCLK*³

t^SOVLI

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

t

SCYC

2.4 V

SCK

0.8 V

t

SHOVI

t

SOVLI

2.4 V

0.8 V

2.4 V

0.8 V

SOT

SIN

tSLIXI

tIVSLI

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

54

MB95120MB Series

Sampling at the falling edge of sampling clock*¹and enabled serial clock delay*²

(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)

(V^CC= 5.0 V 10%, AV^SS= V^SS= 0.0 V, T^A= −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

5 t^MCLK*³

−95

Max

⎯

Serial clock cycle time

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

tSCYC

t^SLOVI

t^IVSHI

t^SHIXI

t^SOVHI

SCK

ns

SCK, SOT

+95

⎯

Internal clock

SCK, SIN operating output pin : t^MCLK*³+ 190

C^L= 80 pF + 1 TTL.

SCK ↑ → valid SIN hold time

SOT → SCK ↑ delay time

SCK, SIN

SCK, SOT

0

⎯

4 t^MCLK*³

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

t

SCYC

2.4 V

SCK

0.8 V

t

SOVHI

t

SLOVI

2.4 V

0.8 V

2.4 V

0.8 V

SOT

SIN

t

IVSHI

tSHIXI

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

55

MB95120MB Series

(8) I²C Timing

(V^CC= 5.0 V 10%, AV^SS= V^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym-

name

Standard-

mode

Re-

marks

Parameter

bol

Conditions

Fast-mode Unit

Min

Max

Min

Max

SCL clock frequency

f^SCL

SCL0

0

100

0

400 kHz

(Repeat) Start condition hold time

SDA ↓ → SCL ↓

SCL0

SDA0

t^HD;STA

4.0

⎯

0.6

⎯

µs

SCL clock “L” width

SCL clock “H” width

t^LOW

t^HIGH

SCL0

4.7

4.0

⎯

1.3

0.6

⎯

µs

(Repeat) Start condition setup time

SCL ↑ → SDA ↓

SCL0

SDA0

t^SU;STA

4.7

0

⎯

3.45*²

⎯

0.6

0

⎯

µs

R = 1.7 kΩ,

C = 50 pF*¹

SCL0

SDA0

Data hold time SCL ↓ → SDA ↓ ↑ t^HD;DAT

Data setup time SDA ↓ ↑ → SCL ↑ t^SU;DAT

0.9*³µs

SCL0

SDA0

0.25

4.0

4.7

0.1

0.6

1.3

⎯

µs

Stop condition setup time SCL ↑ →

SDA ↑

SCL0

SDA0

t^SU;STO

⎯

Bus free time between stop

t^BUF

SCL0

SDA0

⎯

condition and start condition

*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum t^HD;DAThave only to be met if the device dose not stretch the “L” width (t^LOW) of the SCL signal.

*3 : A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement

t^SU;DAT≥ 250 ns must then be met.

tWAKEUP

SDA0

SCL0

tHD;STA

t

SU;DAT

t

HIGH

t

BUF

t

LOW

tSU;STO

t

HD;STA

tHD;DAT

t

SU;STA

56

MB95120MB Series

(V^CC= 5.0 V 10%, AV^SS= V^SS= 0.0 V, T^A= −40 °C to + 85 °C)

Value*²

Sym- Pin

bol name

Condi-

tions

Parameter

Unit

Remarks

Min

Max

SCL clock

“L” width

(2 + nm / 2) t^MCLK− 20

t^LOW

t^HIGH

SCL0

⎯

ns Master mode

SCL clock

“H” width

(nm / 2) t^MCLK− 20

(nm / 2 ) t^MCLK+ 20

ns Master mode

Master mode

Maximum value is

applied when m,

ns n = 1, 8.

Start

condition

hold time

SCL0

SDA0

(−1 + nm / 2) t^MCLK− 20

(−1 + nm) t^MCLK+ 20

t^HD;STA

Otherwise, the

minimum value is

applied.

Stop condition

setup time

SCL0

SDA0

t^SU;STO

(1 + nm / 2) t^MCLK− 20 (1 + nm / 2) t^MCLK+ 20 ns Master mode

Start condition

setup time

SCL0

SDA0

t^SU;STA

Bus free time

between stop

condition and

start condition

SCL0

SDA0

t^BUF

(2 nm + 4) t^MCLK− 20

⎯

ns

SCL0

SDA0

Data hold time t^HD;DAT

3 t^MCLK− 20

ns Master mode

Master mode

R = 1.7 kΩ,

C = 50 pF*¹

When assuming

that “L” of SCL is

not extended, the

minimum value is

Data setup

t^SU;DAT

SCL0

SDA0

(−2 + nm / 2) t

^MCLK− 20 (−1 + nm / 2) t^MCLK+ 20 ns applied to first bit

time

of continuous

data.

Otherwise,

the maximum

value is applied.

Minimum value is

appliedtointerrupt

at 9th SCL↓.

Maximum value is

appliedtointerrupt

at 8th SCL↓.

Setup time

between

clearing

interrupt and

SCL rising

t^SU;INTSCL0

(nm / 2) t^MCLK− 20

(1 + nm / 2) t^MCLK+ 20 ns

SCL clock “L”

width

4 t^MCLK− 20

t^LOW

t^HIGH

SCL0

⎯

ns At reception

SCL clock “H”

width

Undetected when

ns 1 t^MCLKis used at

reception

Start condition

detection

SCL0

SDA0

2 t^MCLK− 20

t^HD;STA

⎯

(Continued)

57

MB95120MB Series

(Continued)

(V^CC= 5.0 V 10%, AV^SS= V^SS= 0.0 V, T^A= −40 °C to + 85 °C)

Value*²

Sym- Pin

bol name

Condi-

tions

Parameter

Unit

Remarks

Min

Max

Undetected when 1

ns t^MCLKis used at

reception

Stop condition

detection

SCL0

t^SU;STO

2 t^MCLK− 20

⎯

SDA0

Undetected when 1

ns t^MCLKis used at

reception

Restart condition

detection condition

SCL0

t^SU;STA

2 t^MCLK− 20

⎯

SDA0

SCL0

t^BUF

Bus free time

⎯

ns At reception

SDA0

SCL0

t^HD;DAT

At slave transmission

mode

Data hold time

Data setup time

Data hold time

Data setup time

2 t^MCLK− 20

ns

SDA0

R = 1.7 kΩ,

C = 50 pF*¹

SCL0

t^SU;DAT

At slave transmission

mode

t^LOW− 3 t^MCLK− 20

ns

SDA0

SCL0

t^HD;DAT

0

ns At reception

SDA0

SCL0

t^SU;DAT

t^MCLK− 20

SDA0

Oscillation

stabilization

wait time +

2 t^MCLK− 20

SDA↓→SCL↑

(at wakeup function)

t^WAKE-SCL0

⎯

ns

UP

SDA0

*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : • Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

• m is CS4 bit and CS3 bit (bit 4 and bit 3) of I²C clock control register (ICCR) .

• n is CS2 bit to CS0 bit (bit 2 to bit 0) of I²C clock control register (ICCR) .

• Actual timing of I²C is determined by m and n values set by the machine clock (t^MCLK) and CS4 to CS0 of

ICCR0 register.

• Standard-mode :

m and n can be set at the range : 0.9 MHz < t^MCLK(machine clock) < 10 MHz.

Setting of m and n determines the machine clock that can be used below.

(m, n) = (1, 8)

: 0.9 MHz < t^MCLK≤ 1 MHz

(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < t^MCLK≤ 2 MHz

(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < t^MCLK≤ 4 MHz

(m, n) = (1, 98)

• Fast-mode :

: 0.9 MHz < t^MCLK≤ 10 MHz

m and n can be set at the range : 3.3 MHz < t^MCLK(machine clock) < 10 MHz.

Setting of m and n determines the machine clock that can be used below.

(m, n) = (1, 8)

(m, n) = (1, 22) , (5, 4)

(m, n) = (6, 4)

: 3.3 MHz < t^MCLK≤ 4 MHz

: 3.3 MHz < t^MCLK≤ 8 MHz

: 3.3 MHz < t^MCLK≤ 10 MHz

58

MB95120MB Series

(9) Low Voltage Detection

Parameter

(AVss = Vss = 0.0 V, T^A= −40 °C to + 85 °C)

Value

Typ

2.70

2.60

100

⎯

Symbol

Unit

Remarks

Min

2.55

2.45

70

Max

2.85

2.75

⎯

Release voltage

V^DL+

V^DL-

V^HYS

V^off

V

At power-supply rise

Detection voltage

At power-supply fall

Hysteresis width

mV

V

Power-supply start voltage

Power-supply end voltage

⎯

2.3

V^on

4.9

⎯

V

Slope of power supply that reset release

signal generates

0.3

⎯

3000

⎯

µs

Power-supply voltage

change time

(at power supply rise)

t^r

Slope of power supply that reset release

signal generates within rating (V^DL+)

Slope of power supply that reset

detection signal generates

300

Power-supply voltage

change time

(at power supply fall)

t^f

Slope of power supply that reset

⎯

300

⎯

µs detection signal generates within rating

(V^DL-)

Reset release delay time

Reset detection delay time

t^d1

t^d2

⎯

400

30

µs

Current consumption of low voltage

detection circuit only

Current consumption

I^LVD

⎯

38

50

µA

VCC

Von

Voff

time

tr

tf

VCC

VDL+

VDL-

VHYS

Internal reset signal

td1

td2

59

MB95120MB Series

5. A/D Converter

(1) A/D Converter Electrical Characteristics

(AVcc = Vcc = 4.0 V to 5.5 V, AVss = Vss = 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Typ

⎯

Parameter

Resolution

Symbol

Unit

Remarks

Min

⎯

Max

10

bit

LSB

V

Total error

− 3.0

− 2.5

− 1.9

⎯

+ 3.0

+ 2.5

+ 1.9

⎯

Linearity error

⎯

Differential linear error

Zero transition voltage

⎯

V^OT

AVss − 1.5 LSB AVss + 0.5 LSB AVss + 2.5 LSB

Full-scale transition

voltage

V^FST

AVR − 3.5 LSB AVR − 1.5 LSB AVR + 0.5 LSB

V

4.5 V ≤ AVcc ≤ 5.5

0.9

1.8

⎯

16500

µs

V

Compare time

Sampling time

⎯

4.0 V ≤ AVcc < 4.5

V

4.5 V ≤ AVcc ≤ 5.5

V,

At external imped-

ance < 5.4 kΩ

0.6

1.2

⎯

∞

µs

4.0 V ≤ AVcc < 4.5

V,

At external imped-

ance < 2.4 kΩ

Analog input current

Analog input voltage

Reference voltage

I^AIN

V^AIN

⎯

−0.3

AVss

⎯

+0.3

AVR

AVcc

µA

V

AVss + 4.0

V

AVR pin

AVR pin,

I^R

⎯

600

900

5

µA During A/D

Reference voltage

supply current

operation

AVR pin,

µA

I^RH

⎯

At stop mode

60

MB95120MB Series

(2) Notes on Using A/D Converter

• About the external impedance of analog input and its sampling time

A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/

D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship

between the external impedance and minimum sampling time and either adjust the register value and operating

frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,

if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• Analog input equivalent circuit

R

Analog input

Comparator

C

During sampling : ON

R

C

4.5 V ≤ AVcc ≤ 5.5 V 2.0 kΩ (Max)

4.0 V ≤ AVcc < 4.5 V 8.2 kΩ (Max)

16 pF (Max)

Note : The values are reference values.

• The relationship between external impedance and minimum sampling time

(External impedance = 0 kΩ to 20 kΩ)

(External impedance = 0 kΩ to 100 kΩ)

100

20

18

90

AVCC ≥ 4.5 V

80

16

AVCC ≥ 4.5 V

70

14

60

12

AV^CC≥ 4.0 V

50

10

40

30

20

10

0

8

6

4

2

0

8

14

0

2

4

6

10

12

0

1

2

3

4

Minimum sampling time [µs]

• About errors

As |AV^CC− AV^SS| becomes smaller, values of relative errors grow larger.

61

MB95120MB Series

(3) Definition of A/D Converter Terms

• Resolution

The level of analog variation that can be distinguished by the A/D converter.

When the number of bits is 10, analog voltage can be divided into 2¹⁰= 1024.

• Linearity error (unit : LSB)

The deviation between the value along a straight line connecting the zero transition point

(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point

(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.

• Differential linear error (Unit : LSB)

Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

• Total error (unit: LSB)

Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,

linearity error, quantum error, and noise.

Ideal I/O characteristics

Total error

V

FST

3FF

H

3FF

H

3FE

H

3FE

H

Actual conversion

characteristic

1.5 LSB

3FD

H

3FD

H

{1 LSB × (N − 1) + 0.5 LSB}

004

003

002

001

H

004

003

002

001

H

V

NT

VOT

Actual conversion

characteristic

1 LSB

0.5 LSB

Ideal characteristics

AV^SS

AVSS

AVR

Analog input

Total error of

digital output N

AVR − AV^SS

1024

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

=

1 LSB =

(V)

[LSB]

1 LSB

N

: A/D converter digital output value

V^NT: A voltage at which digital output transits from (N - 1) to N.

(Continued)

62

MB95120MB Series

(Continued)

Full-scale transition error

Zero transition error

Ideal

004

H

characteristics

Actual conversion

characteristic

3FF

3FE

3FD

H

Actual conversion

characteristic

003

002

001

Ideal

characteristics

V^FST

(measurement

value)

Actual conversion

characteristic

Actual conversion

characteristic

3FC

H

V^OT(measurement value)

AVSS

AVR

AVSS

AVR

Analog input

Linearity error

Differential linear error

Actual conversion

characteristic

Ideal characteristics

3FF

3FE

3FD

H

N+1

N

H

Actual conversion

characteristic

{1 LSB × N + VOT

}

H

V

(N+1)T

V^FST

(measurement

value)

V

NT

004

003

002

001

H

N-1

N-2

V

NT

Actual conversion

characteristic

Actual conversion

characteristic

Ideal characteristics

V^OT(measurement value)

AVSS

AVR

AVSS

AVR

Analog input

Linear error in

digital output N

V^NT− {1 LSB × N + V^OT}

V ^(N+ ^{1) T}− V^NT

Differential linear error

in digital output N

=

− 1

1 LSB

N

: A/D Converter digital output value

V^NT: A voltage at which digital output transits from (N − 1) to N.

V^OT(Ideal value) = AV^SS+ 0.5 LSB [V]

V^FST(Ideal value) = AVR − 1.5 LSB [V]

63

MB95120MB Series

6. Flash Memory Program/Erase Characteristics

Value

Parameter

Unit

Remarks

Min

Typ

Max

Sector erase time

(4 Kbytes sector)

⎯

0.2*¹

0.5*²

s

Excludes 00^Hprogramming prior erasure.

Sector erase time

(16 Kbytes sector)

⎯

0.5*¹

7.5*²

Byte programming time

Program/erase cycle

⎯

32

3600

µs Excludes system-level overhead.

cycle

10000

⎯

Power supply voltage at

program/erase

4.5

⎯

5.5

V

Flash memory data retention

time

20*³

⎯

year Average T^A= +85 °C

*1 : T^A= + 25 °C, V^CC= 5.0 V, 10000 cycles

*2 : T^A= + 85 °C, V^CC= 4.5 V, 10000 cycles

*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at +85 °C) .

64

MB95120MB Series

■ MASK OPTION

MB95F124MB/F124NB/

MB95F126MB/F126NB/

MB95F128MB/F128NB

Part number

MB95FV100D-103

Setting disabled

No.

Specifying procedure

Clock mode select

• Single-system clock mode

• Dual-system clock mode

Setting disabled

Changing by the switch on

MCU board

1

2

3

Dual-system clock mode

Low voltage detection reset*

• With low voltage detection reset

• Without low voltage detection reset

Changing by the switch on

MCU board

Specified by part number

Fixed to oscillation

stabilization wait time of

(2¹⁴−2) /F^CH

Oscillation stabilization

wait time

Fixed to oscillation stabilization wait

time of (2¹⁴−2) /F^CH

* : Refer to table below about clock mode select, low voltage detection reset, and reset output.

Part number

MB95F124MB

Clock mode select

Low voltage detection reset

No

Yes

No

MB95F124NB

MB95F126MB

MB95F126NB

MB95F128MB

MB95F128NB

Dual-system

Yes

No

Yes

No

Single-system

Dual-system

Yes

No

MB95FV100D-103

Yes

65

MB95120MB Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB95F124MBPFV/

MB95F124NBPFV/

MB95F126MBPFV/

MB95F126NBPFV/

MB95F128MBPFV/

MB95F128NBPFV

100-pin plastic LQFP

(FPT-100P-M05)

MB95F124MBPF/

MB95F124NBPF/

MB95F126MBPF/

MB95F126NBPF/

MB95F128MBPF/

MB95F128NBPF

100-pin plastic QFP

(FPT-100P-M06)

MCU board

224-pin plastic PFBGA

(BGA-224P-M08)

MB2146-303A

(MB95FV100D-103PBT)

(

)

66

MB95120MB Series

■ PACKAGE DIMENSIONS

100-pin plastic LQFP

Lead pitch

0.50 mm

14.0 × 14.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.70 mm MAX

0.65g

Code

(Reference)

(FPT-100P-M05)

P-LFQFP100-14×14-0.50

100-pin plastic LQFP

(FPT-100P-M05)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

16.00 0.20(.630 .008)SQ

*

14.00 0.10(.551 .004)SQ

75

51

76

50

0.08(.003)

Details of "A" part

1.50 ⁺–0⁰.^.1²0⁰.059 –⁺.^.0⁰0⁰4⁸

(Mounting height)

INDEX

0.10 0.10

(.004 .004)

(Stand off)

100

26

0˚~8˚

"A"

0.50 0.20

(.020 .008)

0.25(.010)

1

25

0.60 0.15

(.024 .006)

0.50(.020)

0.20 0.05

(.008 .002)

0.145 0.055

(.0057 .0022)

M

0.08(.003)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2003 FUJITSU LIMITED F100007S-c-4-6

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

(Continued)

67

MB95120MB Series

(Continued)

100-pin plastic QFP

Lead pitch

0.65 mm

14.00 × 20.00 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Plastic mold

3.35 mm MAX

P-QFP100-14×20-0.65

Code

(Reference)

(FPT-100P-M06)

100-pin plastic QFP

(FPT-100P-M06)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

23.90 0.40(.941 .016)

*

20.00 0.20(.787 .008)

80

51

81

50

0.10(.004)

17.90 0.40

(.705 .016)

*

14.00 0.20

(.551 .008)

INDEX

Details of "A" part

100

31

0.25(.010)

3.00 ⁺^–0⁰^.^.²³⁰⁵

.118 ⁺^–.^.⁰⁰⁰¹⁸⁴

(Mounting height)

0~8

˚

1

30

0.65(.026)

0.32 0.05

(.013 .002)

0.17 0.06

(.007 .002)

M

0.13(.005)

0.25 0.20

(.010 .008)

(Stand off)

0.80 0.20

(.031 .008)

"A"

0.88 0.15

(.035 .006)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2002 FUJITSU LIMITED F100008S-c-5-5

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

68

MB95120MB Series

The information for microcontroller supports is shown in the following homepage.

http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

Edited

Business Promotion Dept.

F0608


型号：	MB95F128NBPFV
厂家：	SPANSION
描述：	Microcontroller, 8-Bit, FLASH, 16.25MHz, CMOS, PQFP100, 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100 时钟微控制器外围集成电路
文件：	总69页 (文件大小：1001K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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