MB95F134MBSPFV [SPANSION]
Microcontroller, 8-Bit, FLASH, 32.5MHz, CMOS, PDSO30, 5.60 X 9.70 MM, 1.45 MM HEIGHT, 0.65 MM PITCH, PLASTIC, SSOP-30;
| 型号： | MB95F134MBSPFV |
| 厂家： | 
SPANSION |
| 描述： | Microcontroller, 8-Bit, FLASH, 32.5MHz, CMOS, PDSO30, 5.60 X 9.70 MM, 1.45 MM HEIGHT, 0.65 MM PITCH, PLASTIC, SSOP-30 微控制器 光电二极管 |
| 文件： | 总69页 (文件大小：1964K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Spansion® Analog and Microcontroller
Products
The following document contains information on Spansion analog and microcontroller products. Although the
document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion
will continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal document improvements and are noted in the document revision
summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a
revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “MB”. To order these products, please use
only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory, analog, and
microcontroller products and solutions.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12621-3E
8-bit Microcontrollers
CMOS
F2MC-8FX MB95130MB Series
MB95136MB/F133MBS/F133NBS/F133JBS/F134MBS/F134NBS/F134JBS/
MB95F136MBS/F136NBS/F136JBS/F133MBW/F133NBW/F133JBW/F134MBW/
MB95F134NBW/F134JBW/F136MBW/F136NBW/F136JBW/FV100D-103
■ DESCRIPTION
The MB95130MB series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product)
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2007-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.7
MB95130MB Series
(Continued)
• Timer
• 8/16-bit compound timer × 1 channel
• 8/16-bit PPG × 1 channel
• 16-bit PPG × 1 channel
• Time-base timer × 1 channel
• Watch prescaler (for dual clock product) × 1 channel
• LIN-UART × 1 channel
• LIN function, Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
• UART/SIO × 1 channel
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
• External interrupt × 8 channels
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter × 8 channels
• 8-bit or 10-bit resolution can be selected.
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode (for dual clock product)
• Time-base timer mode
• I/O port
• The number of maximum ports
• Single clock product : 19 ports
• Dual clock product : 17 ports
• Configuration
General-purpose I/O ports (COMS) : Single clock product : 19 ports
Dual clock product : 17 ports
• Power-on reset
A power-on reset is generated when the power is switched on.
• Programmable input voltage levels of port
Automotive input level / CMOS input level / hysteresis input level
• Flash memory security function
Protects the content of Flash memory (Flash memory device only)
2
DS07-12621-3E
MB95130MB Series
■ MEMORY LINEUP
Flash memory
RAM
MB95F133MBS/F133NBS/F133JBS
MB95F133MBW/F133NBW/F133JBW
MB95F134MBS/F134NBS/F134JBS
MB95F134MBW/F134NBW/F134JBW
MB95F136MBS/F136NBS/F136JBS
MB95F136MBW/F136NBW/F136JBW
8 Kbytes
256 bytes
16 Kbytes
32 Kbytes
512 bytes
1 Kbyte
DS07-12621-3E
3
MB95130MB Series
■ PRODUCT LINEUP
Part number
MB95
MB95
MB95
MB95
MB95
MB95
F133MBS/
F133NBS/
F134NBS/
F136NBS
F133MBW/
F134MBW/
F136MBW
F133NBW/
F134NBW/
F136NBW
F133JBS/
F134JBS/
F136JBS
F133JBW/
F134JBW/
F136JBW
MB95136MB
F134MBS/
F136MBS
Parameter
MASK ROM
Type
Flash memory product
product
ROM capacity*1
RAM capacity*1
Power-on reset
32 Kbytes (Max)
1 Kbyte (Max)
Yes
Not
Reset output
Yes
No
selectable*2
Selectable
single/dual
clock*3
Clock
system
Single clock
Dual clock
Single clock Dual clock
Low voltage
detection
reset
Yes/No
No
Yes
No
Yes
Clock
supervisor
Yes/No
No
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
Yes
Number of basic instructions
Instruction bit length
Instruction length
CPU functions
Data bit length
Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)
Interrupt processing time
: 0.6 μs (at machine clock frequency 16.25 MHz)
• Single clock product : 19 ports
• Dual clock product : 17 ports
General-
purpose
I/O port
Programmable input voltage levels of port :
Automotive input level / CMOS input level / hysteresis input level
Time-base
timer
Interval time : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
(1 channel)
Reset generated cycle
At main oscillation clock 10 MHz
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
Watchdog
timer
: Min 105 ms
Wild register Capable of replacing 3 bytes of ROM data
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator
UART/SIO
NRZ type transfer format, error detected function
(1 channel)
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
Dedicated reload timer allowing a wide range of communication speeds to be set.
LIN-UART Full duplex double buffer.
(1 channel) Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN functions available as the LIN master or LIN slave.
(Continued)
4
DS07-12621-3E
MB95130MB Series
(Continued)
Part number
MB95
MB95
MB95
MB95
MB95
MB95
F133MBS/
F134MBS/
F136MBS
F133NBS/
F134NBS/
F136NBS
F133MBW/
F134MBW/
F136MBW
F133NBW/
F134NBW/
F136NBW
F133JBS/
F134JBS/
F136JBS
F133JBW/
F134JBW/
F136JBW
MB95136MB
Parameter
8/10-bit
A/D
converter
(8 channels)
8-bit or 10-bit resolution can be selected.
8/16-bit
compound
timer
Each channel of the timer can be used as “8-bit timer x 2 channels” or “16-bit timer x 1 channel”.
Built-in timer function, PWC function, PWM function, capture function and square wave-form output
Count clock: 7 internal clocks and external clock can be selected.
(1 channel)
PWM mode or one-shot mode can be selected.
Counter operating clock: Eight selectable clock sources
Support for external trigger start
16-bit PPG
(1 channel)
8/16-bit PPG Each channel of the PPG can be used as “8-bit PPG x 2 channels” or “16-bit PPG x 1 channel”.
(1 channel) Counter operating clock: Eight selectable clock sources
Watch
counter
(for dual
clock
product)
Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting clock
source 1 second and setting counter value to 60)
(1 channel)
Watch
prescaler
(for dual
clock
Four selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
product)
(1 channel)
External
interrupt
Interrupt by edge detection (rising, falling, or both edges can be selected.)
Can be used to recover from standby modes.
(8 channels)
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Flash memory Data retention time : 20 years
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
(MB95F136MBS/F136NBS/F136JBS/F136MBW/F136NBW/F136JBW)
Standby mode Sleep, stop, watch (for dual clock product), and time-base timer
*1 : For ROM capacity and RAM capacity, refer to “■ MEMORY LINEUP”.
*2 : For details of option, refer to “■ MASK OPTION”.
*3 : Specify clock mode when ordering MASK ROM.
Note: Part number of evaluation product in MB95130MB series is MB95FV100D-103.
When using it, the MCU board (MB2146-303A-E) is required.
DS07-12621-3E
5
MB95130MB Series
■ OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum
value is shown below.
Oscillation stabilization wait time
Remarks
(214-2) /FCH
Approx. 4.10 ms (at main oscillation clock 4 MHz)
■ PACKAGES AND CORRESPONDING PRODUCTS
MB95F133MBS
Part number
MB95F133MBW
MB95F133NBW
MB95F134MBW
MB95F134NBW
MB95F136MBW
MB95F136NBW
MB95F133JBW
MB95F134JBW
MB95F136JBW
MB95F133NBS
MB95F134MBS
MB95F134NBS
MB95136MB
MB95F136MBS
MB95F136NBS
MB95F133JBS
MB95F134JBS
MB95F136JBS
MB95FV100D-103
Package
FPT-28P-M17
FPT-30P-M02
BGA-224P-M08
: Available
: Unavailable
6
DS07-12621-3E
MB95130MB Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on using evaluation products
The Evaluation product has not only the functions of the MB95130MB series but also those of other products to
support software development for multiple series and models of the F2MC-8FX. The I/O addresses for peripheral
resources not used by the MB95130MB series are therefore access-barred. Read/write access to those access-
barred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected
malfunctions of hardware or software.
Particularly, do not use word access to an odd-numbered-byte address in the prohibited areas (If such access is
used, the address may be read or written unexpectedly) .
Also, as the read values of prohibited addresses on the evaluation product are different to the values on the flash
memory and mask ROM products, do not use these values in the software processing.
The Evaluation product does not support the functions of some bits in single-byte registers. Read/write access
to these bits does not cause hardware malfunctions. No particular precautions are required to the flash memory
and mask ROM products, as they have the identical read/write operation to the evaluation products.
• Difference of memory spaces
If the amount of memory on the Evaluation product is different from that of the Flash memory or MASK ROM
product, carefully check the difference in the amount of memory from the model to be actually used when
developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current consumption
• The current consumption of Flash memory product is greater than for MASK ROM product.
• For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS”
and “■ PACKAGE DIMENSION”.
• Operating voltage
The operating voltage is different among the Evaluation, Flash memory, and MASK ROM products.
For details of the operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Difference MOD Pins
A pull-down resistor is provided for the MOD pin of the MASK ROM product.
DS07-12621-3E
7
MB95130MB Series
■ PIN ASSIGNMENT
(TOP VIEW)
P16
PF0
PF1
MOD
X0
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P15
2
P14/PPG0
3
P13/TRG0/ADTG
P12/UCK0/EC0
4
5
P11/UO0
X1
6
P10/UI0
VSS
VCC
C
7
P07/INT07/AN07
P06/INT06/AN06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/INT01/AN01/PPG01
P00/INT00/AN00/PPG00
SOP-28
8
9
*
10
11
12
13
14
PG2/X1A
*
PG1/X0A
RST
AVCC
AVSS
(FPT-28P-M17)
* : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
(Continued)
8
DS07-12621-3E
MB95130MB Series
(Continued)
(TOP VIEW)
P16
PF0
PF1
MOD
X0
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P15
2
P14/PPG0
3
P13/TRG0/ADTG
P12/UCK0/EC0
NC
4
5
X1
6
P11/UO0
VSS
VCC
C
7
P10/UI0
SSOP-30
8
P07/INT07/AN07
P06/INT06/AN06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN
NC
9
*
*
PG2/X1A
PG1/X0A
10
11
12
13
14
15
RST
AVCC
AVSS
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/INT01/AN01/PPG01
P00/INT00/AN00/PPG00
(FPT-30P-M02)
* : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
DS07-12621-3E
9
MB95130MB Series
■ PIN DESCRIPTION
Pin no.
I/O
circuit
Pin name
Function
SSOP*1 SOP*2
type*3
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P16
PF0
PF1
MOD
X0
H
K
B
A
General-purpose I/O port
General-purpose I/O port for large current
Operating mode designation pin
Main clock oscillation input pin
Main clock oscillation input/output pin
Power supply pin (GND)
X1
VSS
VCC
C
⎯
⎯
⎯
Power supply pin
Capacity connection pin
Single clock product is general-purpose port (PG2) .
Dual clock product is sub clock input/output oscillation pin (32 kHz) .
10
11
10
11
PG2/X1A
PG1/X0A
H/A
Single clock product is general-purpose port (PG1) .
Dual clock product is sub clock input oscillation pin (32 kHz) .
12
13
14
12
13
14
RST
AVCC
AVSS
B’
⎯
⎯
Reset pin
A/D converter power supply pin
A/D converter power supply pin (GND)
P00/INT00/
AN00/
PPG00
General-purpose I/O port
Shared with external interrupt input (INT00), A/D converter analog
input (AN00) and 8/16-bit PPG ch.0 output (PPG00).
15
16
17
18
20
15
16
17
18
19
P01/INT01/
AN01/
PPG01
General-purpose I/O port
Shared with external interrupt input (INT01), A/D converter analog
input (AN01) and 8/16-bit PPG ch.0 output (PPG01).
D
General-purpose I/O port
Shared with external interrupt input (INT02), A/D converter analog
input (AN02) and LIN-UART clock I/O (SCK).
P02/INT02/
AN02/SCK
General-purpose I/O port
Shared with external interrupt input (INT03), A/D converter analog
input (AN03) and LIN-UART data output (SOT).
P03/INT03/
AN03/SOT
General-purpose I/O port
Shared with external interrupt input (INT04), A/D converter analog
input (AN04) and LIN-UART data input (SIN).
P04/INT04/
AN04/SIN
E
D
P05/INT05/
AN05/TO00
General-purpose I/O port
21
22
20
21
Shared with external interrupt input (INT05 & INT06), A/D converter
analog input (AN05 & AN06) and 8/16-bit compound timer ch.0
output (TO00 & TO01).
P06/INT06/
AN06/TO01
General-purpose I/O port
Shared with external interrupt input (INT07) and A/D converter
analog input (AN07).
P07/INT07/
AN07
23
22
(Continued)
10
DS07-12621-3E
MB95130MB Series
(Continued)
Pin no.
I/O
circuit
Pin name
Function
SSOP*1 SOP*2
type*3
General-purpose I/O port
Shared with UART/SIO ch.0 data input (UI0)
24
25
23
24
P10/UIO
P11/UO0
G
General-purpose I/O port
Shared with UART/SIO ch.0 data output (UO0)
General-purpose I/O port
Shared with UART/SIO ch.0 clock I/O (UCK0) and 8/16-bit compound
timer ch.0 clock input (EC0)
P12/UCK0/
EC0
27
28
25
26
H
General-purpose I/O port
Shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D converter
trigger input (ADTG)
P13/TRG0/
ADTG
General-purpose I/O port
Shared with 16-bit PPG ch.0 output (PPG0)
29
30
27
28
⎯
P14/PPG0
P15
General-purpose I/O port
Internally connected pins.
Be sure to leave it open.
19,26
NC
⎯
*1 : FPT-30P-M02
*2 : FPT-28P-M17
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
DS07-12621-3E
11
MB95130MB Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Oscillation circuit
A
• High-speed side
Feedback resistance: approx. 1 MΩ
• Low-speed side
X1 (X1A)
Clock
input
N-ch
X0 (X0A)
X
Feedback resistance: approx. 10 MΩ
Standby control
B
Only for input
• Hysteresis input
• Pull-downresistoravailable only to MASK
ROM product
Mode input
Reset input
R
B’
• Hysteresis input only for MASK ROM
product
• Reset output
Reset output
N-ch
D
• CMOS output
• Hysteresis input
• Analog input
• Pull-up control available
• Automotive input
R
P-ch
Pull-up control
P-ch
N-ch
Digital output
Digital output
Analog input
Automotive input
Hysteresis input
A/D control
Standby control
External
interrupt control
(Continued)
12
DS07-12621-3E
MB95130MB Series
(Continued)
Type
Circuit
Remarks
E
• CMOS output
• CMOS input
• Hysteresis input
• Analog input
• Pull-up control available
• Automotive input
R
P-ch
Pull-up control
P-ch
Digital output
Digital output
N-ch
Analog input
CMOS input
Hysteresis input
Automotive input
A/D control
Standby control
External
interrupt control
G
• CMOS output
• CMOS input
R
P-ch
Pull-up control
• Hysteresis input
• Pull-up control available
• Automotive input
P-ch
N-ch
Digital output
Digital output
CMOS input
Hysteresis input
Automotive input
Standby
control
H
• CMOS output
• Hysteresis input
• Pull-up control available
• Automotive input
Pull-up control
R
P-ch
P-ch
N-ch
Digital output
Digital output
Hysteresis input
Automotive input
Standby
control
K
• CMOS output
• Hysteresis input
• Automotive input
P-ch
Digital output
Digital output
N-ch
Hysteresis input
Automotive input
Standby
control
DS07-12621-3E
13
MB95130MB Series
■ HANDLING DEVICES
• Preventing latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when the devices are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if voltage higher than the rating voltage is applied between
VCC pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
Also, take care to prevent the analog power supply voltage (AVCC) and analog input voltage from exceeding the
digital power supply voltage (VCC) when the analog system power supply is turned on or off.
• Stable supply voltage
Supply voltage should be stabilized.
A sudden change in power supply voltage may cause a malfunction even within the guaranteed operating range
of the VCC power supply voltage.
For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range
(50 / 60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient
variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
• Precautions for use of external clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from the sub clock mode or stop mode.
PIN CONNECTION
• Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent
damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ.
Any unused input/output pins may be set to the output mode and left open, or set to the input mode and treated
the same as unused input pins. If there is any unused output pin, make it open.
• Treatment of power supply pins on A/D converter
Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 μF ceramic capacitor
as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, all the pins must be connected to external power
supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe
signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect
the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS pins
near this device.
• Mode pin (MOD)
Connect the mode pin directly to VCC or VSS pins.
To prevent the device unintentionally entering the test mode due to noise, lay out the printed circuit board so as
to minimize the distance from the mode pins to VCC or VSS pins and to provide a low-impedance connection.
14
DS07-12621-3E
MB95130MB Series
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin
must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram
below.
• C Pin Connection Diagram
C
CS
• Analog power supply
Always set the same potential to AVCC pin and VCC pin. When VCC > AVCC, the current may flow through the
AN00 to AN07 pins.
• NC pins
Any pins marked “NC”(not connected) must be left open.
DS07-12621-3E
15
MB95130MB Series
■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER
• Supported parallel programmers and adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
TEF110-95F136HSPF
TEF110-95F136MB
Parallel programmers
FPT-28P-M17
FPT-30P-M02
AF9708 (Since Rev 02.43E )
AF9709/B (Since Rev 02.43E )
Note: : For information about applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector configuration
The following table shows sector-specific addresses for data access by CPU and by the parallel programmer.
• MB95F136MBS/F136NBS/F136MBW/F136NBW/F136JBS/F136JBW (32 Kbytes)
Flash memory
32 Kbytes
CPU address
8000H
Programmer address*
18000H
FFFFH
1FFFFH
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in
Flash memory.
• Programming method
1) Set the type code of the parallel programmer to “17237”.
2) Load program data to programmer addresses 18000H to 1FFFFH.
3) Write data with the parallel programmer.
• MB95F134MBS/F134NBS/F134JBS/F134MBW/F134NBW/F134JBW (16 Kbytes)
Flash memory
16 Kbytes
CPU address
C000H
Programmer address*
1C000H
FFFFH
1FFFFH
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in
Flash memory.
• Programming method
1) Set the type code of the parallel programmer to “17237”.
2) Load program data to programmer addresses 1C000H to 1FFFFH.
3) Write data with the parallel programmer.
16
DS07-12621-3E
MB95130MB Series
• MB95F133MBS/F133NBS/F133JBS/F133MBW/F133NBW/F133JBW (8 Kbytes)
Flash memory
8 Kbytes
CPU address
E000H
Programmer address*
1E000H
FFFFH
1FFFFH
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in
Flash memory.
• Programming method
1) Set the type code of the parallel programmer to “17237”.
2) Load program data to programmer addresses 1E000H to 1FFFFH.
3) Write data with the parallel programmer.
DS07-12621-3E
17
MB95130MB Series
■ BLOCK DIAGRAM
F2MC-8FX CPU
RST
ROM 32 Kbytes
RAM 1 Kbyte
Reset control
Clock control
X0/X1
PG2/(X1A)*
PG1/(X0A)*
Interrupt control
Wild register
Watch counter
Watch prescaler
External interrupt
8 channels
P00/INT00 to P07/INT07
(P00/PPG00)
(P01/PPG01)
8/16-bit PPG
2 channels
P10/U10
P11/UO0
P12/UCK0
UART/SIO
1 channel
(P02/SCK)
(P03/SOT)
(P04/SIN)
LIN-UART
1 channel
P13/TRG0/ADTG
P14/PPG0
16-bit PPG
1 channel
8/16-bit
compound timer
1 channel
(P05/TO00)
(P06/TO01)
(P12/EC0)
P15/P16
P00/AN00 to P07/AN07
8/10-bit
AVCC
A/D converter
8 channels
PF0/PF1
AVSS
Port
Port
Other pins
MOD, VCC, VSS, C
*: Single clock product is a general-purpose port, and dual clock product is a sub clock oscillation pin.
18
DS07-12621-3E
MB95130MB Series
■ CPU CORE
1. Memory Space
Memory space of the MB95130MB series is 64 Kbytes and consists of I/O area, data area, and program area.
The memory space includes special-purpose areas such as the general-purpose registers and vector table.
Memory map of the MB95130MB series is shown below.
• Memory Map
MB95F133MBS/F133NBS/F133JBS
MB95F134MBS/F134NBS/F134JBS
MB95F136MBS/F136NBS/F136JBS
MB95F133MBW/F133NBW/F133JBW
MB95F134MBW/F134NBW/F134JBW
MB95136MB
MB95FV100D-103
MB95F136MBW/F136NBW/F136JBW
0000
H
0000
H
0000
H
I/O
I/O
I/O
0080
0100
0200
H
H
H
0080
0100
0200
H
H
H
0080
0100
0200
H
H
H
RAM 3.75 Kbytes
RAM 1 Kbyte
RAM
Register
Register
Register
Address #1
Access
0480
H
Access
prohibited
prohibited
0F80
H
0F80
1000
H
0F80
H
Extended I/O
Extended I/O
Extended I/O
1000
H
H
1000
H
Access
Access
prohibited
prohibited
8000
H
Flash memory
60 Kbytes
Address #2
MASK ROM
32 Kbytes
Flash memory
FFFF
H
FFFF
H
FFFF
H
Flash memory
RAM
Address #1
Address #2
MB95F133MBS/F133NBS/F133JBS
MB95F133MBW/F133NBW/F133JBW
MB95F134MBS/F134NBS/F134JBS
MB95F134MBW/F134NBW/F134JBW
MB95F136MBS/F136NBS/F136JBS
MB95F136MBW/F136NBW/F136JBW
8 Kbytes
256 bytes
512 bytes
1 Kbyte
0180H
E000H
16 Kbytes
32 Kbytes
0280H
0480H
C000H
8000H
DS07-12621-3E
19
MB95130MB Series
2. Register
The MB95130MB series has two types of registers; dedicated registers inthe CPU and general-purpose registers
in the memory. The dedicated registers are as include:
Program counter (PC)
Accumulator (A)
: A 16-bit register to indicate locations where instructions are stored.
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower 1-byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower 1-byte is used.
Index register (IX)
Extra pointer (EP)
Stack pointer (SP)
Program status (PS)
: A 16-bit register for index modification
: A 16-bit pointer to point to a memory address.
: A 16-bit register to indicate a stack area.
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register
Initial Value
16 bits
FFFDH
0000H
0000H
0000H
0000H
0000H
0030H
: Program counter
: Accumulator
PC
AH
TH
AL
TL
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR). (Refer to the diagram below.)
• Structure of the program status
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1
bit0
C
R4
R3
R2
R1
R0 DP2 DP1 DP0
H
I
IL1
IL0
N
Z
PS
V
RP
DP
CCR
20
DS07-12621-3E
MB95130MB Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP upper
OP code lower
“0” “0” “0” “0” “0” “0” “0” “1”
R4 R3 R2 R1 R0 b2
b1
b0
Generated address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The DP specifies the area for mapping instructions (16 different types of instructions such as MOV A and dir)
using direct addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
0000H to 007FH (without mapping)
0080H to 00FFH (without mapping)
0100H to 017FH
XXXB (no effect to mapping)
0000H to 007FH
000B (initial value)
001B
010B
011B
100B
101B
110B
111B
0180H to 01FFH
0200H to 027FH
0080H to 00FFH
0280H to 02FFH
0300H to 037FH
0380H to 03FFH
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data content and the bits that
control CPU operations at interrupt.
H flag
I flag
Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is cleared to “0” when reset.
Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
:
:
:
IL1, IL0
IL1
0
IL0
0
Interrupt level
Priority
0
1
2
High
0
1
1
0
1
1
3
Low (no interruption)
N flag
Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
:
:
:
Z flag
V flag
Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
C flag
Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
:
DS07-12621-3E
21
MB95130MB Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8
registers. Up to a total of 32 banks can be used on the MB95130MB series. The bank currently in use is specified
by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)
to general-purpose register 7 (R7).
• Register Bank Configuration
8-bit
1F8H
This address = 0100
H
+ 8 × (RP)
Address 100H
R0
R1
R0
R1
R0
R1
R2
R3
R4
R5
R6
R7
R2
R3
R4
R5
R6
R7
R2
R3
R4
R5
R6
R7
1FFH
Bank 31
107H
32 banks
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
Bank 0
Memory area
22
DS07-12621-3E
MB95130MB Series
■ I/O MAP
Register
Address
Register name
R/W
Initial value
abbreviation
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
PDR0
DDR0
PDR1
DDR1
⎯
Port 0 data register
Port 0 direction register
R/W
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
00000000B
⎯
Port 1 data register
Port 1 direction register
(Disabled)
WATR
PLLC
SYCC
STBC
RSRR
TBTC
WPCR
WDTC
Oscillation stabilization wait time setting register
PLL control register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11111111B
00000000B
1010X011B
00000000B
XXXXXXXXB
00000000B
00000000B
00000000B
System clock control register
Standby control register
Reset source register
Timebase timer control register
Watch prescaler control register
Watchdog timer control register
000DH
to
0027H
⎯
(Disabled)
⎯
⎯
0028H
0029H
002AH
002BH
002CH
002DH
PDRF
DDRF
PDRG
DDRG
PUL0
PUL1
Port F data register
Port F direction register
Port G data register
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Port G direction register
Port 0 pull-up register
Port 1 pull-up register
002EH
to
0034H
⎯
(Disabled)
⎯
⎯
0035H
0036H
0037H
PULG
Port G pull-up register
R/W
R/W
R/W
00000000B
00000000B
00000000B
T01CR1
T00CR1
8/16-bit compound timer 01 control status register 1 ch.0
8/16-bit compound timer 00 control status register 1 ch.0
0038H,
0039H
⎯
(Disabled)
⎯
⎯
003AH
003BH
PC01
PC00
8/16-bit PPG1 control register ch.0
8/16-bit PPG0 control register ch.0
R/W
R/W
00000000B
00000000B
003CH
to
0041H
⎯
(Disabled)
⎯
⎯
0042H
0043H
PCNTH0
PCNTL0
16-bit PPG control status register (Upper byte) ch.0
16-bit PPG control status register (Lower byte) ch.0
R/W
R/W
00000000B
00000000B
(Continued)
DS07-12621-3E
23
MB95130MB Series
Register
Address
Register name
R/W Initial value
abbreviation
0044H
to
0047H
⎯
(Disabled)
⎯
⎯
0048H
0049H
004AH
004BH
EIC00
EIC10
EIC20
EIC30
External interrupt circuit control register ch.0,ch.1
External interrupt circuit control register ch.2,ch.3
External interrupt circuit control register ch.4,ch.5
External interrupt circuit control register ch.6,ch.7
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
004CH
to
004FH
⎯
(Disabled)
⎯
⎯
0050H
0051H
0052H
0053H
0054H
0055H
0056H
0057H
0058H
0059H
005AH
SCR
SMR
LIN-UART serial control register
LIN-UART serial mode register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
00000000B
00000000B
00001000B
00000000B
00000100B
000000XXB
00000000B
00100000B
00000001B
00000000B
00000000B
SSR
LIN-UART serial status register
RDR/TDR
ESCR
ECCR
SMC10
SMC20
SSR0
LIN-UART reception/transmission data register
LIN-UART extended status control register
LIN-UART extended communication control register
UART/SIO serial mode control register 1 ch.0
UART/SIO serial mode control register 2 ch.0
UART/SIO serial status register ch.0
TDR0
UART/SIO serial output data register ch.0
UART/SIO serial input data register ch.0
RDR0
005BH
to
006BH
⎯
(Disabled)
⎯
⎯
006CH
006DH
006EH
006FH
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
ADC1
ADC2
ADDH
ADDL
WCSR
⎯
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register (Upper byte)
8/10-bit A/D converter data register (Lower byte)
Watch counter status register
(Disabled)
R/W
R/W
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
00000000B
00000000B
⎯
FSR
⎯
Flash memory status register
(Disabled)
R/W
⎯
000X0000B
⎯
⎯
(Disabled)
⎯
⎯
⎯
(Disabled)
⎯
⎯
WREN
WROR
Wild register address compare enable register
Wild register data test setting register
R/W
R/W
00000000B
00000000B
(Continued)
24
DS07-12621-3E
MB95130MB Series
Register
abbreviation
Address
Register name
R/W Initial value
(Register bank pointer (RP)
Mirror of direct bank pointer (DP)
0078H
⎯
⎯
⎯
0079H
007AH
007BH
007CH
007DH
007EH
007FH
0F80H
0F81H
0F82H
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
ILR0
ILR1
Interrupt level setting register 0
Interrupt level setting register 1
R/W
R/W
R/W
R/W
R/W
R/W
⎯
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
⎯
ILR2
Interrupt level setting register 2
ILR3
Interrupt level setting register 3
ILR4
Interrupt level setting register 4
ILR5
Interrupt level setting register 5
⎯
(Disabled)
WRARH0
WRARL0
WRDR0
WRARH1
WRARL1
WRDR1
WRARH2
WRARL2
WRDR2
Wild register address setting register (Upper byte) ch.0
Wild register address setting register (Lower byte) ch.0
Wild register data setting register ch.0
Wild register address setting register (Upper byte) ch.1
Wild register address setting register (Lower byte) ch.1
Wild register data setting register ch.1
Wild register address setting register (Upper byte) ch.2
Wild register address setting register (Lower byte) ch.2
Wild register data setting register ch.2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
0F89H
to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
0F93H
0F94H
0F95H
T01CR0
T00CR0
T01DR
T00DR
8/16-bit compound timer 01 control status register 0 ch.0
8/16-bit compound timer 00 control status register 0 ch.0
8/16-bit compound timer 01 data register ch.0
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
8/16-bit compound timer 00 data register ch.0
8/16-bit compound timer 00/01 timer mode control register
ch.0
0F96H
TMCR0
R/W
00000000B
0F97H
to
0F9BH
⎯
(Disabled)
⎯
⎯
0F9CH
0F9DH
0F9EH
0F9FH
PPS01
PPS00
PDS01
PDS00
8/16-bit PPG1 cycle setting buffer register ch.0
8/16-bit PPG0 cycle setting buffer register ch.0
8/16-bit PPG1 duty setting buffer register ch.0
8/16-bit PPG0 duty setting buffer register ch.0
R/W
R/W
R/W
R/W
11111111B
11111111B
11111111B
11111111B
0FA0H
to
0FA3H
⎯
(Disabled)
⎯
⎯
(Continued)
DS07-12621-3E
25
MB95130MB Series
(Continued)
Register
abbreviation
Address
Register name
R/W Initial value
0FA4H
0FA5H
PPGS
REVC
8/16-bit PPG start register
R/W
R/W
00000000B
00000000B
8/16-bit PPG output inversion register
0FA6H
to
0FA9H
⎯
(Disabled)
⎯
⎯
0FAAH
0FABH
0FACH
0FADH
0FAEH
0FAFH
PDCRH0
PDCRL0
PCSRH0
PCSRL0
PDUTH0
PDUTL0
16-bit PPG down counter register (Upper byte) ch.0
16-bit PPG down counter register (Lower byte) ch.0
16-bit PPG cycle setting buffer register (Upper byte) ch.0
16-bit PPG cycle setting buffer register (Lower byte) ch.0
16-bit PPG duty setting buffer register (Upper byte) ch.0
16-bit PPG duty setting buffer register (Lower byte) ch.0
R
00000000B
00000000B
11111111B
11111111B
11111111B
11111111B
R
R/W
R/W
R/W
R/W
0FB0H
to
0FBBH
⎯
(Disabled)
⎯
⎯
0FBCH
0FBDH
BGR1
BGR0
LIN-UART baud rate generator register 1
LIN-UART baud rate generator register 0
R/W
R/W
00000000B
00000000B
UART/SIO dedicated baud rate generator
prescaler selection register ch.0
0FBEH
0FBFH
PSSR0
BRSR0
R/W
R/W
00000000B
00000000B
UART/SIO dedicated baud rate generator
baud rate setting register ch.0
0FC0H
to
0FC2H
⎯
AIDRL
⎯
(Disabled)
A/D input disable register (Lower byte)
(Disabled)
⎯
R/W
⎯
⎯
00000000B
⎯
0FC3H
0FC4H
to
0FE2H
0FE3H
WCDR
⎯
Watch counter data register
(Disabled)
R/W
⎯
00111111B
⎯
0FE4H
to
0FE6H
0FE7H
ILSR2
⎯
Input level select register 2 (option)
(Disabled)
R/W
⎯
00000000B
⎯
0FE8H,
0FE9H
0FEAH
CSVCR
Clock supervisor control register
R/W
00011100B
0FEBH
to
0FEDH
⎯
(Disabled)
⎯
⎯
0FEEH
0FEFH
ILSR
Input level select register
R/W
R/W
00000000B
01000000B
WICR
Interrupt pin control register
0FF0H
to
0FFFH
⎯
(Disabled)
⎯
⎯
26
DS07-12621-3E
MB95130MB Series
• R/W access symbols
R/W : Readable / Writable
R
W
: Read only
: Write only
• Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is undefined.
Note: : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
DS07-12621-3E
27
MB95130MB Series
■ INTERRUPT SOURCE TABLE
Vector table address
Same level
priority order
(atsimultaneous
occurrence)
Interrupt
request
number
Bit name of
interrupt level
setting register
Interrupt source
Upper
Lower
High
External interrupt ch.0
IRQ0
FFFAH
FFFBH
L00 [1 : 0]
External interrupt ch.4
External interrupt ch.1
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
UART/SIO ch.0
IRQ1
IRQ2
IRQ3
FFF8H
FFF6H
FFF4H
FFF9H
FFF7H
FFF5H
L01 [1 : 0]
L02 [1 : 0]
L03 [1 : 0]
IRQ4
IRQ5
FFF2H
FFF0H
FFEEH
FFECH
FFEAH
FFE8H
FFE6H
FFE4H
FFE2H
FFE0H
FFDEH
FFDCH
FFDAH
FFD8H
FFD6H
FFD4H
FFD2H
FFD0H
FFCEH
FFCCH
FFF3H
FFF1H
FFEFH
FFEDH
FFEBH
FFE9H
FFE7H
FFE5H
FFE3H
FFE1H
FFDFH
FFDDH
FFDBH
FFD9H
FFD7H
FFD5H
FFD3H
FFD1H
FFCFH
FFCDH
L04 [1 : 0]
L05 [1 : 0]
L06 [1 : 0]
L07 [1 : 0]
L08 [1 : 0]
L09 [1 : 0]
L10 [1 : 0]
L11 [1 : 0]
L12 [1 : 0]
L13 [1 : 0]
L14 [1 : 0]
L15 [1 : 0]
L16 [1 : 0]
L17 [1 : 0]
L18 [1 : 0]
L19 [1 : 0]
L20 [1 : 0]
L21 [1 : 0]
L22 [1 : 0]
L23 [1 : 0]
8/16-bit compound timer ch.0 (Lower)
8/16-bit compound timer ch.0 (Higher)
LIN-UART (reception)
LIN-UART (transmission)
(Unused)
IRQ6
IRQ7
IRQ8
IRQ9
(Unused)
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
IRQ20
IRQ21
IRQ22
IRQ23
(Unused)
8/16-bit PPG ch.0 (Upper)
8/16-bit PPG ch.0 (Lower)
(Unused)
16-bit PPG ch.0
(Unused)
(Unused)
8/10-bit A/D converter
Timebase timer
Watch prescaler/Watch counter
(Unused)
(Unused)
Flash memory
Low
28
DS07-12621-3E
MB95130MB Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
AVCC
Power supply voltage*1
VSS − 0.3
VSS + 6.0
V
*2
Input voltage*1
Output voltage*1
VI
VO
VSS − 0.3
VSS − 0.3
− 2.0
VSS + 6.0
VSS + 6.0
+ 2.0
V
V
*3
*3
Maximum clamp current
ICLAMP
mA Applicable to pins*4
Total maximum clamp
current
Σ|ICLAMP|
⎯
⎯
20
mA Applicable to pins*4
IOL1
IOL2
15
15
Other than PF0, PF1
“L” level maximum
output current
mA
PF0, PF1
Other than PF0, PF1
Average output current =
operating current × operating ratio
IOLAV1
4
(1 pin)
“L” level average
current
⎯
mA
PF0, PF1
Average output current =
operating current × operating ratio
(1 pin)
IOLAV2
12
“L” level total maximum
output current
ΣIOL
⎯
⎯
100
50
mA
Total average output current =
mA operating current × operating ratio
(Total of pins)
“L” level total average
output current
ΣIOLAV
IOH1
IOH2
− 15
− 15
Other than PF0, PF1
“H” level maximum
output current
⎯
mA
PF0, PF1
Other than PF0, PF1
Average output current =
IOHAV1
− 4
− 8
operating current × operating ratio
(1 pin)
mA
“H” level average
current
⎯
PF0, PF1
Average output current =
operating current × operating ratio
(1 pin)
IOHAV2
“H” level total maximum
output current
ΣIOH
⎯
⎯
− 100
− 50
mA
Total average output current =
mA operating current × operating ratio
(Total number of pins)
“H” level total average
output current
ΣIOHAV
Power consumption
Operating temperature
Storage temperature
Pd
TA
⎯
320
mW
°C
− 40
− 55
+ 105
+ 150
Tstg
°C
(Continued)
29
DS07-12621-3E
MB95130MB Series
(Continued)
*1: These parameters are based on the condition that both AVSS and VSS are 0.0 V.
*2: Apply equal potential to AVCC and VCC.
*3: VI and VO should not exceed Vcc + 0.3 V. VI must not exceed the rating voltage. However, if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes
the VI rating.
*4: Applicable pins: P10 to P15, PF0, PF1 (Inapplicable pins: PG1, PG2)
• Use within recommended operating conditions.
• Use at DC voltage (current).
• +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affects
other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
•Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept
+B signal input.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
Vcc
Limiting
resistance
P-ch
+ B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
30
DS07-12621-3E
MB95130MB Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Parameter
Symbol
Unit
Remarks
Min
2.42*2
2.3
Max
5.5*1
5.5
At normal operation
VCC,
AVCC
Power supply voltage
V
Holds condition in stop mode
*3
Smoothing capacitor
CS
TA
0.1
1.0
μF
°C
Operating temperature
− 40
+ 105
*1: The value varies depending on the operating frequency.
*2: The value is 2.88 V when the low-voltage detection reset is used.
*3: Use ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin
must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram
below.
• C pin connection diagram
C
C
S
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-12621-3E
31
MB95130MB Series
3. DC Characteristics
(VCC = = AVCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Typ
Parameter Symbol
Pin name
Condition
Unit
Remarks
Min
Max
P04 (selectable
in SIN),
P10 (selectable
in UI0)
VIHI
⎯
0.7 VCC
⎯
⎯
⎯
VCC + 0.3
V
Hysteresis input
P00 to P07,
P10 to P16, PF0,
PF1,
VIHSI
⎯
⎯
0.8 VCC
0.8 Vcc
VCC + 0.3
VCC + 0.3
V
V
Hysteresis input
PG1, PG2
“H” level
input
voltage
P00 to P07,
P10 to P16, PF0,
PF1,
Pin input at selecting
of Automotive
input level
VIHA
PG1, PG2
CMOS input
(Flash memory
product)
⎯
⎯
0.7 VCC
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
VIHM
RST, MOD
Hysteresis input
(MASK ROM
product)
P04 (selectable
in SIN),
P10 (selectable
in UI0)
VIL
VILS
VILA
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
VSS − 0.3
⎯
⎯
⎯
0.3 VCC
0.2 VCC
0.5 VCC
V
V
V
Hysteresis input
Hysteresis input
P00 to P07,
P10 to P16, PF0,
PF1,
PG1, PG2
“L” level
input
voltage
P00 to P07,
P10 to P16, PF0,
PF1,
Pin input at selecting
of Automotive
input level
PG1, PG2
CMOS input
(Flash memory
product)
⎯
⎯
VSS − 0.3
VSS − 0.3
⎯
⎯
0.3 VCC
0.2 VCC
V
V
VILM
RST, MOD
Hysteresis input
(MASK ROM
product)
Outputpinsother
than PF0, PF1
“H” level
output
voltage
VOH1
VOH2
IOH = − 4.0 mA VCC − 0.5
IOH = − 8.0 mA VCC − 0.5
⎯
⎯
⎯
⎯
V
V
PF0, PF1
Outputpinsother
“L” level
output
voltage
VOL1
VOL2
than PF0 to PF7, IOL = 4.0 mA
⎯
⎯
⎯
⎯
0.4
0.4
V
V
RST*1
PF0, PF1
IOL = 12 mA
(Continued)
32
DS07-12621-3E
MB95130MB Series
(VCC = AVCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Parameter Symbol
Pin name
Condition
Unit
Remarks
Min
Typ
Max
Input
leakage
current
(Hi-Z out-
put leakage
current)
When the
pull-up
prohibition
setting
P00 to P07, P10
to P16, PF0,
PF1, PG1, PG2
ILI
0.0 V < VI < VCC
− 5
⎯
+ 5
μA
When the
pull-up
permission
setting
P00 to P07, P10
to P16, PG1,
PG2
Pull-up
RPULL
VI = 0.0 V
25
50
100
kΩ
resistor
Pull-down
RMOD
MASK ROM
product only
MOD
VI = VCC
50
100
5
200
15
kΩ
resistor
Other than
AVCC, AVss, C,
Vcc and Vss
Input
CIN
f = 1 MHz
⎯
pF
capacity
Flash memory
product
(at other than
Flash memory
writing and
erasing)
⎯
9.5
12.5
mA
VCC = 5.5 V
FCH = 20 MHz
FMP = 10 MHz
Main clock mode
(divided by 2)
Flash memory
product
mA (at Flash
memory writing
⎯
⎯
30
35
and erasing)
MASK ROM
product
7.2
9.5
mA
mA
Power
VCC
supply
ICC
(External clock
operation)
Flash memory
product
(at other than
Flash memory
writing and
erasing)
current*2
⎯
15.2
20.0
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
Flash memory
product
mA (at Flash
memory writing
⎯
⎯
35.7
11.6
42.5
15.2
and erasing)
MASK ROM
product
mA
(Continued)
DS07-12621-3E
33
MB95130MB Series
(VCC = AVCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Parameter Symbol
Pin name
Condition
Unit
Remarks
Min
Typ
Max
VCC = 5.5 V
FCH = 20 MHz
FMP = 10 MHz
Main Sleep mode
(divided by 2)
⎯
4.5
7.2
7.5
mA
ICCS
FCH = 32 MHz
FMP = 16 MHz
Main Sleep mode
(divided by 2)
⎯
⎯
12.0
100
mA
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Sub clock mode
(divided by 2) ,
TA = + 25 °C
Dual clock
product only
ICCL
45
μA
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2) ,
TA = + 25 °C
Dual clock
product only
ICCLS
⎯
⎯
10
81
27
μA
μA
Power
VCC
supply
(External clock
operation)
current*2
VCC = 5.5 V
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
Dual clock
product only
ICCT
4.6
VCC = 5.5 V
Flash memory
product
⎯
⎯
9.3
7
12.5
9.5
mA
mA
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
MASK ROM
product
ICCMPLL
Flash memory
product
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
⎯
⎯
14.9
11.2
20.0
15.2
mA
mA
MASK ROM
product
VCC = 5.5 V
FCL = 32 kHz
Dual clock
product only
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
ICCSPLL
⎯
160
400
μA
(Continued)
34
DS07-12621-3E
MB95130MB Series
(Continued)
(VCC = AVCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Parameter Symbol
Pin name
Condition
Unit
Remarks
Min
Typ
Max
VCC = 5.5 V
FCH = 10 MHz
Timebase timer
mode
ICTS
⎯
0.15
1.1
mA
VCC
(External clock
operation)
TA = + 25 °C
VCC = 5.5 V
Sub stop mode
TA = + 25 °C
Mainstopmode
ICCH
⎯
⎯
3.5
2.4
20.0
4.7
μA for single clock
product
Power
supply
VCC = 5.5 V
FCH = 16 MHz
When A/D conver-
sion is in operation
current*2
IA
mA
AVcc
VCC = 5.5 V
FCH = 16 MHz
When A/D conver-
sion is stopped
TA = + 25 °C
IAH
⎯
1
5
μA
*1: Product without clock supervisor only
*2: • The power supply current is specified by the external clock. When the low-voltage detection and clock
supervisor options are selected, the consumption current values of both the low-voltage detection circuit (ILVD)
and the built-in CR oscillator (ICSV) must also be added to the power supply current value.
• Refer to “4. AC Characteristics: (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC Characteristics: (2) Source Clock / Machine Clock” for FMP and FMPL.
DS07-12621-3E
35
MB95130MB Series
4. AC Characteristics
(1) Clock Timing
(VCC = 2.42 V to 5.0 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Sym-
bol
Condi-
tion
Parameter
Pin name
Unit
16.25 MHz
Remarks
Min
Typ
Max
When using main
oscillation circuit
1.00
⎯
1.00
3.00
3.00
3.00
3.00
⎯
⎯
⎯
⎯
⎯
32.50 MHz When using external clock
10.00 MHz Main PLL multiplied by 1
8.13 MHz Main PLL multiplied by 2
6.50 MHz Main PLL multiplied by 2.5
4.06 MHz Main PLL multiplied by 4
When using sub
FCH
X0, X1
Clock frequency
⎯
⎯
32.768
32.768
⎯
kHz
kHz
ns
oscillation circuit
FCL
X0A, X1A
X0, X1
When using sub PLL
VCC = 2.3 V to 3.6 V
⎯
⎯
When using main
oscillation circuit
61.5
30.8
⎯
⎯
⎯
1000
1000
⎯
tHCYL
Clock cycle time
ns When using external clock
When using sub
μs
tLCYL X0A, X1A
30.5
oscillation circuit
tWH1
tWL1
X0
61.5
⎯
⎯
15.2
⎯
⎯
⎯
5
ns
When using external clock
duty ratio is about 30% to
70%.
Input clock pulse width
Input clock rise/fall time
tWH2
X0A
tWL2
μs
tCR
X0, X0A
tCF
⎯
ns When using external clock
36
DS07-12621-3E
MB95130MB Series
• Input wave form for using external clock (main clock)
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of Main Clock Input Port External Connection
When using crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0
X1
X0
X1
Open
F
CH
FCH
C1
C2
• Input wave form for using external clock (sub clock)
t
LCYL
t
WH2
tWL2
t
CR
tCF
0.8 VCC 0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of Sub clock Input Port External Connection
When using crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0A
X1A
X0A
X1A
Open
FCL
F
CL
C1
C2
DS07-12621-3E
37
MB95130MB Series
(2) Source Clock / Machine Clock
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Pin
name
Parameter
Symbol
Unit
Remarks
Min
Typ
Max
When using main clock
61.5
⎯
2000
ns Min : FCH = 8.125 MHz, PLL multiplied by 2
Source clock
cycle time*1
(Clock before
setting division)
Max : FCH = 1 MHz, divided by 2
tSCLK
⎯
When using sub clock
7.6
⎯
61.0
μs Min : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
FSP
⎯
⎯
0.50
⎯
⎯
16.25 MHz When using main clock
131.072 kHz When using sub clock
When using main clock
Source clock
frequency
FSPL
16.384
Machine clock
cycle time*2
(Minimum
instruction
execution time)
61.5
7.6
⎯
⎯
32000
ns Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
tMCLK
⎯
When using sub clock
976.5
μs Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
FMP
0.031
1.024
⎯
⎯
16.250 MHz When using main clock
131.072 kHz When using sub clock
Machine clock
frequency
⎯
FMPL
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
38
DS07-12621-3E
MB95130MB Series
• Outline of clock generation block
F
CH
Divided by 2
(main oscillation)
Main PLL
× 1
× 2
× 2.5
× 4
Division
circuit
SCLK
(source clock)
× 1
MCLK
(machine clock)
× 1/4
× 1/8
× 1/16
F
CL
Divided by 2
(sub oscillation)
Clock mode select bit
(SYCC: SCS1, SCS0)
Sub PLL
× 2
× 3
× 4
DS07-12621-3E
39
MB95130MB Series
• Operating voltage - Operating frequency (When TA = − 40 °C to + 105 °C)
• MB95136MB/F133MBS/F133NBS/F133JBS/F134MBS/F134NBS/F134JBS/F136MBS/F136NBS/F136JBS/
MB95F133MBW/F133NBW/F133JBW/F134MBW/F134NBW/F134JBW/F136MBW/F136NBW/
MB95F136JBW
Sub PLL, sub clock mode and
watch mode operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
5.5
5.5
3.5
2.42
2.42
0.5 MHz 3 MHz
10 MHz
16.25 MHz
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSPL)
• Operating voltage - Operating frequency (When TA = + 5 °C to + 35 °C)
• MB95FV100D-103
Sub PLL, sub clock mode and
watch mode operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
5.5
5.5
2.7
3.5
2.7
0.5 MHz 3 MHz
10 MHz
16.25 MHz
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
PLL operation guarantee range
Source clock frequency (FSPL)
40
DS07-12621-3E
MB95130MB Series
• Main PLL operation frequency
[MHz]
16.25
16
15
× 4
12
10
× 2.5
× 1
× 2
7.5
6
5
3
[MHz]
10
0
3
4
5
6.4
8
6.5
4.062
8.125
Main oscillation (FCH)
DS07-12621-3E
41
MB95130MB Series
(3) External Reset
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Pin
Parameter Symbol
name
Unit
Remarks
Min
Max
2 tMCLK*1
⎯
ns At normal operation
RST “L” level
pulse width
Oscillation time of oscillator*2
At stop mode, sub clock mode,
μs
tRSTL
RST
⎯
⎯
+ 100
sub sleep mode & watch mode
100
μs At timebase timer mode
*1 : Refer to “ (2) Source Clock / Machine Clock” for tMCLK.
*2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the
oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between
hundreds of μs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
100 μs
Oscillation stabilization wait time
Oscillation time
of oscillator
Execute instruction
Internal reset
42
DS07-12621-3E
MB95130MB Series
(4) Power-on Reset
Parameter
(AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Pin
name
Symbol
Condition
Unit
Remarks
Min
Max
Power supply rising time
Power supply cutoff time
tR
⎯
⎯
⎯
50
ms
ms
VCC
Waiting time until
power-on
tOFF
1
⎯
Note: Complete the power-on process within the selected oscillation stabilization wait time.
tR
tOFF
2.5 V
0.2 V
0.2 V
0.2 V
VCC
Note: Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 30 mV/ms as shown below.
V
CC
Limiting the slope of rising within
30 mV/ms is recommended.
2.3 V
Hold Condition in stop mode
V
SS
DS07-12621-3E
43
MB95130MB Series
(5) Peripheral Input Timing
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Parameter
Symbol
Pin name
Unit
Min
Max
⎯
tILIH
tIHIL
Peripheral input “H” pulse
Peripheral input “L” pulse
2 tMCLK*
2 tMCLK*
ns
ns
INT00 to INT07,
EC0, TRG0/ADTG
⎯
* : Refer to “ (2) Source Clock / Machine Clock” for tMCLK.
tILIH
tIHIL
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
INT00 to INT07,
EC0,TRG0/ADTG
44
DS07-12621-3E
MB95130MB Series
(6) UART/SIO Serial I/O Timing
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Parameter
Symbol
Pin name
Condition
Unit
Min
Max
⎯
Serial clock cycle time
UCK ↓ → UO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
UCK0
UCK0, UO0
UCK0, UI0
UCK0, UI0
UCK0
4 tMCLK*
− 190
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
+190
⎯
Valid UI → UCK ↑
2 tMCLK*
2 tMCLK*
4 tMCLK*
4 tMCLK*
⎯
UCK ↑→ valid UI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
UCK ↓ → UO time
⎯
⎯
UCK0
⎯
External clock
UCK0, UO0 operation output pin :
190
⎯
CL = 80 pF + 1 TTL.
Valid UI → UCK ↑
UCK0, UI0
2 tMCLK*
2 tMCLK*
UCK ↑→ valid UI hold time
UCK0, UI0
⎯
* : Refer to “ (2) Source Clock / Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
2.4 V
UCK0
0.8 V
0.8 V
tSLOV
UO0
2.4 V
0.8 V
tIVSH
tSHIX
UI0
• External shift clock mode
UCK0
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tSLSH
tSHSL
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tSLOV
UO0
UI0
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
DS07-12621-3E
45
MB95130MB Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Min
5 tMCLK*3
− 95
Max
Serial clock cycle time
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSCYC
SCK
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
tSLOVI SCK, SOT
+95
tIVSHI
tSHIXI
tSLSH
tSHSL
SCK, SIN
SCK, SIN
SCK
tMCLK*3 + 190
⎯
SCK ↑ → valid SIN hold time
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
0
3 tMCLK*3 − tR
tMCLK*3 + 95
⎯
⎯
⎯
SCK
⎯
tSLOVE SCK, SOT
2 tMCLK*3 + 95
External clock
tIVSHE SCK, SIN operationoutputpin:
190
⎯
⎯
10
10
CL = 80 pF + 1 TTL.
SCK ↑ → valid SIN hold time
SCK fall time
tSHIXE SCK, SIN
tMCLK*3 + 95
⎯
tF
SCK
SCK
SCK rise time
tR
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock / Machine Clock” for tMCLK.
46
DS07-12621-3E
MB95130MB Series
• Internal shift clock mode
SCK
tSCYC
2.4 V
0.8 V
tSLOVI
0.8 V
2.4 V
0.8 V
SOT
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
SIN
• External shift clock mode
tSHSL
tSLSH
0.8 VCC
0.8 VCC
0.8 VCC
SCK
SOT
SIN
0.2 VCC
tSLOVE
0.2 VCC
tR
tF
2.4 V
0.8 V
tIVSHE
tSHIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
DS07-12621-3E
47
MB95130MB Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Min
5 tMCLK*3
− 95
Max
Serial clock cycle time
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
tSCYC
tSHOVI
tIVSLI
tSLIXI
tSHSL
tSLSH
SCK
SCK, SOT
SCK, SIN
SCK, SIN
SCK
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
+95
tMCLK*3 + 190
⎯
SCK ↓ → valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
0
3 tMCLK*3 − tR
tMCLK*3 + 95
⎯
⎯
⎯
SCK
⎯
tSHOVE SCK, SOT
2 tMCLK*3 + 95
External clock
tIVSLE
tSLIXE
tF
SCK, SIN operation output pin :
190
⎯
⎯
10
10
CL = 80 pF + 1 TTL.
SCK ↓ → valid SIN hold time
SCK fall time
SCK, SIN
tMCLK*3 + 95
⎯
SCK
SCK
SCK rise time
tR
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “(2) Source Clock / Machine Clock” for tMCLK.
48
DS07-12621-3E
MB95130MB Series
• Internal shift clock mode
SCK
tSCYC
2.4 V
2.4 V
0.8 V
tSHOVI
2.4 V
0.8 V
SOT
SIN
tSLIXI
tIVSLI
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
SCK
tSHSL
tSLSH
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tF
tR
tSHOVE
2.4 V
0.8 V
SOT
SIN
tIVSLE
tSLIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
DS07-12621-3E
49
MB95130MB Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Min
Max
⎯
Serial clock cycle time
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
tSCYC
tSHOVI
tIVSLI
SCK
5 tMCLK*3
ns
ns
ns
SCK, SOT
SCK, SIN
− 95
+95
⎯
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
tMCLK*3 + 190
SCK ↓ → valid SIN hold
tSLIXI
SCK, SIN
SCK, SOT
0
⎯
ns
ns
time
SOT → SCK ↓ delay time
tSOVLI
⎯
4 tMCLK*3
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock / Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSHOVI
tSOVLI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
tSLIXI
t
IVSLI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
50
DS07-12621-3E
MB95130MB Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Min
Max
⎯
Serial clock cycle time
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSOVHI
SCK
5 tMCLK*3
ns
ns
ns
ns
ns
SCK, SOT
− 95
+95
⎯
Internal clock
SCK, SIN operating output pin : tMCLK*3 + 190
CL = 80 pF + 1 TTL.
SCK ↑ → valid SIN hold time
SOT → SCK ↑ delay time
SCK, SIN
SCK, SOT
0
⎯
4 tMCLK*3
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock / Machine Clock” for tMCLK.
tSCYC
2.4 V
2.4 V
SCK
0.8 V
tSOVHI
tSLOVI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
tIVSHI
tSHIXI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
DS07-12621-3E
51
MB95130MB Series
(8) Low voltage Detection
(AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Typ
2.70
2.60
100
⎯
Sym-
Parameter
Unit
Remarks
bol
Min
Max
2.88
2.78
⎯
Release voltage
VDL+
VDL−
VHYS
Voff
2.52
2.42
70
V
V
At power-supply rise
Detection voltage
At power-supply fall
Hysteresis width
mV
V
Power-supply start voltage
Power-supply end voltage
⎯
2.3
Von
4.9
⎯
⎯
V
Slope of power supply that reset re-
lease signal generates
0.3
⎯
3000
⎯
⎯
⎯
⎯
⎯
μs
μs
μs
μs
Power-supply voltage
change time
(at power supply rise)
tr
Slope of power supply that reset re-
lease signal generates within rating
(VDL+)
⎯
Slope of power supply that reset
detection signal generates
300
⎯
Power-supply voltage
change time
(at power supply fall)
tf
Slope of power supply that reset
detection signal generates within rat-
ing (VDL-)
300
Reset release delay time
Reset detection delay time
td1
td2
⎯
⎯
⎯
⎯
400
30
μs
μs
Consumption current of low voltage
detection circuit only
Consumption current
ILVD
⎯
38
50
μA
52
DS07-12621-3E
MB95130MB Series
VCC
Von
Voff
Time
tf
tr
VCC
VDL+
VDL-
VHYS
Internal reset
signal
Time
td1
td2
DS07-12621-3E
53
MB95130MB Series
(9) Clock Supervisor Clock
(VCC = AVCC = 5 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Typ
100
⎯
Sym-
bol
Parameter
Unit
Remarks
Min
50
Max
200
10
Oscillation frequency
Oscillation start time
fOUT
twk
kHz
⎯
μs
Current consumption of built-in
Current consumption
ICSV
⎯
20
36
μA CR oscillator at 100 kHz
oscillation
54
DS07-12621-3E
MB95130MB Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVCC = VCC = 4.0 V to 5.5 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Parameter
Resolution
Symbol
Unit
Remarks
Min
⎯
Typ
⎯
Max
10
bit
Total error
− 3.0
− 2.5
⎯
+ 3.0
+ 2.5
LSB
LSB
⎯
Linearity error
⎯
Differential linear
error
− 1.9
⎯
+ 1.9
LSB
V
Zero transition
voltage
VOT
AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
AVCC − 4.5 LSB AVCC − 1.5 LSB AVCC + 0.5 LSB
Full-scale transition
voltage
VFST
V
0.9
1.8
⎯
⎯
16500
16500
μs 4.5 V ≤ AVCC ≤ 5.5 V
μs 4.0 V ≤ AVCC < 4.5 V
Compare time
Sampling time
⎯
4.5 V ≤ AVcc ≤ 5.5 V,
μs At external impedance
< at 5.4 kΩ
0.6
1.2
⎯
⎯
∞
∞
⎯
4.0 V ≤ AVcc ≤ 4.5 V,
μs At external impedance
< at 2.4 kΩ
Analog input current
Analog input voltage
IAIN
− 0.3
⎯
⎯
+ 0.3
μA
VAIN
AVSS
AVCC
V
DS07-12621-3E
55
MB95130MB Series
(2) Notes on Using A/D Converter
• External impedance of analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• Analog input equivalent circuit
R
Analog input
Comparator
C
During sampling : ON
R
C
4.5 V ≤ AVCC ≤ 5.5 V 2.0 kΩ (Max)
4.0 V ≤ AVCC < 4.5 V 8.2 kΩ (Max)
16 pF (Max)
16 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = at 0 kΩ to 20 kΩ)
(External impedance = at 0 kΩ to 100 kΩ)
100
20
90
18
AVCC ≥ 4.5 V
AVCC ≥ 4.5 V
80
70
16
14
12
AVCC ≥ 4.0 V
60
50
40
30
20
10
0
AVCC ≥ 4.0 V
10
8
6
4
2
0
0
2
4
6
8
10
12
14
0
1
2
3
4
Minimum sampling time [μs]
Minimum sampling time [μs]
• Errors
As |AVCC − AVSS| becomes smaller, values of relative errors grow larger.
56
DS07-12621-3E
MB95130MB Series
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
3FE
H
3FE
H
Actual conversion
characteristic
1.5 LSB
3FD
H
3FD
H
{1 LSB × (N − 1) + 0.5 LSB}
004
003
002
001
H
H
H
H
004
003
002
001
H
H
H
H
V
NT
V
OT
Actual conversion
characteristic
1 LSB
0.5 LSB
Ideal characteristics
AVSS
AVSS
AVCC
AVCC
Analog input
Analog input
Total error of
digital output N
AVCC − AVSS
VNT − {1 LSB × (N − 1) + 0.5 LSB}
=
1 LSB =
(V)
[LSB]
1024
1 LSB
N
: A/D converter digital output value
VNT : Voltage at which digital output transits from (N-1) H to NH.
(Continued)
DS07-12621-3E
57
MB95130MB Series
(Continued)
Full-scale transition error
Zero transition error
Ideal
004H
characteristics
Actual conversion
characteristics
3FFH
3FEH
3FDH
3FCH
Actual conversion
characteristics
003H
Ideal
characteristics
002H
VFST
(Actual value)
Actual conversion
characteristics
Actual conversion
characteristics
001H
VOT (Actual value)
AVSS
AVCC
AVSS
AVCC
Analog input
Analog input
Linearity error
Differential linear error
Actualconversion
characteristics
Ideal characteristics
3FFH
3FEH
3FDH
(N+1)H
NH
Actual conversion
characteristics
{1 LSB × N + VOT}
V (N+1)T
VFST
(Actual value)
VNT
004H
003H
002H
001H
(N-1)H
(N-2)H
VNT
Actual conversion
characteristics
Actual conversion
characteristics
Ideal characteristics
VOT (Actual value)
AVSS
AVCC
AVSS
AVCC
Analog input
Analog input
Linear error of
digital output N
VNT − {1 LSB × N + VOT}
V (N + 1) T − VNT
Differential linear error
of digital output N
=
=
− 1
1 LSB
1 LSB
N
: A/D converter digital output value
VNT : Voltage at which digital output transits from (N - 1)H to NH.
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVCC − 1.5 LSB [V]
58
DS07-12621-3E
MB95130MB Series
6. Flash Memory Program/Erase Characteristics
Value
Parameter
Unit
Remarks
Min
⎯
Typ
1.0*1
32
Max
15.0*2
3600
⎯
Chip erase time
s
Excludes 00H programming prior erasure.
Byte programming time
Erase/program cycle
⎯
μs Excludes system-level overhead.
cycle
10000
⎯
Power supply voltage at erase/
program
4.5
⎯
⎯
5.5
V
Flash memory data retention
time
20*3
⎯
year Average TA = +85 °C
*1 : TA = + 25 °C, VCC = 5.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 4.5 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
DS07-12621-3E
59
MB95130MB Series
■ MASK OPTION
MB95F133MBS
MB95F133NBS
MB95F133JBS
MB95F134MBS
MB95F134NBS
MB95F134JBS
MB95F136MBS
MB95F136NBS
MB95F136JBS
MB95F133MBW
MB95F133NBW
MB95F133JBW
MB95F134MBW
MB95F134NBW
MB95F134JBW
MB95F136MBW
MB95F136NBW
MB95F136JBW
Part number
MB95136MB
MB95FV100D-103
No.
Specify when
ordering
Setting
disabled
Setting
disabled
Setting
disabled
Specifying procedure
MASK
Clock mode select
• Single-system clock mode
• Dual-system clock mode
Single-system
clock mode
Dual-system clock
mode
Changing by the
switch on MCU board
1
2
3
selectable
Low voltage detection reset*
• With low voltage detection Specify when
reset
• Without low voltage
detection reset
Specified by
part number
Specified by
part number
Change by the switch
on MCU board
ordering
MASK
Clock supervisor*
• With clock supervisor
• Without clock supervisor
Specify when
ordering
Specified by part Specified by part Change by the switch
number
number
on MCU board
MASK
MCU board switch set
as following ;
• With supervisor :
Without reset output
• Without supervisor :
With reset output
Reset output*
• With reset output
• Without reset output
4
5
Not selectable Not selectable
Fixed to
Not selectable
Fixed to oscillation Fixed to oscillation
oscillation
Fixed to oscillation
stabilization wait time
of (214 − 2) /FCH
Oscillation stabilization
wait time
stabilization wait
time of
stabilization wait
time of
stabilization
wait time of
(214 − 2) /FCH
(214 − 2) /FCH
(214 − 2) /FCH
*: Refer to table below about clock mode select, low voltage detection reset, clock supervisor select and reset
output.
60
DS07-12621-3E
MB95130MB Series
Low-voltage
detection reset
Part number
Clock mode select
Clock supervisor
Reset output*
No
Yes
Yes
No
No
No
Yes
Yes
No
Single - system
Yes
No
MB95136MB
Yes
Yes
No
Dual - system
Yes
Yes
No
No
Yes
No
MB95F133MBS
MB95F133NBS
MB95F133JBS
MB95F134MBS
MB95F134NBS
MB95F134JBS
MB95F136MBS
MB95F136NBS
MB95F136JBS
MB95F133MBW
MB95F133NBW
MB95F133JBW
MB95F134MBW
MB95F134NBW
MB95F134JBW
MB95F136MBW
MB95F136NBW
MB95F136JBW
Yes
Yes
No
Yes
Yes
No
No
Yes
No
Yes
Yes
No
Single - system
Yes
Yes
No
No
Yes
No
Yes
Yes
No
Yes
Yes
No
No
Yes
No
Yes
Yes
No
Yes
Yes
No
No
Yes
No
Yes
Yes
No
Dual - system
Yes
Yes
No
No
Yes
No
Yes
Yes
No
Yes
Yes
No
No
Yes
No
Yes
Yes
No
Single - system
Dual - system
Yes
Yes
No
No
Yes
No
MB95FV100D-103
Yes
Yes
No
Yes
Yes
No
Yes
*: If the clock supervisor is selected, reset output is always disabled.
DS07-12621-3E
61
MB95130MB Series
■ ORDERING INFORMATION
Part number
Package
MB95136MBPF
MB95F133MBSPF
MB95F133NBSPF
MB95F133JBSPF
MB95F134MBSPF
MB95F134NBSPF
MB95F134JBSPF
MB95F136MBSPF
MB95F136NBSPF
MB95F136JBSPF
MB95F133MBWPF
MB95F133NBWPF
MB95F133JBWPF
MB95F134MBWPF
MB95F134NBWPF
MB95F134JBWPF
MB95F136MBWPF
MB95F136NBWPF
MB95F136JBWPF
28-pin plastic SOP
(FPT-28P-M17)
MB95136MBPFV
MB95F133MBSPFV
MB95F133NBSPFV
MB95F133JBSPFV
MB95F134MBSPFV
MB95F134NBSPFV
MB95F134JBSPFV
MB95F136MBSPFV
MB95F136NBSPFV
MB95F136JBSPFV
MB95F133MBWPFV
MB95F133NBWPFV
MB95F133JBWPFV
MB95F134MBWPFV
MB95F134NBWPFV
MB95F134JBWPFV
MB95F136MBWPFV
MB95F136NBWPFV
MB95F136JBWPFV
30-pin plastic SSOP
(FPT-30P-M02)
MCU board
224-pin plastic PFBGA
MB2146-303A-E
(MB95FV100D-103PBT)
(
)
(BGA-224P-M08)
62
DS07-12621-3E
MB95130MB Series
■ PACKAGE DIMENSION
28-pin plastic SOP
Lead pitch
Package width
1.27 mm
8.6 × 17.75 mm
Gullwing
×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
2.80 mm MAX
0.82 g
Code
(Reference)
P-SOP28-8.6×17.75-1.27
(FPT-28P-M17)
28-pin plastic SOP
(FPT-28P-M17)
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
*117.75 +–00..2205 .699 –+..000180
0.17 +–00..0043
.007 +–..000021
28
15
11.80 0.30
(.465 .012)
*28.60 0.20
(.339 .008)
INDEX
Details of "A" part
2.65 0.15
(.104 .006)
(Mounting height)
0.25(.010)
1
14
"A"
0~8°
1.27(.050)
0.47 0.08
(.019 .003)
M
0.13(.005)
0.80 0.20
(.031 .008)
0.20 0.15
(.008 .006)
(Stand off)
0.88 0.15
(.035 .006)
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F28048S-c-3-6
(Continued)
DS07-12621-3E
63
MB95130MB Series
(Continued)
30-pin plastic SSOP
Lead pitch
0.65 mm
5.60 × 9.70 mm
Gullwing
Package width
package length
×
Lead shape
Sealing method
Plastic mold
Mounting height
1.45 mm MAX
P-SSOP30-5.6×9.7-0.65
Code
(Reference)
(FPT-30P-M02)
30-pin plastic SSOP
(FPT-30P-M02)
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
1 9.70 0.10(.382 .004)
*
0.17 0.03
(.007 .001)
30
16
25.60 0.10
7.60 0.20
(.220 .004) (.299 .008)
*
INDEX
Details of "A" part
1.25 +–00..1200
(Mounting height)
.049 –+..000048
1
15
"A"
0.25(.010)
0.24 –+00..0078
.009 –+..000033
0.65(.026)
0~8°
0.50 0.20
(.020 .008)
0.10 0.10
(.004 .004)
(Stand off)
0.60 0.15
(.024 .006)
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F30003S-c-3-6
64
DS07-12621-3E
MB95130MB Series
■ MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
■ FEATURES
Change Results
Added “• Power-on reset”.
2
4
■ PRODUCT LINEUP
Added the parameter “Power-on reset”.
Changed the reset output of MB95136MB.
Yes → Not selectable
29
■ ELECTRICAL
Changed the maximum rating of the operating temperature.
CHARACTERISTICS
1. Absolute Maximum Ratings
85 → 105
40
41
■ ELECTRICAL
Added MB95136MB to the part numbers in “• Operating voltage -
CHARACTERISTICS
4. AC Characteristics
(2) Source Clock / Machine Clock
Operating frequency”.
Changed the x-axis of the graph in “ • Main PLL operation fre-
quency”.
Machine clock frequency (FMP) → Main oscillation (FCH)
60
■ MASK OPTION
Changed the “Reset output” of the products listed below to “Not
selectable”.
MB95136MB
MB95F133MBS
MB95F133NBS
MB95F133JBS
MB95F134MBS
MB95F134NBS
MB95F134JBS
MB95F136MBS
MB95F136NBS
MB95F136JBS
MB95F133MBW
MB95F133NBW
MB95F133JBW
MB95F134MBW
MB95F134NBW
MB95F134JBW
MB95F136MBW
MB95F136NBW
MB95F136JBW
61
Added the following note.
If the clock supervisor is selected, reset output is always disabled.
DS07-12621-3E
65
MB95130MB Series
MEMO
66
DS07-12621-3E
MB95130MB Series
MEMO
DS07-12621-3E
67
MB95130MB Series
FUJITSU SEMICONDUCTOR LIMITED
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Specifications are subject to change without notice. For further information please contact each office.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
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by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
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weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-
ing in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
current levels and other abnormal operating conditions.
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The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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