MB9BF122L_技术文档

MB9B120M Series

32-bit ARM^®Cortex^®-M3 based Microcontroller

MB9BF124K/L/M, MB9BF122K/L/M,

MB9BF121K/L/M

Data Sheet (Full Production)

Notice to Readers: This document states the current technical specifications regarding the Spansion

product(s) described herein. Spansion Inc. deems the products to have been in sufficient production

volume such that subsequent versions of this document are not expected to change. However,

typographical or specification corrections, or modifications to the valid combinations offered may occur.

Publication Number MB9B120M_DS706-00050

Revision 3.0

Issue Date March 18, 2015

D a t a S h e e t

Notice On Data Sheet Designations

Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers

of product information or intended specifications throughout the product life cycle, including development,

qualification, initial production, and full production. In all cases, however, readers are encouraged to

verify that they have the latest information before finalizing their design. The following descriptions of

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The Advance Information designation indicates that Spansion Inc. is developing one or more specific

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Spansion Inc. therefore places the following conditions upon Advance Information content:

“This document contains information on one or more products under development at Spansion

Inc. The information is intended to help you evaluate this product. Do not design in this product

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“This document states the current technical specifications regarding the Spansion product(s)

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When a product has been in production for a period of time such that no changes or only nominal

changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes

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those needed to clarify a description or to correct a typographical error or incorrect specification.

Spansion Inc. applies the following conditions to documents in this category:

“This document states the current technical specifications regarding the Spansion product(s)

described herein. Spansion Inc. deems the products to have been in sufficient production

volume such that subsequent versions of this document are not expected to change. However,

typographical or specification corrections, or modifications to the valid combinations offered may

occur.”

Questions regarding these document designations may be directed to your local sales office.

MB9B120M_DS706-00050-3v0-E, March 18, 2015

MB9B120M Series

32-bit ARM^®Cortex^®-M3 based Microcontroller

MB9BF124K/L/M, MB9BF122K/L/M,

MB9BF121K/L/M

Data Sheet (Full Production)

 Description

The MB9B120M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers

with low-power consumption mode and competitive cost.

These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have

peripheral functions such as various timers, ADCs, DACs and Communication Interfaces (UART, CSIO,

I²C, LIN).

The products which are described in this data sheet are placed into TYPE9 product categories in "FM3

Family PERIPHERAL MANUAL".

Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.

Publication Number MB9B120M_DS706-00050

Revision 3.0

Issue Date March 18, 2015

This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient

production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the

valid combinations offered may occur.

D a t a S h e e t

 Features

 32-bit ARM Cortex-M3 Core

 Processor version: r2p1

 Up to 72 MHz Frequency Operation

 Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and

48 peripheral interrupts and 16 priority levels

 24-bit System timer (Sys Tick): System timer for OS task management

 On-chip Memories

[Flash memory]

 Dual operation Flash memory

 Dual Operation Flash memory has the upper bank and the lower bank.

So, this series could implement erase, write and read operations

for each bank simultaneously.

 Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)

 Work area: 32 Kbytes (lower bank)

 Read cycle: 0 wait-cycle

 Security function for code protection

[SRAM]

This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is

connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.

 SRAM0: Up to 16 Kbytes

 SRAM1: Up to 16 Kbytes

 Multi-function Serial Interface (Max eight channels)

 4 channels with 16steps×9-bit FIFO (ch.0/1/3/4), 4 channels without FIFO (ch.2/5/6/7)

 Operation mode is selectable from the followings for each channel.

 UART

 CSIO

 LIN

 I²C

[UART]

 Full duplex double buffer

 Selection with or without parity supported

 Built-in dedicated baud rate generator

 External clock available as a serial clock

 Hardware Flow control : Automatically control the transmission/reception by CTS/RTS (only ch.4)

 Various error detection functions available (parity errors, framing errors, and overrun errors)

[CSIO]

 Full duplex double buffer

 Built-in dedicated baud rate generator

 Overrun error detection function available

[LIN]

 LIN protocol Rev.2.1 supported

 Full duplex double buffer

 Master/Slave mode supported

 LIN break field generation (can be changed to 13 to 16-bit length)

 LIN break delimiter generation (can be changed to 1 to 4-bit length)

 Various error detection functions available (parity errors, framing errors, and overrun errors)

[I²C]

Standard mode (Max 100 kbps) / Fast mode (Max 400 kbps) supported

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 DMA Controller (Eight channels)

The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process

simultaneously.

 8 independently configured and operated channels

 Transfer can be started by software or request from the built-in peripherals

 Transfer address area: 32-bit (4 Gbytes)

 Transfer mode: Block transfer/Burst transfer/Demand transfer

 Transfer data type: byte/half-word/word

 Transfer block count: 1 to 16

 Number of transfers: 1 to 65536

 A/D Converter (Max 26 channels)

[12-bit A/D Converter]

 Successive Approximation type

 Built-in 2units

 Conversion time: 0.8 μs @ 5 V

 Priority conversion available (priority at 2 levels)

 Scanning conversion mode

 Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion:

4 steps)

 D/A Converter (Max two channels)

 R-2R type

 10-bit resolution

 Base Timer (Max eight channels)

Operation mode is selectable from the followings for each channel.

 16-bit PWM timer

 16-bit PPG timer

 16-/32-bit reload timer

 16-/32-bit PWC timer

 General-Purpose I/O Port

This series can use its pins as general-purpose I/O ports when they are not used for peripherals. Moreover,

the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.

 Capable of pull-up control per pin

 Capable of reading pin level directly

 Built-in the port relocate function

 Up to 65 high-speed general-purpose I/O Ports @ 80 pin Package

 Some ports are 5 V tolerant.

See "List of Pin Functions" and "I/O Circuit Type" to confirm the corresponding pins

 Dual Timer (32-/16-bit Down Counter)

The Dual Timer consists of two programmable 32-/16-bit down counters.

Operation mode is selectable from the followings for each channel.

 Free-running

 Periodic (=Reload)

 One-shot

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D a t a S h e e t

 Quadrature Position/Revolution Counter (QPRC) (Max two channels)

The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position

encoder. Moreover, it is possible to use as the up/down counter.

 The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.

 16-bit position counter

 16-bit revolution counter

 Two 16-bit compare registers

 Multi-function Timer

The Multi-function timer is composed of the following blocks.

 16-bit free-run timer × 3ch./unit

 Input capture × 4ch./unit

 Output compare × 6ch./unit

 A/D activation compare × 2ch./unit

 Waveform generator × 3ch./unit

 16-bit PPG timer × 3ch./unit

The following function can be used to achieve the motor control.

 PWM signal output function

 DC chopper waveform output function

 Dead time function

 Input capture function

 A/D convertor activate function

 DTIF (Motor emergency stop) interrupt function

 Real-time clock (RTC)

The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.

 The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of

the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or

Minute.

 Timer interrupt function after set time or each set time.

 Capable of rewriting the time with continuing the time count.

 Leap year automatic count is available.

 Watch Counter

The Watch counter is used for wake up from Sleep and Timer mode.

Interval timer: up to 64s (Max) @ Sub Clock : 32.768 kHz

 External Interrupt Controller Unit

 Up to 23 external interrupt input pins @ 80 pin Package

 Include one non-maskable interrupt (NMI) input pin

 Watchdog Timer (Two channels)

A watchdog timer can generate interrupts or a reset when a time-out value is reached.

This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.

The "Hardware" watchdog timer is clocked by the built-in Low-speed CR oscillator. Therefore, the

"Hardware" watchdog is active in any low-power consumption modes except RTC, Stop, Deep Standby

RTC, Deep Standby Stop modes.

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D a t a S h e e t

 CRC (Cyclic Redundancy Check) Accelerator

The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a

reduction of the integrity check processing load for reception data and storage.

CCITT CRC16 and IEEE-802.3 CRC32 are supported.

 CCITT CRC16 Generator Polynomial: 0x1021

 IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7

 Clock and Reset

[Clocks]

Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).

 Main Clock:

 Sub Clock:

4 MHz to 48 MHz

32.768 kHz

 Built-in High-speed CR Clock: 4 MHz

 Built-in Low-speed CR Clock: 100 kHz

 Main PLL Clock

[Resets]

 Reset requests from INITX pin

 Power-on reset

 Software reset

 Watchdog timers reset

 Low-voltage detection reset

 Clock Super Visor reset

 Clock Super Visor (CSV)

Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.

 If external clock failure (clock stop) is detected, reset is asserted.

 If external frequency anomaly is detected, interrupt or reset is asserted.

 Low-Voltage Detector (LVD)

This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the

voltage that has been set, Low-Voltage Detector generates an interrupt or reset.

 LVD1: error reporting via interrupt

 LVD2: auto-reset operation

 Low-Power Consumption Mode

Six low-power consumption modes supported.

 Sleep

 Timer

 RTC

 Stop

 Deep Standby RTC (selectable between keeping the value of RAM and not)

 Deep Standby Stop (selectable between keeping the value of RAM and not)

 Debug

Serial Wire JTAG Debug Port (SWJ-DP)

 Unique ID

Unique value of the device (41 bits) is set.

 Power Supply

Wide range voltage: VCC = 2.7 V to 5.5 V

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D a t a S h e e t

 Product Lineup

 Memory size

Product name

On-chip

MB9BF121K/L/M

MB9BF122K/L/M

MB9BF124K/L/M

Main area

64 Kbytes

32 Kbytes

128 Kbytes

256 Kbytes

Flash

Work area

32 Kbytes

memory

16 Kbytes

32 Kbytes

SRAM0

SRAM1

Total

8 Kbytes

16 Kbytes

8 Kbytes

16 Kbytes

On-chip

SRAM

 Function

MB9BF121K

MB9BF122K

MB9BF124K

48

MB9BF121L

MB9BF122L

MB9BF124L

64

Cortex-M3

72 MHz

MB9BF121M

MB9BF122M

MB9BF124M

80/96

Product name

Pin count

CPU

Freq.

Power supply voltage range

DMAC

2.7 V to 5.5 V

8ch.

4ch. (Max)

ch.0/1/3: FIFO

ch.5: No FIFO

8ch. (Max)

ch.0/1/3/4 FIFO

ch.2/5/6/7: No FIFO

Multi-function Serial Interface

(UART/CSIO/LIN/I²C)

(In ch.1/5, only UART

and LIN are available.)

(In ch.1, only UART and LIN are available.)

Base Timer

(PWC/Reload timer/PWM/PPG)

8ch. (Max)

A/D activation

compare

2ch.

Input capture

Free-run timer

Output compare

Waveform

generator

4ch.*

3ch.

6ch.

MF-

Timer

1 unit

3ch.

PPG

QPRC

1ch.

2ch. (Max)

Dual Timer

1 unit

Real-Time Clock

Watch Counter

CRC Accelerator

Watchdog timer

1 unit

Yes

1ch. (SW) + 1ch. (HW)

14 pins (Max) +

NMI × 1

35 pins (Max)

14ch. (2 units)

19 pins (Max) +

NMI × 1

50 pins (Max)

23ch. (2 units)

2ch. (Max)

Yes

23 pins (Max) +

NMI × 1

65 pins (Max)

26ch. (2 units)

External Interrupts

I/O ports

12-bit A/D converter

10-bit D/A converter

CSV (Clock Super Visor)

LVD (Low-Voltage Detector)

2ch.

High-speed

Low-speed

4 MHz

Built-in CR

100 kHz

SWJ-DP

Yes

Debug Function

Unique ID

*: The external input channel which can be used is shown as follws.

 ch.0 to ch.3 : MB9BF121M/F122M/F124M

 ch.0, ch.2, ch.3 : MB9BF121K/F122K/F124K, MB9BF121L/F122L/F124L

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MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.

It is necessary to use the port relocate function of the I/O port according to your function use.

See " Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics" for

accuracy of built-in CR.

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

 Packages

MB9BF121K

MB9BF122K

MB9BF124K

MB9BF121L

MB9BF122L

MB9BF124L

MB9BF121M

MB9BF122M

MB9BF124M

-

Product name

Package

LQFP: FPT-48P-M49 (0.5 mm pitch)

QFN: LCC-48P-M73 (0.5 mm pitch)

LQFP: FPT-64P-M38 (0.5 mm pitch)

LQFP: FPT-64P-M39 (0.65 mm pitch)

QFN: LCC-64P-M24 (0.5 mm pitch)

LQFP: FPT-80P-M37 (0.5 mm pitch)

LQFP: FPT-80P-M40 (0.65 mm pitch)

BGA: BGA-96P-M07 (0.5 mm pitch)

-



-

-

-



-

-

-



-

: Supported

Note: See "Package Dimensions" for detailed information on each package.

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MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

 Pin Assignment

 FPT-80P-M37/M40

(TOP VIEW)

VCC

1

2

3

4

5

6

7

8

9

60 P20/INT05_0/CROUT_0/AIN1_1

59 P21/AN14/SIN0_0/INT06_1/BIN1_1/WKUP2

58 P22/AN13/SOT0_0/TIOB7_1/ZIN1_1

57 P23/AN12/SCK0_0/TIOA7_1

56 P1B/AN11/SOT4_1/INT20_2/IC01_1

55 P1A/AN10/SIN4_1/INT05_1/IC00_1

54 P19/AN09/SCK2_2

P50/AN22/INT00_0/AIN0_2/SIN3_1

P51/AN23/INT01_0/BIN0_2/SOT3_1

P52/AN24/INT02_0/ZIN0_2/SCK3_1

P53/SIN6_0/TIOA1_2/INT07_2

P54/SOT6_0/TIOB1_2/INT18_1

P55/SCK6_0/ADTG_1/INT19_1

P56/INT08_2

53 P18/AN08/SOT2_2

P30/AN25/AIN0_0/TIOB0_1/INT03_2

52 AVRL

P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2 10

P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2 11

P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 12

P39/DTTI0X_0/INT06_0/ADTG_2 13

P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 14

P3B/RTO01_0/TIOA1_1 15

51 AVRH

LQFP - 80

50 AVCC

49 P17/AN07/SIN2_2/INT04_1

48 P16/AN06/SCK0_1/INT15_0

47 P15/AN05/SOT0_1/INT14_0/IC03_2

46 P14/AN04/SIN0_1/INT03_1/IC02_2

45 AVSS

P3C/RTO02_0/TIOA2_1/INT18_2 16

P3D/RTO03_0/TIOA3_1 17

44 P12/AN02/SOT1_1/IC00_2

43 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1

42 P10/AN00

P3E/RTO04_0/TIOA4_1/INT19_2 18

P3F/RTO05_0/TIOA5_1 19

VSS 20

41 VCC

<Note>

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated

port number. For these pins, there are multiple pins that provide the same function for the same channel.

Use the extended port function register (EPFR) to select the pin.

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D a t a S h e e t

 FPT-64P-M38/M39

(TOP VIEW)

VCC

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P21/AN14/SIN0_0/INT06_1/WKUP2

P22/AN13/SOT0_0/TIOB7_1

P23/AN12/SCK0_0/TIOA7_1

P19/AN09/SCK2_2

P50/AN22/INT00_0/AIN0_2/SIN3_1

P51/AN23/INT01_0/BIN0_2/SOT3_1

P52/AN24/INT02_0/ZIN0_2/SCK3_1

P30/AN25/AIN0_0/TIOB0_1/INT03_2

P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2

P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2

P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6

P39/DTTI0X_0/INT06_0/ADTG_2

P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2

P3B/RTO01_0/TIOA1_1

3

4

5

P18/AN08/SOT2_2

6

AVRL

7

AVRH

LQFP - 64

8

AVCC

9

P17/AN07/SIN2_2/INT04_1

P15/AN05/SOT0_1/INT14_0/IC03_2

P14/AN04/SIN0_1/INT03_1/IC02_2

AVSS

10

11

12

13

14

15

16

P3C/RTO02_0/TIOA2_1/INT18_2

P3D/RTO03_0/TIOA3_1

P12/AN02/SOT1_1/IC00_2

P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1

P10/AN00

P3E/RTO04_0/TIOA4_1/INT19_2

P3F/RTO05_0/TIOA5_1

VSS

VCC

<Note>

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated

port number. For these pins, there are multiple pins that provide the same function for the same channel.

Use the extended port function register (EPFR) to select the pin.

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D a t a S h e e t

 LCC-64P-M24

(TOP VIEW)

VCC

1

2

3

4

5

6

7

8

9

48 P21/AN14/SIN0_0/INT06_1/WKUP2

47 P22/AN13/SOT0_0/TIOB7_1

46 P23/AN12/SCK0_0/TIOA7_1

45 P19/AN09/SCK2_2

44 P18/AN08/SOT2_2

43 AVRL

P50/AN22/INT00_0/AIN0_2/SIN3_1

P51/AN23/INT01_0/BIN0_2/SOT3_1

P52/AN24/INT02_0/ZIN0_2/SCK3_1

P30/AN25/AIN0_0/TIOB0_1/INT03_2

P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2

P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2

P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6

P39/DTTI0X_0/INT06_0/ADTG_2

42 AVRH

QFN - 64

41 AVCC

40 P17/AN07/SIN2_2/INT04_1

39 P15/AN05/SOT0_1/INT14_0/IC03_2

38 P14/AN04/SIN0_1/INT03_1/IC02_2

37 AVSS

P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 10

P3B/RTO01_0/TIOA1_1 11

P3C/RTO02_0/TIOA2_1/INT18_2 12

P3D/RTO03_0/TIOA3_1 13

36 P12/AN02/SOT1_1/IC00_2

35 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1

34 P10/AN00

P3E/RTO04_0/TIOA4_1/INT19_2 14

P3F/RTO05_0/TIOA5_1 15

VSS 16

33 VCC

<Note>

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated

port number. For these pins, there are multiple pins that provide the same function for the same channel.

Use the extended port function register (EPFR) to select the pin.

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D a t a S h e e t

 FPT-48P-M49

(TOP VIEW)

VCC

1

2

36

P21/AN14/SIN0_0/INT06_1/WKUP2

P22/AN13/SOT0_0/TIOB7_1

P23/AN12/SCK0_0/TIOA7_1

AVRL

P50/AN22/INT00_0/AIN0_2/SIN3_1

P51/AN23/INT01_0/BIN0_2/SOT3_1

P52/AN24/INT02_0/ZIN0_2/SCK3_1

P39/DTTI0X_0/INT06_0/ADTG_2

P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2

P3B/RTO01_0/TIOA1_1

35

34

33

32

31

30

29

28

27

26

25

3

4

5

AVRH

6

AVCC

LQFP - 48

7

P15/AN05/SOT0_1/INT14_0/IC03_2

P14/AN04/SIN0_1/INT03_1/IC02_2

AVSS

P3C/RTO02_0/TIOA2_1/INT18_2

P3D/RTO03_0/TIOA3_1

8

9

P3E/RTO04_0/TIOA4_1/INT19_2

P3F/RTO05_0/TIOA5_1

10

11

12

P12/AN02/SOT1_1/IC00_2

P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1

P10/AN00

VSS

<Note>

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated

port number. For these pins, there are multiple pins that provide the same function for the same channel.

Use the extended port function register (EPFR) to select the pin.

12

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

 LCC-48P-M73

(TOP VIEW)

VCC

1

2

3

4

5

6

7

8

9

36 P21/AN14/SIN0_0/INT06_1/WKUP2

35 P22/AN13/SOT0_0/TIOB7_1

34 P23/AN12/SCK0_0/TIOA7_1

33 AVRL

P50/AN22/INT00_0/AIN0_2/SIN3_1

P51/AN23/INT01_0/BIN0_2/SOT3_1

P52/AN24/INT02_0/ZIN0_2/SCK3_1

P39/DTTI0X_0/INT06_0/ADTG_2

32 AVRH

P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2

P3B/RTO01_0/TIOA1_1

31 AVCC

QFN - 48

30 P15/AN05/SOT0_1/INT14_0/IC03_2

29 P14/AN04/SIN0_1/INT03_1/IC02_2

28 AVSS

P3C/RTO02_0/TIOA2_1/INT18_2

P3D/RTO03_0/TIOA3_1

P3E/RTO04_0/TIOA4_1/INT19_2 10

P3F/RTO05_0/TIOA5_1 11

VSS 12

27 P12/AN02/SOT1_1/IC00_2

26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1

25 P10/AN00

<Note>

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated

port number. For these pins, there are multiple pins that provide the same function for the same channel.

Use the extended port function register (EPFR) to select the pin.

March 18, 2015, MB9B120M_DS706-00050-3v0-E

13

D a t a S h e e t

 BGA-96P-M07

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

TMS/

SWDIO

A

B

C

D

E

F

TRSTX

VSS

VCC

AN22

P53

P81

VSS

AN23

P54

AN25

VSS

P33

P3B

P3E

VSS

C

P80

AN24

VSS

P55

VCC

AN20

AN21

Index

VSS

P63

AN18

P0D

P0E

VSS

AN17

AN16

P07

VSS

TDI

TDO/

SWO

TCK/

SWCLK

AN19

AN15

VSS

AN13

AN11

AN08

AN06

P20

AN14

VSS

AN09

AN12

AN10

P56

AN26

VSS

P39

VSS

P32

AN07 AVRH

AN05 AVRL

G

H

J

P3A

P3D

VCC

VSS

P3C

VSS

X1A

X0A

AN04 AVSS AVCC

P3F

INITX

VSS

P48

P45

P44

P4A

P49

VSS

P4D

P4C

P4B

AN02

P4E

VSS

MD1

X0

AN01

VSS

X1

AN00

VCC

VSS

K

L

MD0

<Note>

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated

port number. For these pins, there are multiple pins that provide the same function for the same channel.

Use the extended port function register (EPFR) to select the pin.

14

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

 List of Pin Functions

 List of pin numbers

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated

port number. For these pins, there are multiple pins that provide the same function for the same channel.

Use the extended port function register (EPFR) to select the pin.

Pin No

I/O circuit Pin state

Pin Name

LQFP-64 LQFP-48

type

LQFP-80

BGA-96

QFN-64

QFN-48

1

B1

1

VCC

P50

-

INT00_0

AIN0_2

SIN3_1

AN22

2

3

C1

C2

2

3

2

3

F

N

P51

INT01_0

BIN0_2

F

N

SOT3_1

(SDA3_1)

AN23

P52

INT02_0

ZIN0_2

4

B3

4

SCK3_1

(SCL3_1)

AN24

P53

SIN6_0

TIOA1_2

INT07_2

P54

5

6

D1

D2

-

E

L

SOT6_0

(SDA6_0)

TIOB1_2

INT18_1

P55

SCK6_0

(SCL6_0)

7

8

9

D3

E1

E2

-

E

F

L

N

ADTG_1

INT19_1

P56

INT08_2

P30

AIN0_0

TIOB0_1

INT03_2

AN25

5

March 18, 2015, MB9B120M_DS706-00050-3v0-E

15

D a t a S h e e t

Pin No

I/O circuit Pin state

Pin Name

LQFP-64

LQFP-48

QFN-48

type

LQFP-80

BGA-96

QFN-64

P31

BIN0_0

TIOB1_1

10

E3

6

-

F

N

SCK6_1

(SCL6_1)

INT04_2

AN26

P32

ZIN0_0

TIOB2_1

11

G1

7

E

L

SOT6_1

(SDA6_1)

INT05_2

P33

INT04_0

TIOB3_1

SIN6_1

ADTG_6

P39

12

13

G2

G3

8

9

-

E

L

DTTI0X_0

INT06_0

ADTG_2

P3A

5

RTO00_0

(PPG00_0)

TIOA0_1

INT07_0

SUBOUT_2

RTCCO_2

P3B

14

H1

10

6

G

L

RTO01_0

(PPG00_0)

15

16

17

H2

H3

J1

11

12

13

7

8

9

G

K

L

TIOA1_1

P3C

RTO02_0

(PPG02_0)

TIOA2_1

INT18_2

P3D

RTO03_0

(PPG02_0)

K

TIOA3_1

16

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

Pin No

I/O circuit Pin state

Pin Name

LQFP-64

QFN-64

LQFP-48

QFN-48

type

LQFP-80

BGA-96

P3E

RTO04_0

(PPG04_0)

18

J2

14

10

G

L

TIOA4_1

INT19_2

P3F

RTO05_0

(PPG04_0)

19

J4

15

11

G

K

TIOA5_1

20

21

L1

L5

16

-

12

-

VSS

P44

TIOA4_0

INT10_0

P45

TIOA5_0

INT11_0

C

-

G

L

22

K5

-

23

24

25

L2

L4

K1

17

-

13

-

VSS

VCC

18

14

P46

26

L3

19

15

D

F

X0A

P47

27

28

K3

K4

20

21

16

17

D

B

G

C

X1A

INITX

P48

29

J5

-

18

-

INT14_1

SIN3_2

P49

E

L

TIOB0_0

INT20_1

DA0_0

30

K6

22

L

SOT3_2

(SDA3_2)

AIN0_1

P4A

TIOB1_0

INT21_1

DA1_0

19

-

31

J6

23

L

SCK3_2

(SCL3_2)

BIN0_1

March 18, 2015, MB9B120M_DS706-00050-3v0-E

17

D a t a S h e e t

Pin No

LQFP-64 LQFP-48

I/O circuit Pin state

Pin Name

type

LQFP-80

BGA-96

QFN-64

QFN-48

P4B

TIOB2_0

INT22_1

IGTRG_0

ZIN0_1

P4C

32

L7

24

-

E

L

TIOB3_0

SCK7_1

(SCL7_1)

33

K7

25

-

I*

L

INT12_0

AIN1_2

P4D

TIOB4_0

SOT7_1

(SDA7_1)

34

35

J7

26

27

-

I*

L

INT13_0

BIN1_2

P4E

TIOB5_0

INT06_2

SIN7_1

ZIN1_2

MD1

K8

36

37

38

K9

L8

L9

28

29

30

20

21

22

C

K

A

E

D

A

PE0

MD0

X0

PE2

X1

39

L10

31

23

A

F

B

M

N

PE3

40

41

L11

K11

32

33

24

-

VSS

-

VCC

P10

42

J11

34

25

AN00

P11

AN01

SIN1_1

INT02_1

FRCK0_2

WKUP1

P12

43

J10

35

26

AN02

44

J8

36

27

F

M

SOT1_1

(SDA1_1)

IC00_2

18

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

Pin No

I/O circuit Pin state

Pin Name

LQFP-64 LQFP-48

type

LQFP-80

BGA-96

QFN-64

QFN-48

45

H10

37

28

AVSS

P14

-

AN04

INT03_1

IC02_2

SIN0_1

P15

46

47

H9

38

39

29

30

F

N

AN05

IC03_2

G10

F

N

SOT0_1

(SDA0_1)

INT14_0

P16

AN06

48

49

G9

-

F

N

SCK0_1

(SCL0_1)

INT15_0

P17

AN07

SIN2_2

INT04_1

AVCC

AVRH

AVRL

P18

F10

40

50

51

52

H11

F11

G11

41

42

43

31

32

33

-

AN08

53

54

F9

44

45

-

F

M

SOT2_2

(SDA2_2)

P19

AN09

E11

SCK2_2

(SCL2_2)

P1A

AN10

55

E10

-

SIN4_1

INT05_1

IC00_1

F

N

March 18, 2015, MB9B120M_DS706-00050-3v0-E

19

D a t a S h e e t

Pin No

LQFP-64 LQFP-48

I/O circuit Pin state

Pin Name

type

LQFP-80

BGA-96

QFN-64

QFN-48

P1B

AN11

SOT4_1

(SDA4_1)

56

E9

D10

D9

-

F

N

IC01_1

INT20_2

P23

SCK0_0

(SCL0_0)

57

58

46

34

F

M

TIOA7_1

AN12

P22

SOT0_0

(SDA0_0)

47

-

35

-

TIOB7_1

AN13

ZIN1_1

P21

SIN0_0

INT06_1

WKUP2

BIN1_1

AN14

P20

59

60

C11

C10

48

36

F

E

N

INT05_0

CROUT_0

AIN1_1

P00

-

61

62

63

64

A10

B9

49

50

51

52

37

38

39

40

E

J

TRSTX

P01

TCK

SWCLK

P02

B11

A9

TDI

P03

TMS

SWDIO

P04

65

66

B8

A8

53

-

41

-

TDO

E

J

SWO

P07

ADTG_0

INT23_1

L

20

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

Pin No

I/O circuit Pin state

Pin Name

LQFP-64 LQFP-48

type

LQFP-80

BGA-96

QFN-64

QFN-48

P0A

SIN4_0

INT00_2

AN15

67

C8

54

-

J*

N

P0B

SOT4_0

(SDA4_0)

68

69

C7

B7

55

56

-

J*

N

TIOB6_1

AN16

INT18_0

P0C

SCK4_0

(SCL4_0)

TIOA6_1

INT19_0

AN17

P0D

RTS4_0

TIOA3_2

INT20_0

P0E

70

71

B6

C6

-

E

L

CTS4_0

TIOB3_2

INT21_0

P0F

NMIX

SUBOUT_0

CROUT_1

RTCCO_0

WKUP0

AN18

72

A6

57

42

F

I

P63

73

74

B5

C5

-

E

F

L

INT03_0

P62

SCK5_0

(SCL5_0)

58

M

ADTG_3

AN19

P61

SOT5_0

(SDA5_0)

75

B4

59

43

F

M

TIOB2_2

DTTI0X_2

AN20

March 18, 2015, MB9B120M_DS706-00050-3v0-E

21

D a t a S h e e t

Pin No

LQFP-64

I/O circuit Pin state

Pin Name

LQFP-48

QFN-48

type

LQFP-80

BGA-96

QFN-64

P60

SIN5_0

TIOA2_2

INT15_1

WKUP3

IGTRG_1

AN21

76

C4

60

44

J*

N

77

78

A4

A3

61

62

45

46

VCC

-

P80

H

INT16_1

P81

79

80

A2

A1

63

64

47

48

INT17_1

VSS

-

A5, A7, A11,

B2, B10, C3,

C9, F1, F2,

F3, J3, J9, K2,

K10, L6

-

VSS

*: 5 V tolerant I/O

22

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

 List of functions

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated

port number. For these pins, there are multiple pins that provide the same function for the same channel.

Use the extended port function register (EPFR) to select the pin.

Pin No

function

Pin name

Function description

LQFP-64 LQFP-48

QFN-64 QFN-48

LQFP-80 BGA-96

ADC

ADTG_0

ADTG_1

66

7

A8

D3

G3

C5

G2

J11

J10

J8

H9

G10

G9

F10

F9

-

9

58

8

34

35

36

38

39

-

40

44

45

-

5

-

25

26

27

29

30

-

ADTG_2 A/D converter external trigger input pin

13

74

12

42

43

44

46

47

48

49

53

54

55

56

57

58

59

67

68

69

72

74

75

76

2

ADTG_3

ADTG_6

AN00

AN01

AN02

AN04

AN05

AN06

AN07

AN08

AN09

AN10

AN11

AN12

AN13

AN14

AN15

AN16

AN17

AN18

AN19

AN20

AN21

AN22

AN23

AN24

AN25

AN26

-

E11

E10

E9

-

D10

D9

C11

C8

C7

B7

A6

C5

B4

C4

C1

C2

B3

E2

46

47

48

54

55

56

57

58

59

60

2

34

35

36

-

42

-

43

44

2

A/D converter analog input pin.

ANxx describes ADC ch.xx.

3

4

9

10

3

4

5

6

3

4

-

E3

March 18, 2015, MB9B120M_DS706-00050-3v0-E

23

D a t a S h e e t

Pin No

LQFP-64 LQFP-48

function

Pin name

Function description

LQFP-80 BGA-96

QFN-64 QFN-48

Base Timer

0

TIOA0_1

TIOB0_0

TIOB0_1

TIOA1_1

TIOA1_2

TIOB1_0

TIOB1_1

TIOB1_2

TIOA2_1

TIOA2_2

TIOB2_0

TIOB2_1

TIOB2_2

TIOA3_1

TIOA3_2

TIOB3_0

TIOB3_1

TIOB3_2

TIOA4_0

TIOA4_1

TIOB4_0

TIOA5_0

TIOA5_1

TIOB5_0

TIOA6_1

TIOB6_1

TIOA7_1

TIOB7_1

Base timer ch.0 TIOA pin

Base timer ch.0 TIOB pin

14

30

9

15

5

31

10

6

H1

K6

E2

H2

D1

J6

E3

D2

H3

C4

L7

G1

B4

J1

B6

K7

G2

C6

L5

J2

10

22

5

11

-

23

6

-

12

60

24

7

59

13

-

25

8

-

6

18

-

7

-

19

-

8

44

-

43

9

-

10

-

Base Timer

1

Base timer ch.1 TIOA pin

Base timer ch.1 TIOB pin

Base timer ch.2 TIOA pin

Base timer ch.2 TIOB pin

Base timer ch.3 TIOA pin

Base timer ch.3 TIOB pin

Base Timer

2

16

76

32

11

75

17

70

33

12

71

21

18

34

22

19

35

69

68

57

58

Base Timer

3

Base Timer

4

-

Base timer ch.4 TIOA pin

Base timer ch.4 TIOB pin

Base timer ch.5 TIOA pin

14

26

-

15

27

56

55

46

47

J7

K5

J4

K8

B7

C7

D10

D9

Base Timer

5

-

11

-

Base timer ch.5 TIOB pin

Base timer ch.6 TIOA pin

Base timer ch.6 TIOB pin

Base timer ch.7 TIOA pin

Base timer ch.7 TIOB pin

Serial wire debug interface clock input

Base Timer

6

Base Timer

7

Debugger

34

35

SWCLK

SWDIO

62

64

B9

A9

50

52

38

40

Serial wire debug interface data input /

output pin

SWO

TCK

TDI

TDO

TMS

Serial wire viewer output pin

J-TAG test clock input pin

J-TAG test data input pin

J-TAG debug data output pin

J-TAG test mode state input/output pin

J-TAG test reset input pin

65

62

63

65

64

61

B8

B9

B11

B8

A9

A10

53

50

51

53

52

49

41

38

39

41

40

37

TRSTX

24

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

Pin No

LQFP-64 LQFP-48

function

Pin name

Function description

LQFP-80 BGA-96

QFN-64 QFN-48

External

Interrupt

INT00_0

INT00_2

INT01_0

INT02_0

INT02_1

INT03_0

INT03_1

INT03_2

INT04_0

INT04_1

INT04_2

INT05_0

INT05_1

INT05_2

INT06_0

INT06_1

INT06_2

INT07_0

INT07_2

INT08_2

INT10_0

INT11_0

INT12_0

INT13_0

INT14_0

INT14_1

INT15_0

INT15_1

INT16_1

INT17_1

INT18_0

INT18_1

INT18_2

INT19_0

INT19_1

INT19_2

INT20_0

INT20_1

INT20_2

INT21_0

INT21_1

INT22_1

INT23_1

NMIX

2

C1

C8

C2

B3

J10

B5

H9

E2

2

54

3

4

35

-

38

5

8

40

6

-

7

9

48

27

10

-

2

-

3

4

26

-

29

-

External interrupt request 00 input pin

External interrupt request 01 input pin

External interrupt request 02 input pin

67

3

4

43

73

46

9

12

49

10

60

55

11

13

59

35

14

5

External interrupt request 03 input pin

External interrupt request 04 input pin

External interrupt request 05 input pin

G2

F10

E3

P20

E10

G1

G3

C11

K8

H1

D1

E1

-

5

36

-

6

-

External interrupt request 06 input pin

External interrupt request 07 input pin

External interrupt request 08 input pin

External interrupt request 10 input pin

External interrupt request 11 input pin

External interrupt request 12 input pin

External interrupt request 13 input pin

8

21

22

33

34

47

29

48

76

78

79

68

6

L5

K5

K7

J7

G10

J5

G9

C4

A3

A2

C7

D2

H3

C11

D3

J2

B6

K6

E9

C6

J6

L7

A8

A6

-

25

26

39

-

30

-

External interrupt request 14 input pin

External interrupt request 15 input pin

-

60

62

63

55

-

12

56

-

14

-

22

-

44

46

47

-

8

-

10

-

18

-

External interrupt request 16 input pin

External interrupt request 17 input pin

External interrupt request 18 input pin

External interrupt request 19 input pin

16

59

7

18

70

30

56

71

31

32

66

72

External interrupt request 20 input pin

External interrupt request 21 input pin

-

23

24

-

19

-

External interrupt request 22 input pin

External interrupt request 23 input pin

Non-Maskable Interrupt input pin

57

42

March 18, 2015, MB9B120M_DS706-00050-3v0-E

25

D a t a S h e e t

Pin No

LQFP-64 LQFP-48

function

Pin name

Function description

LQFP-80 BGA-96

QFN-64 QFN-48

GPIO

P00

P01

P02

P03

P04

P07

P0A

P0B

P0C

P0D

P0E

P0F

P10

P11

P12

P14

P15

P16

P17

P18

P19

P1A

P1B

P20

P21

P22

P23

P30

P31

P32

P33

P39

P3A

P3B

P3C

P3D

P3E

P3F

61

A10

B9

B11

A9

B8

A8

C8

C7

B7

B6

C6

A6

J11

J10

J8

H9

G10

G9

F10

F9

E11

E10

E9

49

50

51

52

53

-

54

55

56

-

37

38

39

40

41

-

62

63

64

65

66

67

68

69

70

71

72

42

43

44

46

47

48

49

53

54

55

56

60

59

58

57

9

General-purpose I/O port 0

-

57

34

35

36

38

39

-

40

44

45

-

48

47

46

5

6

7

8

9

10

11

12

13

14

15

42

25

26

27

29

30

-

36

35

34

-

5

General-purpose I/O port 1

General-purpose I/O port 2

General-purpose I/O port 3

C10

C11

D9

D10

E2

10

11

12

13

14

15

16

17

18

19

E3

G1

G2

G3

H1

H2

H3

J1

6

7

8

9

10

11

J2

J4

26

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

Pin No

LQFP-64 LQFP-48

function

Pin name

Function description

LQFP-80 BGA-96

QFN-64 QFN-48

GPIO

P44

P45

P46

P47

P48

P49

P4A

P4B

P4C

P4D

P4E

P50

P51

P52

P53

P54

P55

P56

P60

P61

P62

P63

P80

P81

PE0

PE2

PE3

21

22

26

27

29

30

31

32

33

34

35

2

3

4

5

6

7

8

76

75

74

73

78

79

36

38

39

L5

K5

L3

K3

J5

K6

J6

L7

K7

J7

K8

C1

C2

B3

D1

D2

D3

E1

C4

B4

C5

B5

A3

A2

K9

L9

L10

-

15

16

-

18

19

-

2

3

4

-

44

43

-

19

20

-

22

23

24

25

26

27

2

3

4

-

60

59

58

-

62

63

28

30

31

General-purpose I/O port 4

General-purpose I/O port 5

General-purpose I/O port 6

-

46

47

20

22

23

General-purpose I/O port 8

General-purpose I/O port E

March 18, 2015, MB9B120M_DS706-00050-3v0-E

27

D a t a S h e e t

Pin No

LQFP-64 LQFP-48

function

Pin name

Function description

LQFP-80 BGA-96

QFN-64 QFN-48

Multi-

function

Serial

0

SIN0_0

SIN0_1

59

46

C11

H9

48

38

36

29

Multi-function serial interface ch.0

input pin

Multi-function serial interface ch.0

output pin.

SOT0_0

(SDA0_0)

58

47

57

D9

47

39

46

35

30

34

This pin operates as SOT0 when it is

used in a UART/CSIO/LIN (operation

modes 0 to 3) and as SDA0 when it is

used in an I²C (operation mode 4).

Multi-function serial interface ch.0

clock I/O pin.

This pin operates as SCK0 when it is

used in a CSIO (operation mode 2)

and as SCL0 when it is used in an I²C

(operation mode 4).

Multi-function serial interface ch.1

input pin

Multi-function serial interface ch.1

output pin.

SOT0_1

(SDA0_1)

G10

D10

SCK0_0

(SCL0_0)

SCK0_1

(SCL0_1)

48

43

G9

-

Multi-

function

Serial

1

SIN1_1

J10

35

26

SOT1_1

(SDA1_1)

This pin operates as SOT1 when it is

used in a UART/LIN (operation

modes 0,1,3) .

Multi-function serial interface ch.2

input pin

44

49

J8

36

40

27

-

Multi-

function

Serial

2

SIN2_2

F10

Multi-function serial interface ch.2

output pin.

SOT2_2

This pin operates as SOT2 when it is

53

54

F9

44

45

-

(SDA2_2) used in a UART/CSIO/LIN (operation

modes 0 to 3) and as SDA2 when it is

used in an I²C (operation mode 4).

Multi-function serial interface ch.2

clock I/O pin.

SCK2_2

(SCL2_2)

This pin operates as SCK2 when it is

used in a CSIO (operation mode 2)

and as SCL2 when it is used in an I²C

(operation mode 4).

E11

Multi-

function

Serial

3

SIN3_1

SIN3_2

2

29

C1

J5

2

-

2

-

Multi-function serial interface ch.3

input pin

Multi-function serial interface ch.3

output pin.

This pin operates as SOT3 when it is

used in a UART/CSIO/LIN (operation

modes 0 to 3) and as SDA3 when it is

used in an I²C (operation mode 4).

Multi-function serial interface ch.3

clock I/O pin.

This pin operates as SCK3 when it is

used in a CSIO (operation mode 2)

and as SCL3 when it is used in an I²C

(operation mode 4).

SOT3_1

(SDA3_1)

3

30

4

C2

K6

B3

J6

3

-

3

-

SOT3_2

(SDA3_2)

SCK3_1

(SCL3_1)

4

-

4

-

SCK3_2

(SCL3_2)

31

28

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

Pin No

LQFP-64 LQFP-48

function

Pin name

Function description

LQFP-80 BGA-96

QFN-64 QFN-48

Multi-

function

Serial

4

SIN4_0

SIN4_1

67

55

C8

E10

54

-

Multi-function serial interface ch.4

input pin

Multi-function serial interface ch.4

output pin.

This pin operates as SOT4 when it is

used in a UART/CSIO/LIN (operation

modes 0 to 3) and as SDA4 when it is

used in an I²C (operation mode 4).

Multi-function serial interface ch.4

clock I/O pin.

SOT4_0

(SDA4_0)

68

56

C7

E9

55

-

SOT4_1

(SDA4_1)

SCK4_0

(SCL4_0)

This pin operates as SCK4 when it is

used in a CSIO (operation mode 2)

and as SCL4 when it is used in an I²C

(operation mode 4).

69

B7

56

-

Multi-function serial interface ch.4

RTS output pin

Multi-function serial interface ch.4

CTS input pin

Multi-function serial interface ch.5

input pin

RTS4_0

CTS4_0

SIN5_0

70

71

76

B6

C6

C4

-

Multi-

function

Serial

5

60

44

Multi-function serial interface ch.5

output pin.

SOT5_0

This pin operates as SOT5 when it is

75

74

B4

C5

59

58

43

(SDA5_0) used in a UART/CSIO/LIN (operation

modes 0 to 3) and as SDA5 when it is

used in an I²C (operation mode 4).

Multi-function serial interface ch.5

clock I/O pin.

SCK5_0

(SCL5_0)

This pin operates as SCK5 when it is

used in a CSIO (operation mode 2)

and as SCL5 when it is used in an I²C

(operation mode 4).

-

Multi-

function

Serial

6

SIN6_0

SIN6_1

5

12

D1

G2

-

8

-

Multi-function serial interface ch.6

input pin

Multi-function serial interface ch.6

output pin.

SOT6_0

(SDA6_0)

6

11

7

D2

G1

D3

E3

-

7

-

This pin operates as SOT6 when it is

used in a UART/CSIO/LIN (operation

modes 0 to 3) and as SDA6 when it is

used in an I²C (operation mode 4).

Multi-function serial interface ch.6

clock I/O pin.

This pin operates as SCK6 when it is

used in a CSIO (operation mode 2)

and as SCL6 when it is used in an I²C

(operation mode 4).

SOT6_1

(SDA6_1)

SCK6_0

(SCL6_0)

SCK6_1

(SCL6_1)

10

6

March 18, 2015, MB9B120M_DS706-00050-3v0-E

29

D a t a S h e e t

Pin No

LQFP-64 LQFP-48

function

Pin name

Function description

LQFP-80 BGA-96

QFN-64 QFN-48

Multi-

function

Serial

7

Multi-function serial interface ch.7

input pin

Multi-function serial interface ch.7

output pin.

SIN7_1

35

K8

27

-

SOT7_1

This pin operates as SOT7 when it is

34

J7

26

-

(SDA7_1) used in a UART/CSIO/LIN (operation

modes 0 to 3) and as SDA7 when it is

used in an I²C (operation mode 4).

Multi-function serial interface ch.7

clock I/O pin.

SCK7_1

(SCL7_1)

This pin operates as SCK7 when it is

used in a CSIO (operation mode 2)

and as SCL7 when it is used in an I²C

(operation mode 4).

33

K7

25

-

Multi-

function

Timer

0

Input signal of waveform generator to

control outputs RTO00 to RTO05 of

Multi-function timer 0.

16-bit free-run timer ch.0 external

clock input pin

DTTI0X_0

DTTI0X_2

13

75

G3

B4

9

5

59

43

FRCK0_2

43

J10

35

26

IC00_1

IC00_2

IC01_1

IC02_2

IC03_2

55

44

56

46

47

E10

J8

E9

H9

G10

-

36

-

38

39

-

27

-

29

30

16-bit input capture input pin of

Multi-function timer 0.

ICxx describes channel number.

Waveform generator output pin of

Multi-function timer 0.

(PPG00_0) This pin operates as PPG00 when it is

used in PPG0 output mode.

Waveform generator output pin of

Multi-function timer 0.

(PPG00_0) This pin operates as PPG00 when it is

used in PPG0 output mode.

Waveform generator output pin of

Multi-function timer 0.

(PPG02_0) This pin operates as PPG02 when it is

used in PPG0 output mode.

Waveform generator output pin of

Multi-function timer 0.

(PPG02_0) This pin operates as PPG02 when it is

used in PPG0 output mode.

Waveform generator output pin of

Multi-function timer 0.

(PPG04_0) This pin operates as PPG04 when it is

used in PPG0 output mode.

Waveform generator output pin of

Multi-function timer 0.

(PPG04_0) This pin operates as PPG04 when it is

used in PPG0 output mode.

RTO00_0

14

15

16

17

18

19

H1

H2

H3

J1

10

11

12

13

14

15

6

7

RTO01_0

RTO02_0

8

RTO03_0

9

RTO04_0

J2

10

11

RTO05_0

J4

IGTRG_0

IGTRG_1

32

76

L7

C4

24

60

-

44

PPG IGBT mode external trigger input

30

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

Pin No

LQFP-64 LQFP-48

function

Pin name

Function description

QPRC ch.0 AIN input pin

QPRC ch.0 BIN input pin

QPRC ch.0 ZIN input pin

LQFP-80 BGA-96

QFN-64 QFN-48

Quadrature

Position/

Revolution

Counter 0

AIN0_0

AIN0_1

AIN0_2

BIN0_0

BIN0_1

BIN0_2

ZIN0_0

ZIN0_1

ZIN0_2

AIN1_1

AIN1_2

BIN1_1

BIN1_2

ZIN1_1

9

30

2

10

31

3

11

32

4

60

33

59

34

58

35

72

14

72

14

E2

K6

C1

E3

J6

C2

G1

L7

B3

C10

K7

C11

J7

D9

K8

A6

H1

A6

H1

5

22

2

6

23

3

7

24

4

-

25

-

2

-

3

-

4

-

42

6

42

6

Quadrature

Position/

Revolution

Counter 1

QPRC ch.1 AIN input pin

QPRC ch.1 BIN input pin

QPRC ch.1 ZIN input pin

26

-

ZIN1_2

27

57

10

57

10

Real-time

clock

RTCCO_0

RTCCO_2

SUBOUT_0

SUBOUT_2

0.5 seconds pulse output pin of

Real-time clock

Sub clock output pin

Low-Power

Consumption

Mode

Deep standby mode return signal

input pin 0

Deep standby mode return signal

input pin 1

Deep standby mode return signal

input pin 2

Deep standby mode return signal

input pin 3

WKUP0

WKUP1

WKUP2

WKUP3

72

43

59

76

A6

J10

C11

C4

57

35

48

60

42

26

36

44

DAC

DA0

DA1

D/A converter ch.0 analog output pin

D/A converter ch.1 analog output pin

External Reset Input pin.

A reset is valid when INITX="L".

30

31

K6

J6

22

23

18

19

RESET

INITX

28

K4

21

17

March 18, 2015, MB9B120M_DS706-00050-3v0-E

31

D a t a S h e e t

Pin No

LQFP-64 LQFP-48

function

Pin name

MD0

Function description

LQFP-80 BGA-96

QFN-64 QFN-48

Mode

Mode 0 pin.

During normal operation, MD0="L"

must be input. During serial

programming to Flash memory,

MD0="H" must be input.

Mode 1 pin.

37

L8

29

21

MD1

During serial programming to Flash

memory, MD1="L" must be input.

Power supply Pin

GND Pin

36

K9

28

20

POWER

GND

VCC

VSS

1

25

41

77

-

B1

K1

K11

A4

F1

1

18

33

61

-

1

14

-

45

-

VSS

GND Pin

-

F2

-

VSS

GND Pin

-

F3

-

VSS

GND Pin

-

20

-

B2

L1

K2

J3

-

16

-

12

-

VSS

GND Pin

-

L6

-

VSS

GND Pin

24

40

-

L4

-

32

-

24

-

L11

K10

J9

-

VSS

GND Pin

-

B10

C9

-

VSS

GND Pin

-

D11

A11

A7

C3

-

VSS

X0

X0A

X1

GND Pin

-

A5

A1

L9

-

80

38

26

39

27

60

72

64

30

19

31

20

-

48

22

15

23

16

-

CLOCK

Main clock (oscillation) input pin

Sub clock (oscillation) input pin

Main clock (oscillation) I/O pin

Sub clock (oscillation) I/O pin

Built-in high-speed CR-osc clock

output port

L3

L10

K3

C10

A6

X1A

CROUT_0

CROUT_1

57

42

Analog

POWER

A/D converter and D/A converter

analog power supply pin

A/D converter analog reference

voltage input pin

A/D converter and D/A converter

GND pin

A/D converter analog reference

voltage input pin

Power supply stabilization capacity

AVCC

AVRH

AVSS

AVRL

C

50

51

45

52

23

H11

F11

H10

G11

L2

41

42

37

43

17

31

32

28

33

13

Analog

GND

C pin

32

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

 I/O Circuit Type

Type

Circuit

Remarks

A

It is possible to select the main

oscillation / GPIO function

Pull-up

resistor

When the main oscillation is

selected.

 Oscillation feedback resistor

: Approximately 1 MΩ

 With Standby mode control

Digital output

P-ch

X1A

When the GPIO is selected.

 CMOS level output.

 CMOS level hysteresis input

 With pull-up resistor control

 With standby mode control

 Pull-up resistor

N-ch

R

: Approximately 50 kΩ

 I_OH= -4 mA, I_OL= 4 mA

Pull-up resistor control

Digital input

Standby mode control

Clock input

Feedback

resistor

Standby mode control

Digital input

Standby mode control

Pull-up

resistor

R

Digital output

P-ch

N-ch

P-ch

X0A

Digital output

Pull-up resistor control

B

 CMOS level hysteresis input

 Pull-up resistor

: Approximately 50 kΩ

Pull-up resistor

Digital input

March 18, 2015, MB9B120M_DS706-00050-3v0-E

33

D a t a S h e e t

Type

Circuit

Remarks

C

 Open drain output

 CMOS level hysteresis input

Digital input

Digital output

N-ch

D

It is possible to select the sub

oscillation / GPIO function

Pull-up

resistor

When the sub oscillation is

selected.

 Oscillation feedback resistor

: Approximately 5 MΩ

 With Standby mode control

P-ch

Digital output

X1A

When the GPIO is selected.

 CMOS level output.

N-ch

 CMOS level hysteresis input

 With pull-up resistor control

 With standby mode control

 Pull-up resistor

: Approximately 50 kΩ

 I_OH= -4 mA, I_OL= 4 mA

R

Pull-up resistor control

Digital input

Standby mode control

Clock input

Feedback

resistor

Standby mode control

Digital input

Standby mode control

Pull-up

resistor

R

Digital output

P-ch

N-ch

P-ch

X0A

Digital output

Pull-up resistor control

34

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

Type

Circuit

Remarks

E

 CMOS level output

 CMOS level hysteresis input

 With pull-up resistor control

 With standby mode control

 Pull-up resistor

P-ch

: Approximately 50 kΩ

 I_OH= -4 mA, I_OL= 4 mA

 When this pin is used as an

I²C pin, the digital output

P-ch transistor is always off

 +B input is available

Digital output

N-ch

R

Pull-up resistor control

Digital input

Standby mode control

F

 CMOS level output

 CMOS level hysteresis input

 With input control

 Analog input

 With pull-up resistor control

 With standby mode control

 Pull-up resistor

: Approximately 50 kΩ

 I_OH= -4 mA, I_OL= 4 mA

 When this pin is used as an

I²C pin, the digital output

P-ch transistor is always off

 +B input is available

Digital output

P-ch

N-ch

Pull-up resistor control

Digital input

R

Standby mode control

Analog input

Input control

March 18, 2015, MB9B120M_DS706-00050-3v0-E

35

D a t a S h e e t

Type

Circuit

Remarks

G

 CMOS level output

 CMOS level hysteresis input

 With pull-up resistor control

 With standby mode control

 Pull-up resistor

: Approximately 50 kΩ

 I_OH= -12 mA, I_OL= 12 mA

 +B input is available

P-ch

Digital output

N-ch

R

Pull-up resistor control

Digital input

Standby mode control

H

 CMOS level output

 CMOS level hysteresis input

 With standby mode control

 I_OH= -18 mA, I_OL= 16.5 mA

P-ch

Digital output

N-ch

R

Digital input

Standby mode control

36

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

Type

Circuit

Remarks

 CMOS level output

 CMOS level hysteresis input

 5 V tolerant

I

 With pull-up resistor control

 With standby mode control

 Pull-up resistor

: Approximately 50 kΩ

 I_OH= -4 mA, I_OL= 4 mA

 Available to control PZR

registers.

 When this pin is used as an

I²C pin, the digital output

P-ch transistor is always off

P-ch

Digital output

N-ch

R

Pull-up resistor control

Digital input

Standby mode control

J

 CMOS level output

 CMOS level hysteresis input

 With input control

 Analog input

 5 V tolerant

Digital output

P-ch

 With pull-up resistor control

 With standby mode control

 Pull-up resistor

: Approximately 50 kΩ

 I_OH= -4 mA, I_OL= 4 mA

 Available to control PZR

registers.

N-ch

 When this pin is used as an

I²C pin, the digital output

P-ch transistor is always off

Pull-up resistor control

Digital input

R

Standby mode control

Analog input

Input control

K

CMOS level hysteresis input

Mode input

March 18, 2015, MB9B120M_DS706-00050-3v0-E

37

D a t a S h e e t

Type

Circuit

Remarks

L

 CMOS level output

 CMOS level hysteresis input

 With input control

 Analog output

P-ch

Digital output

 With pull-up resistor control

 With standby mode control

 Pull-up resistor

: Approximately 50 kΩ

 I_OH= -4 mA, I_OL= 4 mA

N-ch

Digital output

Pull-up resistor control

Digital input

R

Standby mode Control

Analog output

38

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

 Handling Precautions

Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly

affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This

page describes precautions that must be observed to minimize the chance of failure and to obtain higher

reliability from your Spansion semiconductor devices.

1. Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices.

 Absolute Maximum Ratings

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,

etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.

 Recommended Operating Conditions

Recommended operating conditions are normal operating ranges for the semiconductor device. All the

device's electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside these

ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data

sheet. Users considering application outside the listed conditions are advised to contact their sales

representative beforehand.

 Processing and Protection of Pins

These precautions must be followed when handling the pins which connect semiconductor devices to power

supply and input/output functions.

(1) Preventing Over-Voltage and Over-Current Conditions

Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause

deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to

prevent such overvoltage or over-current conditions at the design stage.

(2) Protection of Output Pins

Shorting of output pins to supply pins or other output pins, or connection to large capacitance can

cause large current flows. Such conditions if present for extended periods of time can damage the

device.

Therefore, avoid this type of connection.

(3) Handling of Unused Input Pins

Unconnected input pins with very high impedance levels can adversely affect stability of operation.

Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.

 Latch-up

Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When

subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may

be formed, causing large current levels in excess of several hundred mA to flow continuously at the power

supply pin. This condition is called latch-up.

CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but

can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the

following:

(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should

include attention to abnormal noise, surge levels, etc.

(2) Be sure that abnormal current flows do not occur during the power-on sequence.

Code: DS00-00004-3E

March 18, 2015, MB9B120M_DS706-00050-3v0-E

39

D a t a S h e e t

 Observance of Safety Regulations and Standards

Most countries in the world have established standards and regulations regarding safety, protection from

electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards

in the design of products.

 Fail-Safe Design

Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,

damage or loss from such failures by incorporating safety design measures into your facility and equipment

such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating

conditions.

 Precautions Related to Usage of Devices

Spansion semiconductor devices are intended for use in standard applications (computers, office automation

and other office equipment, industrial, communications, and measurement equipment, personal or

household devices, etc.).

CAUTION: Customers considering the use of our products in special applications where failure or

abnormal operation may directly affect human lives or cause physical injury or property damage, or where

extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea

floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult

with sales representatives before such use. The company will not be responsible for damages arising from

such use without prior approval.

2. Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance

during soldering, you should only mount under Spansion's recommended conditions. For detailed

information about mount conditions, contact your sales representative.

 Lead Insertion Type

Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct

soldering on the board, or mounting by using a socket.

Direct mounting onto boards normally involves processes for inserting leads into through-holes on the

board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the

soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for

storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.

If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can

lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment

of socket contacts and IC leads be verified before mounting.

 Surface Mount Type

Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are

more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in

increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.

You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has

established a ranking of mounting conditions for each product. Users are advised to mount packages in

accordance with Spansion ranking of recommended conditions.

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MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

 Lead-Free Packaging

CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic

soldering, junction strength may be reduced under some conditions of use.

 Storage of Semiconductor Devices

Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions

will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed

moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,

do the following:

(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.

Store products in locations where temperature changes are slight.

(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at

temperatures between 5°C and 30°C.

When you open Dry Package that recommends humidity 40% to 70% relative humidity.

(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum

laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags

for storage.

(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.

 Baking

Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion

recommended conditions for baking.

Condition: 125°C/24 h

 Static Electricity

Because semiconductor devices are particularly susceptible to damage by static electricity, you must take

the following precautions:

(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus

for ion generation may be needed to remove electricity.

(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.

(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high

resistance (on the level of 1 MΩ).

Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to

minimize shock loads is recommended.

(4) Ground all fixtures and instruments, or protect with anti-static measures.

(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board

assemblies.

March 18, 2015, MB9B120M_DS706-00050-3v0-E

41

D a t a S h e e t

3. Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described

above.

For reliable performance, do the following:

(1) Humidity

Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high

humidity levels are anticipated, consider anti-humidity processing.

(2) Discharge of Static Electricity

When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal

operation. In such cases, use anti-static measures or processing to prevent discharges.

(3) Corrosive Gases, Dust, or Oil

Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will

adversely affect the device. If you use devices in such conditions, consider ways to prevent such

exposure or to protect the devices.

(4) Radiation, Including Cosmic Radiation

Most devices are not designed for environments involving exposure to radiation or cosmic radiation.

Users should provide shielding as appropriate.

(5) Smoke, Flame

CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible

substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.

Customers considering the use of Spansion products in other special environmental conditions should

consult with sales representatives.

Please check the latest handling precautions at the following URL.

http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf

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D a t a S h e e t

 Handling Devices

 Power supply pins

In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected

within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be

connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,

to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the

total output current rating.

Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low

impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass

capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin, between

AVRH pin and AVRL pin near this device.

 Stabilizing power supply voltage

A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is

within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage

stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at

the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended

operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary

fluctuation on switching the power supply.

 Crystal oscillator circuit

Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit

board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as

close to the device as possible.

It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins

are surrounded by ground plane as this is expected to produce stable operation.

Evaluate oscillation of your using crystal oscillator by your mount board.

 Sub crystal oscillator

This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to

fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.

・ Surface mount type

Size : More than 3.2 mm × 1.5 mm

Load capacitance : Approximately 6 pF to 7 pF

・

Lead type

Load capacitance : Approximately 6 pF to 7 pF

March 18, 2015, MB9B120M_DS706-00050-3v0-E

43

D a t a S h e e t

 Using an external clock

When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input

the clock to X0. X1(PE3) can be used as a general-purpose I/O port.

Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock

input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.

• Example of Using an External Clock

Device

X0(X0A)

Set as

Can be used as

general-purpose

I/O ports.

External clock

input

X1(PE3),

X1A (P47)

 Handling when using Multi-function serial pin as I²C pin

If it is using the multi-function serial pin as I²C pins, P-ch transistor of digital output is always disabled.

However, I²C pins need to keep the electrical characteristic like other pins and not to connect to the external

I²C bus system with power OFF.

 C Pin

This series contains the regulator. Be sure to connect a smoothing capacitor (C_S) for the regulator between

the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency

characteristics as a smoothing capacitor.

However, some laminated ceramic capacitors have the characteristics of capacitance variation due to

thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the

specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.

A smoothing capacitor of about 4.7μF would be recommended for this series.

C

Device

C_S

VSS

GND

 Mode pins (MD0)

Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the

pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins

is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for

switching the pin level and rewriting the Flash memory data. It is because of preventing the device

erroneously switching to test mode due to noise.

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D a t a S h e e t

 Notes on power-on

Turn power on/off in the following order or at the same time.

If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.

Turning on : VCC →AVCC → AVRH

Turning off : AVRH → AVCC → VCC

 Serial Communication

There is a possibility to receive wrong data due to the noise or other causes on the serial communication.

Therefore, design a printed circuit board so as to avoid noise.

Consider the case of receiving wrong data due to noise, perform error detection such as by applying a

checksum of data at the end. If an error is detected, retransmit the data.

 Differences in features among the products with different memory sizes and between

Flash memory products and MASK products

The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and

oscillation characteristics among the products with different memory sizes and between Flash memory

products and MASK products are different because chip layout and memory structures are different.

If you are switching to use a different product of the same series, please make sure to evaluate the electric

characteristics.

 Pull-Up function of 5 V tolerant I/O

Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant

I/O.

March 18, 2015, MB9B120M_DS706-00050-3v0-E

45

D a t a S h e e t

 Block Diagram

MB9BF121K/L/M, F122K/L/M, F124K/L/M

TRSTX,TCK,

TDI,TMS

TDO

SRAM0

8/16 Kbytes

SWJ-DP

ROM Table

Cortex-M3ꢀCore

@72MHz(Max)

I

SRAM1

8/16 Kbytes

D

Sys

NVIC

On-Chip Flash

64+32 Kbytes/

128+32 Kbytes/

256+32 Kbytes

Flash I/F

Security

Dual-Timer

WatchDog Timer

(Software)

Clock Reset

Generator

INITX

WatchDog Timer

(Hardware)

DMAC

8ch.

CSV

CLK

Main

X0

X1

Source Clock

PLL

Osc

Sub

Osc

CR

4MHz

CR

100kHz

X0A

X1A

CROUT

AVCC,

AVSS,

AVRH,

AVRL

12-bit A/D Converter

Unit 0

ANxx

Unit 1

Power-On

Reset

ADTGx

10-bit D/A Converter

2units

LVD

LVD Ctrl

DAx

C

Regulator

IRQ-Monitor

Base Timer

16-bit 8ch./

32-bit 4ch.

TIOAx

TIOBx

CRC

Accelerator

AINx

BINx

ZINx

RTCCO_x,

SUBOUT_x

QPRC

2ch.

Real-Time Colck

Watch Counter

A/D Activation

Compare 2ch.

External Interrupt

Controller

16-pin + NMI

INTx

NMIX

16-bit Input Capture

4ch.

IC0x

MD0,

MD1

MODE-Ctrl

16-bit Free-run Timer

3ch.

FRCKx

WKUPx

Deep Standby Ctrl

16-bit Output

Compare 6ch.

P0x,

P1x,

・

GPIO

PIN-Function-Ctrl

DTTI0X

RTO0x

Waveform Generator

3ch.

PFx

SCKx

Multi-Function Serial I/F

8ch.

(with FIFO ch.0/1/3/4)

HW flow control(ch.4)

SINx

16-bit PPG

3ch.

IGTRG_x

SOTx

CTS4

RTS4

Multi-function Timer

 Memory Size

See " Memory size" in "Product Lineup" to confirm the memory size.



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D a t a S h e e t

 Memory Map

 Memory Map (1)

Peripherals Area

0x41FF_FFFF

Reserved

0xFFFF_FFFF

Reserved

0xE010_0000

0xE000_0000

Cortex-M3 Private

Peripherals

0x4006_1000

0x4006_0000

DMAC

Reserved

0x4003_C000

0x4003_B000

0x4003_A000

0x4003_9000

0x4003_8000

RTC

Watch Counter

CRC

0x7000_0000

0x6000_0000

External DeviceArea

Reserved

MFS

Reserved

0x4003_6000

0x4003_5000

0x4003_4000

0x4003_3000

0x4003_2000

0x4003_1000

0x4003_0000

0x4002_F000

0x4002_E000

0x4002_9000

0x4002_8000

0x4002_7000

0x4002_6000

0x4002_5000

0x4002_4000

LVD/DS mode

Reserved

GPIO

0x4400_0000

0x4200_0000

0x4000_0000

0x2400_0000

0x2200_0000

32Mbytes

Bit band alias

Reserved

Int-Req.Read

EXTI

Peripherals

Reserved

CR Trim

Reserved

D/AC

32Mbytes

Bit band alias

Reserved

A/DC

0x2008_0000

0x2000_0000

0x1FF8_0000

SRAM1

SRAM0

QPRC

Base Timer

PPG

Reserved

0x0020_8000

0x0020_0000

0x0010_4000

0x0010_0000

Reserved

Flash(Work area)

Reserved

0x4002_1000

0x4002_0000

See " Memory Map (2)"

for the memory size

details.

Security/CR Trim

MFT unit0

Reserved

Dual Timer

Reserved

0x4001_6000

0x4001_5000

Flash(Main area)

0x4001_3000

0x4001_2000

0x4001_1000

0x4001_0000

SW WDT

HW WDT

0x0000_0000

Clock/Reset

Reserved

Flash I/F

0x4000_1000

0x4000_0000

March 18, 2015, MB9B120M_DS706-00050-3v0-E

47

D a t a S h e e t

 Memory Map (2)

MB9BF124K/L/M

MB9BF122K/L/M

MB9BF121K/L/M

0x2008_0000

Reserved

0x2000_4000

0x2000_0000

0x1FFF_C000

0x0020_8000

0x2000_2000

0x2000_0000

0x1FFF_E000

0x2000_2000

0x2000_0000

0x1FFF_E000

SRAM1

16Kbytes

SRAM1

8Kbytes

SRAM1

8Kbytes

SRAM0

8Kbytes

SRAM0

8Kbytes

SRAM0

16Kbytes

Reserved

0x0020_8000

0x0020_0000

0x0020_8000

0x0020_0000

SA7(8KB)

SA6(8KB)

SA5(8KB)

SA4(8KB)

SA7(8KB)

SA6(8KB)

SA5(8KB)

SA4(8KB)

SA7(8KB)

SA6(8KB)

SA5(8KB)

SA4(8KB)

0x0020_0000

Reserved

0x0010_4000

0x0010_2000

0x0010_0000

0x0010_4000

0x0010_2000

0x0010_0000

0x0010_4000

0x0010_2000

0x0010_0000

CR trimming

Security

CR trimming

Security

CR trimming

Security

Reserved

0x0004_0000

Reserved

SA11(64KB)

SA10(64KB)

Reserved

0x0002_0000

SA9(64KB)

SA8(48KB)

SA9(64KB)

SA8(48KB)

0x0001_0000

0x0000_0000

SA8(48KB)

SA3(8KB)

SA2(8KB)

SA3(8KB)

SA2(8KB)

SA3(8KB)

SA2(8KB)

0x0000_0000

Refer to the programming manual for the detail of Flash main area.

MB9AB40N/A40N/340N/140N/150R,MB9B520M/320M/120M Series Flash Programming Manual

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 Peripheral Address Map

Start address

End address

Bus

Peripherals

0x4000_0000

0x4000_1000

0x4001_0000

0x4001_1000

0x4001_2000

0x4001_3000

0x4001_5000

0x4001_6000

0x4002_0000

0x4002_1000

0x4002_4000

0x4002_5000

0x4002_6000

0x4002_7000

0x4002_8000

0x4002_9000

0x4002_E000

0x4002_F000

0x4003_0000

0x4003_1000

0x4003_2000

0x4003_3000

0x4003_4000

0x4003_5000

0x4003_5800

0x4003_6000

0x4003_8000

0x4003_9000

0x4003_A000

0x4003_B000

0x4003_C000

0x4004_0000

0x4006_0000

0x4006_1000

0x4000_0FFF

Flash Memory I/F register

AHB

0x4000_FFFF

0x4001_0FFF

0x4001_1FFF

0x4001_2FFF

0x4001_4FFF

0x4001_5FFF

0x4001_FFFF

0x4002_0FFF

0x4002_3FFF

0x4002_4FFF

0x4002_5FFF

0x4002_6FFF

0x4002_7FFF

0x4002_8FFF

0x4002_DFFF

0x4002_EFFF

0x4002_FFFF

0x4003_0FFF

0x4003_1FFF

0x4003_2FFF

0x4003_3FFF

0x4003_4FFF

0x4003_57FF

0x4003_5FFF

0x4003_7FFF

0x4003_8FFF

0x4003_9FFF

0x4003_AFFF

0x4003_BFFF

0x4003_FFFF

0x4005_FFFF

0x4006_0FFF

0x41FF_FFFF

Reserved

Clock/Reset Control

Hardware Watchdog timer

Software Watchdog timer

Reserved

APB0

Dual-Timer

Reserved

Multi-function timer unit0

Reserved

PPG

Base Timer

Quadrature Position/Revolution Counter (QPRC)

A/D Converter

APB1

D/A Converter

Reserved

built-in CR trimming

Reserved

External Interrupt

Interrupt Source Check Register

Reserved

GPIO

Reserved

Low-Voltage Detector

APB2 Deep standby mode Controller

Reserved

Multi-function serial Interface

CRC

Watch Counter

Real-time clock

Reserved

AHB

DMAC register

Reserved

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

 Pin Status in Each CPU State

The terms used for pin status have the following meanings.

 INITX=0

This is the period when the INITX pin is the "L" level.

 INITX=1

This is the period when the INITX pin is the "H" level.

 SPL=0

This is the status that the standby pin level setting bit (SPL) in the standby mode control register

(STB_CTL) is set to "0".

 SPL=1

This is the status that the standby pin level setting bit (SPL) in the standby mode control register

(STB_CTL) is set to "1".

 Input enabled

Indicates that the input function can be used.

 Internal input fixed at "0"

This is the status that the input function cannot be used. Internal input is fixed at "L".

 Hi-Z

Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.

 Setting disabled

Indicates that the setting is disabled.

 Maintain previous state

Maintains the state that was immediately prior to entering the current mode.

If a built-in peripheral function is operating, the output follows the peripheral function.

If the pin is being used as a port, that output is maintained.

 Analog input is enabled

Indicates that the analog input is enabled.

 Trace output

Indicates that the trace function can be used.

 GPIO selected

In Deep standby mode, pins switch to the general-purpose I/O port.

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 List of Pin Status

Power-on

Deep standby

RTC mode or Deep

standby STOP mode

state

Return from

Deep

standby

reset or

low-voltage

detection

state

Device Run mode

internal or SLEEP

reset state mode state STOP mode state

Timer mode,

RTC mode, or

INITX

input state

mode state

Function

group

Power

supply

unstable

Power

supply

stable

Power

supply

stable

INITX = 1

-

Power supply stable

Power supply stable Power supply stable

INITX = 1 INITX = 1

-

INITX = 0 INITX = 1 INITX = 1

-

SPL = 0

SPL = 1

SPL = 0

SPL = 1

GPIO

selected

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Maintain

GPIO

Setting

GPIO

selected

disabled

selected

A

Main crystal

oscillator input

pin/

Input

External main

clock input

selected

enabled

GPIO

selected

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Maintain

GPIO

Setting

GPIO

selected

disabled

selected

Hi-Z /

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

External main

clock input

selected

Maintain

Setting

disabled

B

Maintain

Internal

input

state/When state/When state/When state/When state/When state/When

oscillation oscillation oscillation oscillation oscillation oscillation

Hi-Z /

Main crystal

oscillator output

Internal

fixed at

"0"/

stops*¹,

input fixed input fixed

Hi-Z /

at "0"

or Input

enable

Internal

input fixed input fixed input fixed input fixed input fixed input fixed

at "0"

Pull-up /

Input

Pull-up /

Input

Pull-up /

Input

Pull-up /

Input

Pull-up /

Input

Pull-up /

Input

Pull-up /

Input

Pull-up /

Input

Pull-up /

Input

INITX

C

D

input pin

enabled

Mode

Input

input pin

enabled

Mode

Input

input pin

enabled

E

Maintain

Hi-Z /

Input

Hi-Z /

Input

GPIO

Setting

GPIO

selected

disabled

selected

enabled

March 18, 2015, MB9B120M_DS706-00050-3v0-E

51

D a t a S h e e t

Power-on

reset or

low-voltage

detection

state

Deep standby

RTC mode or Deep

standby STOP mode

state

Return from

Deep

standby

Device Run mode

internal or SLEEP

reset state mode state STOP mode state

Timer mode,

RTC mode, or

INITX

input state

mode state

Function

group

Power

supply

unstable

Power

supply

stable

Power

supply

stable

INITX = 1

-

Power supply stable

Power supply stable Power supply stable

INITX = 1 INITX = 1

-

INITX = 0 INITX = 1 INITX = 1

-

SPL = 0

SPL = 1

SPL = 0

SPL = 1

GPIO

selected

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Maintain

GPIO

Setting

GPIO

selected

disabled

selected

F

Sub crystal

oscillator input

pin /

Input

External sub

clock input

selected

enabled

GPIO

selected

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Maintain

GPIO

Setting

GPIO

selected

disabled

selected

Hi-Z /

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

External sub

clock input

selected

Maintain

Setting

disabled

G

Maintain

Internal

input

state/When state/When state/When state/When state/When

Maintain oscillation oscillation oscillation oscillation oscillation

Hi-Z /

Sub crystal

oscillator output

Internal

fixed at

"0"/

stops*²,

input fixed input fixed

Hi-Z /

at "0"

or Input

enable

Internal

input fixed input fixed input fixed input fixed input fixed

at "0"

Maintain

External interrupt

enabled selected

Setting

GPIO

selected

Internal

input fixed

at "0"

disabled

Hi-Z /

Internal

input fixed

at "0"

Maintain

GPIO

H

Hi-Z /

Internal

input fixed

at "0"

selected

Hi-Z /

Input

Hi-Z /

Input

GPIO

Hi-Z

selected

enabled

52

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D a t a S h e e t

Power-on

reset or

low-voltage

detection

state

Deep standby

RTC mode or Deep

standby STOP mode

state

Return from

Deep

standby

Device Run mode

internal or SLEEP

reset state mode state STOP mode state

Timer mode,

RTC mode, or

INITX

input state

mode state

Function

group

Power

supply

unstable

Power

supply

stable

Power

supply

stable

INITX = 1

-

Power supply stable

Power supply stable Power supply stable

INITX = 1 INITX = 1

-

INITX = 0 INITX = 1 INITX = 1

-

SPL = 0

SPL = 1

SPL = 0

SPL = 1

Hi-Z /

Internal

Hi-Z /

Internal

Hi-Z /

Internal

Hi-Z /

Internal

input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed

Analog input

selected

Hi-Z

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

enabled

Maintain

disabled

Setting

I

NMIX selected

disabled

GPIO

Hi-Z /

WKUP

input

selected

Resource other

than above

selected

Maintain

WKUP

input

Hi-Z /

Internal

input fixed

at "0"

Hi-Z /

Input

Hi-Z /

Input

enabled

Hi-Z

Maintain

enabled

GPIO

selected

Pull-up /

Input

Pull-up /

Input

Maintain

JTAG

selected

enabled

Maintain

GPIO

selected

Internal

input fixed

at "0"

J

Hi-Z /

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

GPIO

Setting

GPIO

selected

disabled

selected

Resource selected

GPIO

selected

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Hi-Z /

Input

Hi-Z /

Input

Maintain

GPIO

K

Hi-Z

selected

GPIO

enabled

selected

Analog output

selected

*3

*4

Setting

Maintain

disabled

External interrupt

enabled selected

GPIO

selected

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Maintain

GPIO

L

Maintain

Resource other

than above

selected

Hi-Z /

Internal

input fixed

at "0"

Hi-Z /

Input

Hi-Z /

Input

Hi-Z

enabled

GPIO

selected

March 18, 2015, MB9B120M_DS706-00050-3v0-E

53

D a t a S h e e t

Power-on

reset or

low-voltage

detection

state

Deep standby

RTC mode or Deep

standby STOP mode

state

Return from

Deep

standby

Device Run mode

internal or SLEEP

reset state mode state STOP mode state

Timer mode,

RTC mode, or

INITX

input state

mode state

Function

group

Power

supply

unstable

Power

supply

stable

Power

supply

stable

INITX = 1

-

Power supply stable

Power supply stable Power supply stable

INITX = 1 INITX = 1

-

INITX = 0 INITX = 1 INITX = 1

-

SPL = 0

SPL = 1

SPL = 0

SPL = 1

Hi-Z /

Internal

input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed

Analog input

selected

Hi-Z

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

enabled

M

Resource other

than above

selected

GPIO

selected

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Maintain

Setting

GPIO

disabled

selected

GPIO

selected

Hi-Z /

Internal

input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed

Analog input

selected

Hi-Z

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

at "0" /

Analog

input

enabled

N

Maintain

External interrupt

enabled selected

GPIO

selected

Internal

input fixed

at "0"

Hi-Z /

Internal

input fixed

at "0"

Maintain

Resource other

than above

selected

Setting

GPIO

disabled

selected

Hi-Z /

Internal

input fixed

at "0"

GPIO

selected

*1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep

Standby RTC mode, and Deep Standby Stop mode.

*2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.

*3: Maintain previous state at Timer mode. GPIO selected Internal input fixed at "0" at RTC mode, Stop mode.

*4: Maintain previous state at Timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, Stop mode.

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 Electrical Characteristics

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit Remarks

Min

Max

Power supply voltage*^1,*²

V_CC

AV_CC

AVRH

Vss - 0.5

V_SS- 0.5

V_SS+ 6.5

V_CC+ 0.5

(≤ 6.5 V)

V_SS+ 6.5

AV_CC+ 0.5

(≤ 6.5 V)

V_CC+ 0.5

(≤ 6.5 V)

+2

V

Analog power supply voltage*^1,*³

Analog reference voltage*^1,*³

V_SS- 0.5

V

Input voltage*¹

V_I

V

5 V tolerant

Analog pin input voltage*¹

Output voltage*¹

V_IA

V_O

V_SS- 0.5

-2

V

Clamp maximum current

I_CLAMP

mA *7

Clamp total maximum current

Σ[I_CLAMP

]

+20

10

20

39

4

mA *7

mA 4 mA type

mA 12 mA type

mA P80/P81 pin

mA 4 mA type

mA 12 mA type

mA P80/P81 pin

mA

L level maximum output current*⁴

I_OL

-

L level average output current*⁵

I_OLAV

12

16.5

100

50

L level total maximum output current

L level total average output current*⁶

∑I_OL

∑I_OLAV

-

mA

- 10

- 20

- 39

- 4

- 12

- 18

- 100

- 50

300

+ 150

mA 4 mA type

mA 12 mA type

mA P80/P81 pin

mA 4 mA type

mA 12 mA type

mA P80/P81 pin

mA

mW

°C

H level maximum output current*⁴

I_OH

-

H level average output current*⁵

I_OHAV

H level total maximum output current

H level total average output current*⁶

Power consumption

∑I_OH

∑I_OHAV

P_D

-

Storage temperature

T_STG

- 55

*1: These parameters are based on the condition that V_SS= AV_SS= 0 V.

*2: V_CCmust not drop below V_SS- 0.5 V.

*3: Ensure that the voltage does not exceed V_CC+ 0.5 V, for example, when the power is turned on.

*4: The maximum output current is defined as the value of the peak current flowing through any one of the

corresponding pins.

*5: The average output current is defined as the average current value flowing through any one of the

corresponding pins for a 100 ms period.

*6: The total average output current is defined as the average current value flowing through all of

corresponding pins for a 100 ms period.

March 18, 2015, MB9B120M_DS706-00050-3v0-E

55

D a t a S h e e t

*7:



See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin.

Use within recommended operating conditions.

Use at DC voltage (current) the +B input.

The +B signal should always be applied a limiting resistance placed between the +B signal and the device.

The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the device pin does not exceed rated values, either instantaneously or for prolonged periods.

Note that when the device drive current is low, such as in the low-power consumpsion modes, the +B input

potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and

this may affect other devices.



Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is

provided from the pins, so that incomplete operation may result.

The following is a recommended circuit example (I/O equivalent circuit).

Protection Diode

V_CC

P-ch

Limiting

resistor

Digital output

Digital input

+B input (0V to 16V)

N-ch

R

AV_CC

Analog input

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,

etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

56

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D a t a S h e e t

2. Recommended Operating Conditions

(V_SS= AV_SS= AVRL = 0.0V)

Value

Parameter

Symbol Conditions

Unit

Remarks

Min

Max

5.5

Power supply voltage

Analog power supply voltage

V_CC

AV_CC

AVRH

AVRL

C_S

-

2.7*²

2.7

V

μF

°C

5.5

AV_CC= V_CC

2.7

AV_CC

AV_SS

10

Analog reference voltage

AV_SS

1

Smoothing capacitor

Operating temperature

For Regulator*¹

T_A

- 40

+ 105

*1: See " C Pin" in "Handling Devices" for the connection of the smoothing capacitor.

*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or

more, instruction execution and low voltage detection function by built-in High-speed CR(including Main

PLL is used) or bulit-in Low-speed CR is possible to operate only.

The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure. No warranty is made

with respect to uses, operating conditions, or combinations not represented on the data sheet. Users

considering application outside the listed conditions are advised to contact their representatives beforehand.

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

3. DC Characteristics

(1) Current Rating

(V_CC= AV_CC= 2.7V to 5.5V, V_SS= AV_SS= AVRL = 0V, T_A= - 40°C to + 105°C)

Value

Typ Max

name

Parameter Symbol

Conditions

Unit Remarks

CPU : 72MHz,

Peripheral : 36MHz

32.5

18

41

23

mA *1, *5

PLL

Run mode

CPU:72MHz,

Peripheral clock stops

NOP operation

mA *1, *5

Run

mode

High-speed

CR

CPU/ Peripheral : 4MHz*²

2.5

3.4

mA *1

I_CC

current

Run mode

Sub

Run mode

CPU/ Peripheral : 32kHz

110

980

µA *1, *6

Low-speed

CR

Run mode

PLL

Sleep mode

High-speed

CR

Sleep mode

Sub

VCC

CPU/ Peripheral : 100kHz

Peripheral : 36MHz

Peripheral : 4MHz*²

Peripheral : 32kHz

130

22

1030 µA *1

28

mA *1, *5

1.6

96

2.6

mA *1

Sleep

mode

current

I_CCS

955

975

µA *1, *6

µA *1

Sleep mode

Low-speed

CR

Peripheral : 100kHz

115

Sleep mode

*1: When all ports are fixed.

*2: When setting it to 4 MHz by trimming.

*3: T_A=+25°C, V_CC=5.5 V

*4: T_A=+105°C, V_CC=5.5 V

*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)

*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)

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D a t a S h e e t

(V_CC= AV_CC= 2.7V to 5.5V, V_SS= AV_SS= AVRL = 0V, T_A= - 40°C to + 105°C)

Value

name

Parameter Symbol

Conditions

Unit Remarks

mA *1, *4

μA *1, *5

μA *1

Typ*²Max*²

T_A= + 25°C,

4.1

4.8

5.4

66

When LVD is off

T_A= + 105°C,

Main

I_CCT

Timer mode

-

Timer

mode

current

I_CCT

When LVD is off

T_A= + 25°C,

17

-

When LVD is off

T_A= + 105°C,

Sub

Timer mode

835

61

When LVD is off

T_A= + 25°C,

15

-

RTC

When LVD is off

T_A= + 105°C,

When LVD is off

T_A= + 25°C,

When LVD is off

T_A= + 105°C,

mode

I_CCR

RTC mode

Stop mode

current

680

53

14

-

Stop

mode

current

I_CCH

600

μA *1

When LVD is off

T_A= + 25°C,

When LVD is off,

When RAM is off

T_A= + 25°C,

When LVD is off,

When RAM is on

T_A= + 105°C,

When LVD is off,

When RAM is off

T_A= + 105°C,

When LVD is off,

When RAM is on

T_A= + 25°C,

When LVD is off,

When RAM is off

T_A= + 25°C,

When LVD is off,

When RAM is on

T_A= + 105°C,

2.2

6.2

11

23

μA *1, *3, *5

μA *1, *3

VCC

Deep Standby

RTC mode

I_CCRD

155

215

9.6

22

-

Deep

Standby

mode

current

1.6

5.6

μA *1, *3

Deep Standby

Stop mode

I_CCHD

When LVD is off,

When RAM is off

T_A= + 105°C,

When LVD is off,

When RAM is on

150

210

μA *1, *3

-

μA *1, *3

*1: When all ports are fixed.

*2: V_CC=5.5 V

*3: RAM on/off setting is on-chip SRAM only.

*4: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)

*5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)

March 18, 2015, MB9B120M_DS706-00050-3v0-E

59

D a t a S h e e t

· Low-Voltage Detection Current

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

name

Parameter

Symbol

Conditions

Unit

Remarks

Typ

Max

At operation

for reset

Vcc = 5.5 V

0.13

0.3

μA At not detect

Low-voltage

detection circuit

(LVD) power

supply current

I_CCLVD

VCC

At operation

for interrupt

Vcc = 5.5 V

0.13

0.3

· Flash Memory Current

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

name

Parameter

Symbol

Conditions

Unit

Remarks

Typ

Max

Flash memory

write/erase

current

I_CCFLASH

VCC

At Write/Erase

9.5

11.2

mA

*

*: The current at which to write or erase Flash memory, "I_CCFLASH" is added to "I_CC".

· A/D Converter Current

(V_CC= AV_CC= 2.7V to 5.5V, V_SS= AV_SS= AVRL = 0V, T_A= - 40°C to + 105°C)

Value

Max

name

Parameter

Symbol

Conditions

Unit

mA

μA

Remarks

Typ

At 1unit

operation

0.69

0.90

Power supply

current

I_CCAD

AVCC

AVRH

At stop

0.25

1.1

25.84

At 1unit

operation

AVRH=5.5 V

1.97

3.4

mA

Reference power

supply current

I_CCAVRH

At stop

0.2

μA

· D/A Converter Current

(V_CC= AV_CC= 2.7V to 5.5V, V_SS= AV_SS= 0V, T_A= - 40°C to + 105°C)

Value

Typ

name

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

At 1unit

operation

AV_CC=3.3 V

At 1unit

operation

AV_CC=5.0 V

250

315

380

μA

IDDA*²

IDSA

Power supply

current*¹

AVCC

380

-

475

-

580

16

μA

At stop

*1: No-load

*2: Generates the max current by the CODE about 0x200

60

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

(2) Pin Characteristics

(V_CC= AV_CC= 2.7V to 5.5V, V_SS= AV_SS= AVRL = 0V, T_A= - 40°C to + 105°C)

Value

Typ

Parameter Symbol Pin name

Conditions

Unit Remarks

Min

Max

CMOS

hysteresis

input pin,

MD0, MD1

5V tolerant

input pin

H level input

voltage

(hysteresis

input)

-

V_CC× 0.8

-

V_CC+ 0.3

V

V_IHS

V_CC× 0.8

V_SS- 0.3

-

V_SS+ 5.5

V_CC× 0.2

CMOS

hysteresis

input pin,

MD0, MD1

5 V tolerant

input pin

L level input

voltage

(hysteresis

input)

V_ILS

V_CC≥ 4.5 V,

I_OH= - 4 mA

4 mA type

12 mA type

P80, P81

V_CC- 0.5

V_CC- 0.4

V_SS

-

V_CC

0.4

V

V_CC< 4.5 V,

I_OH= - 2 mA

V_CC≥ 4.5 V,

I_OH= - 12 mA

V_CC< 4.5 V,

I_OH= - 8 mA

V_CC≥ 4.5 V,

I_OH= - 18.0 mA

V_CC< 4.5 V,

I_OH= - 12.0 mA

V_CC≥ 4.5 V,

I_OL= 4 mA

V_CC< 4.5 V,

I_OL= 2 mA

V_CC≥ 4.5 V,

I_OL= 12 mA

V_CC< 4.5 V,

I_OL= 8 mA

H level

output voltage

V_OH

4 mA type

12 mA type

P80, P81

L level

output voltage

V_OL

V_SS

0.4

V_CC≥ 4.5 V,

I_OL= 16.5 mA

V_CC< 4.5 V,

I_OL= 10.5 mA

V_SS

- 5

-

0.4

+ 5

Input leak

current

I_IL

-

μA

kΩ

Pull-up

resistance

value

V_CC≥ 4.5 V

33

-

50

-

90

R_PU

Pull-up pin

V_CC< 4.5 V

180

Other than

VCC,

VSS,

Input

capacitance

C_IN

AVCC,

AVSS,

AVRH,

AVRL

-

5

15

pF

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

4. AC Characteristics

(1) Main Clock Input Characteristics

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

name

Parameter

Input frequency

Input clock cycle

Symbol

Conditions

Unit

Remarks

Min

Max

48

V_CC≥ 4.5 V

V_CC< 4.5 V

V_CC≥ 4.5 V

V_CC< 4.5 V

V_CC≥ 4.5 V

V_CC< 4.5 V

PWH/tCYLH,

PWL/tCYLH

4

When crystal oscillator

is connected

When using external

Clock

When using external

Clock

When using external

Clock

MHz

ns

20

48

20

250

f_CH

20.83

50

X0,

X1

t_CYLH

-

Input clock pulse

width

45

55

%

Input clock rising

time and falling

time

t_CF,

t_CR

When using external

Clock

-

5

ns

f_CM

f_CC

-

72

MHz Master clock

Base clock

(HCLK/FCLK)

MHz

Internal operating

clock frequency^*1

f_CP0

f_CP1

f_CP2

-

40

MHz APB0 bus clock*²

MHz APB1 bus clock*²

MHz APB2 bus clock*²

Base clock

t_CYCC

-

13.8

-

ns

(HCLK/FCLK)

Internal operating

clock cycle time^*1

t_CYCP0

t_CYCP1

t_CYCP2

-

25

-

ns

APB0 bus clock*²

APB1 bus clock*²

APB2 bus clock*²

*1: For more information about each internal operating clock, see "Chapter 2-1:Clock" in "FM3 Family

PERIPHERAL MANUAL".

*2: For about each APB bus which each peripheral is connected to, see "Block Diagram" in this data sheet.

X0

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MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

(2) Sub Clock Input Characteristics

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

Typ

name

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

When crystal

-

32.768

-

kHz oscillator is

connected

Input frequency

1/ t_CYLL

When using

external clock

When using

external clock

When using

external clock

-

32

10

45

-

100

31.25

55

kHz

X0A,

X1A

Input clock cycle

t_CYLL

-

μs

Input clock pulse

width

PWH/tCYLL,

PWL/tCYLL

%

*: See " Sub crystal oscillator" in "Handling Devices" for the crystal oscillator used.

X0A

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(3) Built-in CR Oscillation Characteristics

 Built-in High-speed CR

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

Min Typ Max

Parameter

Symbol

Conditions

Unit

Remarks

T_A= + 25°C

3.92

3.9

4

4.08

T_A= 0°C to + 85°C

4

4.1

T_A= -40°C to + 105°C 3.88

4.12

When trimming*¹

T_A= + 25°C

3.94

Clock frequency

f_CRH

4.06 MHz

V_CC≤ 3.6 V

T_A= - 20°C to + 85°C

V_CC≤ 3.6 V

T_A= - 20°C to + 105°C

3.92

4

-

4.08

4.1

3.9

V_CC≤ 3.6 V

T_A= - 40°C to + 105°C

-

2.8

-

5.2

When not trimming

Frequency

stabilization time

2

t_CRWT

30

μs

*

*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature

trimming.

*2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value.

This period is able to use high-speed CR clock as source clock.

 Built-in Low-speed CR

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

Typ Max

Parameter

Symbol

Conditions

Unit

Remarks

Min

Clock frequency

f_CRL

-

50

100

150

kHz

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(4-1) Operating Conditions of Main PLL (In the case of using main clock for input of PLL)

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Unit

Remarks

Min Typ Max

PLL oscillation stabilization wait time*¹

(LOCK UP time)

t_LOCK

100

-

μs

PLL input clock frequency

PLL multiplication rate

f_PLLI

-

f_PLLO

f_CLKPLL

4

5

75

-

16

MHz

37 multiplier

150

72

PLL macro oscillation clock frequency

MHz

Main PLL clock frequency*²

*1: Time from when the PLL starts operating until the oscillation stabilizes.

*2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM3 Family

PERIPHERAL MANUAL".

(4-2) Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock

of Main PLL)

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Unit

Remarks

Min Typ Max

PLL oscillation stabilization wait time*¹

(LOCK UP time)

t_LOCK

100

-

μs

PLL input clock frequency

PLL multiplication rate

f_PLLI

-

f_PLLO

f_CLKPLL

3.8

19

72

-

4

-

4.2

MHz

35 multiplier

150

72

PLL macro oscillation clock frequency

MHz

Main PLL clock frequency*²

-

*1: Time from when the PLL starts operating until the oscillation stabilizes.

*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family

PERIPHERAL MANUAL".

Note: Make sure to input to the Main PLL source clock, the high-speed CR clock (CLKHC) that the

frequency/temperature has been trimmed.

When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account

and prevent the master clock from exceeding the maximum frequency.

Main PLL connection

Main PLL

clock

(CLKPLL)

PLL input

clock

PLL macro

oscillation clock

K

M

divider

Main

PLL

divider

N

divider

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

(5) Reset Input Characteristics

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

name

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

Reset input time

t_INITX

INITX

-

500

-

ns

(6) Power-on Reset Timing

Parameter

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

name

Symbol

Unit

Remarks

Min

0

Max

Power supply rising time

t_VCCR

t_OFF

-

ms

Power supply shut down time

1

VCC

Time until releasing

Power-on reset

t_PRT

1.34

18.6

ms

VCC_minimum

VDH_minimum

VCC

0.2V

t_VCCR

t_PRT

t_OFF

Internal reset

Reset active

Release

start

CPU Operation

Glossary

 VCC_minimum : Minimum V_CCof recommended operating conditions

 VDH_minimum : Minimum detection voltage (when SVHR=00000) of Low-Voltage detection reset

See "7. Low-Voltage Detection Characteristics"

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D a t a S h e e t

(7) Base Timer Input Timing

 Timer input timing

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Pin name Conditions

Unit Remarks

Min

Max

TIOAn/TIOBn

(when using as

ECK, TIN)

t_TIWH

t_TIWL

,

Input pulse width

-

2t_CYCP

-

ns

t_TIWH

t_TIWL

ECK

TIN

V_IHS

V_ILS

 Trigger input timing

Parameter

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

Symbol Pin name Conditions

Unit Remarks

Min

Max

TIOAn/TIOBn

(when using as

TGIN)

t_TRGH

t_TRGL

,

Input pulse width

-

2t_CYCP

-

ns

t_TRGH

t_TRGL

V_IHS

TGIN

V_ILS

Note: t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which the Base Timer is connected to, see "Block Diagram" in this data

sheet.

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D a t a S h e e t

(8) CSIO/UART Timing

 CSIO (SPI = 0, SCINV = 0)

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

V_CC< 4.5 V

V_CC≥ 4.5 V

Parameter

Serial clock cycle time

SCK ↓ → SOT delay time

Symbol

Conditions

Unit

ns

name

SCKx

SCKx,

SOTx

SCKx,

SINx

Min

Max

Min

Max

t_SCYC

4t_CYCP

-

4t_CYCP

-

t_SLOVI

- 30

50

0

+ 30

- 20

30

0

+ 20

ns

Master mode

SIN → SCK ↑ setup time

SCK ↑ → SIN hold time

Serial clock L pulse width

Serial clock H pulse width

SCK ↓ → SOT delay time

SIN → SCK ↑ setup time

SCK ↑ → SIN hold time

t_IVSHI

t_SHIXI

t_SLSH

-

ns

SCKx,

SINx

2t_CYCP

10

-

2t_CYCP

10

-

SCKx

-

t_CYCP

10

+

t_CYCP

10

+

t_SHSL

-

SCKx,

SOTx

SCKx,

SINx

SCKx,

SINx

t_SLOVE

t_IVSHE

t_SHIXE

-

50

-

30

-

Slave mode

10

20

10

20

-

SCK falling time

SCK rising time

t_F

t_R

SCKx

-

5

-

5

ns

Notes:  The above characteristics apply to CLK synchronous mode.

 t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which Multi-function serial is connected to, see "Block Diagram" in

this data sheet.

 These characteristics only guarantee the same relocate port number.

For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.

 When the external load capacitance C_L= 30 pF.

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D a t a S h e e t

t_SCYC

V_OH

SCK

SOT

V_OL

t_SLOVI

V_OH

V_OL

t_IVSHI

t_SHIXI

V_IH

V_IL

V_IH

V_IL

SIN

Master mode

t_SLSH

t_SHSL

V_IH

t_R

V_IH

t_F

V_IH

SCK

V_IL

t_SLOVE

V_OH

V_OL

SOT

SIN

t_IVSHE

t_SHIXE

V_IH

V_IL

V_IH

V_IL

Slave mode

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

 CSIO (SPI = 0, SCINV = 1)

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

V_CC< 4.5 V

V_CC≥ 4.5 V

Parameter

Serial clock cycle time

SCK ↑ → SOT delay time

Symbol

Conditions

Unit

ns

name

SCKx

SCKx,

SOTx

SCKx,

SINx

Min

Max

Min

Max

t_SCYC

4t_CYCP

-

4t_CYCP

-

t_SHOVI

- 30

50

0

+ 30

- 20

30

0

+ 20

ns

Master mode

SIN → SCK ↓ setup time

SCK ↓ → SIN hold time

Serial clock L pulse width

Serial clock H pulse width

SCK ↑ → SOT delay time

SIN → SCK ↓ setup time

SCK ↓ → SIN hold time

t_IVSLI

t_SLIXI

t_SLSH

-

ns

SCKx,

SINx

2t_CYCP

10

-

2t_CYCP

10

-

SCKx

-

t_CYCP

10

+

t_CYCP

10

+

t_SHSL

-

SCKx,

SOTx

SCKx,

SINx

SCKx,

SINx

t_SHOVE

t_IVSLE

t_SLIXE

-

50

-

30

-

Slave mode

10

20

10

20

-

SCK falling time

SCK rising time

t_F

t_R

SCKx

-

5

-

5

ns

Notes:  The above characteristics apply to CLK synchronous mode.

 t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which Multi-function serial is connected to, see "Block Diagram" in

this data sheet.

 These characteristics only guarantee the same relocate port number.

For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.

 When the external load capacitance C_L= 30 pF.

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D a t a S h e e t

t_SCYC

V_OH

SCK

V_OL

t_SHOVI

V_OH

V_OL

SOT

SIN

t_IVSLI

t_SLIXI

V_IH

V_IL

V_IH

V_IL

Master mode

t_SHSL

t_SLSH

V_IH

t_F

SCK

V_IL

t_R

V_IL

t_SHOVE

V_OH

V_OL

SOT

SIN

t_IVSLE

t_SLIXE

V_IH

V_IL

V_IH

V_IL

Slave mode

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

 CSIO (SPI = 1, SCINV = 0)

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

V_CC< 4.5 V

V_CC≥ 4.5 V

Parameter

Serial clock cycle time

SCK ↑ → SOT delay time

Symbol

Conditions

Unit

ns

name

SCKx

SCKx,

SOTx

SCKx,

SINx Master mode

SCKx,

SINx

Min

Max

Min

Max

t_SCYC

4t_CYCP

-

4t_CYCP

-

t_SHOVI

- 30

50

0

+ 30

- 20

30

0

+ 20

ns

SIN → SCK ↓ setup time

SCK ↓→ SIN hold time

SOT → SCK ↓ delay time

Serial clock L pulse width

Serial clock H pulse width

SCK ↑ → SOT delay time

SIN → SCK ↓ setup time

SCK ↓→ SIN hold time

t_IVSLI

t_SLIXI

t_SOVLI

t_SLSH

-

ns

SCKx,

SOTx

2t_CYCP

30

-

2t_CYCP

30

-

2t_CYCP

10

-

2t_CYCP

10

-

SCKx

-

t_CYCP

10

+

t_CYCP

10

+

t_SHSL

SCKx

SCKx,

SOTx

SCKx,

SINx

SCKx,

SINx

-

t_SHOVE

t_IVSLE

t_SLIXE

-

50

-

30

-

Slave mode

10

20

10

20

-

SCK falling time

SCK rising time

t_F

t_R

SCKx

-

5

-

5

ns

Notes:  The above characteristics apply to CLK synchronous mode.

 t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which Multi-function serial is connected to, see "Block Diagram" in

this data sheet.

 These characteristics only guarantee the same relocate port number.

For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.

 When the external load capacitance C_L= 30 pF.

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D a t a S h e e t

t_SCYC

V_OH

SCK

V_OL

t_SHOVI

t_SOVLI

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_IVSLI

t_SLIXI

V_IH

V_IL

V_IH

V_IL

Master mode

t_SLSH

t_SHSL

V_IH

t_F

V_IH

SCK

SOT

SIN

V_IL

t_R

t_SHOVE

V_OH

V_OL

*

V_OH

V_OL

t_IVSLE

t_SLIXE

V_IH

V_IL

V_IH

V_IL

Slave mode

*: Changes when writing to TDR register

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

 CSIO (SPI = 1, SCINV = 1)

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

V_CC< 4.5 V

name

V_CC≥ 4.5 V

Parameter

Symbol

Conditions

Unit

Min

Max

Min

Max

Serial clock cycle time

t_SCYC

SCKx

4t_CYCP

-

4t_CYCP

-

ns

SCKx,

SOTx

SCK ↓ → SOT delay time

t_SLOVI

- 30

+ 30

- 20

+ 20

ns

SCKx,

SINx

SCKx,

SINx

SCKx,

SOTx

SIN → SCK ↑ setup time

SCK ↑ → SIN hold time

SOT → SCK ↑ delay time

Serial clock L pulse width

Serial clock H pulse width

SCK ↓ → SOT delay time

SIN → SCK ↑ setup time

SCK ↑ → SIN hold time

t_IVSHI

t_SHIXI

t_SOVHI

t_SLSH

50

0

-

30

0

-

ns

Master mode

2t_CYCP

30

2t_CYCP

10

t_CYCP

10

-

2t_CYCP

30

2t_CYCP

10

t_CYCP

10

-

SCKx

-

+

t_SHSL

-

SCKx,

SOTx

SCKx,

SINx

SCKx,

SINx

t_SLOVE

t_IVSHE

t_SHIXE

-

50

-

30

-

Slave mode

10

20

10

20

-

SCK falling time

SCK rising time

t_F

t_R

SCKx

-

5

-

5

ns

Notes:  The above characteristics apply to CLK synchronous mode.

 t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which Multi-function serial is connected to, see "Block Diagram" in

this data sheet.

 These characteristics only guarantee the same relocate port number.

For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.

 When the external load capacitance C_L= 30 pF.

74

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D a t a S h e e t

t_SCYC

V_OL

V_OH

SCK

t_SOVHI

t_SLOVI

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_SHIXI

t_IVSHI

V_IH

V_IL

V_IH

V_IL

Master mode

t_R

t_F

t_SHSL

t_SLSH

V_IH

SCK

V_IL

t_SLOVE

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_IVSHE

t_SHIXE

V_IH

V_IL

V_IH

V_IL

Slave mode

 UART external clock input (EXT = 1)

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Parameter

Symbol Conditions

Min

Max

Unit Remarks

Serial clock L pulse width

Serial clock H pulse width

SCK falling time

t_SLSH

t_SHSL

t_CYCP+ 10

-

5

ns

C_L= 30 pF

t_F

-

SCK rising time

t_R

t_F

t_SHSL

t_SLSH

V_IH

SCK

V_IL

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D a t a S h e e t

(9) External Input Timing

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

Min

Parameter Symbol Pin name Conditions

Unit

Remarks

Max

A/D converter

trigger input

ns Free-run timer input

clock

ADTG

1

-

2t_CYCP

*

-

FRCKx

ICxx

DTTIxX

INTxx,

NMIX

Input capture

ns Waveform generator

t_INH,

t_INL

Input pulse width

1

-

*2

*3

2t_CYCP

*

-

2t_CYCP+ 100*¹

500

ns

External interrupt

NMI

Deep standby wake

up

WKUPx

*4

500

-

ns

*1: t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected

to, see "Block Diagram" in this data sheet.

*2: When in Run mode, in Sleep mode.

*3: When in Stop mode, in RTL mode, in Timer mode.

*4: When in Deep Standby RTC mode, in Deep Standby Stop mode.

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(10) Quadrature Position/Revolution Counter timing

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Conditions

Unit

Min

Max

AIN pin H width

AIN pin L width

BIN pin H width

BIN pin L width

t_AHL

t_ALL

t_BHL

t_BLL

-

BIN rising time from

AIN pin H level

AIN falling time from

BIN pin H level

BIN falling time from

AIN pin L level

AIN rising time from

BIN pin L level

AIN rising time from

BIN pin H level

BIN falling time from

AIN pin H level

AIN falling time from

BIN pin L level

BIN rising time from

AIN pin L level

PC_Mode2 or

PC_Mode3

PC_Mode2 or

PC_Mode3

PC_Mode2 or

PC_Mode3

PC_Mode2 or

PC_Mode3

PC_Mode2 or

PC_Mode3

PC_Mode2 or

PC_Mode3

PC_Mode2 or

PC_Mode3

PC_Mode2 or

PC_Mode3

QCR:CGSC=0

t_AUBU

t_BUAD

t_ADBD

t_BDAU

t_BUAU

t_AUBD

t_BDAD

t_ADBU

2t_CYCP

*

-

ns

ZIN pin H width

ZIN pin L width

t_ZHL

t_ZLL

AIN/BIN rise and falling

time from determined ZIN

level

Determined ZIN level from

AIN/BIN rise and falling

time

t_ZABE

QCR:CGSC=1

t_ABEZ

*: t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see "Block

Diagram" in this data sheet.

tALL

tAHL

AIN

BIN

tADBD

tAUBU

tBUAD

tBDAU

tBHL

tBLL

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

tBLL

tBHL

BIN

AIN

tBDAD

tBUAU

tAUBD

tADBU

tAHL

tALL

ZIN

AIN/BIN

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(11) I²C Timing

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Standard-

mode

Fast-

mode

Parameter

Symbol Conditions

Unit Remarks

Min

Max Min Max

SCL clock frequency

(Repeated) START condition

hold time

f_SCL

0

100

0

400 kHz

t_HDSTA

4.0

-

0.6

-

μs

SDA ↓ → SCL ↓

SCL clock L width

SCL clock H width

(Repeated) START condition

setup time

t_LOW

t_HIGH

4.7

4.0

-

1.3

0.6

-

μs

t_SUSTA

4.7

-

0.6

-

μs

SCL ↑ → SDA ↓

Data hold time

C_L= 30 pF,

R = (V_P/I_OL)*¹

t_HDDAT

0

3.45*²

0

0.9*³μs

SCL ↓ → SDA ↓ ↑

Data setup time

SDA ↓ ↑ → SCL ↑

STOP condition setup time

SCL ↑ → SDA ↑

t_SUDAT

t_SUSTO

250

4.0

-

100

0.6

-

ns

μs

Bus free time between

STOP condition and

START condition

Noise filter

t_BUF

4.7

-

1.3

-

μs

4

t_SP

-

2 t_CYCP

*

2 t_CYCP

*

ns

*1:R and C_Lrepresent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.

V_Pindicates the power supply voltage of the pull-up resistor and I_OLindicates V_OLguaranteed current.

*2:The maximum t_HDDATmust satisfy that it does not extend at least L period (t_LOW) of device's SCL signal.

*3:A Fast-speed mode I²C bus device can be used on a Standard mode I²C bus system as long as the device

satisfies the requirement of "t_SUDAT≥ 250 ns".

*4:t_CYCPis the APB bus clock cycle time.

About the APB bus number that I²C is connected to, see "Block Diagram" in this data sheet.

To use Standard-mode, set the APB bus clock at 2 MHz or more

To use Fast-mode, set the APB bus clock at 8 MHz or more.

SDA

SCL

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

(12) JTAG Timing

Parameter

(V_CC= 2.7V to 5.5V, V_SS= 0V, T_A= - 40°C to + 105°C)

Value

Symbol Pin name Conditions

Unit

ns

Remarks

Min

Max

V_CC≥ 4.5 V

V_CC< 4.5 V

V_CC≥ 4.5 V

V_CC< 4.5 V

V_CC≥ 4.5 V

TMS, TDI setup

time

TCK,

TMS, TDI

t_JTAGS

15

-

TCK,

TMS, TDI

TMS, TDI hold time t_JTAGH

TDO delay time t_JTAGD

15

-

ns

-

25

45

TCK,

TDO

ns

V_CC< 4.5 V

Note: When the external load capacitance C_L= 30 pF.

TCK

TMS/TDI

TDO

80

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D a t a S h e e t

5. 12-bit A/D Converter

 Electrical Characteristics for the A/D Converter

(V_CC= AV_CC= 2.7V to 5.5V, V_SS= AV_SS= AVRL = 0V, T_A= - 40°C to + 105°C)

Value

Typ

-

± 1.5

± 1.7

± 10

name

Parameter

Symbol

Unit

Remarks

Min

Max

12

± 4.5

± 2.5

± 15

Resolution

-

bit

Integral Nonlinearity

Differential Nonlinearity

Zero transition voltage

Full-scale transition

voltage

LSB

mV

AVRH = 2.7 V

to 5.5 V

V_ZT

ANxx

V_FST

ANxx

-

AVRH ± 5 AVRH ± 15 mV

0.8*¹

1.0*¹

0.24

0.3

-

AV_CC≥ 4.5 V

AV_CC< 4.5 V

AV_CC≥ 4.5 V

AV_CC< 4.5 V

AV_CC≥ 4.5 V

AV_CC< 4.5 V

Conversion time

-

μs

ns

Sampling time*²

t_S

10

40

Compare clock cycle*³

t_CCK

-

1000

50

State transition time to

operation permission

t_STT

C_AIN

R_AIN

-

1.0

9.7

μs

pF

kΩ

Analog input capacity

Analog input resistor

1.7

2.4

AV_CC≥ 4.5 V

AV_CC< 4.5 V

Interchannel disparity

Analog port input current

Analog input voltage

-

4

5

LSB

μA

V

ANxx

AVRH

AVRL

2.7

AV_SS

AVRH

AV_CC

AV_SS

Reference voltage

*1: The conversion time is the value of sampling time (t_S) + compare time (t_C).

The condition of the minimum conversion time is the following.

AV_CC≥ 4.5 V, HCLK=50 MHz sampling time: 240 ns, compare time: 560 ns.

AV_CC< 4.5 V, HCLK=40 MHz sampling time: 300 ns, compare time: 700 ns

Ensure that it satisfies the value of the sampling time (t_S) and compare clock cycle (t_CCK).

For setting of the sampling time and compare clock cycle, see "Chapter 1-1: A/D Converter" in "FM3 Family

PERIPHERAL MANUAL Analog Macro Part".

The register settings of the A/D Converter are reflected in the operation according to the APB bus clock

timing.

For the number of the APB bus to which the A/D Converter is connected, see "Block Diagram".

The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.

*2: A necessary sampling time changes by external impedance.

Ensure that it sets the sampling time to satisfy (Equation 1).

*3: The compare time (t_C) is the value of (Equation 2).

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

Comparator

ANxx

Analog input pin

R_EXT

R_AIN

Analog

signal source

C_AIN

(Equation 1) t_S≥ ( R_AIN+ R_EXT) × C_AIN× 9

t_S:

Sampling time

R_AIN

:

input resistor of A/D = 1.5 kΩ at 4.5 V < AV_CC< 5.5 V ch.0 to ch.7

input resistor of A/D = 1.6 kΩ at 4.5 V < AV_CC< 5.5 V ch.8 to ch.15

input resistor of A/D = 1.7 kΩ at 4.5 V < AV_CC< 5.5 V ch.16 to ch.26

input resistor of A/D = 2.2 kΩ at 2.7 V < AV_CC< 4.5 V ch.0 to ch.7

input resistor of A/D = 2.3 kΩ at 2.7 V < AV_CC< 4.5 V ch.8 to ch.15

input resistor of A/D = 2.4 kΩ at 2.7 V < AV_CC< 4.5 V ch.16 to ch.26

input capacity of A/D = 9.7 pF at 2.7 V < AV_CC< 5.5 V

C_AIN

:

R_EXT

:

Output impedance of external circuit

(Equation 2) t_C= t_CCK× 14

t_C:

t_CCK

Compare time

Compare clock cycle

:

82

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 Definition of 12-bit A/D Converter Terms

 Resolution:

 Integral Nonlinearity:

Analog variation that is recognized by an A/D converter.

Deviation of the line between the zero-transition point

(0b000000000000 ←→ 0b000000000001) and the full-scale transition point

(0b111111111110 ←→ 0b111111111111) from the actual conversion

characteristics.

 Differential Nonlinearity:

Deviation from the ideal value of the input voltage that is required to change

the output code by 1 LSB.

Integral Nonlinearity

Differential Nonlinearity

0xFFF

Actual conversion

characteristics

0xFFE

0x(N+1)

0xN

{1 LSB(N-1) + V_ZT}

0xFFD

V_FST

Ideal characteristics

(Actually-

measured

value)

V_NT

0x004

0x003

0x002

(Actually-measured

value)

V_(N+1)T

(Actually-measured

value)

0x(N-1)

0x(N-2)

Actual conversion

characteristics

V_NT

(Actually-measured

value)

Ideal characteristics

0x001

(Actually-measured value)

V_ZT

Actual conversion characteristics

AVRL

AVRH

AVRL

AVRH

Analog input

V_NT- {1LSB × (N - 1) + V_ZT}

1LSB

Integral Nonlinearity of digital output N =

Differential Nonlinearity of digital output N =

[LSB]

V_{(N + 1) T}- V_NT

- 1 [LSB]

1LSB

V_FST- V_ZT

1LSB =

4094

N:

A/D converter digital output value.

V_ZT: Voltage at which the digital output changes from 0x000 to 0x001.

V_FST: Voltage at which the digital output changes from 0xFFE to 0xFFF.

V_NT: Voltage at which the digital output changes from 0x(N − 1) to 0xN.

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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6. 10-bit D/A Converter

 Electrical Characteristics for the D/A Converter

(V_CC= AV_CC= 2.7V to 5.5V, V_SS= AV_SS= AVRL = 0V, T_A= - 40°C to + 105°C)

Value

Typ Max

Parameter

Symbol Pin name

Unit

Remarks

Min

-

0.47

2.37

- 4.0

Resolution

-

10

0.69

3.43

bit

μs

t_C20

t_C100

INL

0.58

2.90

-

Load 20 pF

Load 100 pF

Conversion time

Integral Nonlinearity*¹

Differential

+ 4.0 LSB

DNL

DAx

- 0.9

-

+ 0.9 LSB

Nonlinearity*^1,*²

-

- 20.0

3.10

2.0

-

10.0

mV Code is 0x000

Output Voltage offset

V_OFF

+ 5.4 mV Code is 0x3FF

4.50

-

3.80

-

kΩ D/A operation

MΩ D/A stop

ns

Analog output

impedance

Output undefined period

*1: No-load

R_O

t_R

-

70

*2: Generates the max current by the CODE about 0x200

84

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7. Low-Voltage Detection Characteristics

(1) Low-Voltage Detection Reset

(T_A= - 40°C to + 105°C)

Value

Min Typ Max

Parameter

Symbol Conditions

Unit

Remarks

SVHR*¹=

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

VDL

2.25

2.30

2.39

2.48

2.58

2.67

2.76

2.85

2.94

3.04

3.31

3.40

3.50

3.68

3.77

3.86

3.96

2.45

2.50

2.60

2.70

2.80

2.90

3.00

3.10

3.20

3.30

3.60

3.70

3.80

4.00

4.10

4.20

4.30

2.65

2.70

2.81

2.92

3.02

3.13

3.24

3.35

3.46

3.56

3.89

4.00

4.10

4.32

4.43

4.54

4.64

V

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

00000

SVHR*¹=

00001

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

SVHR*¹=

00010

SVHR*¹=

00011

SVHR*¹=

00100

SVHR*¹=

00101

SVHR*¹=

00110

SVHR*¹=

00111

SVHR*¹=

01000

SVHR*¹=

01001

SVHR*¹=

01010

LVD stabilization

wait time

8160 ×

t_LVDW

-

μs

2

t_CYCP

*

LVD detection delay

time

t_LVDDL

200

*1: The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to "00000" by

Low-Voltage Detection Reset.

*2: t_CYCPindicates the APB2 bus clock cycle time.

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

(2) Interrupt of Low-Voltage Detection

(T_A= - 40°C to + 105°C)

Value

Min Typ Max

Parameter

Symbol Conditions

Unit

Remarks

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

VDL

2.58

2.67

2.76

2.85

2.94

3.04

3.31

3.40

3.50

3.68

3.77

3.86

3.96

2.80

2.90

3.00

3.10

3.20

3.30

3.60

3.70

3.80

4.00

4.10

4.20

4.30

3.02

3.13

3.24

3.35

3.46

3.56

3.89

4.00

4.10

4.32

4.43

4.54

4.64

V

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

SVHI = 00011

VDH

VDL

SVHI = 00100

VDH

VDL

SVHI = 00101

VDH

VDL

SVHI = 00110

VDH

VDL

SVHI = 00111

VDH

VDL

VDH

SVHI = 01000

VDL

SVHI = 01001

VDH

VDL

SVHI = 01010

VDH

LVD stabilization

wait time

8160×

t_CYCP

t_LVDW

-

μs

*

LVD detection

delay time

t_LVDDL

200

*: t_CYCPindicates the APB2 bus clock cycle time.

86

MB9B120M_DS706-00050-3v0-E, March 18, 2015

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8. Flash Memory Write/Erase Characteristics

(1) Write / Erase time

(V_CC= 2.7V to 5.5V, T_A= - 40°C to + 105°C)

Value

Parameter

Unit

Remarks

Typ

Max

Large Sector

Small Sector

1.1

2.7

Sector erase

time

Includes write time prior to internal

erase

s

0.3

16

0.9

Half word (16-bit)

write time

Not including system-level overhead

time

310

μs

Includes write time prior to internal

erase

Chip erase time

6.8

18

s

*: The typical value is immediately after shipment, the maximam value is guarantee value under 10,000 cycle

of erase/write.

(2) Write cycles and data hold time

Erase/write cycles (cycle) Data hold time (year)

Remarks

1,000

10,000

20*

10*

*: At average + 85C

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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9. Return Time from Low-Power Consumption Mode

(1) Return Factor: Interrupt/WKUP

The return time from Low-Power consumption mode is indicated as follows. It is from receiving the

return factor to starting the program operation.

 Return Count Time

(V_CC= 2.7V to 5.5V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Unit

Remarks

Typ

Max*

t_CYCC

Sleep mode

μs

High-speed CR Timer mode,

Main Timer mode,

40

80

μs

PLL Timer mode

Low-speed CR Timer mode

Sub Timer mode

340

680

860

μs

t_ICNT

RTC mode,

Stop mode

268

503

μs

308

268

583

503

μs

When RAM is off

When RAM is on

Deep Standby RTC mode

Deep Standby Stop mode

*: The maximum value depends on the accuracy of built-in CR.

 Operation example of return from Low-Power consumption mode (by external interrupt*)

External

interrupt

Interrupt factor

Active

accept

t_ICNT

Interrupt factor

clear by CPU

CPU

Operation

Start

*: External interrupt is set to detecting fall edge.

88

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

 Operation example of return from Low-Power consumption mode (by internal resource interrupt*)

Internal

resource

interrupt

Interrupt factor

Active

accept

t_ICNT

Interrupt factor

clear by CPU

CPU

Operation

Start

*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.

Notes:  The return factor is different in each Low-Power consumption modes.

See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3

Family PERIPHERAL MANUAL.

 When interrupt recoveries, the operation mode that CPU recoveries depends on the state before

the Low-Power consumption mode transition. See "Chapter 6: Low Power Consumption Mode" in

"FM3 Family PERIPHERAL MANUAL".

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

(2) Return Factor: Reset

The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to

starting the program operation.

 Return Count Time

(V_CC= 2.7V to 5.5V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Unit

Remarks

Typ

Max*

Sleep mode

148

263

μs

High-speed CR Timer mode,

Main Timer mode,

148

263

μs

PLL Timer mode

Low-speed CR Timer mode

Sub Timer mode

248

312

463

496

μs

t_RCNT

RTC mode,

Stop mode

268

503

μs

308

268

583

503

μs

When RAM is off

When RAM is on

Deep Standby RTC mode

Deep Standby Stop mode

*: The maximum value depends on the accuracy of built-in CR.

 Operation example of return from Low-Power consumption mode (by INITX)

INITX

Internal reset

Reset active

Release

t_RCNT

CPU

Operation

Start

90

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

 Operation example of return from low power consumption mode (by internal resource reset*)

Internal

resource

reset

Internal reset

Reset active

Release

t_RCNT

CPU

Operation

Start

*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.

Notes:  The return factor is different in each Low-Power consumption modes.

See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3

Family PERIPHERAL MANUAL.

 When interrupt recoveries, the operation mode that CPU recoveries depends on the state before

the Low-Power consumption mode transition. See "Chapter 6: Low Power Consumption Mode" in

"FM3 Family PERIPHERAL MANUAL".

 The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on

Reset Timing in 4. AC Characteristics in Electrical Characteristics" for the detail on the time

during the power-on reset/low -voltage detection reset.

 When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main

clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or

the Main PLL clock stabilization wait time.

 The internal resource reset means the watchdog reset and the CSV reset.

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

 Ordering Information

On-chip

Flash

memory

On-chip

SRAM

Part number

Package

Packing

Main: 64 Kbyte

Work: 32 Kbyte

MB9BF121KQN-G-AVE2

MB9BF122KQN-G-AVE2

MB9BF124KQN-G-AVE2

MB9BF121KPMC-G-JNE2

MB9BF122KPMC-G-JNE2

MB9BF124KPMC-G-JNE2

MB9BF121LQN-G-AVE2

MB9BF122LQN-G-AVE2

MB9BF124LQN-G-AVE2

MB9BF121LPMC1-G-JNE2

MB9BF122LPMC1-G-JNE2

MB9BF124LPMC1-G-JNE2

MB9BF121LPMC-G-JNE2

MB9BF122LPMC-G-JNE2

MB9BF124LPMC-G-JNE2

MB9BF121MPMC-G-JNE2

MB9BF122MPMC-G-JNE2

MB9BF124MPMC-G-JNE2

MB9BF121MPMC1-G-JNE2

MB9BF122MPMC1-G-JNE2

MB9BF124MPMC1-G-JNE2

16 Kbyte

32 Kbyte

16 Kbyte

32 Kbyte

16 Kbyte

32 Kbyte

16 Kbyte

32 Kbyte

16 Kbyte

32 Kbyte

16 Kbyte

32 Kbyte

16 Kbyte

32 Kbyte

Plastic・QFN

(0.5 mm pitch), 48-pin

(LCC-48P-M73)

Main: 128 Kbyte

Work: 32 Kbyte

Main: 256 Kbyte

Work: 32 Kbyte

Main: 64 Kbyte

Work: 32 Kbyte

Plastic・LQFP

(0.5 mm pitch), 48-pin

(FPT-48P-M49)

Main: 128 Kbyte

Work: 32 Kbyte

Main: 256 Kbyte

Work: 32 Kbyte

Main: 64 Kbyte

Work: 32 Kbyte

Plastic・QFN

(0.5 mm pitch), 64-pin

(LCC-64P-M24)

Main: 128 Kbyte

Work: 32 Kbyte

Main: 256 Kbyte

Work: 32 Kbyte

Main: 64 Kbyte

Work: 32 Kbyte

Plastic・LQFP

(0.5 mm pitch), 64-pin

(FPT-64P-M38)

Main: 128 Kbyte

Work: 32 Kbyte

Tray

Main: 256 Kbyte

Work: 32 Kbyte

Main: 64 Kbyte

Work: 32 Kbyte

Plastic・LQFP

(0.65 mm pitch), 64-pin

(FPT-64P-M39)

Main: 128 Kbyte

Work: 32 Kbyte

Main: 256 Kbyte

Work: 32 Kbyte

Main: 64 Kbyte

Work: 32 Kbyte

Plastic・LQFP

(0.5 mm pitch), 80-pin

(FPT-80P-M37)

Main: 128 Kbyte

Work: 32 Kbyte

Main: 256 Kbyte

Work: 32 Kbyte

Main: 64 Kbyte

Work: 32 Kbyte

Plastic・LQFP

(0.65 mm pitch), 80-pin

(FPT-80P-M40)

Main: 128 Kbyte

Work: 32 Kbyte

Main: 256 Kbyte

Work: 32 Kbyte

92

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D a t a S h e e t

On-chip

Flash

memory

On-chip

SRAM

Part number

Package

Packing

Main: 64 Kbyte

Work: 32 Kbyte

MB9BF121MBGL-GE1

MB9BF122MBGL-GE1

MB9BF124MBGL-GE1

16 Kbyte

32 Kbyte

Plastic・PFBGA

(0.5 mm pitch), 96-pin

(BGA-96P-M07)

Main: 128 Kbyte

Work: 32 Kbyte

Tray

Main: 256 Kbyte

Work: 32 Kbyte

March 18, 2015, MB9B120M_DS706-00050-3v0-E

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D a t a S h e e t

 Major Changes

Page

Section

Change Results

Revision 1.0

-

Preliminary → Data Sheet

FEATURES

• A/D Converter (Max 26channels)

Revised the conversion time: 1.0μs → 0.8μs

3

• UniqueID

Added the "Unique ID".

5

6

PRODUCT LINEUP

• Function

LIST OF PIN FUNCTIONS

• List of pin numbers

• List of pin functions

• Corrected the I/O circuit type.

• Corrected the Pin state type.

Corrected the Pin function.

15 to 17

32

38

I/O CIRCUIT TYPE

Added the "Type: L".

BLOCK DIAGRAM

Corrected the figure.



45

- TIOA: input → input/output

- TIOB: output → input

Revised the value of "TBD".

ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

2. Recommended Operating Conditions

54

55

Revised the Condition of "Operating temperature".

3. DC Characteristics

(1) Current Rating

4. AC Characteristics

(3) Built-in CR Oscillation Characteristics

(4-2) Operating Conditions of Main PLL (In the

case of using built-in high-speed CR for input clock

of main PLL)

• Revised the value of "TBD".

• Added "Flash memory write/erase current".

• Revised the Condition.

• Revised the footnote.

Revised the value of "TBD".

56, 57

60

61

5. 12-bit A/D Converter

• Electrical characteristics for the A/D converter

• Deleted "(Preliminary value)".

• Revised the conversion time.

Min: 1.0μs → 0.8μs

• Revised the value of "Compare clock cycle

77

(AV_CC≥ 4.5V)".

Min: 50ns → 40ns

• Revised the footnote.

6. 10-bit D/A Converter

Deleted "(Preliminary value)".

80

81

7. Low-Voltage Detection Characteristics

8. MainFlash Memory Write/Erase Characteristics

Revised the value of "TBD".

• Revised the value of "TBD".

• Revised the value of "Sector erase time".

- Large Sector Typ: 1.065s → 1.1s

- Small Sector Typ: 0.606s → 0.3s

• Revised the value of "Chip erase time".

Typ: 9.11s → 6.8s

82

• Deleted "(targeted value)".

Revision 1.1

-

Company name and layout design change

Revision 2.0

FEATURES

• On-chip Memories [Flash memory]

Revised the features of Dual operation Flash memory

2

Corrected the mode.

• Multi-function Serial Interface [I²C]

High speed mode → Fast mode

Revised the features of 5V tolerant I/O.

Corrected the number of A/D activating compare channels.

3ch. → 2ch.

3

4

• General-Purpose I/O Port

• Multi-function Timer

• Corrected the number of A/D activating compare channels.

3ch. → 2ch.

6

• Revised Built-in CR.

PRODUCT LINEUP

• Function

High-speed: 4MHz(± 2%) → 4MHz

Low-speed: 100kHz(Typ) → 100kHz

Revised the footnote.

7

LIST OF PIN FUNCTIONS

• List of pin numbers

20

Corrected the pin number of ZIN1_1.

23

28

30

Corrected the pin number of ADTG_2.

Corrected pin numbers of SIN0_1 and SOT0_1.

Corrected the pin number of DTTI0X_2.

TYPE H :

• List of pin functions

I/O CIRCUIT TYPE

36

Revised the value of "TBD".

102

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

Page

Section

HANDLING DEVICES

Change Results

43

46

Added the descriptions.

Corrected the figure.

• Sub crystal oscillator

BLOCK DIAGRAM

-A/D Activation Compare: 3ch → 2ch

MEMORY MAP

• Memory Map (2)

48

53

54

Added the explanatory note.

Added the pin function of selected Analog output about type L.

• Corrected the footnote.

PIN STATUS IN EACH CPU STATE

• List of Pin Status

Sub CR timer→ Low-speed CR tim

• Added the note and footnote.

• Corrected the value of Analog reference voltage “AVRH”.

Min.: AVss → 2.7

ELECTRICAL CHARACTERISTICS

2. Recommended Operating Conditions

56

57

• Added notes and footnotes.

• Added the remarks of Icc.

• Added the frequency of main clock crystal oscillator in remarks.

3. DC Characteristics

(1) Current Rating

4. AC Characteristics

61

62

64

Added the footnote.

(2) Sub clock input Characteristics

(3) Built-in CR Oscillation Characteristics

• Built-in High-speed CR

• Added "Frequency stabilization time"

• Added notes and footnotes.

• Added "Timing until releaseing Power-on reset"

• Added the timing chart

(6) Power-on Reset Timing

• Corrected the title.

UART Timing → CSIO Timing

• Corrected the notefoot.

UART → Multi-function serial

66

(8) CSIO Timing

Corrected the notefoot.

UART → Multi-function serial

• Revised the Condition.

• Revised the footnote.

68,70,72

77

(11) I²C Timing

• Changed the name of parameter.

•Non Linearity error → Integral Nonlinearity

•Differential linearity error → Differential Nonlinearity

• Changed the Symbol. Of Zero transition voltage.

Vo_T→ V_ZT

79

5. 12-bit A/D Converter

• Electrical characteristics for the A/D converter

• Changed the pin name.

AN00 to AN26 → ANxx

• Corrected the value of V_0T,V_FST,Ts, Tstt, and reference voltage.

• Revides footnotes.

Change the figure.

AN00 to AN26 → ANxx

•Linearity error → Integral Nonlinearity

•Differential linearity error → Differential Nonlinearity

• V_0T→ V_ZT

80

81

• Difinition of 12-bit A/D Converter Terms

•Revised the remark of IDDA.

D/A operation → D/A 1unit operation

• Changed the name of parameter.

•Linearity error → Integral Nonlinearity

•Differential linearity error → Differential Nonlinearity

• Corrected the condition and the value.

• Added the note and the footnote.

• Added “LVD detection delay time”.

• Corrected the condition and the value.

• Added “LVD detection delay time”.

Changed the title of Chapter.

6. 10-bit D/A Converter

• Electrical characteristics for the D/A converter

82

7. Low-Voltage Detection Characteristics

(1) Low-Voltage Detection Reset

83

84

85

(2) Interrupt of Low-Voltage Detection

8. Flash Memory Write/Erase Characteristics

9. Return Time Low-Power Consumption Mode

Main Flash Memory Write/Erase Characteristics →

Flash Memory Write/Erase Characteristics

Added the Chapter “Return Time from Low-Power Consumption Mode”.

86

Revision 3.0

Features

USB Interface

I/O Circuit Type

Memory Map

2

Added the description of PLL for USB

Added about +B input

35, 36

48

Added the summary of Flash memory sector and the note

· Memory map(2)

PIN STATUS IN EACH CPU STAE

· List of Pin Status

Electrical Characteristics

1. Absolute Maximum Ratings

52

Changed the pin status of I-type

· Added the Clamp maximum current

· Added about +B input

55, 56

· Changed the table format

Electrical Characteristics

3. DC Characteristics

(1) Current rating

· Added Main TIMER mode current

· Moved A/D Converter Current

· Moved D/A Converter Current

58-60

March 18, 2015, MB9B120M_DS706-00050-3v0-E

103

D a t a S h e e t

Electrical Characteristics

4. AC Characteristics

(4-1) Operating Conditions of Main PLL

(4-2) Operating Conditions of Main PLL

Electrical Characteristics

4. AC Characteristics

(7) CSIO/UART Timing

Electrical Characteristics

4. AC Characteristics

65

· Added the figure of Main PLL connection

· Modified from UART Timing to CSIO/UART Timing

· Changed from Internal shift clock operation to Master mode

· Changed from External shift clock operation to Slave mode

68-75

76

Added input pulse width of WKUPx pin

(9) External Input Timing

· Added the typical value of Integral Nonlinearity, Differential Nonlinearity,

Zero transition voltage and Full-scale transition voltage

· Added Conversion time at AVcc < 4.5V

Electrical Characteristics

5. 12bit A/D Converter

81

92, 93

Ordering Information

Change to full part number

104

MB9B120M_DS706-00050-3v0-E, March 18, 2015

D a t a S h e e t

March 18, 2015, MB9B120M_DS706-00050-3v0-E

105

D a t a S h e e t

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use,

including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not

designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless

extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,

severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use

where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not

be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the

products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss

from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire

protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in

this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and

Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the

prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a

Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any

product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to

its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party

rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind

arising out of the use of the information in this document.

ORNAND^TM, Easy DesignSim^TM, Traveo^TMand combinations thereof, are trademarks and registered trademarks of

,

Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be

trademarks of their respective owners.

106

MB9B120M_DS706-00050-3v0-E, March 18, 2015


型号：	MB9BF122L
厂家：	SPANSION
描述：	The MB9B120M Series are highly integrated
文件：	总109页 (文件大小：3136K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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