MBM29DL323BE90TN_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20881-7E

FLASH MEMORY

CMOS

32M(4M× 8/2M× 16)BITDualOperation

MBM29DL32XTE/BE⁸⁰/90

■ DESCRIPTION

The MBM29DL32XTE/BE are a 32 M-bit, 3.0 V-only Flash memory organized as 4 Mbytes of 8 bits each or

2 Mwords of 16 bits each. These devices are designed to be programmed in-system with the standard system

3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also

be reprogrammed in standard EPROM programmers.

MBM29DL32XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate

memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories, with the additional capability

of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either

a program or an erase) operation is simultaneously taking place on the other bank.

(Continued)

■ PRODUCT LINE UP

MBM29DL32XTE/BE

Part No.

80

90

+0.3

−0.3

+0.6

Power Supply Voltage V^CC(V)

Max Address Access Time (ns)

Max CE Access Time (ns)

Max OE Access Time (ns)

3.3

3.0

−0.3

80

90

80

30

90

35

■ PACKAGES

48-pin plastic TSOP (1)

Marking Side

48-pin plastic TSOP (1)

63-ball plastic FBGA

Marking Side

(FPT-48P-M19)

(FPT-48P-M20)

(BGA-63P-M01)

MBM29DL32XTE/BE⁸⁰/90

(Continued)

In the MBM29DL32XTE/BE, a new design concept is implemented, so called “Sliding Bank Architecture”. Under

this concept, the MBM29DL32XTE/BE can be produced a series of devices with different Bank 1/Bank 2 size

combinations; 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb.

To eliminate bus contention the devices have separate chip enable (CE) , write enable (WE) , and output enable

(OE) controls.

The MBM29DL32XTE/BE are pin and command set compatible with JEDEC standard E²PROMs. Commands

are written to the command register using standard microprocessor write timings. Register contents serve as

input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations.

Typically, each sector can be programmed and verified in about 0.5 seconds.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29DL32XTE/BE are erased when shipped from the

factory.

Internallygeneratedandregulatedvoltagesareprovidedfortheprogramanderaseoperations. AlowV^CCdetector

automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data

Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase

cycle has been completed, the devices internally reset to the read mode.

The MBM29DL32XTE/BE memories electrically erase the entire chip or all bits within a sector simultaneously

via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM

programming mechanism of hot electron injection.

2

MBM29DL32XTE/BE⁸⁰/90

■ FEATURES

• 0.23 µm Process Technology

• Simultaneous Read/Write operations (dual bank)

Multiple devices available with different bank sizes (Refer to “MBM29DL32XTE/BE Device Bank Divisions” in

“■ FEATURES”)

Host system can program or erase in one bank, then immediately and simultaneously read from the other bank

Zero latency between read and write operations

Read-while-erase

Read-while-program

• Single 3.0 V read, program, and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E²PROMs

• Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP (1) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type)

63-ball FBGA (Package suffix : PBT)

• Minimum 100,000 program/erase cycles

• High performance

80 ns maximum access time

• Sector erase architecture

Eight 4 Kword and sixty-three 32 Kword sectors in word mode

Eight 8 Kbyte and sixty-three 64 Kbyte sectors in byte mode

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• HiddenROM region

64 Kbyte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC input pin

At V^IL, allows protection of boot sectors, regardless of sector group protection/unprotection status

At V^ACC, increases program performance

• Embedded Erase^TMAlgorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TMAlgorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low V^CCwrite inhibit ≤ 2.5 V

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector group protection

Hardware method disables any combination of sector groups from program or erase operations

Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

(Continued)

3

MBM29DL32XTE/BE⁸⁰/90

(Continued)

• Sector Group Protection Set function by Extended sector group protection command

• Fast Programming Function by Extended Command

• Temporary sector group unprotection

Temporary sector group unprotection via the RESET pin.

• In accordance with CFI (Common Flash Memory Interface)

MBM29DL32XTE/BE Device Bank Divisions

Bank 1

Sector sizes

Bank 2

Device

Part Number

Organiza-

tion

Mega-

bits

Mega-

bits

Sector sizes

Eight 8 Kbyte/4 Kword,

seven 64 Kbyte/32 Kword

Fifty-six

64 Kbyte/32 Kword

MBM29DL322TE/BE

MBM29DL323TE/BE

4 Mbit

8 Mbit

28 Mbit

24 Mbit

Eight 8 Kbyte/4 Kword,

fifteen 64 Kbyte/32 Kword

Forty-eight

64 Kbyte/32 Kword

× 8/× 16

Eight 8 Kbyte/4 Kword,

thirty-one 64 Kbyte/

32 Kword

Thirty-two

64 Kbyte/32 Kword

MBM29DL324TE/BE

16 Mbit

4

MBM29DL32XTE/BE⁸⁰/90

■ PIN ASSIGNMENTS

TSOP (1)

A15

A14

A13

A12

A11

A10

A9

A8

A19

A16

48

1

2

3

4

5

6

7

8

(Marking Side)

BYTE

VSS

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE

9

A20

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE

RESET

N.C.

WP/ACC

RY/BY

A18

Normal Bend

A17

A7

A6

A5

A4

A3

A2

A1

VSS

CE

A0

(FPT-48P-M19)

A1

A2

A3

A4

A5

A6

A7

A17

A18

A0

CE

VSS

OE

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

(Marking Side)

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

VCC

DQ4

DQ12

DQ5

DQ13

DQ6

DQ14

DQ7

DQ15/A-1

VSS

RY/BY

WP/ACC

N.C.

RESET

WE

A20

Reverse Bend

A19

A8

A9

A10

A11

A12

A13

A14

BYTE

A16

A15

(FPT-48P-M20)

(Continued)

5

MBM29DL32XTE/BE⁸⁰/90

(Continued)

FBGA

(TOP VIEW)

(Marking Side)

A8

B8

L8

M8

*

N.C.

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

*

N.C.

A13

A12

A14

A15

A16

BYTE DQ15/A-1 VSS

N.C.

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

WE

RESET N.C.

A19

DQ5

DQ12

VCC

DQ4

C4

D4

E4

F4

G4

H4

J4

K4

RY/BY WP/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

A2

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

CE

J2

K2

L2

M2

*

N.C.

OE

VSS

N.C.

A1

B1

L1

M1

*

N.C.

*

N.C.

(BGA-63P-M01)

* : Peripheral Balls on each corner are shorted together via substrate but not connected to the die.

6

MBM29DL32XTE/BE⁸⁰/90

■ PIN DESCRIPTIONS

MBM29DL32XTE/BE Pin Configuration

Function

Pin Name

A²⁰to A0, A-1

DQ¹⁵to DQ0

CE

Address Input

Data Input/Output

Chip Enable

OE

Output Enable

Write Enable

WE

RY/BY

RESET

BYTE

Ready/Busy Output

Hardware Reset Pin/Temporary Sector Group Unprotection

Selects 8-bit or 16-bit mode

WP/ACC

N.C.

Hardware Write Protection/Program Acceleration

No Internal Connection

V^SS

Device Ground

VCC

Device Power Supply

7

MBM29DL32XTE/BE⁸⁰/90

■ BLOCK DIAGRAM

VCC

VSS

Bank 2 Address

Cell Matrix

(Bank 2)

A20 to A0

(A-1)

X-Decoder

RY/BY

RESET

State

Control

WE

Status

DQ15 to DQ0

CE

OE

&

Command

Control

BYTE

WP/ACC

Register

DQ15 to DQ0

X-Decoder

Bank 1 Address

Cell Matrix

(Bank 1)

■ LOGIC SYMBOL

A-1

21

A20 to A0

16 or 8

DQ15 to DQ0

RY/BY

CE

OE

WE

RESET

BYTE

WP/ACC

8

MBM29DL32XTE/BE⁸⁰/90

■ DEVICE BUS OPERATION

MBM29DL32XTE/BE User Bus Operations (BYTE = V^IH)

DQ¹⁵to

DQ⁰

Operation

CE OE WE A⁰

A¹

A⁶

A⁹

RESET WP/ACC

Auto-Select Manufacturer Code*¹

Auto-Select Device Code*¹

Read*³

L

H

L

X

L

H

X

H

L

H

A0

X

A⁰

L

VID

A9

X

Code

DOUT

High-Z

DIN

H

VID

L

X

L

A1

X

A6

X

A6

L

Standby

X

H

VID

L

Output Disable

X

Write (Program/Erase)

A1

H

X

A9

VID

X

Enable Sector Group Protection*^2,*⁴

Verify Sector Group Protection*^2,*⁴

Temporary Sector Group Unprotection*⁵

Reset (Hardware) /Standby

Boot Block Sector Write Protection

X

H

X

L

Code

X

High-Z

X

Legend : L = V^IL, H = VIH, X = VIL or VIH,

= Pulse input. See DC Characteristics for voltage levels.

*1 : Manufacturer and device codes are accessed via a command register write sequence. See “MBM29DL32XTE/

BE Command Definitions”.

*2 : Refer to the section on Sector Group Protection.

*3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*4 : VCC = 3.3 V ± 10%

*5 : Also used for the extended sector group protection.

9

MBM29DL32XTE/BE⁸⁰/90

MBM29DL32XTE/BE User Bus Operations (BYTE = V^IL)

DQ¹⁵

/A-¹

DQ⁷to

DQ⁰

Operation

CE OE WE

A⁰

A¹

A⁶

A⁹

RESET WP/ACC

Auto-Select Manufacturer Code*¹

Auto-Select Device code*¹

Read*³

L

H

L

H

X

H

L

H

L

VID

A9

X

Code

DOUT

H

X

L

A-1

X

A0

X

A1

X

A6

X

Standby

X

H

High-Z

DIN

Output Disable

X

Write (Program/Erase)

A-¹

A0

A1

A6

A9

Enable Sector Group Protection

*^2,*⁴

L

X

VID

L

H

X

L

X

VID

X

Code

X

H

X

Verify Sector Group Protection*^2,*⁴

H

X

Temporary Sector Group

Unprotection*⁵

X

VID

Reset (Hardware) /Standby

X

High-Z

X

L

X

L

Boot Block Sector Write Protection

X

Legend : L = V^IL, H = VIH, X = VIL or VIH,

= Pulse input. See DC Characteristics for voltage levels.

*1 : Manufacturer and device codes are accessed via a command register write sequence. See “MBM29DL32XTE/

BE Command Definitions”.

*2 : Refer to the section on Sector Group Protection.

*3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*4 : VCC = 3.3 V ± 10%

*5 : Also used for the extended sector group protection.

10

MBM29DL32XTE/BE⁸⁰/90

MBM29DL32XTE/BE Command Definitions

Bus

write

cy-

cles

req’d

Fourth bus

read/write

cycle

First bus Second bus Third bus

write cycle write cycle write cycle

Fifth bus

write cycle write cycle

Sixth bus

Command

sequence

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Word

Byte

Word

Byte

Read/

1

3

XXXh F0h

Reset*¹

555h

2AAh

555h

Read/

Reset*¹

AAh

55h

F0h RA*⁷RD*⁷

AAAh

(BA)

555h

Word

Byte

555h

2AAh

555h

Autoselect

3

4

90h

A0h

IA*⁷ID*⁷

(BA)

AAAh

Word

Byte

555h

2AAh

555h

Program

PA

PD

AAAh

Program

Suspend

1

BA

B0h

30h

Program

Resume

Word

Byte

Word

Byte

555h

AAAh

555h

AAAh

BA

2AAh

555h

2AAh

555h

AAAh

555h

AAAh

555h

AAAh

555h

AAAh

2AAh

555h

2AAh

555h

Chip Erase

6

AAh

55h

80h

AAh

55h

10h

30h

AAAh

Sector

Erase

SA

Erase Suspend

Erase Resume

1

B0h

30h

BA

Word

555h

AAAh

2AAh

555h

Set to

Fast Mode

3

2

AAh

55h

PD

20h

Byte

Word

Byte

AAAh

Fast

Program *²

XXXh A0h

PA

Word

Reset from

Fast Mode

*

6

*

2

4

BA

90h XXXh

F0h

Byte

2

Extended

Sector

Group

Word

XXXh 60h SPA 60h SPA 40h SPA SD

Protection

*

Byte

3

(BA)

Word

Byte

55h

98h

(BA)

Query*⁴

1

AAh

(Continued)

11

MBM29DL32XTE/BE⁸⁰/90

(Continued)

Bus

write

cy-

Fourth bus

read/write

cycle

First bus Second bus Third bus

write cycle write cycle write cycle

Fifth bus

write cycle write cycle

Sixth bus

Command

sequence

cles

req’d

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Word

555h

AAAh

555h

AAAh

555h

AAAh

2AAh

555h

2AAh

555h

2AAh

555h

AAAh

555h

AAAh

555h

AAAh

HiddenROM

Entry

3

4

6

AAh

55h

88h

A0h

80h

Byte

Word

Byte

Word

Byte

HiddenROM

Program *⁵

(HRA)

PA

PD

555h

2AAh

555h

HiddenROM

Erase *⁵

AAh

55h HRA 30h

AAAh

(HRBA)

Word

Byte

555h

2AAh

555h

HiddenROM

Exit *⁵

4

AAh

55h

90h XXXh 00h

(HRBA)

AAAh

*1 : Both of these reset commands are equivalent.

*2 : This command is valid during Fast Mode.

*3 : This command is valid while RESET = VID (except during HiddenROM MODE).

*4 : The valid address are A⁶to A0.

*5 : This command is valid during HiddenROM mode.

*6 : The data “00h” is also acceptable.

*7 : The fourth bus cycle is only for read.

Notes : • Address bits A²⁰to A11 = X = “H” or “L” for all address commands except or Program Address (PA) , Sector

Address (SA) , Bank Address (BA) and Sector Group Address (SPA) .

• Bus operations are defined in “MBM29DL32XTE/BE User Bus Operations (BYTE = VIH) ” and

“MBM29DL32XTE/BE User Bus Operations (BYTE = VIL) ”.

• RA = Address of the memory location to be read

IA = Autoselect read address sets both the bank address specified at (A¹⁹, A18, A17, A16, A15) and all the

other A⁶, A1, A0, (A−1) .

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A²⁰, A19, A18, A17, A16, A15, A14, A13, and

A¹²will uniquely select any sector.

BA = Bank Address (A²⁰to A15)

• RD = Data read from location RA during read operation.

ID = Device code/manufacture code for the address located by IA.

PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.

• SPA = Sector group address to be protected. Set sector group address and (A⁶, A1, A0) = (0, 1, 0) .

SD = Sector group protection verify data. Output 01h at protected sector group addresses and output

00h at unprotected sector group addresses.

• HRA = Address of the HiddenROM area

29DL32XTE (Top Boot Type)

Word Mode : 1F8000h to 1FFFFFh

Byte Mode : 3F0000h to 3FFFFFh

29DL32XBE (Bottom Boot Type) Word Mode : 000000h to 007FFFh

Byte Mode : 000000h to 00FFFFh

• HRBA = Bank Address of the HiddenROM area

29DL32XTE (Top Boot Type) : A²⁰= A¹⁹= A¹⁸= A¹⁷= A¹⁶= A¹⁵= VIH

29DL32XBE (Bottom Boot Type) : A²⁰= A¹⁹= A¹⁸= A¹⁷= A¹⁶= A¹⁵= VIL

• The system should generate the following address patterns :

Word Mode : 555h or 2AAh to addresses A¹⁰to A0

Byte Mode : AAAh or 555h to addresses A10 to A0, and A-1

12

MBM29DL32XTE/BE⁸⁰/90

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

• The command combinations not described in “MBM29DL32XTE/BE Command Definitions” are illegal.

In case of applying V^IDon A9, since both Bank 1 and Bank 2 enters Autoselect mode, the simultaneous operation

can not be executed.

MBM29DL322TE/BE Sector Group Protection Verify Autoselect Codes

*1

Type

A²⁰to A¹²

A⁶

A¹

A⁰

A-¹

VIL

X

Code (HEX)

04h

Manufacture’s Code

BA*³

VIL

Byte

Word

Byte

55h

MBM29DL322TE

BA*³

VIL

VIH

2255h

56h

Device

Code

VIL

X

MBM29DL322BE

VIL

VIH

VIL

Word

2256h

Sector group

addresses

Sector Group Protection

V^IL

VIL

01h^*2

*1 : A-¹is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address.

*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

*3 : When V^IDis applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous

operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank

address needs to be indicated when Autoselect mode is read out at command mode, because then it enables

to activate simultaneous operation.

Extended Autoselect Code Table

DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Code

A-1/

0

Manufacturer’s Code

04h

0

1

0

(B) * 55h A-¹HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0

1

0

1

0

1

0

1

0

MBM29DL322

TE

(W) 2255h

0

1

0

1

0

Device

Code

(B) * 56h A-¹HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0

MBM29DL322

BE

(W) 2256h

01h

0

1

0

1

0

A-1/

0

Sector Group Protection

0

1

* : At Byte mode, DQ⁸to DQ14 are High-Z and DQ15 is A-1, the lowest address.

(B) : Byte mode

(W) : Word mode

HI-Z : High-Z

13

MBM29DL32XTE/BE⁸⁰/90

MBM29DL323TE/BE Sector Group Protection Verify Autoselect Codes

*1

Type

A²⁰to A¹²

A⁶

A¹

A⁰

A-¹

Code (HEX)

04h

Manufacture’s Code

BA*³

VIL

X

Byte

Word

Byte

50h

MBM29DL323TE

BA*³

VIL

VIH

2250h

53h

Device

Code

VIL

X

MBM29DL323BE

VIL

VIH

VIL

Word

2253h

Sector group

addresses

Sector Group Protection

V^IL

VIL

01h^*2

*1 : A-1 is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address.

*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

*3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous

operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank

address needs to be indicated when Autoselect mode is read out at command mode, because then it enables

to activate simultaneous operation.

Extended Autoselect Code Table

DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Code

A-1/

0

04h

Manufacturer’s Code

0

1

0

(B) *

(W)

50h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0

1

0

1

0

1

0

1

MBM29DL323

TE

2250h

53h

0

1

0

1

0

Device

Code

(B) *

(W)

A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0

MBM29DL323

BE

2253h 0

A-1/

0

1

0

1

0

01h

Sector Group Protection

0

1

0

* : At Byte mode, DQ⁸to DQ14 are High-Z and DQ15 is A-1, the lowest address.

(B) : Byte mode

(W) : Word mode

HI-Z : High-Z

14

MBM29DL32XTE/BE⁸⁰/90

MBM29DL324TE/BE Sector Group Protection Verify Autoselect Codes

*1

Type

A²⁰to A¹²

A⁶

A¹

A⁰

A-¹

Code (HEX)

04h

Manufacture’s Code

BA*³

VIL

X

Byte

Word

Byte

5Ch

MBM29DL324TE

BA*³

VIL

VIH

225Ch

5Fh

Device

Code

VIL

X

MBM29DL324BE

VIL

VIH

VIL

Word

225Fh

Sector group

addresses

Sector Group Protection

V^IL

VIL

01h^*2

*1 : A-1 is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address.

*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

*3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous

operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank

address needs to be indicated when Autoselect mode is read out at command mode, because then it enables

to activate simultaneous operation.

Extended Autoselect Code Table

DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Code

A-1/

0

04h

Manufacturer’s Code

0

1

0

(B) *

(W)

5Ch A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0

1

0

1

0

1

0

1

MBM29DL324

TE

225Ch

5Fh

0

1

0

1

0

Device

Code

(B) *

(W)

A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0

MBM29DL324

BE

225Fh 0

A-1/

0

1

0

1

0

01h

Sector Group Protection

0

1

0

* : At Byte mode, DQ⁸to DQ14 are High-Z and DQ15 is A-1, the lowest address.

(B) : Byte mode

(W) : Word mode

HI-Z : High-Z

15

MBM29DL32XTE/BE⁸⁰/90

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE

Sector Address Table (MBM29DL322TE)

Sector address

Bank address

Sector

size

(Kbytes/

Kwords)

Sec-

tor

(×8)

Address range

(×16)

Address range

Bank

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32

000000h to 00FFFFh 000000h to 007FFFh

010000h to 01FFFFh 008000h to 00FFFFh

020000h to 02FFFFh 010000h to 017FFFh

030000h to 03FFFFh 018000h to 01FFFFh

040000h to 04FFFFh 020000h to 027FFFh

050000h to 05FFFFh 028000h to 02FFFFh

060000h to 06FFFFh 030000h to 037FFFh

070000h to 07FFFFh 038000h to 03FFFFh

080000h to 08FFFFh 040000h to 047FFFh

090000h to 09FFFFh 048000h to 04FFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32

0F0000h to 0FFFFFh 078000h to 07FFFFh

100000h to 10FFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

Bank

2

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

200000h to 20FFFFh 100000h to 107FFFh

(Continued)

16

MBM29DL32XTE/BE⁸⁰/90

Sector address

Bank address

Sector

size

(Kbytes/

Sec-

tor

(×8)

Address range

(×16)

Address range

Bank

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

X

64/32

210000h to 21FFFFh 108000h to 10FFFFh

220000h to 22FFFFh 110000h to 117FFFh

230000h to 23FFFFh 118000h to 11FFFFh

240000h to 24FFFFh 120000h to 127FFFh

250000h to 25FFFFh 128000h to 12FFFFh

260000h to 26FFFFh 130000h to 137FFFh

270000h to 27FFFFh 138000h to 13FFFFh

280000h to 28FFFFh 140000h to 147FFFh

290000h to 29FFFFh 148000h to 14FFFFh

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

Bank

2

64/32

2F0000h to 2FFFFFh 178000h to 17FFFFh

300000h to 30FFFFh 180000h to 187FFFh

310000h to 31FFFFh 188000h to 18FFFFh

320000h to 32FFFFh 190000h to 197FFFh

330000h to 33FFFFh 198000h to 19FFFFh

340000h to 34FFFFh 1A0000h to 1A7FFFh

350000h to 35FFFFh 1A8000h to 1AFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

390000h to 39FFFFh 1C8000h to 1CFFFFh

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

Bank

1

8/4

3F0000h to 3F1FFFh 1F8000h to 1F8FFFh

3F2000h to 3F3FFFh 1F9000h to 1F9FFFh

3F4000h to 3F5FFFh 1FA000h to 1FAFFFh

3F6000h to 3F7FFFh 1FB000h to 1FBFFFh

(Continued)

0

1

0

1

0

1

17

MBM29DL32XTE/BE⁸⁰/90

(Continued)

Sector address

Sec-

tor

Sector

size

(Kbytes/

(×8)

Address range

(×16)

Address range

Bank

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA67

SA68

SA69

SA70

1

0

1

0

1

0

1

X

8/4

3F8000h to 3F9FFFh 1FC000h to 1FCFFFh

3FA000h to 3FBFFFh 1FD000h to 1FDFFFh

3FC000h to 3FDFFFh 1FE000h to 1FEFFFh

3FE000h to 3FFFFFh 1FF000h to 1FFFFFh

Bank

1

Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) .

The address range is A20 : A0 if in word mode (BYTE = VIH) .

Sector Address Table (MBM29DL322BE)

Sector address Sector

Bank address

Sec-

tor

size

(Kbytes/

(×8)

Address range

(×16)

Address range

Bank

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA70

SA69

SA68

SA67

SA66

SA65

SA64

SA63

SA62

SA61

SA60

SA59

SA58

SA57

SA56

SA55

SA54

SA53

SA52

SA51

SA50

SA49

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32

3F0000h to 3FFFFFh 1F8000h to 1FFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32

390000h to 39FFFFh 1C8000h to 1CFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

350000h to 35FFFFh 1A8000h to 1AFFFFh

340000h to 34FFFFh 1A0000h to 1A7FFFh

330000h to 33FFFFh 198000h to 19FFFFh

320000h to 32FFFFh 190000h to 197FFFh

310000h to 31FFFFh 188000h to 18FFFFh

300000h to 30FFFFh 180000h to 187FFFh

2F0000h to 2FFFFFh 178000h to 17FFFFh

Bank

2

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

(Continued)

18

MBM29DL32XTE/BE⁸⁰/90

Sector address

Bank address

Sector

size

(Kbytes/

Sec-

tor

(×8)

Address range

(×16)

Address range

Bank

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA48

SA47

SA46

SA45

SA44

SA43

SA42

SA41

SA40

SA39

SA38

SA37

SA36

SA35

SA34

SA33

SA32

SA31

SA30

SA29

SA28

SA27

SA26

SA25

SA24

SA23

SA22

SA21

SA20

SA19

SA18

SA17

SA16

SA15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32

290000h to 29FFFFh 148000h to 14FFFFh

280000h to 28FFFFh 140000h to 147FFFh

270000h to 27FFFFh 138000h to 13FFFFh

260000h to 26FFFFh 130000h to 137FFFh

250000h to 25FFFFh 128000h to 12FFFFh

240000h to 24FFFFh 120000h to 127FFFh

230000h to 23FFFFh 118000h to 11FFFFh

220000h to 22FFFFh 110000h to 117FFFh

210000h to 21FFFFh 108000h to 10FFFFh

200000h to 20FFFFh 100000h to 107FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32

190000h to 19FFFFh 0C8000h to 0CFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

130000h to 13FFFFh 098000h to 09FFFFh

120000h to 12FFFFh 090000h to 097FFFh

110000h to 11FFFFh 088000h to 08FFFFh

100000h to 10FFFFh 080000h to 087FFFh

0F0000h to 0FFFFFh 078000h to 07FFFFh

Bank

2

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

64/32

090000h to 09FFFFh 048000h to 04FFFFh

080000h to 08FFFFh 040000h to 047FFFh

(Continued)

19

MBM29DL32XTE/BE⁸⁰/90

(Continued)

Sector address

Sec-

tor

Sector

size

(Kbytes/

(×8)

Address range

(×16)

Address range

Bank

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA14

SA13

SA12

SA11

SA10

SA9

SA8

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

0

X

1

0

1

0

X

1

0

1

0

1

0

1

0

X

64/32

8/4

070000h to 07FFFFh 038000h to 03FFFFh

060000h to 06FFFFh 030000h to 037FFFh

050000h to 05FFFFh 028000h to 02FFFFh

040000h to 04FFFFh 020000h to 027FFFh

030000h to 03FFFFh 018000h to 01FFFFh

020000h to 02FFFFh 010000h to 017FFFh

010000h to 01FFFFh 008000h to 00FFFFh

00E000h to 00FFFFh 007000h to 007FFFh

00C000h to 00DFFFh 006000h to 006FFFh

00A000h to 00BFFFh 005000h to 005FFFh

008000h to 009FFFh 004000h to 004FFFh

006000h to 007FFFh 003000h to 003FFFh

004000h to 005FFFh 002000h to 002FFFh

002000h to 003FFFh 001000h to 001FFFh

000000h to 001FFFh 000000h to 000FFFh

Bank

1

8/4

Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) .

The address range is A20 : A0 if in word mode (BYTE = VIH) .

20

MBM29DL32XTE/BE⁸⁰/90

Sector Address Table (MBM29DL323TE)

Sector address

Bank address

Sector

size

(Kbytes/

Kwords)

Sec-

tor

(×8)

Address range

(×16)

Address range

Bank

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32

000000h to 00FFFFh 000000h to 007FFFh

010000h to 01FFFFh 008000h to 00FFFFh

020000h to 02FFFFh 010000h to 017FFFh

030000h to 03FFFFh 018000h to 01FFFFh

040000h to 04FFFFh 020000h to 027FFFh

050000h to 05FFFFh 028000h to 02FFFFh

060000h to 06FFFFh 030000h to 037FFFh

070000h to 07FFFFh 038000h to 03FFFFh

080000h to 08FFFFh 040000h to 047FFFh

090000h to 09FFFFh 048000h to 04FFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32

0F0000h to 0FFFFFh 078000h to 07FFFFh

100000h to 10FFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

Bank

2

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

200000h to 20FFFFh 100000h to 107FFFh

(Continued)

21

MBM29DL32XTE/BE⁸⁰/90

Sector address

Sec-

tor

Sector

size

(Kbytes/

(×8)

Address range

(×16)

Address range

Bank

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

X

64/32

210000h to 21FFFFh 108000h to 10FFFFh

220000h to 22FFFFh 110000h to 117FFFh

230000h to 23FFFFh 118000h to 11FFFFh

240000h to 24FFFFh 120000h to 127FFFh

250000h to 25FFFFh 128000h to 12FFFFh

260000h to 26FFFFh 130000h to 137FFFh

270000h to 27FFFFh 138000h to 13FFFFh

280000h to 28FFFFh 140000h to 147FFFh

290000h to 29FFFFh 148000h to 14FFFFh

Bank

2

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

64/32

2F0000h to 2FFFFFh 178000h to 17FFFFh

300000h to 30FFFFh 180000h to 187FFFh

310000h to 31FFFFh 188000h to 18FFFFh

320000h to 32FFFFh 190000h to 197FFFh

330000h to 33FFFFh 198000h to 19FFFFh

340000h to 34FFFFh 1A0000h to 1A7FFFh

350000h to 35FFFFh 1A8000h to 1AFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

390000h to 39FFFFh 1C8000h to 1CFFFFh

Bank

1

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

8/4

3F0000h to 3F1FFFh 1F8000h to 1F8FFFh

3F2000h to 3F3FFFh 1F9000h to 1F9FFFh

3F4000h to 3F5FFFh 1FA000h to 1FAFFFh

3F6000h to 3F7FFFh 1FB000h to 1FBFFFh

(Continued)

0

1

0

1

0

1

22

MBM29DL32XTE/BE⁸⁰/90

(Continued)

Sector address

Bank address

Sector

size

(Kbytes/

Sec-

tor

(×8)

Address range

(×16)

Address range

Bank

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA67

SA68

SA69

SA70

1

0

1

0

1

0

1

X

8/4

3F8000h to 3F9FFFh 1FC000h to 1FCFFFh

3FA000h to 3FBFFFh 1FD000h to 1FDFFFh

3FC000h to 3FDFFFh 1FE000h to 1FEFFFh

3FE000h to 3FFFFFh 1FF000h to 1FFFFFh

Bank

1

Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) .

The address range is A20 : A0 if in word mode (BYTE = VIH) .

Sector Address Table (MBM29DL323BE)

Sector address Sector

Bank address

Sec-

tor

size

(Kbytes/

(×8)

Address range

(×16)

Address range

Bank

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA70

SA69

SA68

SA67

SA66

SA65

SA64

SA63

SA62

SA61

SA60

SA59

SA58

SA57

SA56

SA55

SA54

SA53

SA52

SA51

SA50

SA49

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32

3F0000h to 3FFFFFh 1F8000h to 1FFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32

390000h to 39FFFFh 1C8000h to 1CFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

350000h to 35FFFFh 1A8000h to 1AFFFFh

340000h to 34FFFFh 1A0000h to 1A7FFFh

330000h to 33FFFFh 198000h to 19FFFFh

320000h to 32FFFFh 190000h to 197FFFh

310000h to 31FFFFh 188000h to 18FFFFh

300000h to 30FFFFh 180000h to 187FFFh

2F0000h to 2FFFFFh 178000h to 17FFFFh

Bank

2

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

(Continued)

23

MBM29DL32XTE/BE⁸⁰/90

Sector address

Sec-

tor

Sector

size

(Kbytes/

(×8)

Address range

(×16)

Address range

Bank

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA48

SA47

SA46

SA45

SA44

SA43

SA42

SA41

SA40

SA39

SA38

SA37

SA36

SA35

SA34

SA33

SA32

SA31

SA30

SA29

SA28

SA27

SA26

SA25

SA24

SA23

SA22

SA21

SA20

SA19

SA18

SA17

SA16

SA15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32

290000h to 29FFFFh 148000h to 14FFFFh

280000h to 28FFFFh 140000h to 147FFFh

270000h to 27FFFFh 138000h to 13FFFFh

260000h to 26FFFFh 130000h to 137FFFh

250000h to 25FFFFh 128000h to 12FFFFh

240000h to 24FFFFh 120000h to 127FFFh

230000h to 23FFFFh 118000h to 11FFFFh

220000h to 22FFFFh 110000h to 117FFFh

210000h to 21FFFFh 108000h to 10FFFFh

200000h to 20FFFFh 100000h to 107FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

Bank

2

64/32

190000h to 19FFFFh 0C8000h to 0CFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

130000h to 13FFFFh 098000h to 09FFFFh

120000h to 12FFFFh 090000h to 097FFFh

110000h to 11FFFFh 088000h to 08FFFFh

100000h to 10FFFFh 080000h to 087FFFh

0F0000h to 0FFFFFh 078000h to 07FFFFh

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

Bank

1

64/32

090000h to 09FFFFh 048000h to 04FFFFh

080000h to 08FFFFh 040000h to 047FFFh

(Continued)

24

MBM29DL32XTE/BE⁸⁰/90

(Continued)

Sector address

Bank address

Sector

size

(Kbytes/

Sec-

tor

(×8)

Address range

(×16)

Address range

Bank

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA14

SA13

SA12

SA11

SA10

SA9

SA8

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

0

X

1

0

1

0

X

1

0

1

0

1

0

1

0

X

64/32

8/4

070000h to 07FFFFh 038000h to 03FFFFh

060000h to 06FFFFh 030000h to 037FFFh

050000h to 05FFFFh 028000h to 02FFFFh

040000h to 04FFFFh 020000h to 027FFFh

030000h to 03FFFFh 018000h to 01FFFFh

020000h to 02FFFFh 010000h to 017FFFh

010000h to 01FFFFh 008000h to 00FFFFh

00E000h to 00FFFFh 007000h to 007FFFh

00C000h to 00DFFFh 006000h to 006FFFh

00A000h to 00BFFFh 005000h to 005FFFh

008000h to 009FFFh 004000h to 004FFFh

006000h to 007FFFh 003000h to 003FFFh

004000h to 005FFFh 002000h to 002FFFh

002000h to 003FFFh 001000h to 001FFFh

000000h to 001FFFh 000000h to 000FFFh

Bank

1

8/4

Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) .

The address range is A20 : A0 if in word mode (BYTE = VIH) .

25

MBM29DL32XTE/BE⁸⁰/90

Sector Address Table (MBM29DL324TE)

Sector address

Bank address

Sector

size

(Kbytes/

Kwords)

Sec-

tor

(×8)

Address range

(×16)

Address range

Bank

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

64/32

000000h to 00FFFFh 000000h to 007FFFh

010000h to 01FFFFh 008000h to 00FFFFh

020000h to 02FFFFh 010000h to 017FFFh

030000h to 03FFFFh 018000h to 01FFFFh

040000h to 04FFFFh 020000h to 027FFFh

050000h to 05FFFFh 028000h to 02FFFFh

060000h to 06FFFFh 030000h to 037FFFh

070000h to 07FFFFh 038000h to 03FFFFh

080000h to 08FFFFh 040000h to 047FFFh

090000h to 09FFFFh 048000h to 04FFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32

0F0000h to 0FFFFFh 078000h to 07FFFFh

100000h to 10FFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

Bank

2

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

(Continued)

26

MBM29DL32XTE/BE⁸⁰/90

Sector address

Bank address

Sector

size

(Kbytes/

Sec-

tor

(×8)

Address range

(×16)

Address range

Bank

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

X

64/32

200000h to 20FFFFh 100000h to 107FFFh

210000h to 21FFFFh 108000h to 10FFFFh

220000h to 22FFFFh 110000h to 117FFFh

230000h to 23FFFFh 118000h to 11FFFFh

240000h to 24FFFFh 120000h to 127FFFh

250000h to 25FFFFh 128000h to 12FFFFh

260000h to 26FFFFh 130000h to 137FFFh

270000h to 27FFFFh 138000h to 13FFFFh

280000h to 28FFFFh 140000h to 147FFFh

290000h to 29FFFFh 148000h to 14FFFFh

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

64/32

2F0000h to 2FFFFFh 178000h to 17FFFFh

300000h to 30FFFFh 180000h to 187FFFh

310000h to 31FFFFh 188000h to 18FFFFh

320000h to 32FFFFh 190000h to 197FFFh

330000h to 33FFFFh 198000h to 19FFFFh

340000h to 34FFFFh 1A0000h to 1A7FFFh

350000h to 35FFFFh 1A8000h to 1AFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

390000h to 39FFFFh 1C8000h to 1CFFFFh

Bank

1

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

8/4

3F0000h to 3F1FFFh 1F8000h to 1F8FFFh

3F2000h to 3F3FFFh 1F9000h to 1F9FFFh

3F4000h to 3F5FFFh 1FA000h to 1FAFFFh

(Continued)

0

1

0

1

0

27

MBM29DL32XTE/BE⁸⁰/90

(Continued)

Sector address

Sec-

tor

Sector

size

(Kbytes/

(×8)

Address range

(×16)

Address range

Bank

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA66

SA67

SA68

SA69

SA70

1

0

1

0

1

0

1

0

1

X

8/4

3F6000h to 3F7FFFh 1FB000h to 1FBFFFh

3F8000h to 3F9FFFh 1FC000h to 1FCFFFh

3FA000h to 3FBFFFh 1FD000h to 1FDFFFh

3FC000h to 3FDFFFh 1FE000h to 1FEFFFh

3FE000h to 3FFFFFh 1FF000h to 1FFFFFh

Bank

1

Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) .

The address range is A20 : A0 if in word mode (BYTE = VIH) .

Sector Address Table (MBM29DL324BE)

Sector address Sector

Sec-

tor

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA70

SA69

SA68

SA67

SA66

SA65

SA64

SA63

SA62

SA61

SA60

SA59

SA58

SA57

SA56

SA55

SA54

SA53

SA52

SA51

SA50

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

64/32

3F0000h to 3FFFFFh 1F8000h to 1FFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32

390000h to 39FFFFh 1C8000h to 1CFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

350000h to 35FFFFh 1A8000h to 1AFFFFh

340000h to 34FFFFh 1A0000h to 1A7FFFh

330000h to 33FFFFh 198000h to 19FFFFh

320000h to 32FFFFh 190000h to 197FFFh

310000h to 31FFFFh 188000h to 18FFFFh

300000h to 30FFFFh 180000h to 187FFFh

2F0000h to 2FFFFFh 178000h to 17FFFFh

Bank

2

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

(Continued)

28

MBM29DL32XTE/BE⁸⁰/90

Sector address

Bank address

Sector

size

(Kbytes/

Sec-

tor

(×8)

Address range

(×16)

Address range

Bank

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA49

SA48

SA47

SA46

SA45

SA44

SA43

SA42

SA41

SA40

SA39

SA38

SA37

SA36

SA35

SA34

SA33

SA32

SA31

SA30

SA29

SA28

SA27

SA26

SA25

SA24

SA23

SA22

SA21

SA20

SA19

SA18

SA17

SA16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

64/32

290000h to 29FFFFh 148000h to 14FFFFh

280000h to 28FFFFh 140000h to 147FFFh

270000h to 27FFFFh 138000h to 13FFFFh

260000h to 26FFFFh 130000h to 137FFFh

250000h to 25FFFFh 128000h to 12FFFFh

240000h to 24FFFFh 120000h to 127FFFh

230000h to 23FFFFh 118000h to 11FFFFh

220000h to 22FFFFh 110000h to 117FFFh

210000h to 21FFFFh 108000h to 10FFFFh

200000h to 20FFFFh 100000h to 107FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

Bank

2

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32

190000h to 19FFFFh 0C8000h to 0CFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

130000h to 13FFFFh 098000h to 09FFFFh

120000h to 12FFFFh 090000h to 097FFFh

110000h to 11FFFFh 088000h to 08FFFFh

100000h to 10FFFFh 080000h to 087FFFh

0F0000h to 0FFFFFh 078000h to 07FFFFh

Bank

1

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

64/32

090000h to 09FFFFh 048000h to 04FFFFh

(Continued)

29

MBM29DL32XTE/BE⁸⁰/90

(Continued)

Sector address

Sec-

tor

Sector

size

(Kbytes/

(×8)

Address range

(×16)

Address range

Bank

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹Kwords)

SA15

SA14

SA13

SA12

SA11

SA10

SA9

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

0

X

1

0

1

0

X

1

0

1

0

1

0

1

0

X

64/32

8/4

080000h to 08FFFFh 040000h to 047FFFh

070000h to 07FFFFh 038000h to 03FFFFh

060000h to 06FFFFh 030000h to 037FFFh

050000h to 05FFFFh 028000h to 02FFFFh

040000h to 04FFFFh 020000h to 027FFFh

030000h to 03FFFFh 018000h to 01FFFFh

020000h to 02FFFFh 010000h to 017FFFh

010000h to 01FFFFh 008000h to 00FFFFh

00E000h to 00FFFFh 007000h to 007FFFh

00C000h to 00DFFFh 006000h to 006FFFh

00A000h to 00BFFFh 005000h to 005FFFh

008000h to 009FFFh 004000h to 004FFFh

006000h to 007FFFh 003000h to 003FFFh

004000h to 005FFFh 002000h to 002FFFh

002000h to 003FFFh 001000h to 001FFFh

000000h to 001FFFh 000000h to 000FFFh

SA8

Bank

1

SA7

SA6

8/4

SA5

8/4

SA4

8/4

SA3

8/4

SA2

8/4

SA1

8/4

SA0

8/4

Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) .

The address range is A20 : A0 if in word mode (BYTE = VIH)

30

MBM29DL32XTE/BE⁸⁰/90

Sector Group Addresses (MBM29DL32XTE)

(Top Boot Block)

Sector group

A²⁰

A¹⁹

A¹⁸

A¹⁷

A¹⁶

0

A¹⁵

0

A¹⁴

A¹³

A¹²

Sectors

SGA0

0

X

SA0

0

1

SGA1

0

1

0

X

SA1 to SA3

1

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

SGA8

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

X

0

X

SA4 to SA7

SA8 to SA11

SA12 to SA15

SA16 to SA19

SA20 to SA23

SA24 to SA27

SA28 to SA31

SA32 to SA35

SA36 to SA39

SA40 to SA43

SA44 to SA47

SA48 to SA51

SA52 to SA55

SA56 to SA59

SGA16

1

0

1

X

SA60 to SA62

1

0

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

1

31

MBM29DL32XTE/BE⁸⁰/90

Sector Group Addresses (MBM29DL32XBE)

(Bottom Boot Block)

Sector group

SGA0

A²⁰

0

A¹⁹

0

A¹⁸

0

A¹⁷

0

A¹⁶

0

A¹⁵

0

A¹⁴

0

A¹³

0

A¹²

0

Sectors

SA0

SGA1

0

1

SA1

SGA2

0

1

0

SA2

SGA3

0

1

SA3

SGA4

0

1

0

SA4

SGA5

0

1

0

1

SA5

SGA6

0

1

0

SA6

SGA7

0

1

SA7

0

1

SGA8

0

1

0

X

SA8 to SA10

1

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

X

0

X

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SA35 to SA38

SA39 to SA42

SA43 to SA46

SA47 to SA50

SA51 to SA54

SA55 to SA58

SA59 to SA62

SA63 to SA66

SGA23

SGA24

1

0

1

X

SA67 to SA69

SA70

1

0

1

32

MBM29DL32XTE/BE⁸⁰/90

Common Flash Memory Interface Code

A⁰to A⁶

Description

DQ⁰to DQ¹⁵

10h

11h

12h

0051h

0052h

0059h

Query-unique ASCII string “QRY”

Primary OEM Command Set

02h : AMD/FJ standard type

13h

14h

0002h

0000h

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = not applicable)

Address for Alternate OEM Extended Table

19h

1Ah

0000h

V^CCMin (write/erase)

DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV

1Bh

1Ch

0027h

0036h

V^CCMax (write/erase)

DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV

VPP Min voltage

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

0016h

VPP Max voltage

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min size buffer write 2^Nµs

Typical timeout per individual sector erase 2^Nms

Typical timeout for full chip erase 2^Nms

Max timeout for byte/word write 2^Ntimes typical

Max timeout for buffer write 2^Ntimes typical

Max timeout per individual sector erase 2^Ntimes typical

Max timeout for full chip erase 2^Ntimes typical

Device Size = 2^Nbyte

Flash Device Interface description

02h : ×8/×16

28h

29h

0002h

0000h

Max number of byte in

multi-byte write = 2^N

2Ah

2Bh

0000h

Number of Erase Block Regions within device

2Ch

0002h

Erase Block Region 1 Information

bit 15 to bit 0 : y = number of sectors

bit 31 to bit 16 : z = size

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

(z × 256 bytes)

Erase Block Region 2 Information

bit 15 to bit 0 : y = number of sectors

bit 31 to bit 16 : z = size

31h

32h

33h

34h

003Eh

0000h

0001h

(z × 256 bytes)

(Continued)

33

MBM29DL32XTE/BE⁸⁰/90

(Continued)

Description

A⁰to A⁶

DQ⁰to DQ¹⁵

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

Major version number, ASCII

Minor version number, ASCII

43h

44h

0031h

0032h

Address Sensitive Unlock

00h = Required

45h

46h

0000h

0002h

Erase Suspend

02h = To Read & Write

Sector Protection

00h = Not Supported

47h

0001h

X = Number of sectors in per group

Sector Temporary Unprotection

01h = Supported

48h

49h

0001h

0004h

Sector Protection Algorithm

Number of Sector for Bank 2

00h = Not Supported

38h = MBM29DL322TE

30h = MBM29DL323TE

20h = MBM29DL324TE

38h = MBM29DL322BE

30h = MBM29DL323BE

20h = MBM29DL324BE

4Ah

00XXh

Burst Mode Type

00h = Not Supported

4Bh

4Ch

4Dh

4Eh

0000h

0085h

0095h

Page Mode Type

00h = Not Supported

V^ACC(Acceleration) Supply Minimum

DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV

VACC (Acceleration) Supply Maximum

DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV

Boot Type

02h = MBM29DL32XBE

03h = MBM29DL32XTE

4Fh

50h

00XXh

0001h

Program Suspend

01h = Supported

34

MBM29DL32XTE/BE⁸⁰/90

■ FUNCTIONAL DESCRIPTION

• Simultaneous Operation

MBM29DL32XTE/BE have feature, which is capability of reading data from one bank of memory while a program

or erase operation is in progress in the other bank of memory (simultaneous operation) , in addition to the

conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . The bank

selection can be selected by bank address (A²⁰to A15) with zero latency.

The MBM29DL322TE/BE have two banks which contain

Bank 1 (8 KB × eight sectors, 64 KB × seven sectors) and Bank 2 (64 KB × fifty-six sectors) .

The MBM29DL323TE/BE have two banks which contain

Bank 1 (8 KB × eight sectors, 64 KB × fifteen sectors) and Bank 2 (64 KB × forty-eight sectors) .

The MBM29DL324TE/BE have two banks which contain

Bank 1 (8 KB × eight sectors, 64 KB × thirty-one sectors) and Bank 2 (64 KB × thirty-two sectors) .

The simultaneous operation can not execute multi-function mode in the same bank. “Simultaneous Operation”

in “■ FUNCTIONAL DESCRIPTION” shows combination to be possible for simultaneous operation. (Refer to

the “Bank-to-bank Read/Write Timing Diagram” in “■ TIMING DIAGRAM”.)

Simultaneous Operation

Case

Bank 1 status

Read Mode

Bank 2 status

Read Mode

1

2

3

4

5

6

7

Read Mode

Autoselect Mode

Program Mode

Erase Mode *

Read Mode

Autoselect Mode

Program Mode

Erase Mode *

Read Mode

* : By writing erase suspend command on the bank address of sector being erased, the erase operation gets

suspended so that it enables reading from or programming the remaining sectors.

• Read Mode

TheMBM29DL32XTE/BEhave twocontrolfunctionswhichmustbesatisfiedinordertoobtaindataattheoutputs.

CE is the power control and should be used for a device selection. OE is the output control and should be used

to gate data to the output pins if a device is selected.

Address access time (t^ACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins (Assuming the

addresses have been stable for at least tACC-tOE time) . When reading out a data without changing addresses

after power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”

• Standby Mode

There are two ways to implement the standby mode on the MBM29DL32XTE/BE devices, one using both the

CE and RESET pins; the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.

Under this condition the current consumed is less than 5 µA Max During Embedded Algorithm operation, VCC

35

MBM29DL32XTE/BE⁸⁰/90

active current (I^CC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either

of these standby modes.

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE

= “H” or “L”) . Under this condition the current is consumed is less than 5 µA Max Once the RESET pin is taken

high, the device requires tRH of wake up time before outputs are valid for read access.

In the standby mode the outputs are in the high impedance state, independent of the OE input.

• Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of

MBM29DL32XTE/BE data. This mode can be used effectively with an application requested low power con-

sumption such as handy terminals.

To activate this mode, MBM29DL32XTE/BE automatically switch themselves to low power mode when

MBM29DL32XTE/BE addresses remain stably during access fine of 150 ns. It is not necessary to control CE,

WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level) .

During simultaneous operation, V^CCactive current (ICC2) is required.

Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,

the mode is canceled automatically and MBM29DL32XTE/BE read-out the data for changed addresses.

• Output Disable

With the OE input at a logic high level (VIH) , output from the devices are disabled. This will cause the output

pins to be in a high impedance state.

• Autoselect

The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer

and type. This mode is intended for use by programming equipment for the purpose of automatically matching

the devices to be programmed with its corresponding programming algorithm. This mode is functional over the

entire temperature range of the devices.

To activate this mode, the programming equipment must force V^ID(11.5 V to 12.5 V) on address pin A9. Two

identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All

addresses are DON’T CARES except A0, A1, and A6 (A-1) . (See “MBM29DL32XTE/BE User Bus Operations

(BYTE = VIH) ” and “MBM29DL32XTE/BE User Bus Operations (BYTE = VIL) ” in “■DEVICE BUS OPERATION”.)

The manufacturer and device codes may also be read via the command register, for instances when the

MBM29DL32XTE/BE are erased or programmed in a system without access to high voltage on the A⁹pin. The

command sequence is illustrated in “MBM29DL32XTE/BE Command Definitions” in “■ DEVICEBUS OPERA-

TION”. (Refer to Autoselect Command section.)

Byte 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device

identifier code (MBM29DL322TE = 55h and MBM29DL322BE = 56h for ×8 mode; MBM29DL322TE = 2255h

and MBM29DL322BE = 2256h for ×16 mode) . (MBM29DL323TE = 50h and MBM29DL323BE = 53h for ×8

mode; MBM29DL323TE = 2250h and MBM29DL323BE = 2253h for ×16

mode) . (MBM29DL324TE = 5Ch and MBM29DL324BE = 5Fh for ×8 mode; MBM29DL324TE = 225Ch and

MBM29DL324BE = 225Fh for ×16 mode) . These two bytes/words are given in “MBM29DL322/323/324TE/BE

Sector Group Protection Verify Autoselect Codes Tables”, “Extended Autoselect Code Tables” in “■ DEVICE

BUS OPERATION”. All identifiers for manufactures and device will exhibit odd parity with DQ⁷defined as the

parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See

“MBM29DL322/323/324TE/BE Sector Group Protection Verify Autoselect Codes Tables”, “Extended Autoselect

Code Tables” in “■ DEVICE BUS OPERATION”.)

36

MBM29DL32XTE/BE⁸⁰/90

• Write

Device erasure and programming are accomplished via the command register. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The com-

mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

whichever happens first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

• Sector Group Protection

The MBM29DL32XTE/BE feature hardware sector group protection. This feature will disable both program and

erase operations in any combination of twenty five sector groups of memory. (See “Sector Group

Addresses (MBM29DL32XTE) (Top Boot Block) ” and “Sector Group Addresses (MBM29DL32XBE) (Bottom

Boot Block) ” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”) . The sector group protection feature is

enabled using programming equipment at the user’s site. The device is shipped with all sector groups unpro-

tected.

To activate this mode, the programming equipment must force V^IDon address pin A9 and control pin OE, (suggest

VID = 11.5 V) , CE = VIL and A6 = A0 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A16, A15, A14,

A13, and A12) should be set to the sector to be protected. “Sector Address Table (MBM29DL322TE) ”, “Sector

Address Table (MBM29DL322BE) ”, “Sector Address Table (MBM29DL323TE) ”, “Sector Address Table

(MBM29DL323BE) ”, “Sector Address Table (MBM29DL324TE) ” and “Sector Address Table (MBM29DL324

BE) ” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE” define the sector address for each of the seventy

one (71) individual sectors, and “Sector Group Addresses (MBM29DL32XTE) (Top Boot Block) ” and “Sector

Group Addresses (MBM29DL32XBE) (Bottom Boot Block) ” in “■ FLEXIBLE SECTOR-ERASE ARCHITEC-

TURE” define the sector group address for each of the twenty five (25) individual group sectors. Programming

of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of

the same. Sector group addresses must be held constant during the WE pulse. See “Sector Group Protection

Timing Diagram” in “■ TIMING DIAGRAM” and “Sector Group Protection Algorithm” in “■ FLOW CHART” for

sector group protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V^IDon address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13,

and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector.

Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except

for A⁰, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer

and device codes. A-1 requires to apply to VIL on byte mode.

It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.

Performing a read operation at the address location XX02h, where the higher order addresses (A20, A19, A18, A17,

A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected

sector group. See “MBM29DL322/323/324TE/BE Sector Group Protection Verify Autoselect Codes Tables”,

“Extended Autoselect Code Tables” in “■ DEVICE BUS OPERATION” for Autoselect codes.

• Temporary Sector Group Unprotection

This feature allows temporary unprotection of previously protected sector groups of the MBM29DL32XTE/BE

devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to

high voltage (VID) . During this mode, formerly protected sector groups can be programmed or erased by selecting

the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector

groups will be protected again. Refer to “Temporary Sector Group Unprotection Timing Diagram” in “■ TIMING

DIAGRAM” and “Temporary Sector Group Unprotection Algorithm” in “■ FLOW CHART”.

37

MBM29DL32XTE/BE⁸⁰/90

• RESET

Hardware Reset

The MBM29DL32XTE/BE devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse

requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine.

Any operation in the process of being executed will be terminated and the internal state machine will be reset

to the read mode “tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the

devices require an additional “tRH” before it will allow read access. When the RESET pin is low, the devices will

be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware

reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please

note that the RY/BY output signal should be ignored during the RESET pulse. See “RESET, RY/BY Timing

Diagram” in “■ TIMING DIAGRAM” for the timing diagram. Refer to Temporary Sector Group Unprotection for

additional functionality.

• Byte/Word Configuration

The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL32XTE/BE devices. When

this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0

to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin

becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always

an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer

to “Timing Diagram for Word Mode Configuration”, “Timing Diagram for Byte Mode Configuration” and “BYTE

Timing Diagram for Write Operations” in “■ TIMING DIAGRAM” for the timing diagram.

• Boot Block Sector Protection

The Write Protection function provides a hardware method of protecting certain boot sectors without using V^ID.

This function is one of two provided by the WP/ACC pin.

If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two

“outermost” 8 Kbyte boot sectors (MBM29DL32XTE : SA69 and SA70, MBM29DL32XBE : SA0 and SA1)

independently of whether those sectors were protected or unprotected using the method described in “Sector

Group Protection”. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses

in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured

device.

If the system asserts V^IHon the WP/ACC pin, the device reverts to whether the two outermost 8 Kbyte boot

sectors were last set to be protected or unprotected. That is, sector group protection or unprotection for these

two sectors depends on whether they were last protected or unprotected using the method described in “Sector

Group Protection”.

• Accelerated Program Operation

MBM29DL32XTE/BE offers accelerated program operation which enables the programming in high speed.

If the system asserts V^ACCto the WP/ACC pin, the device automatically enters the acceleration mode and the

time required for program operation will reduce to about 60%. This function is primarily intended to allow high

speed program, so caution is needed as the sector group will temporarily be unprotected.

The system would use a fact program command sequence when programming during acceleration mode.

Set command to fast mode and reset command from fast mode are not necessary. When the device enters the

acceleration mode, the device automatically set to fast mode. Therefore, the present sequence could be used

for programming and detection of completion during acceleration mode.

Removing V^ACCfrom the WP/ACC pin returns the device to normal operation. Do not remove V^ACCfrom

WP/ACC pin while programming. See “Accelerated Program Timing Diagram” in “■ TIMING DIAGRAM”.

Erase operation during Accelerated Program Operation is strictly prohibited.

38

MBM29DL32XTE/BE⁸⁰/90

■ COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register. Some

commands are required Bank Address (BA) input. When command sequences are inputted to bank being read,

the commands have priority than reading. “MBM29DL32XTE/BE Command Definitions” in “■ DEVICEBUS

OPERATION” defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase

Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program

Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress.

Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please

note that commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.

• Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ⁵= 1) to Read/Reset mode, the

Read/Reset operation is initiated by writing the Read/Reset command sequence into the command register.

Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the

command register contents are altered.

The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not

required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures

that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read

Characteristics and Waveforms for the specific timing parameters.

• Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,

manufacture and device codes must be accessible while the devices reside in the target system. PROM pro-

grammers typically access the signature codes by raising A⁹to a high voltage. However, multiplexing high voltage

onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming method-

ology. The operation is initiated by writing the Autoselect command sequence into the command register.

The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write

cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device

codes can be read from the bank, and an actual data of memory cell can be read from the another bank.

Following the command write, a read cycle from address (BA) 00h retrieves the manufacture code of 04h. A

read cycle from address (BA) 01h for ×16 ( (BA) 02h for ×8) returns the device code (MBM29DL322TE = 55h

and MBM29DL322BE = 56h for ×8 mode; MBM29DL322TE = 2255h and MBM29DL322BE = 2256h for ×16

mode) . (MBM29DL323TE = 50h and MBM29DL323BE = 53h for ×8 mode; MBM29DL323TE = 2250h and

MBM29DL323BE = 2253h for ×16 mode) . (MBM29DL324TE = 5Ch and MBM29DL324BE = 5Fh for ×8 mode;

MBM29DL324TE = 225Ch and MBM29DL324BE = 225Fh for ×16

mode) . (See “MBM29DL322/323/324TE/BE Sector Group Protection Verify Autoselect Codes Tables”, “Ex-

tended Autoselect Code Tables” in “■ DEVICE BUS OPERATION”.)

All manufacturer and device codes will exhibit odd parity with DQ⁷defined as the parity bit. Sector state (protection

or unprotection) will be informed by address (BA) 02h for ×16 ( (BA) 04h for ×8) . Scanning the sector group

addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at

device output DQ0 for a protected sector group. The programming verification should be performed by verify

sector group protection on the protected sector. (See “Sector Address Table (MBM29DL324TE) ”, “Sector

Address Table (MBM29DL324BE) ”, “Sector Group Addresses (MBM29DL32XTE) (Top Boot Block) ” and

“Sector Group Addresses (MBM29DL32XBE) (Bottom Boot Block) ” in “■ FLEXIBLE SECTOR-ERASE AR-

CHITECTURE”.)

The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and

device codes and sector group protection status from non-selected bank, it is necessary to write Read/Reset

command sequence into the register and then Autoselect command should be written into the bank to be read.

39

MBM29DL32XTE/BE⁸⁰/90

If the software (program code) for Autoselect command is stored into the Flash memory, the device and manu-

facture codes should be read from the other bank where is not contain the software.

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and

also to write the Autoselect command during the operation, execute it after writing Read/Reset command se-

quence.

• Byte/Word Programming

The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle

operation. There are two “unlock” write cycles. These are followed by the program set-up command and data

write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is

latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever

happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,

the system is not required to provide further controls or timings. The device will automatically provide adequate

internally generated program pulses and verify the programmed cell margin.

The system can determine the status of the program operation by using DQ⁷(Data Polling) , DQ6 (Toggle Bit) ,

or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.

The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this

bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware

Sequence Flags” in “■ COMMAND DEFINITIONS”, Hardware Sequence Flags.) Therefore, the devices require

that a valid address to the devices be supplied by the system at this particular instance of time. Hence, Data

Polling must be performed at the memory location which is being programmed.

If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being

written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only

erase operations can convert “0”s to “1”s.

“Embedded Program^TMAlgorithm” in “■ FLOW CHART” illustrates the Embedded Program^TMAlgorithm using

typical command strings and bus operations.

• Program Suspend/Resume

The Profram Suspend command allows the system to interrupt a program operation so that data can be read

from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation

immediately suspends the programming. The Program Suspend command may also be issued during a pro-

gramming operation while an erase is suspended. The bank addresses of sector being programmed should be

set when writing the Program Suspend command.

When the Program Suspend command is written during a process, the device halts the program operation within

1 µs and updates the state bits.

After the program operation has been suspended, the system can read data from any address. The data at

program-suspended address is not valid. Normal read timing and command definitions apply.

After Program Resume command (30h) is written, the device reverts to programming. The bank address of

sectorsbeingsuspendedshouldbesetwhenwritingtheProgramResume command. Thesystemcandetermine

the program operation status using the DQ⁷or DQ6 status bits, just as in the standard program operation. See

“Write Operation Status” for more information.

The system may also write Autoselect command sequence when the device in the Program Suspend mode.

The device allows reading Autoselect codes at the addresses within programming sectors, since the codes are

not stored in the memory. When the device exits form the Autoselect mode, the device reverts to the Program

40

MBM29DL32XTE/BE⁸⁰/90

Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more infor-

mation.

The system must write the Program Resume command (address bits are “Bank Address”) to exit from the

Program Suspend mode and continue programming operation. Further writes of the Resume command are

ignored. Another Program Suspend command can be written after the device resumes programming.

• Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the devices will automatically program and verify the entire memory for an all

zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any

controls or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling) , DQ6 (Toggle Bit) , or

RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command

sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the

device returns to read the mode.

Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)

“Embedded Erase^TMAlgorithm” in “■ FLOW CHART” illustrates the Embedded Erase^TMAlgorithm using typical

command strings and bus operations.

• Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever

happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first.

After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will

begin.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29DL32XTE/BE

Command Definitions” in “■ DEVICEBUS OPERATION”. This sequence is followed with writes of the Sector

Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must

be less than “tTOW” otherwise that command will not be accepted and erasure will start. It is recommended that

processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled

after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CEor WE whichever

happens first will initiate the execution of the Sector Erase command (s) . If another falling edge of CE or WE,

whichever happens first occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine

if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Resetting the devices once

execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow

them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the

sector erase buffer may be done in any sequence and with any number of sectors (0 to 38) .

Sector erase does not require the user to program the devices prior to erase. The devices automatically program

all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing

a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any

controls or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling) , DQ6 (Toggle Bit) , or

RY/BY.

The sector erase begins after the “t^TOW” time out from the rising edge of CE or WE whichever happens first for

the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status

41

MBM29DL32XTE/BE⁸⁰/90

section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at

an address within any of the sectors being erased.

Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming) ] × Number of Sector

Erase

In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not perform.

“Embedded Erase^TMAlgorithm” in “■ FLOW CHART” illustrates the Embedded Erase^TMAlgorithm using typical

command strings and bus operations.

• Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads

from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase

operation which includes the time-out period for sector erase. Writing the Erase Suspend command (B0h) during

the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase

operation.

Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being

erasing or suspending should be set when writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum

of “t^SPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the

RY/BY output pin will be at high impedence state and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling.

The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation

has been suspended. Further writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode except that the data must be read from

sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the

device is in the erase-suspend-read mode will cause DQ²to toggle. (See the section on DQ2.)

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com-

mand sequence for Program. This program mode is known as the erase-suspend-program mode. Again, pro-

gramming in this mode is the same as programming in the regular Program mode except that the data must be

programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector

while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-

suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I

(DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address

while DQ6 can be read from any address within bank being erase-suspended.

To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase

suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend

command can be written after the chip has resumed erasing.

• Extended Command

(1) Fast Mode

MBM29DL32XTE/BE has Fast Mode function. This mode dispenses with the initial two unclock cycles required

in the standard program command sequence by writing Fast Mode command into the command register. In this

mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program

command. (Do not write erase command in this mode.) The read operation is also executed after exiting this

mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. The first

cycle must contain the bank address. (Refer to the “Extended Sector Group Protection Algorithm” in “■ FLOW

CHART”.) The V^CCactive current is required even CE = VIH during Fast Mode.

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MBM29DL32XTE/BE⁸⁰/90

(2) Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program

Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) . (Refer to the

“Extended Sector Group Protection Algorithm” in “■ FLOW CHART”.)

(3) Extended Sector Group Protection

In addition to normal sector group protection, the MBM29DL32XTE/BE has Extended Sector Group Protection

as extended function. This function enable to protect sector group by forcing V^IDon RESET pin and write a

command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control

pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group

protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command

(60h) into the command register. Then, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and

A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the

other addresses pins) , and write extended sector group protection command (60h) . A sector group is typically

protected in 250 µs. To verify programming of the protection circuitry, the sector group addresses pins (A20, A19,

A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h) . Following

the command write, a logical “1” at device output DQ0 will produce for protected sector in the read operation. If

the output data is logical “0”, please repeat to write extended sector group protection command (60h) again. To

terminate the operation, it is necessary to set RESET pin to VIH. (Refer to the “Extended Sector Group Protection

Timing Diagram” in “■ TIMING DIAGRAM” and “Extended Sector Group Protection Algorithm” in “■ FLOW

CHART”.)

(4) CFI (Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation

handshake which allows specific vendor-specified software algorithms to be used for entire families of devices.

This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software sup-

port for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98h) into the command register. The bank address

should be set when writing this command. Then the device information can be read from the bank, and an actual

data of memory cell be read from the another bank. Following the command write, a read cycle from specific

address retrieves device information. Please note that output data of upper byte (DQ¹⁵to DQ8) is “0” in word

mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary to write the read/reset

command sequence into the register. (See “Common Flash Memory Interface Code” in “■ FLEXIBLE SECTOR-

ERASE ARCHITECTURE”.)

• HiddenROM Region

The HiddenROM feature provides a Flash memory region that the system may access through a new command

sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the

device with the ESN protected against modification. Once the HiddenROM region is protected, any further

modification of that region is impossible. This ensures the security of the ESN once the product is shipped to

the field.

The HiddenROM region is 64 Kbytes in length and is stored at the same address of the 8 KB ×8 sectors. The

MBM29DL32XTE occupies the address of the byte mode 3F0000h to 3FFFFFh (word mode 1F8000h to

1FFFFFh) and the MBM29DL32XBE type occupies the address of the byte mode 000000h to 00FFFFh (word

mode 000000h to 007FFFh) . After the system has written the Enter HiddenROM command sequence, the

system may read the HiddenROM region by using the addresses normally occupied by the boot sectors. That

is, the device sends all commands that would normally be sent to the boot sectors to the HiddenROM region.

This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until

power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending

commands to the boot sectors.

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MBM29DL32XTE/BE⁸⁰/90

When reading the HiddenROM region, either change addresses or change CE pin from “H” to “L”. The same

procedure should be taken (changing addresses or CE pin from “H” to “L”) after the system issues the Exit

HiddenROM command sequence to read actual data of memory cell.

• HiddenROM Entry Command

MBM29DL32XTE/BE has a HiddenROM area with One Time Protect function. This area is to enter the security

code and to unable the change of the code once set. Program/erase is possible in this area until it is protected.

However, once it is protected, it is impossible to unprotect, so please use this with caution.

HiddenROM area is 64 KByte and in the same address area of 8 KB sector. The address of top boot is 3F0000h

to 3FFFFFh at byte mode (1F8000h to 1FFFFFh at word mode) and the bottom boot is 000000h to 00FFFFh

at byte mode (000000h to 007FFFh at word mode) . These areas are normally the boot block area (8 KB ×8

sector) . Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. It is called

as HiddenROM mode when the HiddenROM area appears.

Sector other than the boot block area could be read during HiddenROM mode. Read/program/erase of the

HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit

the HiddenROM mode. The bank address of the HiddenROM should be set on the third cycle of this reset

command sequence.

• HiddenROM Program Command

To program the data to the HiddenROM area, write the HiddenROM program command sequence during

HiddenROM mode. This command is same as the program command in the past except to write the command

during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the

DQ⁷data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the address to be programmed. If the

address other than the HiddenROM area is selected to program, the data of the address will be changed.

• HiddenROM Erase Command

To erase the HiddenROM area, write the HiddenROM erase command sequence during HiddenROM mode.

This command is same as the sector erase command in the past except to write the command during

HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ⁷data

poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the sector address to be erased. If the sector

address other than the HiddenROM area is selected, the data of the sector will be changed.

• HiddenROM Protect Command

There are two methods to protect the HiddenROM area. One is to write the sector group protect setup command

(60h) , set the sector address in the HiddenROM area and (A⁶, A¹, A⁰) = (0, 1, 0) , and write the sector group

protect command (60h) during the HiddenROM mode. The same command sequence could be used because

except that it is in the HiddenROM mode and that it does not apply high voltage to RESET pin, it is the same as

the extension sector group protect in the past. Please refer to “Function Explanation Extended Command (3)

Extended Sector Group Protection” for details of extension sector group protect setting.

The other is to apply high voltage (V^ID) to A9 and OE, set the sector address in the HiddenROM area and (A⁶,

A¹, A⁰) = (0, 1, 0) , and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply

high voltage (V^ID) to A9, specify (A⁶, A¹, A⁰) = (0, 1, 0) and the sector address in the HiddenROM area, and

read. When “1” appears to DQ0, the protect setting is completed. “0” will appear to DQ0 if it is not protected.

Please apply write pulse again. The same command sequence could be used for the above method because

other than the HiddenROM mode, it is the same as the sector group protect in the past. Please refer to “Function

Explanation Sector Group Protection” for details of sector group protect setting

Other sector group will be effected if the address other than the HiddenROM area is selected for the sector group

address, so please be careful. Once it is protected, protection can not be cancelled, so please pay closest

attention.

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MBM29DL32XTE/BE⁸⁰/90

• Write Operation Status

Detailed in “Hardware Sequence Flags” in “■ COMMAND DEFINITIONS” are all the status flags that can

determine the status of the bank for the current mode operation. The read operation from the bank where is not

operate Embedded Algorithm returns a data of memory cell. These bits offer a method for determining whether

a Embedded Algorithm is completed properly. The information on DQ²is address sensitive. This means that if

an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However, DQ2 will not

toggle if an address from a non-erasing sector is consecutively read. This allows the user to determine which

sectors are erasing and which are not.

The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there

is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] < busy

bank > , [2] < non-busy bank > , [3] < busy bank > , the DQ⁶is toggling in the case of [1] and [3]. In case of [2],

the data of memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ6 will

not be toggled in the [1] and [3].

In the erase suspend read mode, DQ²is toggled in the [1] and [3]. In case of [2], the data of memory cell is

outputted.

Hardware Sequence Flags

Status

Embedded Program Algorithm

Embedded Erase Algorithm

DQ⁷

DQ⁶

DQ⁵DQ³

DQ²

1

DQ⁷Toggle

0

1

0

1

Toggle

1

Toggle*¹

Erase Suspend Read

0

Toggle

Data

1*²

(Erase Suspended Sector)

Erase

Erase Suspend Read

Suspended

Data Data Data Data

DQ⁷Toggle

(Non-Erase Suspended Sector)

In Progress Mode

Erase Suspend Program

(Non-Erase Suspended Sector)

0

Program Suspend Read

(Program Suspended Sector)

Data Data Data Data

Data

Program

Suspended

Mode

Program Suspend Read

(Non-Program Suspended Sector)

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

DQ⁷Toggle

Toggle

1

0

1

0

N/A

Exceeded

Time Limits

Erase Suspend Program

Suspended

Mode

DQ⁷Toggle

1

0

N/A

(Non-Erase Suspended Sector)

*1 : Successive reads from the erasing or erase-suspend sector causes DQ²to toggle.

*2 : Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit.

• DQ⁷

Data Polling

The MBM29DL32XTE/BE devices feature Data Polling as a method to indicate to the host that the Embedded

Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the

devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program

Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded

Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the

45

MBM29DL32XTE/BE⁸⁰/90

Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ⁷output. The flowchart

for Data Polling (DQ7) is shown in “Data Polling Algorithm” in “■ FLOW CHART”.

For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse

sequence.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. Data Polling also works as a flag to indicate whether the device is in erase-suspended

mode. DQ7 goes from “0” to “1” during erase-suspended mode. Notice that to determine DQ7 entering erase-

suspended mode, indicate the sector adress of sector being erased. Data Polling must be performed at sector

address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid.

If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then

that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for

erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode.

Once the Embedded Algorithm operation is close to being completed, the MBM29DL32XTE/BE data pins (DQ⁷)

may change asynchronously while the output enable (OE) is asserted low. This means that the devices are

driving status information on DQ⁷at one instant of time and then that byte’s valid data at the next instant of time.

Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device

has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6

may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts.

TheDataPollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm, EmbeddedEraseAlgorithm

or sector erase time-out. (See “Hardware Sequence Flags” in “■ COMMAND DEFINITIONS”.)

See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “■ TIMING DIAGRAM” for the Data

Polling timing specifications and diagrams.

• DQ⁶

Toggle Bit I

The MBM29DL32XTE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the

Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from

the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During

programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.

For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop

toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the

ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs

and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will

cause the DQ6 to toggle.

The system can use DQ6 to determine whether a sector is actively erasing or is erase-suspended. When a bank

is actively erasing (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters

the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during the erase-suspend-program cause

DQ6 to toggle.

To operate toggle bit function properly, CE or OE must be high when bank address is changed.

See “Toggle Bit I during Embedded Algorithm Operation Timing Diagram” in “■TIMING DIAGRAM” for the Toggle

Bit I timing specifications and diagrams.

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MBM29DL32XTE/BE⁸⁰/90

• DQ⁵

Exceeded Timing Limits

DQ⁵will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under

these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling is the only operating function of the devices under this

condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA) .

The OE and WE pins will control the output disable functions as described in “MBM29DL32XTE/BE User Bus

Operations (BYTE = VIH) ” and “MBM29DL32XTE/BE User Bus Operations (BYTE = VIL) ” in “■ DEVICE BUS

OPERATION”.

The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this

case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never

reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the

DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly

used. If this occurs, reset the device with command sequence.

• DQ³

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ³will

remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase

command sequence.

If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may

be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled

erase cycle has begun. If DQ3 is low (“0”) the device will accept additional sector erase commands. To insure

the command has been accepted, the system software should check the status of DQ3 prior to and following

each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not

have been accepted.

See “Hardware Sequence Flags” in “■ COMMAND DEFINITIONS” : Hardware Sequence Flags.

• DQ²

Toggle Bit II

This toggle bit II, along with DQ⁶, can be used to determine whether the devices are in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the

devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.

DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized

as follows :

For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

(DQ2 toggles while DQ6 does not.) See also “Toggle Bit Status” in “■ COMMAND DEFINITIONS” and “DQ2 vs.

DQ6” in “■ TIMING DIAGRAM”.

Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase

mode, DQ2 toggles if this bit is read from an erasing sector.

To operate toggle bit function properly, CE or OE must be high when bank address is changed.

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MBM29DL32XTE/BE⁸⁰/90

Reading Toggle Bits DQ⁶/DQ²

Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row

to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit

after the first read. After the second read, the system would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can

read array data on DQ7 to DQ0 on the following read cycle.

However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system

also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then

determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5

went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase

operation. If it is still toggling, the device did not complete the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ⁵has not

gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, deter-

mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system

tasks. In this case, the system must start at the begining of the algorithm when it returns to determine the status

of the operation. (Refer to “Toggle Bit Algorithm” in “■ FLOW CHART”.)

Toggle Bit Status

Mode

DQ⁷

DQ7

0

DQ⁶

DQ²

1

Program

Erase

Toggle

Toggle*¹

Erase-Suspend Read

(Erase-Suspended Sector)

1

Toggle

1*²

Erase-Suspend Program

DQ⁷

Toggle

*1 : Successive reads from the erasing or erase-suspend sector will cause DQ²to toggle.

*2 : Reading from the non-erase suspend sector address will indicate logic “1” at the DQ2 bit.

• RY/BY

Ready/Busy

The MBM29DL32XTE/BE provide a RY/BY open-drain output pin as a way to indicate to the host system that

the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are

busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/

write or erase operation. If the MBM29DL32XTE/BE are placed in an Erase Suspend mode, the RY/BY output

will be high.

During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate

a busy condition during the RESET pulse. Refer to “RY/BY Timing Diagram during Program/Erase Operations”

and“RESET, RY/BYTimingDiagram”foradetailedtimingdiagram. TheRY/BYpinispulledhighinstandbymode.

Since this is an open-drain output, the pull-up resistor needs to be connected to VCC; multiples of devices may

be connected to the host system via more than one RY/BY pin in parallel.

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MBM29DL32XTE/BE⁸⁰/90

• Data Protection

The MBM29DL32XTE/BE are designed to offer protection against accidental erasure or programming caused

by spurious system level signals that may exist during power transitions. During power up the devices automat-

ically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of

the memory contents only occurs after successful completion of specific multi-bus cycle command sequences.

The devices also incorporate several features to prevent inadvertent write cycles resulting form V^CCpower-up

and power-down transitions or system noise.

• Low V^CCWrite Inhibit

To avoid initiation of a write cycle during V^CCpower-up and power-down, a write cycle is locked out for VCC less

than VLKO (Min) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are

disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the

VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to

prevent unintentional writes when V^CCis above VLKO (Min) .

If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used.

• Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.

• Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

• Power-Up Write Inhibit

Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

• Sector Group Protection

Device user is able to protect each sector group individually to store and protect data. Protection circuit voids

both write and erase commands that are addressed to protected sectors.

Any commands to write or erase addressed to protected sector are ignored (see “■ FUNCTIONAL DESCRIP-

TION Sector Group Protection”)

49

MBM29DL32XTE/BE⁸⁰/90

■ ABSOLUTE MAXIMUM RATINGS (See WARNING)

Rating

Parameter

Symbol

Unit

Min

−55

−40

Max

+125

+85

Storage Temperature

T^stg

°C

Ambient Temperature with Power Applied

TA

Voltage with Respect to Ground All pins except

A⁹, OE, RESET *^1,*²

VIN, VOUT

−0.5

VCC + 0.5

V

Power Supply Voltage *¹

A9, OE, and RESET *^1,*³

WP/ACC *^1,*⁴

VCC

VIN

−0.5

+4.0

+13.0

+10.5

V

VACC

*1 : Voltage is defined on the basis of VSS = GND = 0 V.

*2 : Minimum DC voltage on input or I/O pins is −0.5 V. During voltage transitions, input or I/O pins may undershoot

VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage

transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns.

*3 : Minimum DC input voltage on A9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and RESET

pinsmayundershootVSS to−2.0Vforperiodsofupto20ns. Voltagedifferencebetweeninputandsupplyvoltage

(VIN − VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which

may overshoot to +14.0 V for periods of up to 20 ns.

*4 : Minimum DC input voltage on WP/ACC pin is −0.5 V. During voltage transitions, WP/ACC pin may undershoot

VSS to −2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may

overshoot to +12.0 V for periods of up to 20 ns when Vcc is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Ambient Temperature

Power Supply Voltage*

Symbol

T^A

Conditions

Unit

Min

−40

Max

+85

MBM29DL32XTE/BE80/90

MBM29DL32XTE/BE80

MBM29DL32XTE/BE90

°C

V

+3.0

+2.7

+3.6

V^CC

V

* : Voltage is defined on the basis of VSS = GND = 0 V.

Note : Operating ranges define those limits between which the functionality of the devices are guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

50

MBM29DL32XTE/BE⁸⁰/90

■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT

20 ns

+0.6 V

−0.5 V

−2.0 V

20 ns

Maximum Undershoot Waveform

20 ns

V^CC+ 2.0 V

VCC + 0.5 V

+2.0 V

20 ns

Maximum Overshoot Waveform 1

20 ns

+14.0 V

+13.0 V

V^CC+ 0.5 V

20 ns

Note : This waveform is applied for A⁹, OE, and RESET.

Maximum Overshoot Waveform 2

51

MBM29DL32XTE/BE⁸⁰/90

■ DC CHARACTERISTICS

Value

Parameter

Input Leakage Current

Symbol

Conditions

Unit

Min Typ Max

I^LI

VIN = VSS to VCC, VCC = VCC Max −1.0

VOUT = VSS to VCC, VCC = VCC Max −1.0

+1.0 µA

Output Leakage Current

I^LO

VCC = VCC Max,

A9, OE, RESET = 12.5 V

A⁹, OE, RESET Inputs Leakage Current

ILIT

ILIA

+35 µA

VCC = VCC Max,

WP/ACC = VACC Max

WP/ACC Accelerated Program Current

V^CCActive Current *¹

20

mA

Byte

Word

Byte

16

18

7

CE = VIL, OE = VIH,

f = 5 MHz

ICC1

CE = VIL, OE = VIH,

f = 1 MHz

mA

Word

7

V^CCActive Current *²

V^CCCurrent (Standby)

ICC2

ICC3

CE = VIL, OE = VIH

35

VCC = VCC Max, CE = VCC ± 0.3

V, RESET = VCC ± 0.3 V,

WP/ACC = VCC ± 0.3 V

1

5

µA

VCC = VCC Max,

RESET = VSS ± 0.3 V

V^CCCurrent (Standby, Reset)

ICC4

ICC5

VCC = VCC Max, CE = VSS ± 0.3 V,

RESET = VCC ± 0.3 V,

VIN = VCC ± 0.3 V or VSS ± 0.3 V

V^CCCurrent

(Automatic Sleep Mode) *⁵

VCC Active Current *⁶

(Read-While-Program)

Byte

CE = VIL, OE = VIH

Word

51

53

51

53

ICC6

ICC7

mA

V^CCActive Current *⁶

(Read-While-Erase)

Byte

CE = VIL, OE = VIH

Word

V^CCActive Current

(Erase-Suspend-Program)

ICC8

V^IL

CE = VIL, OE = VIH

35

mA

V

Input Low Voltage

−0.5

+ 0.6

VCC +

0.3

Input High Voltage

V^IH

2.0

V

Voltage for Autoselect and Sector Group

Protection (A⁹, OE, RESET) *^3,*⁴

VID

11.5

8.5

12

12.5

V

Voltage for WP/ACC Sector Group Protection/

Unprotection and Program Acceleration *⁴

VACC

9.0

9.5

Output Low Voltage

V^OL

IOL = 4.0 mA, VCC = VCC Min

IOH = −2.0 mA, VCC = VCC Min

0.45

V

V^OH1

2.4

Output High Voltage

Low V^CCLock-Out Voltage

VCC −

0.4

V^OH2

IOH = −100 µA

V

VLKO

2.3

2.4

2.5

*1 : The ICC current listed includes both the DC operating current and the frequency dependent component.

*2 : I^CCactive while Embedded Algorithm (program or erase) is in progress.

*3 : This timing is only for Sector Group Protection operation and Autoselect mode.

*4 : Applicable for only V^CC.

*5 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

*6 : Embedded Algorithm (program or erase) is in progress. (@5 MHz)

52

MBM29DL32XTE/BE⁸⁰/90

■ AC CHARACTERISTICS

Value (Note)

Test

setup

Symbol

Parameter

80

90

Unit

JEDEC

t^AVAV

Standard

Min

Max

Min

Max

Read Cycle Time

tRC

80

90

ns

CE = VIL

OE = VIL

Address to Output Delay

t^AVQV

tACC

80

90

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

t^ELQV

tGLQV

t^EHQZ

t^GHQZ

tCE

tOE

tDF

OE = VIL

80

30

25

90

35

30

ns

Output Hold Time from Addresses,

CE or OE, Whichever Occurs First

tAXQX

tOH

0

ns

µs

ns

RESET Pin Low to Read Mode

tREADY

20

5

20

5

tELFL

tELFH

CE to BYTE Switching Low or High

Note : Test Conditions :

Output Load : 1 TTL gate and 30 pF (MBM29DL32XTE/BE80)

1 TTL gate and 100 pF (MBM29DL32XTE/BE90)

Input rise and fall times : 5 ns

Input pulse levels : 0.0 V or 3.0 V

Timing measurement reference level

Input : 1.5 V

Output : 1.5 V

3.3 V

Diode = 1N3064

or Equivalent

2.7 kΩ

Device

Under

Test

6.2 kΩ

CL

Diode = 1N3064

or Equivalent

Notes : • C^L= 30 pF including jig capacitance (MB29DL32XTE/BE80)

• CL = 100 pF including jig capacitance (MB29DL32XTE/BE90)

Test Conditions

53

MBM29DL32XTE/BE⁸⁰/90

• Write/Erase/Program Operations

Value

Symbol

Parameter

80

90

Unit

Standard

JEDEC

t^AVAV

t^AVWL

Min Typ Max Min Typ Max

Write Cycle Time

tWC

tAS

80

0

90

0

ns

Address Setup Time

Address Setup Time to OE Low During

Toggle Bit Polling

tASO

tAH

12

45

0

15

45

0

ns

Address Hold Time

t^WLAX

Address Hold Time from CE or OE High

During Toggle Bit Polling

tAHT

Data Setup Time

Data Hold Time

t^DVWH

t^WHDX

tDS

tDH

30

0

35

0

ns

Read

0

ns

Output Enable

Hold Time

t^OEH

Toggle and Data Polling

10

20

0

10

20

0

ns

CE High During Toggle Bit Polling

OE High During Toggle Bit Polling

Read Recover Time Before Write

CE Setup Time

tCEPH

tOEPH

tGHWL

tGHEL

tCS

ns

t^GHWL

t^GHEL

tELWL

tWLEL

tWHEH

tEHWH

t^WLWH

tELEH

t^WHWL

tEHEL

ns

0

ns

0

ns

WE Setup Time

tWS

0

ns

CE Hold Time

tCH

0

ns

WE Hold Time

tWH

0

ns

Write Pulse Width

tWP

35

25

35

30

ns

CE Pulse Width

tCP

ns

Write Pulse Width High

CE Pulse Width High

tWPH

tCPH

ns

Byte

8

16

1

8

16

1

µs

Programming

Operation

t^WHWH1

tWHWH1

Word

µs

Sector Erase Operation*¹

tWHWH2

tVCS

s

V^CCSetup Time

50

500

4

50

500

4

µs

Rise Time to V^ID*²

Rise Time to V^ACC*³

tVIDR

tVACCR

tVLHT

tWPP

tOESP

tCSP

ns

Voltage Transition Time*²

Write Pulse Width*²

OE Setup Time to WE Active*²

CE Setup Time to WE Active*²

Recover Time from RY/BY

RESET Pulse Width

µs

100

4

100

4

µs

4

µs

ns

tRB

0

tRP

500

ns

(Continued)

54

MBM29DL32XTE/BE⁸⁰/90

(Continued)

Value

Symbol

Standard

Parameter

80

Min Typ Max Min Typ Max

200 200

90

Unit

JEDEC

RESET High Level Period before Read

BYTE Switching Low to Output High-Z

BYTE Switching High to Output Active

Program/Erase Valid to RY/BY Delay

Delay Time from Embedded Output Enable

Erase Time-Out Time

tRH

ns

µs

tFLQZ

tFHQV

tBUSY

t^EOE

30

80

90

80

30

90

t^TOW

tSPD

50

Erase Suspend Transition Time

20

*1 : This does not include preprogramming time.

*2 : This timing is for Sector Group Protection operation.

*3 : This timing is limited for Acclerated Program Operation only.

55

MBM29DL32XTE/BE⁸⁰/90

■ ERASE AND PROGRAMMING PERFORMANCE

Limit

Parameter

Unit

Comments

Min

Typ

Max

Excludes programming time

prior to erasure

Sector Erase Time

1

10

s

Word Programming Time

Byte Programming Time

16

8

360

300

µs

Excludes system-level

overhead

Excludes system-level

overhead

Chip Programming Time

Program/Erase Cycle

100

s

100,000

cycle

■ PIN CAPACITANCE

Parameter

Input Capacitance

Symbol

Test setup

Typ

6.0

Max

7.5

Unit

pF

C^IN

C^OUT

CIN2

CIN3

VIN = 0

Output Capacitance

Control Pin Capacitance

WP/ACC Pin Capacitance

VOUT = 0

VIN = 0

8.5

12.0

11.0

22.5

pF

8.0

pF

21.5

pF

Notes : • Test conditions TA = +25 °C, f = 1.0 MHz

• DQ15/A-1 pin capacitance is stipulated by output capacitance.

■ FBGA PIN CAPACITANCE

Parameter

Input Capacitance

Symbol

C^IN

Condition

Typ

7.0

Max

9.0

Unit

pF

VIN = 0

Output Capacitance

COUT

CIN2

VOUT = 0

VIN = 0

9.5

13.0

12.0

22.5

pF

Control Pin Capacitance

WP/ACC Pin Capacitance

9.0

pF

CIN3

21.5

pF

Notes : • Test conditions TA = +25 °C, f = 1.0 MHz

• DQ15/A-1 pin capacitance is stipulated by output capacitance.

56

MBM29DL32XTE/BE⁸⁰/90

■ TIMING DIAGRAM

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Must Be

Steady

Will Be

Steady

May

Change

Will

Change

from H to L

May

Change

from L to H

Will

Change

from L to H

"H" or "L"

Any Change

Permitted

Changing

State

Unknown

Does Not

Apply

Center Line is

High-

Impedance

"Off" State

tRC

Address

Address Stable

tACC

CE

OE

tOE

tDF

tOEH

WE

tOH

tCE

High-Z

Outputs

Output Valid

Read Operation Timing Diagram

57

MBM29DL32XTE/BE⁸⁰/90

tRC

Address

Address Stable

tACC

CE

tRH

tRP

tRH

tCE

RESET

Outputs

tOH

High-Z

Outputs Valid

Hardware Reset/Read Operation Timing Diagram

58

MBM29DL32XTE/BE⁸⁰/90

Data Polling

3rd Bus Cycle

555h

Address

PA

tWC

tRC

tAS

tAH

CE

tCH

tCS

tCE

OE

tWP

tWPH

tOE

tGHWL

tWHWH1

WE

tOH

tDF

tDS

tDH

A0h

PD

DQ7

DOUT

Data

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at byte address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Alternate WE Controlled Program Operation Timing Diagram

59

MBM29DL32XTE/BE⁸⁰/90

3rd Bus Cycle

Data Polling

Address

555h

PA

tWC

tAS

tAH

WE

tWS

tWH

OE

CE

tGHEL

tCP

tCPH

tWHWH1

tDS

tDH

A0h

PD

DQ7

DOUT

Data

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at byte address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Alternate CE Controlled Program Operation Timing Diagram

60

MBM29DL32XTE/BE⁸⁰/90

2AAh

555h

Address

555h

tWC

2AAh

SA*

tAS

tAH

CE

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

10 for chip Erase

10h/

30h

AAh

55h

80h

AAh

55h

Data

VCC

tVCS

* : SA is the sector address for Sector Erase. Addresses = 555h (Word) , AAAh (Byte) for Chip Erase.

Note : These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Chip/Sector Erase Operation Timing Diagram

61

MBM29DL32XTE/BE⁸⁰/90

CE

tCH

tOE

tDF

OE

tOEH

WE

tCE

*

High-Z

DQ7 =

Data

DQ7

DQ⁷

Valid Data

tWHWH1 or 2

DQ6 to DQ0

Valid Data

Data

DQ6 to DQ0

RY/BY

DQ6 to DQ0 = Output Flag

tBUSY

tEOE

* : DQ7 = Valid Data (The device has completed the Embedded operation) .

Data Polling during Embedded Algorithm Operation Timing Diagram

62

MBM29DL32XTE/BE⁸⁰/90

Address

CE

tAHT tASO

tAHT tAS

tCEPH

WE

tOEPH

tOEH

OE

tOE

tCE

tDH

*

Stop

Toggling

Output

Valid

Toggle

Data

Toggle

Data

Toggle

Data

DQ6/DQ2

Data

tBUSY

RY/BY

* : DQ6 stops toggling (The device has completed the Embedded operation) .

Toggle Bit I during Embedded Algorithm Operation Timing Diagram

63

MBM29DL32XTE/BE⁸⁰/90

Read

tRC

Command

tWC

Read

tRC

Command

tWC

Read

tRC

Read

tRC

BA2

(PA)

BA2

(PA)

Address

CE

BA1

(555h)

tACC

tCE

tAS

tAH

tAHT

tOE

tCEPH

OE

WE

DQ

tDF

tGHWL

tOEH

tWP

tDH

tDS

tDF

Valid

Output

Valid

Intput

Valid

Output

Valid

Intput

Valid

Output

Status

(A0h)

(PD)

Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1 : Address corresponding to Bank 1

BA2 : Address corresponding to Bank 2

Bank-to-bank Read/Write Timing Diagram

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

WE

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase Suspend

Read

Erase

Complete

DQ⁶

DQ2*

Toggle

DQ2 and DQ6

with OE or CE

* : DQ2 is read from the erase-suspended sector.

DQ²vs. DQ⁶

64

MBM29DL32XTE/BE⁸⁰/90

CE

Rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

tBUSY

RY/BY Timing Diagram during Program/Erase Operations

WE

RESET

tRP

tRB

RY/BY

tREADY

RESET, RY/BY Timing Diagram

65

MBM29DL32XTE/BE⁸⁰/90

CE

tCE

BYTE

Data Output

(DQ14 to DQ0)

DQ14 to DQ0

(DQ7 to DQ0)

tELFH

tFHQV

A-1

DQ15

DQ15/A-1

Timing Diagram for Word Mode Configuration

CE

BYTE

tELFL

DQ14 to DQ0

Data Output

(DQ7 to DQ0)

Data Output

(DQ14 to DQ0)

tACC

DQ15/A-1

A-1

DQ15

tFLQZ

Timing Diagram for Byte Mode Configuration

Falling edge of the last write signal

CE or WE

Input

Valid

BYTE

tAS

tAH

BYTE Timing Diagram for Write Operations

66

MBM29DL32XTE/BE⁸⁰/90

A20, A19, A18

A17, A16, A15

A14, A13, A12

SPAX

SPAY

A6, A0

A1

VID

VIH

A9

tVLHT

V^ID

VIH

OE

WE

CE

tVLHT

tWPP

tOESP

tCSP

Data

VCC

01h

tVCS

tOE

SPAX : Sector Group Address to be protected

SPAY : Next Sector Group Address to be protected

Note : A-¹is VIL on byte mode.

Sector Group Protection Timing Diagram

67

MBM29DL32XTE/BE⁸⁰/90

VCC

tVIDR

tVCS

tVLHT

VID

VIH

RESET

CE

WE

tVLHT

Program or Erase Command Sequence

Unprotection period

RY/BY

Temporary Sector Group Unprotection Timing Diagram

68

MBM29DL32XTE/BE⁸⁰/90

VCC

tVCS

tVLHT

RESET

tWC

tVIDR

Address

SPAX

SPAY

A6, A0

A1

CE

OE

TIME-OUT

tWP

WE

60h

40h

01h

60h

Data

tOE

SPAX : Sector Group Address to be protected

SPAY : Next Sector Group Address to be protected

TIME-OUT : Time-Out window = 250 µs (Min)

Extended Sector Group Protection Timing Diagram

69

MBM29DL32XTE/BE⁸⁰/90

VCC

tVACCR

tVCS

tVLHT

VACC

VIH

WP/ACC

CE

WE

tVLHT

Program Command Sequence

Acceleration period

RY/BY

Accelerated Program Timing Diagram

70

MBM29DL32XTE/BE⁸⁰/90

■ FLOW CHART

EMBEDDED ALGORITHM

Start

Write Program

Command Sequence

(See Below)

Data Polling

Embedded

Program

Algorithm

in program

No

Verify Data

?

Yes

No

Increment Address

Last Address

?

Yes

Programming Completed

Program Command Sequence (Address/Command):

555h/AAh

2AAh/55h

555h/A0h

Program Address/Program Data

Notes : • The sequence is applied for ×16 mode.

• The addresses differ from ×8 mode.

Embedded Program^TMAlgorithm

71

MBM29DL32XTE/BE⁸⁰/90

EMBEDDED ALGORITHM

Start

Write Erase

Command Sequence

(See Below)

Data Polling

Embedded

Erase

Algorithm

in progress

No

Data = FFh

?

Yes

Erasure Completed

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

Chip Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

Sector Address

/30h

Sector Address

/30h

Additional sector

erase commands

are optional.

Sector Address

/30h

Notes : • The sequence is applied for ×16 mode.

• The addresses differ from ×8 mode.

Embedded Erase^TMAlgorithm

72

MBM29DL32XTE/BE⁸⁰/90

VA = Address for programming

= Any of the sector addresses

within the sector being erased

during sector erase or multiple

sector erases operation.

Start

Read Byte

(DQ7 to DQ0)

Addr. = VA

= Any of the sector addresses

within the sector not being

protected during chip erase

Yes

operation.

DQ7 = Data?

No

DQ5 = 1?

Yes

Read Byte

(DQ7 to DQ0)

Addr. = VA

Yes

DQ7 = Data?

*

No

Fail

Pass

* : DQ⁷is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Data Polling Algorithm

73

MBM29DL32XTE/BE⁸⁰/90

Start

*1

Read DQ7 to DQ0

Addr. = VA

VA = Bank address being executed

Embedded Algorithm.

Read DQ7 to DQ0

Addr. = VA

No

DQ6

= Toggle?

Yes

No

DQ5 = 1?

Yes

*1, 2

Read DQ7 to DQ0

Addr. = VA

Read DQ7 to DQ0

Addr. = VA

No

DQ6

= Toggle?

Yes

Program/Erase

Operation Not

Complete.Write

Reset Command

Program/Erase

Operation

Complete

*1 : Read toggle bit twice to determine whether it is toggling.

*2 : Recheck toggle bit because it may stop toggling as DQ⁵changes to “1”.

Toggle Bit Algorithm

74

MBM29DL32XTE/BE⁸⁰/90

Start

Setup Sector Group Addr.

A20, A19, A18, A17,A16,

(

)

A15, A14, A13, A12

PLSCNT = 1

OE = VID, A9 = VID

CE = VIL, RESET = VIH

A6 = A0 = VIL, A1 = VIH

Activate WE Pulse

Increment PLSCNT

Time out 100 µs

WE = VIH, CE = OE = VIL

(A9 should remain VID)

Read from Sector Group

Addr. = SPA, A1 = VIH

*

(

)

A6 = A0 = VIL

No

PLSCNT = 25?

Yes

No

Data = 01h?

Yes

Remove VID from A9

Write Reset Command

Protect Another Sector

Group?

No

Remove VID from A9

Write Reset Command

Device Failed

Sector Group Protection

Completed

* : A-¹is VIL on byte mode.

Sector Group Protection Algorithm

75

MBM29DL32XTE/BE⁸⁰/90

Start

RESET = VID

*1

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector Group

Unprotection Completed

*2

*1 : All protected sector groups are unprotected.

*2 : All previously protected sector groups are protected once again.

Temporary Sector Group Unprotection Algorithm

76

MBM29DL32XTE/BE⁸⁰/90

Start

RESET = VID

Wait to 4 µs

Device is Operating in

Temporary Sector Group

Unprotection Mode

No

Extended Sector Group

Protection Entry?

Yes

To Setup Sector Group Protection

Write XXXh/60h

PLSCNT = 1

To Protect Secter Group

Write 60h to Secter Address

(A6 = A0 = VIL, A1 = VIH)

Time out 250 µs

To Verify Sector Group Protection

Write 40h to Secter Address

(A6 = A0 = VIL, A1 = VIH)

Increment PLSCNT

Read from Sector Group Address

No

(A6 = A0 = VIL, A1 = VIH)

Setup Next Sector

Group Address

No

Data = 01h?

PLSCNT = 25?

Yes

Protect Other Sector

Group?

Remove VID from RESET

Write Reset Command

No

Remove VID from RESET

Write Reset Command

Device Failed

Sector Group

Protection Completed

Extended Sector Group Protection Algorithm

77

MBM29DL32XTE/BE⁸⁰/90

FAST MODE ALGORITHM

Start

555h/AAh

2AAh/55h

Set Fast Mode

555h/20h

XXXh/A0h

Program Address/Program Data

Data Polling

In Fast Program

No

Verify Data?

Yes

No

Last Address?

Yes

Increment Address

Programming Completed

(BA) XXXh/90h

XXXh/F0h

Reset Fast Mode

Note : The sequence is applied for ×16 mode.

The addresses differ from ×8 mode.

Embedded Programming Algorithm for Fast Mode

78

MBM29DL32XTE/BE⁸⁰^/90

■ ORDERING INFORMATION

Part No.

Package

Access Time (ns)

Remarks

48-pin plastic TSOP (1)

(FPT-48P-M19)

MBM29DL322TE80TN

MBM29DL322TE90TN

80

90

(Normal Bend)

48-pin plastic TSOP (1)

(FPT-48P-M19)

MBM29DL323TE80TN

MBM29DL323TE90TN

80

90

(Normal Bend)

48-pin plastic TSOP (1)

(FPT-48P-M19)

MBM29DL324TE90TN

90

(Normal Bend)

48-pin plastic TSOP (1)

(FPT-48P-M20)

MBM29DL322TE80TR

MBM29DL322TE90TR

80

90

(Reverse Bend)

Top Sector

48-pin plastic TSOP (1)

(FPT-48P-M20)

MBM29DL323TE80TR

MBM29DL323TE90TR

80

90

(Reverse Bend)

48-pin plastic TSOP (1)

(FPT-48P-M20)

MBM29DL324TE90TR

90

(Reverse Bend)

MBM29DL322TE80PBT

MBM29DL322TE90PBT

63-ball plastic FBGA

(BGA-63P-M01)

80

90

MBM29DL323TE80PBT

MBM29DL323TE90PBT

63-ball plastic FBGA

(BGA-63P-M01)

80

90

63-ball plastic FBGA

(BGA-63P-M01)

MBM29DL324TE90PBT

90

48-pin plastic TSOP (1)

(FPT-48P-M19)

MBM29DL322BE80TN

MBM29DL322BE90TN

80

90

(Normal Bend)

48-pin plastic TSOP (1)

(FPT-48P-M19)

MBM29DL323BE80TN

MBM29DL323BE90TN

80

90

(Normal Bend)

48-pin plastic TSOP (1)

(FPT-48P-M19)

MBM29DL324BE90TN

90

(Normal Bend)

Bottom Sector

48-pin plastic TSOP (1)

(FPT-48P-M20)

MBM29DL322BE80TR

MBM29DL322BE90TR

80

90

(Reverse Bend)

48-pin plastic TSOP (1)

(FPT-48P-M20)

MBM29DL323BE80TR

MBM29DL323BE90TR

80

90

(Reverse Bend)

48-pin plastic TSOP (1)

(FPT-48P-M20)

MBM29DL324BE90TR

90

(Reverse Bend)

(Continued)

79

MBM29DL32XTE/BE⁸⁰/90

(Continued)

Part No.

Package

Access Time (ns)

Remarks

MBM29DL322BE80PBT

MBM29DL322BE90PBT

80

90

63-ball plastic FBGA

(BGA-63P-M01)

MBM29DL323BE80PBT

MBM29DL323BE90PBT

80

90

63-ball plastic FBGA

(BGA-63P-M01)

Bottom Sector

63-ball plastic FBGA

(BGA-63P-M01)

MBM29DL324BE90PBT

90

MBM29DL32X

T

E

80

TN

PACKAGE TYPE

TN = 48-Pin Thin Small Outline Package

(TSOP (1) ) Normal Bend

TR = 48-Pin Thin Small Outline Package

(TSOP (1) ) Reverse Bend

PBT = Fine pitch Ball Grid Array

Package (FBGA)

SPEED OPTION

See Product Selector Guide

DEVICE REVISION

BOOT CODE SECTOR ARCHITECTURE

T = Top sector

B = Bottom sector

DEVICE NUMBER/DESCRIPTION

MBM29DL32X

32 Mega-bit (4 M × 8-Bit or 2 M × 16-Bit) CMOS Dual Operation Flash Memory

3.0 V-only Read, Program, and Erase

80

MBM29DL32XTE/BE⁸⁰/90

■ PACKAGE DIMENSIONS

Note 1) * : Values do not include resin protrusion.

48-pin plastic TSOP (1)

(FPT-48P-M19)

Resin protrusion and gate protrusion are +0.15(.006)Max(each side).

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

LEAD No.

1

48

INDEX

Details of "A" part

0.25(.010)

0~8˚

0.60±0.15

(.024±.006)

24

25

*

20.00±0.20

(.787±.008)

12.00±0.20

(.472±.008)

*18.40±0.20

(.724±.008)

1.10 –⁺0⁰.^.0¹5⁰

.043 –⁺.^.0⁰0⁰2⁴

(Mounting

height)

0.10±0.05

(.004±.002)

(Stand off height)

0.50(.020)

"A"

0.10(.004)

0.17 ^–⁺⁰⁰^.^.⁰⁰⁸³

0.22±0.05

(.009±.002)

M

0.10(.004)

.007 –⁺.^.0⁰0⁰3¹

C

2003 FUJITSU LIMITED F48029S-c-6-7

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

(Continued)

81

MBM29DL32XTE/BE⁸⁰/90

Note 1) * : Values do not include resin protrusion.

48-pin plastic TSOP (1)

(FPT-48P-M20)

Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) .

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

LEAD No.

1

48

Details of "A" part

INDEX

0.60±0.15

(.024±.006)

0~8˚

0.25(.010)

24

25

0.17 –⁺0⁰.^.0⁰8³

.007 –⁺.^.0⁰0⁰3¹

0.22±0.05

(.009±.002)

M

0.10(.004)

0.10±0.05

(.004±.002)

0.50(.020)

0.10(.004)

(Stand off height)

1.10 ⁺^–0⁰^.^.⁰¹⁵⁰

"A"

* 18.40±0.20

(.724±.008)

.043 ⁺^–.^.⁰⁰⁰⁰²⁴

(Mounting height)

20.00±0.20

(.787±.008)

* 12.00±0.20(.472±.008)

C

2003 FUJITSU LIMITED F48030S-c-6-7

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

(Continued)

82

MBM29DL32XTE/BE⁸⁰^/90

(Continued)

63-ball plastic FBGA

(BGA-63P-M01)

11.00±0.10(.433±.004)

1.05 –⁺0⁰.^.1¹0⁵

(8.80(.346))

(7.20(.283))

.041 –⁺.^.0⁰0⁰4⁶

(Mounting height)

0.38±0.10

(.015±.004)

(Stand off)

(5.60(.220))

0.80(.031)TYP

8

7

6

5

4

3

2

1

(4.00(.157))

(5.60(.220))

7.00±0.10

(.276±.004)

M

L

K

J

H

G

F

E

D

C

B

A

INDEX AREA

INDEX BALL

63-ø0.45±0.05

(63-ø0.18±.002)

M

0.08(.003)

0.10(.004)

C

2001 FUJITSU LIMITED B63001S-c-2-2

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

83

MBM29DL32XTE/BE⁸⁰/90

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0306

FUJITSU LIMITED Printed in Japan


型号：	MBM29DL323BE90TN
厂家：	SPANSION
描述：	FLASH MEMORY CMOS 32 M (4 M X 8/2 M X 16) BIT Dual Operation FLASH存储器CMOS 32米（4 MX 8/2 MX 16 ）位双操作闪存存储内存集成电路光电二极管
文件：	总84页 (文件大小：1272K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MBM29DL323BE90TN [SPANSION]

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