MBM29DL400BC-55TN-E1 [SPANSION]
Flash, 256KX16, 55ns, PDSO48, PLASTIC, TSOP1-48;
| 型号： | MBM29DL400BC-55TN-E1 |
| 厂家： | 
SPANSION |
| 描述： | Flash, 256KX16, 55ns, PDSO48, PLASTIC, TSOP1-48 光电二极管 内存集成电路 |
| 文件： | 总58页 (文件大小：521K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
SPANSION Flash Memory
Data Sheet
September 2003
This document specifies SPANSIONTM memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSIONTM product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSIONTM memory
solutions.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20866-6E
FLASH MEMORY
CMOS
4 M (512 K × 8/256 K × 16) BIT
MBM29DL400TC/BC-55/70/90
■ DESCRIPTION
The MBM29DL400TC/BC are a 4 M-bit, 3.0 V-only Flash memory organized as 512 Kbytes of 8 bits each or 256
Kwords of 16 bits each. The MBM29DL400TC/BC are offered in a 48-pin TSOP (1) package. These devices are
designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are
not required for write or erase operations. The devices can also be reprogrammed in standard EPROM program-
mers.
MBM29DL400TC/BC provides simultaneous operation which can read data while program/erase. The simulta-
neous operation architecture provides simultaneous operation by dividing the memory space into two banks. The
devices can allow a host system to program or erase in one bank, then immediately and simultaneously read
from the other bank.
(Continued)
■ PRODUCT LINE UP
MBM29DL400TC/MBM29DL400BC
Part No.
−55
−70
−90
+0.3
−0.3
+0.6
Power Supply Voltage VCC (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
3.3
3.0
−0.3
55
55
30
70
70
30
90
90
35
■ PACKAGES
48-pin plastic TSOP (1)
48-pin plastic TSOP (1)
48-pin plastic FBGA
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(BGA-48P-M11)
MBM29DL400TC/BC-55/70/90
(Continued)
The standard MBM29DL400TC/BC offer access times 55 ns, 70 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices feature separate chip enable
(CE) , write enable (WE) , and output enable (OE) controls.
The MBM29DL400TC/BC are pin and command set compatible with JEDEC standard E2PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29DL400TC/BC are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
One sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29DL400TC/BC are erased when shipped from the
factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle is completed,
the devices internally reset to the read mode.
Fujitsu’s Flash technology integrates years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29DL400TC/BC memories electrically erase the entire
chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed
one byte/word at a time using the EPROM programming mechanism of hot electron injection.
2
MBM29DL400TC/BC-55/70/90
■ FEATURES
• Single 3.0 V Read, Program, and Erase
Minimizes system level power requirements
• Simultaneous Operations
Read-while-Erase or Read-while-Program
• Compatible with JEDEC-standard Commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard World-wide Pinouts (Pin Compatible with MBM29LV400TC/BC)
48-pin TSOP (1) (Package suffix : PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
• Minimum 100,000 Program/Erase Cycles
• High Performance
55 ns maximum access time
• Sector Erase Architecture
Two 16 Kbyte, four 8 Kbytes, two 32 Kbyte, and six 64 Kbytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
• Ready/Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC Write Inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Sector Protection
Hardware method disables any combination of sectors from program or erase operations
• Sector Protection Set function by Extended Sector Protection Command
• Fast Programming Function by Extended Command
• Temporary Sector Unprotection
Temporary sector unprotection via the RESET pin.
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
3
MBM29DL400TC/BC-55/70/90
■ PIN ASSIGNMENTS
TSOP (1)
A15
A14
A13
A12
A11
A10
A9
A8
A16
BYTE
VSS
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
(Marking Side)
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
N.C.
N.C.
WE
RESET
N.C.
N.C.
RY/BY
N.C.
A17
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Normal Bend
A7
A6
A5
A4
A3
A2
A1
VSS
CE
A0
(FPT-48P-M19)
A1
A2
A3
A4
A5
A6
A7
A17
A0
CE
VSS
OE
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
(Marking Side)
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
N.C.
RY/BY
N.C.
N.C.
RESET
WE
N.C.
N.C.
A8
Reverse Bend
A9
A10
A11
A12
A13
A14
A15
BYTE
A16
(FPT-48P-M20)
(Continued)
4
MBM29DL400TC/BC-55/70/90
(Continued)
FBGA
(TOP VIEW)
(Making Side)
A6
B6
C6
D6
E6
F6
G6
H6
A13
A12
A14
A15
A16 BYTEDQ15/A-1 VSS
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7 DQ14 DQ13 DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE RESET N.C. N.C. DQ5 DQ12 VCC
A3 B3 C3 D3 E3 F3 G3
DQ4
H3
RY/BY N.C. N.C. N.C. DQ2 DQ10 DQ11 DQ3
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
OE
H1
CE
VSS
(BGA-48P-M11)
5
MBM29DL400TC/BC-55/70/90
■ PIN DESCRIPTION
MBM29DL400TC/BC Pin Configuration
Function
Pin Name
A17 to A0, A-1
DQ15 to DQ0
CE
Address Inputs
Data Inputs/Outputs
Chip Enable
OE
Output Enable
Write Enable
WE
RY/BY
RESET
BYTE
N.C.
Ready/Busy Output
Hardware Reset
8-bit or 16-bit mode
No Connection
Ground
VSS
VCC
Power Supply
6
MBM29DL400TC/BC-55/70/90
■ BLOCK DIAGRAM
VCC
VSS
Bank 2 Address
A17 to A0
(A-1)
Cell Matrix
(Bank 2)
X-Decoder
DQ15 to DQ0
X-Decoder
RY/BY
Status
RESET
WE
State
Control
CE
Command
Register
OE
BYTE
DQ15 to DQ0
Bank 1 Address
Cell Matrix
(Bank 1)
■ LOGIC SYMBOL
A-1
18
A17 to A0
16 or 8
DQ15 to DQ0
RY/BY
CE
OE
WE
RESET
BYTE
7
MBM29DL400TC/BC-55/70/90
■ DEVICE BUS OPERATION
MBM29DL400TC/BC User Bus Operations (BYTE = VIH)
Operation
Auto-Select Manufacturer Code *1
Auto-Select Device Code *1
Read *3
CE OE WE
A0
L
A1
L
A6
L
A9
DQ15 to DQ0 RESET
L
L
L
H
L
L
L
L
X
X
L
L
H
H
H
X
H
L
VID
VID
A9
X
Code
Code
DOUT
High-Z
High-Z
DIN
H
H
H
H
H
H
H
H
VID
L
H
A0
X
L
L
L
A1
X
A6
X
X
A6
L
Standby
X
H
H
VID
L
Output Disable
X
X
X
Write (Program/Erase)
Enable Sector Protection *2, *4
Verify Sector Protection *2, *4
Temporary Sector Unprotection *5
Reset (Hardware) /Standby
A0
L
A1
H
H
X
A9
VID
VID
X
X
H
X
X
L
L
Code
X
X
X
X
X
X
X
X
X
High-Z
MBM29DL400TC/BC User Bus Operations (BYTE = VIL)
DQ15/
A-1
DQ7 to
Operation
CE
OE WE
A0
A1
A6
A9
RESET
DQ0
Code
Code
DOUT
High-Z
High-Z
DIN
Auto-Select Manufacturer Code *1
Auto-Select Device Code *1
Read *3
L
L
L
H
L
L
L
L
X
X
L
L
H
H
H
X
H
L
L
L
H
A0
X
X
A0
L
L
L
L
L
VID
VID
A9
X
H
H
H
H
H
H
H
H
VID
L
L
L
A-1
X
A1
X
A6
X
X
A6
L
Standby
X
H
H
VID
L
Output Disable
X
X
X
Write (Program/Erase)
Enable Sector Protection *2, *4
Verify Sector Protection *2, *4
Temporary Sector Unprotection *5
Reset (Hardware) /Standby
A-1
L
A1
H
H
X
A9
VID
VID
X
X
H
X
X
L
L
L
Code
X
X
X
X
X
X
X
X
X
X
X
High-Z
Legend : L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See “■DC CHARACTERISTICS” for voltage levels.
*1: Manufacturer and device codes may also be accessed via command register write sequence. See
“MBM29DL400TC/BC Command Definitions” Table.
*2: Refer to the section on Sector Protection.
*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4: VCC = 3.3 V ± 10%
*5: Also used for the extended sector protection.
8
MBM29DL400TC/BC-55/70/90
MBM29DL400TC/BC Command Definitions
Second
Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
First Bus
Write Cycle
Third Bus
Write Cycle
Fifth Bus
Write Cycle Write Cycle
Sixth Bus
Bus
Write
Cycles
Req’d
Command
Sequence
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Word
Read/Reset
Read/Reset
1
3
XXXh F0h
Byte
Word
Byte
555h
2AAh
555h
555h
AAh
AAh
55h
55h
F0h
90h
RA
RD
AAAh
AAAh
(BA)
555h
Word
Byte
555h
2AAh
555h
Autoselect
3
(BA)
AAAh
AAAh
Word
Byte
Word
Byte
Word
Byte
555h
AAAh
555h
AAAh
555h
AAAh
BA
2AAh
555h
2AAh
555h
2AAh
555h
555h
AAAh
555h
AAAh
555h
AAAh
Program
4
6
6
AAh
AAh
AAh
55h
55h
55h
A0h
80h
80h
PA
PD
555h
AAAh
555h
AAAh
2AAh
555h
2AAh
555h
555h
Chip Erase
AAh
AAh
55h
55h
10h
30h
AAAh
Sector
Erase
SA
Erase Suspend
Erase Resume
1
1
B0h
30h
BA
Word
555h
AAAh
XXXh
XXXh
BA
2AAh
555h
555h
Set to
Fast Mode
3
2
2
4
AAh
A0h
90h
55h
PD
20h
Byte
Word
Byte
Word
Byte
Word
Byte
AAAh
Fast
Program *
PA
XXXh
XXXh
Reset from
Fast Mode *
F0h
BA
Extended
Sector Protect
XXXh 60h SPA 60h SPA 40h SPA SD
* : This command is valid while Fast Mode.
Notes : 1. Address bits A17 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) , Sector
Address (SA) , and Bank Address (BA) .
2. Bus operations are defined in “MBM29DL400TC/BC User Bus Operations (BYTE = VIH) and (BYTE =
VIL)” Tables.
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
BA = Bank Address (A16 and A17)
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
9
MBM29DL400TC/BC-55/70/90
5. SPA = Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0) .
SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h at
unprotected sector addresses.
6. The system should generate the following address patterns :
Word Mode : 555h or 2AAh to addresses A0 to A10
Byte Mode : AAAh or 555h to addresses A-1 and A0 to A10
7. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
8. Command combinations not described in “MBM29DL400TC/BC Command Definitions” Table are
illegal.
10
MBM29DL400TC/BC-55/70/90
MBM29DL400TC/BC Sector Protection Verify Autoselect Codes
*1
Type
Manufacture’s Code
A12 to A17
A6
A1
A0
A-1
Code (HEX)
04h
BA
VIL
VIL
VIL
VIL
VIL
X
Byte
Word
Byte
0Ch
MBM29DL400TC
MBM29DL400BC
BA
BA
VIL
VIL
VIH
220Ch
0Fh
Device Code
VIL
X
VIL
VIL
VIL
VIH
VIH
VIL
Word
220Fh
Sector
Addresses
Sector Protection
VIL
01h*2
*1 : A-1 is for Byte mode.
*2 : Outputs 01h at protected sector address and outputs 00h at unprotected sector address.
Expanded Autoselect Code Table
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Type
Code
A-1/0
Manufacturer’s Code
04h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
(B)
(W) 220Ch
(B)
0Ch A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
MBM29DL
400TC
0
0
1
0
0
0
1
0
Device
Code
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0Fh A-1
MBM29DL
400BC
(W) 220Fh
01h
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
A-1/0
Sector Protection
(B) : Byte mode
(W) : Word mode
HI-Z : High-Z
11
MBM29DL400TC/BC-55/70/90
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
Sector Address Table (MBM29DL400TC)
Sector Address
Bank
Sector Size
(Kbytes/
(×8)
(×16)
Address Range
Bank Sector
Address
Address Range
Kwords)
A17 A16 A15 A14 A13 A12
SA0
SA1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
0
0
1
1
1
0
0
0
1
1
X
X
X
X
X
X
0
1
0
1
1
0
0
1
0
1
X
X
X
X
X
X
X
64/32
64/32
64/32
64/32
64/32
64/32
16/8
00000h to 0FFFFh
10000h to 1FFFFh
20000h to 2FFFFh
30000h to 3FFFFh
40000h to 4FFFFh
50000h to 5FFFFh
60000h to 63FFFh
00000h to 07FFFh
08000h to 0FFFFh
10000h to 17FFFh
18000h to 1FFFFh
20000h to 27FFFh
28000h to 2FFFFh
30000h to 31FFFh
SA2
Bank 2
SA3
SA4
SA5
SA6
64000h to 67FFFh
68000h to 6BFFFh
32000h to 33FFFh
34000h to 35FFFh
SA7
SA8
1
1
0
X
32/16
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8/4
8/4
8/4
8/4
6C000h to 6DFFFh
6E000h to 6FFFFh
70000h to 71FFFh
72000h to 73FFFh
36000h to 36FFFh
37000h to 37FFFh
38000h to 38FFFh
39000h to 39FFFh
SA9
Bank 1
SA10
SA11
SA12
SA13
74000h to 77FFFh
78000h to 7BFFFh
3A000h to 3BFFFh
3C000h to 3DFFFh
1
1
1
1
1
1
X
X
32/16
16/8
7C000h to 7FFFFh
3E000h to 3FFFFh
Note : The address range is A17 : A-1 if in byte mode (BYTE = VIL) .
The address range is A17 : A0 if in word mode (BYTE = VIH) .
12
MBM29DL400TC/BC-55/70/90
Sector Address Table (MBM29DL400BC)
Sector Address
Bank
Sector Size
(Kbytes/
(×8)
(×16)
Address Range
Bank Sector
Address
Address Range
Kwords)
A17 A16 A15 A14 A13 A12
SA13
SA12
1
1
1
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
1
1
0
0
0
1
1
1
0
0
X
X
X
X
X
X
1
0
1
0
0
1
1
0
1
0
X
X
X
X
X
X
X
X
X
1
64/32
64/32
64/32
64/32
64/32
64/32
16/8
70000h to 7FFFFh
60000h to 6FFFFh
50000h to 5FFFFh
40000h to 4FFFFh
30000h to 3FFFFh
20000h to 2FFFFh
1C000h to 1FFFFh
38000h to 3FFFFh
30000h to 37FFFh
28000h to 2FFFFh
20000h to 27FFFh
18000h to 1FFFFh
10000h to 17FFFh
0E000h to 0FFFFh
SA11
Bank 2
SA10
SA9
SA8
SA7
14000h to 17FFFh,
18000h to 1BFFFh
0A000h to 0BFFFh,
0C000h to 0DFFFh
SA6
SA5
0
0
1
32/16
0
0
0
0
0
0
0
0
1
1
0
0
8/4
8/4
8/4
8/4
12000h to 13FFFh
10000h to 11FFFh
0E000h to 0FFFFh
0C000h to 0DFFFh
09000h to 09FFFh
08000h to 08FFFh
07000h to 07FFFh
06000h to 06FFFh
SA4
Bank 1
0
SA3
1
SA2
SA1
SA0
0
X
X
X
08000h to 0BFFFh,
04000h to 07FFFh
04000h to 05FFFh,
02000h to 03FFFh
0
0
0
0
0
0
32/16
16/8
00000h to 03FFFh
00000h to 01FFFh
Note : The address range is A17 : A-1 if in byte mode (BYTE = VIL) .
The address range is A17 : A0 if in word mode (BYTE = VIH) .
MBM29DL400TC
MBM29DL400BC
7FFFFh
7FFFFh
70000h
60000h
50000h
40000h
30000h
20000h
1C000h
14000h
12000h
10000h
0E000h
0C000h
04000h
00000h
16 KB
7C000h
32 KB
74000h
8 KB
64 KB
64 KB
64 KB
64 KB
64 KB
72000h
70000h
6E000h
6C000h
64000h
60000h
50000h
40000h
30000h
20000h
10000h
00000h
Bank 2
8 KB
8 KB
Bank 1
8 KB
64 KB
16 KB
32 KB
8 KB
32 KB
16 KB
64 KB
8 KB
64 KB
64 KB
64 KB
64 KB
Bank 1
8 KB
Bank 2
8 KB
32 KB
16 KB
64 KB
13
MBM29DL400TC/BC-55/70/90
■ FUNCTIONAL DESCRIPTION
Simultaneous Operation
MBM29DL400TC/BC features reading data from one bank of memory while either programming or erase oper-
ation is in progress in the other bank of memory (simultaneous operation) , in addition to the conventional features
(read, program, erase, erase-suspend read, and erase-suspend program) . The bank selection can be selected
by bank address (A16, A17) with zero latency.
The MBM29DL400TC/BC have two banks which contain Bank 1 (16 KB, 32 KB, 8 KB, 8 KB, 8 KB, 8 KB, 32 KB,
and 16 KB) and Bank 2 (64 KB × six sectors) .
The simultaneous operation can not execute multi-function mode in the same bank. “Simultaneous Operation”
Table shows combination to be possible for simultaneous operation.
Simultaneous Operation
Case
Bank 1 Status
Read mode
Bank 2 Status
Read mode
1
2
3
4
5
6
7
Read mode
Autoselect mode
Program mode
Erase mode *
Read mode
Read mode
Read mode
Autoselect mode
Program mode
Erase mode *
Read mode
Read mode
* : Erase operation may also be supended to read from or program to a sector not being erased.
Read Mode
TheMBM29DL400TC/BChavetwocontrolfunctionswhichmustbesatisfiedinordertoobtaindataattheoutputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or to change CE pin from “H” to “L”
Standby Mode
There are two ways to implement the standby mode on the MBM29DL400TC/BC devices, one using both the
CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA Max During Embedded Algorithm operation, VCC
active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either
of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE
= “H” or “L”) . Under this condition the current is consumed is less than 5 µA Max Once the RESET pin is taken
high, the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
14
MBM29DL400TC/BC-55/70/90
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29DL400TC/BC data. This mode can be used effectively with an application requested low power con-
sumption such as handy terminals.
To activate this mode, MBM29DL400TC/BC automatically switch themselves to low power mode when
MBM29DL400TC/BC addresses remain stably during access fine of 150 ns. It is not necessary to control CE,
WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level) .
During simultaneous operation, VCC active current (ICC2) is required.
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29DL400TC/BC read-out the data for changed addresses.
Output Disable
With the OE input at a logic high level (VIH) , output from the devices is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, and A6 (A-1) . (See “MBM29DL400TC/BC User Bus Operations
(BYTE = VIH) and (BYTE = VIL)” Tables in “■DEVICE BUS OPERATION”.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29DL400TC/BC are erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in “MBM29DL400TC/BC Command Definitions” Table in “■DEVICE BUS
OPERATION”. (Refer to Autoselect Command section.)
Word 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device
identifier code (MBM29DL400TC = 0Ch and MBM29DL400BC = 0Fh for ×8 mode; MBM29DL400TC = 220Ch
and MBM29DL400BC = 220Fh for ×16 mode) . These two bytes/words are given in the “MBM29DL400TC/BC
Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code” Tables in “■DEVICE BUS OPER-
ATION”. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In
order to read the proper device codes when executing the autoselect, A1 must be VIL. (See “MBM29DL400TC/
BC Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code” Tables in “■DEVICE BUS
OPERATION”.)
In case of applying VID on A9, since both Bank 1 and Bank 2 enters Autoselect mode, the simultenous operation
can not be executed.
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The com-
mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the
falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
15
MBM29DL400TC/BC-55/70/90
Sector Protection
The MBM29DL400TC/BC feature hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 13) . The sector protection feature is enabled using programming
equipment at the user’s site. The devices are shipped with all sectors unprotected. Alternatively, Fujitsu may
program and protect sectors in the factory prior to shiping the device.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5 V) , CE = VIL, and A0 = A6 = VIL, A1 = VIH. The sector addresses (A17, A16, A15, A14, A13, and A12) should
be set to the sector to be protected. MBM29DL400TC/BC’s “Sector Address” Tables in “■FLEXIBLE SECTOR-
ERASEARCHITECTURE”definethesectoraddressforeachoftheforteen (14)individualsectors. Programming
of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of
the same. Sector addresses must be held constant during the WE pulse. See “Sector Protection Timing Diagram”
in “■TIMING DIAGRAM” and “Sector Protection Algorithm” in “■FLOW CHART” for sector protection waveforms
and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A17, A16, A15, A14, A13, and A12) while (A6,
A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the
devices will read 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6
are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.
A-1 requires to apply to VIL on byte mode.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02h, where the higher order addresses (A17, A16, A15, A14, A13, and
A12) are the desired sector address will produce a logical “1” at DQ0 for a protected sector. See “MBM29DL400TC/
BC Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code” Tables in “■DEVICE BUS
OPERATION” for Autoselect codes.
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29DL400TC/BC devices
in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage
(12 V) . During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected
again. See “Temporary Sector Unprotection Timing Diagram” in “■TIMING DIAGRAM” and “Temporary Sector
Unprotection Algorithm” in “■FLOW CHART”.
RESET
Hardware Reset
The MBM29DL400TC/BC devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 µs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional tRH before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See “RESET, RY/BY Timing
Diagram” in “■TIMING DIAGRAM” for the timing diagram. Refer to Temporary Sector Unprotection for additional
functionality.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register. Some
commands are required Bank Address (BA) input. When command sequences are inputed to bank being read,
the commands have priority than reading. “Hardware Sequence Flags” Table defines the valid register command
sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the
Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, reset-
16
MBM29DL400TC/BC-55/70/90
ting the device to the read mode. Please note that commands are always written at DQ0 to DQ7 and DQ8 to DQ15
bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/
Reset operation is initiated by writing the Read/Reset command sequence into the command register. Micro-
processor read cycles retrieve array data from the memory. The devices remain enabled for reads until the
command register contents are altered.
The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM pro-
grammers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage
onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming method-
ology. The operation is initiated by writing the Autoselect command sequence into the command register.
The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write
cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device
codes can be read from the bank, and an actual data of memory cell can be read from the another bank.
Following the command write, a read cycle from address (BA) 00h retrieves the manufacture code of 04h. A
read cycle from address (BA) 01h for ×16 ( (BA) 02h for ×8) returns the device code (MBM29DL400TC = 0Ch
and MBM29DL400BC = 0Fh for ×8 mode; MBM29DL400TC = 220Ch and MBM29DL400BC = 220Fh for ×16
mode). (See“MBM29DL400TC/BCSectorProtectionVerifyAutoselectCodes”and“ExpandedAutoselectCode”
Tables in “ ■DEVICE BUS OPERATION”.)
All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection
or unprotection) will be informed by address (BA) 02h for ×16 ( (BA) 04h for ×8) . Scanning the sector addresses
(A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a
protected sector. The programming verification should be performed by verify sector protection on the protected
sector. (See “MBM29DL400TC/BC User Bus Operations (BYTE = VIH) and (BYTE = VIL)” Tables in “■DEVICE
BUS OPERATION”.)
The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and
device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command
sequence into the register and then Autoselect command should be written into the bank to be read.
If the software (program code) for Autoselect command is stored into the Frash memory, the device and man-
ufacture codes should be read from the other bank where is not contain the software.
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command se-
quence.
Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
17
MBM29DL400TC/BC-55/70/90
The system can determine the status of the program operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) ,
or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware
Sequence Flags” Table.) Therefore, the devices require that a valid address to the devices be supplied by the
system at this particular instance of time. Hence, Data Polling must be performed at the memory location which
is being programmed.
If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being
written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“Embedded ProgramTM Algorithm” in “■FLOW CHART” illustrates the Embedded ProgramTM Algorithm using
typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) , or
RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command
sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the
device returns to read the mode.
Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
“Embedded EraseTM Algorithm” in “■FLOW CHART” illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever
happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first.
Aftertime-outof50µsfromtherisingedgeofthelastsectorerasecommand, thesectoreraseoperationwillbegin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29DL400TC/BC
Command Definitions” Table in “■DEVICE BUS OPERATION”. This sequence is followed with writes of the
Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between
writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is recom-
mended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be
re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of last CE
or WE whichever happens first will initiate the execution of the Sector Erase command (s) . If another falling
edge of CE or WE, whichever happens first occurs within the 50 µs time-out window the timer is reset. (Monitor
DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Resetting
the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase on those
sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer oper-
ation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 13) .
18
MBM29DL400TC/BC-55/70/90
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) , or
RY/BY.
The sector erase begins after the 50 µs time out from the rising edge of CE or WE whichever happens first for
the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status
section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at
an address within any of the sectors being erased.
Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming) ] × Number of Sector
Erase
In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe.
“Embedded EraseTM Algorithm” in “■FLOW CHART” illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. Writting the Erase Suspend command (B0h) during
the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase
operation.
Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being
erasing or suspending should be set when writting the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/
BY output pin will be at Hi-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use
the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been sus-
pended. Further writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com-
mand sequence for Program. This program mode is known as the erase-suspend-program mode. Again, pro-
gramming in this mode is the same as programming in the regular Program mode except that the data must be
programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-
suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I
(DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address
while DQ6 can be read from any address within bank being erase-suspended.
To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase
suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend
command can be written after the chip has resumed erasing.
19
MBM29DL400TC/BC-55/70/90
Extended Command
(1) Fast Mode
MBM29DL400TC/BC has Fast Mode function. This mode dispenses with the initial two unclock cycles required
in the standard program command sequence by writing Fast Mode command into the command register. In this
mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program
command. (Do not write erase command in this mode.) The read operation is also executed after exiting this
mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. The first
cyclemustcontainthebankaddress. (Refertothe“EmbeddedProgrammingAlgorithmforFastMode”in“■FLOW
CHART” Extended algorithm.) The VCC active current is required even CE = VIH during Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) . (Refer to the
“Embedded Programming Algorithm for Fast Mode” in “■FLOW CHART” Extended algorithm.)
(3) Extended Sector Protection
In addition to normal sector protection, the MBM29DL400TC/BC has Extended Sector Protection as extended
function. This function enable to protect sector by forcing VID on RESET pin and write a commnad sequence.
Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET
pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With
this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then,
the sector addresses pins (A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector
to be protected (recommend to set VIL for the other addresses pins) , and write extended sector protect command
(60h) . A sector is typically protected in 150 µs. To verify programming of the protection circuitry, the sector
addresses pins (A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command
(40h) . Following the command write, a logical “1” at device output DQ0 will produce for protected sector in the
read operation. If the output data is logical “0”, please repeat to write extended sector protect command (60h)
again. To terminate the operation, it is necessary to set RESET pin to VIH.
Write Operation Status
Detailed in “Hardware Sequence Flags” Table are all the status flags that can determine the status of the bank
for the current mode operation. The read operation from the bank where is not operate Embedded Algorithm
returns a data of memory cell. These bits offer a method for determining whether a Embedded Algorithm is
completed properly. The information on DQ2 is address sensitive. This means that if an address from an erasing
sector is consectively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-
erasingsectorisconsectivelyread. Thisallowstheusertodeterminewhichsectorsareerasingandwhicharenot.
The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there
is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] < busy
bank > , [2] < non-busy bank > , [3] < busy bank > , the DQ6 is toggling in the case of [1] and [3]. In case of [2],
the data of memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ6 will
not be toggled in the [1] and [3].
In the erase suspend read mode, DQ2 is toggled in the [1] and [3]. In case of [2], the data of memory cell is
outputted.
20
MBM29DL400TC/BC-55/70/90
Hardware Sequence Flags
DQ7
Status
DQ6
DQ5
0
DQ3
0
DQ2
1
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7
0
Toggle
Toggle
0
1
Toggle*
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
Data
0
0
Data
0
Toggle
Data
1*
In Progress
Erase
Erase Suspend Read
(Non-Erase Suspended Sector)
Suspended
Mode
Data
DQ7
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
Toggle
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
DQ7
0
Toggle
Toggle
1
1
0
1
1
N/A
Exceeded
Time Limits
Erase Suspend Program
Suspended
Mode
DQ7
Toggle
1
0
N/A
(Non-Erase Suspended Sector)
* : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase
suspend sector address will indicate logic “1” at the DQ2 bit.
Notes : 1. DQ0 and DQ1 are reserve pins for future use.
2. DQ4 is Fujitsu internal use only.
DQ7
Data Polling
The MBM29DL400TC/BC devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in “Data Polling Algorithm” in “■FLOW CHART”.
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid.
If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ7 is active for approximately 100 µs, then the bank returns to read mode.
Once the Embedded Algorithm operation is close to being completed, the MBM29DL400TC/BC data pins (DQ7)
may change asynchronously while the output enable (OE) is asserted low. This means that the devices are
driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time.
Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device
has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ6 to DQ0
may be still invalid. The valid data on DQ7 to DQ0 will be read on the successive read attempts.
TheDataPollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm, EmbeddedEraseAlgorithm
or sector erase time-out. (See “Hardware Sequence Flags” Table.)
See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “■TIMING DIAGRAM” for the Data
Polling timing specifications and diagrams.
21
MBM29DL400TC/BC-55/70/90
DQ6
Toggle Bit I
The MBM29DL400TC/BC also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
The system can use DQ6 to determine whether a sector is actively erasing or is erase-suspended. When a bank
is actively erasing (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters
the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during the erase-suspend-program cause
DQ6 to toggle.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See “AC Waveforms for Toggle Bit I during Embedded Algorithm Operations” in “■TIMING DIAGRAM” for the
Toggle Bit I timing specifications and diagrams.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA) .
The OE and WE pins will control the output disable functions as described in “MBM29DL400TC/BC User Bus
Operations (BYTE = VIH) and (BYTE = VIL)” Tables in “■DEVICE BUS OPERATIONS”.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the
DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun. If DQ3 is low (“0”) the device will accept additional sector erase commands. To insure
the command has been accepted, the system software should check the status of DQ3 prior to and following
each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not
have been accepted.
See “Hardware Sequence Flags” Table.
22
MBM29DL400TC/BC-55/70/90
DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows :
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also “Hardware Sequence Flags” Table and “DQ2 vs. DQ6” in “■TIMING
DIAGRAM”.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
Mode
DQ7
DQ7
0
DQ6
DQ2
1
Program
Erase
Toggle
Toggle
Toggle*
Erase-Suspend Read
(Erase-Suspended Sector) *
1
1
Toggle
1*
Erase-Suspend Program
DQ7
Toggle
* : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase
suspend sector address will indicate logic “1” at the DQ2 bit.
RY/BY
Ready/Busy
The MBM29DL400TC/BC provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. If the MBM29DL400TC/BC are placed in an Erase Suspend mode, the RY/BY output
will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a ready condition during the RESET pulse. Refer to “RY/BY Timing Diagram during Program/Erase Operation
Timing Diagram” and “RESET, RY/BY Timing Diagram” in “■TIMING DIAGRAM” for a detailed timing diagram.
The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
23
MBM29DL400TC/BC-55/70/90
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL400TC/BC devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ15
to DQ0. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin
becomes the lowest address bit and DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ7 to DQ0 and the DQ15 to DQ8 bits are ignored. Refer
to “Timing Diagram for Word Mode Configuration”, “BYTE Timing Diagram for Write Operations” and “Timing
Diagram for Byte Mode Configuration” in “■TIMING DIAGRAM” for the timing diagram.
Data Protection
The MBM29DL400TC/BC are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices automat-
ically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of
the memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 2.3 V (typically 2.4 V) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
24
MBM29DL400TC/BC-55/70/90
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min
−55
−40
Max
+125
+85
Storage Temperature
Tstg
°C
°C
Ambient Temperature with Power Applied
TA
Voltage with Respect to Ground All pins except A9,
OE, and RESET *1
VIN, VOUT
−0.5
VCC + 0.5
V
Power Supply Voltage *1
A9, OE, and RESET *2
VCC
VIN
−0.5
−0.5
+4.0
V
V
+13.0
*1: Minimum DC voltage on input or I/O pins is −0.5 V. During voltage transitions, input or I/O pins may undershoot
VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns.
*2: Minimum DC input voltage on A9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and RESET
pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage
(VIN - VCC) does not exceed 9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which may
overshoot to +14.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Ambient Temperature
Power Supply Voltage
Symbol
TA
Part No.
Unit
Min
−20
−40
+3.0
+2.7
Max
+70
MBM29DL400TC/BC-55
MBM29DL400TC/BC-70/90
MBM29DL400TC/BC-55
MBM29DL400TC/BC-70/90
°C
°C
V
+85
+3.6
+3.6
VCC
V
Note : Operating ranges define those limits between which the proper device function is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
25
MBM29DL400TC/BC-55/70/90
■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
20 ns
20 ns
+0.6 V
−0.5 V
−2.0 V
20 ns
Maximum Undershoot Waveform
20 ns
VCC + 2.0 V
VCC + 0.5 V
+2.0 V
20 ns
20 ns
Maximum Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
VCC + 0.5 V
20 ns
20 ns
Note : This waveform is applied for A9, OE, and RESET.
Maximum Overshoot Waveform 2
26
MBM29DL400TC/BC-55/70/90
■ DC CHARACTERISTICS
Value
Parameter
Symbol
Conditions
Unit
Min
−1.0
−1.0
Max
+1.0
+1.0
Input Leakage Current
Output Leakage Current
ILI
VIN = VSS to VCC, VCC = VCC Max
VOUT = VSS to VCC, VCC = VCC Max
µA
µA
ILO
A9, OE, RESET Inputs Leakage
Current
VCC = VCC Max
A9, OE, RESET = 12.5 V
ILIT
+35
µA
Byte
Word
Byte
18
20
8
CE = VIL, OE = VIH,
f = 10 MHz
mA
VCC Active Current *1
ICC1
CE = VIL, OE = VIH,
f = 5 MHz
mA
Word
10
35
VCC Active Current *2
VCC Current (Standby)
ICC2
ICC3
CE = VIL, OE = VIH
mA
VCC = VCC Max, CE = VCC ± 0.3 V,
RESET = VCC ± 0.3 V
5
5
µA
VCC = VCC Max,
RESET = VSS ± 0.3 V
VCC Current (Standby, Reset)
ICC4
ICC5
µA
µA
VCC = VCC Max, CE = VSS ± 0.3 V,
RESET = VCC ± 0.3 V
VIN = VCC ± 0.3 V or VSS ± 0.3 V
VCC Current
(Automatic Sleep Mode) *3
5
VCC Active Current *5
(Read-While-Program)
Byte
CE = VIL, OE = VIH
Word
45
45
45
45
ICC6
mA
VCC Active Current *5
(Read-While-Erase)
Byte
CE = VIL, OE = VIH
Word
ICC7
ICC8
mA
mA
VCC Active Current
(Erase-Suspend-Program)
CE = VIL, OE = VIH
35
Input Low Level
Input High Level
VIL
−0.5
0.6
V
V
VIH
2.0
VCC + 0.3
Voltage for Autoselect and Sector
Protection (A9, OE, RESET) *4
VID
11.5
12.5
0.45
V
Output Low Voltage Level
Output High Voltage Level
Low VCC Lock-Out Voltage
VOL
VOH1
VOH2
VLKO
IOL = 4.0 mA, VCC = VCC Min
IOH = −2.0 mA, VCC = VCC Min
IOH = −100 µA
V
V
V
V
2.4
VCC − 0.4
2.3
2.5
*1: The ICC current listed includes both the DC operating current and the frequency dependent component.
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
*4: Applicable for only VCC applying.
*5: Embedded Algorithm (program or erase) is in progress. (@5 MHz)
27
MBM29DL400TC/BC-55/70/90
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Value (Note)
-70
Symbol
Test
Setup
Parameter
-55
-90
Unit
JEDEC Standard
Min Max Min Max Min Max
55 70 90
Read Cycle Time
tAVAV
tRC
ns
ns
CE = VIL
OE = VIL
Address to Output Delay
tAVQV
tACC
55
70
90
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
OE = VIL
55
30
25
25
70
30
25
25
90
35
30
30
ns
ns
ns
ns
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First
tAXQX
tOH
0
0
0
ns
µs
ns
RESET Pin Low to Read Mode
tREADY
20
5
20
5
20
5
tELFL
tELFH
CE to BYTE Switching Low or High
Note : Test Conditions :
Output Load : 1 TTL gate and 30 pF (MBM29DL400TC/BC-55/-70)
1 TTL gate and 100 pF (MBM29DL400TC/BC-90)
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V or 3.0 V
Timing measurement reference level
Input : 1.5 V
Output : 1.5 V
3.3 V
Diodes = 1N3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = 1N3064
or Equivalent
Note : CL = 30 pF including jig capacitance (MBM29DL400TC/BC-55/-70)
CL = 100 pF including jig capacitance (MBM29DL400TC/BC-90)
Test Conditions
28
MBM29DL400TC/BC-55/70/90
• Write/Erase/Program Operations
Value
Symbol
Parameter
Unit
-55
-70
-90
Min Typ Max Min Typ Max Min Typ Max
JEDEC Standard
Write Cycle Time
tAVAV
tWC
tAS
55
0
70
0
90
0
ns
ns
Address Setup Time
tAVWL
Address Setup Time to OE Low
During Toggle Bit Polling
tASO
tAH
15
45
0
15
45
0
15
45
0
ns
ns
ns
Address Hold Time
tWLAX
Address Hold Time from CE or OE
High During Toggle Bit Polling
tAHT
Data Setup Time
Data Hold Time
tDVWH
tDS
tDH
30
0
35
0
45
0
ns
ns
ns
tWHDX
Output
Read
0
0
0
Enable Hold
Time
tOEH
Toggle and Data Polling
10
10
10
ns
CE High During Toggle Bit Polling
OE High During Toggle Bit Polling
Read Recover Time Before Write
Read Recover Time Before Write
CE Setup Time
tCEPH
tOEPH
tGHWL
tGHEL
tCS
20
20
0
20
20
0
20
20
0
ns
ns
tGHWL
tGHEL
ns
0
0
0
ns
tELWL
0
0
0
ns
WE Setup Time
tWLEL
tWS
0
0
0
ns
CE Hold Time
tWHEH
tEHWH
tWLWH
tELEH
tCH
0
0
0
ns
WE Hold Time
tWH
0
0
0
ns
Write Pulse Width
tWP
30
30
25
25
35
35
25
25
45
45
25
25
ns
CE Pulse Width
tCP
ns
Write Pulse Width High
CE Pulse Width High
tWHWL
tEHEL
tWPH
tCPH
tWHWH1
tWHWH2
tVCS
tVIDR
tVLHT
tWPP
tOESP
tCSP
tRB
ns
ns
Byte Programming Operation
Sector Erase Operation *1
VCC Setup Time
tWHWH1
tWHWH2
8
1
8
1
8
1
µs
s
50
500
4
50
500
4
50
500
4
µs
Rise Time to VID *2
ns
Voltage Transition Time *2
Write Pulse Width *2
µs
100
4
100
4
100
4
µs
OE Setup Time to WE Active *2
CE Setup Time to WE Active *2
Recover Time From RY/BY
RESET Pulse Width
µs
4
4
4
µs
0
0
0
ns
ns
tRP
500
200
500
200
500
200
RESET Hold Time Before Read
tRH
ns
(Continued)
29
MBM29DL400TC/BC-55/70/90
(Continued)
Value
-70
Symbol
Parameter
Unit
-55
-90
Min Typ Max Min Typ Max Min Typ Max
JEDEC Standard
BYTE Switching Low to Output High-Z
BYTE Switching High to Output Active
Program/Erase Valid to RY/BY Delay
tFLQZ
tFHQV
tBUSY
30
55
90
30
70
90
35
90
90
ns
ns
ns
Delay Time from Embedded Output
Enable
tEOE
55
70
90
ns
*1: This does not include the preprogramming time.
*2: This timing is for Sector Protection operation.
30
MBM29DL400TC/BC-55/70/90
■ ERASE AND PROGRAMMING PERFORMANCE
Limit
Typ
Parameter
Unit
Remarks
Min
Max
Excludes programming time
prior to erasure
Sector Erase Time
1
10
s
Word Programming Time
Byte Programming Time
16
8
360
300
µs
µs
Excludes system-level
overhead
Excludes system-level
overhead
Chip Programming Time
Program/Erase Cycle
4.2
12.5
s
100,000
cycle
■ INPUT/OUTPUT PIN CAPACITANCE
1. TSOP (1) PIN CAPACITANCE
Value
Unit
Parameter
Symbol
Test Setup
Typ
Max
Input Capacitance
CIN
COUT
CIN2
VIN = 0
6.0
8.5
8.0
7.5
pF
pF
pF
Output Capacitance
VOUT = 0
VIN = 0
12.0
10.0
Control Pin Capacitance
Notes : • Test conditions TA = + 25 °C, f = 1.0 MHz
• DQ15/A−1 pin capacitance is stipulated by output capacitance.
2. FBGA PIN CAPACITANCE
Value
Parameter
Symbol
Test Setup
Unit
Typ
6.0
8.5
8.0
Max
7.5
Input Capacitance
CIN
COUT
CIN2
VIN = 0
pF
pF
pF
Output Capacitance
VOUT = 0
VIN = 0
12.0
10.0
Control Pin Capacitance
Notes : • Test conditions TA = + 25 °C, f = 1.0 MHz
• DQ15/A−1 pin capacitance is stipulated by output capacitance.
31
MBM29DL400TC/BC-55/70/90
■ TIMING DIAGRAM
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will
Change
from H to L
May
Change
from L to H
Will
Change
from L to H
"H" or "L":
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center Line is
High-
Impedance
"Off" State
tRC
Address
Address Stable
tACC
CE
OE
tOE
tDF
tOEH
WE
tOH
tCE
High-Z
High-Z
Output Valid
Outputs
Read Operation Timing Diagram
32
MBM29DL400TC/BC-55/70/90
tRC
Address
Address Stable
tACC
CE
tRH
tRP
tRH
tCE
RESET
Outputs
tOH
High-Z
Output Valid
Hardware Reset/Read Operation Timing Diagram
33
MBM29DL400TC/BC-55/70/90
3rd Bus Cycle
555h
Data Polling
PA
PA
Address
CE
tWC
tRC
tAS
tAH
tCS
tCH
tCE
OE
tOE
tWP
tWPH
tWHWH1
tGHWL
WE
tOH
tDF
tDH
tDS
A0h
PD
DOUT
DOUT
DQ7
Data
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Alternate WE Controlled Program Operation Timing Diagram
34
MBM29DL400TC/BC-55/70/90
3rd Bus Cycle
555h
Data Polling
PA
PA
Address
WE
tWC
tAS
tAH
tWS
tWH
OE
CE
tCPH
tCP
tWHWH1
tGHEL
tDS
tDH
A0h
PD
DOUT
DQ7
Data
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Alternate CE Controlled Program Operation Timing Diagram
35
MBM29DL400TC/BC-55/70/90
555h
tWC
2AAh
555h
555h
2AAh
SA*
Address
tAS
tAH
CE
tCS
tCH
OE
tWP
tWPH
tGHWL
WE
tDS
tDH
30h for Sector Erase
10h/
30h
AAh
55h
80h
AAh
55h
Data
VCC
tVCS
* : SA is the sector address for Sector Erase. Address = 555h (Word) for Chip Erase.
Note : These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Chip/Sector Erase Operation Timing Diagram
36
MBM29DL400TC/BC-55/70/90
CE
tCH
tDF
tOE
OE
tOEH
WE
tCE
*
High-Z
High-Z
DQ7 =
Data
Data
DQ7
DQ7
Valid Data
tWHWH1 or 2
DQ6 to DQ0 =
Output Flag
DQ6 to DQ0
Valid Data
DQ6 to DQ0
RY/BY
tEOE
tBUSY
* : DQ7 = Valid Data (The device has completed the Embedded operation) .
Data Polling during Embedded Algorithm Operation Timing Diagram
37
MBM29DL400TC/BC-55/70/90
Address
tAHT tASO
tAHT tAS
CE
tCEPH
WE
tOEPH
tOEH
tOEH
OE
tOE
tCE
tDH
*
Stop
Toggling
Output
Valid
Toggle
Data
Toggle
Data
Toggle
Data
DQ6/DQ2
Data
tBUSY
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation) .
AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
38
MBM29DL400TC/BC-55/70/90
Read
tRC
Command
tWC
Read
tRC
Command
tWC
Read
tRC
Read
tRC
BA2
BA2
(PA)
BA2
(PA)
Address
CE
BA1
BA1
BA1
(555h)
tACC
tCE
tAS
tAS
tAH
tAHT
tOE
tCEPH
OE
WE
DQ
tDF
tGHWL
tOEH
tWP
tDH
tDS
tDF
Valid
Output
Valid
Intput
Valid
Output
Valid
Intput
Valid
Output
Status
(A0h)
(PD)
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1 : Address Corresponding to Bank 1.
BA2 : Address Corresponding to Bank 2.
Bank-to-Bank Read/Write Timing Diagram
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase Suspend
Read
Erase Suspend
Read
WE
Erase
Erase
Suspend
Program
Erase
Erase
Complete
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE
or CE
Note : DQ2 is read from the erase-suspended sector.
DQ2 vs. DQ6
39
MBM29DL400TC/BC-55/70/90
CE
Rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
RY/BY Timing Diagram during Program/Erase Operation Timing Diagram
WE
RESET
tRP
tRB
RY/BY
tREADY
RESET, RY/BY Timing Diagram
40
MBM29DL400TC/BC-55/70/90
CE
tCE
BYTE
Data Output
(DQ7 to DQ0)
Data Output
(DQ14 to DQ0)
DQ14 to DQ0
tELFH
tFHQV
A-1
DQ15
DQ15/A-1
Timing Diagram for Word Mode Configuration
Falling edge of last write signal
CE or WE
Input
Valid
BYTE
tAS
tAH
BYTE Timing Diagram for Write Operations
CE
BYTE
tELFL
DQ14 to DQ0
Data Output
(DQ7 to DQ0)
Data Output
(DQ14 to DQ0)
tACC
DQ15/A-1
A-1
DQ15
tFLQZ
Timing Diagram for Byte Mode Configuration
41
MBM29DL400TC/BC-55/70/90
A17, A16, A15,
A14, A13, A12
SPAX
SPAY
A6, A0
A1
VID
VIH
A9
tVLHT
VID
VIH
OE
tVLHT
tVLHT
tVLHT
tWPP
WE
tOESP
tCSP
CE
01h
Data
tOE
tVCS
VCC
SPAX : Sector Address to be protected
SPAY : Next Sector Address to be protected
Note : A-1 is VIL on byte mode.
Sector Protection Timing Diagram
42
MBM29DL400TC/BC-55/70/90
VCC
tVIDR
tVCS
tVLHT
VID
VIH
RESET
CE
WE
tVLHT
tVLHT
Program or Erase Command Sequence
RY/BY
Unprotection period
Temporary Sector Unprotection Timing Diagram
43
MBM29DL400TC/BC-55/70/90
VCC
tVCS
tVLHT
RESET
tWC
tWC
tVIDR
Address
SPAX
SPAX
SPAY
A6, A0
A1
CE
OE
TIME-OUT
tWP
WE
60h
60h
40h
01h
60h
Data
tOE
SPAX : Sector Address to be protected
SPAY : Next Sector Address to be protected
TIME-OUT : Time-Out window = 150 µs (Min)
Extended Sector Protection Timing Diagram
44
MBM29DL400TC/BC-55/70/90
■ FLOW CHART
EMBEDDED ALGORITHM
Start
Write Program
Command Sequence
(See Below)
Data Polling
Embedded
Program
Algorithm
in progress
No
Verify Data
?
Yes
No
Increment Address
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
Note : The sequence is applied for ×16 mode.
The addresses differ from ×8 mode.
Embedded ProgramTM Algorithm
45
MBM29DL400TC/BC-55/70/90
EMBEDDED ALGORITHM
Start
Write Erase
Command Sequence
(See Below)
Data Polling
Embedded
Erase
Algorithm
in progress
No
Data = FFh
?
Yes
Erasure Completed
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
Chip Erase Command Sequence
(Address/Command):
555h/AAh
2AAh/55h
555h/80h
555h/AAh
2AAh/55h
555h/10h
555h/AAh
2AAh/55h
555h/80h
555h/AAh
2AAh/55h
Sector Address
/30h
Sector Address
/30h
Additional sector
erase commands
are optional.
Sector Address
/30h
Note : The sequence is applied for ×16 mode.
The addresses differ from ×8 mode.
Embedded EraseTM Algorithm
46
MBM29DL400TC/BC-55/70/90
VA = Address for programming
= Any of the sector addresses
within the sector being erased
during sector erase or multiple
erases operation.
Start
Read Byte
(DQ7 to DQ0)
Addr. = VA
= Any of the sector addresses
within the sector not being
protected during sector erase or
Yes
multiple sector erases
operation.
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read Byte
(DQ7 to DQ0)
Addr. = VA
Yes
DQ7 = Data?
*
No
Fail
Pass
* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Data Polling Algorithm
47
MBM29DL400TC/BC-55/70/90
Start
VA = Bank address being executed
Read DQ7 to DQ0
Embedded Algorithm.
Addr. = VA
*1
Read DQ7 to DQ0
Addr. = VA
No
DQ6
= Toggle?
Yes
No
DQ5 = 1?
Yes
*1, 2
Read DQ7 to DQ0
Addr. = VA
Read DQ7 to DQ0
Addr. = VA
DQ6
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete.Write
Reset Command
Program/Erase
Operation
Complete
*1 : Read toggle bit twice to determine whether it is toggling.
*2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”.
Toggle Bit Algorithm
48
MBM29DL400TC/BC-55/70/90
Start
Setup Sector Addr.
(A17, A16, A15, A14, A13, A12)
PLSCNT = 1
OE = VID, A9 = VID
CE = VIL, RESET = VIH
A6 = A0 = VIL, A1 = VIH
Activate WE Pulse
Increment PLSCNT
Time out 100 µs
WE = VIH, CE = OE = VIL
(A9 should remain VID)
Read from Sector
Addr. = SPA, A1 = VIH
*
(
)
A6 = A0 = VIL
No
PLSCNT = 25?
Yes
No
Data = 01h?
Yes
Yes
Remove VID from A9
Write Reset Command
Protect Another Sector
?
No
Remove VID from A9
Write Reset Command
Device Failed
Sector Protection
Completed
* : A-1 is VIL on byte mode.
Sector Protection Algorithm
49
MBM29DL400TC/BC-55/70/90
Start
RESET = VID
*1
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed
*2
*1 : All protected sectors are unprotected.
*2 : All previously protected sectors are protected once again.
Temporary Sector Unprotection Algorithm
50
MBM29DL400TC/BC-55/70/90
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector
Unprotection Mode
No
Extended Sector
Protection Entry?
Yes
To Setup Sector Protection
Write XXXh/60h
PLSCNT = 1
To Protect Sector
Write 60h to Sector Address
(A6 =A0 = VIL, A1 = VIH)
Time out 150 µs
To Verify Sector Protection
Write 40h to Sector Address
(A6 = A0 = VIL, A1 = VIH)
Increment PLSCNT
Read from Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
No
Setup Next Sector Address
No
Data = 01h?
PLSCNT = 25?
Yes
Yes
Yes
Protect Other Sector
?
Remove VID from RESET
Write Reset Command
No
Remove VID from RESET
Write Reset Command
Device Failed
Sector Protection
Completed
Extended Sector Protection Algorithm
51
MBM29DL400TC/BC-55/70/90
FAST MODE ALGORITHM
Start
555h/AAh
Set Fast Mode
2AAh/55h
555h/20h
XXXh/A0h
In Fast Program
Program Address/Program Data
Data Polling
No
Verify Data?
Yes
No
Last Address?
Yes
Increment Address
Programming Completed
(BA)XXXh/90h
XXXh/F0h
Reset Fast Mode
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device.
Consult the local Fujitsu sales office to confirm avail-
ability of specific valid combinations and to check on
newly released combinations.
Note : The sequence is applied for ×16 mode.
The addresses differ from ×8 mode.
Embedded Programming Algorithm for Fast Mode
52
MBM29DL400TC/BC-55/70/90
■ ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of :
MBM29DL400
T
C
-55
PFTN
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP) Normal Bend
PFTR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Bend
PBT= 63-Ball Fine pitch Ball Grid Array Package
(FBGA)
SPEED OPTION
See Product Selector Guide
Device Revision
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29DL400
4 Mega-bit (512 K × 8-Bit or 256 K × 16-Bit) CMOS Flash Memory
3.0 V-only Read, Program, and Erase
Valid Combinations
55
TN
TR
MBM29DL400 TC/BC
70
90
PBT
53
MBM29DL400TC/BC-55/70/90
■ PACKAGE DIMENSIONS
Note 1) * : Values do not include resin protrusion.
48-pin plastic TSOP (1)
(FPT-48P-M19)
Resin protrusion and gate protrusion are + 0.15 (.006) Max (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
LEAD No.
1
48
INDEX
Details of "A" part
0.25(.010)
0~8˚
0.60±0.15
(.024±.006)
24
25
*
20.00±0.20
(.787±.008)
12.00±0.20
(.472±.008)
*18.40±0.20
(.724±.008)
1.10 –+00..0150
.043 –+..000024
(Mounting
height)
0.10±0.05
(.004±.002)
(Stand off height)
0.50(.020)
"A"
0.10(.004)
0.17 –+00..0083
0.22±0.05
(.009±.002)
M
0.10(.004)
.007 –+..000031
C
2003 FUJITSU LIMITED F48029S-c-6-7
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
(Continued)
54
MBM29DL400TC/BC-55/70/90
Note 1) * : Values do not include resin protrusion.
48-pin plastic TSOP (1)
(FPT-48P-M20)
Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
LEAD No.
1
48
Details of "A" part
INDEX
0.60±0.15
(.024±.006)
0~8˚
0.25(.010)
24
25
0.17 –+00..0083
.007 –+..000031
0.22±0.05
(.009±.002)
M
0.10(.004)
0.10±0.05
(.004±.002)
0.50(.020)
0.10(.004)
(Stand off height)
1.10 +–00..0150
"A"
* 18.40±0.20
(.724±.008)
.043 +–..000024
(Mounting height)
20.00±0.20
(.787±.008)
* 12.00±0.20(.472±.008)
C
2003 FUJITSU LIMITED F48030S-c-6-7
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
(Continued)
55
MBM29DL400TC/BC-55/70/90
(Continued)
48-pin plastic FBGA
(BGA-48P-M11)
8.00±0.20(.315±.008)
1.05 +–00..1105 .041 –+..000046
(Mounting height)
(5.60(.220))
0.80(.031)TYP
0.38±0.10(.015±.004)
(Stand off)
6
5
4
3
2
1
INDEX
6.00±0.20
(.236±.008)
(4.00(.157))
H
G
F
E
D
C
B
A
C0.25(.010)
48-ø0.45±0.10
M
ø0.08(.003)
(48-ø.018±.004)
0.10(.004)
C
2001 FUJITSU LIMITED B48011S-c-5-3
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
56
MBM29DL400TC/BC-55/70/90
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
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without limitation, ordinary industrial use, general office use,
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risks or dangers that, unless extremely high safety is secured, could
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Please note that Fujitsu will not be liable against you and/or any
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FUJITSU LIMITED Printed in Japan
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