MBM29F002BC-70PFTN-E1 [SPANSION]
Flash, 256KX8, 70ns, PDSO32, PLASTIC, TSOP1-32;
| 型号： | MBM29F002BC-70PFTN-E1 |
| 厂家： | 
SPANSION |
| 描述： | Flash, 256KX8, 70ns, PDSO32, PLASTIC, TSOP1-32 光电二极管 内存集成电路 |
| 文件： | 总44页 (文件大小：519K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
SPANSION Flash Memory
Data Sheet
September 2003
This document specifies SPANSIONTM memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSIONTM product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSIONTM memory
solutions.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20868-4E
FLASH MEMORY
CMOS
2M (256K × 8) BIT
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
■ GENERAL DESCRIPTION
The MBM29F002TC/BC is a 2 M-bit, 5.0 V-Only Flash memory organized as 256K bytes of 8 bits each. The
MBM29F002TC/BC is offered in a 32-pin TSOP(1) and 32-pin PLCC packages. This device is designed to be
programmed in-system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for program or
erase operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29F002TC/BC offers access times between 55 ns and 90 ns allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29F002TC/BC is command set compatible with JEDEC standard E2PROMs. Commands are written to
the command register using standard microprocessor write timings. Register contents serve as input to an internal
state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase operations. Reading data out of the device is similar to reading
from 12.0 V Flash or EPROM devices.
The MBM29F002TC/BC is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Each sector can be programmed and verified in less than 0.5 seconds. Erase is
accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which
is an internal algorithm that automatically preprograms the array if it is not already programmed before executing
the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell
margin.
■ PRODUCT LINE UP
Part No.
VCC = 5.0 V ± 5%
VCC = 5.0 V ± 10%
MBM29F002TC/BC
-55
—
—
-70
70
70
30
—
-90
90
90
35
Ordering Part No.
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
55
55
30
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(Continued)
This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to
be erased and reprogrammed without affecting other sectors. A sector is typically erased and verified within 1
second (if already completely preprogrammed). The MBM29F002TC/BC is erased when shipped from the
factory.
The MBM29F002TC/BC device also features hardware sector protection. This feature will disable both program
and erase operations in any number of secotrs (0 through 6).
Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of
time to read data from or program data to a non-busy sector. Thus, true background erase can be achieved.
Thedevicefeaturessingle5.0Vpowersupplyoperationforbothreadandprogramfunctions.Internallygenerated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations during power transitions. The end of program or erase is detected by Data Polling of
DQ7, or by the Toggle Bit I feature on DQ6. Once the end of a program or erase cycle has been completed, the
device automatically resets to the read mode.
TheMBM29F002TC/BCalsohasahardwareRESETpin. Whenthispinisdrivenlow, executionofanyEmbedded
Program or Embedded Erase operations will be terminated. The internal state machine will then be reset into
the read mode. The RESET pin may be tied to the system reset circuity. Therefore, if a system reset occurs
during the Embedded Program or Embedded Erase operation, the device will be automatically reset to a read
mode. This will enable the system microprocessor to read the boot-up firmware from the Flash memory.
Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29F002TC/BC memory electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the
EPROM programming mechanism of hot electron injection.
■ FEATURES
•
Single 5.0 V read, write, and erase
Minimizes system level power requirements
Compatible with JEDEC-standard commands
Pinout and software compatible with single-power supply Flash
Superior inadvertent write protection
•
•
32-pin TSOP(1) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type)
32-pin PLCC (Package Suffix: PD)
•
•
Minimum 100,000 write/erase cycles
High performance
55 ns maximum access time
•
•
Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes
Any combination of sectors can be erased. Also supports full chip erase
Boot Code Sector Architecture
T = Top sector
B = Bottom sector
•
•
•
Embedded Erase™* Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program™* Algorithms
Automatically programs and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
(Continued)
2
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(Continued)
•
•
Low VCC write inhibit ≤ 3.2 V
Hardware RESET pin
Resets internal state machine to the read mode
Erase Suspend/Resume
Supports reading or programming data to a sector not being erased
Sector protection
Hardware method that disables any combination of sector from write or erase operation
Temporary sector unprotection
•
•
•
Temporary sector unprotection via the RESET pin
* : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
■ PACKAGES
32-pin plastic TSOP(1)
32-pin plastic TSOP(1)
Marking Side
Marking Side
(FPT-32P-M24)
(FPT-32P-M25)
32-pin plastic QFJ (PLCC)
Marking Side
(LCC-32P-M02)
3
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
■ PIN ASSIGNMENTS
TSOP (1)
A11
A9
A8
A13
A14
A17
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
Marking Side
DQ7
DQ6
DQ5
DQ4
DQ3
V SS
DQ2
DQ1
DQ0
A0
WE
VCC
RESET
A16
Normal Bend
9
10
11
12
13
14
15
16
A15
A12
A7
A6
A5
A4
A1
A2
A3
(FPT-32P-M24)
16
A4
A5
A6
A7
A12
A3
A2
A1
A0
Marking Side
Reverse Bend
(FPT-32P-M25)
17
15
14
13
12
11
10
9
8
7
6
5
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DQ0
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ7
CE
A15
A16
RESET
VCC
WE
A17
A14
A13
A8
A9
4
3
2
1
A10
OE
A11
(Continued)
4
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(Continued)
QFJ (PLCC)
4
3
2
1
32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
29
28
27
26
25
24
23
22
21
A14
A13
A8
6
7
8
A9
9
A11
OE
A10
CE
DQ7
10
11
12
13
14 15
16 17 18 19
20
(LCC-32P-M02)
Pin
Function
A17 to A0
Address Inputs
Data Inputs/Outputs
Chip Enable
DQ7 to DQ0
CE
OE
Output Enable
Write Enable
WE
RESET
N.C.
Hardware Reset Pin/Sector Protection Unlock
No Internal Connection
VSS
Device Ground
VCC
Device Power Supply
5
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
■ BLOCK DIAGRAM
DQ7 to DQ0
VCC
VSS
Erase Voltage
Generator
Input/Output
Buffers
WE
State
Control
RESET
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
CE
OE
Y-Gating
Y-Decoder
X-Decoder
STB
Timer for
Program/Erase
Address
Latch
Low VCC Detector
Cell Matrix
A17 to A0
■ LOGIC SYMBOL
18
A17to A0
8
DQ7 to DQ0
CE
OE
WE
RESET
6
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
• One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes
• Individual-sector, multiple-sector, or bulk-erase capability
• Individual or multiple-sector protection is user definable
MBM29F002TC/BC User Bus Operations
Operation
Auto-Select Manufacturer Code*1
Auto-Select Device Code*1
Read*3
CE OE WE
A0
L
A1
L
A6
L
A9
VID
VID
A9
X
A10 DQ7 to DQ0 RESET
L
L
L
H
L
L
L
L
X
X
L
L
H
H
H
X
H
L
L
L
Code
Code
DOUT
High-Z
High-Z
DIN
H
H
H
H
H
H
H
H
VID
L
H
A0
X
L
L
L
A1
X
A6
X
X
A6
X
L
A10
X
Standby
X
H
H
VID
L
Output Disable
X
X
X
X
Write (Program/Erase)
Enable Sector Protection*2
Verify Sector Protection*2
Temporary Sector Unprotection
Reset (Hardware)
A0
X
A1
X
A9
VID
VID
X
A10
X
X
H
X
X
L
H
X
L
Code
X
X
X
X
X
X
X
X
X
X
X
High-Z
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse Input. See DC Characteristics for voltage levels.
*1 : Manufacturer and device codes may also be accessed via a command register write sequence. Refer to
“MBM29F002TC/BC Command Definitions Table” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”.
*2 : Refer to the section on Sector Protection.
*3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
7
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
MBM29F002TC/BC Command Definitions
Fourth Bus
First Bus Second Bus Third Bus
Write Cycle Write Cycle Write Cycle
Fifth Bus
Sixth Bus
Bus
Write
Cycles
Req'd
Read/Write
Cycle
Write Cycle Write Cycle
Command
Sequence
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset*1
Reset/Read*1
Manufacture Code
Device Code
Byte Program
Chip Erase
1
3
3
3
4
6
6
XXXh F0h
—
—
—
—
—
—
RD*2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
555h AAh 2AAh 55h 555h F0h RA*2
00h*2 04h*2
555h AAh 2AAh 55h 555h 90h
555h AAh 2AAh 55h 555h 90h 01h*2 ID*2
555h AAh 2AAh 55h 555h A0h PA PD
555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h
555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h
Sector Erase
Sector Erase Suspend
Sector Erase Resume
Erase can be suspended during sector erase with Addr (“H” or “L”), Data (B0h)
Erase can be resumed after suspend with Addr (“H” or “L”), Data (30h)
*1 : Either of the two reset commands will reset the device.
*2 : The fourth bus cycle is only for read.
Notes : • Address bits A17 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA).
• Bus operations are defined in “MBM29F002TC/BC User Bus Operations Table” in “■FLEXIBLE SECTOR-
ERASE ARCHITECTURE”.
• RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of
the WE pulse.
SA = Address of the sector to be erased. The combination of A17, A16, A15, A14, and A13 will uniquely select
any sector.
• RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
ID = Device Code (Refer to the section on Sector Protection Verify Autoselect Codes.)
• The command combinations not described in “MBM29F002TC/BC Command Definitions Table”
in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE” are illegal.
MBM29F002TC/BC Sector Protection Verify Autoselect Codes
Type
A17 to A13
A10
VIL
VIL
VIL
A6
VIL
VIL
VIL
A1
VIL
VIL
VIL
A0
VIL
VIH
VIH
Code (HEX)
04h
Manufacture’s Code
X
X
X
MBM29F002TC
B0h
Device Code
MBM29F002BC
34h
Sector
Addresses
Sector Protection
VIL
VIL
VIH
VIL
01h*
* : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.
8
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
Extended Autoselect Code Table
Type
Code
04h
DQ7
0
DQ6
0
DQ5
0
DQ4
0
DQ3
0
DQ2
1
DQ1
0
DQ0
0
Manufacture’s Code
MBM29F002TC
B0h
34h
1
0
1
1
0
0
0
0
Device Code
MBM29F002BC
0
0
1
1
0
1
0
0
Sector Protection
01h
0
0
0
0
0
0
0
1
Sector Address Table (MBM29F002TC)
A17
0
A16
0
A15
X
X
X
0
A14
X
X
X
X
0
A13
X
X
X
X
0
Address Range
00000h to 0FFFFh
10000h to 1FFFFh
20000h to 2FFFFh
30000h to 37FFFh
38000h to 39FFFh
3A000h to 3BFFFh
3C000h to 3FFFFh
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
X
Sector Address Table (MBM29F002BC)
A17
0
A16
0
A15
0
A14
0
A13
X
0
Address Range
00000h to 03FFFh
04000h to 05FFFh
06000h to 07FFFh
08000h to 0FFFFh
10000h to 1FFFFh
20000h to 2FFFFh
30000h to 3FFFFh
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
0
0
1
0
0
0
1
1
0
0
1
X
X
X
X
X
X
X
X
0
1
X
X
X
1
0
1
1
9
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
Sector Architecture
3FFFFh
3BFFFh
39FFFh
37FFFh
2FFFFh
1FFFFh
0FFFFh
00000h
3FFFFh
16K byte
8K byte
64K byte
64K byte
64K byte
32K byte
8K byte
2FFFFh
1FFFFh
0FFFFh
07FFFh
05FFFh
03FFFh
00000h
8K byte
32K byte
64K byte
64K byte
64K byte
8K byte
16K byte
MBM29F002TC Sector Architecture
MBM29F002BC Sector Architecture
10
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
■ FUNCTIONAL DESCRIPTION
Read Mode
The MBM29F002TC/BC has two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the
addresses have been stable for at least tACC-tOE time).
Standby Mode
There are two ways to implement the standby mode on the MBM29F002TC/BC devices, one using both the CE
and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ±0.3 V.
Under this condition the current consumed is less than 5 µA. A TTL standby mode is achieved with CE and
RESET pins held at VIH. Under this condition the current is reduced to approximately 1 mA. During Embedded
Algorithm operation, VCC Active current (ICC2) is required even CE = VIH. The device can be read with standard
access time (tCE) from either of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ±0.3 V
(CE = “H” or “L”). Under this condition the current consumed is less than 5 µA. A TTL standby mode is achieved
with RESET pin held at VIL (CE = “H” or “L”). Under this condition the current required is reduced to approximately
1 mA. Once the RESET pin is taken high, the device requires 500 ns of wake up time before outputs are valid
for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the device.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All
addressesaredon'tcaresexceptA0,A1,A6 andA10.(See“MBM29F002TC/BCSectorProtectionVerifyAutoselect
Code Table” and “Extended Autoselect Code Table” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29F002TC/BC is erased or programmed in a system without access to high voltage on the A9 pin. The
commandsequenceisillustratedin“MBM29F002TC/BCCommandDefinitionsTable”in“■FLEXIBLESECTOR-
ERASE ARCHITECTURE”. (Refer to Autoselect Command section.)
Byte 0 (A0 = VIL) represents the manufacturer's code (Fujitsu = 04h) and byte 1 (A0 = VIH) represents the device
identifier code for MBM29F002TC = B0h, MBM29F002BC = 34h. These two bytes are given in the
“MBM29F002TC/BC Sector Protection Verify Autoselect Code Table” and “Extended Autoselect Code Table” in
“■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”. All identifiers for manufactures and device will exhibit odd
parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Autoselect,
11
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
A1 must be VIL. (See “MBM29F002TC/BC Sector Protection Verify Autoselect Code Table” and “Extended Au-
toselect Code Table” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”.)
The Autoselect mode also facilitates the determination of sector protection in the system. By performing a read
operation at the address location XX02h with the higher order address bits A13, A14, A15, A16 and A17 set to the
desired sector address, the device will return 01h for a protected sector and 00h for a non-protected sector.
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29F002TC/BC features hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 6). The sector protection feature is enabled using programming
equipment at the user's site. The device is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5 V), CE = VIL. The sector addresses (A13, A14, A15, A16, and A17) should be set to the sector to be
protected. “Sector Address Table (MBM29F002TC) ” and “Sector Address Table (MBM29F002BC) ” in “■ FLEX-
IBLE SECTOR-ERASE ARCHITECTURE”. define the sector address for each of the seven (7) individual sectors.
Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the
rising edge of the same. Sector addresses must be held constant during the WE pulse. See “AC Waveforms for
Sector Protection Timing Diagram” in “■ TIMING DIAGRAM” and “Sector Protection Algorithm” in “■ FLOW
CHART” for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A13, A14, A15, A16, and A17) while (A10, A6,
A1, A0) = (0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the
device will produce 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, A6,
and A10 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device
codes.
ItisalsopossibletodetermineifasectorisprotectedinthesystembywritinganAutoselectcommand. Performing
a read operation at the address location XX02h, where the higher order addresses (A13, A14, A15, A16, and A17)
are the desired sector address will produce a logical “1” at DQ0 for a protected sector. See “MBM29F002TC/BC
Sector Protection Verify Autoselect Code Table” and “Extended Autoselect Code Table” in “■ FLEXIBLE SEC-
TOR-ERASE ARCHITECTURE” for Autoselect codes.
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29F002TC/BC device in
order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage
(12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the 12 V is taken away from the RESETpin, all the previously protected sectors will be protected
again. See “Temporary Sector Unprotection Timing Diagram” in “■ TIMING DIAGRAM” and “Temporary Sector
Unprotection Algorithm” in “■ FLOW CHART”.
12
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the device to the
read mode. “MBM29F002TC/BC Command Definitions Table” in “■ FLEXIBLE SECTOR-ERASE ARCHITEC-
TURE” defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume
(30h) commands are valid only while the Sector Erase operation is in progress. Moreover, both Read/Reset
commands are functionally equivalent, resetting the device to the read mode.
Read/Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the
command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desirable system design practice.
The device contains an autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read
cycle from address XX01h returns the device code D5h. (See “MBM29F002TC/BC Sector Protection Verify
Autoselect Code Table” and “Extended Autoselect Code Table” in “■ FLEXIBLE SECTOR-ERASE
ARCHITECTURE”).
All manufacturer and device codes will exhibit odd parity with the DQ7 defined as the parity bit.
Sector state (protection or unprotection) will be informed by address XX02h.
Scanning the sector addresses (A17, A16, A15, A14, and A13) while (A10, A6, A1, A0) = (0, 0, 1, 0) will produce a
logical “1” at device output DQ0 for a protected sector.
To terminate the operation, it is necessary to write the read/reset command sequence into the register and also
to write the Autoselect command during the operation, execute it after writing Read/Reset command sequence.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of
CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming.
Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide
further controls or timings. The device will automatically provide adequate internally generated program pulses
and verify the programmed cell margin.
This automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the device returns to the read mode and addresses are no longer latched. (See “Hardware
Sequence Flags Table” in “■FUNCTIONAL DESCRIPTION”.) Therefore, the device requires that a valid address
13
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
to the device be supplied by the system at this particular instance of time. Data Polling must be performed at
the memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If a hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from reset/read mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“Embedded EraseTM Algorithm” in “■ FLOW CHART” illustrates the Embedded ProgrammingTM Algorithm using
typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (see Write Operation Status section) at which time the device returns to read the
mode.
“Data Polling Algorithm” in “■ FLOW CHART” illustrates the Embedded Erase™ Algorithm using typical
command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data = 30h) is latched on the rising edge of WE. After time-out of 50 µs from the rising edge of the last sector
erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29F002TC/BC
Command Definitions Table” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”. This sequence is followed
with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The
time between writes must be less than 50 µs otherwise that command will not be accepted and erasure will start.
It is recommended that processor interrupts be disabled during this time to guarantee this condition. The
interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising
edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE
occurs within the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer
window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase
Suspend during this time-out period will reset the device to the read mode, ignoring the previous command
string. Resetting the device once execution has begun will corrupt the data in that sector. In that case, restart
the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for DQ3,
Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any
number of sectors (0 to 6).
Sector erase does not require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the
14
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
remaining unselected sectors are not affected. The system is not required to provide any controls or timings
during these operations.
The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (see Write Operation Status section)
at which time the device returns to the read mode. Data polling must be performed at an address within any of
the sectors being erased.
“Data Polling Algorithm” in “■ FLOW CHART” illustrates the Embedded Erase™ Algorithm using typical
command strings and bus operations.
Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
fromorprogramstoasectornotbeingerased. ThiscommandisapplicableONLYduringaSectorEraseoperation
which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written
during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command during
the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase
operation.
AnyothercommandwrittenduringtheEraseSuspendmodewillbeignoredexcepttheEraseResumecommand.
Writing the Erase Resume command resumes the erase operation. The addresses are DON’T CARES when
writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 15 µs to suspend the erase operation. When the device has entered the erase-suspended mode, the DQ7 bit
will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading
DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend
command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Byte Program. This program mode is known as the erase-suspend-program mode.
Again, programming in this mode is the same as programming in the regular Byte Program mode except that
the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-
suspended sector while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of
the erase-suspended program operation is detected by Data polling of DQ7, or by the Toggle Bit I (DQ6) which
is the same as the regular Byte Program operation. Note that DQ7 must be read from the Byte Program address
while DQ6 can be read from any address.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
15
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
Write Operation Status
Status
DQ7
DQ7
0
DQ6
DQ5
0
DQ3
0
DQ2
1
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
0
1
Toggle
Erase Suspend Read
(Erase Suspended Sector)
Toggle*1
1
1
0
Data
0
0
Data
0
In Progress
Erase
Erase Suspend Read
(Non-Erase Suspended Sector)
Suspended
Mode
Data
DQ7
Data
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
Toggle*2
1*3
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
DQ7
0
Toggle
Toggle
1
1
0
1
1
N/A
Exceeded
Time Limits
Erase Suspend Program
Suspended
Mode
DQ7
Toggle
1
0
N/A
(Non-Erase Suspended Sector)
*1 : Performing successive read operations from the erase-suspended sector will cause DQ2 to toggle.
*2 : Performing successive read operations from any address will cause DQ6 to toggle.
*3 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”
at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
DQ7
Data Polling
The MBM29F002TC/BC device features Data Polling as a method to indicate to the host that the embedded
algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device
will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase™ Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in “Toggle Bit I Algorithm” in “■ FLOW CHART”.
Data polling will also flag the entry into Erase Suspend. DQ7 will switch “0” to “1” at the start of the Erase Suspend
mode. Please note that the address of an erasing sector must be applied in order to observe DQ7 in the Erase
Suspend Mode.
During Program in Erase Suspend, Data polling will perform the same as in regular program execution outside
of the suspend mode.
For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence.
For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling
must be performed at sector address within any of the sectors being erased and not a sector that is within a
protected sector. Otherwise, the status may not be valid.
Just prior to the completion of Embedded Algorithm operation DQ7 may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of
time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations
and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will
be read on the successive read attempts.
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MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out. (See “Hardware Sequence
Flags Table” in “■ FUNCTIONAL DESCRIPTION”.)
See “AC waveforms for Data Polling during Embedded Algorithm Operations” in “■ TIMING DIAGRAM” for the
Data Polling timing specifications and diagrams.
DQ6
Toggle Bit I
The MBM29F002TC/BC also features the “Toggle Bit I” as a method to indicate to the host system that the
embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or
Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive
attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four
write pulse sequence. For chip erase, and sector erase the Toggle Bit I is valid after the rising edge of the sixth
WE pulse in the six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of
the sector erase WE pulse. The Toggle Bit I is active during the sector erase time out.
In programming, if the sector being written to is protected, the Toggle Bit I will toggle for about 2 µs and then
stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for
the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about
100 µs and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause DQ6 to toggle.
See “AC waveforms for Toggle Bit I during Embedded Algorithm Operations” in “■ TIMING DIAGRAM” for the
Toggle Bit I timing specifications and diagrams.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling DQ7, DQ6 is the only operating function of the device under
this condition. The CE circuit will partially power down the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output disable functions as described in “MBM29F002TC/BC User
Bus Operations Table” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”.
TheDQ5 failureconditionmayalsoappearifausertriestoprograma1toalocationthatispreviouslyprogrammed
to 0. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the
system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing
limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was
incorrectly used. If this occurs, reset the device.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
17
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will
be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”),
the device will accept additional sector erase commands. To insure the command has been accepted, the system
software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3
were high on the second status check, the command may not have been accepted.
Refer to “Hardware Sequence Flags Table” in “■ FUNCTIONAL DESCRIPTION”.
DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase™
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase™ Algorithm. If
the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
Mode
DQ7
DQ7
0
DQ6
DQ2
1
Program
Erase
Toggle
Toggle
Toggle
Erase Suspend Read *1
(Erase-Suspended Sector)
1
1
Toggle
1*2
DQ7 *2
Erase Suspend Program
Toggle
*1 : These status flags apply when outputs are read from a sector that has been erase-suspended.
*2 : These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode (DQ2 toggles while
DQ6 doesnot). Seealso“HardwareSequenceFlagsTable”in“■FUNCTIONALDESCRIPTION”and“Embedded
ProgramTM Algorithm” in “■ FLOW CHART”.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from the erasing sector.
RESET
Hardware Reset
The MBM29F002TC/BC device may be reset by driving the RESET pin to VIL. The RESET pin must be kept low
(VIL) for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset
to the read mode 20 µs after the RESET pin is driven low. If a hardware reset occurs during a program operation,
the data at that particular location will be indeterminate.
When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be
accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the
RESET pin is taken high, the device requires tRH of wake up time until outputs are valid for read access.
18
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded
Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system’s
microprocessor to read the boot-up firmware from the Flash memory.
Data Protection
The MBM29F002TC/BC is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completions of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 3.2 V (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 3.2 V.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
19
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min
−55
−40
Max
+125
+85
Storage Temperature
Tstg
TA
°C
°C
Ambient Temperature with Power Applied
Voltage with Respect to Ground All pins except
A9, OE, and RESET *1, *2
VIN, VOUT
−2.0
+7.0
V
Power Supply Voltage *1, *3
A9, OE, and RESET *2
VCC
VIN
−2.0
−2.0
+7.0
V
V
+13.5
*1 : Voltage is defined on the basis of VSS = GND = 0 V.
*2 : Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC +0.5 V. During
voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns.
*3 : Minimum DC input voltage on A9, OE, and RESET pins is –0.5 V. During voltage transitions, A9, OE, and
RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and
power supply (VIN – VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE, and RESET is
+13.0 V which may overshoot to +14.0 V for periods up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Ambient Temperature
VCC Supply Voltages*
Symbol
TA
Unit
Min
−40
Max
+85
°C
V
MBM29F002TC/BC-55
+4.75
+4.50
+5.25
+5.50
VCC
MBM29F002TC/BC-70/-90
V
* : Voltage is defined on the basis of VSS = GND = 0 V.
Note : Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
20
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
1. Maximum Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
2. Maximum Overshoot Waveform 1
20 ns
VCC +2.0 V
VCC +0.5 V
+2.0 V
20 ns
20 ns
3. Maximum Overshoot Waveform 2
20 ns
+14.0 V
+13.0 V
VCC +0.5 V
20 ns
20 ns
Note : This waveform is applied for A9, OE and RESET.
21
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
■ DC CHARACTERISTICS
Value
Parameter
Symbol
Test Conditions
Unit
Min
Max
Input Leakage Current
Output Leakage Current
ILI
VIN = VSS to VCC, VCC = VCC Max
—
±1.0
µA
µA
VOUT = VSS to VCC,
VCC = VCC Max
ILO
—
—
±1.0
50
A9, OE, RESET Inputs Leakage
Current
VCC = VCC Max,
A9, OE, RESET = 12.5 V
ILIT
µA
VCC Active Current *1
VCC Active Current *2
ICC1
ICC2
CE = VIL, OE = VIH
CE = VIL, OE = VIH
—
—
35
50
mA
mA
VCC = VCC Max, CE = VIH,
RESET = VIH
—
—
—
—
1
5
1
5
mA
µA
VCC Current (Standby)
ICC3
ICC4
VCC = VCC Max, CE = VCC ±0.3 V,
RESET = VCC ±0.3 V
VCC = VCC Max,
RESET = VIL
mA
µA
VCC Current (Standby, Reset)
VCC = VCC Max,
RESET = VSS ±0.3 V
Input Low Level
Input High Level
VIL
—
—
–0.5
2.0
0.8
V
V
VIH
VCC+0.5
Voltage for Autoselect and Sector
Protection (A9, OE, RESET) *3, *4
VID
—
11.5
12.5
V
Output Low Voltage Level
Output High Voltage Level
Low VCC Lock-Out Voltage
VOL
IOL = 12.0 mA, VCC = VCC Min
IOH = –2.5 mA, VCC = VCC Min
IOH = –100 µA
—
2.4
0.45
—
V
V
V
V
VOH1
VOH2
VLKO
VCC–0.4
3.2
—
—
4.2
*1 : The ICC current listed includes both the DC operating current and the frequency dependent component
(at 6 MHz). The frequency component typically is 2 mA/MHz, with OE at VIH.
*2 : ICC active while Embedded Algorithm (program or erase) is in progress.
*3 : Applicable to sector protection function.
*4 : (VID – VCC) do not exceed 9 V.
22
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
■ AC CHARACTERISTICS
•
Read Only Operations Characteristics
Value
-70*2
Symbol
Test
Setup
-55*1
-90*2
Parameter
Unit
JEDEC Standard
Min Max Min Max Min Max
Read Cycle Time
tAVAV
tRC
—
55
—
70
—
90
—
ns
ns
CE = VIL
OE = VIL
Address to Output Delay
tAVQV
tACC
—
55
—
70
—
90
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
OE = VIL
—
—
—
—
55
30
20
20
—
—
—
—
70
30
20
20
—
—
—
—
90
35
20
20
ns
ns
ns
ns
—
—
—
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First
tAXQX
—
tOH
—
—
0
—
0
—
0
—
ns
RESET Pin Low to Read Mode
tREADY
—
20
—
20
—
20
µs
*1 : Test Conditions:
*2 : Test Conditions:
Output Load:1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or 3.0 V
Timing measurement reference level
Input: 1.5 V
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.45 V or 2.4 V
Timing measurement reference level
Input: 0.8 V and 2.0 V
Output: 1.5 V
Output: 0.8 V and 2.0 V
5.0 V
Diode = 1N3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diode = 1N3064
or Equivalent
Notes : • CL = 30 pF including jig capacitance
• CL = 100 pF including jig capacitance
Figure 4 Test Conditions
23
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
•
Write/Erase/Program Operations
MBM29F002TC/BC
-70
Symbol
Standard
-55
-90
Parameter
Unit
JEDEC
Min Typ Max Min Typ Max Min Typ Max
Write Cycle Time
tAVAV
tAVWL
tWLAX
tDVWH
tWHDX
—
tWC
tAS
55
0
70
0
90
0
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
tAH
40
25
0
45
30
0
45
45
0
tDS
Data Hold Time
tDH
tOES
Output Enable Setup Time
0
0
0
Read
0
0
0
OutputEnable
—
tOEH
Toggle Bit I and
Data Polling
Hold Time
10
10
10
ns
Read Recover Time Before Write
Read Recover Time Before Write
CE Setup Time
tGHWL
tGHEL
tELWL
tWLEL
tWHEH
tEHWH
tWLWH
tELEH
tGHWL
tGHEL
tCS
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
0
0
0
WE Setup Time
tWS
0
0
0
CE Hold Time
tCH
0
0
0
WE Hold Time
tWH
0
0
0
Write Pulse Width
tWP
30
30
20
20
35
35
20
20
45
45
20
20
Write Pulse Width
tCP
Write Pulse Width High
Write Pulse Width High
Byte Programming Operation
tWHWL
tEHEL
tWPH
tCPH
tWHWH1
tWHWH1
8
1
8
1
8
1
s
s
Sector Erase Operation *1
tWHWH2
tWHWH2
8
8
8
VCC Setup Time
—
—
—
—
—
—
tVCS
tVIDR
tVLHT
tWPP
tOESP
tCSP
50
500
4
50
500
4
50
500
4
µs
ns
µs
µs
µs
µs
Rise Time to VID
Voltage Transition Time *2
Write Pulse Width *2
100
4
100
4
100
4
OE Setup Time to WE Active *2
CE Setup Time to WE Active *2
4
4
4
(Continued)
24
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(Continued)
MBM29F002TC/BC
Symbol
-55
-70
-90
Parameter
Unit
Standard
tRP
JEDEC
—
Min Typ Max Min Typ Max Min Typ Max
RESET Pulse Width
500
50
500
50
500
50
ns
ns
RESET Hold Time Before Read
—
tRH
Delay Time from Embedded Output
Enable
—
tEOE
30
30
35
ns
*1 : This does not include the preprogramming time.
*2 : This timing is for Sector Protection operation.
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Comments
Min
Typ
Max
Excludes 00h programming
prior to erasure
Sector Erase Time
—
1
8
s
Excludes system-level
overhead
Byte Programming Time
—
8
150
µs
Excludes system-level
overhead
Chip Programming Time
Erase/Program Cycle
—
2.1
—
5
s
100,000
—
cycle
■ TSOP(1) PIN CAPACITANCE
Value
Unit
Parameter
Symbol
Test Setup
Typ
Max
Input Capacitance
CIN
VIN = 0
7
8
8
8
pF
pF
pF
Output Capacitance
COUT
CIN2
VOUT = 0
VIN = 0
10
10
Control Pin Capacitance
Note : Test conditions TA = +25°C, f = 1.0 MHz
■ PLCC PIN CAPACITANCE
Value
Parameter
Symbol
Test Setup
Unit
Typ
7
Max
8
Input Capacitance
CIN
VIN = 0
VOUT = 0
VIN = 0
pF
pF
pF
Output Capacitance
COUT
8
10
10
Control Pin Capacitance
CIN2
8
Notes : • Sampled, not 100% tested.
• Test conditions TA = +25°C, f = 1.0 MHz
25
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
■ SWITCHING WAVEFORMS
•
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
“H” or “L”
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center Line is
High-
Impedance
“Off” State
(1) AC Waveforms for Read Operations
tRC
Address
Address Stable
tACC
CE
OE
tOE
tDF
tOEH
WE
tCE
High-Z
High-Z
DQ
7
to DQ
0
Output Valid
26
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(2) AC Waveforms for Read Operations
tRC
Address
RESET
Address Stable
tACC
tRH
tOH
High-Z
DQ
7
to DQ
0
Output Valid
(3) AC Waveforms for Alternate WE Controlled Program Operations
3rd Bus Cycle
555h
Data Polling
PA
PA
Address
tAH
tWC
tRC
tAS
CE
tCH
tCS
tCE
OE
tWP
tOE
tWHWH1
tGHWL
WE
tWPH
tOH
tDH
DOUT
DOUT
A0h
PD
DQ7
Data
tDS
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles of four bus cycle sequence.
27
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(4) AC Waveforms for Alternate CE Controlled Program Operations
3rd Bus Cycle
555
Data Polling
Address
WE
h
PA
PA
t
AH
t
WC
tAS
t
WH
t
GHEL
OE
CE
t
CP
t
WHWH1
t
CPH
tWS
t
DH
DQ
7
DOUT
A0
h
PD
Data
tDS
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles of four bus cycle sequence.
28
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(5) AC Waveforms Chip/Sector Erase Operations
2AAh
555h
555h
Address
555h
2AAh
SA*
t
WC
t
AS
t
AH
CE
t
CS
t
CH
OE
t
WP
t
WPH
t
GHWL
WE
t
DS
t
DH
10h/
30h
AAh
55h
80h
AAh
55h
Data
t
VCS
V
CC
* : SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.
(6) AC Waveforms for Data Polling During Embedded Algorithm Operations
tCH
CE
t
DF
tOE
OE
tOEH
WE
tCE
*
High-Z
Valid 7Data
DQ
=
DQ
7
Data
Data
DQ
7
t
EOE
t
WHWH1 or 2
High-Z
DQ
7 to DQ0
Valid Data
DQ
6
to DQ
0
DQ
6
to DQ = Output Flug
0
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
29
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
CE
tOEH
WE
tOES
OE
*
DQ6 =
Stop Toggling
DQ7 to DQ0
Data
DQ6 = Toggle
DQ6 = Toggle
DQ6
Valid
tOE
* : DQ6 stops toggling (The device has completed the Embedded operation.)
(8) RESET Timing Diagram
tRP
RESET
tREADY
30
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(9) AC Waveforms for Sector Protection Timing Diagram
A
17, A , A15,
1164, A13
SAx
SAy
A
A0
A1
A6
V ID
5 V
A9
tVLHT
V ID
5 V
OE
WE
CE
tVLHT
tOESP
tWPP
tVLHT
tVLHT
tCSP
Data
VCC
01h
tOE
tVCS
SGAx = Sector Address for initial sector
SGAy = Sector Address for initial sector
31
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(10) Temporary Sector Unprotection Timing Diagram
VCC
tVIDR
tVCS
tVLHT
VID
5 V
5 V
RESET
CE
Program or Erase Command Sequence
WE
tVLHT
tVLHT
Unprotection period
(11) DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
WE
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2*
Toggle
DQ2 and DQ6
with OE or CE
* : DQ2 is read from the erase-suspended sector.
32
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
■ FLOW CHART
(1) Embedded ProgramTM Algorithm
EMBEDDED ALGORITHMS
Start
Write Program Command
Sequence
(See Below)
Data Polling Device
No
Increment Address
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
33
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(2) Embedded Erase™ Algorithm
Start
Write Erase Command
Sequence
(See Below)
Data Polling or Toggle Bit I
Successfully Completed
Erasure Completed
Individual Sector/Multiple Sector
Chip Erase Command Sequence
Erase Command Sequence
(Address/Command):
(Address/Command):
555h/AAh
2AAh/55h
555h/80h
555h/AAh
2AAh/55h
555h/10h
555h/AAh
2AAh/55h
555h/80h
555h/AAh
2AAh/55h
Sector Address/30h
Sector Address/30h
Sector Address/30h
Additional sector
erase commands
are optional.
Note : To insure the command has been accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on
the second status check, the command may not have been accepted.
34
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(3) Data Polling Algorithm
Start
Read Byte
(DQ7 to DQ0)
Addr. = VA
VA = Address for programming
= Any of the sector addresses
within the sector being erased
during sector erase or multiple
erases operation.
Yes
DQ7 = Data?
No
= Any of the sector
addresses within the sector not
being protected during sector
erase or multiple sector erases
operation.
No
DQ5 = 1?
Yes
Read Byte
(DQ7 to DQ0)
Addr. = VA
Yes
DQ7 = Data?
No
Fail
Pass
Note : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
35
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(4) Toggle Bit I Algorithm
Start
*1
*1
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
No
DQ6 = Toggle
?
Yes
No
DQ5 = 1
?
Yes
*1,*2
*1,*2
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
No
DQ6 = Toggle
?
Yes
Fail
Pass
*1 : Read toggle bit twice to determin whether it is toggling.
*2 : DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5
changing to “1”.
36
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(5) Sector Protection Algorithm
Start
Setup Sector Addr.
(A17, A16, A15, A14, A13)
PLSCNT = 1
OE = VID, A9 = VID,
CE = VIL, RESET = VIH
Increment PLSCNT
Activate WE Pulse
Time out 100 µs
WE = VIH, CE = OE = VIL,
(A9 should remain VID)
Read from Sector
Addr. (A19, A18, A17)
A1 = 1, A0 = A6 = 0
No
PLSCNT = 25?
Yes
No
Data = 01h?
Yes
Yes
Remove VID from A9
Write Reset Command
Protect Another Sector?
No
Remove VID from A9
Device Failed
Write Reset Command
Sector Protection
Completed
37
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(6) Temporary Sector Unprotection Algorithm
Start
RESET = VID*1
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed*2
*1 : All Protected sectors unprotected.
*2 : All previously protected sectors are protected once again.
38
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
■ ORDERING INFORMATION
Part No.
Package
Access Time (ns)
Remarks
MBM29F002TC-55PFTN
MBM29F002TC-70PFTN
MBM29F002TC-90PFTN
32-pin plastic TSOP (1)
(FPT-32P-M24)
55
70
90
(Normal Bend)
MBM29F002TC-55PFTR
MBM29F002TC-70PFTR
MBM29F002TC-90PFTR
32-pin plastic TSOP (1)
(FPT-32P-M25)
55
70
90
Top Sector
(Reverse Bend)
MBM29F002TC-55PD
MBM29F002TC-70PD
MBM29F002TC-90PD
55
70
90
32-pin plastic QFJ (PLCC)
(LCC-32P-M02)
MBM29F002BC-55PFTN
MBM29F002BC-70PFTN
MBM29F002BC-90PFTN
32-pin plastic TSOP (1)
(FPT-32P-M24)
55
70
90
(Normal Bend)
MBM29F002BC-55PFTR
MBM29F002BC-70PFTR
MBM29F002BC-90PFTR
32-pin plastic TSOP (1)
(FPT-32P-M25)
55
70
90
Bottom Sector
(Reverse Bend)
MBM29F002BC-55PD
MBM29F002BC-70PD
MBM29F002BC-90PD
55
70
90
32-pin plastic QFJ (PLCC)
(LCC-32P-M02)
MBM29F002
T
C
-70
PFTN
PACKAGE TYPE
PFTN = 32-Pin Thin Small Outline Package
(TSOP (1) ) Normal Bend
PFTR = 32-Pin Thin Small Outline Package
(TSOP (1) ) Reverse Bend
PD
= 32-Pin Rectangular Plastic Leaded
Chip Carrier (QFJ (PLCC) )
SPEED OPTION
See Product Selector Guide
C = Device Revision
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29F002
2 Mega-bit (256K × 8-Bit) CMOS Flash Memory
5.0 V-only Read, Write, and Erase
39
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
■ PACKAGE DIMENSIONS
32-pin plastic TSOP(1)
Note 1) * : Resin protrusion. (Each side : +0.15 (.006) Max)
Note 2) Pins width and pins thickness include plating thickness.
(FPT-32P-M24)
Note 3) Pins width do not include tie bar cutting remainder.
Details of "A" part
LEAD No.
1
32
0.25(.010)
INDEX
0~8˚
0.60±0.15
(.024±.006)
16
17
0.17 –+00..0083
.007 –+..000031
0.10±0.05(.004±.002)
(Stand off)
20.00±0.20
(.787±.008)
*18.40±0.20
(.724±.008)
*8.00±0.20
(.315±.008)
1.10 +–00..0150
.043 +–..000024
(Mounting height)
0.50(.020)
0.10(.004)
"A"
0.22±0.05
(.009±.002)
M
0.10(.004)
C
2002 FUJITSU LIMITED F32035S-c-4-4
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
(Continued)
40
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
32-pin plastic TSOP(1)
Note 1) * : Resin protrusion. (Each side : +0.15 (.006) Max)
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
(FPT-32P-M25)
Details of "A" part
LEAD No.
1
32
0.60±0.15
(.024±.006)
INDEX
0~8˚
0.25(.010)
16
17
0.22±0.05
(.009±.002)
M
0.10(.004)
0.10±0.05(.004±.002)
0.17 –+00..0083
(Stand off)
0.50(.020)
.007 –+..000031
0.10(.004)
1.10 –+00..0150
(Mounting height)
.043 –+..000024
"A"
*18.40±0.20
(.724±.008)
*8.00±0.20
(.315±.008)
20.00±0.20
(.787±.008)
C
2002 FUJITSU LIMITED F32036S-c-4-5
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
(Continued)
41
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
(Continued)
32-pin plastic QFJ(PLCC)
(LCC-32P-M02)
3.40±0.16
12.37±0.13
(.134±.006)
(.487±.005)
2.25±0.38
11.43±0.08
7.62(.300)REF
(.089±.015)
(.450±.003)
0.64(.025)
MIN
1.27±0.13
(.050±.005)
4
1
32
30
5
29
INDEX
12.95±0.51
(.510±.020)
13.97±0.08 14.94±0.13
(.550±.003) (.588±.005)
10.16(.400)
REF
13
21
14
20
R0.95(.037)
TYP
0.66(.026)
TYP
0.20 –+00..0025
.008 –+..000012
0.43(.017)
TYP
0.10(.004)
10.41±0.51
(.410±.020)
No
: LEAD No.
C
1994 FUJITSU LIMITED C32021S-2C-4
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
42
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
FUJITSU LIMITED
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representatives before ordering.
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circuit examples, in this document are presented solely for the
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information. When you develop equipment incorporating the
device based on such information, you must assume any
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F0306
FUJITSU LIMITED Printed in Japan
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