MBM29LV160TE-90TN_技术文档

MBM29LV160TE/BE70/90

Data Sheet (Retired Product)

MBM29LV160TE/BE70/90Cover Sheet

This product has been retired and is not recommended for new designs. Availability of this document is retained for reference

and historical purposes only.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been

made are the result of normal data sheet improvement and are noted in the document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number MBM29LV160TE/BE

Revision DS05-20883-7E

Issue Date July 31, 2007

D a t a S h e e t ( R e t i r e d P r o d u c t )

This page left intentionally blank.

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MBM29LV160TE/BE_DS05-20883-7E July 31, 2007

TM

SPANSION Flash Memory

Data Sheet

September 2003

This document specifies SPANSION^TMmemory products that are now offered by both Advanced Micro Devices and

Fujitsu. Although the document is marked with the name of the company that originally developed the specification,

these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a SPANSION^TMproduct. Future routine

revisions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these

products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about SPANSION^TMmemory

solutions.

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20883-7E

FLASH MEMORY

CMOS

16M (2M × 8/1M × 16) BIT

MBM29LV160TE/BE70/90

■ GENERAL DESCRIPTION

The MBM29LV160TE/BE is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words

of 16 bits each. The MBM29LV160TE/BE is offered in a 48-pin TSOP (1), 48-pin CSOP and 48-ball FBGA

packages. The device is designed to be programmed in-system with the standard system 3.0 V V^CCsupply.

12.0 V V^PPand 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed

in standard EPROM programmers.

The standard MBM29LV160TE/BE offers access times of 70 ns and 90 ns allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write

enable (WE), and output enable (OE) controls.

The MBM29LV160TE/BE is pin and command set compatible with JEDEC standard E²PROMs. Commands are

written to the command register using standard microprocessor write timings. Register contents serve as input

to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch

addresses and data needed for the programming and erase operations. Reading data out of the device is similar

to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV160TE/BE is programmed by executing the program command sequence. This will invoke the

Embedded Program^TM* Algorithm which is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase^TM*

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the device automatically times the erase pulse widths and

verifies proper cell margins.

(Continued)

■ PRODUCT LINE UP

MBM29LV160TE/160BE

Part No.

70

90

+0.6 V

–0.3 V

Power Supply Voltage V^CC(V)

V^CC= 3.0 V

Max Address Access Time (ns)

Max CE Access Time (ns)

Max OE Access Time (ns)

70

30

90

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(Continued)

Any individual sector is typically erased and verified in 1.0 second (if already preprogrammed).

The device also features sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed withoutaffecting other sectors. The MBM29LV160TE/BE is erased when shipped from the factory.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V^CCdetector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,

by the Toggle Bit feature on DQ⁶, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the device internally resets to the read mode.

The MBM29LV160TE/BE also has a hardware RESET pin. When this pin is driven low, execution of any Em-

bedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then

reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset

occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically

reset to the read mode and will have erroneous data stored in the address locations being programmed or

erased. These locations need re-writing after the Reset. Resetting the device enables the system’s micropro-

cessor to read the boot-up firmware from the Flash memory.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The MBM29LV160TE/BE memory electrically erases all bits

within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word

at a time using the EPROM programming mechanism of hot electron injection.

*: Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

■ PACKAGES

48-pin plastic TSOP (1)

Marking Side

(FPT-48P-M19)

(FPT-48P-M20)

48-pin plastic CSOP

48-ball plastic FBGA

(LCC-48P-M03)

(BGA-48P-M11)

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MBM29LV160TE70/90/MBM29LV160BE70/90

■ FEATURES

• 0.23 μm Process Technology

• Single 3.0 V Read, Program and Erase

Minimizes system level power requirements

• Compatible with JEDEC-standard Commands

Uses same software commands as E²PROMs

• Compatible with JEDEC-standard Worldwide Pinouts

48-pin TSOP (1) (Package suffix: TN-Normal Bend Type, TR-Reversed Bend Type)

48-pin CSOP (Package suffix: PCV)

48-ball FBGA (Package suffix: PBT)

• Minimum 100,000 Program/Erase Cycles

• High Performance

70 ns maximum access time

• Sector Erase Architecture

One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode

One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode

Any combination of sectors can be concurrently erased. Also supports full chip erase

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• Embedded Erase^TMAlgorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TMAlgorithms

Automatically programs and verifies data at specified address

• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion

• Ready/Busy Output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic Sleep Mode

When addresses remain stable, the device automatically switches to low power mode

• Low V^CCWrite Inhibit ≤ 2.5 V

• Erase Suspend/Resume

Suspends the erase operation to allow to read data and/or program in another sector within the same device

• Sector Protection

Hardware method disables any combination of sectors from program or erase operations

• Sector Protection Set Function by Extended Sector Protection Command

• Fast Programming Function by Extended Command

• Temporary Sector Unprotection

Temporary sector unprotection via the RESET pin

• In Accordance with CFI (Common Flash Memory Interface)

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MBM29LV160TE70/90/MBM29LV160BE70/90

■ PIN ASSIGNMENTS

TSOP(1)

A

15

14

13

12

11

10

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

(Marking Side)

2

BYTE

3

VSS

4

DQ15/A-1

5

DQ7

6

DQ14

A

9

8

7

DQ6

A

8

DQ13

A

19

9

DQ5

N.C.

WE

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DQ12

DQ

4

RESET

N.C.

VCC

Normal Bend

DQ11

N.C.

DQ3

RY/BY

DQ10

A

18

17

DQ

OE

2

9

1

8

0

A

7

6

5

4

3

2

1

A

V

SS

CE

A0

(FPT-48P-M19)

(Marking Side)

A

1

2

3

4

5

6

7

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

45

46

47

48

A

0

CE

VSS

OE

DQ

0

8

1

9

2

A

17

18

A

RY/BY

N.C.

DQ10

DQ

3

N.C.

DQ11

Reverse Bend

RESET

WE

VCC

DQ

4

N.C.

DQ12

A

19

DQ5

A

8

9

8

DQ13

A

7

DQ6

A10

A11

A12

A13

A14

A15

6

DQ14

5

DQ7

4

DQ15/A-1

3

VSS

2

BYTE

1

A16

(FPT-48P-M20)

(Continued)

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(Continued)

CSOP

(TOP VIEW)

(Marking side)

A¹

A2

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A0

2

CE

A3

3

VSS

OE

A4

4

A5

5

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

VCC

A6

6

A7

7

A17

8

A18

9

RY/BY

N.C.

RESET

WE

N.C.

A¹⁹

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DQ4

DQ12

DQ5

DQ13

DQ6

DQ14

DQ7

DQ15/A-1

VSS

A8

A9

A10

A11

A12

A13

A14

BYTE

A16

A15

(LCC-48P-M03)

FBGA

(TOP VIEW)

Making side

B6

C6

D6

E6

F6

G6

H6

A6

A

B5

12

A

C5

14

A

D5

15

A

E5

16

DQ15/A-1

VSS

A

A5

13

BYTE

F5

G5 H5

A

8

A

10

A

11

DQ

7

DQ14

F4

DQ12

F3

DQ10

F2

DQ13 DQ

G4 H4

DQ

H3

6

A

9

B4

RESET

B3

N.C.

B2

C4

N.C.

C3

A

C2

D4

A

E4

DQ

A4

WE

A3

19

5

V

CC

4

D3

N.C.

D2

E3

DQ

E2

G3

2

DQ11 DQ

G2 H2

DQ

H1

3

18

RY/BY

A2

A17

A

6

A

5

DQ0

DQ8

DQ

G1

OE

9

1

A7

B1

C1

A

D1

A

E1

F1

A1

A4

2

1

A0

VSS

A3

CE

(BGA-48P-M11)

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MBM29LV160TE70/90/MBM29LV160BE70/90

■ BLOCK DIAGRAM

DQ¹⁵to DQ0

VCC

VSS

RY/BY

Buffer

Input/Output

Buffer

Erase Voltage

Generator

WE

BYTE

State

Control

RESET

Command

Register

Program Voltage

Generator

STB

Chip Enable

Output Enable

Logic

Data Latch

CE

OE

Y-Decoder

Y-Gating

STB

Timer for

Program/Erase

Address

Latch

Low VCC Detector

X-Decoder

Cell Matrix

A¹⁹to A0

A-1

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MBM29LV160TE70/90/MBM29LV160BE70/90

■ PIN DESCRIPTION

MBM29LV160TE/BE Pin Configuration

Pin name

A¹⁹to A0, A-1

DQ¹⁵to DQ0

CE

Function

Address Inputs

Data Inputs/Outputs

Chip Enable

OE

Output Enable

Write Enable

WE

RY/BY

Ready/Busy Output

Hardware Reset Pin/

Temporary Sector Unprotection

RESET

BYTE

N.C.

V^SS

Selects 8-bit or 16-bit mode

Pin Not Connected Internally

Device Ground

V^CC

Device Power Supply

■ LOGIC SYMBOL

A-1

20

A

19 to A

0

16 or 8

DQ15 to DQ

0

CE

OE

RY/BY

WE

RESET

BYTE

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MBM29LV160TE70/90/MBM29LV160BE70/90

■ DEVICE BUS OPERATIONS

MBM29LV160TE/BE User Bus Operation (BYTE = VIH)

DQ15 to DQ0

Operation

CE

OE

WE

A0

A1

A6

A9

RESET

Auto-Select Manufacture Code *¹

Auto-Select Device Code *¹

Read *³

L

H

L

X

L

H

X

H

L

H

A0

X

A⁰

L

VID

A9

X

Code

DOUT

High-Z

DIN

H

VID

L

A1

X

A6

X

A6

L

Standby

X

H

VID

L

Output Disable

X

Write (Program/Erase)

Enable Sector Protection *^2,*⁴

Verify Sector Protection *^2,*⁴

Temporary Sector Unprotection *⁵

Reset (Hardware)/Standby

A1

H

X

A9

VID

X

H

X

L

Code

X

High-Z

MBM29LV160TE/BE User Bus Operation (BYTE = VIL)

DQ15 /

Operation

CE OE WE

A0

A1

A6

A9

DQ7 to DQ0

RESET

A^-1

L

Auto-Select Manufacture Code *¹

Auto-Select Device Code *¹

Read *³

L

H

L

X

L

H

X

H

L

H

A0

X

A0

L

VID

A9

X

Code

DOUT

High-Z

DIN

H

VID

L

A-1

X

A1

X

A6

X

A6

L

Standby

X

H

VID

L

Output Disable

X

Write (Program/Erase)

Enable Sector Protection *^2,*⁴

Verify Sector Protection *^2,*⁴

Temporary Sector Unprotection *⁵

Reset (Hardware)/Standby

A^-1

L

A1

H

X

A9

VID

X

H

X

L

Code

X

High-Z

Legend: L = VIL, H = VIH, X = VIL or VIH.

= Pulse input. See “■DC CHARACTERISTICS” for voltage levels.

*1: Manufacturer and device codes may also be accessed via a command register write sequence. See

“MBM29LV160TE/BE Standard Command Definitions” Table in “■FLEXIBLE SECTOR-ERASE ARCHITEC-

TURE”.

*2: Refer to the section on Sector Protection.

*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*4: V^CC= 3.3 V 10%

*5: It is also used for the extended sector protection.

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MBM29LV160TE70/90/MBM29LV160BE70/90

MBM29LV160TE/BE Standard Command Definitions

Second

Bus

Fourth Bus

Read/Write

Cycle

Bus

Write

Cycles

Req’d

First Bus

Third Bus

Fifth Bus

Sixth Bus

Command

Sequence

Write Cycle

Write Cycle Write Cycle

Write Cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Word

Read/Reset

Autoselect

Program

1

3

4

6

XXXh F0h

—

RA

—

RD

—

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

555h

AAh

2AAh

555h

2AAh

555h

2AAh

555h

2AAh

555h

2AAh

555h

—

555h

AAAh

555h

AAAh

555h

AAAh

555h

AAAh

555h

AAAh

—

55h

F0h

90h

A0h

80h

AAAh

555h

AAh

—

AAAh

555h

AAh

PA

PD

AAh

—

AAAh

555h

AAh

555h

AAAh

555h

AAAh

—

2AAh

555h

2AAh

555h

—

555h

Chip Erase

55h

10h

30h

AAAh

555h

AAh

Sector

Erase

SA

AAAh

Erase Suspend

Erase Resume

1

XXXh B0h

XXXh 30h

—

Word

555h

AAh

2AAh

555h

AAAh

Set to

Fast Mode

3

2

55h

PD

20h

—

Byte

Word

Byte

AAAh

XXXh

A0h

Fast

PA

—

Program *¹

XXXh

4

Reset from Word

XXXh

*

Fast Mode

2

90h

—

F0h

1

Byte

XXXh

*

Extended

Sector

Word

4

1

XXXh 60h SPA 60h SPA 40h SPA SD

—

Protection

Byte

2

*

Word

Byte

55h

AAh

Query *³

98h

—

*1: This command is valid while Fast Mode.

*2: This command is valid while RESET = VID.

*3: The valid addresses are A⁶to A0. The other addresses are “Don’t care”.

*4: The data “00h” is also acceptable.

Notes : • Address bits A¹⁹to A11 = X = “H” or “L” for all address commands except or Program Address (PA) and

Sector Address (SA).

• Bus operations are defined in “MBM29LV160TE/BE User Bus Operation (BYTE = VIH) and (BYTE = VIL)”

Tables in “■DEVICE BUS OPERATIONS”.

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MBM29LV160TE70/90/MBM29LV160BE70/90

• RA =Address of the memory location to be read.

PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of

the WE pulse.

SA =Address of the sector to be erased. The combination of A¹⁹, A18, A17, A16, A15, A14, A13, and A12 will

uniquely select any sector.

• RD =Data read from location RA during read operation.

PD =Data to be programmed at location PA. Data is latched on the rising edge of WE.

• SPA=Sector address to be protected. Set sector address (SA) and (A⁶, A1, A0) = (0, 1, 0).

SD =Sector protection verify data. Output 01h at protected sector addressed and output 00h at

unprotected sector addresses.

• The system should generate the following address patterns:

Word Mode: 555h or 2AAh to addresses A⁰to A10

Byte Mode: AAAh or 555h to addresses A-1 to A10

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

• The command combinations not described in "MBM29LV160TE/BE Standard Command Definitions" are

illegal.

MBM29LV160TE/BE Sector Protection Verify Autoselect Code

Code

A-1*¹

Type

Manufacture’s Code

A¹⁹to A12

A6

A1

A0

(HEX)

04h

X

V^IL

VIL

X

Byte

Word

Byte

C4h

MBM29LV160TE

MBM29LV160BE

X

V^IL

VIL

VIH

22C4h

49h

Device Code

VIL

X

V^IL

VIL

VIH

VIL

Word

2249h

Sector

Addresses

01h*²

Sector Protection

VIL

*1: A^-1is for Byte mode.

*2: Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.

Expanded Autoselect Code Table

Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Type

Manufacture’s Code*

04h A-1/0

C4h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 1

(W) 22C4h

(B) 49h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0

0

1

0

1

0

1

0

1

(B)

MBM29LV160TE

Device

0

1

0

1

0

1

Code

MBM29LV160BE

(W) 2249h

0

1

0

1

0

Sector Protection*

01h A^-1/0

(B): Byte mode

(W): Word mode

HI-Z: High-Z

* : At byte mode, DQ¹⁴to DQ8 are High-Z and DQ15 is A-1, the lowest address.

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MBM29LV160TE70/90/MBM29LV160BE70/90

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE

• One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode.

• One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode.

• Individual-sector, multiple-sector, or bulk-erase capability.

• Individual or multiple-sector protection is user definable.

MBM29LV160TE Top Boot Sector Architecture

Sector

SA0

Sector Size

(× 8) Address Range

00000h to 0FFFFh

10000h to 1FFFFh

20000h to 2FFFFh

30000h to 3FFFFh

40000h to 4FFFFh

50000h to 5FFFFh

60000h to 6FFFFh

70000h to 7FFFFh

80000h to 8FFFFh

90000h to 9FFFFh

A0000h to AFFFFh

B0000h to BFFFFh

C0000h to CFFFFh

D0000h to DFFFFh

E0000h to EFFFFh

F0000h to FFFFFh

100000h to 10FFFFh

110000h to 11FFFFh

120000h to 12FFFFh

130000h to 13FFFFh

140000h to 14FFFFh

150000h to 15FFFFh

160000h to 16FFFFh

170000h to 17FFFFh

180000h to 18FFFFh

190000h to 19FFFFh

1A0000h to 1AFFFFh

1B0000h to 1BFFFFh

1C0000h to 1CFFFFh

1D0000h to 1DFFFFh

1E0000h to 1EFFFFh

1F0000h to 1F7FFFh

1F8000h to 1F9FFFh

1FA000h to 1FBFFFh

1FC000h to 1FFFFFh

(× 16) Address Range

00000h to 07FFFh

08000h to 0FFFFh

10000h to 17FFFh

18000h to 1FFFFh

20000h to 27FFFh

28000h to 2FFFFh

30000h to 37FFFh

38000h to 3FFFFh

40000h to 47FFFh

48000h to 4FFFFh

50000h to 57FFFh

58000h to 5FFFFh

60000h to 67FFFh

68000h to 6FFFFh

70000h to 77FFFh

78000h to 7FFFFh

80000h to 87FFFh

88000h to 8FFFFh

90000h to 97FFFh

98000h to 9FFFFh

A0000h to A7FFFh

A8000h to AFFFFh

B0000h to B7FFFh

B8000h to BFFFFh

C0000h to C7FFFh

C8000h to CFFFFh

D0000h to D7FFFh

D8000h to DFFFFh

E0000h to E7FFFh

E8000h to EFFFFh

F0000h to F7FFFh

F8000h to FBFFFh

FC000h to FCFFFh

FD000h to FDFFFh

FE000h to FFFFFh

64 Kbytes or 32 Kwords

32 Kbytes or 16 Kwords

8 Kbytes or 4 Kwords

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

8 Kbytes or 4 Kwords

16 Kbytes or 8 Kwords

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MBM29LV160TE70/90/MBM29LV160BE70/90

MBM29LV160BE Bottom Boot Sector Architecture

Sector

SA0

Sector Size

(× 8) Address Range

00000h to 03FFFh

04000h to 05FFFh

06000h to 07FFFh

08000h to 0FFFFh

10000h to 1FFFFh

20000h to 2FFFFh

30000h to 3FFFFh

40000h to 4FFFFh

50000h to 5FFFFh

60000h to 6FFFFh

70000h to 7FFFFh

80000h to 8FFFFh

90000h to 9FFFFh

A0000h to AFFFFh

B0000h to BFFFFh

C0000h to CFFFFh

D0000h to DFFFFh

E0000h to EFFFFh

F0000h to FFFFFh

100000h to 10FFFFh

110000h to 11FFFFh

120000h to 12FFFFh

130000h to 13FFFFh

140000h to 14FFFFh

150000h to 15FFFFh

160000h to 16FFFFh

170000h to 17FFFFh

180000h to 18FFFFh

190000h to 19FFFFh

1A0000h to 1AFFFFh

1B0000h to 1BFFFFh

1C0000h to 1CFFFFh

1D0000h to 1DFFFFh

1E0000h to 1EFFFFh

1F0000h to 1FFFFFh

(× 16) Address Range

00000h to 01FFFh

02000h to 02FFFh

03000h to 03FFFh

04000h to 07FFFh

08000h to 0FFFFh

10000h to 17FFFh

18000h to 1FFFFh

20000h to 27FFFh

28000h to 2FFFFh

30000h to 37FFFh

38000h to 3FFFFh

40000h to 47FFFh

48000h to 4FFFFh

50000h to 57FFFh

58000h to 5FFFFh

60000h to 67FFFh

68000h to 6FFFFh

70000h to 77FFFh

78000h to 7FFFFh

80000h to 87FFFh

88000h to 8FFFFh

90000h to 97FFFh

98000h to 9FFFFh

A0000h to A7FFFh

A8000h to AFFFFh

B0000h to B7FFFh

B8000h to BFFFFh

C0000h to C7FFFh

C8000h to CFFFFh

D0000h to D7FFFh

D8000h to DFFFFh

E0000h to E7FFFh

E8000h to EFFFFh

F0000h to F7FFFh

F8000h to FFFFFh

16 Kbytes or 8 Kwords

8 Kbytes or 4 Kwords

SA1

SA2

8 Kbytes or 4 Kwords

SA3

32 Kbytes or 16 Kwords

64 Kbytes or 32 Kwords

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

15

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

Sector Address Table (MBM29LV160TE)

Sector

A¹⁹

A18

A17

A16

A15

A14

A13

A12

(× 8) Address Range (× 16) Address Range

Address

SA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

00000h to 0FFFFh

10000h to 1FFFFh

20000h to 2FFFFh

30000h to 3FFFFh

40000h to 4FFFFh

50000h to 5FFFFh

60000h to 6FFFFh

70000h to 7FFFFh

80000h to 8FFFFh

90000h to 9FFFFh

A0000h to AFFFFh

B0000h to BFFFFh

C0000h to CFFFFh

D0000h to DFFFFh

E0000h to EFFFFh

F0000h to FFFFFh

100000h to 10FFFFh

110000h to 11FFFFh

120000h to 12FFFFh

130000h to 13FFFFh

140000h to 14FFFFh

150000h to 15FFFFh

160000h to 16FFFFh

170000h to 17FFFFh

180000h to 18FFFFh

190000h to 19FFFFh

1A0000h to 1AFFFFh

1B0000h to 1BFFFFh

1C0000h to 1CFFFFh

1D0000h to 1DFFFFh

1E0000h to 1EFFFFh

1F0000h to 1F7FFFh

1F8000h to 1F9FFFh

1FA000h to 1FBFFFh

1FC000h to 1FFFFFh

00000h to 07FFFh

08000h to 0FFFFh

10000h to 17FFFh

18000h to 1FFFFh

20000h to 27FFFh

28000h to 2FFFFh

30000h to 37FFFh

38000h to 3FFFFh

40000h to 47FFFh

48000h to 4FFFFh

50000h to 57FFFh

58000h to 5FFFFh

60000h to 67FFFh

68000h to 6FFFFh

70000h to 77FFFh

78000h to 7FFFFh

80000h to 87FFFh

88000h to 8FFFFh

90000h to 97FFFh

98000h to 9FFFFh

A0000h to A7FFFh

A8000h to AFFFFh

B0000h to B7FFFh

B8000h to BFFFFh

C0000h to C7FFFh

C8000h to CFFFFh

D0000h to D7FFFh

D8000h to DFFFFh

E0000h to E7FFFh

E8000h to EFFFFh

F0000h to F7FFFh

F8000h to FBFFFh

FC000h to FCFFFh

FD000h to FDFFFh

FE000h to FEFFFh

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

1

0

1

X

16

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

Sector Address Table (MBM29LV160BE)

Sector

A¹⁹

A18

A17

A16

A15

A14

A13

A12

(× 8) Address Range (× 16) Address Range

Address

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

00000h to 03FFFh

04000h to 05FFFh

06000h to 07FFFh

08000h to 0FFFFh

10000h to 1FFFFh

20000h to 2FFFFh

30000h to 3FFFFh

40000h to 4FFFFh

50000h to 5FFFFh

60000h to 6FFFFh

70000h to 7FFFFh

80000h to 8FFFFh

90000h to 9FFFFh

A0000h to AFFFFh

B0000h to BFFFFh

C0000h to CFFFFh

D0000h to DFFFFh

E0000h to EFFFFh

F0000h to FFFFFh

100000h to 1FFFFFh

110000h to 11FFFFh

120000h to 12FFFFh

130000h to 13FFFFh

140000h to 14FFFFh

150000h to 15FFFFh

160000h to 16FFFFh

170000h to 17FFFFh

180000h to 18FFFFh

190000h to 19FFFFh

1A0000h to 1AFFFFh

1B0000h to 1BFFFFh

1C0000h to 1CFFFFh

1D0000h to 1DFFFFh

1E0000h to 1EFFFFh

1F0000h to 1FFFFFh

00000h to 01FFFh

02000h to 02FFFh

03000h to 03FFFh

04000h to 07FFFh

08000h to 0FFFFh

10000h to 17FFFh

18000h to 1FFFFh

20000h to 27FFFh

28000h to 2FFFFh

30000h to 37FFFh

38000h to 3FFFFh

40000h to 47FFFh

48000h to 4FFFFh

50000h to 57FFFh

58000h to 5FFFFh

60000h to 67FFFh

68000h to 6FFFFh

70000h to 77FFFh

78000h to 7FFFFh

80000h to 87FFFh

88000h to 8FFFFh

90000h to 97FFFh

98000h to 9FFFFh

A0000h to A7FFFh

A8000h to 8FFFFh

B0000h to B7FFFh

B8000h to BFFFFh

C0000h to C7FFFh

C8000h to CFFFFh

D0000h to D7FFFh

D8000h to DFFFFh

E0000h to E7FFFh

E8000h to EFFFFh

F0000h to F7FFFh

F8000h to FFFFFh

SA2

0

1

SA3

1

0

X

SA4

X

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

17

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

Common Flash Memory Interface Code

DQ15 to DQ0

Description

A⁶to A0

Description

A6 to A0

Query-unique ASCII string

“QRY”

Erase Block Region 1 Information

bit¹⁵to bit0 : y = number of sectors

bit³¹to bit16 : Z = size

2Dh

2Eh

2Fh

30h

0000h

0040h

0000h

10h

11h

12h

0051h

0052h

0059h

(Z × 256 bytes)

Primary OEM Command Set

02h: AMD/FJ standard type

13h

14h

0002h

0000h

Erase Block Region 2 Information

bit¹⁵to bit0 : y = number of sectors

bit³¹to bit16 : Z = size

31h

32h

33h

34h

0001h

0000h

0020h

0000h

Address for Primary

Extended Table

15h

16h

0040h

0000h

(Z × 256 bytes)

Alternate OEM Command Set

(00h = not applicable)

17h

18h

0000h

Erase Block Region 3 Information

bit¹⁵to bit0 : y = number of sectors

bit³¹to bit16 : Z = size

35h

36h

37h

38h

0000h

0080h

0000h

Address for Alternate OEM

Extended Table

19h

1Ah

0000h

(Z × 256 bytes)

V^CCMin voltage (write/erase)

DQ⁷to DQ4 : 1 V,

DQ³to DQ0 : 100 mV

1Bh

0027h

Erase Block Region 4 Information

bit¹⁵to bit0 : y = number of sectors

bit³¹to bit16 : Z = size

39h

3Ah

3Bh

3Ch

001Eh

0000h

0001h

(Z × 256 bytes)

V^CCMax voltage (write/erase)

DQ⁷to DQ4 : 1 V,

1Ch

0036h

DQ³to DQ0 : 100 mV

V^PPMin voltage

V^PPMax voltage

1Dh

1Eh

1Fh

0000h

0004h

Query-unique ASCII string “PRI”

40h

41h

42h

0050h

0052h

0049h

Typical timeout per single

byte/word write 2^Nμs

Typical timeout for Min size

20h

21h

22h

23h

24h

25h

26h

27h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

0015h

Major version number, ASCII

Minor version number, ASCII

43h

44h

45h

46h

47h

0031h

0000h

0002h

0001h

buffer write 2^Nμs

Typical timeout per individual

block erase 2^Nms

Typical timeout for full chip

erase 2^Nms

Address Sensitive Unlock

00h = Required

Max timeout for byte/word

write 2^Ntimes typical

Max timeout for buffer write 2^N

times typical

Erase Suspend

02h = To Read & Write

Sector Protect

00h = Not Supported

X = Number of sectors in per group

Max timeout per individual

block erase 2^Ntimes typical

Max timeout for full chip erase

2^Ntimes typical

Device Size = 2^Nbyte

Sector Temporary Unprotect

01h = Supported

48h

0001h

Flash Device Interface

description

02h : × 8/ × 16

28h

29h

0002h

0000h

Sector Protection Algorithm

49h

4Ah

04h

00h

Number of Sector for Bank 2

00h = Not Supported

Max number of byte in

multi-byte write = 2^N

2Ah

2Bh

0000h

Burst Mode Type

00h = Not Supported

4Bh

4Ch

00h

Number of Erase Block

Regions within device

2Ch

0004h

Page Mode Type

00h = Not Supported

18

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

■ FUNCTIONAL DESCRIPTION

• Read Mode

The MBM29LV160TE/BE has two control functions which must be satisfied in order to obtain data at the outputs.

CE is the power control and should be used for a device selection. OE is the output control and should be used

to gate data to the output pins if a device is selected.

Address access time (t^ACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (t^CE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the

addresses have been stable for at least t^ACC- tOE time.) When reading out a data without changing addresses

after power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”.

• Standby Mode

There are two ways to implement the standby mode on the MBM29LV160TE/BE devices. One is by using both

the CE and RESET pins; the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC 0.3 V.

Under this condition the current consumed is less than 5 μA Max During Embedded Algorithm operation, V^CC

Active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from

either of these standby modes.

When using the RESET pin only, a CMOS standby mode is achieved with the RESET input held at VSS 0.3 V

(CE = “H” or “L”). Under this condition the current consumed is less than 5 μA Max Once the RESET pin is taken

high, the device requires t^RHof wake up time before outputs are valid for read access.

In the standby mode, the outputs are in the high-impedance state, independent of the OE input.

• Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of

MBM29LV160TE/BE data. This mode can be used effectively with an application requesting low power con-

sumption such as handy terminals.

To activate this mode, MBM29LV160TE/BE automatically switches itself to low power mode when addresses

remain stable for 150 ns. It is not necessary to control CE, WE, and OE in this mode. During such mode, the

current consumed is typically 1 μA (CMOS Level).

Standard address access timings provide new data when addresses are changed. While in sleep mode, output

data is latched and always available to the system.

• Output Disable

If the OE input is at a logic high level (VIH), output from the device is disabled. This will cause the output pins to

be in a high-impedance state.

• Autoselect

The Autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer

and type. The intent is to allow programming equipment to automatically match the device to be programmed

with its corresponding programming algorithm. The Autoselect command may also be used to check the status

of write-protected sectors. (See “MBM29LV160TE/BE Sector Protection Verify Autoselect Code” and “Expanded

Autoselect Code” Tables in “■FLEXIBLE SECTOR-ERASE ARCHITECTURE”.) This mode is functional over

the entire temperature range of the device.

To activate this mode, the programming equipment must force V^ID(11.5 V to 12.5 V) on address pin A9. Two

identifier bytes may then be sequenced from the devices outputs by toggling address A⁰from VIL to VIH. All

addresses are DON’T CARES except A⁰, A1, and A6 (A-1). (See “MBM29LV160TE/BE User Bus Operation

(BYTE = VIH) or (BYTE = VIL)” Tables in “■DEVICE BUS OPERATIONS”) .

The manufacturer and device codes may also be read via the command register, for instances when the

MBM29LV160TE/BE is erased or programmed in a system without access to high voltage on the A⁹pin. The

19

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

command sequence is illustrated in “MBM29LV160TE/BE Standard Command Definitions” Table.

Byte 0 (A⁰= VIL) represents the manufacture’s code and byte 1 (A0 = VIH) represents the device identifier code.

For the MBM29LV160TE/BE these two bytes are given in the Expanded Autoselect Code Table. All identifiers

for manufactures and device will exhibit odd parity with DQ⁷defined as the parity bit. In order to read the proper

device codes when executing the Autoselect, A¹must be VIL. (See “MBM29LV160TE/BE User Bus Operation

(BYTE = VIH) or (BYTE = VIL)” Tables in “■DEVICE BUS OPERATIONS”.) For device identification in word mode

(BYTE = VIH), DQ9 and DQ13 are equal to ‘1’ and DQ8, DQ10 to DQ12, DQ14, and DQ15 are equal to ‘0’.

If BYTE = VIL (for byte mode), the device code is C4h (for top boot block) or 49h (for bottom boot block). If BYTE =

V^IH(for word mode), the device code is 22C4h (for top boot block) or 2249h (for bottom boot block).

In order to determine which sectors are write protected, A¹must be at VIH while running through the sector

addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ⁰(DQ0 =1).

• Write

Device erasure and programming are accomplished via the command register. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The com-

mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

whichever happens first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

• Sector Protection

The MBM29LV160TE/BE features hardware sector protection. This feature will disable both program and erase

operations in any number of sectors (0 through 34). The sector protection feature is enabled using programming

equipment at the user’s site. The device is shipped with all sectors unprotected.

To activate this mode, the programming equipment must force V^IDon address pin A9 and control pin OE, CE =

V^IL, A0 = A6 = VIL, A1 = VIH. The sector addresses pins (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to

the sector to be protected. MBM29LV160TE’s/BE’s “Sector Address Table” define the sector address for each

of the thirty five (35) individual sectors. Programming of the protection circuitry begins on the falling edge of the

WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during

the WE pulse. See “Sector Protection Timing Diagram” in “■TIMING DIAGRAM” and “Sector Protection Algo-

rithm” in “■FLOW CHART” for sector protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V^IDon address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12)

while (A⁶, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. Otherwise the

device will read 00h for an unprotected sector. In this mode, the lower order addresses, except for A⁰, A1, and

A⁶are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device

codes. A^-1requires to VIL in byte mode.

It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing

a read operation at the address location XX02h, where the higher order addresses pins (A¹⁹, A18, A17, A16, A15,

A¹⁴, A13, and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See

“MBM29LV160TE/BE Sector Protection Verify Autoselect Code and Expanded Autoselect Code” Tables for

Autoselect codes.

• Temporary Sector Unprotection

This feature allows temporary unprotection of previously protected sectors of the MBM29LV160TE/BE devices

in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage

(V^ID). During this mode, formerly protected sectors can be programmed or erased by selecting the sector ad-

dresses. Once the V^IDis taken away from the RESET pin, all the previously protected sectors will be protected

again. (See “Temporary Sector Unprotection Timing Diagram” in “■TIMING DIAGRAM” and “Temporary Sector

Unprotection Algorithm” in “■FLOW CHART”.)

20

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

■ COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register.

Writing incorrect address and data values or writing them in an improper sequence will reset the device to the

read mode. “MBM29LV160TE/BE Standard Command Definitions” Table in “■FLEXIBLE SECTOR-ERASE

ARCHITECTURE” defines the valid register command sequences. Note that the Erase Suspend (B0h) and

Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover both

Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that

commands are always written at DQ⁷to DQ0 and DQ15 to DQ8 bits are ignored.

• Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read mode, the read/reset

operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor

read cycles retrieve array data from the memory. The device remains enabled for reads until the command

register contents are altered.

The device willautomatically power-up inthe Read/Resetstate. Inthis case, acommandsequenceis notrequired

to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no

spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read Charac-

teristics and Waveforms for specific timing parameters. (See “Read Operation Timing Diagram” in “■TIMING

DIAGRAM”.)

• Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,

manufactures and device codes must be accessible while the device resides in the target system. PROM

programmers typically access the signature codes by raising A⁹to a high voltage. However, multiplexing high

voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming method-

ology. The operation is initiated by writing the Autoselect command sequence into the command register. Fol-

lowing the last command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read

cycle from address XX01h for ×16 (XX02h for ×8) retrieves the device code (MBM29LV160TE = C4h and

MBM29LV160BE = 49h for ×8 mode; MBM29LV160TE = 22C4h and MBM29LV160BE = 2249h for ×16 mode).

(See “MBM29LV160TE/BE Sector Protection Verify Autoselect Code and Expanded Autoselect Code” Tables

in “■FLEXIBLE SECTOR-ERASE ARCHITECTURE”.)

All manufactures and device codes will exhibit odd parity with DQ⁷defined as the parity bit.

The sector state (protection or unprotection) will be indicated by address XX02h for ×16 (XX04h for ×8).

Scanning the sector addresses (A¹⁹, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce

a logical “1” at device output DQ⁰for a protected sector. The programming verification should be perform margin

mode verification on the protected sector. (See “MBM29LV160TE/BE User Bus Operation (BYTE = VIH) and

(BYTE = VIL)” Tables in “■DEVICE BUS OPERATIONS”.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and,

also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command

sequence.

• Byte/Word Programming

The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.

There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.

Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the

rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens

first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system

is not required to provide further controls or timings. The device will automatically provide adequate internally

generated program pulses and verify the programmed cell margin. (See “Alternate WE Controlled Program

Operation Timing Diagram” and “Alternate CE Controlled Program Operation Timing Diagram” in “■TIMING

DIAGRAM”.)

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Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

The automatic programming operation is completed when the data on DQ⁷is equivalent to data written to this

bit at which time the device return to the read mode and addresses are no longer latched. (See “Hardware

Sequence Flags” Table.) Therefore, the device requires that a valid address be supplied by the system at this

time. Hence, Data Polling must be performed at the memory location which is being programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occurs during the pro-

gramming operation, it is impossible to guarantee whether the data being written is correct or not.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only

erase operations can convert “0”s to “1”s.

“Embedded Program^TMAlgorithm” in “■FLOW CHART” illustrates the Embedded Program^TMAlgorithm using

typical command strings and bus operations.

• Chip Erase

Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the device will automatically program and verify the entire memory for an all zero

data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide any controls

or timings during these operations.

The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates

when the data on DQ⁷is “1” (See Write Operation Status section.) at which time the device returns to read mode.

(See “Chip/Sector Erase Operation Timing Diagram” in “■TIMING DIAGRAM”.)

“Embedded Erase^TMAlgorithm” in “■FLOW CHART” illustrates the Embedded Erase^TMAlgorithm using typical

command strings and bus operations.

• Sector Erase

Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up”

command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address

(any address location within the desired sector) is latched on the falling edge of WE, while the command (Data =

30h) is latched on the rising edge of WE. After a time-out of “tTOW” from the rising edge of the last sector erase

command, the sector erase operation will begin.

Multiple sectors may be erased concurrently by writing six-bus cycle operations on “MBM29LV160TE/BE Stan-

dard Command Definitions” Table in “■FLEXIBLE SECTOR-ERASE ARCHITECTURE”. This sequence is fol-

lowed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased.

The time between writes must be less than “t^TOW” otherwise that command will not be accepted and erasure will

start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The

interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “t^TOW” from the rising

edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE

occurs within the “tTOW” time-out window the timer is reset. Monitor DQ3 to determine if the sector erase timer

window is still open. (See section DQ³, Sector Erase Timer.) Any command other than Sector Erase or Erase

Suspend during this time-out period will reset the device to the read mode, ignoring the previous command

string. Resetting the device once execution has begun will corrupt the data in the sector. In that case, restart

the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector

Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of

sectors (0 to 34).

Sector erase does not require the user to program the device prior to erase. The device automatically programs

all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram Function). When erasing

a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any

controls or timings during these operations.

The automatic sector erase begins after the “t^TOW” time out from the rising edge of the WE pulse for the last

sector erase command pulse and terminates when the data on DQ⁷is “1” (See Write Operation Status section)

at which time the device returns to the read mode. Data polling must be performed at an address within any of

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the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogramming) + Sector Erase

Time] × Number of Sector Erase.

“Embedded Erase^TMAlgorithm” in “■FLOW CHART” illustrates the Embedded Erase^TMAlgorithm using typical

command strings and bus operations.

• Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads

from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase

operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if

written during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command

during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the

erase operation.

Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when

writing the Erase Suspend or Erase Resume commands.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum

of “t^SPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the

RY/BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address

of the erasing sector for reading DQ⁶and DQ7 to determine if the erase operation has been suspended. Further

writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode except that the data must be read from

sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the

device is in the erase-suspend-read mode will cause DQ²to toggle. (See the section on DQ2.)

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com-

mand sequence for Program. This Program mode is known as the erase-suspend-program mode. Again, pro-

gramming in this mode is the same as programming in the regular Program mode except that the data must be

programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector

while the devices are in the erase-suspend-program mode will cause DQ²to toggle. The end of the erase-

suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or the Toggle Bit (DQ6)

which is the same as the regular Program operation. Note that DQ⁷must be read from the Program address

while DQ⁶can be read from any address.

To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of

the Resume command at this point will be ignored. Another Erase Suspend command can be written after the

chip has resumed erasing.

• Extended Command

(1) Fast Mode

MBM29LV160TE/BE has Fast Mode function. This mode dispenses with the initial two unlock cycles required

in the standard program command sequence writing Fast Mode command into the command register. In

this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard

program command. The read operation is also executed after exiting this mode. During the Fast mode, do

not write any command other than the Fast program/Fast mode reset command. To exit this mode, it is

necessary to write Fast Mode Reset command into the command register. (Refer to the “Embedded

Programming Algorithm for Fast Mode” in “■FLOW CHART” Extended algorithm.) The V^CCactive current is

required even CE = VIH during Fast Mode.

(2) Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program

Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to

the “Embedded Programming Algorithm for Fast Mode” in “■FLOW CHART” Extended algorithm.)

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(3) Extended Sector Protection

Inadditiontonormalsectorprotection, theMBM29LV160TE/BEhasExtendedSectorProtectionasextended

function. This function enable to protect sector by forcing V^IDon RESET pin and write a commnad sequence.

Unlike conventional procedure, it is not necessary to force V^IDand control timing for control pins. The only

RESETpin requires VID forsectorprotectioninthis mode. The extended sector protectrequiresVID onRESET

pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command

register. Then, the sector addresses pins (A¹⁹, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0)

should be set to the sector to be protected (recommend to set V^ILfor the other addresses pins), and write

extended sector protect command (60h). A sector is typically protected in 250 μs. To verify programming of

the protection circuitry, the sector addresses pins (A¹⁹, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) =

(0, 1, 0) should be set and write a command (40h). Following the command write, a logical “1” at device

output DQ⁰will produce for protected sector in the read operation. If the output data is logical “0”, please

repeat to write extended sector protect command (60h) again. To terminate the operation, it is necessary to

set RESET pin to VIH.

(4) CFI (Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and host system software

interrogation handshake which allows specific vendor-specified software algorithms to be used for entire

families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-

compatible software support for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98h) into the command register. Following the

command write, a read cycle from specific address retrives device information. Please note that output data

of upper byte (DQ¹⁵to DQ8) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate

operation, it is necessary to write the read/reset command sequence into the register.

• Write Operation Status

Hardware Sequence Flags

Status

DQ⁷

0

DQ6

DQ5

0

DQ3

0

DQ2

1

Embedded Program Algorithm

Embedded/Erase Algorithm

Toggle

0

1

Toggle

Erase Suspend Read

(Erase Suspended Sector)

1

0

Data

0

Data

0

Toggle

Data

1 *²

In

Erase

Progress

Erase Suspend Read

Suspend

Data

DQ⁷

Data

(Non-Erase Suspended Sector)

Mode

Erase Suspend Program

(Non-Erase Suspended Sector)

Toggle *¹

Embedded Program Algorithm

Embedded/Erase Algorithm

DQ⁷

0

Toggle

1

0

1

Exceeded

Time

N/A

Limits

Erase Suspend Program

(Non-Erase Suspended Sector)

DQ⁷

Toggle

1

0

N/A

*1 : Performing successive read operations from any address will cause DQ⁶to toggle.

*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”

at the DQ²bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.

Notes: • DQ⁰and DQ1 are reserve pins for future use.

• DQ⁴is Fujitsu internal use only.

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• DQ7

Data Polling

The MBM29LV160TE/BE device features Data Polling as a method to indicate to the host that the Embedded

Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the

devices will produce the complement of the data last written to DQ⁷. Upon completion of the Embedded Program

Algorithm, an attempt to read the device will produce the true data last written to DQ⁷. During the Embedded

Erase Algorithm, an attempt to read the device will produce a “0” at the DQ⁷output. Upon completion of the

Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ⁷output. The flowchart

for Data Polling (DQ7) is shown in “Data Polling Algorithm” in “■FLOW CHART”.

For chip erase and sector erase, Data Polling is valid after the rising edge of the sixth WE pulse in the six-write

pulse sequence. Data Polling must be performed at a sector address within any of the sectors being erased and

not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is

close to being completed, the MBM29LV160TE/BE data pins (DQ⁷) may change asynchronously while the output

enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of

time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ⁷

output, it may read the status or valid data. Even if the device has completed the Embedded Program Algorithm

operation and DQ⁷has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7

to DQ0 will be read on successive read attempts.

TheData PollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm, EmbeddedEraseAlgorithm

or sector erase time-out.

See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “■TIMING DIAGRAM” for the Data

Polling timing specifications and diagram.

• DQ6

Toggle Bit I

The MBM29LV160TE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the

Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from

the device will result in DQ⁶toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ⁶will stop toggling and valid data can be read on the next successive attempts. During

programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.

For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six-

write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 μs and then stop

toggling without the data having changed. In erase, the device will erase all the selected sectors except for the

ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about

200 μs and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will

cause the DQ⁶to toggle.

See “Toggle Bit I during Embedded Algorithm Operation Timing Diagram” in “■TIMING DIAGRAM” and “Toggle

Bit Algorithm” in “■FLOW CHART” for the Toggle Bit I timing specifications and diagram.

• DQ5

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ⁵will produce a “1”. This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling is the only operating function of the device under this

condition. The CE circuit will partially power down the device under these conditions. The OE and WE pins will

control the output disable functions as described in “MBM29LV160TE/BE User Bus Operation (BYTE = VIH) and

(BYTE = VIL)” Tables in “■DEVICE BUS OPERATIONS”.

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The DQ⁵failure condition may also appear if a user tries to program a non blank location without erasing. In this

case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never

reads a valid data on DQ⁷and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5

bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.

If this occurs, reset the device with command sequence.

• DQ3

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will

remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase

command sequence.

If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may

be used to determine if the sector erase timer window is still open. If DQ³is high (“1”) the internally controlled

erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept

additional sector erase commands. To insure the command has been accepted, the system software should

check the status of DQ³prior to and following each subsequent sector erase command. If DQ3 is high on the

second status check, the command may not have been accepted.

See “Hardware Sequence Flags” Table.

• DQ2

Toggle Bit II

This Toggle Bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ²to toggle during the Embedded Erase Algorithm. If the

device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ²to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic “1” at DQ².

DQ⁶is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress.

For example, DQ²and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

(DQ²toggles while DQ6 does not.) See also “Toggle Bit Status” Table and “DQ2 vs. DQ6” in “■TIMING

DIAGRAM”.

Furthermore, DQ²can also be used to determine which sector is being erased. When the device is in the erase

mode, DQ²toggles if this bit is read from an erasing sector.

Toggle Bit Status

Mode

DQ⁷

DQ7

0

DQ6

DQ2

1

Program

Erase

Toggle

Erase Suspend Read

1

Toggle

1 *²

(Erase Suspended Sector) *¹

Erase-Suspend Program

DQ⁷

Toggle *¹

*1 : Performing successive read operations from any address will cause DQ⁶to toggle.

*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”

at the DQ²bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.

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• RY/BY

Ready/Busy Pin

The MBM29LV160TE/BE provides a RY/BY open-drain output pin as a way to indicate to the host system that

the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy

with either a program or erase operation. If the output is high, the device is ready to accept any read/write or

erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase com-

mands with the exception of the Erase Suspend command. If the MBM29LV160TE/BE is placed in an Erase

Suspend mode, the RY/BY output will be high, by means of connecting with a pull-up resister to VCC.

During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a

busy condition during the RESET pulse. See “RY/BY Timing Diagram during Program/Erase Operation Timing

Diagram” and “RESET, RY/BY Timing Diagram” in “■TIMING DIAGRAM” for a detailed timing diagram. The

RY/BY pin is pulled high in standby mode.

Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.

• RESET

Hardware Reset Pin

The MBM29LV160TE/BE device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse

requirement and has to be kept low (V^IL) for at least “tRP” in order to properly reset the internal state machine.

Any operation in the process of being executed will be terminated and the internal state machine will be reset

to the read mode “t^READY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the

device requires an additional “t^RH” before it allows read access. When the RESET pin is low, the device will be

in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware

reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please

note that the RY/BY output signal should be ignored during the RESET pulse. Refer to “RESET, RY/BY Timing

Diagram” in “■TIMING DIAGRAM” for the timing diagram. Refer to Temporary Sector Unprotection for additional

functionality.

If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) will

need to be erased again before they can be programmed.

• Byte/Word Configuration

The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV160TE/BE device. When

this pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ¹⁵

to DQ0. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ15/A-1 pin

becomes the lowest address bit and DQ¹⁴to DQ8 bits are tri-stated. However, the command bus cycle is always

an 8-bit operation and hence commands are written at DQ⁷to DQ0 and DQ15 to DQ8 bits are ignored. Refer to

“Timing Diagram for Word Mode Configuration”, “Timing Diagram for Byte Mode Configuration” and “BYTE

Timing Diagram for Write Operations” in “■TIMING DIAGRAM” for the timing diagram.

• Data Protection

The MBM29LV160TE/BE is designed to offer protection against accidental erasure or programming caused by

spurious system level signals that may exist during power transitions. During power up the device automatically

resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the

memory contents only occurs after successful completion of specific multi-bus cycle command sequence.

The device also incorporates several features to prevent inadvertent write cycles resulting form V^CCpower-up

and power-down transitions or system noise.

• Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less

than V^LKO(Min). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are

disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until

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the V^CClevel is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct

to prevent unintentional writes when V^CCis above VLKO (Min).

If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be

erased again prior to programming.

• Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not change the command registers.

• Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must

be a logical zero while OE is a logical one.

• Power-up Write Inhibit

Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to read mode on power-up.

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■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Storage Temperature

Symbol

Unit

Min

–55

–40

Max

+125

+85

Tstg

T^A

°C

Ambient Temperature with Power Applied

Voltage with Respect to Ground All pins except

A⁹, OE, RESET *¹

VIN, VOUT

–0.5

VCC + 0.5

V

Power Supply Voltage *¹

A⁹, OE, and RESET *²

VCC

VIN

–0.5

+5.5

V

+13.0

*1: Minimum DC voltage on input or l/O pins is –0.5 V. During voltage transitions, inputs or I/O pins may undershoot

V^SSto –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC +0.5 V. During voltage

transitions, inputs or I/O pins may overshoot to V^CC+2.0 V for periods of up to 20 ns.

*2: Minimum DC input voltage on A⁹, OE, and RESET pins is –0.5 V. During voltage transitions, A9, OE, and RESET

pins may undershoot V^SSto –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage

(V^IN– VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE, and RESET pins is +13.0 V which

may overshoot to 14.0 V for periods of up to 20 ns.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Unit

Min

–40

+2.7

Typ

⎯

Max

+85

Ambient Temperature

Power Supply Voltage

T^A

°C

V

V^CC

⎯

+3.6

Note: Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

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■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT

20 ns

+0.6 V

-0.5 V

-2.0 V

20 ns

Maximum Undershoot Waveform

20 ns

V^CC+ 2.0 V

VCC + 0.5 V

+2.0 V

20 ns

Maximum Overshoot Waveform 1

20 ns

+14.0 V

+13.0 V

V^CC+ 0.5 V

20 ns

Note : This waveform is applied for A⁹, OE, and RESET.

Maximum Overshoot Waveform 2

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■ DC CHARACTERISTICS

Value

Parameter

Symbol

Test Conditions

Unit

Min

–1.0

Max

+1.0

Input Leakage Current

Output Leakage Current

I^LI

VIN = VSS to VCC, VCC = VCC Max

VOUT = VSS to VCC, VCC = VCC Max

µA

I^LO

A⁹, OE, RESET Inputs Leakage

Current

VCC = VCC Max,

A⁹, OE, RESET = 12.5 V

I^LIT

—

35

µA

Byte

30

35

15

17

35

CE = VIL, OE = VIH,

f = 10 MHz

Word

mA

V^CCActive Current *¹

ICC1

Byte

CE = VIL, OE = VIH,

f = 5 MHz

Word

—

mA

V^CCActive Current *²

V^CCCurrent (Standby)

ICC2

ICC3

CE = VIL, OE = VIH

—

mA

µA

VCC = VCC Max, CE = VCC ±0.3 V,

RESET = VCC ±0.3 V

5

VCC = VCC Max,

RESET = VSS ±0.3 V

V^CCCurrent (Standby, RESET)

ICC4

ICC5

—

µA

VCC = VCC Max, CE = VSS ±0.3 V,

RESET = VCC ±0.3 V,

V^IN= VCC ±0.3 V or VSS ±0.3 V

V^CCCurrent

5

(Automatic Sleep Mode) *³

Input Low Level

Input High Level

V^IL

V^IH

—

–0.5

2.0

0.6

V

VCC + 0.3

Voltage for Autoselect, Sector

Protection, and Temporary

Sector Unprotection

VID

—

11.5

12.5

V

(A⁹, OE, RESET) *⁴

Output Low Voltage Level

Output High Voltage Level

Low V^CCLock-Out Voltage

V^OL

V^OH1

V^OH2

VLKO

IOL = 4.0 mA, VCC = VCC Min

IOH = –2.0 mA, VCC = VCC Min

IOH = –100 µA

—

2.4

0.45

—

V

VCC – 0.4

2.3

—

2.5

*1: lCC current listed includes both the DC operating current and the frequency dependent component.

*2: l^CCactive while Embedded Erase or Embedded Program is in progress.

*3: Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

*4: (V^ID– VCC) do not exceed 9 V.

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■ AC CHARACTERISTICS

• Read Only Operations Characteristics

Value (Note)

Symbol

Test

Parameter

70

90

Unit

Setup

JEDEC Standard

Min

Max

Min

Max

Read Cycle Time

t^AVAV

t^AVQV

tRC

—

70

—

90

—

ns

CE = VIL

OE = VIL

Address to Output Delay

tACC

—

70

—

90

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

tCE

tOE

tDF

OE = VIL

—

70

30

25

—

90

35

30

ns

—

Output Hold Time From Address, CE or

OE, Whichever Occurs First

t^AXQX

—

tOH

—

0

—

20

5

0

—

20

5

ns

μs

ns

RESET Pin Low to Read Mode

tREADY

—

t^ELFL

tELFH

CE to BYTE Switching Low or High

—

Note: Test Conditions:

Output Load:1 TTL gate and 30 pF (MBM29LV160TE/BE70)

1 TTL gate and 100 pF (MBM29LV160TE/BE90)

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V or 3.0 V

Timing measurement reference level

Input: 0.5 Vccf

Output: 0.5 Vccf

3.3 V

Diode = 1N3064

or Equivalent

2.7 kΩ

Device

Under

Test

6.2 kΩ

C^L

Diode = 1N3064

or Equivalent

Notes : C^L= 30 pF including jig capacitance (MBM29LV160TE/BE70)

C^L= 100 pF including jig capacitance (MBM29LV160TE/BE90)

Test Conditions

32

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

• Write (Erase/Program) Operations

Parameter

Value

Symbol

Standard

70

90

Unit

JEDEC

t^AVAV

t^AVWL

t^WLAX

t^DVWH

t^WHDX

—

Min Typ Max Min Typ Max

Write Cycle Time

tWC

tAS

70

0

—

90

0

—

ns

Address Setup Time

Address Hold Time

Data Setup Time

tAH

45

35

0

45

0

tDS

Data Hold Time

tDH

t^OES

Output Enable Setup Time

0

Read

0

Output Enable

—

t^OEH

Hold Time

Toggle and Data Polling

10

0

10

0

Read Recover Time Before Write

t^GHWL

t^GHEL

tGHWL

tGHEL

Read Recover Time Before Write

(OE High to CE Low)

0

—

0

—

ns

CE Setup Time

tELWL

tWLEL

tWHEH

tEHWH

t^WLWH

tELEH

t^WHWL

tEHEL

tCS

tWS

tCH

0

—

8

—

90

70

30

0

—

8

—

90

35

ns

WE Setup Time

CE Hold Time

0

WE Hold Time

tWH

tWP

tCP

0

Write Pulse Width

CE Pulse Width

Write Pulse Width High

CE Pulse Width High

35

25

—

50

500

4

45

25

—

50

500

4

tWPH

tCPH

Byte

Programming Operation

t^WHWH1

tWHWH1

µs

Word

16

1

16

1

Sector Erase Operation *¹

V^CCSetup Time

tWHWH2

—

tWHWH2

tVCS

tVIDR

tVLHT

tWPP

tOESP

tCSP

tRB

s

—

µs

ns

µs

ns

Rise Time to V^ID*²

—

Voltage Transition Time *²

Write Pulse Width *²

—

100

4

100

4

OE Setup Time to WE Active *²

CE Setup Time to WE Active *²

Recover Time From RY/BY

RESET Pulse Width

—

4

—

0

—

tRP

500

200

—

500

200

—

RESET High Level Period Before Read

Program/Erase Valid to RY/BY Delay

—

tRH

—

tBUSY

t^EOE

tFLQZ

Delay Time from Embedded Output Enable

BYTE Switching Low to Output High-Z

—

(Continued)

33

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

(Continued)

Value

Symbol

Parameter

70

90

Unit

Standard

JEDEC

—

Min Typ Max Min Typ Max

BYTE Switching High to Output Active

Erase Time-out Time

tFHQV

t^TOW

t^SPD

—

50

—

70

—

20

—

50

—

90

—

20

ns

µs

—

Erase Suspend Transition Time

—

*1: Does not include the preprogramming time.

*2: For Sector Protection operation.

34

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

■ ERASE AND PROGRAMMING PERFORMANCE

Limits

Typ

Parameter

Unit

s

Comments

Min

Max

Excludes programming time

prior to erasure

Sector Erase Time

—

1

10

Byte Programming Time

Word Programming Time

—

8

300

360

Excludes system-level

overhead

µs

16

Excludes system-level

overhead

Chip Programming Time

Erase/Program Cycle

—

16.8

—

50

—

s

100,000

cycle

—

■ PIN CAPACITANCE

Parameter

Input Capacitance

Symbol

Test Setup

Typ

Max

7.5

10

Unit

pF

C^IN

VIN = 0

VOUT = 0

VIN = 0

6

8

Output Capacitance

Control Pin Capacitance

C^OUT

C^IN2

pF

7.5

9

pF

Notes : • Test conditions TA = +25°C, f = 1.0 MHz

• DQ¹⁵/A-1 pin capacitance is stipulated by output capacitance.

35

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

■ TIMING DIAGRAM

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Will Be

Steady

Must Be

Steady

Will

Change

from H to L

May

Change

from H to L

May

Change

from L to H

Will

Change

from L to H

H or L ;

Any Change

Permitted

Changing,

State

Unknown

Center Line Is

High-

Impedance

Off State

Does Not

Apply

t^RC

Address

Address Stable

tACC

CE

OE

tOE

tDF

tOEH

WE

tOH

tCE

High-Z

Outputs Valid

Outputs

Read Operation Timing Diagram

36

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

t^RC

Address

Address Stable

tACC

CE

tRH

tRP

tRH

tCE

RESET

Outputs

tOH

High-Z

Outputs Valid

Hardware Reset/Read Operation Timing Diagram

37

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

3rd Bus Cycle

Data Polling

PA

555h

tWC

PA

Address

CE

tRC

tAS

tAH

tCS

tCH

tCE

OE

tWPH

tOE

tWP

tWHWH1

tGHWL

WE

tDH

tDF

tDS

tOH

A0h

PD

DOUT

DQ7

Data

Notes: • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ⁷is the output of the complement of the data written to the device.

• D^OUTis the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Alternate WE Controlled Program Operation Timing Diagram

38

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

3rd Bus Cycle

Data Polling

PA

555h

tWC

Address

WE

tAH

tAS

tWS

tWH

OE

CE

tCP

tCPH

tWHWH1

tGHEL

tDS

tDH

A0h

PD

DQ7

DOUT

Data

Notes: • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ⁷is the output of the complement of the data written to the device.

• D^OUTis the output of the data written to the device.

• Figure indicates the last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode (the addresses differ from ×8 mode).

Alternate CE Controlled Program Operation Timing Diagram

39

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

2AAh

555h

2AAh

Address

CE

555h

tWC

SA*

tAS

tAH

tCH

tCS

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

10h for Chip Erase

10h/

30h

AAh

55h

80h

AAh

55h

Data

tVCS

VCC

* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.

Note : These waveforms are for the ×16 mode. The addresses differ from ×8 mode.

Chip/Sector Erase Operation Timing Diagram

40

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

CE

tCH

tDF

tOE

OE

tOEH

WE

tCE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

tWHWH1 or 2

DQ⁶to DQ0 =

Output Flag

DQ⁶to DQ0

Valid Data

DQ6 to DQ0

RY/BY

tEOE

tBUSY

* : DQ7 = Valid Data (The device has completed the Embedded operation).

Data Polling during Embedded Algorithm Operation Timing Diagram

41

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

Address

tAHT tASO

tAHT tAS

CE

tCEPH

WE

tOEPH

tOEH

OE

tOE

tCE

tDH

*

Stop

Output

Valid

Toggle

Data

Toggle

Data

Toggle

Data

DQ 6/DQ2

Data

Toggling

tBUSY

RY/BY

*: DQ6 = Stops toggling. (The device has completed the Embedded operation.)

Toggle Bit I during Embedded Algorithm Operation Timing Diagram

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Rasume

WE

Erase

Erase Suspend

Read

Erase

Erase Suspend

Read

Erase

Complate

Suspend

Program

DQ6

DQ2

Toggle

DQ²and DQ6

With OE or CE

Note: DQ2 is read from the erase-suspended sector.

DQ2 vs. DQ6

42

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

CE

Rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

tBUSY

RY/BY Timing Diagram during Program/Erase Operation Timing Diagram

WE

RESET

tRB

tRP

RY/BY

tREADY

RESET, RY/BY Timing Diagram

43

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

CE

tCE

BYTE

Data Output

(DQ¹⁴to DQ0)

Data Output

(DQ⁷to DQ0)

tELFH

DQ14 to DQ0

DQ15/A -1

tFHQV

A -1

DQ15

Timing Diagram for Word Mode Configuration

CE

BYTE

tELFL

Data Output

(DQ14 to DQ0)

Data Output

(DQ⁷to DQ0)

DQ14 to DQ0

tACC

A -1

DQ15

tFLQZ

DQ15/A -1

Timing Diagram for Byte Mode Configuration

Falling edge of the last write signal

CE or WE

BYTE

Input

Valid

t^SET

(tAS)

tHOLD (tAH)

BYTE Timing Diagram for Write Operations

44

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

A19, A18, A17,

A16, A15, A14,

A13, A12

SPAX

SPAY

A6, A0

A1

VID

3 V

A9

tVLHT

VID

3 V

OE

tVLHT

tOESP

tVLHT

tWPP

WE

CE

tCSP

01h

Data

VCC

tOE

tVCS

SPAX : Sector Address to be protected.

SPAY : Next Sector Address to be protected.

Note: A^-1is VIL on byte mode.

Sector Protection Timing Diagram

45

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

V^CC

tVIDR

tVCS

tVLHT

VID

3 V

RESET

CE

WE

tVLHT

Program or Erase Command Sequence

Unprotection Period

RY/BY

Temporary Sector Unprotection Timing Diagram

46

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

VCC

tVCS

tVLHT

RESET

Add

tVIDR

tWC

SPAX

SPAY

A0

A¹

A6

CE

OE

TIME-OUT

tWP

WE

Data

60h

40h

01h

60h

tOE

SPAX : Sector Address to be protected

SPAY : Next Sector Address to be protected

TIME-OUT : Time-Out window = 250 μs (Min)

Extended Sector Protection Timing Diagram

47

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

■ FLOW CHART

EMBEDDED ALGORITHM

Start

Write Program

Command Sequence

(See Below)

Data Polling

Embedded

Program

Algorithm

in progress

No

Verify Data

?

Yes

No

Last Address

?

Increment Address

Yes

Programming Completed

Program Command Sequence (Address/Command) :

555h/AAh

2AAh/55h

555h/A0h

Program Address/Program Data

Note : The sequence is applied for ×16 mode.

The addresses differ from ×8 mode.

Embedded Program^TMAlgorithm

48

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

EMBEDDED ALGORITHM

Start

Write Erase

Command Sequence

(See Below)

Data Polling

Embedded

Erase

Algorithm

in Progress

No

Data = FFh

?

Yes

Erasure Completed

Chip Erase Command Sequence

(Address/Command) :

Individual Sector/Multlple Sector

Erase Command Sequence

(Address/Command) :

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

Sector Address

/30h

Sector Address

/30h

Additional sector

erase commands

are optional.

Sector Address

/30h

Note : The sequence is applied for ×16 mode.

The addresses differ from ×8 mode.

Embedded Erase^TMAlgorithm

49

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

VA =Address for programming

=Any of the sector addresses

within the sector being erased

during sector erase or multiple

erases operation.

=Any of the sector addresses

within the sector not being

protected during sector erase or

multiple sector erases

Start

Read Byte

(DQ7 to DQ0)

Addr. = VA

Yes

DQ7 = Data ?

No

operation.

No

DQ5 = 1 ?

Yes

Read Byte

(DQ7 to DQ0)

Addr. = VA

Yes

DQ7 = Data ?

*

No

Fail

Pass

* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Data Polling Algorithm

50

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

Start

*1

7 0)

to DQ

Read (DQ

Addr. = “H” or “L”

*1

Read (DQ7 to DQ0)

Addr. = “H” or “L”

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1 ?

Yes

*1, *2

Read

(DQ⁷to DQ0)

Addr. = “H” or “L”

Read

(DQ⁷to DQ0)

Addr. = “H” or “L”

No

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not

Complete. Write

Reset Command

Program/Erase

Operation

Complete

*1 : Read toggle bit twice to determine whether it is toggling.

*2 : Recheck toggle bit because it may stop toggling as DQ⁵changes to “1”.

Toggle Bit Algorithm

51

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

Start

Setup Sector Addr.

A19, A18, A17, A16,

A¹⁵, A14, A13, A12

(

)

PLSCNT = 1

OE = VID, A9 = VID

CE = VIL, RESET = VIH

A6 = A0 = VIL, A1 = VIH

Increment PLSCNT

Activate WE Pulse

Time out 100 µs

WE = VIH, CE = OE = VIL

(A9 should remain VID)

Read from Sector Address

Addr. = SPA, A¹= VIH

A6 = A0 = VIL

*

(

)

No

PLSCNT = 25 ?

Yes

No

Data = 01h ?

Yes

Pemove VID from A9

Write Reset Command

Protect Another Sector

?

No

Remove VID from A9

Write Reset Command

Device Failed

Sector Protection

Completed

* : A-1 is VIL on byte mode.

Sector Protection Algorithm

52

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

Start

RESET = VID

*1

Perform Erase or

Program Operations

RESET = V^IH

Temporary Sector

Unprotection Completed

*2

*1 : All protected sectors are unprotected.

*2 : All previously protected sectors are protected once again.

Temporary Sector Unprotection Algorithm

53

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

FAST MODE ALGORITHM

Start

555h/AAh

2AAh/55h

555h/20h

Set Fast Mode

XXXh/A0h

Program Address/Program Data

Data Polling

No

In Fast Program

Verify Data ?

Yes

No

Last Address

Increment Address

?

Yes

Programming Completed

XXXh/90h

Reset Fast Mode

XXXh/F0h

Note : The sequence is applied for ×16 mode.

The addresses differ from ×8 mode.

Embedded Programming Algorithm for Fast Mode

54

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

Start

RESET = VID

Wait to 4 µs

Device Is Operating in

Temporary Sector

Unprotection Mode

No

Extended Sector

Protect Entry ?

Yes

To Setup Sector Protection

Write XXXh/60h

PLSCNT = 1

To Protect Sector

Write 60h to Sector Address

(A⁶= A0 = VIL, A1 = VIH)

Time Out 250 µs

To Verify Sector Protection

Write 40h to Sector Address

(A⁶= A0 = VIL, A1 = VIH)

Increment PLSCNT

Read from Sector Address

(Addr. = SPA, A⁰= VIL,

A1 = VIH, A6 = VIL)

No

Setup Next Sector Address

No

PLSCNT = 25 ?

Yes

Data = 01h ?

Yes

Protect Other Sector

?

Remove VID from RESET

Write Reset Command

No

Remove VID from RESET

Write Reset Command

Device Failed

Sector Protection

Completed

Extended Sector Protection Algorithm

55

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

■ ORDERING INFORMATION

Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of:

MBM29LV160

T

E

70

TN

PACKAGE TYPE

TN = 48-Pin Thin Small Outline Package

(TSOP (1) ) Normal Bend

TR = 48-Pin Thin Small Outline Package

(TSOP (1) ) Reverse Bend

PCV = 48-Pin C- leaded Small Outline

Package (CSOP)

PBT = 48-ball Fine Pitch Ball Grid Array

Package (FBGA)

SPEED OPTION

See Product Selector Guide

DEVICE REVISION

BOOT CODE SECTOR ARCHITECTURE

T = Top sector

B = Bottom sector

DEVICE NUMBER/DESCRIPTION

MBM29LV160

16 Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Flash Memory

3.0 V-only Read, Write, and Erase

Valid Combinations

Valid Combinations list configurations planned to

be supported in volume for this device. Consult

the local Fujitsu sales office to confirm availability

of specific valid combinations and to check on

newly released combinations.

TN

TR

PCV

PBT

70

90

MBM29LV160TE/BE

56

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

■ PACKAGE DIMENSIONS

Note 1) * : Values do not include resin protrusion.

48-pin plastic TSOP (1)

(FPT-48P-M19)

Resin protrusion and gate protrusion are +0.15 (.006) MAX (each side) .

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

LEAD No.

1

48

INDEX

Details of "A" part

0.25(.010)

0~8

˚

0.60 0.15

(.024 .006)

24

25

*

20.00 0.20

(.787 .008)

12.00 0.20

(.472 .008)

*

18.40 0.20

(.724 .008)

1.10 ^+0.10

–

0.05

.043 ^+.004

–.002

(Mounting

height)

0.10 0.05

(.004 .002)

(Stand off height)

0.50(.020)

"A"

0.10(.004)

0.17 ^+0.03

.007 ^+.001

–

0.08

0.22 0.05

(.009 .002)

M

0.10(.004)

–

.003

C

2003 FUJITSU LIMITED F48029S-c-6-7

Dimensions in mm (inches) .

Note : The values in parentheses are reference values.

(Continued)

57

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

Note 1) * : Values do not include resin protrusion.

48-pin plastic TSOP (1)

(FPT-48P-M20)

Resin protrusion and gate protrusion are +0.15 (.006) MAX (each side) .

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

LEAD No.

1

48

Details of "A" part

INDEX

0.60 0.15

(.024 .006)

0~8˚

0.25(.010)

24

25

+0.03

0.17 –0.08

0.22 0.05

(.009 .002)

M

0.10(.004)

+.001

.007 –.003

0.10 0.05

(.004 .002)

0.50(.020)

0.10(.004)

(Stand off height)

1.10 –⁺0⁰.^.0¹5⁰

"A"

* 18.40 0.20

(.724 .008)

.043 –⁺.^.0⁰0⁰2⁴

(Mounting height)

20.00 0.20

(.787 .008)

* 12.00 0.20(.472 .008)

C

2003 FUJITSU LIMITED F48030S-c-6-7

Dimensions in mm (inches) .

Note : The values in parentheses are reference values.

(Continued)

58

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

Note 1) *1 : Resin protrusion (Each side : +0.15 (.006) Max) .

Note 2) *2 : These dimensions do not include resin protrusion.

Note 3) Pins width includes plating thickness.

48-pin plastic CSOP

(LCC-48P-M03)

Note 4) Pins width do not include tie bar cutting remainder.

"A"

48

25

10.00 0.20

(.394 .008)

²9.50 0.10

*

(.374 .004)

INDEX

0.05 –⁺0^0.05

INDEX

.002 –⁺.^.0⁰⁰²

(Stand off)

1

24

LEAD No.

0.22 0.035

(.009 .001)

0.95 0.05(.037 .002)

(Mounting height)

¹10.00 0.10(.394 .004)

*

Details of "A" part

0˚~10˚

0.65(.026)

1.15(.045)

0.40(.016)

0.08(.003)

9.20(.362)REF

C

2003 FUJITSU LIMITED C48056S-c-2-2

Dimensions in mm (inches) .

Note : The values in parentheses are reference values.

(Continued)

59

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

(Continued)

48-ball plastic FBGA

(BGA-48P-M11)

8.00±0.20(.315±.008)

1.05 ⁺–0⁰.^.1¹0⁵.041 –⁺.^.0⁰0⁰4⁶

(Mounting height)

(5.60(.220))

0.80(.031)TYP

0.38±0.10(.015±.004)

(Stand off)

6

5

4

3

2

1

INDEX

6.00±0.20

(.236±.008)

(4.00(.157))

H

G

F

E

D

C

B

A

C0.25(.010)

48-ø0.45±0.10

M

ø0.08(.003)

(48-ø.018±.004)

0.10(.004)

C

2001 FUJITSU LIMITED B48011S-c-5-3

Dimensions in mm (inches) .

Note : The values in parentheses are reference values.

60

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

MEMO

61

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

MEMO

62

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

Revision History

Revision DS05-20883-7E（July 31, 2007）

The following comment is added.

This product has been retired and is not recommended for new designs. Availability of this

document is retained for reference and historical purposes only.

63

Retired ProductꢀDS05-20883-7E_July 31, 2007

MBM29LV160TE70/90/MBM29LV160BE70/90

FUJITSU LIMITED

For further information please contact:

Japan

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

FUJITSU LIMITED

Marketing Division

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Electronic Devices

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3353

Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94088-3470, U.S.A.

Tel: +1-408-737-5600

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fme.fujitsu.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Singapore 556741

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Tel: +65-6281-0770

Fax: +65-6281-0220

http://www.fmal.fujitsu.com/

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

F0404

Retired ProductꢀDS05-20883-7E_July 31, 2007


型号：	MBM29LV160TE-90TN
厂家：	SPANSION
描述：	Flash, 1MX16, 90ns, PDSO48, PLASTIC, TSOP1-48 光电二极管内存集成电路
文件：	总64页 (文件大小：478K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MBM29LV160TE-90TN [SPANSION]

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