MBM29LV160TM90_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20906-3E

FLASH MEMORY

CMOS

16 M (2M × 8/1M × 16) BIT

MirrorFlash^TM*

MBM29LV160TM/BM ⁹⁰

■ DESCRIPTION

The MBM29LV160TM/BM is a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes by 8 bits or 2M words

by 16 bits. The MBM29LV160TM/BM is offered in 48-pin TSOP(1) and 48-ball FBGA. The device is designed to

be programmed in-system with the standard 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for

program or erase operations. The devices can also be reprogrammed in standard EPROM programmers.

The standard MBM29LV160TM/BM offers access times of 90 ns, allowing operation of high-speed microproces-

sors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable

(WE), and output enable (OE) controls.

(Continued)

■ PRODUCT LINE UP

MBM29LV160TM/BM

Part No.

90

V^CC

3.0 V to 3.6 V

90 ns

Max Address Access Time

Max CE Access Time

Max OE Access Time

90 ns

25 ns

■ PACKAGES

48-pin plastic TSOP (1)

48-ball plastic FBGA

Marking Side

(FPT-48P-M19)

(BGA-48P-M20)

* : MirrorFlash^TMis a trademark of Fujitsu Limited.

Notes : • Programming in byte mode ( × 8) is prohibited.

• Programming to the address that already contains data is prohibited (It is mandatory to erase data prior to

overprogram on the same address) .

MBM29LV160TM/BM90

(Continued)

The MBM29LV160TM/BM supports command set compatible with JEDEC single-power-supply EEPROMS stan-

dard. Commands are written into the command register. The register contents serve as input to an internal state-

machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and

data needed for the programming and erase operations. Reading data out of the devices is similar to reading

from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV160TM/BM is programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm^TMwhich is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margin. Erase is accomplished by executing the erase command sequence. This will

invoke the Embedded Erase Algorithm^TMwhich is an internal algorithm that automatically preprograms the array

if it is not already programmed before executing the erase operation. During erase, the device automatically

times the erase pulse widths and verifies proper cell margin.

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. All sectors are erased when shipped from the factory.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V^CCdetector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,

by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the devices

internally return to the read mode.

Fujitsu Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The devices electrically erase all bits within a sector simulta-

neously via hot-hole assisted erase. The bytes/words are programmed one bytes/words at a time using the

EPROM programming mechanism of hot electron injection.

2

MBM29LV160TM/BM90

■ FEATURES

• 0.23 µm Process Technology

• Single 3.0 V read, program and erase

Minimizes system level power requirements

• Industry-standard pinouts

48-pin TSOP (1) (Package suffix: TN - Normal Bend Type)

48-ball FBGA (Package suffix: PBT)

• Minimum 100,000 program/erase cycles

• High performance

90 ns maximum access time

• Sector erase architecture

One 16K bytes, two 8K bytes, one 32K bytes, and thirty-one 64K bytes sectors in byte mode

One 8K words, two 4K words, one 16K words, and thirty-one 32K words sectors in word mode

Any combination of sectors can be concurrently erased. Also supports full chip erase

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• Embedded Erase^TM* Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TM* Algorithms

Automatically program and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switches themselves to low power mode

• Program Suspend/Resume

Suspends the program operation to allow a read in another address

• Low V^CCwrite inhibit ≤ 2.5 V

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector Protection

Hardware method disables any combination of sectors from program or erase operations

• Sector Protection Set function by Extended sector protect command

• Fast Programming Function by Extended Command

• Temporary sector unprotection

Temporary sector unprotection via the RESET pin

This feature allows code changes in previously locked sectors

• In accordance with CFI (Common Flash Memory Interface)

* : Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

3

MBM29LV160TM/BM90

■ PIN ASSIGNMENTS

48-pin TSOP(1)

(Top View)

A15

A14

A13

A12

A11

A10

A9

A8

A19

A16

BYTE

VSS

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

(Marking Side)

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE

9

N.C.

WE

RESET

N.C.

RY/BY

A¹⁸

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A17

A7

A6

A5

A4

A3

A2

A1

VSS

CE

A⁰

FPT-48P-M19

48-pin FBGA

(Top View)

Marking Side

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16 BYTE DQ15/ VSS

A-1

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7 DQ14 DQ13 DQ6

A4

B4

C4

D4

E4

F4

G4

H4

WE RESET N.C. A19 DQ5 DQ12 VCC DQ4

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY N.C. A18 N.C. DQ2 DQ10 DQ11 DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0 DQ8 DQ9 DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

OE

H1

CE

VSS

BGA-48P-M20

4

MBM29LV160TM/BM90

■ PIN DESCRIPTIONS

MBM29LV160TM/BM Pin Configuration

Function

A¹⁹to A0, A-1

DQ¹⁵to DQ0

CE

Address Inputs

Data Inputs/Outputs

Chip Enable

OE

Output Enable

Write Enable

WE

RESET

BYTE

RY/BY

VCC

Hardware Reset Pin/Temporary Sector Unprotection

Select Byte or Word mode

Ready/Busy Output

Device Power Supply

V^SS

Device Ground

N.C.

No Internal Connection

5

MBM29LV160TM/BM90

■ BLOCK DIAGRAM

DQ15 to DQ0

RY/BY

RY/BY Buffer

VCC

VSS

Input/Output

Buffers

Erase Voltage

Generator

WE

RESET

BYTE

State

Control

Command

Register

Program Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Data Latch

CE

OE

Y-Gating

Y-Decoder

X-Decoder

STB

Timer for

Program/Erase

Low V^CCDetector

Address

Latch

Cell Matrix

A19 to A0

A -1

■ LOGIC SYMBOL

A-1

20

A

19 to A0

16 or 8

DQ 15 to DQ 0

CE

OE

WE

RESET

BYTE

RY/BY

6

MBM29LV160TM/BM90

■ DEVICE BUS OPERATION

MBM29LV160TM/BM User Bus Operations (Word Mode : BYTE = V^IH)

DQ¹⁵to

DQ⁰

Operation

CE OE WE

A⁰

A¹

A⁶

A⁹

RESET

Standby

H

L

X

L

X

H

L

X

L

X

L

X

L

X

VID

A9

X

Hi-Z

Code

DOUT

Hi-Z

*3

H

Autoselect Manufacture Code ^*1

Autoselect Device Code ^*1

Read

L

H

A⁰

X

L

H

L

A1

X

A6

X

A6

L

H

Output Disable

H

X

H

Write (Program/Erase)

Enable Sector Protection ^*2

Temporary Sector Unprotection

Reset (Hardware)

A⁰

L

A1

H

X

A9

X

H

L

*3

VID

L

X

*3

X

Hi-Z

Legend : L = V^IL, H = VIH, X = VIL or VIH. See “1. DC Characteristics” in ■ELECTRICAL CHARACTERISTICS for

voltage levels.

Hi-Z = High-Z, VID = 11.5 V to 12.5 V

*1 : Manufacturer and device codes may also be accessed via a command register write sequence. See

“MBM29LV160TM/BM Standard Command Definitions”.

*2 : Refer to “Sector Protection” in ■FUNCTIIONAL DESCRIPTION.

*3 : D^INor DOUT as required by command sequence, data polling, or sector protect algorithm.

7

MBM29LV160TM/BM90

MBM29LV160TM/BM User Bus Operations (Byte Mode : BYTE = V^IL)

DQ¹⁵/

A^-1

DQ⁷to

DQ⁰

Operation

CE OE WE

A⁰

A¹

A⁶

A⁹

RESET

Standby

H

L

X

L

X

H

L

X

L

X

L

X

L

X

L

X

VID

A9

X

Hi-Z

Code

DOUT

Hi-Z

*3

H

Autoselect Manufacture Code ^*1

Autoselect Device Code ^*1

Read

L

H

A0

X

L

H

L

A^-1

X

A1

X

A6

X

A6

L

H

Output Disable

H

X

H

Write (Program/Erase)

Enable Sector Protection ^*2

Temporary Sector Unprotection

Reset (Hardware)

A^-1

L

A0

L

A1

H

X

A9

X

H

L

*3

VID

L

X

*3

X

Hi-Z

Legend : L = V^IL, H = VIH, X = VIL or VIH. See “1. DC Characteristics” in ■ELECTRICAL CHARACTERISTICS for

voltage levels.

Hi-Z = High-Z, VID = 11.5 V to 12.5V

*1 : Manufacturer and device codes may also be accessed via a command register write sequence.

See “MBM29LV160TM/BM Standard Command Definitions”.

*2 : Refer to “Sector Protection” in ■FUNCTIIONAL DESCRIPTION.

*3 : D^INor DOUT as required by command sequence, data polling, or sector protect algorithm.

8

MBM29LV160TM/BM90

MBM29LV160TM/BM Standard Command Definitions*¹

Bus

Write

Cy-

Fourth Bus

Read/Write

Cycle

First Bus Second Bus Third Bus

Write Cycle Write Cycle Write Cycle

Fifth Bus

Sixth Bus

Command

Sequence

Write Cycle Write Cycle

cles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Req'd

Word

/Byte

Reset *²

1

3

XXXh F0h

—

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

2AAh

555h

2AAh

555h

2AAh

555h

2AAh

555h

2AAh

555h

—

555h

AAh

555h

AAAh

555h

AAAh

555h

AAAh

555h

AAAh

555h

AAAh

—

RD

55h

F0h RA*¹⁰

10

*

AAAh

555h

AAh

00h 04h

Autoselect(Device ID)

Program

3

4

6

55h

90h

—

10

*

AAAh

555h

AAh

A0h PA

PD

AAAh

2AAh

555h

2AAh

555h

—

555h

AAh

555h

80h

555h

AAAh

Chip Erase

AAh

55h

10h

AAAh

555h

AAh

555h

80h

Sector Erase

55h SA 30h

AAAh

Program/Erase Suspend *³

Program/Erase Resume *³

1

—

XXXh

B0h

XXXh 30h

—

Word

Set to Fast Mode *⁴

Byte

2AAh

555h

AAh

555h

AAAh

3

55h

20h

—

AAAh

Word

Fast Program*⁴

/Byte

XXXh

2

A0h PA

PD

—

Reset from Fast

Mode *⁵

00h

Word

/Byte

XXXh 90h XXXh

—

9

*

Word

Byte

Word

Byte

Extended Sector

Protection* *

SD

*

4

1

XXXh 60h SA 60h SA 40h SA*¹⁰

—

10

6,

7

55h

AAh

Query*⁸

98h

—

(Continued)

9

MBM29LV160TM/BM90

(Continued)

Legend : Address bits A¹⁹to A12 = X = “H” or “L” for all address commands except for Program Address (PA),

Sector Address (SA).

Bus operations are defined in “MBM29LV160TM/BM User Bus Operations (Word Mode: BYTE = VIH)”

and “MBM29LV160TM/BM User Bus Operations (Byte Mode : BYTE = VIL)”.

RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of

the write pulse.

SA = Address of the sector to be programmed / erased. The combination of A19, A18, A17, A16, A15, A14,

A13 and A12 will uniquely select any sector. See “Sector Address Table (MBM29LV160TM)” and

“Sector Address Table (MBM29LV160BM)”.

SD = Sector protection verify data. Output 01h at protected sector addresses and output

00h at unprotected sector addresses.

RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.

*1 : The command combinations not described in “MBM29LV160TM/BM Standard Command Definitions” are

illegal.

*2 : Both of these reset commands are equivalent.

*3 : The Erase Suspend and Erase Resume command are valid only during a sector erase operation.

*4 : The Set to Fast Mode command is required prior to the Fast Program command.

*5 : The Reset from Fast Mode command is required to return to the read mode when the device is in fast mode.

*6 : This command is valid while RESET = VID.

*7 : Sector Address (SA) with A⁶= 0, A1 = 1, and A0 = 0

*8 : The valid address are A6 to A0.

*9 : The data “F0h” is also acceptable.

*10 : Indicates read cycle.

10

MBM29LV160TM/BM90

Sector Protection Verify Autoselect Codes

Type

A¹⁹to A¹²

A⁶

A¹

A⁰

A^-1*¹

VIL

X

Code (HEX)

04h

Manufacturer’s Code

X

V^IL

VIL

Word

Byte

Word

Byte

22C4h

C4h

MBM29LV160TM

MBM29LV160BM

X

V^IL

VIL

VIH

VIL

X

Device Code

2249h

49h

V^IL

VIL

VIH

VIL

V^IL

Sector

Addresses

Sector Protection

VIL

*2

*1 : A-1 is for Byte mode.

*2 : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.

11

MBM29LV160TM/BM90

Sector Address Table (MBM29LV160TM)

Sector Size

(Kbytes/

Kwords)

Sector

Address

Address Range

( x 8 )

Address Range

( x 16 )

A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

64/32

32/16

8/4

00000h to 0FFFFh

10000h to 1FFFFh

20000h to 2FFFFh

30000h to 3FFFFh

40000h to 4FFFFh

50000h to 5FFFFh

60000h to 6FFFFh

70000h to 7FFFFh

80000h to 8FFFFh

90000h to 9FFFFh

000000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

A0000h to AFFFFh 050000h to 057FFFh

B0000h to BFFFFh 058000h to 05FFFFh

C0000h to CFFFFh 060000h to 067FFFh

D0000h to DFFFFh 068000h to 06FFFFh

E0000h to EFFFFh 070000h to 077FFFh

F0000h to FFFFFh 078000h to 07FFFFh

100000h to 10FFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to B0FFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1F7FFFh 0F8000h to 0FBFFFh

1F8000h to 1F9FFFh 0FC000h to 0FCFFFh

1FA000h to 1FBFFFh 0FD000h to 0FDFFFh

1FC000h to 1FFFFFh 0FE000h to 0FEFFFh

1

0

1

8/4

1

X

16/8

12

MBM29LV160TM/BM90

Sector Address Table (MBM29LV160BM)

Sector Size

(Kbytes/

Kwords)

Sector

Address

Address Range

( x 8 )

Address Range

( x 16 )

A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

16/8

8/4

00000h to 03FFFh 000000h to 001FFFh

04000h to 05FFFh 002000h to 002FFFh

06000h to 07FFFh 003000h to 003FFFh

08000h to 0FFFFh 004000h to 007FFFh

10000h to 1FFFFh 008000h to 00FFFFh

20000h to 2FFFFh 010000h to 017FFFh

30000h to 3FFFFh 018000h to 01FFFFh

40000h to 4FFFFh 020000h to 027FFFh

50000h to 5FFFFh 028000h to 02FFFFh

60000h to 6FFFFh 030000h to 037FFFh

70000h to 7FFFFh 038000h to 03FFFFh

80000h to 8FFFFh 040000h to 047FFFh

90000h to 9FFFFh 048000h to 04FFFFh

A0000h to AFFFFh 050000h to 057FFFh

B0000h to BFFFFh 058000h to 05FFFFh

C0000h to CFFFFh 060000h to 067FFFh

D0000h to DFFFFh 068000h to 06FFFFh

E0000h to EFFFFh 070000h to 077FFFh

F0000h to FFFFFh 078000h to 07FFFFh

100000h to 1FFFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 08FFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

SA2

0

1

8/4

SA3

1

0

X

32/16

64/32

SA4

X

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

13

MBM29LV160TM/BM90

Common Flash Memory Interface Code

Description

A⁰to A⁶

DQ¹⁵to DQ⁰

10h

11h

12h

0051h

0052h

0059h

Query-unique ASCII string “QRY”

13h

14h

0002h

0000h

Primary OEM Command Set

(02h = Fujitsu standard)

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set

(00h = not applicable)

19h

1Ah

0000h

Address for Alternate OEM Extended Table

(00h = not applicable)

V^CCMin (write/erase)

DQ7 to DQ4: 1V/bit,

DQ3 to DQ0: 100 mV/bit

1Bh

1Ch

0027h

0036h

V^CCMax (write/erase)

DQ7 to DQ4: 1V/bit,

DQ3 to DQ0: 100 mV/bit

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

0000h

0007h

0000h

000Ah

0000h

0001h

0000h

0004h

0000h

0015h

V^PPMin voltage (00h = no Vpp pin)

VPP Max voltage (00h =no Vpp pin)

Typical timeout per single write 2^Nµs

Typical timeout for Min size buffer write 2^Nµs

Typical timeout per individual sector erase 2^Nms

Typical timeout for full chip erase 2^Nms

Max timeout for write 2^Ntimes typical

Max timeout for buffer write 2^Ntimes typical

Max timeout per individual sector erase 2^Ntimes typical

Max timeout for full chip erase 2^Ntimes typical

Device Size = 2^Nbyte

28h

29h

0002h

0000h

Flash Device Interface description

2Ah

2Bh

0000h

Max number of byte in

multi-byte write = 2^N

2Ch

0004h

Number of Erase Block Regions within device (01h = uniform)

2Dh

2Eh

2Fh

30h

0000h

0040h

0000h

Erase Block Region 1 Information

(Continued)

14

MBM29LV160TM/BM90

(Continued)

A⁰to A⁶

DQ¹⁵to DQ⁰

Description

31h

32h

33h

34h

0001h

0000h

0020h

0000h

Erase Block Region 2 Information

35h

36h

37h

38h

0000h

0080h

0000h

Erase Block Region 3 Information

39h

3Ah

3Bh

3Ch

001Eh

0000h

0001h

Erase Block Region 4 Information

Query-unique ASCII string “PRI”

40h

41h

42h

0050h

0052h

0049h

43h

44h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock

Required

45h

0000h

Erase Suspend

(02h = To Read & Write)

46h

47h

48h

49h

4Ah

0002h

0001h

0004h

0000h

Number of sectors in per group

Sector Temporary Unprotection

(01h = Supported)

Sector Protection Algorithm

Dual Operation

(00h = Not Supported)

Burst Mode Type

(00h = Not Supported)

4Bh

4Ch

50h

0000h

0001h

Page Mode Type

(00h = Not Supported)

Program Suspend

(01h = Supported)

15

MBM29LV160TM/BM90

■ FUNCTIONAL DESCRIPTION

Standby Mode

There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and

the other via the RESET pin only.

When using both pins, CMOS standby mode is achieved with CE and RESET input held at VCC ±0.3 V. Under

this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC active

current (ICC2) is required even when CE = “H”. The device can be read with standard access time (tCE) from either

of these standby modes.

When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS ±0.3 V (CE =

“H” or “L”) . Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is set high,

the device requires tRH as a wake-up time for output to be valid for read access.

During standby mode, the output is in the high impedance state, regardless of OE input.

Automatic Sleep Mode

Automatic sleep mode works to restrain power consumption during read-out of device data. It can be useful in

applications such as handy terminal, which requires low power consumption.

To activate this mode, the device automatically switch themselves to low power mode when the device addresses

remain stable after t^ACC+30 ns from data valid. It is not necessary to control CE, WE, and OE in this mode. The

current consumed is typically 1 µA (CMOS Level).

Since the data are latched during this mode, the data are continuously read out. When the addresses are

changed, the mode is automatically canceled and the device read-out the data for changed addresses.

Autoselect

The Autoselect mode allows reading out of a binary code and identifies its manufacturer and type.It is intended

for use by programming equipment for the purpose of automatically matching the device to be programmed with

its corresponding programming algorithm.

To activate this mode, the programming equipment must force V^IDon address pin A9. Two identifier bytes may

then be sequenced from the devices outputs by toggling A0. All addresses can be either High or Low except A6,

A1 and A0. See “MBM29LV160TM/BM User Bus Operations (Word Mode: BYTE = VIH)” and “MBM29LV160TM/

BM User Bus Operations (Byte Mode : BYTE = VIL)” in ■DEVICE BUS OPERATION.

The manufacturer and device codes may also be read via the command register, for instances when the device

is erased or programmed in a system without access to high voltage on the A⁹pin. The command sequence is

illustrated in “MBM29LV160TM/BM Standard Command Definitions” in ■DEVICE BUS OPERATION.Refer to

“Autoselect Command” in ■COMMAND DEFINITIONS.

In Word mode, a read cycle from address 00h returns the manufacturer’s code (Fujitsu = 04h) . A read cycle at

address 01h outputs device code(MBM29LV160TM: 22C4h; MBM29LV160BM: 2249h). Notice that the above

applies to Word mode. The addresses and codes differ from those of Byte mode. Refer to “Sector Protection

Verify Autoselect Codes” in ■DEVICE BUS OPERATION.

Read Mode

The device has two control functions required to obtain data at the outputs. CE is the power control and used

for a device selection. OE is the output control and used to gate data to the output pins.

Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the

addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after

power-up, input hardware reset or to change CE pin from “H” or “L”.

Output Disable

With the OE input at logic high level (VIH), output from the devices are disabled. This may cause the output pins

to be in a high impedance state.

16

MBM29LV160TM/BM90

Write

Device erasure and programming are accomplished via the command register. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the device function.

The command register itself does not occupy any addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The com-

mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

falling edge of WE or CE, whichever starts later; while data is latched on the rising edge of WE or CE, whichever

starts first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and “Alternate WE Controlled Program Operation Timing Diagram” in

■SWITCHING WAVEFORMS for specific timing parameters.

Sector Protection

The device features hardware sector protection. This feature will disable both program and erase operations in

any combination of 35 sectors of memory. The user‘s side can use the sector protection using programming

equipment. The device is shipped with all sectors that are unprotected.

To activate it, the programming equipment must force V^IDon address pin A9 and control pin OE, CE = VIL and

A6 = A0 = VIL, A1 = VIH. The sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector

to be protected. “Sector Address Table (MBM29LV160TM)” and “Sector Address Table (MBM29LV160BM)” in

■DEVICE BUS OPERATION defines the sector address for each of the thirty-five (35) individual sectors. Pro-

gramming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising

edge of the same. Sector addresses must be held constant during the WE pulse. See “Sector Protection Timing

Diagram” in ■SWITCHING WAVEFORMS and “Sector Protection Algorithm” in ■FLOW CHART for sector

protection timing diagram and algorithm.

To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12)

while (A⁶, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise

the device will produce “0” for unprotected sectors. In this mode, the lower order addresses, except for A0, A1,

and A6 can be either High or Low. Address locations with A1 = VIL are reserved for Autoselect manufacturer and

device codes. A-1 requires applying to VIL on Byte mode.

It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing

a read operation at the address location XX02h, where the higher order addresses (A19, A18, A17, A16, A15, A14,

A13, and A12) are the desired sector address will produce a logical “1” at DQ0 for a protected sector. See “Sector

Protection Verify Autoselect Codes” in ■DEVICE BUS OPERATION for Autoselect codes.

Temporary Sector Unprotection

This feature allows temporary unprotection of previously protected sectors of the devices in order to change

data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this

mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the

V^IDis taken away from the RESET pin, all the previously protected sectors will be protected again. Refer to

“Temporary Sector Unprotection Timing Diagram” in ■SWITCHING WAVEFORMS and “Temporary Sector Un-

protection Algorithm” in ■FLOW CHART.

Hardware Reset

The devices may be reset by driving the RESET pin to VIL from VIH. The RESET pin has a pulse requirement

and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation

in the process of being executed will be terminated and the internal state machine will be reset to the read mode

“tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an

additional “tRH” before it will allow read access. When the RESET pin is low, the devices will be in the standby

mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during

a program or erase operation, the data at that particular location will be corrupted.

17

MBM29LV160TM/BM90

■ COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register.

“MBM29LV160TM/BM Standard Command Definitions” in ■DEVICE BUS OPERATION shows the valid register

command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only

while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h)

commands are valid only while the Program operation is in progress.Moreover Reset commands are functionally

equivalent, resetting the device to the read mode. Please note that commands must be asserted to DQ7 to DQ0

and DQ15 to DQ8 bits are ignored.

Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ⁵= 1) to Read mode, the Reset operation

is initiated by writing the Reset command sequence into the command register. The devices remain enabled for

reads until the command register contents are altered.

The devices will automatically be in the reset state after power-up. In this case, a command sequence is not

required in order to read data.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore,

manufacture and device codes must be accessible while the devices reside in the target system. PROM pro-

grammers typically access the signature codes by raising A⁹to a high voltage. However applying high voltage

onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming method-

ology. The operation is initiated by writing the Autoselect command sequence into the command register.

The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write

cycle that contains the address and the Autoselect command. Then the manufacture and device codes can be

read from the address, and an actual data of memory cell can be read from the another address.

Following the command write, a read cycle from address 00h returns the manufactures’s code (Fujitsu = 04h).

A read cycle at address 01h outputs device code (MBM29LV160TM : C4h in byte mode and 22C4h in word

mode ; MBM29LV160BM : 49h in byte mode and 2249h in word mode). Refer to “Sector Protection Verify

Autoselect Codes” in ■DEVICE BUS OPERATION.

To terminate the operation, it is necessary to write the Reset command into the register. To execute the Autoselect

command during the operation, Reset command must be written before the Autoselect command.

Programming

The devices are programmed on a word-by-word (or byte-by-byte ) basis. Programming is a four bus cycle

operation. There are 2 “unlock” write cycles. These are followed by the program set-up command and data write

cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched

on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first)

starts programming. Upon executing the Embedded Program Algorithm command sequence, the system is not

requiredtoprovidefurthercontrolsortimings. Thedevicewillautomaticallyprovideadequateinternallygenerated

program pulses and verify the programmed cell margin.

The system can determine the status of the program operation by using DQ⁷(Data Polling), DQ6 (Toggle Bit) or

RY/BY. The Data Polling and Toggle Bit are automatically performed at the memory location being programmed.

The programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which

the devices return to the read mode and plogram addresses are no longer latched. Therefore, the devices require

that a valid address to the devices be supplied by the system at this particular instance. Hence Data Polling

requires the same address which is being programmed.

If hardware reset occurs during the programming operation, the data being written is not guaranteed.

Programming is allowed in any address sequence and across sector boundaries. Beware that a data “0” cannot

be programmed back to a “1”. Attempting to do so may result in either failure condition or an apparent success

18

MBM29LV160TM/BM90

according to the data polling algorithm. But a read from Reset mode will show that the data is still “0”. Only erase

operations can convert “0”s to “1”s.

Note that attempting to program a “1” over a “0” will result in programming failure. This precaution is the same

with Fujitsu standard NOR devices. “Embedded Program^TMAlgorithm” in ■FLOW CHART illustrates the Em-

bedded Program^TMAlgorithm using typical command strings and bus operations.

Program Suspend/Resume

The Program Suspend command allows the system to interrupt a program operation so that data can be read

from any address. Writing the Program Suspend command (B0h) during Embedded Program operation imme-

diately suspends the programming. Refer to "Erase Suspend/Resume" for the detail.

When the Program Suspend command is written during a programming process, the device halts the program

operation within 1us and updates the status bits.After the program operation has been suspended, the system

can read data from any address. The data at program-suspended address is not valid. Normal read timing and

command definitions apply.

After the Program Resume command (30h) is written, the device reverts to programming. The system can

determine the status of the program operation using the DQ⁷or DQ6 status bits, just as in the standard program

operation. See "Write Operation Status" for more information. When issuing program suspend command in

4 µs after issuing program command, determine the status of program operation by reading status bit at more

4 µs after issuing program resume command.

The system also writes the Autoselect command sequence in the Program Suspend mode. The device allows

reading Autoselect codes at the addresses within programming sectors, since the codes are not stored in the

memory. When the device exits the Autoselect mode, the device reverts to the Program Suspend mode, and is

ready for another valid operation. See "Autoselect Command" for more information.

The system must write the Program Resume command to exit from the Program Suspend mode and continue

the programming operation. Further writes of the Resume command are ignored. Another Program Suspend

command can be written after the device resumes programming.

Do not read CFI code after HiddenROM Entry and Exit in program suspend mode.

Chip Erase

Chip erase is a six bus cycle operation. It begins 2 “unlock” write cycles followed by writing the “set-up” command,

and 2 “unlock” write cycles followed by the chip erase command which invokes the Embedded Erase Algorithm.

The device does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm the devices automatically programs and verifies the entire memory for an all zero data pattern prior

to electrical erase (Preprogram function). The system is not required to provide any controls or timings during

these operations.

The system can determine the erase operation status by using DQ⁷(Data Polling), DQ6 (Toggle Bit I) and DQ2

(Toggle Bit II) or RY/BY output signal. The chip erase begins on the rising edge of the last CE or WE, whichever

happens first from last command sequence and completes when the data on DQ7 is “1” (See “Write Operation

Status”.) at which time the device returns to read mode.

Sector Erase

Sector erase is a six bus cycle operation. There are 2 “unlock” write cycles. These are followed by writing the

“set-up” command. 2 more “unlock” write cycles are then followed by the Sector Erase command.

Multiple sectors may be erased concurrently by writing the same six bus cycle operations. This sequence is

followed by writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased.

The time between writes must be less than Erase Time-out time(t^TOW). Otherwise that command will not be

accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to

guarantee this condition. The interrupts can reoccur after the last Sector Erase command is written. A time-out

of “t^TOW” from the rising edge of last CE or WE, whichever happens first, will initiate the execution of the Sector

Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-

out window the timer is reset (monitor DQ3 to determine if the sector erase timer window is still open, see section

19

MBM29LV160TM/BM90

“DQ³”, Sector Erase Timer). Resetting the devices once execution has begun will corrupt the data in the sector.

In that case, restart the erase on those sectors and allow them to complete (refer to “Write Operation Status”).

Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 34).

Sector erase does not require the user to program the devices prior to erase. The devices automatically program

all memory locations in the sector(s) to be erased prior to electrical erase using the Embedded Erase Algorithm.

When erasing a sector, the remaining unselected sectors remain unaffected. The system is not required to

provide any controls or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling), DQ6 (Toggle Bit) or

RY/BY.

The sector erase begins after the “t^TOW” time-out from the rising edge of CE or WE whichever happens first for

the last sector erase command pulse and completes when the data on DQ7 is “1” (see “Write Operation Status”),

at which the devices return to the read mode. Data polling and Toggle Bit must be performed at an address

within any of the sectors being erased.

Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt Sector Erase operation and then perform read to a

sector not being erased. This command is applicable ONLY during the Sector Erase operation within the time-

out period for sector erase. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results

in immediate termination of the time-out period and suspension of the erase operation.

Writing the "Erase Resume" command (30h) resumes the erase operation.

When the "Erase Suspend" command is written during the Sector Erase operation, the device takes maximum

of “t^SPD” to suspend the erase operation. When the devices enter the erase-suspended mode, the RY/BY output

pin will be at Hi-Z and the DQ7 bit will be at logic “1” and DQ6 will stop toggling. The user must use the address

of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further

writes of the Erase Suspend command are ignored.

When the erase operation is suspended, the devices default to the erase-suspend-read mode. Reading data in

this mode is the same as reading from the standard read mode, except that the data must be read from sectors

that have not been erase-suspended. Reading successively from the erase-suspended sector while the device

is in the erase-suspend-read mode will cause DQ²to toggle. see the section on DQ2.

To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of

the Resume command at this point will be ignored. Another Erase Suspend command can be written after the

chip has resumed erasing.

Do not issue program command after entering erase-suspend-read mode.

Fast Mode Set/Reset

The device has Fast Mode function. It dispenses with the initial two unclock cycles required in the standard

program command sequence by writing Fast Mode command into the command register. In this mode, the

required bus cycle for programming consists of two cycles instead of four bus cycles in standard program

command. During the Fast mode, do not write any commands other than the Fast program/Fast mode reset

command. The read operation is also executed after exiting this mode. To exit from this mode, write Fast Mode

Reset command into the command register. (Refer to the “Embedded Program^TMAlgorithm for Fast Mode” in

■FLOW CHART.) The V^CCactive current is required even CE = VIH during Fast Mode.

20

MBM29LV160TM/BM90

Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program

Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). See “Embedded

Program^TMAlgorithm for Fast Mode” in ■FLOW CHART.

Extended Sector Protection

In addition to normal sector protection, the device has Extended Sector Protection as extended function. This

function enables protection of the sector by forcing VID on RESET pin and writes a command sequence. Unlike

conventional procedures, it is not necessary to force VID and control timing for control pins. The only RESET pin

requires VID for sector protection in this mode. The extended sector protection requires VID on RESET pin. With

this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then

the sector addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 0, 1, 0) should be set to

the sector to be protected (set VIL for the other addresses pins is recommended), and write extended sector

protection command (60h). A sector is typically protected in 250 µs. To verify programming of the protection

circuitry, the sector addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be

set and write a command (40h). Following the command write, a logical “1” at device output DQ0 will produce

for protected sector in the read operation. If the output data is logical “0”, write the extended sector protection

command(60h)again. Toterminatetheoperation, setRESETpintoVIH. (Refertothe“ExtendedSectorProtection

Timing Diagram” in ■SWITCHING WAVEFORMS and “Extended Sector Protection Algorithm” in ■FLOW

CHART.)

Query Command (CFI : Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation

handshake which allows specific vendor-specified software algorithms to be used for entire families of devices.

This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software sup-

port for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98h) into the command register. Following the command

write, a read cycle from specific address retrieves device information. Please note that output data of upper byte

(DQ¹⁵to DQ8) is “0”. Refer to “Common Flash Memory Interface Code” in ■DEVICE BUS OPERATION. To

terminate operation, it is necessary to write the Reset command sequence into the register. (See “Common

Flash Memory Interface Code” in ■DEVICE BUS OPERATION.)

Write Operation Status

Detailed in “Hardware Sequence Flags” are all the status flags which can determine the status of the device for

current mode operation. When checking Hardware Sequence Flags during program operations, it should be

checked 4 µs after issuing program command. During sector erase, the part provides the status flags automat-

ically to the I/O ports. The information on DQ²is address sensitive. If an address from an erasing sector is

consecutively read, then the DQ2 bit will toggle. However DQ2 will not toggle if an address from a non-erasing

sector is consecutively read. This allows the user to determine which sectors are erasing.

Once erase suspend is entered address sensitivity still applies. If the address of a non-erasing sector (one

available for read) is provided, then stored data can be read from the device. If the address of an erasing sector

(one unavailable for read) is applied, the device will output its status bits.

21

MBM29LV160TM/BM90

Hardware Sequence Flags

Status

DQ⁷

0

DQ⁶

DQ⁵

0

DQ³

0

DQ²

1

Embedded Program Algorithm

Embedded Erase Algorithm

Program-Suspend-Read

Toggle

0

1

Toggle*¹

Data

1

Data

1

Data

0

Data

0

Data

Program

Suspend

(Program Suspended Sector)

Program-Suspend-Read

Mode

In

(Non-Program Suspended Sector)

Progress

Erase-Suspend-Read

(Erase Suspended Sector)

Toggle*¹

Data

Erase

Erase-Suspend-Read

Suspend

Data

DQ7

Data

Toggle

Data

0

Data

0

(Non-Erase Suspended Sector)

Mode

Erase-Suspend-Program

(Non-Erase Suspended Sector)

1*²

Embedded Program Algorithm

DQ⁷

0

Toggle

1

0

1

Exceeded Embedded Erase Algorithm

N/A

Time

Limits

Erase

Suspend

Mode

Erase-Suspend-Program

(Non-Erase Suspended Sector)

DQ7

Toggle

1

0

N/A

*1 : Successive reads from the erasing or erase-suspend sector will cause DQ²to toggle.

*2 : Reading from non-erase suspend sector address will indicate logic “1” at the DQ²bit.

DQ⁷

Data Polling

The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in

progress or completed. During the Embedded Program Algorithm, an attempt to read devices will produce

reverse data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the

device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the

device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to

read device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in “Data Polling

Algorithm” in ■FLOW CHART.

For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse

sequence.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. Data Polling must be performed at sector addresses of sectors being erased, not protected

sectors. Otherwise, the status may become invalid.

If a program address falls within a protected sector, Data polling on DQ7 is active for approximately 1 µs, then

the device returns to read mode. After an erase command sequence is written, if all sectors selected for erasing

are protected, Data Polling on DQ7 is active for approximately 100 µs, then the device returns to read mode. If

not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and

ignores the selected sectors that are protected.

Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ⁷) may change

asynchronously while the output enable (OE) is asserted low. This means that the device is driving status

information on DQ7 at one instant of time, and then that byte’s valid data the next. Depending on when the system

samples the DQ7 output, it may read the status or valid data. Even if the device completes the Embedded

22

MBM29LV160TM/BM90

Algorithm operation and DQ⁷has a valid data, the data outputs on DQ6 to DQ0 may still be invalid. The valid data

on DQ7 to DQ0 will be read on the successive read attempts.

The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algo-

rithm, Erase Suspend mode or sector erase time-out.

See “Data Polling during Embedded Algorithm Operation Timing Diagram” in ■SWITCHING WAVEFORMS for

the Data Polling timing specifications and diagram.

DQ⁶

Toggle Bit I

The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded

Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data

from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase

Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts.

During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse

sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse

in the six write pulse sequences. The Toggle Bit I is active during the sector time out.

In programm operation, if the sector being written to is protected, the Toggle bit will toggle for about 1 µs and

then stop toggling with the data unchanged. In erase, the device will erase all the selected sectors except for

the protected ones. If all selected sectors are protected, the chip will toggle the Toggle bit for about 100 µs and

then drop back into read mode, having data kept remained.

Either CE or OE toggling will cause the DQ6 to toggle. See “Toggle Bit l Timing Diagram during Embedded

Algorithm Operations” in ■SWITCHING WAVEFORMS for the Toggle Bit I timing specifications and diagram.

DQ⁵

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ5 will produce a “1”. This is a failure condition indicating that the program or erase cycle was

not successfully completed. Data Polling is the only operating function of the device under this condition. The

CE circuit will partially power down the device under these conditions. The OE and WE pins will control the

output disable functions as described in “MBM29LV160TM/BM User Bus Operations (Word Mode : BYTE = VIH)”

and “MBM29LV160TM/BM User Bus Operations (Byte Mode : BYTE = VIL)” in ■DEVICE BUS OPERATION.

The DQ⁵failure condition may also appear if a user tries to program a non blank location without pre-erase. In

this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never

reads a valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5

bit will indicate a “1”. Note that this is not a device failure condition since the device was incorrectly used. If this

occurs, reset the device with command sequence.

DQ³

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will

remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase

command sequence.

If Data Polling or the Toggle Bit I indicates a valid erase command has been written, DQ3 may be used to

determine whether the sector erase timer window is still open. If DQ3 is “1” the internally controlled erase cycle

has begun. If DQ3 is “0”, the device will accept additional sector erase commands. To insure the command has

been accepted, the system software should check the status of DQ3 prior to and following each subsequent

SectorErasecommand. IfDQ3 werehighonthesecondstatuscheck, thecommandmaynothavebeenaccepted.

See “Hardware Sequence Flags”.

23

MBM29LV160TM/BM90

DQ²

Toggle Bit II

This Toggle bit II, along with DQ⁶, can be used to determine whether the devices are in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the

devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase

suspended sector will indicate a logic “1” at the DQ2 bit.

DQ⁶is different from DQ2 in that DQ6 toggles only when the standard program or erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized

as follows:

For example, DQ²and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

(DQ2 toggles while DQ6 does not.) See also “Hardware Sequence Flags” and “DQ2 vs. DQ6” in ■SWITCHING

WAVEFORMS.

Furthermore, DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles

if this bit is read from an erasing sector.

Reading Toggle Bits DQ⁶/ DQ²

Whenever the system initially begins reading Toggle bit status, it must read DQ7 to DQ0 at least twice in a row

to determine whether a Toggle bit is toggling. Typically a system would note and store the value of the Toggle

bit after the first read. After the second read, the system would compare the new value of the Toggle bit with the

first. If the Toggle bit is not toggling, the device has completed the program or erase operation. The system can

read array data on DQ7 to DQ0 on the following read cycle.

However, if, after the initial two read cycles, the system determines that the Toggle bit is still toggling, the system

also should note whether the value of DQ⁵is high (see the section on “DQ5”) . If it is, the system should then

determine again whether the Toggle bit is toggling, since the Toggle bit may have stopped toggling just as DQ5

went high. If the Toggle bit is no longer toggling, the device has successfully completed the program or erase

operation. If it is still toggling, the device did not complete the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the Toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the Toggle bit and DQ5 through successive read cycles, deter-

mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system

tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the

status of the operation. (Refer to “Toggle Bit Algorithm” in ■FLOW CHART.)

Toggle Bit Status

Mode

DQ⁷

DQ7

0

DQ⁶

DQ²

1

Program

Erase

Toggle

Toggle*¹

Erase-Suspend-Read

(Erase-Suspended Sector)

1

Toggle*¹

1*²

Erase-Suspend-Program

DQ7

Toggle

*1 : Successive reads from the erasing or erase-suspend sector will cause DQ²to toggle.

*2 : Reading from the non-erase suspend sector address will indicate logic “1” at the DQ²bit.

24

MBM29LV160TM/BM90

RY/BY

Ready/Busy

The device provides a RY/BY open-drain output pin to indicate to the host system that the Embedded Algorithms

are either in progress or has been completed. If the output is low, the device is busy with either a program or

erase operation. If the output is high, the device is ready to accept any read/write or erase operation. If the

device is placed in an Erase Suspend mode, the RY/BY output will be high, by means of connecting with a pull-

up resister to VCC.

During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a

busy condition during the RESET pulse. See “RY/BY Timing Diagram during Program/Erase Operation Timing

Diagram”, “RESET Timing Diagram ( Not during Embedded Algorithms )” and “RESET Timing Diagram ( During

Embedded Algorithms )” in ■SWITCHING WAVEFORMS for a detailed timing diagram. The RY/BY pin is pulled

high in standby mode.

Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.

Word/Byte Configuration

BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high, the

device operates in the word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven

low, the device operates in byte (8-bit) mode. In this mode, DQ15/A-1 pin becomes the lowest address bit, and

DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence com-

mands are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored.

Data Protection

The device is designed to offer protection against accidental erasure or programming caused by spurious system

level signals that may exist during power transitions. During power up the device automatically reset the internal

state machine in Read mode. Also, with its control register architecture, alteration of memory contents only

occurs after successful completion of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent inadvertent write cycles resulting form V^CCpower-up

and power-down transitions or system noise.

(1) Low V^CCWrite Inhibit

To avoid initiation of a write cycle during V^CCpower-up and power-down, a write cycle is locked out for VCC less

than VLKO. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled.

Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level

is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct to prevent

unintentional writes when VCC is above VLKO.

If Embedded Erase Algorithm is interrupted, the intervened erasing sector(s) is(are) not valid.

(2) Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.

(3) Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must

be a logical zero while OE is a logical one.

(4) Power-up Write Inhibit

Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to read mode on power-up.

(5) Sector Protection

Device user is able to protect each sector group individually to store and protect data. Protection circuit voids

both write and erase commands that are addressed to protected sectors.

Any commands to write or erase addressed to protected sector are ignored .

25

MBM29LV160TM/BM90

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

Min

–55

–20

Max

+125

+70

Storage Temperature

Tstg

T^A

°C

Ambient Temperature with Power Applied

Voltage with Respect to Ground All Pins Except

A⁹, OE, and RESET ^*1,*2

VIN, VOUT

–0.5

VCC + 0.5

V

Power Supply Voltage ^*1

VCC

VIN

–0.5

+4.0

V

*1,*3

A9, OE, and RESET

+12.5

*1 : Voltage is defined on the basis of VSS = GND = 0V.

*2 : Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot

V^SSto –0.2 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage

transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns.

*3 : Minimum DC input voltage is –0.5V. During voltage transitions, these pins may undershoot V^SSto –0.2 V for

periods of up to 20 ns.Voltage difference between input and supply voltage ( VIN–VCC) dose not exceed to

+9.0 V. Maximum DC input voltage is +12.5 V which may overshoot to +14.0 V for periods of up to 20 ns .

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS*¹

Value

Parameter

Symbol

Unit

Min

–20

+3.0

Max

+70

Ambient Temperature

VCC Supply Voltage *²

T^A

°C

V

VCC

+3.6

*1 : Operating ranges define those limits between which the functionality of the device is guaranteed.

*2 : Voltage is defined on the basis of V^SS= GND = 0V.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

26

MBM29LV160TM/BM90

■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT

20 ns

+0.6 V

–0.5 V

–2.0 V

20 ns

Maximum Undershoot Waveform

20 ns

VCC +2.0 V

VCC +0.5 V

0.7 × VCC

20 ns

Maximum Overshoot Waveform 1

20 ns

+14.0 V

+12.5 V

VCC +0.5 V

20 ns

Note: This waveform is applied for A⁹, OE, and RESET.

Maximum Overshoot Waveform 2

27

MBM29LV160TM/BM90

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

Value

Typ Max

Parameter

Symbol

Conditions

Unit

Min

–1.0

—

VIN = VSS to VCC,

VCC = VCC Max

Input Leakage Current

Output Leakage Current

I^LI

—

+1.0

35

µA

I^LO

ILIT

VOUT = VSS to VCC, VCC = VCC Max

A⁹, OE, RESET Inputs Leakage

Current

VCC = VCC Max,

A9, OE, RESET = 12.5 V

Word

Byte

Word

Byte

—

18

16

35

20

50

CE = VIL, OE = VIH,

f = 5 MHz

V^CCActive Current

(Read ) *^1,*²

ICC1

mA

CE = VIL, OE = VIH,

f = 10 MHz

V^CCActive Current

(Program / Erase) *^2,*³

ICC3

CE = VIL, OE = VIH

—

50

60

CE = VCC ±0.3 V, RESET = VCC ±0.3 V,

OE = VIH

V^CCStandby Current *²

V^CCReset Current *²

ICC4

ICC5

ICC6

—

1

5

µA

RESET = VCC ±0.3 V

CE = VSS ±0.3 V, RESET = VCC ±0.3 V,

VIN = VCC ±0.3V or Vss ±0.3V

VCC Automatic Sleep Current *⁴

V^CCActive Current

ICC7

V^IL

CE = VIL, OE = VIH

—

50

—

60

mA

V

(Erase-Suspend-Program) *²

Input Low Level

—

–0.5

0.6

VCC +

0.3

Input High Level

VIH

0.7×VCC

V

Voltage for Autoselect, and

Temporary Sector Unprotected

V^ID

VCC = 3.0 V to 3.6 V

11.5

12.0 12.5

V

Output Low Voltage Level

Output High Voltage Level

Low VCC Lock-Out Voltage

V^OL

VOH

VLKO

IOL = 4.0 mA, VCC = VCC Min

IOH = –2.0 mA, VCC = VCC Min

—

0.85×VCC

2.3

—

0.45

—

V

2.5

*1 : The lCC current listed includes both the DC operating current and the frequency dependent comnent.

*2 : Maximum I^CCvalues are tested with VCC = VCC Max.

*3 : lCC active while Embedded Erase or Embedded Program is in progress.

*4 : Automatic sleep mode enables the low power mode when address remain stable for tACC + 30 ns.

28

MBM29LV160TM/BM90

2. AC Characteristics

• Read Only Operations Characteristics

Symbol

Value*

Parameter

Condition

Unit

JEDEC Standard

Min

Max

Read Cycle Time

t^AVAV

tRC

—

90

ns

CE = VIL,

OE = VIL

Address to Output Delay

tAVQV

tACC

90

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

t^ELQV

t^GLQV

tEHQZ

tCE

tOE

tDF

OE = VIL

90

25

ns

—

Read

0

Output Enable

Hold Time

—

t^OEH

Toggle and Data Polling

10

Output Enable to Output High-Z

t^GHQZ

tAXQX

—

tDF

tOH

25

20

Output Hold Time From Addresses,

CE or OE, Whichever Occurs First

—

0

ns

µs

RESET Pin Low to Read Mode

tREADY

* : Test Conditions : Output Load

: 1 TTL gate and 30 pF

Input rise and fall times : 5 ns

Input pulse levels

: 0.0 V or V^CC

Timing measurement reference level

Input

: VCC / 2

Output : VCC / 2

3.3 V

Diode = 1N3064

or Equivalent

2.7 kΩ

Device

Under

Test

6.2 kΩ

CL

Diode = 1N3064

or Equivalent

Test Conditions

29

MBM29LV160TM/BM90

• Write (Erase/Program) Operations

Symbol

JEDEC Standard

Value

Typ

Parameter

Unit

Min

90

0

Max

Write Cycle Time

t^AVAV

t^AVWL

tWC

tAS

ns

Address Setup Time

Address Setup Time to OE Low During

Toggle Bit Polling

—

t^WLAX

—

tASO

tAH

15

45

0

ns

Address Hold Time

Address Hold Time from CE or OE High

During Toggle Bit Polling

tAHT

Data Setup Time

tDVWH

t^WHDX

—

tDS

tDH

35

0

ns

Data Hold Time

Output Enable Setup Time

CE High During Toggle Bit Polling

OE High During Toggle Bit Polling

tOES

tCEPH

tOEPH

0

—

20

—

Read Recover Time Before Write

(OE High to WE Low)

tGHWL

tGHEL

tGHWL

tGHEL

0

ns

Read Recover Time Before Write

(OE High to CE Low)

CE Setup Time

tELWL

tWLEL

tWHEH

tEHWH

tELEH

tWLWH

tEHEL

t^WHWL

tCS

tWS

tCH

0

ns

WE Setup Time

CE Hold Time

0

WE Hold Time

tWH

tCP

0

CE Pulse Width

Write Pulse Width

CE Pulse Width High

Write Pulse Width High

35

25

30

tWP

tCPH

tWPH

Word

25

Programming Time

Byte

t^WHWH1

tWHWH1

µs

Sector Erase Operation *¹

tWHWH2

—

tWHWH2

tVCS

1.0

s

µs

V^CCSetup Time

50

0

Recovery Time From RY/BY

—

tRB

ns

(Continued)

30

MBM29LV160TM/BM90

(Continued)

Symbol

JEDEC Standard

Value

Unit

Parameter

Min

Typ

Max

Erase/Program Valid to RY/BY Delay

Rise Time to V^ID*²

—

tBUSY

tVIDR

tVLHT

tWPP

tOESP

tCSP

tRP

90

ns

µs

ns

µs

500

4

Voltage Transition Time *²

Write Pulse Width*²

100

4

OE Setup Time to WE Active *²

CE Setup Time to WE Active *²

RESET Pulse Width

4

500

100

RESET High Time Before Read

Delay Time from Embedded Output Enable

Erase Time-out Time

tRH

tEOE

tTOW

tSPD

90

20

50

Erase Suspend Transition Time

*1 : This does not include the preprogramming time.

*2 : This timing is for Sector Protection operation.

31

MBM29LV160TM/BM90

■ ERASE AND PROGRAMMING PERFORMANCE

Value

Parameter

Unit

Remarks

Min

Typ

Max

Excludes programming time prior to

erasure

Sector Erase Time

—

1

15

s

Programming Time

—

25

—

1000

100

—

µs

s

Excludes system-level overhead

Chip Programming Time

Erase/Program Cycle

100,000

cycle

■ TSOP (1) PIN CAPACITANCE

Value

Unit

Parameter

Symbol

Test Setup

Typ

8

Max

Input Capacitance

C^IN

C^OUT

C^IN2

CIN3

VIN = 0

10

pF

Output Capacitance

VOUT = 0

VIN = 0

8.5

8

12

Control Pin Capacitance

OE Pin and RESET Pin Capacitance

10

20

25

Note : Test conditions TA = +25°C, f = 1.0 MHz

■ FBGA PIN CAPACITANCE

Value

Parameter

Input Capacitance

Symbol

Test Setup

Unit

Typ

8

Max

10

C^IN

C^OUT

C^IN2

CIN3

VIN = 0

VOUT = 0

VIN = 0

pF

Output Capacitance

8.5

8

12

Control Pin Capacitance

10

OE Pin and RESET Pin Capacitance

15

20

Note : Test conditions TA = +25°C, f = 1.0 MHz

32

MBM29LV160TM/BM90

■ SWITCHING WAVEFORMS

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Must Be

Steady

Will Be

Steady

May

Change

from H to L

Will Be

Changing

from H to L

May

Change

from L to H

Will Be

Changing

from L to H

“H” or “L”

Any Change

Permitted

Changing

State

Unknown

Does Not

Apply

Center Line is

High-

Impedance

“Off” State

t

RC

Address

Address Stable

t

ACC

CE

OE

t

OE

t

DF

t

OEH

WE

t

CE

t

OH

High-Z

Data

Output Valid

Read Operation Timing Diagram

33

MBM29LV160TM/BM90

tRC

Address

Address Stable

tACC

CE

tRH

tRP

tRH

tCE

RESET

Data

tOH

High-Z

Output Valid

Hardware Reset/Read Operation Timing Diagram

34

MBM29LV160TM/BM90

3rd Bus Cycle

Data Polling

555h

PA

Address

tWC

tRC

tAS

tAH

CE

tCH

tCS

tCE

OE

tOE

tWP

tWPH

tGHWL

tWHWH1

WE

tOH

tDF

tDS

tDH

PD

DOUT

A0h

DQ7

Data

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates the last two bus cycles out of four bus cycle sequence.

Alternate WE Controlled Program Operation Timing Diagram

35

MBM29LV160TM/BM90

3rd Bus Cycle

Data Polling

Address

555h

PA

tWC

tAS

tAH

WE

tWS

tWH

OE

tGHEL

tCP

tCPH

tWHWH1

CE

tDS

tDH

A0h

PD

DQ 7

D ^OUT

Data

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates the last two bus cycles out of four bus cycle sequence.

Alternate CE Controlled Program Operation Timing Diagram

36

MBM29LV160TM/BM90

555h

tWC

2AAh

555h

2AAh

SA*

Address

tAS

tAH

CE

tCS

tCH

OE

tWP

tWPH

tGHWL

tTOW

WE

tDS

tDH

10h for Chip Erase

10h/

30h

AAh

55h

80h

AAh

55h

Data

tBUSY

RY/BY

VCC

tVCS

* : SA is the sector address for Sector Erase. Addresses = 555h (Word), AAAh (Byte) for Chip Erase.

Chip/Sector Erase Operation Timing Diagram

37

MBM29LV160TM/BM90

XXXh

tWC

Address

CE

tCS

tCH

tWP

tDS

WE

tSPD

B0h

Data

RY/BY

Erase Suspend Operation Timing Diagram

38

MBM29LV160TM/BM90

VA

Address

CE

tCH

tDF

tOE

OE

tOEH

WE

4

s

tCE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

tWHWH1 or 2

DQ6 to DQ0 =

Output Flag

DQ6 to DQ0

Valid Data

DQ6 to DQ0

RY/BY

tBUSY

tEOE

* : DQ7 = Valid Data (The device has completed the Embedded operation.)

Note : When checking Hardware Sequence Flags during program operations, it should be

checked 4 µs after issuing program command.

Data Polling during Embedded Algorithm Operation Timing Diagram

39

MBM29LV160TM/BM90

Address

tAHT tASO

tAHT tAS

CE

tCEPH

WE

tOEPH

4

s

tOEH

OE

tOE

tCE

tDH

*

Stop

Output

Valid

Toggle

Data

Toggle

Data

Toggle

Data

DQ 6/DQ2

Data

Toggling

tBUSY

RY/BY

* : DQ6 stops toggling (The device has completed the Embedded operation).

Note : When checking Hardware Sequence Flags during program operations, it should be

checked 4 µs after issuing program command.

Toggle Bit l Timing Diagram during Embedded Algorithm Operations

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

WE

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase Suspend

Read

Erase

Complete

DQ⁶

DQ²*

Toggle

and DQ

with OE or CE

DQ

2

6

* : DQ2 is read from the erase-suspended sector.

DQ²vs. DQ⁶

40

MBM29LV160TM/BM90

CE

Rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

tBUSY

RY/BY Timing Diagram during Program/Erase Operation Timing Diagram

CE, OE

tRH

RESET

tRP

tREADY

RESET Timing Diagram (Not during Embedded Algorithms)

41

MBM29LV160TM/BM90

WE

RESET

tRP

tRB

RY/BY

tREADY

RESET Timing Diagram (During Embedded Algorithms)

42

MBM29LV160TM/BM90

A

19 to

A12

SPAX

SPAY

A

6, A

0

A1

V

ID

IH

V

A

9

t

VLHT

V

ID

IH

V

OE

WE

CE

VLHT

t

VLHT

t

VLHT

t

WPP

t

OESP

t

CSP

Data

01h

t

VCS

t

OE

V

CC

SPAX : Sector Address to be protected

SPAY : Next Sector Address to be protected

Sector Protection Timing Diagram

43

MBM29LV160TM/BM90

tVIDR

VCS

t

VCC

t

VLHT

VID

VSS, VIL or VIH

RESET

CE

WE

t

VLHT

t

VLHT

Program or Erase Command Sequence

Unprotection period

RY/BY

Temporary Sector Unprotection Timing Diagram

44

MBM29LV160TM/BM90

VCC

tVCS

RESET

Add

t

VLHT

t

VIDR

SAX

SAY

A6, A0

A1

CE

OE

TIME-OUT

WE

Data

60h

40h

01h

60h

tOE

SPAX

SPAY

: Sector Address to be protected

: Next Sector Address to be protected

TIME-OUT : Time-Out window = 250 µs (Min)

Extended Sector Protection Timing Diagram

45

MBM29LV160TM/BM90

■ FLOW CHART

EMBEDDED ALGORITHMS

Start

Write Program

Command Sequence

(See Below)

Data Polling

Embedded

Program

Algorithm

in progress

No

Verify Data

?

Yes

No

Increment Address

Last Address

?

Yes

Programming Completed

Program Command Sequence (Address/Command):

555h/AAh

2AAh/55h

555h/A0h

Program Address/Program Data

Note : The sequence is applied for Word ( ×16 ) mode.

The addresses differ from Byte ( × 8 ) mode.

Embedded Program^TMAlgorithm

46

MBM29LV160TM/BM90

EMBEDDED ALGORITHMS

Start

Write Erase

Command Sequence

(See Below)

Data Polling

Embedded

Erase

Algorithm

in progress

No

Data = FFh

?

Yes

Erasure Completed

Individual Sector/Multiple Sector

Erase Command Sequence

Chip Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

Sector Address

/30h

Sector Address

/30h

Additional sector

erase commands

are optional.

Sector Address

/30h

Note : The sequence is applied for Word ( ×16 ) mode.

The addresses differ from Byte ( × 8 ) mode.

Embedded Erase^TMAlgorithm

47

MBM29LV160TM/BM90

Start

Wait 4

s

after issuing

Program Command

Read Byte

(DQ ⁷to DQ 0)

Addr. = VA

VA = Valid address for programming

= Any of the sector addresses within

the sector being erased during

sector erase or multiple sector

erases operation

Yes

DQ 7 = Data?

No

= Any of the sector addresses within

the sector not being protected

during chip erase operation

No

DQ 5 = 1?

Yes

Read Byte

(DQ 7 to DQ 0)

Addr. = VA

Yes

DQ 7 = Data?

*

No

Fail

Pass

* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Data Polling Algorithm

48

MBM29LV160TM/BM90

Start

Wait 4

s

after issuing

Program Command

*1

Read DQ7 to DQ0

Addr. = "H" or "L"

*1

Read DQ7 to DQ0

Addr. = "H" or "L"

No

DQ6 = Toggle

?

Yes

No

DQ5 = 1?

Yes

*1, *2

Read DQ7 to DQ0

Addr. = "H" or "L"

Read DQ7 to DQ0

Addr. = "H" or "L"

No

DQ6 = Toggle

?

Yes

Program/Erase

Operation Not

Complete.Write

Reset Command

Program/Erase

Operation

Complete

*1 : Read Toggle bit twice to determine whether it is toggling.

*2 : Recheck Toggle bit because it may stop toggling as DQ⁵changes to “1”.

Toggle Bit Algorithm

49

MBM29LV160TM/BM90

Start

Setup Sector Addr.

(A19 to A12)

PLSCNT = 1

OE = VID, A9 = VID

CE = VIL, RESET = VIH

A6 = A0 = VIL, A1 = VIH

Activate WE Pulse

Increment PLSCNT

Time out 250 µs

WE = VIH, CE = OE = VIL

(A9 should remain VID)

Read from Sector

Addr. = SA, A1 = VIH

(

)

A6 = A0 = VIL

No

PLSCNT = 25?

Yes

No

Data = 01h?

Yes

Protect Another Sector?

No

Yes

Remove VID from A9

Write Reset Command

Remove VID from A9

Write Reset Command

Device Failed

Sector Protection

Completed

Note : A-1 is VIL in Byte ( × 8 ) mode.

Sector Protection Algorithm

50

MBM29LV160TM/BM90

Start

RESET = VID

*1

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector

Unprotection Completed

*2

*1 : All protected sectors are unprotected.

*2 : All previously protected sectors are protected.

Temporary Sector Unprotection Algorithm

51

MBM29LV160TM/BM90

Start

RESET = V^ID

Wait to 4 µs

Device is Operating in

Temporary Sector

Unprotection Mode

No

Extended Sector

Protection Entry?

Yes

To Setup Sector

Protection Write XXXh/60h

PLSCNT = 1

To Protect Sector

Write 60h to Sector Address

(A⁶= A⁰=V^IL, A¹= V^IH)

Time Out 250 µs

Increment PLSCNT

Setup Next Sector

Address

To Verify Sector Protection

Write 40h to Sector Address

(A⁶= A⁰=V^IL, A¹= V^IH)

Read from Sector

Address

(A⁶= A⁰=V^IL, A¹= V^IH

)

No

PLSCNT = 25?

Yes

No

Data = 01h?

Yes

Remove VID from RESET

Write Reset Command

Protection Other Sector?

No

Remove VID from RESET

Write Reset Command

Device Failed

Sector Protection

Completed

Extended Sector Protection Algorithm

52

MBM29LV160TM/BM90

FAST MODE ALGORITHM

Start

555h/AAh

2AAh/55h

555h/20h

XXXh/A0h

Set Fast Mode

Program Address/Program Data

Data Polling

No

In Fast Program

Verify Data?

Yes

No

Last Address

?

Increment Address

Yes

Programming Completed

XXXh/90h

XXXh/F0h

Reset Fast Mode

Notes : • The sequence is applied for Word ( ×16 ) mode.

• The addresses differ from Byte ( × 8 ) mode.

Embedded Program^TMAlgorithm for Fast Mode

53

MBM29LV160TM/BM90

■ ORDERING INFORMATION

Part No.

Package

Access Time (ns)

Remarks

48-pin, plastic TSOP (1)

(FPT-48P-M19)

MBM29LV160TM90TN

(Normal Bend)

90 ns

Top Sector

48-ball, plastic FBGA

(BGA-48P-M20)

MBM29LV160TM90PBT

MBM29LV160BM90TN

MBM29LV160BM90PBT

48-pin, plastic TSOP (1)

(FPT-48P-M19)

(Normal Bend)

90 ns

Bottom Sector

48-ball, plastic FBGA

(BGA-48P-M20)

MBM29LV160TM/BM

90

TN

PACKAGE TYPE

TN = 48-Pin Thin Small Outline Package

(TSOP(1)) Standard Pinout

PBT = 48-Ball Fine Pitch Ball Grid Array

Package (FBGA)

SPEED OPTION

90 = 90 ns access time

DEVICE NUMBER/DESCRIPTION

16 Mega-bit (2M × 8/1M × 16) MirrorFlash,

Boot Sector

3.0 V-only Read, Program, and Erase

54

MBM29LV160TM/BM90

■ PACKAGE DIMENSIONS

Note 1) * : Values do not include resin protrusion.

48-pin plastic TSOP(1)

(FPT-48P-M19)

Resin protrusion and gate protrusion are +0.15(.006)Max(each side).

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

LEAD No.

1

48

INDEX

Details of "A" part

0.25(.010)

0~8˚

0.60±0.15

(.024±.006)

24

25

*

20.00±0.20

(.787±.008)

12.00±0.20

(.472±.008)

*18.40±0.20

(.724±.008)

1.10 –⁺0⁰.^.0¹5⁰

.043 –⁺.^.0⁰0⁰2⁴

(Mounting

height)

0.10±0.05

(.004±.002)

(Stand off height)

0.50(.020)

"A"

0.10(.004)

0.17 ^–⁺⁰⁰^.^.⁰⁰⁸³

0.22±0.05

(.009±.002)

M

0.10(.004)

.007 –⁺.^.0⁰0⁰3¹

C

2003 FUJITSU LIMITED F48029S-c-6-7

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

(Continued)

55

MBM29LV160TM/BM90

(Continued)

48-ball plastic FBGA

(BGA-48P-M20)

8.00±0.20(.315±.008)

1.08 ⁺–0⁰.^.1¹3².043 –⁺.^.0⁰0⁰5³

(Mounting height)

5.60(.220)

0.80(.031)TYP

0.38±0.10(.015±.004)

(Stand off)

6

5

4

3

2

1

6.00±0.20

(.236±.008)

4.00(.157)

H

G

F

E

D

C

B

A

(INDEX AREA)

48-ø0.45±0.05

(48-ø.018±.002)

M

ø0.08(.003)

0.10(.004)

C

2003 FUJITSU LIMITED B48020S-c-2-2

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

56

MBM29LV160TM/BM90

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0312

FUJITSU LIMITED Printed in Japan


型号：	MBM29LV160TM90
厂家：	SPANSION
描述：	FLASH MEMORY CMOS 16 M (2M X 8/1M X 16) BIT MirrorFlashTM FLASH存储器CMOS 16 M（ 2M ×8 / 1M ×16 ）位MirrorFlashTM 存储
文件：	总57页 (文件大小：521K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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