MBM29LV650UE90TR-E1 [SPANSION]
Flash, 4MX16, 90ns, PDSO48, PLASTIC, REVERSE, TSOP1-48;型号: | MBM29LV650UE90TR-E1 |
厂家: | SPANSION |
描述: | Flash, 4MX16, 90ns, PDSO48, PLASTIC, REVERSE, TSOP1-48 光电二极管 |
文件: | 总57页 (文件大小:640K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TM
SPANSION Flash Memory
Data Sheet
September 2003
This document specifies SPANSIONTM memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSIONTM product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSIONTM memory
solutions.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20882-5E
FLASH MEMORY
CMOS
64M (4M × 16) BIT
MBM29LV650UE90
MBM29LV651UE90
■ DESCRIPTION
The MBM29LV650UE/651UE is a 64M-bit, 3.0 V-only Flash memory organized as 4M words of 16 bits each. The
device is designed to be programmed in system with the standard system 3.0 V VCC supply. 12.0 V VPP and
5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard
EPROM programmers.
To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable
(OE) controls.
(Continued)
■ PRODUCT LINE UP
Part No.
MBM29LV650UE90/651UE90
-40°C to +85°C
90 ns
Ambient Temperature
Address Access Time (Max)
Power Supply Voltage
3.3 V ± 0.3 V
58 mW
Operating mode(@5 MHz)
Erase/Programming mode
CMOS Standby mode
Power Consumption (Max)
126 mW
0.018 mW
■ PACKAGES
48-pin plastic TSOP (1)
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
MBM29LV650UE90/651UE90
(Continued)
The MBM29LV650UE/651UE is entirely command set compatible with JEDEC single-power-supply Flash stan-
dard. Commands are written to the command register using standard microprocessor write timings. Register
contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and erase operations.
Typically, each sector can be programmed and verified in about 0.5 seconds.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV650UE/651UE is erased when shipped from the
factory.
Internallygeneratedandregulatedvoltagesareprovidedfortheprogramanderaseoperations. AlowVCC detector
automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data
Polling of DQ7, by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed,
the devices internally reset to the read mode.
The devices electrically erase all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The words
are programmed one word at a time using the EPROM programming mechanism of hot electron injection.
■ FEATURES
• 0.23 µm Process Technology
• Single 3.0 V read, program and erase
Minimizes system level power requirements
• Compatible with JEDEC-standards
Uses same software commands with single-power supply Flash
• Address don’t care during the command sequence
• Industry-standard pinouts
48-pin TSOP (1) (Package suffix: TN - Normal Bend Type, TR - Reversed Bend Type)
• Minimum 100,000 program/erase cycles
• High performance
90 ns maximum access time
• Flexible sector architecture
128 32 K word sectors
Any combination of sectors can be concurrently erased.
Also supports full chip erase.
• HiddenROM region
128 words of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP input pin
At VIL, allows protection of first or last 32 K word sector, regardless of sector protection/unprotection status
At VIH, allows removal of protection
MBM29LV650UE: has the function to protect the last 32 K word sector (SA 127).
MBM29LV651UE: has the function to protect the first 32 K word sector (SA 0).
• ACC input pin
At VACC, increases program performance
• Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded programTM* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
(Continued)
*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
MBM29LV650UE90/651UE90
(Continued)
• Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector protect command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
Temporary sector group unprotection via the RESET pin
This feature allows code changes in previously locked sectors
• In accordance with CFI (Common Flash Memory Interface)
3
MBM29LV650UE90/651UE90
■ PIN ASSIGNMENTS
TSOP(I)
A15
A14
A13
A12
A11
A10
A9
A16
VCCq
VSS
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
(Marking Side)
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
A8
A21
A20
WE
RESET
ACC
WP
A19
A18
A17
A7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MBM29LV650UE/651UE
Normal Bend
A6
A5
A4
A3
A2
A1
VSS
CE
A0
FPT-48P-M19
A1
A2
A3
A4
A5
A0
CE
VSS
OE
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
(Marking Side)
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15
VSS
A6
A7
A17
A18
A19
WP
ACC
RESET
WE
A20
A21
A8
MBM29LV650UE/651UE
Reverse Bend
A9
A10
A11
A12
A13
A14
A15
VCCq
A16
FPT-48P-M20
4
MBM29LV650UE90/651UE90
■ PIN DESCRIPTION
Pin
Function
A0 to A21
DQ0 to DQ15
CE
Address Inputs
Data Inputs/Outputs
Chip Enable
OE
Output Enable
WE
Write Enable
WP
Hardware Write Protection
RESET
ACC
Hardware Reset Pin/Temporary Sector Group Unprotection
Program Acceleration
VCCq
Output Buffer Power
VSS
Device Ground
VCC
Device Power Supply
5
MBM29LV650UE90/651UE90
■ BLOCK DIAGRAM
DQ0 to DQ15
VCC
VSS
Input/Output
Buffers
Erase Voltage
Generator
VCCq
WE
State
Control
RESET
WP
Command
Register
ACC
Program Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
CE
OE
Y-Gating
Y-Decoder
STB
Timer for
Program/Erase
Address
Latch
X-Decoder
Cell Matrix
A0 to A21
6
MBM29LV650UE90/651UE90
■ LOGIC SYMBOL
22
A21 to A0
16
DQ 15 to DQ 0
CE
OE
WE
WP
RESET
ACC
VCCq
7
MBM29LV650UE90/651UE90
■ DEVICE BUS OPERATION
MBM29LV650UE/651UE User Bus Operations Table
Operation
CE OE WE A0
A1
A6
A9 DQ0 to DQ15 RESET WP
Auto-Select Manufacture Code*1
Auto-Select Device Code*1
Read*3
L
L
L
H
L
L
L
L
X
X
X
L
L
H
H
H
X
H
L
L
H
A0
X
X
A0
L
L
L
L
L
VID
VID
A9
X
Code
Code
DOUT
High-Z
High-Z
DIN
H
H
H
H
H
H
H
H
VID
L
X
X
X
X
X
X
X
X
X
X
L
L
A1
X
A6
X
X
A6
L
Standby
X
H
H
VID
L
Output Disable
X
X
Write (Program/Erase)
A1
H
H
X
A9
VID
VID
X
Enable Sector Group Protection*2, *4
Verify Sector Group Protection*2, *4
Temporary Sector Group Unprotection*5
Reset (Hardware)/Standby
Boot Block Sector Write Protection*6
X
H
X
X
X
L
L
Code
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
X
X
X
X
Legend: L = VIL, H = VIH, X = VIL or VIH.
= Pulse input.
*1 : Manufacturer and device codes may also be accessed via a command register write sequence.
*2 : Refer to “Sector Group Protection” in ■ FUNCTIONAL DESCRIPTION.
*3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4 : VCC = + 3.3 V ±10%
*5 : Also used for the extended sector group protection.
*6 : Either side of boot block sector are protected.
8
MBM29LV650UE90/651UE90
MBM29LV650UE/651UE Command Definitions Table
Fourth Bus
Read/Write
Cycle
Bus
Write
First Bus
Second Bus Third Bus
Fifth Bus
Sixth Bus
Command
Sequence
Write Cycle Write Cycle Write Cycle
Write Cycle Write Cycle
Cycles
Req’d
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset*1
Read/Reset*1
Autoselect
1
3
3
4
6
6
1
1
3
2
XXXh F0h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
XXXh AAh XXXh 55h XXXh F0h RA*7 RD*7
IA*7
PA
ID*7
PD
XXXh AAh XXXh 55h XXXh 90h
XXXh AAh XXXh 55h XXXh A0h
Program
Chip Erase
XXXh AAh XXXh 55h XXXh 80h XXXh AAh XXXh 55h XXXh 10h
Sector Erase
Erase Suspend
Erase Resume
Set to Fast Mode
Fast Program *2
XXXh AAh XXXh 55h XXXh 80h XXXh AAh XXXh 55h
SA
—
—
—
—
30h
—
XXXh B0h
XXXh 30h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
XXXh AAh XXXh 55h XXXh 20h
—
XXXh A0h
PA
PD
—
—
—
Reset from Fast
Mode *2
F0h*6
2
XXXh 90h XXXh
—
—
—
—
—
—
—
—
Extended Sector
Group Protection
*
Query *4
4
XXXh 60h SPA
60h
—
SPA 40h SPA*7 SD*7
—
—
—
—
3
1
3
XXh 98h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
HiddenROM Entry
XXXh AAh XXXh 55h XXXh 88h
HiddenROM
Program *5
HiddenROM Exit *5
4
4
XXXh AAh XXXh 55h XXXh A0h
PA
PD
—
—
—
—
—
—
—
—
XXXh AAh XXXh 55h XXXh 90h XXXh 00h
*1: Both of these reset commands are equivalent.
*2: This command is valid during fast mode.
*3: This command is valid while RESET = VID.
*4: The valid addresses are A6 to A0.
*5: This command is valid during HiddenROM mode.
*6: The data “00” is also acceptable.
*7 : The fourth bus cycle is only for read.
Notes : • Address bits = X = “H” or “L” for all address commands except for Program Address (PA) and Sector
Address (SA).
• Bus operations are defined in “User Bus Operations Table”.
• RA = Address of the memory location to be read.
IA = Autoselect read address sets both the bank address specified at (A19, A18, A17, A16, A15) and all the
other A6, A1, A0, (A−1) .
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of
the write pulse.
SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17,A16, and A15 will
uniquely select any sector.
• RD = Data read from location RA during read operation.
ID = Device code/manufacture code for the address located by IA.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
• SPA= Sector group address to be protected. Set sector group address (SA) and (A6, A1, A0) = (0, 1, 0).
SD = Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• Command combinations not described in “MBM29LV650UE/651UE Command Definitions Table” are
illegal.
9
MBM29LV650UE90/651UE90
MBM29LV650UE/651UE Sector Group Protection Verify Autoselect Codes Table
Type
Manufacturer’s Code
A17 to A21
A6
VIL
VIL
A1
VIL
VIL
A0
VIL
VIH
Code (HEX)
04h
X
X
Device Code MBM29LV650UE/651UE
Sector Group Protection
22D7h
Sector Group
Address
VIL
VIL
VIH
VIH
VIL
VIH
01h *
MBM29LV650UE
Extended
0010h
0000h
X
Code
MBM29LV651UE
*: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
Extended Autoselect Code Table
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Type
Code
Manufacturer’s Code
04h
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
Device MBM29LV650UE/
22D7h
Code
651UE
Sector Group Protection 01h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
MBM29LV650UE 0010h
Extend
Code
MBM29LV651UE 0000h
10
MBM29LV650UE90/651UE90
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
Sector Address Table
Sector
Address
Sector Size
(K words)
A21
A20
A19
A18
A17
A16
A15
Address Range
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
000000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
(Continued)
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
11
MBM29LV650UE90/651UE90
Sector
Sector Size
(K words)
A21
A20
A19
A18
A17
A16
A15
Address Range
Address
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
(Continued)
12
MBM29LV650UE90/651UE90
Sector
Sector Size
A21
A20
A19
A18
A17
A16
A15
Address Range
Address
(K words)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
200000h to 207FFFh
208000h to 20FFFFh
210000h to 217FFFh
218000h to 21FFFFh
220000h to 227FFFh
228000h to 22FFFFh
230000h to 237FFFh
238000h to 23FFFFh
240000h to 247FFFh
248000h to 24FFFFh
250000h to 257FFFh
258000h to 25FFFFh
260000h to 267FFFh
268000h to 26FFFFh
270000h to 277FFFh
278000h to 27FFFFh
280000h to 287FFFh
288000h to 28FFFFh
290000h to 297FFFh
298000h to 29FFFFh
2A0000h to 2A7FFFh
2A8000h to 2AFFFFh
2B0000h to 2B7FFFh
2B8000h to 2BFFFFh
2C0000h to 2C7FFFh
2C8000h to 2CFFFFh
2D0000h to 2D7FFFh
2D8000h to 2DFFFFh
2E0000h to 2E7FFFh
2E8000h to 2EFFFFh
2F0000h to 2F7FFFh
2F8000h to 2FFFFFh
(Continued)
13
MBM29LV650UE90/651UE90
(Continued)
Sector
Address
Sector Size
(K words)
A21
A20
A19
A18
A17
A16
A15
Address Range
SA96
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
300000h to 307FFFh
308000h to 30FFFFh
310000h to 317FFFh
318000h to 31FFFFh
320000h to 327FFFh
328000h to 32FFFFh
330000h to 337FFFh
338000h to 33FFFFh
340000h to 347FFFh
348000h to 34FFFFh
350000h to 357FFFh
358000h to 35FFFFh
360000h to 367FFFh
368000h to 36FFFFh
370000h to 377FFFh
378000h to 37FFFFh
380000h to 387FFFh
388000h to 38FFFFh
390000h to 397FFFh
398000h to 39FFFFh
3A0000h to 3A7FFFh
3A8000h to 3AFFFFh
3B0000h to 3B7FFFh
3B8000h to 3BFFFFh
3C0000h to 3C7FFFh
3C8000h to 3CFFFFh
3D0000h to 3D7FFFh
3D8000h to 3DFFFFh
3E0000h to 3E7FFFh
3E8000h to 3EFFFFh
3F0000h to 3F7FFFh
3F8000h to 3FFFFFh
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
14
MBM29LV650UE90/651UE90
Sector Group Address Table
Sector Group
Address
Sector Group Size
(K words)
A21
A20
A19
A18
A17
Sectors
SGA0
SGA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
SA0 to SA3
SA4 to SA7
SGA2
SA8 to SA11
SGA3
SA12 to SA15
SA16 to SA19
SA20 to SA23
SA24 to SA27
SA28 to SA31
SA32 to SA35
SA36 to SA39
SA40 to SA43
SA44 to SA47
SA48 to SA51
SA52 to SA55
SA56 to SA59
SA60 to SA63
SA64 to SA67
SA68 to SA71
SA72 to SA75
SA76 to SA79
SA80 to SA83
SA84 to SA87
SA88 to SA91
SA92 to SA95
SA96 to SA99
SA100 to SA103
SA104 to SA107
SA108 to SA111
SA112 to SA115
SA116 to SA119
SA120 to SA123
SA124 to SA127
SGA4
SGA5
SGA6
SGA7
SGA8
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
SGA25
SGA26
SGA27
SGA28
SGA29
SGA30
SGA31
15
MBM29LV650UE90/651UE90
Common Flash Memory Interface Code Table
Description
A6 to A0 DQ15 toDQ0
Description
A6 to A0 DQ15 to DQ0
Erase Block Region 1 Information
bit 15 to bit 0 : y = number of sectors 2Eh
bit 31 to bit 16 : z = size
(z×256 bytes)
Erase Block Region 2 Information
bit 15 to bit 0 : y = number of sectors 32h
bit 31 to bit 16 : z = size
(z×256 bytes)
2Dh
007Fh
0000h
0000h
0001h
10h
0051h
0052h
0059h
Query-unique ASCII string “QRY” 11h
12h
2Fh
30h
Primary OEM Command Set
02h: AMD/FJ standard type
13h
14h
0002h
0000h
31h
0000h
0000h
0000h
0000h
Address for Primary Extended
Table
15h
16h
0040h
0000h
33h
34h
Alternate OEM Command Set
(00h = not applicable)
17h
18h
0000h
0000h
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
Address for Alternate OEM
Extended Table
19h
1Ah
0000h
0000h
Major version number, ASCII
Minor version number, ASCII
43h
44h
0031h
0031h
VCC Min. (write/erase)
DQ7 to DQ4: 1 V,
DQ3 to DQ0: 100 mV
1Bh
1Ch
0027h
0036h
Address Sensitive Unlock
00h = Required
45h
0001h
VCC Max. (write/erase)
DQ7 to DQ4: 1 V,
DQ3 to DQ0: 100 mV
Erase Suspend
00h = Not supported
01h = To read only
02h = To Read & Write
46h
0002h
VPP Min. voltage
VPP Max. voltage
1Dh
1Eh
0000h
0000h
Sector Protection
00h = Not Supported
X = Number of sectors in per group
Typical timeout per single byte/
word write 2N µs
47h
48h
0004h
0001h
1Fh
20h
21h
22h
23h
24h
25h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
Typical timeout for Min size buffer
write 2N µs
Sector Temporary Unprotection
00h = Not supported
01h = Supported
Typical timeout per individual
sector erase 2N ms
Sector Protection Algorithm
49h
4Ah
0004h
0000h
Number of Sector for Bank 2
00h = Not Supported
Typical timeout for full chip erase
2N ms
Burst Mode Type
00h = Not Supported
Max timeout for byte/word write
2N times typical (µs)
Max timeout for buffer write 2N
times typical (µs)
4Bh
4Ch
0000h
0000h
Page Mode Type
00h = Not Supported
VACC (Acceleration) Supply
Minimum
00h = Not Supported,
DQ7 to DQ4: 1 V,
Max timeout per individual sector
erase 2N times typical (µs)
Max timeout for full chip erase 2N
times typical (ms)
4Dh
00B5h
26h
27h
0000h
0017h
DQ3 to DQ0: 100 mV
Device Size = 2N byte
VACC (Acceleration) Supply
Maximum
00h = Not Supported,
DQ7 to DQ4: 1 V,
Flash Device Interface
description 1h : × 16
28h
29h
0001h
0000h
4Eh
4Fh
00C5h
00XXh
Max number of byte in
multi-byte write = 2N
2Ah
2Bh
0000h
0000h
DQ3 to DQ0: 100 mV
Boot Type
04h = MBM29LV651UE
05h = MBM29LV650UE
Number of Erase Block Regions
within device
2Ch
0001h
16
MBM29LV650UE90/651UE90
■ FUNCTIONAL DESCRIPTION
Read Mode
The MBM29LV650UE/651UE have two control functions required to obtain data at the outputs. CE is the power
control and used for a device selection. OE is the output control and used to gate data to the output pins if a
device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time (tOE) is the delay from the falling edge of OE to valid data at the output pins, assuming the
addresses have been stable for at least tACC-tOE time. When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”.
Standby Mode
There are two ways to implement the standby mode on the MBM29LV650UE/651UE devices, one using both
the CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ±0.3 V.
Under this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC
active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either
of these standby modes.
When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS ±0.3 V (CE =
“H” or “L”). Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is taken high,
the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Automatic Sleep Mode
Automatic sleep mode works to restrain power consumption during read-out of MBM29LV650UE/651UE data.
This is effective with an application requesting low power consumption such as handy terminals.
To activate this mode, MBM29LV650UE/651UE automatically switch themselves to low power mode when
MBM29LV650UE/651UE addresses remain stable during access fine of 150 ns. It is not necessary to control
CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level).
Since the data are latched during this mode, the data are read out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29LV650UE/651UE read out the data for changed addresses.
Output Disable
With the OE input at a logic high level (VIH), output from the devices are disabled. This causes the output pins
to be in a high impedance state.
Autoselect
Autoselect mode allows the reading out of a binary code from the devices and identifies its manufacturer and
type. This mode is intended for use by programming equipment for the purpose of automatically matching the
devices to be programmed with its corresponding programming algorithm.
To activate this mode, the programming equipment must force VID on address pin A9. Two identifier words may
then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON’T
CARES except A0, A1, and A6. (recommend to set VIL for other addresses pins.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29LV650UE/651UE are erased or programmed in a system without access to high voltage on the A9 pin.
The command sequence is illustrated in “MBM29LV650UE/651UE Command Definitions Table” in ■ DEVICE
BUS OPERATION. (Refer to “Autoselect Command” in ■ COMMAND DEFINITIONS.)
Word 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device
identifier code (MBM29LV650UE/651UE = 22D7h). These two words are given in “MBM29LV650UE/651UE
Sector Group Protection Verify Autoselect Codes Table” and “Extended Autoselect Code Table” in ■ DEVICE
BUS OPERATION. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the
parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL.
17
MBM29LV650UE90/651UE90
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever starts later; while data is latched on the rising edge of WE or CE,
whichever starts first. Standard microprocessor write timings are used.
Refer to ■ AC CHARACTERISTICS and ■ TIMING DIAGRAM.
Sector Group Protection
The MBM29LV650UE/651UE feature hardware sector group protection. This feature will disable both program
and erase operations in any combination of 32 sector groups of memory. Each sector group consists of 4
successive sectors. (See “Sector Group Address Table” in ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE).
The sector group protection feature is enabled using programming equipment at the user’s site. The device is
shipped with all sector groups unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, CE =
VIL and A0 = A6 = VIL, A1 = VIH. The sector group addresses (A21, A20, A19, A18, and A17) should be set to the sector
to be protected. “Sector Group Address Table” in ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE defines the
sector address for each of the 32 individual sectors. Programming of the protection circuitry begins on the falling
edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held
constant during the WE pulse. See “(9) Sector Group Protection Timing Diagram” in ■ TIMING DIAGRAM and
“(5) Sector Group Protection Algorithm” in ■FLOW CHART for sector group protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A21, A20, A19, A18, and A17) while
(A6, A1, A0) = (0, 1, 0) will produce a logic “1” code at device output DQ0 for a protected sector. Otherwise the
device will read 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6
are DON’T CARES (recommend to set VIL for other addresses pins). See “MBM29LV650UE/651UE User Bus
Operations Table” and “MBM29LV650UE/651UE Sector Group Protection Verify Autoselect Codes Table” in
■ DEVICE BUS OPERATION for Autoselect codes. It is also possible to determine if a sector group is protected
in the system by writing an Autoselect command. See “Extended Command (3) Extended Sector Group
Protection” in ■ COMMAND DEFINITIONS.
Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the MBM29LV650UE/651UE
devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to
high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting
the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector
groups will be protected again. Refer to “(9) Sector Group Protection Timing Diagram” in ■ TIMING DIAGRAM.
The MBM29LV650UE/651UE also have Extended Sector Group Protection function. See ■ COMMAND
DEFINITIONS.
This temporary sector group unprotect mode is disabled whenever the chip is in the HiddenROM mode. This
area cannot be programmed within this mode. Once this area is programmed, protection is for good.
18
MBM29LV650UE90/651UE90
RESET
Hardware Reset Pin
The MBM29LV650UE/651UE devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode “tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional “tRH” before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted.
Write Protect (WP)
The Write Protection function provides a hardware method of protecting certain “outermost” 32 K word sector
without using VID.
If the system asserts VIL on the WP pin, the device disables program and erase functions in the “outermost”
32 K word sector independently of the protection status of this sector. The outermost 32 K word sector is the
highest addresses in MBM29LV650UE, or the lowest addresses in MBM29LV651UE.
(MBM29LV650UE: SA127, MBM29LV651UE: SA0)
If the system asserts VIH on the WP pin, the device reverts to whether the outermost 32 K word sector was last
set to be protected or unprotected. That is, sector protection or unprotection for this sector depends on whether
this was last protected or unprotected using the method described in “Sector protection/unprotection”.
Accelerated Program Operation
MBM29LV650UE/651UE offer accelerated program operation which enables the programming in high speed. If
the system asserts VACC to the ACC pin, the device automatically enters the acceleration mode and the time
required for program operation will reduce to about 60%. This function is primarily intended to allow high speed
program, so caution is needed as the sector group will temporarily be unprotected.
The system would use a fast program command sequence when programming during acceleration mode. It is
unnecessary to set command to fast mode and to reset command from fast mode. When the device enters the
acceleration mode, the device automatically set to fast mode. Therefore, the present sequence could be used
for programming and detection of completion during acceleration mode.
Removing VACC from the ACC pin returns the device to normal operation. Do not remove VACC from the ACC pin
during programming. Erase operation during Accelerated Program Operation is strictly prohibited.
19
MBM29LV650UE90/651UE90
■ COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect data values or writing them in the improper sequence will reset the devices to the read mode.
The valid register command sequences is defined in “MBM29LV650UE/651UE Command Definitions Table” in
■ DEVICE BUS OPERATION Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are
valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally
equivalent, resetting the device to the read mode. Please note that commands are always written at DQ0 to DQ7
and DQ8 to DQ15 bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits to Read/Reset mode, the Read/Reset
operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The devices remain enabled for reads until the command
register contents are altered.
The devices will automatically power up in the Read/Reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of the memory content occurs during the power transition. Refer to the
■ AC CHARACTERISTICS and ■ TIMING DIAGRAM for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write
cycle that contains the address and the Autoselect command. Then the manufacture and device codes can be
read from the address, and an actual data of memory cell can be read from the another address.
Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read
cycle from address XX01h returns the device code (MBM29LV650UE/651UE = 22D7h). A read cycle from
address XX03h returns the Extended Code (MBM29LV650UE = 0010h, MBM29LV651UE = 0000h). (See
“MBM29LV650UE/651UE Sector Group Protection Verify Autoselect Codes Table” in ■ DEVICE BUS
OPERATION.)
AllmanufactureranddevicecodeswillexhibitoddparitywithDQ7 definedastheparitybit. Sectorstate(protection
or unprotection) will be informed by address XX02h. Scanning the sector group addresses (A21, A20, A19, A18,
and A17) while (A6, A1, A0) = (0, 1, 0) will produce a logic “1” at device output DQ0 for a protected sector group.
The programming verification should be performed by verify sector group protection on the protected sector.
(See “User Bus Operations Table” in ■ DEVICE BUS OPERATION.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
20
MBM29LV650UE90/651UE90
Word Programming
The devices are programmed on a word-by-word basis. Programming is a four bus cycle operation. There are
two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses
are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge
of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins
programming.UponexecutingtheEmbeddedProgramAlgorithmcommandsequence,thesystemisnotrequired
to provide further controls or timings. The device will automatically provide adequate internally generated
program pulses and verify the programmed cell margin.
The system can determine the status of the program operation by using DQ7 (Data Polling), and DQ6 (Toggle
Bit). (See “Write Operation Status”.) The Data Polling and Toggle Bit must be performed at the memory location
which is being programmed.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. Therefore, the
devices require that a valid address to the devices be supplied by the system at this particular instance of time.
Hence, Data Polling must be performed at the memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1” Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0” Only
erase operations can convert “0”s to “1”s.
The Embedded ProgramTM Algorithm using typical command strings and bus operations are illustrated in
“(1) Embedded ProgramTM Algorithm” in ■ FLOW CHART.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all 0
data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls
or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling), and DQ6 (Toggle Bit).
The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence
and terminates when the data on DQ7 is “1” (See “Write Operation Status” section.) at which time the device
returns to read the mode.
Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
The Embedded EraseTM Algorithm using typical command strings and bus operations are illustrated in
“(2) Embedded EraseTM Algorithm” in ■ FLOW CHART.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever
happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first.
Aftertime-outof“tTOW”fromtherisingedgeofthelastsectorerasecommand, thesectoreraseoperationwillbegin.
21
MBM29LV650UE90/651UE90
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29LV650UE/651UE
Command Definitions Table” in ■ DEVICE BUS OPERATION. This sequence is followed with writes of the Sector
Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must
be less than “tTOW” otherwise that command will not be accepted and erasure will start. It is recommended that
processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled
afterthelastSectorErasecommandiswritten. Atime-outof“tTOW”fromtherisingedgeoflastCEorWEwhichever
happens first will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE,
whichever happens first occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine
if the sector erase timer window is still open, see section “DQ3”, Sector Erase Timer.) Any command other than
Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the
previous command string. Resetting the devices once execution has begun will corrupt the data in the sector.
In that case, restart the erase on those sectors and allow them to complete. (Refer to “Write Operation Status”
section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and
with any number of sectors (0 to 127).
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling), and DQ6 (Toggle Bit).
The sector erase begins after the “tTOW” time out from the rising edge of CE or WE whichever happens first for
the last sector erase command pulse and terminates when the data on DQ7 is “1” (See “Write Operation Status”
section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at
an address within any of the sectors being erased.
Multiple Sector Erase Time = [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of Sector
Erase
The Embedded EraseTM Algorithm using typical command strings and bus operations are illustrated
“(2) Embedded EraseTM Algorithm” in ■ FLOW CHART.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
(B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension
of the erase operation.
Writing the Erase Resume command (30h) resumes the erase operation. The addresses are “Don’t Care” when
writting the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of “tSPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the DQ7
bit will be at logic “1” and DQ6 will stop toggling. The user must use the address of the erasing sector for reading
DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend
command are ignored.
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on “DQ2”.)
22
MBM29LV650UE90/651UE90
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
beprogrammedtosectorsthatarenoterase-suspended. Successivelyreadingfromtheerase-suspendedsector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-
suspended Program operation is detected by the Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the
same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can
be read from any address.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Extended Command
(1) Fast Mode
MBM29LV650UE/651UE have Fast Mode function. This mode dispenses with the initial two unclock cycles
requiredinthestandardprogramcommandsequenceby writingFastModecommandintothecommandregister.
In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program
command. (Do not write erase command in this mode.) The read operation is also executed after exiting this
mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer
to “(7) Extended Sector Group Protection Algorithm” in ■ FLOW CHART.) The VCC active current is required
even CE = VIH during Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to
“(7) Extended Sector Group Protection Algorithm” in ■ FLOW CHART.)
(3) Extended Sector Group Protection
In addition to normal sector group protection, the MBM29LV650UE/651UE have Extended Sector Group
Protection as extended function. This function enables to protect sector group by forcing VID on RESET pin and
write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing
for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector
group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up
command (60h) into the command register. Then, the sector group addresses pins (A21, A20, A19, A18, and A17)
and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other
addressespins), andwriteextendedsectorgroupprotectioncommand(60h). Asectorgroupistypicallyprotected
in 250 µs. To verify programming of the protection circuitry, the sector group addresses pins (A21, A20, A19, A18,
and A17) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h). Following the command write, a
logic “1” at device output DQ0 will produce for protected sector in the read operation. If the output data is logical
“0”, please repeat to write extended sector group protection command (60h) again. To terminate the operation,
it is necessary to set RESET pin to VIH. (Refer to “(11) Extended Sector Group Protection Timing Diagram” in
■ TIMING DIAGRAM and “(8) Embedded ProgramTM Algorithm for Fast Mode” in ■ FLOW CHART.)
(4) CFI (Common Flash Memory Interface)
The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation
handshake which allows specific vendor-specified software algorithms to be used for entire families of devices.
This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software
support for the specified flash device families. Refer to CFI specification in detail.
The operation is initiated by writing the query command (98h) into the command register. Following the command
write, a read cycle from specific address retrieves device information. Please note that output data of upper byte
(DQ8 to DQ15) is “0” in word mode (16 bit) read. To terminate operation, it is necessary to write the read/reset
command sequence into the register. (See “Common Flash Memory Interface Code Table” in ■ FLEXIBLE
SECTOR-ERASE ARCHITECTURE.)
23
MBM29LV650UE90/651UE90
HiddenROM Region
The HiddenROM feature provides a Flash memory region that the system may access through a new command
sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the
device with the ESN protected against modification. Once the HiddenROM region is programmed, any further
modification of that region is impossible. This ensures the security of the ESN once the product is shipped to
the field.
The HiddenROM region is 128 words in length. After the system writes the Enter HiddenROM command
sequence, it may read the HiddenROM region by using device addresses A0 to A6 (A7 to A14 are “00”, A15 to A21
are don’t care). That is, the device sends only program command that would normally be sent to the address to
the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command
sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device
reverts to sending commands to the address.
If you request Fujitsu to program the ESN in the device, please contact a Fujitsu representative for more
information.
Write Operation Status
Detailed in “Hardware Sequence Flags” are all the status flags that can be used to check the status of the device
for current mode operation. During sector erase, the part provides the status flags automatically to the I/O ports.
TheinformationonDQ2 isaddresssensitive. Thismeansthatifanaddressfromanerasingsectorisconsecutively
read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is
consecutively read. This allows the user to determine which sectors are erasing and which are not.
Once erase suspend is entered, address sensitivity still applies. If the address of a non-erasing sector (that is,
one available for read) is provided, then stored data can be read from the device. If the address of an erasing
sector (that is, one unavailable for read) is applied, the device will output its status bits.
Hardware Sequence Flags Table
Status
DQ7
DQ7
0
DQ6
DQ5
0
DQ3
0
DQ2
1
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
0
1
Toggle*
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
Data
0
0
Data
0
Toggle
Data
1*
In Progress
Erase
Erase Suspend Read
Suspended
Data
DQ7
Data
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Toggle
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7
0
Toggle
Toggle
1
1
0
1
1
N/A
Exceeded
Time Limits
Erase
Erase Suspend Program
Suspended
DQ7
Toggle
1
0
N/A
(Non-Erase Suspended Sector)
Mode
*: Successive reads from the erasing or erase-suspend sector causes DQ2 to toggle. Reading from non-erase
suspend sector address will indicate logic “1” at the DQ2 bit.
24
MBM29LV650UE90/651UE90
DQ7
Data Polling
The MBM29LV650UE/651UE devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices produce reverse data last written to DQ7. Upon completion of the Embedded Program Algorithm, an
attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm,
an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase
Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7)
is shown in “(3) Data Polling Algorithm” in ■ FLOW CHART.
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid.
Once the Embedded Algorithm operation is close to being completed, the MBM29LV650UE/651UE data pins
(DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the devices
are driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of
time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the
device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to
DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts.
TheDataPollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm,EmbeddedEraseAlgorithm
or sector erase time-out. (See “Hardware Sequence Flags”.)
See “(6) Data Polling during Embedded Algorithm Operation Timing Diagram” in ■ TIMING DIAGRAM for the
Data Polling timing specifications and diagram.
DQ6
Toggle Bit I
The MBM29LV650UE/651UE also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data
from the devices will result in DQ6 toggling between 1 and 0. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, theToggleBitIisvalidaftertherisingedgeofthefourthwritepulseinthefourwritepulsesequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
See “(7) Toggle Bit I during Embedded Algorithm Operation Timing Diagram” in ■ TIMING DIAGRAM for the
Toggle Bit I timing specifications and diagram.
25
MBM29LV650UE90/651UE90
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in “MBM29LV650UE/651UE User
Bus Operations Table” in ■ DEVICE BUS OPERATION.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the
DQ5 bit will indicate a “1”. Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on
the second status check, the command may not have been accepted.
See “Hardware Sequence Flags Table”.
DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress (see“Hardware Sequences Flags”). The behavior of these two status bits, along
with that of DQ7, is summarized as follows:
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.)
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
26
MBM29LV650UE90/651UE90
Toggle Bit Status Table
Mode
DQ7
DQ7
0
DQ6
DQ2
1
Program
Erase
Toggle
Toggle
Toggle *
Erase-Suspend Read
(Erase-Suspended Sector)
1
1
Toggle
1 *
Erase-Suspend Program
DQ7
Toggle
*: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase
suspend sector address will indicate logic “1” at the DQ2 bit.
Data Protection
The MBM29LV650UE/651UE is designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences. The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC
power-up and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
thanVLKO (Min). IfVCC <VLKO,thecommandregisterisdisabledandallinternalprogram/erasecircuitsaredisabled.
Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level
is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent
unintentional writes when VCC is above VLKO (Min).
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE do not initiate write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must
be a logic 0 while OE is a logic 1.
Power-up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to read mode on power-up.
Sector Group Protection
Device user is able to protect each sector group individually to store and protect data. Protection circuit voids
both program and erase commands that are addressed to protected sectors. Any commands to program or
erase addressed to protected sector are ignored (see “Sector Group Protection” in ■ FUNCTIONAL DESCRIP-
TION).
27
MBM29LV650UE90/651UE90
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min
–55
–40
Max
+125
+85
Storage Temperature
Tstg
TA
°C
°C
Ambient Temperature with Power Applied
Voltage with respect to Ground All Pins Except
A9, OE, ACC, and RESET*1, *2
VIN, VOUT
–0.5
VCC +0.5
V
Power Supply Voltage*1
A9, OE, ACC, and RESET*1, *3
Power Supply Voltage*1
VCC
VIN
–0.5
–0.5
–0.2
+4.0
+13.0
+7.0
V
V
V
Vccq
*1 : Voltage is defined on the basis of VSS = GND = 0 V.
*2 : Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns.
*3: Minimum DC input voltage on A9, OE, ACC and RESET pins is –0.5 V. During voltage transitions, A9, OE, ACC
and RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and
supply voltage on (VIN - VCC) dose not exceed +9.0 V. Maximum DC input voltage on A9, OE, ACC and RESET
pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min
–40
Max
+85
Ambient Temperature
TA
°C
V
Power Supply Voltage (VCC)*
Power Supply Voltage (Vccq)*
VCC
+3.0
+3.0
+3.6
+3.6
Vccq
V
*: Voltage is defined on the basis of VSS = GND = 0 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses , operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
28
MBM29LV650UE90/651UE90
■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
20 ns
20 ns
+0.6 V
–0.5 V
–2.0 V
20 ns
Maximum Undershoot Waveform
20 ns
VCC +2.0 V
VCC +0.5 V
+2.0 V
20 ns
20 ns
Maximum Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
VCC +0.5 V
20 ns
20 ns
Note: This waveform is applied for A9, OE, ACC, and RESET.
Maximum Overshoot Waveform 2
29
MBM29LV650UE90/651UE90
■ DC CHARACTERISTICS
Value
Parameter
Symbol
Conditions
Unit
Min
Max
VIN = VSS to VCC, VCC = VCC Max,
VCCq = VCCq Max
Input Leakage Current
Output Leakage Current
ILI
–1.0
+1.0
µA
µA
VOUT = VSS to VCC, VCC = VCC Max,
VCCq = VCCq Max
ILO
ILIT
–1.0
—
+1.0
35
16
7
A9, OE, RESET Inputs Leakage
Current
VCC = VCC Max,
A9, OE, RESET = 12.5 V
µA
CE = VIL, OE = VIH, VCC = VCC Max,
VCCq = VCCq Max, f = 5 MHz
—
mA
mA
mA
VCC Active Current *1
ICC1
CE = VIL, OE = VIH, VCC = VCC Max,
VCCq = VCCq Max, f = 1 MHz
—
CE = VIL, OE = VIH, VCC = VCC Max,
VCCq = VCCq Max
VCC Active Current*2
ICC2
ICC3
ICC4
—
40
VCC = VCC Max, VCCq = VCCq Max,
CE = VCC ±0.3 V,
RESET = VCC ±0.3 V
VCC Current (Standby)
VCC Current (Standby, RESET)
—
—
5
5
µA
µA
VCC = VCC Max, VCCq = VCCq Max,
RESET = VSS ±0.3 V
VCC = VCC Max, VCCq = VCCq Max,
CE = VSS ±0.3 V,
RESET = VCC ±0.3 V,
VCC Current
ICC5
—
—
5
µA
(Automatic Sleep Mode) *5
VIN = VCC ±0.3 V or VSS ±0.3 V
VCC = VCC Max,
ACC = VACC Max
ACC Accelerated Program Current
IACC
20
mA
Input Low Voltage
VIL
VIH
—
—
—
–0.5
2.0
0.6
V
V
V
Input High Voltage
VCC + 0.5
12.5
Voltage for Program Acceleration
VACC
11.5
Voltage for Autoselect, Sector
VID
VOL
—
11.5
—
12.5
0.45
—
V
V
V
Protection (A9, OE, RESET) *3, *4
IOL = 4.0 mA, VCC = VCC Min,
VCCq = VCCq Min
Output Low Voltage
IOH = –2.0 mA, VCC = VCC Min,
VCCq = VCCq Min
VOH1
2.4
Output High Voltage
IOH = –100 µA, VCC Min,
VCCq = VCCq Min
VOH2
VCCq – 0.4
2.3
—
V
V
Low VCC Lock-Out Voltage
VLKO
—
2.5
*1 : The lCC current listed includes both the DC operating current and the frequency dependent component.
*2 : lCC active while Embedded Erase or Embedded Program is in progress.
*3 : This timing is only for Sector Group Protection Operation.
*4 : Applicable for only VCC applying.
*5 : Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
30
MBM29LV650UE90/651UE90
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Symbol
Value*
Parameter
Test Setup
Unit
JEDEC
tAVAV
Standard
Min
Max
Read Cycle Time
tRC
—
90
—
ns
ns
CE = VIL
OE = VIL
Address to Output Delay
tAVQV
tACC
—
90
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
OE = VIL
—
—
—
—
90
35
30
30
ns
ns
ns
ns
—
—
—
Output Hold Time From Address, CE
or OE, Whichever Occurs First
tAXQX
—
tOH
—
—
0
—
ns
RESET Pin Low to Read Mode
tREADY
—
20
µs
* : Test Conditions :
Output Load
: 1 TTL gate and 30 pF (MBM29LV650UE/651UE90)
Input rise and fall times : 5 ns
Input pulse levels
: 0.0 V or 3.0 V
Timing measurement reference level
Input
: 1.5 V
Output : 1.5 V
3.3 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = IN3064
or Equivalent
Note : CL = 30 pF including jig capacitance
Test Conditions
31
MBM29LV650UE90/651UE90
• Write (Erase/Program) Operations
Symbols
JEDEC Standard
Value
Typ
Parameter
Unit
Min
90
0
Max
Write Cycle Time
tAVAV
tAVWL
tWLAX
tDVWH
tWHDX
—
tWC
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
Address Setup Time
Address Hold Time
Data Setup Time
tAH
45
35
0
tDS
Data Hold Time
tDH
tOES
Output Enable Setup Time
0
Read
Toggle and Data Polling
0
Output Enable Hold
Time
—
tOEH
10
0
Read Recover Time Before Write
Read Recover Time Before Write
CE Setup Time
tGHWL
tGHEL
tELWL
tWLEL
tWHEH
tEHWH
tWLWH
tELEH
tWHWL
tEHEL
tWHWH1
tWHWH2
—
tGHWL
tGHEL
tCS
0
0
WE Setup Time
tWS
0
CE Hold Time
tCH
0
WE Hold Time
tWH
0
Write Pulse Width
tWP
35
35
30
30
CE Pulse Width
tCP
Write Pulse Width High
CE Pulse Width High
tWPH
tCPH
tWHWH1
tWHWH2
tVCS
tVIDR
tVACCR
tVLHT
tWPP
tOESP
tCSP
tRP
Programming Operation
Sector Erase Operation *1
VCC Setup Time
16
1
50
500
500
4
µs
ns
ns
µs
µs
µs
µs
ns
ns
ns
µs
µs
Rise Time to VID *2
—
Rise Time to VACC *3
Voltage Transition Time *2
Write Pulse Width *2
OE Setup Time to WE Active *2
CE Setup Time to WE Active *2
RESET Pulse Width
—
—
—
100
4
—
—
4
—
500
200
RESET High Level Period Before Read
Delay Time from Embedded Output Enable
Erase Time-out Time
—
tRH
—
tEOE
tTOW
tSPD
90
20
—
50
Erase Suspend Transition Time
—
*1 : This does not include the preprogramming time.
*2 : This timing is for Sector Group Protection operation.
*3 : This timing is for Accelerated Program operation.
32
MBM29LV650UE90/651UE90
■ ERASE AND PROGRAMMING PERFORMANCE
Limit
Typ
Parameter
Unit
Comments
Min
Max
Excludes programming time
prior to erasure
Sector Erase Time
—
1
10
s
Excludes system-level
overhead
Programming Time
—
16
360
µs
Excludes system-level
overhead
Chip Programming Time
Erase/Program Cycle
—
—
—
200
—
s
100,000
cycle
■ PIN CAPACITANCE
Value
Unit
Parameter
Symbol
Test Setup
Typ
Max
Input Capacitance
CIN
COUT
CIN2
CIN3
VIN = 0
VOUT = 0
VIN = 0
VIN = 0
6
8.5
8
7.5
12
10
20
pF
pF
pF
pF
Output Capacitance
Control Pin Capacitance
ACC Pin Capacitance
15
Note: Test conditions TA = + 25°C, f = 1.0 MHz
33
MBM29LV650UE90/651UE90
■ TIMING DIAGRAM
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
“H” or “L”
Any Change
Permitted
Changing
State
Unknown
Does Not
Apply
Center Line is
High-
Impedance
“Off” State
(1) Read Operation Timing Diagram
tRC
Address
Address Stable
tACC
CE
OE
tOE
tDF
tOEH
WE
tCE
tOH
High-Z
High-Z
Outputs
Output Valid
34
MBM29LV650UE90/651UE90
(2) Hardware Reset/Read Operation Timing Diagram
tRC
Address
Address Stable
tACC
CE
tRH
tRP
tRH
tCE
RESET
Outputs
tOH
High-Z
Output Valid
35
MBM29LV650UE90/651UE90
(3) Alternate WE Controlled Program Operation Timing Diagram
Data Polling
3rd Bus Cycle
Address
XXXh
PA
PA
tWC
tRC
tAS
tAH
CE
tCH
tCS
tCE
OE
tWP
tWPH
tOE
tGHWL
tWHWH1
WE
tDF
tOH
tDS
tDH
A0h
PD
DQ 7
DOUT
DOUT
Data
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates the last two bus cycles out of four bus cycle sequence.
36
MBM29LV650UE90/651UE90
(4) Alternate CE Controlled Program Operation Timing Diagram
3rd Bus Cycle
Data Polling
Address
WE
PA
XXXh
PA
tWC
tAS
tAH
tWS
tWH
OE
CE
tGHEL
tCP
tCPH
tWHWH1
tDS
tDH
A0h
PD
DQ 7
DOUT
Data
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates the last the two bus cycles out of four bus cycle sequence.
37
MBM29LV650UE90/651UE90
(5) Chip/Sector Erase Operation Timing Diagram
XXXh
XXXh
XXXh
Address
XXXh
XXXh
SA *
tWC
tAS
tAH
CE
tCS
tCH
OE
tWP
tWPH
tGHWL
WE
tDS
tDH
10h for chip erase
30h
AAh
55h
80h
AAh
55h
Data
tVCS
VCC
* : SA is the sector address for Sector Erase. Addresses = XXXh for Chip Erase.
38
MBM29LV650UE90/651UE90
(6) Data Polling during Embedded Algorithm Operation Timing Diagram
CE
tCH
tOE
tDF
OE
tOEH
WE
tCE
*
High-Z
High-Z
DQ7 =
Data
Data
DQ7
DQ7
Valid Data
tWHWH1 or tWHWH2
DQ0 to DQ6
Valid Data
DQ0 to DQ6
DQ0 to DQ6 = Output Flag
tEOE
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
(7) Toggle Bit I during Embedded Algorithm Operation Timing Diagram
CE
tOEH
WE
tOES
OE
tDH
*
DQ6 =
Stop Toggling
DQ0 to DQ7
Data Valid
DQ6 = Toggle
DQ6 = Toggle
Data (DQ0 to DQ7)
DQ6
tOE
* : DQ6 = Stops toggling. (The device has completed the Embedded operation.)
39
MBM29LV650UE90/651UE90
(8) DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
WE
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE or CE
Note: DQ2 is read from the erase-suspended sector.
40
MBM29LV650UE90/651UE90
(9) Sector Group Protection Timing Diagram
A21, A20, A19
SPAX
SPAY
A18, A17
A6, A0
A1
12 V
3 V
A9
tVLHT
12 V
3 V
OE
tVLHT
tVLHT
tVLHT
tWPP
WE
tOESP
tCSP
CE
Data
01h
tVCS
tOE
VCC
SPAX : Sector Group Address to be protected
SPAY : Next Sector Group Address to be protected
41
MBM29LV650UE90/651UE90
(10) Temporary Sector Group Unprotection Timing Diagram
VCC
tVIDR
tVCS
tVLHT
VID
VIH
RESET
CE
WE
tVLHT
tVLHT
Program or Erase Command Sequence
Unprotection period
42
MBM29LV650UE90/651UE90
(11) Extended Sector Group Protection Timing Diagram
VCC
tVCS
tVLHT
RESET
tVIDR
tWC
tWC
SPAX
SPAX
SPAY
Address
A6, A3,
A2, A0
A1
CE
OE
TIME-OUT
tWP
WE
Data
60h
60h
40h
01h
60h
tOE
SPAX: Sector Group Address to be protected
SPAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
43
MBM29LV650UE90/651UE90
(12) Accelerated Program Timing Diagram
VCC
tVACCR
tVCS
tVLHT
VACC
VIH
ACC
CE
WE
tVLHT
tVLHT
Program Command Sequence
Acceleration period
44
MBM29LV650UE90/651UE90
■ FLOW CHART
1. Embedded ProgramTM Algorithm
EMBEDDED ALGORITHMS
Start
Write Program Command
Sequence
(See below)
Data Polling
Embeded
Program
Algorithm
in progress
No
Verify Data
?
Yes
No
Last Address
?
Increment Address
Yes
Programming Completed
Program Command Sequence (Address/Command):
XXXh/AAh
XXXh/55h
XXXh/A0h
Program Address/Program Data
45
MBM29LV650UE90/651UE90
2. Embedded EraseTM Algorithm
EMBEDDED ALGORITHMS
Start
Write Erase Command
Sequence
(See below)
Data Polling
Embeded
Program
Algorithm
in progress
No
Data=FFh
?
Yes
Erasure Completed
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
Chip Erase Command Sequence
(Address/Command):
XXXh/AAh
XXXh/55h
XXXh/80h
XXXh/AAh
XXXh/55h
XXXh/10h
XXXh/AAh
XXXh/55h
XXXh/80h
XXXh/AAh
XXXh/55h
Sector Address/30h
Sector Address/30h
Additional sector
erase commands
are optional.
Sector Address/30h
46
MBM29LV650UE90/651UE90
3. Data Polling Algorithm
Start
Read Byte
(DQ 7 to DQ 0)
Addr. = VA
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during
Yes
sector erase or multiple sector
erases operation
= Any of the sector addresses within
the sector not being protected
during chip erase
DQ 7 = Data?
No
No
DQ 5 = 1?
Yes
Read Byte
(DQ 7 to DQ 0)
Addr. = VA
Yes
DQ 7 = Data?
*
No
Fail
Pass
* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
47
MBM29LV650UE90/651UE90
4. Toggle Bit Algorithm
Start
Read
(DQ 7 to DQ 0 )
Addr. = "H" or "L"
*1
Read
(DQ 7 to DQ 0 )
Addr. = "H" or "L"
DQ 6
= Toggle
?
No
Yes
No
DQ 5 = 1?
Yes
*1,*2
Read DQ 7 to DQ 0
Twice
Addr. = "H" or "L"
No
DQ 6
= Toggle
?
Yes
Program/Erase
Operation Not
Complete.Write
Reset Command
Program/Erase
Operation Complete
*1:Reset toggle bit twice to determine whether it is toggling.
*2:Recheck toggle bit because it may stop toggling as DQ5 changes to “1” .
48
MBM29LV650UE90/651UE90
5. Sector Group Protection Algorithm
Start
Setup Sector Group Addr.
(A21, A20, A19, A18, A17)
PLSCNT = 1
OE
=
V ID, A 9
V IL, RESET
A 0 V IL, A 1
= V ID,
CE
=
=
=
=
V IH
V IH
A 6
=
Activate WE Pulse
Time out 100 µs
Increment PLSCNT
WE = V IH, CE = OE = V IL
(A 9 should remain V ID)
Read from Sector Group
(Addr. = SPA, A 1
=
V IH,
)
A 6 A0 = V IL
=
No
No
PLSCNT = 25?
Yes
Data = 01h?
Yes
Yes
Remove V ID from A
Write Reset Command
9
Protect Another Sector
Group ?
No
Device Failed
Remove V ID from A
9
Write Reset Command
Sector Group Protection
Completed
49
MBM29LV650UE90/651UE90
6. Temporary Sector Group Unprotection Algorithm
Start
RESET = VID
* 1
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector Group
Unprotection Completed
* 2
*1: All protected sector groups are unprotected.
*2: All previously protected sector groups are protected once again.
50
MBM29LV650UE90/651UE90
7. Extended Sector Group Protection Algorithm
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector Group
Unprotection Mode
No
Extended Sector Group
Protection Entry?
Yes
To Setup Sector Group
Protection Write XXXh/60h
PLSCNT = 1
To Sector Group Protection
Write SPA/60h
(A6 = A0 = VIL, Addr. = SPA,
A1 = VIH)
Time Out 250 µs
Increment PLSCNT
Setup Next Sector Group
To Verify Sector Group
Address
Protection Write SPA/40h
(A6 = A0 = VIL, A1 = VIH)
Read from Sector Group
Address
(A6 = A0 = VIL, Addr. = SPA,
A1 = VIH)
No
PLSCNT = 25?
Yes
No
Data = 01h?
Yes
Yes
Remove VID from RESET
Write Reset Command
Protection Other Sector
Group?
No
Remove VID from RESET
Write Reset Command
Device Failed
Sector Group Protection
Completed
51
MBM29LV650UE90/651UE90
8. Embedded ProgramTM Algorithm for Fast Mode
FAST MODE ALGORITHM
Start
XXXh/AAh
XXXh/55h
XXXh/20h
XXXh/A0h
Set Fast Mode
Program Address/Program Data
Data Polling Device
No
In Fast Program
Verify Data?
Yes
No
Last Address
?
Increment Address
Yes
Programming Completed
XXXh/90h
XXXh/F0h
Reset Fast Mode
52
MBM29LV650UE90/651UE90
■ ORDERING INFORMATION
MBM29LV650U(651U)
E
90 TN
PACKAGE TYPE
TN= 48-Pin Thin Small Outline Package
(TSOP) Normal Bend
TR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Bend
SPEED OPTION
See Product Selector Guide
DEVICE REVISION
DEVICE NUMBER/DESCRIPTION
MBM29LV650U(651U)
64 Mega-bit (4M × 16-Bit)
3.0 V-only Read, Program and Erase
Part No.
Package
Access Time (ns)
Remarks
48-pin plastic TSOP (1)
MBM29LV650UE90TN
MBM29LV650UE90TR
MBM29LV651UE90TN
MBM29LV651UE90TR
(FPT-48P-M19)
Normal Bend
90
Hardware protection
with WP = SA127
48-pin plastic TSOP (1)
(FPT-48P-M20)
90
90
90
Reverse Bend
48-pin plastic TSOP (1)
(FPT-48P-M19)
Normal Bend
Hardware protection
with WP = SA0
48-pin plastic TSOP (1)
(FPT-48P-M20)
Reverse Bend
53
MBM29LV650UE90/651UE90
■ PACKAGE DIMENSIONS
Note 1) * : Values do not include resin protrusion.
48-pin plastic TSOP (1)
(FPT-48P-M19)
Resin protrusion and gate protrusion are +0.15(.006)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.
LEAD No.
1
48
INDEX
Details of "A" part
0.25(.010)
0~8˚
0.60±0.15
(.024±.006)
24
25
*
20.00±0.20
(.787±.008)
12.00±0.20
(.472±.008)
*18.40±0.20
(.724±.008)
1.10 –+00..0150
.043 –+..000024
(Mounting
height)
0.10±0.05
(.004±.002)
(Stand off height)
0.50(.020)
"A"
0.10(.004)
0.17 –+00..0083
0.22±0.05
(.009±.002)
M
0.10(.004)
.007 –+..000031
C
2003 FUJITSU LIMITED F48029S-c-6-7
Dimensions in mm (inches)
(Continued)
54
MBM29LV650UE90/651UE90
(Continued)
Note 1) * : Values do not include resin protrusion.
48-pin plastic TSOP (1)
(FPT-48P-M20)
Resin protrusion and gate protrusion are +0.15(.006)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
LEAD No.
1
48
Details of "A" part
INDEX
0.60±0.15
(.024±.006)
0~8˚
0.25(.010)
24
25
0.17 –+00..0083
.007 –+..000031
0.22±0.05
(.009±.002)
M
0.10(.004)
0.10±0.05
(.004±.002)
0.50(.020)
0.10(.004)
(Stand off height)
1.10 +–00..0150
"A"
* 18.40±0.20
(.724±.008)
.043 +–..000024
(Mounting height)
20.00±0.20
(.787±.008)
* 12.00±0.20(.472±.008)
C
2003 FUJITSU LIMITED F48030S-c-6-7
Dimensions in mm (inches)
(Continued)
55
MBM29LV650UE90/651UE90
FUJITSU LIMITED
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circuit examples, in this document are presented solely for the
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F0303
FUJITSU LIMITED Printed in Japan
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