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MBM29LV800TA-12PBT-SF2-E1 [SPANSION]

Flash, 512KX16, 120ns, PBGA48, PLASTIC, FBGA-48;
MBM29LV800TA-12PBT-SF2-E1
型号： MBM29LV800TA-12PBT-SF2-E1
厂家： SPANSION    SPANSION
描述：

Flash, 512KX16, 120ns, PBGA48, PLASTIC, FBGA-48

内存集成电路
文件： 总59页 (文件大小：608K)
中文：  中文翻译
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FUJITSU SEMICONDUCTOR  
DATA SHEET  
DS05-20845-4E  
FLASH MEMORY  
CMOS  
8M (1M × 8/512K × 16) BIT  
MBM29LV800TA-70/90/-12/MBM29LV800BA-70/-90/-12  
■ FEATURES  
• Single 3.0 V read, program, and erase  
Minimizes system level power requirements  
• Compatible with JEDEC-standard commands  
Uses same software commands as E2PROMs  
• Compatible with JEDEC-standard world-wide pinouts  
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)  
44-pin SOP (Package suffix: PF)  
48-ball FBGA (Package suffix: PBT)  
• Minimum 100,000 program/erase cycles  
• High performance  
70 ns maximum access time  
• Sector erase architecture  
One 8K word, two 4K words, one 16K word, and fifteen 32K words sectors in word mode  
One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes sectors in byte mode  
Any combination of sectors can be concurrently erased. Also supports full chip erase  
• Boot Code Sector Architecture  
T = Top sector  
B = Bottom sector  
• Embedded EraseTM Algorithms  
Automatically pre-programs and erases the chip or any sector  
• Embedded ProgramTM Algorithms  
Automatically writes and verifies data at specified address  
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion  
• Ready/Busy output (RY/BY)  
Hardware method for detection of program or erase cycle completion  
• Automatic sleep mode  
When addresses remain stable, automatically switch themselves to low power mode  
• Low VCC write inhibit ≤ 2.5 V  
• Erase Suspend/Resume  
Suspends the erase operation to allow a read in another sector within the same device  
(Continued)  
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
(Continued)  
• Sector protection  
Hardware method disables any combination of sectors from program or erase operations  
• Sector Protection set function by Extended sector Protect command  
• Temporary sector unprotection  
Temporary sector unprotection via the RESET pin  
■ PACKAGE  
48-pin Plastic TSOP (I)  
48-pin Plastic TSOP (I)  
Marking Side  
Marking Side  
(FPT-48P-M19)  
(FPT-48P-M20)  
44-pin Plastic SOP  
48-pin Plastic FBGA  
Marking Side  
(FPT-44P-M16)  
(BGA-48P-M02)  
(BGA-48P-M12)  
2
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ GENERAL DESCRIPTION  
The MBM29LV800TA/BA are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K  
words of 16 bits each. The MBM29LV800TA/BA are offered in a 48-pin TSOP(I), 44-pin SOP, and 48-ball FBGA  
packages. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply.  
12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed  
in standard EPROM programmers.  
The standard MBM29LV800TA/BA offer access times 70 ns and 120 ns, allowing operation of high-speed  
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),  
write enable (WE), and output enable (OE) controls.  
The MBM29LV800TA/BA are pin and command set compatible with JEDEC standard E2PROMs. Commands  
are written to the command register using standard microprocessor write timings. Register contents serve as  
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally  
latch addresses and data needed for the programming and erase operations. Reading data out of the devices  
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.  
The MBM29LV800TA/BA are programmed by executing the program command sequence. This will invoke the  
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths  
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.  
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase  
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed  
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and  
verify proper cell margin.  
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)  
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and  
reprogrammed without affecting other sectors. The MBM29LV800TA/BA are erased when shipped from the  
factory.  
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated  
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically  
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,  
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been  
completed, the devices internally reset to the read mode.  
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels  
of quality, reliability, and cost effectiveness. The MBM29LV800TA/BA memories electrically erase the entire chip  
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one  
byte/word at a time using the EPROM programming mechanism of hot electron injection.  
3
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE  
• One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes  
• Individual-sector, multiple-sector, or bulk-erase capability  
• Individual or multiple-sector protection is user definable.  
(×8)  
(×16)  
(×8)  
(×16)  
FFFFFH 7FFFFH  
FBFFFH 7DFFFH  
F9FFFH 7CFFFH  
F7FFFH 7BFFFH  
EFFFFH 77FFFH  
DFFFFH 6FFFFH  
CFFFFH 67FFFH  
BFFFFH 5FFFFH  
AFFFFH 57FFFH  
9FFFFH 4FFFFH  
8FFFFH 47FFFH  
7FFFFH 3FFFFH  
6FFFFH 37FFFH  
5FFFFH 2FFFFH  
4FFFFH 27FFFH  
3FFFFH 1FFFFH  
2FFFFH 17FFFH  
1FFFFH 0FFFFH  
0FFFFH 07FFFH  
00000H 00000H  
FFFFFH 7FFFFH  
EFFFFH 77FFFH  
DFFFFH 6FFFFH  
CFFFFH 67FFFH  
BFFFFH 5FFFFH  
AFFFFH 57FFFH  
9FFFFH 4FFFFH  
8FFFFH 47FFFH  
7FFFFH 3FFFFH  
6FFFFH 37FFFH  
5FFFFH 2FFFFH  
4FFFFH 27FFFH  
3FFFFH 1FFFFH  
2FFFFH 17FFFH  
1FFFFH 0FFFFH  
0FFFFH 07FFFH  
07FFFH 03FFFH  
05FFFH 02FFFH  
03FFFH 01FFFH  
00000H 00000H  
16K byte  
8K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
32K byte  
8K byte  
8K byte  
32K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
64K byte  
8K byte  
16K byte  
MBM29LV800TA Sector Architecture  
MBM29LV800BA Sector Architecture  
4
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ PRODUCT LINE UP  
Part No.  
VCC = 3.3 V  
MBM29LV800TA/MBM29LV800BA  
+0.3 V  
–0.3 V  
-70  
—
—
Ordering Part No.  
+0.6 V  
–0.3 V  
VCC = 3.0 V  
—
70  
70  
30  
-90  
90  
90  
35  
-12  
120  
120  
50  
Max. Address Access Time (ns)  
Max. CE Access Time (ns)  
Max. OE Access Time (ns)  
■ BLOCK DIAGRAM  
DQ 0 to DQ 15  
RY/BY  
Buffer  
RY/BY  
V CC  
V SS  
Erase Voltage  
Generator  
Input/Output  
Buffers  
WE  
State  
Control  
BYTE  
RESET  
Command  
Register  
Program Voltage  
Generator  
Chip Enable  
Output Enable  
Logic  
STB  
Data Latch  
CE  
OE  
Y-Decoder  
Y-Gating  
STB  
Timer for  
Program/Erase  
Address  
Latch  
Low V CC Detector  
X-Decoder  
Cell Matrix  
A0 to A18  
A-1  
5
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ CONNECTION DIAGRAMS  
SOP  
TSOP(I)  
(Top View)  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A16  
BYTE  
VSS  
1
2
3
4
5
6
7
8
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
(Marking Side)  
RY/BY  
A18  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
RESET  
WE  
2
DQ 15/A-1  
DQ7  
DQ14  
DQ6  
DQ13  
DQ5  
DQ12  
DQ4  
VCC  
DQ11  
DQ3  
DQ10  
DQ2  
DQ9  
DQ1  
DQ8  
DQ0  
OE  
A17  
3
A8  
A7  
4
A9  
N.C.  
N.C.  
WE  
RESET  
N.C.  
N.C.  
RY/BY  
A18  
9
A6  
5
A10  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
A5  
6
A11  
MBM29LV800TA/MBM29LV800BA  
Standard Pinout  
A4  
7
A12  
A3  
8
A13  
A2  
9
A14  
A17  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
A15  
A0  
A16  
VSS  
CE  
A0  
CE  
BYTE  
V SS  
VSS  
OE  
DQ0  
DQ8  
DQ1  
DQ9  
DQ2  
DQ10  
DQ3  
DQ11  
FPT-48P-M19  
DQ 15/A-1  
DQ 7  
DQ 14  
DQ 6  
DQ 13  
DQ5  
DQ 12  
DQ4  
VCC  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A17  
A18  
A0  
CE  
VSS  
OE  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
(Marking Side)  
DQ0  
DQ8  
DQ1  
DQ9  
DQ2  
DQ10  
DQ3  
DQ11  
VCC  
DQ4  
DQ12  
DQ5  
DQ13  
DQ6  
DQ14  
DQ7  
DQ15/A-1  
VSS  
RY/BY  
N.C.  
N.C.  
RESET  
WE  
N.C.  
N.C.  
A8  
MBM29LV800TA/MBM29LV800BA  
Reverse Pinout  
FPT-44P-M16  
A9  
A10  
A11  
A12  
A13  
A14  
A15  
BYTE  
A16  
FPT-48P-M20  
6
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
(Continued)  
FBGA  
(Top View)  
Marking side  
A1  
B1  
C1  
D1  
E1  
F1  
G1  
H1  
A2  
B2  
C2  
A3  
B3  
C3  
A4  
B4  
C4  
A5  
B5  
C5  
A6  
B6  
C6  
D2  
E2  
F2  
G2  
H2  
D3  
E3  
F3  
G3  
H3  
D4  
E4  
F4  
G4  
H4  
D5  
E5  
F5  
G5  
H5  
D6  
E6  
F6  
G6  
H6  
BGA-48P-M02  
BGA-48P-M12  
A1  
B1  
C1  
D1  
E1  
F1  
G1  
H1  
A3  
A2  
B2  
C2  
D2  
E2  
F2  
G2  
H2  
A7  
A3  
B3  
C3  
D3  
E3  
F3  
G3  
H3  
RY/BY  
N.C.  
A18  
A4  
B4  
C4  
D4  
E4  
F4  
G4  
H4  
WE  
A5  
A9  
A6  
B6  
C6  
D6  
E6  
F6  
G6  
H6  
A13  
A4  
A17  
A6  
RESET B5  
A8  
A12  
A2  
N.C.  
N.C.  
DQ5  
DQ12  
VCC  
C5  
D5  
E5  
F5  
G5  
H5  
A10  
A14  
A1  
A5  
N.C.  
DQ2  
A11  
A15  
A0  
DQ0  
DQ8  
DQ9  
DQ1  
DQ7  
DQ14  
DQ13  
DQ6  
A16  
CE  
OE  
VSS  
DQ10  
DQ11  
DQ3  
BYTE  
DQ15/A-1  
VSS  
DQ4  
7
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ LOGIC SYMBOL  
Table 1 MBM29LV800TA/800BA Pin Configuration  
Pin  
A-1, A0 to A18  
DQ0 to DQ15  
CE  
Function  
A-1  
Address Inputs  
Data Inputs/Outputs  
Chip Enable  
19  
A0 to A18  
16 or 8  
DQ 0 to DQ 15  
OE  
Output Enable  
CE  
WE  
Write Enable  
OE  
RY/BY  
Ready/Busy Output  
WE  
RESET  
BYTE  
RY/BY  
Hardware Reset Pin/Temporary Sector  
Unprotection  
RESET  
BYTE  
N.C.  
VSS  
Selects 8-bit or 16-bit mode  
No Internal Connection  
Device Ground  
VCC  
Device Power Supply  
Table 2 MBM29LV800TA/800BA User Bus Operations (BYTE = VIH)  
Operation  
CE OE WE  
A0  
L
A1  
L
A6  
L
A9  
VID  
VID  
A9  
X
DQ0 to DQ15 RESET  
Auto-Select Manufacturer Code (1)  
Auto-Select Device Code (1)  
Read (3)  
L
L
L
H
L
L
L
L
X
X
L
L
H
H
H
X
H
L
Code  
Code  
DOUT  
H
H
H
H
H
H
H
H
VID  
L
H
A0  
X
L
L
L
A1  
X
A6  
X
X
A6  
L
Standby  
X
H
H
VID  
L
HIGH-Z  
HIGH-Z  
DIN  
Output Disable  
X
X
X
Write (Program/Erase)  
Enable Sector Protection (2), (4)  
Verify Sector Protection (2), (4)  
Temporary Sector Unprotection  
Reset (Hardware)/Standby  
A0  
L
A1  
H
H
X
A9  
VID  
VID  
X
X
H
X
X
L
L
Code  
X
X
X
X
X
X
X
X
X
HIGH-Z  
8
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Table 3 MBM29LV800TA/800BA User Bus Operations (BYTE = VIL)  
DQ15/  
Operation  
CE  
OE WE  
A0  
A1  
A6  
A9 DQ0 to DQ7 RESET  
A-1  
Auto-Select Manufacturer Code (1)  
Auto-Select Device Code (1)  
Read (3)  
L
L
L
H
L
L
L
L
X
X
L
L
H
H
H
X
H
L
L
L
H
A0  
X
X
A0  
L
L
L
L
L
VID  
VID  
A9  
X
Code  
Code  
DOUT  
H
H
H
H
H
H
H
H
VID  
L
L
L
A-1  
X
A1  
X
A6  
X
X
A6  
L
Standby  
X
H
H
VID  
L
HIGH-Z  
HIGH-Z  
DIN  
Output Disable  
X
X
X
Write (Program/Erase)  
Enable Sector Protection (2), (4)  
Verify Sector Protection (2), (4)  
Temporary Sector Unprotection (5)  
Reset (Hardware)/Standby  
A-1  
L
A1  
H
H
X
A9  
VID  
VID  
X
X
H
X
X
L
L
L
Code  
X
X
X
X
X
X
X
X
X
X
X
HIGH-Z  
Legend: L = VIL, H = VIH, X = VIL or VIH,  
= Pulse input. See DC Characteristics for voltage levels.  
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See  
Table 7.  
2. Refer to the section on Sector Protection.  
3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.  
4. VCC = 3.3 V ± 10%  
5. It is also used for the extended sector protection.  
9
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ ORDERING INFORMATION  
Standard Products  
Fujitsu standard products are available in several packages. The order number is formed by a combination of:  
MBM29LV800  
T
A
-70  
PFTN  
PACKAGE TYPE  
PFTN = 48-Pin Thin Small Outline Package  
(TSOP) Standard Pinout  
PFTR = 48-Pin Thin Small Outline Package  
(TSOP) Reverse Pinout  
PF =  
PBT =  
44-Pin Small Outline Package  
48-Ball Fine Pitch Ball Grid Array  
Package (FBGA:BGA-48P-M02)  
PBT-SF2 =48-Ball Fine Pitch Ball Grid Array  
Package (FBGA:BGA-48P-M12)  
SPEED OPTION  
See Product Selector Guide  
Device Revision  
BOOT CODE SECTOR ARCHITECTURE  
T = Top sector  
B = Bottom sector  
DEVICE NUMBER/DESCRIPTION  
MBM29LV800  
8Mega-bit (1M × 8-Bit or 512K × 16-Bit) CMOS Flash Memory  
3.0 V-only Read, Program, and Erase  
10  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ FUNCTIONAL DESCRIPTION  
Read Mode  
The MBM29LV800TA/BA have two control functions which must be satisfied in order to obtain data at the outputs.  
CE is the power control and should be used for a device selection. OE is the output control and should be used  
to gate data to the output pins if a device is selected.  
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable  
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output  
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the  
addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after  
power-up, it is necessary to input hardware reset or change CE pin from “H” or “L”  
Standby Mode  
There are two ways to implement the standby mode on the MBM29LV800TA/BA devices, one using both the CE  
and RESET pins; the other via the RESET pin only.  
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.  
Under this condition the current consumed is less than 5 µA. The device can be read with standard access time  
(tCE) from either of these standby modes. During Embedded Algorithm operation, VCC active current (ICC2) is  
required even CE = “H”.  
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V  
(CE = “H” or “L”). Under this condition the current is consumed is less than 5 µA. Once the RESET pin is taken  
high, the device requires tRH of wake up time before outputs are valid for read access.  
In the standby mode the outputs are in the high impedance state, independent of the OE input.  
Automatic Sleep Mode  
There is a function called automatic sleep mode to restrain power consumption during read-out of  
MBM29LV800TA/800BA data. This mode can be used effectively with an application requested low power  
consumption such as handy terminals.  
To activate this mode, MBM29LV800TA/800BA automatically switch themselves to low power mode when  
MBM29LV800TA/800BA addresses remain stably during access fine of 150 ns. It is not necessary to control CE,  
WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level).  
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,  
the mode is canceled automatically and MBM29LV800TA/800BA read-out the data for changed addresses.  
Output Disable  
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins  
to be in a high impedance state.  
Autoselect  
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer  
and type. This mode is intended for use by programming equipment for the purpose of automatically matching  
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the  
entire temperature range of the devices.  
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two  
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All  
addresses are DON’T CARES except A0, A1, A6, and A-1. (See Table 4.1.)  
11  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
The manufacturer and device codes may also be read via the command register, for instances when the  
MBM29LV800TA/BA are erased or programmed in a system without access to high voltage on the A9 pin. The  
command sequence is illustrated in Table 7. (Refer to Autoselect Command section.)  
Byte 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04H) and (A0 = VIH) represents the device identifier  
code (MBM29LV800TA = DAH and MBM29LV800BA = 5BH for ×8 mode; MBM29LV800TA = 22DAH and  
MBM29LV800BA=225BHfor×16mode). Thesetwobytes/wordsaregiveninthetables4.1and4.2. Allidentifiers  
for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper  
device codes when executing the autoselect, A1 must be VIL. (See Tables 4.1 and 4.2.)  
Table 4 .1 MBM29LV800TA/800BA Sector Protection Verify Autoselect Codes  
*1  
Type  
Manufacture’s Code  
A12 to A18  
A6  
A1  
A0  
A-1  
VIL  
VIL  
X
Code (HEX)  
04H  
X
VIL  
VIL  
VIL  
Byte  
Word  
Byte  
DAH  
MBM29LV800TA  
MBM29LV800BA  
X
X
VIL  
VIL  
VIH  
22DAH  
5BH  
Device Code  
VIL  
X
VIL  
VIL  
VIL  
VIH  
VIH  
VIL  
Word  
225BH  
Sector  
Addresses  
Sector Protection  
VIL  
01H*2  
*1: A-1 is for Byte mode.  
*2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.  
Table 4 .2 Expanded Autoselect Code Table  
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0  
Type  
Code  
A-1/0  
Manufacturer’s Code  
04H  
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
(B) DAH A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z  
MBM29LV800TA  
(W) 22DAH  
0
0
1
0
0
0
1
0
Device  
Code  
(B) 5BH A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z  
MBM29LV800BA  
(W) 225BH  
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
A-1/0  
Sector Protection  
01H  
(B): Byte mode  
(W): Word mode  
12  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Write  
Device erasure and programming are accomplished via the command register. The contents of the register serve  
as inputs to the internal state machine. The state machine outputs dictate the function of the device.  
The command register itself does not occupy any addressable memory location. The register is a latch used to  
store the commands, along with the address and data information needed to execute the command. The  
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on  
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,  
whichever happens first. Standard microprocessor write timings are used.  
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.  
Sector Protection  
The MBM29LV800TA/BA feature hardware sector protection. This feature will disable both program and erase  
operations in any number of sectors (0 through 18). The sector protection feature is enabled using programming  
equipment at the user’s site. The devices are shipped with all sectors unprotected. Alternatively, Fujitsu may  
program and protect sectors in the factory prior to shiping the device.  
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest  
VID = 11.5 V), CE = VIL, and A6 = VIL. The sector addresses (A18, A17, A16, A15, A14, A13, and A12) should be set to  
the sector to be protected. Tables 5 and 6 define the sector address for each of the nineteen (19) individual  
sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated  
with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See Figures 16  
and 24 for sector protection waveforms and algorithm.  
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9  
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while  
(A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the  
devices will read 00H for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6  
are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.  
A-1 requires to apply to VIL on byte mode.  
ItisalsopossibletodetermineifasectorisprotectedinthesystembywritinganAutoselectcommand. Performing  
a read operation at the address location XX02H, where the higher order addresses (A18, A17, A16, A15, A14, A13,  
and A12) are the desired sector address will produce a logical “1” at DQ0 for a protected sector. See Tables 4.1  
and 4.2 for Autoselect codes.  
Temporary Sector Unprotection  
This feature allows temporary unprotection of previously protected sectors of the MBM29LV800TA/BA devices  
in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage  
(12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector  
addresses. Once the 12 V is taken away from the RESETpin, all the previously protected sectors will be protected  
again. See Figures 17 and 25.  
13  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
RESET  
Hardware Reset  
The MBM29LV800TA/BA devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse  
requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine.  
Any operation in the process of being executed will be terminated and the internal state machine will be reset  
to the read mode 20 µs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the  
devices require an additional tRH before it will allow read access. When the RESET pin is low, the devices will  
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware  
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please  
note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 12 for the timing  
diagram. Refer to Temporary Sector Unprotection for additional functionality.  
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)  
cannot be used.  
14  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Table 5 Sector Address Tables (MBM29LV800TA)  
Sector  
Address  
A18  
A17  
A16  
A15  
A14  
A13  
A12  
Address Range (×8) Address Range (×16)  
SA0  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
00000H to 0FFFFH  
10000H to 1FFFFH  
20000H to 2FFFFH  
30000H to 3FFFFH  
40000H to 4FFFFH  
50000H to 5FFFFH  
60000H to 6FFFFH  
70000H to 7FFFFH  
80000H to 8FFFFH  
90000H to 9FFFFH  
A0000H to AFFFFH  
B0000H to BFFFFH  
C0000H to CFFFFH  
D0000H to DFFFFH  
E0000H to EFFFFH  
F0000H to F7FFFH  
F8000H to F9FFFH  
FA000H to FBFFFH  
FC000H to FFFFFH  
00000H to 07FFFH  
08000H to 0FFFFH  
10000H to 17FFFH  
18000H to 1FFFFH  
20000H to 27FFFH  
28000H to 2FFFFH  
30000H to 37FFFH  
38000H to 3FFFFH  
40000H to 47FFFH  
48000H to 4FFFFH  
50000H to 57FFFH  
58000H to 5FFFFH  
60000H to 67FFFH  
68000H to 6FFFFH  
70000H to 77FFFH  
78000H to 7BFFFH  
7C000H to 7CFFFH  
7D000H to 7DFFFH  
7E000H to 7FFFFH  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
SA11  
SA12  
SA13  
SA14  
SA15  
SA16  
SA17  
SA18  
1
1
0
1
1
1
X
15  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Table 6 Sector Address Tables (MBM29LV800BA)  
Sector  
A18  
A17  
A16  
A15  
A14  
A13  
A12  
Address Range (×8) Address Range (×16)  
Address  
SA0  
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
0
00000H to 03FFFH  
04000H to 05FFFH  
06000H to 07FFFH  
08000H to 0FFFFH  
10000H to 1FFFFH  
20000H to 2FFFFH  
30000H to 3FFFFH  
40000H to 4FFFFH  
50000H to 5FFFFH  
60000H to 6FFFFH  
70000H to 7FFFFH  
80000H to 8FFFFH  
90000H to 9FFFFH  
A0000H to AFFFFH  
B0000H to BFFFFH  
C0000H to CFFFFH  
D0000H to DFFFFH  
E0000H to EFFFFH  
F0000H to FFFFFH  
00000H to 01FFFH  
02000H to 02FFFH  
03000H to 03FFFH  
04000H to 07FFFH  
08000H to 0FFFFH  
10000H to 17FFFH  
18000H to 1FFFFH  
20000H to 27FFFH  
28000H to 2FFFFH  
30000H to 37FFFH  
38000H to 3FFFFH  
40000H to 47FFFH  
48000H to 4FFFFH  
50000H to 57FFFH  
58000H to 5FFFFH  
60000H to 67FFFH  
68000H to 6FFFFH  
70000H to 77FFFH  
78000H to 7FFFFH  
SA1  
SA2  
0
1
1
SA3  
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA4  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
SA11  
SA12  
SA13  
SA14  
SA15  
SA16  
SA17  
SA18  
16  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Table 7 MBM29LV800TA/800BA Standard Command Definitions  
Fourth Bus  
First Bus Second Bus Third Bus  
Write Cycle Write Cycle Write Cycle  
Fifth Bus  
Sixth Bus  
Bus  
Write  
Read/Write  
Cycle  
Command  
Sequence  
Write Cycle Write Cycle  
Cycles  
Req’d  
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data  
Word  
Read/Reset  
Read/Reset  
Autoselect  
Program  
1
3
3
4
6
6
XXXH F0H  
—
—
—
—
—
RA  
—
—
RD  
—
—
—
—
—
—
—
—
—
—
—
—
—
Byte  
Word  
Byte  
Word  
Byte  
Word  
Byte  
Word  
Byte  
Word  
Byte  
555H  
AAH  
2AAH  
555H  
2AAH  
555H  
2AAH  
555H  
2AAH  
555H  
2AAH  
555H  
555H  
AAAH  
555H  
AAAH  
555H  
AAAH  
555H  
AAAH  
555H  
AAAH  
55H  
55H  
55H  
55H  
55H  
F0H  
90H  
A0H  
80H  
80H  
AAAH  
555H  
AAH  
—
—
AAAH  
555H  
AAH  
PA  
PD  
—
—
AAAH  
555H  
AAH  
555H  
AAAH  
555H  
AAAH  
2AAH  
555H  
2AAH  
555H  
555H  
AAAH  
Chip Erase  
Sector Erase  
AAH  
AAH  
55H  
55H  
10H  
30H  
AAAH  
555H  
AAH  
SA  
AAAH  
Sector Erase Suspend  
Sector Erase Resume  
Erase can be suspended during sector erase with Addr. (“H” or “L”). Data (B0H)  
Erase can be resumed after suspend with Addr. (“H” or “L”). Data (30H)  
Notes: 1. Address bits A11 to A18 = X = “H” or “L” for all address commands except or Program Address (PA) and  
Sector Address (SA)  
2. Bus operations are defined in Tables 2 and 3.  
3. RA = Address of the memory location to be read  
PA = Address of the memory location to be programmed  
Addresses are latched on the falling edge of the WE pulse.  
SA = Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will  
uniquely select any sector.  
4. RD = Data read from location RA during read operation.  
PD = Data to be programmed at location PA. Data is latched on the falling edge of WE.  
5. The system should generate the following address patterns:  
Word Mode: 555H or 2AAH to addresses A0 to A10  
Byte Mode: AAAH or 555H to addresses A–1 and A0 to A10  
6. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.  
17  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Table 8 MBM29LV800TA/BA Extended Command Definitions  
Bus  
Write  
First Bus  
Second Bus  
Write Cycle  
Third Bus  
Fourth Bus  
Read Cycle  
Command  
Sequence  
Write Cycle  
Write Cycle  
Cycles  
Req'd  
Addr  
Data  
Addr  
2AAH  
555H  
Data  
Addr  
Data  
Addr  
Data  
Word  
Byte  
Word  
Byte  
555H  
AAAH  
XXXH  
XXXH  
555H  
Set to  
Fast Mode  
3
2
AAH  
55H  
20H  
—
—
AAAH  
Fast  
A0H  
90H  
PA  
PD  
—
—
—
—
—
—
—
—
Program*1  
Word  
XXXH  
XXXH  
XXXH  
XXXH  
Reset from  
F0H*3  
2
4
Fast Mode *1  
Byte  
Word  
Byte  
Extended  
Sector  
XXXH  
60H  
SPA  
60H  
SPA  
40H  
SPA  
SD  
Protect*2  
SPA : Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).  
SD : Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected  
sector addresses.  
*1:This command is valid while Fast Mode.  
*2:This command is valid while RESET=VID.  
*3:This data "00H" is also acceptable.  
Command Definitions  
Device operations are selected by writing specific address and data sequences into the command register.  
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the  
read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and  
Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both  
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that  
commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.  
Read/Reset Command  
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset  
operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor  
read cycles retrieve array data from the memory. The devices remain enabled for reads until the command  
register contents are altered.  
The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required  
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no  
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read  
Characteristics and Waveforms for the specific timing parameters.  
18  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Autoselect Command  
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,  
manufacture and device codes must be accessible while the devices reside in the target system. PROM  
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high  
voltage onto the address lines is not generally desired system design practice.  
The device contains an Autoselect command operation to supplement traditional PROM programming  
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.  
Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read  
cycle from address XX01H for ×16(XX02H for ×8) returns the device code (MBM29LV800TA = DAH and  
MBM29LV800BA = 5BH for ×8 mode; MBM29LV800TA = 22DAH and MBM29LV800BA = 225BH for ×16 mode).  
(See Tables 4.1 and 4.2.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity  
bit. Sector state (protection or unprotection) will be informed by address XX02H for ×16 (XX04H for ×8).  
Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a  
logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin  
mode on the protected sector. (See Tables 2 and 3.)  
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and  
also to write the Autoselect command during the operation, execute it after writing Read/Reset command  
sequence.  
Byte/Word Programming  
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle  
operation. There are two “unlock” write cycles. These are followed by the program set-up command and data  
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is  
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever  
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,  
the system is not required to provide further controls or timings. The device will automatically provide adequate  
internally generated program pulses and verify the programmed cell margin.  
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this  
bitatwhichtimethedevicesreturntothereadmodeandaddressesarenolongerlatched. (SeeTable9, Hardware  
Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by the system  
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being  
programmed.  
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the  
programming operation, it is impossible to guarantee the data are being written.  
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be  
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success  
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only  
erase operations can convert “0”s to “1”s.  
Figure 20 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.  
19  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Chip Erase  
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the  
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.  
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase  
Algorithm command sequence the devices will automatically program and verify the entire memory for an all  
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any  
controls or timings during these operations.  
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates  
when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the  
mode.  
Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)  
Figure 21 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.  
Sector Erase  
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the  
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector  
address (any address location within the desired sector) is latched on the falling edge of WE, while the command  
(Data=30H) is latched on the rising edge of WE. After time-out of 50 µs from the rising edge of the last sector  
erase command, the sector erase operation will begin.  
Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 7. This sequence  
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently  
erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and  
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this  
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs  
from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling  
edge of the WE occurs within the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine if the  
sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector  
Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the previous  
command string. Resetting the devices once execution has begun will corrupt the data in the sector. In that  
case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section  
for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any  
number of sectors (0 to 18).  
Sector erase does not require the user to program the devices prior to erase. The devices automatically program  
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing  
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any  
controls or timings during these operations.  
The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last  
sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section.)  
at which time the devices return to the read mode. Data polling must be performed at an address within any of  
the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time  
(Preprogramming)] × Number of Sector Erase  
Figure 21 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.  
20  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Erase Suspend  
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads  
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase  
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if  
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command  
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the  
erase operation.  
Writing the Erase Resume command resumes the erase operation. The addresses are DON’T CARES when  
writing the Erase Suspend or Erase Resume command.  
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum  
of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/  
BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of  
the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further  
writes of the Erase Suspend command are ignored.  
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading  
data in this mode is the same as reading from the standard read mode except that the data must be read from  
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the  
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)  
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate  
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,  
programming in this mode is the same as programming in the regular Program mode except that the data must  
beprogrammedtosectorsthatarenoterase-suspended. Successivelyreadingfromtheerase-suspendedsector  
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-  
suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or by the Toggle Bit I  
(DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address  
while DQ6 can be read from any address.  
To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of  
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the  
chip has resumed erasing.  
21  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Extended Command  
(1) Fast Mode  
MBM29LV800TA/BAhasFastModefunction. Thismodedispenseswiththeinitialtwounclockcyclesrequired  
in the standard program command sequence by writing Fast Mode command into the command register. In  
this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard  
program command. (Do not write erase command in this mode.) The read operation is also executed after  
exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command  
register. (Refer to the Figure 27 Extended algorithm.) The VCC active current is required even CE = VIH during  
Fast Mode.  
(2) Fast Programming  
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program  
Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to  
the Figure 27 Extended algorithm.)  
(3) Extended Sector Protection  
In addition to normal sector protection, the MBM29LV800TA/BA has Extended Sector Protection as extended  
function. This function enable to protect sector by forcing VID on RESET pin and write a commnad sequence.  
Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only  
RESET pinrequiresVID forsectorprotectioninthismode. TheextendedsectorprotectrequiresVID onRESET  
pin. With this condition, the operation is initiated by writing the set-up command (60H) into the command  
register. Then, the sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should  
be set to the sector to be protected (recommend to set VIL for the other addresses pins), and write extended  
sector protect command (60H). A sector is typically protected in 150 µs. To verify programming of the  
protection circuitry, the sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0)  
should be set and write a command (40H). Following the command write, a logical “1” at device output DQ0  
will produce for protected sector in the read operation. If the output data is logical “0”, please repeat to write  
extended sector protect command (60H) again. To terminate the operation, it is necessary to set RESET  
pin to VIH.  
22  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Write Operation Status  
Table 9 Hardware Sequence Flags  
Status  
DQ7  
DQ6  
DQ5 DQ3  
DQ2  
1
Embedded Program Algorithm  
Embedded Erase Algorithm  
DQ7 Toggle  
0
0
0
1
0
1
Toggle  
1
Toggle  
Erase Suspend Read  
(Erase Suspended Sector)  
0
0
Toggle  
In Progress  
Erase  
Erase Suspend Read  
Suspended  
Data Data Data Data Data  
(Non-Erase Suspended Sector)  
Mode  
Erase Suspend Program  
(Non-Erase Suspended Sector)  
Toggle  
(Note 1)  
1
DQ7  
0
0
(Note 2)  
Embedded Program Algorithm  
Embedded Erase Algorithm  
DQ7 Toggle  
Toggle  
1
1
0
1
1
0
N/A  
Exceeded  
Time Limits  
Erase  
Erase Suspend Program  
Suspended  
DQ7 Toggle  
1
0
N/A  
(Non-Erase Suspended Sector)  
Mode  
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.  
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate  
logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to  
toggle.  
3. DQ0 and DQ1 are reserve pins for future use.  
4. DQ4 is Fujitsu internal use only.  
23  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
DQ7  
Data Polling  
The MBM29LV800TA/BA devices feature Data Polling as a method to indicate to the host that the Embedded  
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the  
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program  
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded  
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the  
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart  
for Data Polling (DQ7) is shown in Figure 22.  
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six  
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased  
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is  
close to being completed, the MBM29LV800TA/BA data pins (DQ7) may change asynchronously while the output  
enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant  
of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the  
DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm  
operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0  
to DQ7 will be read on the successive read attempts.  
TheDataPollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm,EmbeddedEraseAlgorithm  
or sector erase time-out. (See Table 9.)  
See Figure 9 for the Data Polling timing specifications and diagrams.  
DQ6  
Toggle Bit I  
The MBM29LV800TA/BA also feature the “Toggle Bit I” as a method to indicate to the host system that the  
Embedded Algorithms are in progress or completed.  
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from  
the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm  
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During  
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.  
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six  
write pulse sequence. The Toggle Bit I is active during the sector time out.  
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop  
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the  
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs  
and then drop back into read mode, having changed none of the data.  
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will  
cause the DQ6 to toggle.  
See Figure 10 for the Toggle Bit I timing specifications and diagrams.  
24  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
DQ5  
Exceeded Timing Limits  
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under  
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase  
cycle was not successfully completed. Data Polling is the only operating function of the devices under this  
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).  
The OE and WE pins will control the output disable functions as described in Tables 2 and 3.  
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this  
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never  
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the  
DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly  
used. If this occurs, reset the device with command sequence.  
DQ3  
Sector Erase Timer  
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will  
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase  
command sequence.  
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may  
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled  
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase  
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept  
additional sector erase commands. To insure the command has been accepted, the system software should  
check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on  
the second status check, the command may not have been accepted.  
See Table 9: Hardware Sequence Flags.  
DQ2  
Toggle Bit II  
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase  
Algorithm or in Erase Suspend.  
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the  
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause  
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte  
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.  
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend  
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized  
as follows:  
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.  
(DQ2 toggles while DQ6 does not.) See also Table 9 and Figure 18.  
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase  
mode, DQ2 toggles if this bit is read from an erasing sector.  
25  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Mode  
DQ7  
DQ7  
0
DQ6  
DQ2  
1
Program  
Erase  
Toggle  
Toggle  
Toggle  
Erase-Suspend Read  
(Erase-Suspended Sector)  
(Note 1)  
1
1
Toggle  
Erase-Suspend Program  
DQ7  
Toggle (Note 1)  
1 (Note 2)  
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.  
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate  
logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to  
toggle.  
RY/BY  
Ready/Busy  
The MBM29LV800TA/BA provide a RY/BY open-drain output pin as a way to indicate to the host system that the  
Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy  
with either a program or erase operation. If the output is high, the devices are ready to accept any read/write or  
erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase  
commands. If the MBM29LV800TA/BA are placed in an Erase Suspend mode, the RY/BY output will be high.  
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase  
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a  
busy condition during the RESET pulse. Refer to Figure 11 and 12 for a detailed timing diagram. The RY/BY  
pin is pulled high in standby mode.  
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.  
Byte/Word Configuration  
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV800TA/BA devices. When  
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0  
to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin  
becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always  
an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer  
to Figures 13, 14 and 15 for the timing diagram.  
Data Protection  
The MBM29LV800TA/BA are designed to offer protection against accidental erasure or programming caused by  
spurious system level signals that may exist during power transitions. During power up the devices automatically  
reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the  
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.  
The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up  
and power-down transitions or system noise.  
26  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Low VCC Write Inhibit  
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less  
than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits  
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until  
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct  
to prevent unintentional writes when VCC is above 2.3 V.  
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.  
Write Pulse “Glitch” Protection  
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.  
Logical Inhibit  
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE  
must be a logical zero while OE is a logical one.  
Power-Up Write Inhibit  
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.  
The internal state machine is automatically reset to the read mode on power-up.  
27  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ ABSOLUTE MAXIMUM RATINGS  
Storage Temperature ..................................................................................................–55°C to +125°C  
Ambient Temperature with Power Applied ..................................................................–40°C to +85°C  
Voltage with respect to Ground All pins except A9, OE, RESET (Note 1)...................–0.5 V to VCC+0.5 V  
VCC (Note 1) ................................................................................................................–0.5 V to +5.5 V  
A9, OE, and RESET (Note 2) ......................................................................................–0.5 V to +13.0 V  
Notes: 1. Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negative  
overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCC  
+0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.  
2. Minimum DC input voltage on A9, OE and RESET pins are –0.5 V. During voltage transitions, A9, OE  
and RESET pins may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input  
voltage on A9, OE and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of  
up to 20 ns. Voltage difference between input voltage and supply voltage (VIN – VCC) do not exceed 9 V.  
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,  
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.  
■ RECOMMENDED OPERATING RANGES  
Ambient Temperature (TA)........................................................................................ –40°C to +85°C  
VCC Supply Voltages  
MBM29LV800TA/BA-70......................................................................................... +3.0 V to +3.6 V  
MBM29LV800TA/BA-90/-12 ................................................................................. +2.7 V to +3.6 V  
Operating ranges define those limits between which the functionality of the devices are guaranteed.  
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the  
semiconductor device. All the device’s electrical characteristics are warranted when the device is  
operated within these ranges.  
Always use semiconductor devices within their recommended operating condition ranges. Operation  
outside these ranges may adversely affect reliability and could result in device failure.  
No warranty is made with respect to uses, operating conditions, or combinations not represented on  
the data sheet. Users considering application outside the listed conditions are advised to contact their  
FUJITSU representatives beforehand.  
28  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ MAXIMUM OVERSHOOT  
20 ns  
20 ns  
+0.6 V  
–0.5 V  
–2.0 V  
20 ns  
Figure 1 Maximum Negative Overshoot Waveform  
20 ns  
V CC +2.0 V  
V CC +0.5 V  
+2.0 V  
20 ns  
20 ns  
Figure 2 Maximum Positive Overshoot Waveform 1  
20 ns  
+14.0 V  
+13.0 V  
V CC +0.5 V  
20 ns  
20 ns  
*: This waveform is applied for A9, OE, and RESET.  
Figure 3 Maximum Positive Overshoot Waveform 2  
29  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ DC CHARACTERISTICS  
Parameter  
Symbol  
Parameter Description  
Test Conditions  
Min.  
Max.  
Unit  
ILI  
Input Leakage Current  
Output Leakage Current  
VIN = VSS to VCC, VCC = VCC Max.  
VOUT = VSS to VCC, VCC = VCC Max.  
–1.0  
–1.0  
+1.0  
+1.0  
µA  
µA  
ILO  
A9, OE, RESET Inputs Leakage VCC = VCC Max.  
ILIT  
—
—
35  
µA  
Current  
A9, OE, RESET = 12.5 V  
Byte  
Word  
Byte  
22  
25  
12  
15  
35  
CE = VIL, OE = VIH,  
f=10 MHz  
mA  
ICC1  
VCC Active Current (Note 1)  
CE = VIL, OE = VIH,  
f=5 MHz  
—
mA  
Word  
ICC2  
ICC3  
ICC4  
VCC Active Current (Note 2)  
VCC Current (Standby)  
CE = VIL, OE = VIH  
—
—
mA  
VCC = VCC Max., CE = VCC ± 0.3 V,  
RESET = VCC ± 0.3 V  
5
5
µA  
VCC = VCC Max.,  
RESET = VSS ± 0.3 V  
VCC Current (Standby, Reset)  
—
—
µA  
VCC = VCC Max., CE = VSS ± 0.3 V,  
RESET = VCC ± 0.3 V  
VIN = VCC ± 0.3 V or VSS ± 0.3 V  
VCC Current  
(Automatic Sleep Mode) (Note 3)  
ICC5  
5
µA  
VIL  
VIH  
Input Low Level  
Input High Level  
—
—
–0.5  
2.0  
0.6  
V
V
VCC+0.3  
Voltage for Autoselect and Sector  
Protection (A9, OE, RESET)  
(Note 4)  
VID  
—
11.5  
12.5  
V
VOL  
Output Low Voltage Level  
Output High Voltage Level  
Low VCC Lock-Out Voltage  
IOL = 4.0 mA, VCC = VCC Min.  
IOH = –2.0 mA, VCC = VCC Min.  
IOH = –100 µA  
—
2.4  
0.45  
—
V
V
V
V
VOH1  
VOH2  
VLKO  
VCC–0.4  
2.3  
—
—
2.5  
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component  
(at 10 MHz).  
2. ICC active while Embedded Algorithm (program or erase) is in progress.  
3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.  
4. (VID – VCC) do not exceed 9 V.  
30  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ AC CHARACTERISTICS  
• Read Only Operations Characteristics  
Parameter  
Symbols  
-70  
(Note)  
-90  
-12  
Description  
Test Setup  
Unit  
(Note) (Note)  
JEDEC Standard  
tAVAV  
tRC  
Read Cycle Time  
—
Min.  
Max.  
70  
70  
90  
90  
120  
120  
ns  
ns  
CE = VIL  
OE = VIL  
tAVQV  
tACC  
Address to Output Delay  
tELQV  
tGLQV  
tEHQZ  
tGHQZ  
tCE  
tOE  
tDF  
tDF  
Chip Enable to Output Delay  
Output Enable to Output Delay  
Chip Enable to Output High-Z  
Output Enable to Output High-Z  
OE = VIL Max.  
70  
30  
25  
25  
90  
35  
30  
30  
120  
50  
ns  
ns  
ns  
ns  
—
—
—
Max.  
Max.  
Max.  
30  
30  
Output Hold Time From Addresses,  
CE or OE, Whichever Occurs First  
tAXQX  
—
tOH  
—
—
—
Min.  
Max.  
Max.  
0
20  
5
0
20  
5
0
20  
5
ns  
µs  
ns  
tREADY  
RESET Pin Low to Read Mode  
tELFL  
tELFH  
—
CE or BYTE Switching Low or High  
Note: Test Conditions:  
Output Load: 1 TTL gate and 30 pF (MBM29LV800TA/BA-70)  
1 TTL gate and 100 pF (MBM29LV800TA/BA-90/-12)  
Input rise and fall times: 5 ns  
Input pulse levels: 0.0 V to 3.0 V  
Timing measurement reference level  
Input: 1.5 V  
Output:1.5 V  
3.3 V  
IN3064  
or Equivalent  
2.7 kΩ  
Device  
Under  
Test  
6.2 kΩ  
CL  
Diodes = IN3064  
or Equivalent  
Notes: CL = 30 pF including jig capacitance (MBM29LV800TA/BA-70)  
CL = 100 pF including jig capacitance (MBM29LV800TA/BA-90/-12)  
Figure 4 Test Conditions  
31  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
• Write/Erase/Program Operations  
Parameter Symbols  
JEDEC Standard  
MBM29LV800TA/BA  
Description  
Write Cycle Time  
Unit  
-70  
-90  
90  
0
-12  
tAVAV  
tAVWL  
tWLAX  
tDVWH  
tWHDX  
—
tWC  
tAS  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Typ.  
Typ.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
70  
0
120  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
sec  
µs  
ns  
µs  
µs  
µs  
µs  
ns  
ns  
ns  
Address Setup Time  
Address Hold Time  
Data Setup Time  
tAH  
45  
35  
0
45  
45  
0
50  
50  
0
tDS  
tDH  
tOES  
Data Hold Time  
Output Enable Setup Time  
0
0
0
Output  
Read  
0
0
0
—
tOEH  
Enable Hold  
Time  
Toggle and Data Polling  
10  
0
10  
0
10  
0
tGHWL  
tGHEL  
tELWL  
tWLEL  
tWHEH  
tEHWH  
tWLWH  
tELEH  
tWHWL  
tEHEL  
tWHWH1  
tWHWH2  
—
tGHWL  
tGHEL  
tCS  
Read Recover Time Before Write  
Read Recover Time Before Write  
CE Setup Time  
0
0
0
0
0
0
tWS  
WE Setup Time  
0
0
0
tCH  
CE Hold Time  
0
0
0
tWH  
WE Hold Time  
0
0
0
tWP  
Write Pulse Width  
35  
35  
25  
25  
8
45  
45  
25  
25  
8
50  
50  
30  
30  
8
tCP  
CE Pulse Width  
tWPH  
tCPH  
tWHWH1  
tWHWH2  
tVCS  
tVIDR  
tVLHT  
tWPP  
tOESP  
tCSP  
tRB  
Write Pulse Width High  
CE Pulse Width High  
Byte Programming Operation  
Sector Erase Operation (Note 1)  
VCC Setup Time  
1
1
1
50  
500  
4
50  
500  
4
50  
500  
4
—
Rise Time to VID (Note 2)  
Voltage Transition Time (Note 2)  
Write Pulse Width (Note 2)  
OE Setup Time to WE Active (Note 2)  
CE Setup Time to WE Active (Note 2)  
Recover Time From RY/BY  
RESET Pulse Width  
—
—
100  
4
100  
4
100  
4
—
—
4
4
4
—
0
0
0
—
tRP  
500  
200  
500  
200  
500  
200  
—
tRH  
RESET Hold Time Before Read  
(Continued)  
32  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
(Continued)  
Parameter Symbols  
JEDEC Standard  
MBM29LV800TA/BA  
Description  
Unit  
-70  
30  
30  
90  
30  
-90  
35  
35  
90  
35  
-12  
50  
50  
90  
50  
—
—
—
—
tFLQZ  
tFHQV  
tBUSY  
tEOE  
BYTE Switching Low to Output High-Z Max.  
ns  
ns  
ns  
ns  
BYTE Switching High to Output Active  
Program/Erase Valid to RY/BY Delay  
Delay Time from Embedded Output Enable  
Min.  
Max.  
Max.  
Notes: 1. This does not include the preprogramming time.  
2. This timing is for Sector Protection operation.  
33  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ SWITCHING WAVEFORMS  
• Key to Switching Waveforms  
WAVEFORM  
INPUTS  
OUTPUTS  
Must Be  
Steady  
Will Be  
Steady  
May  
Change  
from H to L  
Will Be  
Changing  
from H to L  
May  
Change  
from L to H  
Will Be  
Changing  
from L to H  
“H” or “L”  
Any Change  
Permitted  
Changing  
State  
Unknown  
Does Not  
Apply  
Center Line is  
High-  
Impedance  
“Off” State  
t RC  
Addresses  
Addresses Stable  
t ACC  
CE  
OE  
t OE  
t DF  
t OEH  
WE  
t CE  
High-Z  
High-Z  
Outputs  
Output Valid  
Figure 5.1 AC Waveforms for Read Operations  
34  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
t RC  
Addresses  
Addresses Stable  
t ACC  
t RH  
RESET  
Outputs  
t OH  
High-Z  
Output Valid  
Figure 5.2 AC Waveforms for Hardware Reset/Read Operations  
35  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Data Polling  
3rd Bus Cycle  
Addresses  
555H  
PA  
PA  
t WC  
t RC  
t AS  
t AH  
CE  
t CH  
t CS  
t CE  
OE  
t WP  
t WPH  
t OE  
t GHWL  
t WHWH1  
WE  
t OH  
t DS  
t DH  
A0H  
PD  
DQ 7  
D OUT  
D OUT  
Data  
Notes: 1. PA is address of the memory location to be programmed.  
2. PD is data to be programmed at byte address.  
3. DQ7 is the output of the complement of the data written to the device.  
4. DOUT is the output of the data written to the device.  
5. Figure indicates last two bus cycles out of four bus cycle sequence.  
6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)  
Figure 6 AC Waveforms for Alternate WE Controlled Program Operations  
36  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
3rd Bus Cycle  
Data Polling  
Addresses  
PA  
PA  
555H  
t WC  
t AS  
t AH  
WE  
t WS  
t WH  
OE  
CE  
t GHEL  
t CP  
t CPH  
t WHWH1  
t DS  
t DH  
A0H  
PD  
DQ 7  
D OUT  
Data  
Notes: 1. PA is address of the memory location to be programmed.  
2. PD is data to be programmed at byte address.  
3. DQ7 is the output of the complement of the data written to the device.  
4. DOUT is the output of the data written to the device.  
5. Figure indicates last two bus cycles out of four bus cycle sequence.  
6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)  
Figure 7 AC Waveforms for Alternate CE Controlled Program Operations  
37  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
2AAH  
555H  
555H  
Addresses  
555H  
2AAH  
SA  
t WC  
t AS  
t AH  
CE  
t CS  
t CH  
OE  
t WP  
t WPH  
t GHWL  
WE  
t DS  
t DH  
10H/  
30H  
AAH  
55H  
80H  
AAH  
55H  
Data  
t VCS  
V CC  
Notes: 1. SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte)  
for Chip Erase.  
2. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)  
Figure 8 AC Waveforms Chip/Sector Erase Operations  
38  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
CE  
t CH  
t OE  
t DF  
OE  
t OEH  
WE  
t CE  
*
High-Z  
High-Z  
DQ7 =  
Data  
Data  
DQ7  
DQ7  
Valid Data  
t WHWH1 or 2  
DQ0 to DQ6  
Valid Data  
DQ0 to DQ6  
DQ0 to DQ6 = Output Flag  
t EOE  
* : DQ7 = Valid Data (The device has completed the Embedded operation).  
Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations  
CE  
tOEH  
WE  
tOES  
OE  
*
DQ 6 =  
Stop Toggling  
DQ 6  
Data  
DQ 6 = Toggle  
DQ 6 = Toggle  
Valid  
tOE  
* : DQ6 stops toggling (The device has completed the Embedded operation).  
Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations  
39  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
CE  
The rising edge of the last WE signal  
WE  
Entire programming  
or erase operations  
RY/BY  
t BUSY  
Figure 11 RY/BY Timing Diagram during Program/Erase Operations  
WE  
RESET  
tRP  
t RB  
RY/BY  
tREADY  
Figure 12 RESET/RY/BY Timing Diagram  
40  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
CE  
BYTE  
Data Output  
(DQ0 to DQ7)  
Data Output  
(DQ0 to DQ14)  
DQ0 to DQ14  
tELFH  
tFHQV  
DQ15  
DQ15/A-1  
A-1  
Figure 13 Timing Diagram for Word Mode Configuration  
CE  
BYTE  
tELFL  
DQ0 to DQ14  
Data Output  
(DQ0 to DQ14)  
Data Output  
(DQ0 to DQ7)  
DQ15/A-1  
DQ15  
A-1  
tFLQZ  
Figure 14 Timing Diagram for Byte Mode Configuration  
The falling edge of the last write signal  
CE or WE  
Input  
Valid  
BYTE  
tSET  
(tAS)  
tHOLD (tAH)  
Figure 15 BYTE Timing Diagram for Write Operations  
41  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
A18, A17, A16  
SAX  
SAY  
A15, A14  
A13, A12  
A0  
A1  
A6  
12 V  
3 V  
A9  
t VLHT  
12 V  
3 V  
OE  
WE  
CE  
t VLHT  
t VLHT  
t VLHT  
t WPP  
t OESP  
t CSP  
Data  
VCC  
01H  
t VCS  
t OE  
SAX : Sector Address for initial sector  
SAY : Sector Address for next sector  
Note: A-1 is VIL on byte mode.  
Figure 16 AC Waveforms for Sector Protection Timing Diagram  
42  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
VCC  
tVIDR  
tVCS  
tVLHT  
12 V  
3 V  
3 V  
RESET  
CE  
WE  
tVLHT  
tVLHT  
Program or Erase Command Sequence  
Unprotection Period  
RY/BY  
Figure 17 Temporary Sector  
Unprotection Timing Diagram  
Enter  
Erase  
Enter Erase  
Suspend Program  
Erase  
Resume  
Embedded  
Erasing  
Suspend  
WE  
Erase  
Erase Suspend  
Read  
Erase  
Suspend  
Program  
Erase Suspend  
Read  
Erase  
Erase  
Complete  
DQ6  
DQ2  
Toggle  
DQ2 and DQ6  
with OE  
Note: DQ2 is read from the erase-suspended sector.  
Figure 18 DQ2 vs. DQ6  
43  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
VCC  
tVCS  
RESET  
Add  
tVLHT  
tVIDR  
SPAX  
SPAX  
SPAY  
A0  
A1  
A6  
CE  
OE  
TIME-OUT  
WE  
Data  
60H  
60H  
40H  
01H  
60H  
tOE  
SPAX : Sector Address to be protected  
SPAY : Next Sector Address to be protected  
TIME-OUT : Time-Out window = 150 µs (min)  
Figure 19 Extended Sector Protection Timing Diagram  
44  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
EMBEDDED ALGORITHMS  
Start  
Write Program Command  
Sequence  
(See below)  
Data Polling Device  
No  
Last Address  
?
Increment Address  
Yes  
Programming Completed  
Program Command Sequence* (Address/Command):  
555H/AAH  
2AAH/55H  
555H/A0H  
Program Address/Program Data  
* : The sequence is applied for × 16 mode.  
The addresses differ from × 8 mode.  
Figure 20 Embedded ProgramTM Algorithm  
45  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
EMBEDDED ALGORITHMS  
Start  
Write Erase Command  
Sequece  
(See below)  
Data Polling or Toggle Bit  
Successfully Completed  
Erasure Completed  
Individual Sector/Multiple Sector*  
Chip Erase Command Sequence*  
Erase Command Sequence  
(Address/Command):  
(Address/Command):  
555H/AAH  
2AAH/55H  
555H/80H  
555H/AAH  
2AAH/55H  
555H/10H  
555H/AAH  
2AAH/55H  
555H/80H  
555H/AAH  
2AAH/55H  
Sector Address/30H  
Sector Address/30H  
Sector Address/30H  
Additional sector  
erase commands  
are optional.  
* : The sequence is applied for × 16 mode.  
The addresses differ from × 8 mode.  
Figure 21 Embedded EraseTM Algorithm  
46  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Start  
Read  
(DQ 0 to DQ 7)  
Addr. = VA  
VA = Byte address for programming  
= Any of the sector addresses within  
the sector being erased during  
sector erase or multiple sector  
erases operation  
Yes  
DQ 7 = Data?  
No  
= Any of the sector addresses within  
the sector not being protected  
during chip erase  
No  
DQ 5 = 1?  
Yes  
Read  
(DQ 0 to DQ 7)  
Addr. = VA  
Yes  
DQ 7 = Data?  
No  
Fail  
Pass  
Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.  
Figure 22 Data Polling Algorithm  
47  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Start  
Read  
(DQ 0 to DQ 7)  
Addr. = "H" or "L"  
No  
DQ 6 = Toggle  
?
Yes  
No  
DQ 5 = 1?  
Yes  
Read  
(DQ 0 to DQ 7)  
Addr. = VA  
No  
DQ 6 = Toggle  
?
Yes  
Fail  
Pass  
Note: DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as  
DQ5 changing to “1” .  
Figure 23 Toggle Bit Algorithm  
48  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Start  
Setup Sector Addr.  
(A18, A17, A16, A15, A14, A13, A12)  
PLSCNT = 1  
OE  
=
=
=
V ID, A 9  
V IL, RESET  
V IL, A 1  
= V ID,  
A 6  
=
CE  
= V IH  
A 0  
=
V IH  
Activate WE Pulse  
Time out 100 µs  
Increment PLSCNT  
WE = V IH, CE = OE = V IL  
(A 9 should remain V ID  
)
Read from Sector  
(Addr. = SA, A 0  
= V IL,  
A 1 V IH, A6 = V IL)*  
=
No  
No  
PLSCNT = 25?  
Yes  
Data = 01H?  
Yes  
Yes  
Remove V ID from A 9  
Write Reset Command  
Protect Another Sector?  
No  
Device Failed  
Remove V ID from A 9  
Write Reset Command  
Sector Protection  
Completed  
* : A-1 is VIL on byte mode.  
Figure 24 Sector Protection Algorithm  
49  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
Start  
RESET = VID  
(Note 1)  
Perform Erase or  
Program Operations  
RESET = VIH  
Temporary Sector  
Unprotection Completed  
(Note 2)  
Notes: 1. All protected sectors are unprotected.  
2. All previously protected sectors are protected once again.  
Figure 25 Temporary Sector Unprotection Algorithm  
50  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
FAST MODE ALGORITHM  
Start  
RESET = VID  
Wait to 4 µs  
Device is Operating in  
Temporary Sector  
Unprotection Mode  
No  
Extended Sector  
Protection Entry?  
Yes  
To Setup Sector Protection  
Write XXXH/60H  
PLSCNT = 1  
To Sector Protection  
Write SPA/60H  
(A0 = VIL, A1 = VIH, A6 = VIL)  
Time Out 150 µs  
Increment PLSCNT  
To Verify Sector Protection  
Write SPA/40H  
Setup Next Sector Address  
(A0 = VIL, A1 = VIH, A6 = VIL)  
Read from Sector Address  
(A0 = VIL, A1 = VIH, A6 = VIL)  
No  
No  
Data = 01H?  
Yes  
PLSCNT = 25?  
Yes  
Yes  
Remove VID from RESET  
Write Reset Command  
Protection Other Sector  
?
No  
Remove VID from RESET  
Write Reset Command  
Device Failed  
Sector Protection  
Completed  
Figure 26 Extended Sector Protection Algorithm  
51  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
FAST MODE ALGORITHM  
Start  
555H/AAH  
Set Fast Mode  
2AAH/55H  
555H/20H  
XXXH/A0H  
Program Address/Program Data  
Data Polling Device  
No  
In Fast Program  
Verify Byte?  
Yes  
No  
Last Address  
?
Increment Address  
Yes  
Programming Completed  
XXXH/90H  
XXXH/F0H  
Reset Fast Mode  
* : The sequence is applied for × 16 mode.  
The addresses differ from × 8 mode.  
Figure 27 Embedded ProgramTM Algorithm for Fast Mode  
52  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ ERASE AND PROGRAMMING PERFORMANCE  
Limits  
Typ.  
Parameter  
Unit  
Comments  
Min.  
Max.  
Excludes programming time  
prior to erasure  
Sector Erase Time  
—
1
10  
sec  
Word Programming Time  
Byte Programming Time  
—
—
16  
8
360  
300  
µs  
µs  
Excludes system-level  
overhead  
Excludes system-level  
overhead  
Chip Programming Time  
Program/Erase Cycle  
—
8.4  
—
25  
—
sec  
100,000  
cycles  
—
■ TSOP(I) PIN CAPACITANCE  
Parameter  
Symbol  
Parameter Description  
Test Setup  
Typ.  
Max.  
Unit  
CIN  
Input Capacitance  
VIN = 0  
7.5  
8
9.5  
10  
13  
pF  
pF  
pF  
COUT  
Output Capacitance  
Control Pin Capacitance  
VOUT = 0  
VIN = 0  
CIN2  
10  
Note: Test conditions TA = 25°C, f = 1.0 MHz  
■ SOP PIN CAPACITANCE  
Parameter  
Parameter Description  
Symbol  
Test Setup  
Typ.  
Max.  
Unit  
CIN  
Input Capacitance  
VIN = 0  
VOUT = 0  
VIN = 0  
7.5  
8
9.5  
10  
13  
pF  
pF  
pF  
COUT  
CIN2  
Output Capacitance  
Control Pin Capacitance  
10  
Note: Test conditions TA = 25°C, f = 1.0 MHz  
■ SON PIN CAPACITANCE  
Parameter  
Parameter Description  
Symbol  
Test Setup  
Typ.  
Max.  
Unit  
CIN  
Input Capacitance  
VIN = 0  
VOUT = 0  
VIN = 0  
7.5  
8
9.5  
10  
13  
pF  
pF  
pF  
COUT  
CIN2  
Output Capacitance  
Control Pin Capacitance  
10  
Note: Test conditions TA = 25°C, f = 1.0 MHz  
53  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ FBGA PIN CAPACITANCE  
Parameter  
Parameter Description  
Test Setup  
VIN = 0  
Typ.  
Max.  
Unit  
Symbol  
CIN  
Input Capacitance  
7.5  
8
9.5  
10  
13  
pF  
pF  
pF  
COUT  
Output Capacitance  
Control Pin Capacitance  
VOUT = 0  
VIN = 0  
CIN2  
10  
Note: Test conditions TA = 25°C, f = 1.0 MHz  
54  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
■ PACKAGE DIMENSIONS  
* Resin Protrusin. (Each Side: 0.15 (.006)Max)  
48-Pin plastic TSOP(I)  
(FPT-48P-M19)  
LEAD No.  
1
48  
Details of "A" part  
INDEX  
0.15(.006)  
MAX  
0.35(.014)  
MAX  
"A"  
0.15(.006)  
0.25(.010)  
24  
25  
20.00±0.20  
(.787±.008)  
* 12.00±0.20  
(.472±.008)  
*18.40±0.20  
(.724±.008)  
11.50REF  
(.460)  
1.10−+00..1050  
.043−+..000024  
(Mounting height)  
0.50(.0197)  
TYP  
0.05(0.02)MIN  
STAND OFF  
0.10(.004)  
0.15±0.05  
(.006±.002)  
0.20±0.10  
(.008±.004)  
M
0.10(.004)  
19.00±0.20  
(.748±.008)  
0.50±0.10  
(.020±.004)  
Dimensions in mm (inches)  
C
1996 FUJITSU LIMITED F48029S-2C-2  
* Resin Protrusin. (Each Side: 0.15 (.006)Max)  
48-Pin plastic TSOP(I)  
(FPT-48P-M20)  
LEAD No.  
1
48  
Details of "A" part  
INDEX  
0.15(.006)  
MAX  
0.35(.014)  
MAX  
"A"  
0.15(.006)  
0.25(.010)  
24  
25  
19.00±0.20  
(.748±.008)  
0.50±0.10  
(.020±.004)  
0.15±0.10  
(.006±.002)  
0.20±0.10  
(.008±.004)  
M
0.10(.004)  
0.50(.0197)  
TYP  
0.05(0.02)MIN  
STAND OFF  
0.10(.004)  
1.10−+00..1050  
*18.40±0.20  
(.724±.008)  
11.50(.460)REF  
* 12.00±0.20(.472±.008)  
.043−+..000024  
(Mounting height)  
20.00±0.20  
(.787±.008)  
Dimensions in mm (inches)  
C
1996 FUJITSU LIMITED F48030S-2C-2  
(Continued)  
55  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
44-pin plastic SOP  
(FPT-44P-M16)  
28.45+−0.250 1.120−+..000180  
2.50(.098)MAX  
(Mounting heght)  
(Mounting height)  
0.80±0.20  
(.031±.008)  
44  
23  
13.00±0.10 16.00±0.20  
(.512±.004) (.630±.008)  
14.40±0.20  
(.567±.008)  
INDEX  
"A"  
1
22  
LEAD No.  
0.15±0.05  
(.006±.002)  
1.27(.050)TYP  
0.10(.004)  
0.40−+00..1050  
.016−+..000024  
0.05(.002)MIN  
(Stand off)  
M
Ø0.13(.005)  
26.67(1.050)REF  
C
1995 FUJITSU LIMITED F44023S-3C-3  
Dimensions in mm (inches)  
(Continued)  
56  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
(Continued)  
48-pin plastic FBGA  
Note: The actual shape of corners may differ from the dimension.  
(BGA-48P-M02)  
5.60(.221)  
0.80(.031)NOM  
9.00±0.20(.354±.008)  
1.20(.047)MAX  
(Mounting height)  
0.35±0.10(.014±.004)  
(Stand off)  
6
5
4
3
2
1
0.80(.031)  
NOM  
4.00(.157)  
INDEX  
6.00±0.20  
(.236±.008)  
H
G
F
E
D
C
B
A
Ø0.40±0.10  
(.016±.004)  
M
Ø0.08(.003)  
0.10(.004)  
C
Dimensions in mm (inches)  
1997 FUJITSU LIMITED B48002S-1C-2  
(Continued)  
57  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
(Continued)  
48-pin plastic FBGA  
Note: The actual shape of corners may differ from the dimension.  
(BGA-48P-M12)  
9.00±0.20(.354±.008)  
1.05 +–00..1105 .041 –+..000046  
(Mounting height)  
5.60(.221)  
0.80(.031)TYP  
0.38±0.10(.015±.004)  
(Stand off)  
6
5
4
3
2
1
INDEX  
6.00±0.20  
(.236±.008)  
4.00(.157)  
H
G
F
E
D
C
B
A
C0.25(.010)  
48-Ø0.45±0.10  
(48-.018±.004)  
M
Ø0.08(.003)  
0.10(.004)  
C
Dimensions in mm (inches)  
1998 FUJITSU LIMITED B480012S-2C-2  
58  
MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12  
FUJITSU LIMITED  
For further information please contact:  
Japan  
FUJITSU LIMITED  
Corporate Global Business Support Division  
Electronic Devices  
KAWASAKI PLANT, 4-1-1, Kamikodanaka  
Nakahara-ku, Kawasaki-shi  
Kanagawa 211-8588, Japan  
Tel: 81(44) 754-3763  
All Rights Reserved.  
The contents of this document are subject to change without  
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CAUTION:  
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Any semiconductor devices have an inhereut chance of  
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F9904  
FUJITSU LIMITED Printed in Japan  
59  

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