MBM29LV800TA-90PBT-SF2 [SPANSION]
Flash, 512KX16, 90ns, PBGA48, PLASTIC, FBGA-48;型号: | MBM29LV800TA-90PBT-SF2 |
厂家: | SPANSION |
描述: | Flash, 512KX16, 90ns, PBGA48, PLASTIC, FBGA-48 内存集成电路 |
文件: | 总60页 (文件大小:472K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MBM29LV800TA-70/-90/
MBM29LV800BA-70/-90
MBM29LV800TA-70/-90/MBM29LV800BA-70/-
Data Sheet (Retired Product)
90Cover Sheet
This product has been retired and is not recommended for new designs. Availability of this document is retained for reference
and historical purposes only.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number MBM29LV800TA/BA
Revision DS05-20845-7E
Issue Date July 31, 2007
D a t a S h e e t ( R e t i r e d P r o d u c t )
This page left intentionally blank.
2
MBM29LV800TA/BA_DS05-20845-7E July 31, 2007
TM
SPANSION Flash Memory
Data Sheet
September 2003
This document specifies SPANSIONTM memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSIONTM product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSIONTM memory
solutions.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20845-7E
FLASH MEMORY
CMOS
8M (1M × 8/512K × 16) BIT
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
■ DESCRIPTION
The MBM29LV800TA/BA are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K
words of 16 bits each. The MBM29LV800TA/BA are offered in a 48-pin TSOP(1), 44-pin SOP, and 48-ball FBGA
packages. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply.
12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed
in standard EPROM programmers.
The standard MBM29LV800TA/BA offer access times 70 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The MBM29LV800TA/BA are pin and command set compatible with JEDEC standard E2PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the devices is similar
to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV800TA/BA are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
(Continued)
■ PRODUCT LINE UP
Part No.
MBM29LV800TA/MBM29LV800BA
+0.3 V
–0.3 V
VCC = 3.3 V
VCC = 3.0 V
-70
—
—
Ordering Part No.
+0.6 V
–0.3 V
-90
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
70
70
30
90
90
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MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
(Continued)
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV800TA/BA are erased when shipped from the
factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29LV800TA/BA memories electrically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one
byte/word at a time using the EPROM programming mechanism of hot electron injection.
■ PACKAGES
48-pin Plastic TSOP (1)
48-pin Plastic TSOP (1)
44-pin Plastic SOP
Marking Side
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
48-pin Plastic SCSP
(FPT-44P-M16)
48-pin Plastic FBGA
(BGA-48P-M12)
(WLP-48P-M03)
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MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
■ FEATURES
• Single 3.0 V Read, Program, and Erase
Minimizes system level power requirements
• Compatible with JEDEC-standard Commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard Worldwide Pinouts
48-pin TSOP(1) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
44-pin SOP (Package suffix: PF)
48-ball FBGA (Package suffix: PBT)
48-ball SCSP (Package suffix: PW)
• Minimum 100,000 Program/Erase Cycles
• High performance
70 ns maximum access time
• Sector Erase Architecture
One 8K word, two 4K words, one 16K word, and fifteen 32K words sectors in word mode
One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
• Ready/Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode
• Low VCC Write Inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Sector Protection
Hardware method disables any combination of sectors from program or erase operations
• Sector Protection Set Function by Extended Sector Protect Command
• Fast Programming Function by Extended Command
• Temporary Sector Unprotection
Temporary sector unprotection via the RESET pin
*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
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MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
■ PIN ASSIGNMENTS
SOP
(Top View)
TSOP(1)
A15
A14
A13
A12
A11
A10
A9
A8
A16
BYTE
VSS
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
(Marking Side)
RY/BY
A18
1
44
RESET
WE
2
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
DQ 15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
A17
3
A8
A7
4
A9
N.C.
N.C.
WE
RESET
N.C.
N.C.
RY/BY
A18
9
A6
5
A10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A5
6
A11
MBM29LV800TA/MBM29LV800BA
Normal Bend
A4
7
A12
A3
8
A13
A2
9
A14
A17
A7
A6
A5
A4
A3
A2
A1
A1
10
11
12
13
14
15
16
17
18
19
20
21
22
A15
A0
A16
VSS
CE
A0
CE
BYTE
V SS
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
(FPT-48P-M19)
(Marking Side)
DQ 15/A-1
DQ 7
DQ 14
DQ 6
DQ 13
DQ5
DQ 12
DQ4
VCC
A1
A2
A3
A4
A5
A6
A7
A17
A18
A0
CE
VSS
OE
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
RY/BY
N.C.
N.C.
RESET
WE
N.C.
N.C.
A8
MBM29LV800TA/MBM29LV800BA
Reverse Bend
(FPT-44P-M16)
A9
A10
A11
A12
A13
A14
A15
BYTE
A16
(FPT-48P-M20)
(Continued)
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MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
(Continued)
(TOP VIEW)
Marking side
A1
B1
C1
D1
E1
F1
G1
H1
A2
B2
C2
D2
E2
F2
G2
H2
A3
B3
C3
D3
E3
F3
G3
H3
A4
B4
C4
D4
E4
F4
G4
H4
A5
B5
C5
D5
E5
F5
G5
H5
A6
B6
C6
D6
E6
F6
G6
H6
(BGA-48P-M12)
A1
B1
C1
D1
E1
F1
G1
H1
A3
A2
B2
C2
D2
E2
F2
G2
H2
A7
A3
B3
RY/BY
N.C.
A18
A4
B4
C4
D4
E4
F4
G4
H4
WE
A5
A9
A6
B6
C6
D6
E6
F6
G6
H6
A13
A4
A17
A6
RESET B5
A8
A12
A2
C3
D3
E3
F3
G3
H3
N.C.
N.C.
DQ5
DQ12
VCC
C5
D5
E5
F5
G5
H5
A10
A14
A1
A5
N.C.
DQ2
A11
A15
A0
DQ0
DQ8
DQ9
DQ1
DQ7
DQ14
DQ13
DQ6
A16
CE
OE
VSS
DQ10
DQ11
DQ3
BYTE
DQ15/A-1
VSS
DQ4
SCSP
(Top View)
Marking side
A6
B6
C6
A2
D6
E6
A0
E5
F6
G6
OE
G5
H6
A3
A5
A7
A4
B5
A1
D5
A5
CE
F5
VSS
H5
C5
A6
A17
DQ0 DQ8 DQ9 DQ1
A4
B4
C4
A18
C3
D4
E4
F4
G4
DQ11
G3
H4
RY/BY N.C
A3 B3
N.C DQ2 DQ10
D3 E3 F3
DQ3
H3
WE RESET N.C N.C DQ5 DQ12 VCC DQ4
A2
B2
C2
D2
E2
F2
G2
H2
A9
A8
A10
C1
A11
D1
DQ7 DQ14 DQ13 DQ6
A1
B1
E1
F1
G1
H1
A13
A12
A14
A15
A16
VSS
BYTE DQ15/A-1
(WLP-48P-M03)
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Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
■ PIN DESCRIPTION
Pin name
A-1, A0 to A18
DQ0 to DQ15
CE
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
OE
Output Enable
Write Enable
WE
RY/BY
RESET
BYTE
VSS
Ready/Busy Output
Hardware Reset Pin/Temporary Sector Unprotection
Selects 8-bit or 16-bit mode
Device Ground
VCC
Device Power Supply
N.C.
No Internal Connection
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MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
■ BLOCK DIAGRAM
DQ 0 to DQ 15
RY/BY
Buffer
RY/BY
V CC
V SS
Erase Voltage
Generator
Input/Output
Buffers
WE
State
Control
BYTE
RESET
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
CE
OE
Y-Decoder
Y-Gating
STB
Timer for
Program/Erase
Address
Latch
Low V CC Detector
X-Decoder
Cell Matrix
A0 to A18
A-1
■ LOGIC SYMBOL
A-1
19
A0 to A18
16 or 8
DQ 0 to DQ 15
CE
OE
WE
RESET
BYTE
RY/BY
10
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■ DEVICE BUS OPERATION
MBM29LV800TA/800BA User Bus Operations Table (BYTE = VIH)
Operation
Auto-Select Manufacturer Code *1
Auto-Select Device Code *1
Read *3
CE OE WE
A0
L
A1
L
A6
L
A9
VID
VID
A9
X
DQ0 to DQ15 RESET
L
L
L
H
L
L
L
L
X
X
L
L
H
H
H
X
H
L
Code
Code
DOUT
High-Z
High-Z
DIN
H
H
H
H
H
H
H
H
VID
L
H
A0
X
L
L
L
A1
X
A6
X
X
A6
L
Standby
X
H
H
VID
L
Output Disable
X
X
X
Write (Program/Erase)
Enable Sector Protection *2, *4
Verify Sector Protection *2, *4
Temporary Sector Unprotection*5
Reset (Hardware)/Standby
A0
L
A1
H
H
X
A9
VID
VID
X
X
H
X
X
L
L
Code
X
X
X
X
X
X
X
X
X
High-Z
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See “■DC CHARACTERISTICS” for voltage levels.
*1: Manufacturer and device codes may also be accessed via a command register write sequence. See
“MBM29LV800TA/BA Standard Command Definitions Table”.
*2: Refer to “7. Sector Protection” in “■FUNCTIONAL DESCRIPTIONS”.
*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4: VCC = 3.3 V 10%
*5: It is also used for the extended sector protection.
MBM29LV800TA/800BA User Bus Operations Table (BYTE = VIL)
DQ15/
Operation
CE
OE WE
A0
A1
A6
A9 DQ0 to DQ7 RESET
A-1
L
Auto-Select Manufacturer Code *1
Auto-Select Device Code *1
Read *3
L
L
L
H
L
L
L
L
X
X
L
L
H
H
H
X
H
L
L
H
A0
X
X
A0
L
L
L
L
L
VID
VID
A9
X
Code
Code
DOUT
High-Z
High-Z
DIN
H
H
H
H
H
H
H
H
VID
L
L
L
A-1
X
A1
X
A6
X
X
A6
L
Standby
X
H
H
VID
L
Output Disable
X
X
X
Write (Program/Erase)
Enable Sector Protection *2, *4
Verify Sector Protection *2, *4
Temporary Sector Unprotection *5
Reset (Hardware)/Standby
A-1
L
A1
H
H
X
A9
VID
VID
X
X
H
X
X
L
L
L
Code
X
X
X
X
X
X
X
X
X
X
X
High-Z
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See “■DC CHARACTERISTICS” for voltage levels.
*1: Manufacturer and device codes may also be accessed via a command register write sequence. See
“MBM29LV800TA/BA Standard Command Definitions Table”.
*2: Refer to “7. Sector Protection” in “■FUNCTIONAL DESCRIPTIONS”.
*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4: VCC = 3.3 V 10%
*5: It is also used for the extended sector protection.
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MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
MBM29LV800TA/800BA Sector Protection Verify Autoselect Codes Table
*1
Type
Manufacture’s Code
A12 to A18
A6
A1
A0
Code (HEX)
04h
A-1
VIL
VIL
X
X
VIL
VIL
VIL
Byte
Word
Byte
DAh
MBM29LV800TA
MBM29LV800BA
X
X
VIL
VIL
VIH
22DAh
5Bh
Device Code
VIL
X
VIL
VIL
VIL
VIH
VIH
VIL
Word
225Bh
Sector
Addresses
Sector Protection
VIL
01h*2
*1: A-1 is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address.
*2: Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.
Extended Autoselect Code Table
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Code
Type
A-1/0
Manufacturer’s Code
04h
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
(B)* DAh A-1
MBM29LV800TA
Device
(W) 22DAh
0
0
1
0
0
0
1
0
Code
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
(B)* 5Bh A-1
MBM29LV800B
A
(W) 225Bh
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
A-1/0
Sector Protection
01h
* : At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address.
(B): Byte mode
(W): Word mode
HI-Z: High-Z
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MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
MBM29LV800TA/800BA Standard Command Definitions Table
Fourth Bus
First Bus Second Bus Third Bus
Write Cycle Write Cycle Write Cycle
Fifth Bus
Sixth Bus
Bus
Write
Read/Write
Cycle
Command
Sequence
Write Cycle Write Cycle
Cycles
Req’d
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Word
Read/Reset
Read/Reset
Autoselect
Program
1
3
3
4
6
6
XXXh F0h
—
—
—
—
—
RA
—
—
RD
—
—
—
—
—
—
—
—
—
—
—
—
—
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555h
AAh
2AAh
555h
2AAh
555h
2AAh
555h
2AAh
555h
2AAh
555h
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
55h
55h
55h
55h
55h
F0h
90h
A0h
80h
80h
AAAh
555h
AAh
—
—
AAAh
555h
AAh
PA
PD
AAh
AAh
—
—
AAAh
555h
AAh
555h
AAAh
555h
AAAh
2AAh
555h
2AAh
555h
555h
AAAh
Chip Erase
Sector Erase
55h
55h
10h
30h
AAAh
555h
AAh
SA
AAAh
Sector Erase Suspend
Sector Erase Resume
Erase can be suspended during sector erase with Addr. (“H” or “L”). Data (B0h)
Erase can be resumed after suspend with Addr. (“H” or “L”). Data (30h)
Notes: • Address bits A11 to A18 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA)
• Bus operations are defined in “MBM29LV800TA/BA User Bus Operations Tables (BYTE = VIH and
BYTE = VIL)” .
• RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
• RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
• The system should generate the following address patterns:
Word Mode: 555h or 2AAh to addresses A0 to A10
Byte Mode: AAAh or 555h to addresses A–1 and A0 to A10
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• Command combinations not described in “MBM29LV800TA/800BA Standard Command Definitions
Table” and “MBM29LV800TA/BA Extended Command Definitions Table” are illegal.
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MBM29LV800TA/BA Extended Command Definitions Table
Bus
Write
First Bus
Second Bus
Write Cycle
Third Bus
Fourth Bus
Read Cycle
Command
Sequence
Write Cycle
Write Cycle
Cycles
Req'd
Addr
Data
Addr
2AAh
555h
Data
Addr
Data
Addr
Data
Word
Byte
Word
Byte
555h
AAAh
XXXh
XXXh
555h
Set to
Fast Mode
3
2
AAh
55h
20h
—
—
AAAh
Fast
A0h
90h
PA
PD
—
—
—
—
—
—
—
Program*1
Word
XXXh
XXXh
XXXh
XXXh
Reset from
F0h*3
2
4
—
Fast Mode *1
Byte
Word
Byte
Extended
Sector
XXXh
60h
SPA
60h
SPA
40h
SPA
SD
Protect*2
SPA : Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).
SD : Sector protection verify data. Output 01h at protected sector addresses and output 00h at unprotected
sector addresses.
*1: This command is valid while Fast Mode.
*2: This command is valid while RESET=VID.
*3: This data “00h” is also acceptable.
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■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
• One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes
• Individual-sector, multiple-sector, or bulk-erase capability
• Individual or multiple-sector protection is user definable.
(×8)
(×16)
(×8)
(×16)
FFFFFh 7FFFFh
FBFFFh 7DFFFh
F9FFFh 7CFFFh
F7FFFh 7BFFFh
EFFFFh 77FFFh
DFFFFh 6FFFFh
CFFFFh 67FFFh
BFFFFh 5FFFFh
AFFFFh 57FFFh
9FFFFh 4FFFFh
8FFFFh 47FFFh
7FFFFh 3FFFFh
6FFFFh 37FFFh
5FFFFh 2FFFFh
4FFFFh 27FFFh
3FFFFh 1FFFFh
2FFFFh 17FFFh
1FFFFh 0FFFFh
0FFFFh 07FFFh
00000h 00000h
FFFFFh 7FFFFh
EFFFFh 77FFFh
DFFFFh 6FFFFh
CFFFFh 67FFFh
BFFFFh 5FFFFh
AFFFFh 57FFFh
9FFFFh 4FFFFh
8FFFFh 47FFFh
7FFFFh 3FFFFh
6FFFFh 37FFFh
5FFFFh 2FFFFh
4FFFFh 27FFFh
3FFFFh 1FFFFh
2FFFFh 17FFFh
1FFFFh 0FFFFh
0FFFFh 07FFFh
07FFFh 03FFFh
05FFFh 02FFFh
03FFFh 01FFFh
00000h 00000h
16K byte
8K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
32K byte
8K byte
8K byte
32K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
8K byte
16K byte
MBM29LV800TA Sector Architecture
MBM29LV800BA Sector Architecture
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Sector Address Table (MBM29LV800TA)
Sector
A18
A17
A16
A15
A14
A13
A12
Address Range (×8) Address Range (×16)
Address
SA0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
00000h to 0FFFFh
10000h to 1FFFFh
20000h to 2FFFFh
30000h to 3FFFFh
40000h to 4FFFFh
50000h to 5FFFFh
60000h to 6FFFFh
70000h to 7FFFFh
80000h to 8FFFFh
90000h to 9FFFFh
A0000h to AFFFFh
B0000h to BFFFFh
C0000h to CFFFFh
D0000h to DFFFFh
E0000h to EFFFFh
F0000h to F7FFFh
F8000h to F9FFFh
FA000h to FBFFFh
FC000h to FFFFFh
00000h to 07FFFh
08000h to 0FFFFh
10000h to 17FFFh
18000h to 1FFFFh
20000h to 27FFFh
28000h to 2FFFFh
30000h to 37FFFh
38000h to 3FFFFh
40000h to 47FFFh
48000h to 4FFFFh
50000h to 57FFFh
58000h to 5FFFFh
60000h to 67FFFh
68000h to 6FFFFh
70000h to 77FFFh
78000h to 7BFFFh
7C000h to 7CFFFh
7D000h to 7DFFFh
7E000h to 7FFFFh
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
1
1
0
1
1
1
X
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Sector Address Table (MBM29LV800BA)
Sector
A18
A17
A16
A15
A14
A13
A12
Address Range (×8) Address Range (×16)
Address
SA0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
0
00000h to 03FFFh
04000h to 05FFFh
06000h to 07FFFh
08000h to 0FFFFh
10000h to 1FFFFh
20000h to 2FFFFh
30000h to 3FFFFh
40000h to 4FFFFh
50000h to 5FFFFh
60000h to 6FFFFh
70000h to 7FFFFh
80000h to 8FFFFh
90000h to 9FFFFh
A0000h to AFFFFh
B0000h to BFFFFh
C0000h to CFFFFh
D0000h to DFFFFh
E0000h to EFFFFh
F0000h to FFFFFh
00000h to 01FFFh
02000h to 02FFFh
03000h to 03FFFh
04000h to 07FFFh
08000h to 0FFFFh
10000h to 17FFFh
18000h to 1FFFFh
20000h to 27FFFh
28000h to 2FFFFh
30000h to 37FFFh
38000h to 3FFFFh
40000h to 47FFFh
48000h to 4FFFFh
50000h to 57FFFh
58000h to 5FFFFh
60000h to 67FFFh
68000h to 6FFFFh
70000h to 77FFFh
78000h to 7FFFFh
SA1
SA2
0
1
1
SA3
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
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■ FUNCTIONAL DESCRIPTION
1. Read Mode
The MBM29LV800TA/BA have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or change CE pin from “H” or “L”
2. Standby Mode
There are two ways to implement the standby mode on the MBM29LV800TA/BA devices, one using both the CE
and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC 0.3 V.
Under this condition the current consumed is less than 5 μA. The device can be read with standard access time
(tCE) from either of these standby modes. During Embedded Algorithm operation, VCC active current (ICC2) is
required even CE = “H”.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS 0.3 V
(CE = “H” or “L”). Under this condition the current is consumed is less than 5 μA. Once the RESET pin is taken
high, the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
3. Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29LV800TA/800BA data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.
To activate this mode, MBM29LV800TA/800BA automatically switch themselves to low power mode when
MBM29LV800TA/800BA addresses remain stably during access fine of 150 ns. It is not necessary to control
CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 μA (CMOS Level).
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29LV800TA/800BA read-out the data for changed addresses.
4. Output Disable
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins
to be in a high impedance state.
5. Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, A6, and A-1. (See “MBM29LV800TA/BA Sector Protection Verify
Autoselect Codes Table” in “■DEVICE BUS OPERATION”.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29LV800TA/BA are erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in “MBM29LV800TA/BA Standard Command Definitions Table” (“■DEVICE
BUS OPERATION”). (Refer to “2. Autoselect Command” in “■COMMAND DEFINITIONS”.)
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Byte 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and (A0 = VIH) represents the device identifier
code (MBM29LV800TA = DAh and MBM29LV800BA = 5Bh for ×8 mode; MBM29LV800TA = 22DAh and
MBM29LV800BA = 225Bh for ×16 mode). These two bytes/words are given in “MBM29LV800TA/800BA Sector
Protection Verify Autoselect Codes Table” and “Extended Autoselect Code Table” (“■ DEVICE BUS
OPERATION”). All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity
bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See
“MBM29LV800TA/BA Sector Protection Verify Autoselect Codes Table” and “Extended Autoselect Code Table”
in “■ DEVICE BUS OPERATION”.)
6. Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
7. Sector Protection
The MBM29LV800TA/BA feature hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 18). The sector protection feature is enabled using programming
equipment at the user’s site. The devices are shipped with all sectors unprotected. Alternatively, Fujitsu may
program and protect sectors in the factory prior to shiping the device.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5 V), CE = VIL, and A6 = VIL. The sector addresses (A18, A17, A16, A15, A14, A13, and A12) should be set to
the sector to be protected. “Sector Address Tables (MBM29LV800TA) ”and “Sector Address Tables
(MBM29LV800BA) ” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE” define the sector address for each
of the nineteen (19) individual sectors. Programming of the protection circuitry begins on the falling edge of the
WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during
the WE pulse. See “13. AC Waveforms for Sector Protection Timing Diagram” in “■SWITCHING WAVEFORMS”
and “5. Sector Protection Algorithm” in “■FLOW CHART” for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while
(A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the
devices will read 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6
are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.
A-1 requires to apply to VIL on byte mode.
ItisalsopossibletodetermineifasectorisprotectedinthesystembywritinganAutoselectcommand. Performing
a read operation at the address location XX02h, where the higher order addresses (A18, A17, A16, A15, A14, A13,
and A12) are the desired sector address will produce a logical “1” at DQ0 for a protected sector. See
“MBM29LV800TA/800BA Sector Protection Verify Autoselect Codes Table” and “Extended Autoselect Code
Table” in “■ DEVICE BUS OPERATION” for Autoselect codes.
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8. Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29LV800TA/BA devices
in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage
(12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the 12 V is taken away from the RESETpin, all the previously protected sectors will be protected
again. See “14. Temporary Sector Unprotection Timing Diagram” in “■SWITCHING WAVEFORMS” and
“6. Temporary Sector Unprotection Algorithm” in “■FLOW CHART”.
9. RESET
Hardware Reset
The MBM29LV800TA/BA devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 μs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional tRH before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See “9. RESET/RY/BY Timing
Diagram” in “■SWITCHING WAVEFORMS” for the timing diagram. Refer to “8. Temporary Sector Unprotection”
for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
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■ COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the
read mode. “MBM29LV800TA/800BA Standard Command Definitions Table” in “■ DEVICE BUS OPERATION”
defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h)
commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands
are functionally equivalent, resetting the device to the read mode. Please note that commands are always written
at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.
1. Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset
operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The devices remain enabled for reads until the command
register contents are altered.
The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
2. Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read
cycle from address XX01h for ×16(XX02h for ×8) returns the device code (MBM29LV800TA = DAh and
MBM29LV800BA = 5Bh for ×8 mode; MBM29LV800TA = 22DAh and MBM29LV800BA = 225Bh for ×16 mode).
(See “MBM29LV800TA/800BA SectorProtection Verify AutoselectCodes Table” and “Extended AutoselectCode
Table” in “■ DEVICE BUS OPERATION”.) All manufacturer and device codes will exhibit odd parity with DQ7
defined as the parity bit. Sector state (protection or unprotection) will be informed by address XX02h for ×16
(XX04h for ×8).
Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a
logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin
mode on the protected sector. (See “MBM29LV800TA/BA User Bus Operations Tables (BYTE = VIH and
BYTE = VIL)” in “■ DEVICE BUS OPERATION”.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
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3. Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware
Sequence Flags Table”.) Therefore, the devices require that a valid address to the devices be supplied by the
system at this particular instance of time. Hence, Data Polling must be performed at the memory location which
is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“1. Embedded ProgramTM Algorithm” in “■FLOW CHART” illustrates the Embedded ProgramTM Algorithm using
typical command strings and bus operations.
4. Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (See “8. Write Operation Status”.) at which time the device returns to read the mode.
Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
“2. Embedded EraseTM Algorithm” in “■FLOW CHART” illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
5. Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data=30h) is latched on the rising edge of WE. After time-out of 50 μs from the rising edge of the last sector
erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29LV800TA/800BA
Standard Command Definitions Table” in “■ DEVICE BUS OPERATION”. This sequence is followed with writes
of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between
writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is
recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts
can be re-enabled after the last Sector Erase command is written. A time-out of 50 μs from the rising edge of
the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs
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within the 50 μs time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window
is still open, see “12. DQ3”, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend
during this time-out period will reset the devices to the read mode, ignoring the previous command string.
Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase
on those sectors and allow them to complete. (Refer to “8. Write Operation Status” for Sector Erase Timer
operation.)Loadingthesectorerasebuffermaybedoneinanysequenceandwithanynumberofsectors(0to18).
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The automatic sector erase begins after the 50 μs time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (See “8. Write Operation Status”.) at
which time the devices return to the read mode. Data polling must be performed at an address within any of
the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time
(Preprogramming)] × Number of Sector Erase
“2. Embedded EraseTM Algorithm” in “■FLOW CHART” illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
6. Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.
Writing the Erase Resume command resumes the erase operation. The addresses are DON’T CARES when
writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 μs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/
BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of
the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further
writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See “13. DQ2”.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
beprogrammedtosectorsthatarenoterase-suspended. Successivelyreadingfromtheerase-suspendedsector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-
suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or by the Toggle Bit I
(DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address
while DQ6 can be read from any address.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
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7. Extended Command
(1) Fast Mode
MBM29LV800TA/BA has Fast Mode function. This mode dispenses with the initial two unclock cycles required
in the standard program command sequence by writing Fast Mode command into the command register. In this
mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program
command. (Do not write erase command in this mode.) The read operation is also executed after exiting this
mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer
to “8. Embedded ProgramTM Algorithm for Fast Mode” in “■FLOW CHART” Extended algorithm.) The VCC active
current is required even CE = VIH during Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to “8.
Embedded ProgramTM Algorithm for Fast Mode” in “■FLOW CHART” Extended algorithm.)
(3) Extended Sector Protection
In addition to normal sector protection, the MBM29LV800TA/BA has Extended Sector Protection as extended
function. This function enable to protect sector by forcing VID on RESET pin and write a commnad sequence.
Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET
pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With
this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then,
the sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the
sector to be protected (recommend to set VIL for the other addresses pins), and write extended sector protect
command (60h). A sector is typically protected in 250 μs. To verify programming of the protection circuitry, the
sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a
command (40h). Following the command write, a logical “1” at device output DQ0 will produce for protected
sector in the read operation. If the output data is logical “0”, please repeat to write extended sector protect
command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH.
8. Write Operation Status
Hardware Sequence Flags Table
Status
DQ7
DQ7
0
DQ6
DQ5
0
DQ3
0
DQ2
1
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
0
1
Toggle*1
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
0
Toggle
Data
1*2
In Progress
Erase
Erase Suspend Read
Suspended Mode (Non-Erase Suspended Sector)
Data
DQ7
Data
Data Data
Erase Suspend Program
(Non-Erase Suspended Sector)
Toggle
0
0
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7
0
Toggle
Toggle
1
1
0
1
1
Exceeded
Time Limits
N/A
Erase
Erase Suspend Program
DQ7
Toggle
1
0
N/A
Suspended Mode (Non-Erase Suspended Sector)
*1: Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle.
*2: Reading from non-erase suspend sector address indicates logic “1” at the DQ2 bit.
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9. DQ7
Data Polling
The MBM29LV800TA/BA devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in “3. Data Polling Algorithm” (“■FLOW CHART”).
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29LV800TA/BA data pins (DQ7) may change asynchronously while the output
enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant
of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the
DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm
operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0
to DQ7 will be read on the successive read attempts.
TheDataPollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm, EmbeddedEraseAlgorithm
or sector erase time-out. (See “Hardware Sequence Flags Table”.)
See “6. AC Waveforms for Data Polling during Embedded Algorithm Operations” in “■SWITCHING
WAVEFORMS” for the Data Polling timing specifications and diagrams.
10. DQ6
Toggle Bit I
The MBM29LV800TA/BA also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 μs and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
See“7.ACWaveformsforToggleBitIduringEmbeddedAlgorithmOperations”in“■SWITCHINGWAVEFORMS”
for the Toggle Bit I timing specifications and diagrams.
11. DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
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The OE and WE pins will control the output disable functions as described in “MBM29LV800TA/BA User Bus
Operations Tables (BYTE = VIH and BYTE = VIL)” in “■ DEVICE BUS OPERATION”.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the
DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
12. DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on
the second status check, the command may not have been accepted.
See “Hardware Sequence Flags Table”.
13. DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also “Hardware Sequence Flags Table” and “15. DQ2 vs. DQ6” in
“■SWITCHING WAVEFORMS”.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
14. Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row
to determin whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, this indicates that the device has completed the program or erase operation.
The system can read array data on DQ7 to DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see “11. DQ5”) . If it is the system should then determine
again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high.
If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If
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Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
it is still toggling, the device did not complete the operation successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine
the status of the operation (see “4. Toggle Bit Algorithm” in “■ FLOW CHART”) .
Toggle Bit Status Table
Mode
DQ7
DQ7
0
DQ6
DQ2
1
Program
Erase
Toggle
Toggle
Toggle*1
Erase-Suspend Read
(Erase-Suspended Sector)
1
1
Toggle
1*2
Erase-Suspend Program
DQ7
Toggle
*1: Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle.
*2: Reading from non-erase suspend sector address indecates logic “1” at the DQ2 bit.
15. RY/BY
Ready/Busy
The MBM29LV800TA/BA provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29LV800TA/BA are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. Refer to “8. RY/BY Timing Diagram during Program/Erase Operations”
and “9. RESET/RY/BY Timing Diagram” in “■SWITCHING WAVEFORMS” for a detailed timing diagram. The
RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to VCC; multiples of devices may
be connected to the host system via more than one RY/BY pin in parallel.
16. Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV800TA/BA devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0
to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin
becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer
to “10. Timing Diagram for Word Mode Configuration” , “11. Timing Diagram for Byte Mode Configuration” and
“12. BYTE Timing Diagram for Write Operations” in “■SWITCHING WAVEFORMS” for the timing diagram.
17. Data Protection
The MBM29LV800TA/BA are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
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sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
18. Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
19. Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
20. Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
21. Power-Up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
22. Sector Protection
Device user is able to protect each sector individually to store and protect data. Protection circuit voids both
write and erase commands that are addressed to protected sectors.
Any commands to write or erase addressed to protected sector are ignore (see “7. Sector Protection”
in “■ FUNCTIONAL DESCRIPTION”) .
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Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min
–55
–40
–0.5
–0.5
–0.5
Max
+125
+85
Storage Temperature
Ambient Temperature with Power Applied
Tstg
TA
°C
°C
V
Voltage with respect to Ground All pins except A9, OE, RESET *1,*2 VIN,VOUT
VCC+0.5
+5.5
Power Supply Voltage*1
A9, OE, and RESET *1,*3
VCC
VIN
V
+13.0
V
*1 : Voltage is defined on the basis of VSS = GND = 0 V.
*2 : Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns.
*3 : Minimum DC input voltage on A9, OE and RESET pins is –0.5 V. During voltage transitions, A9, OE and RESET
pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply
voltage (VIN – VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V
which may overshoot to +14.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING RANGES
Value
Parameter
Ambient Temperature
Power Supply Voltage*
Symbol
TA
Conditions
Unit
Min
–40
Max
+85
⎯
°C
V
MBM29LV800TA/BA-70
MBM29LV800TA/BA-90
+3.0
+2.7
+3.6
+3.6
VCC
V
* : Voltage is defined on the basis of VSS = GND = 0 V.
Note: Operating ranges define those limits between which the functionality of the devices are guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
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MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
■ MAXIMUM OVERSHOOT /MAXIMUM UNDERSHOOT
20 ns
20 ns
+0.6 V
–0.5 V
–2.0 V
20 ns
Figure 1 Maximum Undershoot Waveform
20 ns
V CC +2.0 V
V CC +0.5 V
+2.0 V
20 ns
20 ns
Figure 2 Maximum Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
V CC +0.5 V
20 ns
20 ns
Note: This waveform is applied for A9, OE, and RESET.
Figure 3 Maximum Overshoot Waveform 2
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MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
■ DC CHARACTERISTICS
Value
Typ
—
Parameter
Symbol
Test Conditions
Unit
Min
–1.0
–1.0
Max
+1.0
+1.0
Input Leakage Current
Output Leakage Current
ILI
VIN = VSS to VCC, VCC = VCC Max
VOUT = VSS to VCC, VCC = VCC Max
μA
μA
ILO
—
A9, OE, RESET Inputs Leakage
Current
VCC = VCC Max
A9, OE, RESET = 12.5 V
ILIT
—
—
—
—
35
μA
Byte
22
25
12
15
35
CE = VIL, OE = VIH,
f=10 MHz
Word
mA
VCC Active Current *1
ICC1
Byte
CE = VIL, OE = VIH,
f=5 MHz
Word
—
—
mA
VCC Active Current *2
VCC Current (Standby)
ICC2
ICC3
CE = VIL, OE = VIH
—
—
—
1
mA
VCC = VCC Max, CE = VCC 0.3 V,
RESET = VCC 0.3 V
5
5
μA
VCC = VCC Max,
RESET = VSS 0.3 V
VCC Current (Standby, Reset)
ICC4
ICC5
—
—
1
1
μA
VCC = VCC Max, CE = VSS 0.3 V,
RESET = VCC 0.3 V
VIN = VCC 0.3 V or VSS ± 0.3 V
VCC Current
5
µA
(Automatic Sleep Mode) *3
Input Low Voltage
Input High Voltage
VIL
VIH
—
—
–0.5
2.0
—
—
0.6
V
V
VCC+0.3
Voltage for Autoselect and Sector
Protection (A9, OE, RESET) *4,*5
VID
—
11.5
12
12.5
V
Output Low Voltage
VOL
VOH1
VOH2
VLKO
IOL = 4.0 mA, VCC = VCC Min
IOH = –2.0 mA, VCC = VCC Min
IOH = –100 μA
—
2.4
—
—
0.45
—
V
V
V
V
Output High Voltage
VCC–0.4
2.3
—
—
Low VCC Lock-Out Voltage
—
2.4
2.5
*1: The ICC current listed includes both the DC operating current and the frequency dependent component (at 10
MHz).
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
*4: This timing is only for Sector Protection operation and Autoselect mode.
*5: (VID – VCC) do not exceed 9 V.
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Retired ProductꢀDS05-20845-7E_July 31, 2007
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■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Value *
Symbol
Parameter
Test Setup
-70
-90
Unit
JEDEC Standard
Min
Max
Min
Max
Read Cycle Time
tAVAV
tAVQV
tRC
—
70
—
90
—
ns
ns
CE = VIL
OE = VIL
Address to Output Delay
tACC
—
70
—
90
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
OE = VIL
—
—
—
—
70
30
25
25
—
—
—
—
90
35
30
30
ns
ns
ns
ns
—
—
—
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First
tAXQX
—
tOH
—
—
—
0
—
20
5
0
—
20
5
ns
μs
ns
RESET Pin Low to Read Mode
tREADY
—
—
—
—
tELFL
tELFH
CE to BYTE Switching Low or High
—
Note: Test Conditions:
Output Load: 1 TTL gate and 30 pF (MBM29LV800TA/BA-70)
1 TTL gate and 100 pF (MBM29LV800TA/BA-90)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or 3.0 V
Timing measurement reference level
Input: 1.5 V
Output:1.5 V
VCC
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = IN3064
or Equivalent
Notes : CL = 30 pF including jig capacitance (MBM29LV800TA/BA-70)
CL = 100 pF including jig capacitance (MBM29LV800TA/BA-90)
Figure 4 Test Conditions
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Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
• Write/Erase/Program Operations
Parameter
Symbol
-70
-90
Unit
Standard
JEDEC
tAVAV
Min Typ Max Min Typ Max
Write Cycle Time
tWC
tAS
70
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
25
70
90
70
90
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
30
90
90
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
sec
µs
ns
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
tAVWL
tWLAX
tDVWH
tWHDX
—
tAH
45
35
0
45
45
0
tDS
Data Hold Time
tDH
tOES
Output Enable Setup Time
0
0
Read
0
0
Output Enable
Hold Time
—
tOEH
Toggle and Data Polling
10
0
10
0
Read Recover Time Before Write
Read Recover Time Before Write
CE Setup Time
tGHWL
tGHEL
tELWL
tWLEL
tWHEH
tEHWH
tWLWH
tELEH
tWHWL
tEHEL
tGHWL
tGHEL
tCS
0
0
0
0
WE Setup Time
tWS
0
0
CE Hold Time
tCH
0
0
WE Hold Time
tWH
0
0
Write Pulse Width
tWP
35
35
25
25
⎯
⎯
⎯
50
500
4
45
45
25
25
⎯
⎯
⎯
50
500
4
CE Pulse Width
tCP
Write Pulse Width High
CE Pulse Width High
tWPH
tCPH
Byte
Programming
Operation
tWHWH1
tWHWH1
Word
16
1
16
1
Sector Erase Operation *1
tWHWH2
—
tWHWH2
tVCS
VCC Setup Time
Rise Time to VID *2
Voltage Transition Time *2
Write Pulse Width *2
OE Setup Time to WE Active *2
CE Setup Time to WE Active *2
Recover Time From RY/BY
RESET Pulse Width
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
—
tVIDR
tVLHT
tWPP
tOESP
tCSP
—
—
100
4
100
4
—
—
4
4
—
tRB
0
0
—
tRP
500
200
⎯
⎯
⎯
⎯
500
200
⎯
⎯
⎯
⎯
RESET Hold Time Before Read
BYTE Switching Low to Output High-Z
BYTE Switching High to Output Active
Program/Erase Valid to RY/BY Delay
Delay Time from Embedded Output Enable
—
tRH
—
tFLQZ
tFHQV
tBUSY
tEOE
—
—
—
*1: This does not include the preprogramming time.
*2: This timing is for Sector Protection operation.
33
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
■ ERASE AND PROGRAMMING PERFORMANCE
Limit
Parameter
Unit
Comments
Min
Typ
Max
Excludes programming time
prior to erasure
Sector Erase Time
—
1
10
s
Word Programming Time
Byte Programming Time
—
—
16
8
360
300
μs
μs
Excludes system-level
overhead
Excludes system-level
overhead
Chip Programming Time
Program/Erase Cycle
—
8.4
—
25
—
s
100,000
cycle
—
■ PIN CAPACITANCE
• TSOP(1)
Parameter
Symbol
Test Setup
Typ
7.5
Max
9.5
Unit
pF
Input Capacitance
CIN
VIN = 0
Output Capacitance
Control Pin Capacitance
COUT
CIN2
VOUT = 0
VIN = 0
8.0
10.0
13.0
pF
10.0
pF
Notes: • Test conditions TA = +25°C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
• SOP
Parameter
Symbol
CIN
Test Setup
Typ
7.5
Max
9.5
Unit
pF
Input Capacitance
VIN = 0
Output Capacitance
Control Pin Capacitance
COUT
CIN2
VOUT = 0
VIN = 0
8.0
10.0
13.0
pF
10.0
pF
Notes: • Test conditions TA = +25°C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
• FBGA
Parameter
Symbol
CIN
Test Setup
Typ
7.5
Max
9.5
Unit
pF
Input Capacitance
VIN = 0
Output Capacitance
Control Pin Capacitance
COUT
CIN2
VOUT = 0
VIN = 0
8.0
10.0
13.0
pF
10.0
pF
Notes: • Test conditions TA = +25°C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
• SCSP
Parameter
Symbol
CIN
Test Setup
Typ
7.5
Max
9.5
Unit
pF
Input Capacitance
VIN = 0
Output Capacitance
Control Pin Capacitance
COUT
CIN2
VOUT = 0
VIN = 0
8.0
10.0
13.0
pF
10.0
pF
Notes: • Test conditions TA = +25°C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
34
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
■ SWITCHING WAVEFORMS
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
“H” or “L”
Any Change
Permitted
Changing
State
Unknown
Does Not
Apply
Center Line is
High-
Impedance
“Off” State
1. AC Waveforms for Read Operations
tRC
Address
Address Stable
tACC
CE
OE
tOE
tDF
tOEH
WE
tOH
tCE
High-Z
High-Z
Outputs
Output Valid
35
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
2. AC Waveforms for Hardware Reset/Read Operations
tRC
Address
Address Stable
tACC
tRH
RESET
Outputs
tOH
High-Z
Output Valid
3. AC Waveforms for Alternate WE Controlled Program Operations
Data Polling
3rd Bus Cycle
Address
555h
PA
PA
tWC
tRC
tAS
tAH
CE
tCH
tCS
tCE
OE
tWP
tWPH
tOE
tGHWL
tWHWH1
WE
tDF
tOH
tDS
tDH
A0h
PD
DQ7
DOUT
DOUT
Data
Notes: • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
36
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
4. AC Waveforms for Alternate CE Controlled Program Operations
3rd Bus Cycle
Data Polling
Address
WE
PA
PA
555h
tWC
tAS
tAH
tWS
tWH
OE
CE
tGHEL
tCP
tCPH
tWHWH1
tDS
tDH
A0h
PD
DQ7
DOUT
Data
Notes: • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
37
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
5. AC Waveforms Chip/Sector Erase Operations
2AAh
555h
555h
Address
555h
2AAh
SA*
tWC
tAS
tAH
CE
tCS
tCH
OE
tWP
tWPH
tGHWL
WE
tDS
tDH
10h for Chip Erase
10h/
30h
AAh
55h
80h
AAh
55h
Data
tVCS
VCC
:
*
SA is the sector address for Sector Erase. Addresses = 555h (Word), AAAh (Byte)
for Chip Erase.
Note: These waveforms are for the ×16 mode. The addresses differ from ×8 mode.
38
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
6. AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tCH
tOE
tDF
OE
tOEH
WE
tCE
*
High-Z
High-Z
DQ7 =
Data
Data
DQ7
DQ7
Valid Data
tWHWH1 or 2
DQ
0
to DQ
6
DQ0 to DQ6
DQ0 to DQ6 = Output Flag
Valid Data
tEOE
*: DQ7 = Valid Data (The device has completed the Embedded operation).
7. AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
CE
tOEH
WE
tOES
OE
*
DQ
6
=
DQ6
Data
DQ
6
= Toggle
DQ
6
= Toggle
Valid
Stop Toggling
tOE
*: DQ6 stops toggling (The device has completed the Embedded operation).
39
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
8. RY/BY Timing Diagram during Program/Erase Operations
CE
Rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
9. RESET/RY/BY Timing Diagram
WE
RESET
tRP
tRB
RY/BY
tREADY
10. Timing Diagram for Word Mode Configuration
CE
tCE
BYTE
Data Output
(DQ14 to DQ0)
Data Output
(DQ7 to DQ0)
tELFH
DQ14 to DQ0
DQ15/A -1
tFHQV
A -1
DQ15
40
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
11. Timing Diagram for Byte Mode Configuration
CE
BYTE
tELFL
Data Output
(DQ14 to DQ0)
Data Output
(DQ7 to DQ0)
DQ14 to DQ0
tACC
A -1
DQ15
tFLQZ
DQ15/A -1
12. BYTE Timing Diagram for Write Operations
Falling edge of the last write signal
CE or WE
BYTE
Input
Valid
tAS
tAH
41
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
13. AC Waveforms for Sector Protection Timing Diagram
A18, A17, A16
SPAX
SPAY
A15, A14
A13, A12
A0
A1
A6
VID
VIH
A9
tVLHT
VID
VIH
OE
WE
CE
tVLHT
tVLHT
tVLHT
tWPP
tOESP
tCSP
Data
VCC
01h
tVCS
tOE
SPAX:Sector Address for initial sector
SPAY:Sector Address for next sector
Note: A-1 is VIL on byte mode.
42
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
14. Temporary Sector Unprotection Timing Diagram
VCC
tVIDR
tVCS
tVLHT
VID
VIH
RESET
CE
WE
tVLHT
tVLHT
Program or Erase Command Sequence
Unprotection Period
RY/BY
15. DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
WE
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE or CE
Note DQ2 is read from the erase-suspended sector.
43
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
16. Extended Sector Protection Timing Diagram
VCC
tVCS
RESET
Add
tVLHT
tVIDR
SPAX
SPAX
SPAY
A0
A1
A6
CE
OE
TIME-OUT
WE
Data
60h
60h
40h
01h
60h
tOE
SPAX : Sector Address to be protected
SPAY : Next Sector Address to be protected
TIME-OUT : Time-Out window = 250 μs (Min)
44
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
■ FLOW CHART
1. Embedded ProgramTM Algorithm
EMBEDDED ALGORITHM
Start
Write Program
Command Sequence
(See Below)
Data Polling
Embedded
Program
Algorithm
in progress
No
Verify Data
?
Yes
No
Last Address
?
Increment Address
Yes
Programming Completed
Program Command Sequence (Address/Command) :
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
Notes: • The sequence is applied for × 16 mode.
• The addresses differ from × 8 mode.
45
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
2. Embedded EraseTM Algorithm
EMBEDDED ALGORITHM
Start
Write Erase
Command Sequence
(See Below)
Data Polling
Embedded
Erase
Algorithm
in Progress
No
Data = FFh
?
Yes
Erasure Completed
Chip Erase Command Sequence
(Address/Command) :
Individual Sector/Multlple Sector
Erase Command Sequence
(Address/Command) :
555h/AAh
2AAh/55h
555h/80h
555h/AAh
2AAh/55h
555h/10h
555h/AAh
2AAh/55h
555h/80h
555h/AAh
2AAh/55h
Sector Address
/30h
Sector Address
/30h
Additional sector
erase commands
are optional.
Sector Address
/30h
Notes: • The sequence is applied for × 16 mode.
• The addresses differ from × 8 mode.
46
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
3. Data Polling Algorithm
Start
Read Byte
(DQ7 to DQ0)
Addr. = VA
VA = Address for programming
= Any of the sector addresses within
the sector being erased during
sector erase or multiple sector
erases operation
Yes
DQ 7 = Data?
No
= Any of the sector addresses within
the sector not being protected
during chip erase operation
No
DQ 5 = 1?
Yes
Read Byte
(DQ7 to DQ0)
Addr. = VA
Yes
DQ 7 = Data?
*
No
Fail
Pass
*: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
47
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
4. Toggle Bit Algorithm
Start
Read (DQ
7 to DQ0)
Addr. = “H” or “L”
*1
Read (DQ7 to DQ0)
Addr. = “H” or “L”
DQ6 =
No
Toggle?
Yes
No
DQ5 = 1 ?
Yes
*1, *2
Read DQ7 to DQ0
Twice
Addr. = “H” or “L”
No
DQ6 =
Toggle?
Yes
Program/Erase
Operation Not
Complete. Write
Reset Command
Program/Erase
Operation
Complete
*1: Read toggle bit twice to determine whether it is togglimg.
*2: Recheck toggle bit because it may stop toggling as DQ5 changes to “1”.
48
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
5. Sector Protection Algorithm
Start
Setup Sector Addr.
(A18, A17, A16, A15, A14, A13, A12
)
PLSCNT = 1
OE
=
=
=
V ID, A 9
=
V ID,
V IL, RESET
V IL, A 1
A 6
=
CE
= V IH
A 0
= V IH
Activate WE Pulse
Time out 100 μs
Increment PLSCNT
WE = V IH, CE = OE = V IL
(A 9 should remain V ID
)
Read from Sector
(Addr. = SPA, A 0
=
V IL,
A 1 V IH, A
=
6
= V IL)*
No
No
PLSCNT = 25?
Yes
Data = 01h?
Yes
Yes
Remove V ID from A
Write Reset Command
9
Protect Another Sector?
No
Device Failed
Remove V ID from A
9
Write Reset Command
Sector Protection
Completed
*: A-1 is V IL on byte mode.
49
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
6. Temporary Sector Unprotection Algorithm
Start
RESET = VID*1
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed*2
*1 : All protected sectors are unprotected.
*2 : All previously protected sectors are protected once again.
50
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
7. Extended Sector Protection Algorithm
FAST MODE ALGORITHM
Start
RESET = VID
Wait to 4 μs
Device is Operating in
Temporary Sector
Unprotection Mode
No
Extended Sector
Protection Entry?
Yes
To Setup Sector Protection
Write XXXh/60h
PLSCNT = 1
To Sector Protection
Write SPA/60h
(Addr. = SPA, A0 = VIL,
A1 = VIH, A6 = VIL)
Time Out 250 μs
Increment PLSCNT
To Verify Sector Protection
Write SPA/40h
Setup Next Sector Address
(Addr. = SPA, A0 = VIL,
A1 = VIH, A6 = VIL)
Read from Sector Address
(Addr. = SPA, A0 = VIL,
A1 = VIH, A6 = VIL)
No
No
Yes
Data = 01h?
Yes
PLSCNT = 25?
Yes
Remove VID from RESET
Write Reset Command
Protection Other Sector
?
No
Remove VID from RESET
Write Reset Command
Device Failed
Sector Protection
Completed
51
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
8. Embedded ProgramTM Algorithm for Fast Mode
FAST MODE ALGORITHM
Start
555h/AAh
Set Fast Mode
2AAh/55h
555h/20h
XXXh/A0h
Program Address/Program Data
Data Polling
No
In Fast Program
Verify Data?
Yes
No
Last Address
?
Increment Address
Yes
Programming Completed
XXXh/90h
XXXh/F0h
Reset Fast Mode
Notes: • The sequence is applied for × 16 mode.
• The addresses differ from × 8 mode.
52
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
■ ORDERING INFORMATION
Part No.
Package
Access Time
Sector Architecture
MBM29LV800TA-70PF
MBM29LV800TA-90PF
44-pin plastic SOP
(FPT-44P-M16)
70
90
48-pin plastic TSOP (1)
(FPT-48P-M19)
MBM29LV800TA-70PFTN
MBM29LV800TA-90PFTN
70
90
(Normal Bend)
48-pin plastic TSOP (1)
(FPT-48P-M20)
MBM29LV800TA-70PFTR
MBM29LV800TA-90PFTR
70
90
Top Sector
(Reverse Bend)
MBM29LV800TA-70PBT-SF2
MBM29LV800TA-90PBT-SF2
48-pin plastic FBGA
(BGA-48P-M12)
70
90
48-pin plastic SCSP
(WLP-48P-M03)
MBM29LV800TA-90PW
90
MBM29LV800BA-70PF
MBM29LV800BA-90PF
44-pin plastic SOP
(FPT-44P-M16)
70
90
48-pin plastic TSOP (1)
(FPT-48P-M19)
MBM29LV800BA-70PFTN
MBM29LV800BA-90PFTN
70
90
(Normal Bend)
48-pin plastic TSOP (1)
(FPT-48P-M20)
MBM29LV800BA-70PFTR
MBM29LV800BA-90PFTR
70
90
Bottom Sector
(Reverse Bend)
MBM29LV800BA-70PBT-SF2
MBM29LV800BA-90PBT-SF2
48-pin plastic FBGA
(BGA-48P-M12)
70
90
48-pin plastic SCSP
(WLP-48P-M03)
MBM29LV800BA-90PW
90
53
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
MBM29LV800
T
A
-70
PFTN
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP) Normal Bend
PFTR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Bend
PF =
PBT =
44-Pin Small Outline Package
48-Ball Fine Pitch Ball Grid Array
Package (FBGA:BGA-48P-M02)
PBT-SF2 =48-Ball Fine Pitch Ball Grid Array
Package (FBGA:BGA-48P-M12)
PW=
48-Ball Super Chip Size Package
(SCSP)
SPEED OPTION
See Product Selector Guide
Device Revision
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29LV800
8Mega-bit (1M × 8-Bit or 512K × 16-Bit) CMOS Flash Memory
3.0 V-only Read, Program, and Erase
54
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
■ PACKAGE DIMENSIONS
Note 1 : * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) .
Note 2 : Pins width and pins thickness include plating thickness.
48-pin plastic TSOP(1)
(FPT-48P-M19)
LEAD No.
1
48
INDEX
Details of "A" part
0.25(.010)
0~8˚
0.60 0.15
(.024 .006)
24
25
20.00 0.20
(.787 .008)
* 12.00 0.20
(.472 .008)
* 18.40 0.20
(.724 .008)
1.10 +0.10
–
0.05
.043 +.004
–.002
(Mounting
height)
0.10 0.05
(.004 .002)
(Stand off height)
"A"
0.50(.020)
TYP
0.10(.004)
0.17 +0.03
.007 +.001
–
0.08
0.22 0.05
(.009 .002)
M
0.10(.004)
–
.003
C
2002 FUJITSU LIMITED F48029S-c-5-5
Dimensions in mm (inches)
Note 1 : * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) .
Note 2 : Pins width and pins thickness include plating thickness.
48-pin plastic TSOP(1)
(FPT-48P-M20)
LEAD No.
1
48
Details of "A" part
INDEX
0.60 0.15
(.024 .006)
0~8
˚
0.25(.010)
24
25
0.17 –+00..0083
.007 –+..000031
0.22 0.05
(.009 .002)
M
0.10(.004)
0.10 0.05
(.004 .002)
0.50(.020)
TYP
0.10(.004)
(Stand off height)
1.10 –+00..0150
"A"
* 18.40 0.20
(.724 .008)
.043 –+..000024
(Mounting height)
20.00 0.20
(.787 .008)
* 12.00 0.20(.472 .008)
C
2002 FUJITSU LIMITED F48030S-c-5-6
Dimensions in mm (inches)
(Continued)
55
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
Note1: Pins width and pins thickness include plating thickness.
Note2: * This dimension includes resin protrusion.
44-pin plastic SOP
(FPT-44P-M16)
* 28.45 +–00..2205 1.120 +–..000180
0.17 –+00..0043
.007 +–..000021
44
23
16.00 0.20
(.630 .008)
Details of "A" part
2.35 0.15
13.00 0.10
(.512 .004)
(Mounting height)
INDEX
(.093 .006)
0.25(.010)
"A"
1
22
0~8°
0.42 –+00..0078
.017 +–..00002381
1.27(.050)
M
0.13(.005)
0.80 0.20
(.031 .008)
0.20 –+00..1150
.008 –+..000064
0.88 0.15
(Stand off)
(.035 .006)
0.10(.004)
Dimensions in mm (inches)
C
2001 FUJITSU LIMITED F44023S-c-5-5
48-pin plastic FBGA
(BGA-48P-M12)
9.00 0.20(.354 .008)
1.05 +–00..1105 .041 –+..000046
(Mounting height)
5.60(.220)
0.80(.031)TYP
0.38 0.10(.015 .004)
(Stand off)
6
5
4
3
2
1
INDEX
6.00 0.20
(.236 .008)
4.00(.157)
H
G
F
E
D
C
B
A
C0.25(.010)
48-ø0.45 0.10
M
ø0.08(.003)
(48-ø.018 .004)
0.10(.004)
Dimensions in mm (inches)
C
2001 FUJITSU LIMITED B48012S-c-3-3
(Continued)
56
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
(Continued)
48-pin plastic SCSP
(WLP-48P-M03)
(3.50=0.50x7)
((.138=.020x7))
7.06 0.10(.278 .004)
0.50(.020)
TYP
Y
(0.13SQ)
((.005SQ))
(INDEX)
3.52 0.10
(.139 .004)
(2.50=0.50x5)
((.098=.020x5))
(0.25(.010)
0.50(.020)
TYP
(2.25)
X
((.089))
INDEX AREA
(LASER MARKING)
4-Ø0.13(4-Ø.005)
1.00(.039)
Max.
48-Ø0.35 0.10
(48-Ø.014 .004)
M
XYZ
0.08(.003)
0.25(.010)
Min.
0.10(.004)
Z
Z
(Stand off)
Dimensions in mm (inches)
C
2001 FUJITSU LIMITED W48003S-c-1-1
57
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
MEMO
58
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
Revision History
Revision DS05-20845-7E(July 31, 2007)
The following comment is added.
This product has been retired and is not recommended for new designs. Availability of this
document is retained for reference and historical purposes only.
59
Retired ProductꢀDS05-20845-7E_July 31, 2007
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90
FUJITSU LIMITED
For further information please contact:
Japan
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The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
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Electronic Devices
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http://edevice.fujitsu.com/
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presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
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any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
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The products described in this document are designed, developed
and manufactured as contemplated for general use, including
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and manufactured as contemplated (1) for use accompanying fatal
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extremely high reliability (i.e., submersible repeater and artificial
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Please note that Fujitsu will not be liable against you and/or any
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above-mentioned uses of the products.
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Asia Pacific
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
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#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-6281-0770
Fax: +65-6281-0220
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
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Korea
FUJITSU MICROELECTRONICS KOREA LTD.
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Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
F0211
© FUJITSU LIMITED Printed in Japan
Retired ProductꢀDS05-20845-7E_July 31, 2007
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