MBM29PDS322BE10PBT_技术文档

MBM29PDS322TE10/11/

MBM29PDS322BE10/11

MBM29PDS322TE10/11/MBM29PDS322BE10/11Cover

Data Sheet (Retired Product)

Sheet

This product has been retired and is not recommended for new designs. Availability of this document is retained for reference

and historical purposes only.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been

made are the result of normal data sheet improvement and are noted in the document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number MBM29PDS322TE/BE

Revision DS05-20889-6E

Issue Date July 31, 2007

D a t a S h e e t ( R e t i r e d P r o d u c t )

This page left intentionally blank.

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MBM29PDS322TE/BE_DS05-20889-6E July 31, 2007

TM

SPANSION Flash Memory

Data Sheet

September 2003

This document specifies SPANSION^TMmemory products that are now offered by both Advanced Micro Devices and

Fujitsu. Although the document is marked with the name of the company that originally developed the specification,

these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a SPANSION^TMproduct. Future routine

revisions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these

products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about SPANSION^TMmemory

solutions.

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20889-6E

FLASH MEMORY

CMOS

32M (2M × 16) BIT Page Dual Operation

MBM29PDS322TE^10/11

MBM29PDS322BE10/11

■ DESCRIPTION

The MBM29PDS322TE/BE is 32M-bit, 1.8 V-only Flash memory organized as 2M words of 16 bits each. The

device is offered in 63-ball FBGA package. This device is designed to be programmed in system with standard

system 1.8 V V^CCsupply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can

also be reprogrammed in standard EPROM programmers.

The device is organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory

arrays for operations are concerned. It is the Fujitsu’s standard 1.8 V only Flash memories with the additional

capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded

write (either a program or an erase) operation is simultaneously taking place on the other bank.

(Continued)

■ PRODUCT LINE-UP

MBM29PDS322TE/BE

Part No.

10

11

+0.2 V

2.0 V

–0.2 V

Power Supply Voltage V^CC(V)

Max Random Address Access Time (ns)

Max Page Address Access Time (ns)

Max CE Access Time (ns)

100

40

115

50

100

35

115

45

Max OE Access Time (ns)

■ PACKAGE

63-ball plastic FBGA

(BGA-63P-M01)

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(Continued)

The device provides truly high performance non-volatile Flash memory solution. The device offers fast page

access times of 45 ns with random access times of 100 ns and 115 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write

enable (WE), and output enable (OE) controls. The page size is 4 words.

The device is pin and command set compatible with JEDEC standard E²PROMs. Commands are written to the

command register using standard microprocessor write timings. Register contents serve as input to an internal

state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses

and data needed for the programming and erase operations. Reading data out of the device is similar to reading

from 5.0 V and 12.0 V Flash or EPROM devices.

The device is programmed by executing the program command sequence. This will invoke the Embedded

Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies

proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is

accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which

is an internal algorithm that automatically preprograms the array if it is not already programmed before executing

the erase operation. During erase, the device automatically time the erase pulse widths and verify proper cell

margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The device is erased when shipped from the factory.

The device features single 1.8 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V^CCdetector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,

by the Toggle Bit feature on DQ⁶, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the device internally resets to the read mode.

The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program

Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read

mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the

Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode

and will have erroneous data stored in the address locations being programmed or erased. These locations

need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up

firmware from the Flash memory.

Fujitsu’s Flash technology combines years of EPROM and E²PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The device memory electrically erase the entire chip or all bits within

a sector simultaneously via Fowler-Nordhiem tunneling. The words are programmed one word at a time using

the EPROM programming mechanism of hot electron injection.

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■ FEATURES

• 0.23 μm Process Technology

• Simultaneous Read/Write Operations (Dual Bank)

Host system can program or erase in one bank, and then read immediately and simultaneously from the other

bank with zero latency between read and write operations.

Read-while-erase

Read-while-program

• High Performance Page Mode

45 ns maximum page access time (100 ns random access time)

4 words Page Size

• Single 1.8 V Read, Program, and Erase

Minimized system level power requirements

• Compatible with JEDEC-standard Commands

Use the same software commands as E²PROMs.

• Compatible with JEDEC-standard World-wide Pinouts

63-ball FBGA (Package suffix: PBT)

• Minimum 100,000 Program/Erase Cycles

• Sector Erase Architecture

Eight 4 K word and sixty-three 32 K word sectors in word mode

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• HiddenROM Region

32 K word of HiddenROM, accessible through a new “HiddenROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC Input Pin

At V^IL, allows protection of boot sectors, regardless of sector protection/unprotection status.

At V^ACC, increases program performance.

• Embedded Erase^TM* Algorithms

Automatically pre-programs and erases the chip or any sector.

• Embedded Program^TM* Algorithms

Automatically writes and verifies data at specified address.

• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion

• Ready/Busy Output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic Sleep Mode

When addresses remain stable, automatically switch themselves to low power mode.

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device.

• Sector Group Protection

Hardware method disables any combination of sector groups from program or erase operations.

• Sector Group Protection Set Function by Extended Sector Group Protection Command

• Fast Programming Function by Extended Command

• Temporary Sector Group Unprotection

Temporary sector group unprotection via the RESET pin.

* : Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

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MBM29PDS322TE/BE Device Bank Division

Bank 1

Sector Sizes

Bank 2

Sector Sizes

Device

Part Number

Organization

Megabits

Eight 4 K word,

seven 32 K word

MBM29PDS322TE/BE

× 16

4 Mbit

28 Mbit

Fifty-six 32 K word

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■ PIN ASSIGNMENT

(TOP VIEW)

(Marking Side)

A8

B8

M8

L8

*

N.C.

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

N.C.

A¹³

A12

A14

A15

A16

DQ15

VSS

N.C.

C6

A⁹

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

WE

RESET

N.C.

A¹⁹

DQ5

DQ12

VCC

DQ4

C4

D4

E4

F4

G4

H4

J4

K4

RY/BY WP/ACC

A¹⁸

A20

DQ2

DQ10

DQ11

DQ3

C3

A⁷

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

A2

C2

A³

D2

A4

E2

A2

F2

A1

G2

A0

H2

CE

J2

K2

L2

M2

*

N.C.

OE

VSS

N.C.

A1

B1

L1

M1

*

N.C.

(BGA-63P-M01)

*: Peripheral balls on each corner are shorted together via the substrate but not connected to the die.

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■ PIN DESCRIPTION

MBM29PDS322TE/BE Pin Configuration

Function

Pin name

A²⁰to A0

DQ¹⁵to DQ0

CE

Address Inputs

Data Inputs/Outputs

Chip Enable

OE

Output Enable

WE

Write Enable

RY/BY

RESET

WP/ACC

N.C.

Ready/Busy Output

Hardware Reset Pin/Temporary Sector Group Unprotection

Hardware Write Protection/Program Acceleration

No Internal Connection

Device Ground

V^SS

V^CC

Device Power Supply

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■ BLOCK DIAGRAM

VCC

VSS

Bank 2

address

Cell Matrix

(Bank 2)

A20 to A0

X-Decoder

State

Control

&

Command

Register

RESET

RY/BY

WE

CE

OE

Status

DQ15 to DQ0

WP/ACC

Control

DQ¹⁵to DQ0

X-Decoder

Cell Matrix

(Bank 1)

Bank 1

address

■ LOGIC SYMBOL

21

A²⁰to A0

16

DQ15 to DQ0

RY/BY

CE

OE

WE

RESET

WA/ACC

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■ DEVICE BUS OPERATION

MBM29PDS322TE/BE User Bus Operations Table

DQ15 to

DQ⁰

WP/

ACC

Operation

CE OE WE A0

A1

A2

A3

A6

A9

RESET

Auto-Select Manufacturer

Code *¹

Auto-Select Device Code *¹

L

H

L

H

L

VID

Code

H

X

Extended Auto-Select Device

Code *¹

L/H

H

Read *³

L

H

L

X

H

X

H

L

A0

X

A1

X

A2

X

A3

X

A6

X

A9

X

DOUT

High-Z

DIN

H

X

Standby

Output Disable

Write (Program/Erase)

X

L

A⁰

A1

A2

A3

A6

A9

Enable Sector Group

Protection *^2,*⁴

L

VID

L

H

L

VID

X

H

X

Verify Sector Group Protection

*^2,*⁴

L

H

Code

Temporary Sector Group

Unprotection *⁵

X

High-Z

X

VID

L

X

L

Reset (Hardware) / Standby

Boot Block Sector Write

Protection *⁶

X

Legend: L = V^IL, H = VIH, X = VIL or VIH,

= Pulse input. See “■ DC CHARACTERISTICS” for voltage levels.

*1: Manufacturer and device codes may also be accessed via a command register write sequence. See

“MBM29PDS322TE/BE User Bus Operations” Table.

*2: Refer to section on Sector Group Protection.

*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*4: V^CCmust be between the minimum and maximum of the operation range.

*5: Also used for the extended sector group protection.

*6: Protect “outermost” 2 × 4 K words of the boot block sectors.

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MBM29PDS322TE/BE Command Definitions Table

Fourth Bus

Read/Write

Cycle

Bus

First Bus

Write Cycle

Third Bus

Write Cycle

Fifth Bus

Write Cycle Write Cycle

Sixth Bus

Second Bus

Write Cycle

Command

Sequence

Write

Cycles

Req’d

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Read/Reset Word

1

3

XXXh F0h

—

555h AAh 2AAh 55h 555h F0h

(BA)

RA

RD

Auto

Word

select

3

555h AAh 2AAh 55h

90h

—

555h

Program

Word

4

6

1

555h AAh 2AAh 55h 555h A0h

PA

PD

Chip Erase Word

Sector Erase Word

Erase Suspend

555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h

555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h

SA

—

30h

—

BA

B0h

30h

—

Erase Resume

—

Set to

Fast Mode

Word

3

2

555h AAh 2AAh 55h 555h 20h

—

Fast

Word

XXXh A0h

PA

PD

*

—

Program *¹

4

Reset from

Word

BA 90h XXXh

Fast Mode *¹

F0h

Extended

Sector Group

Protection *²

Word

4

XXXh 60h SPA 60h SPA 40h SPA SD

—

HiddenROM

Entry

Word

3

4

6

4

555h AAh 2AAh 55h 555h 88h

555h AAh 2AAh 55h 555h A0h

—

HiddenROM

Program *³

(HRA)

PA

PD

HiddenROM

Erase *³

555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h HRA 30h

HiddenROM

Exit *³

(HRBA)

555h AAh 2AAh 55h

90h XXXh 00h

—

555h

*1: This command is valid during Fast Mode.

*2: This command is valid while RESET = VID.

*3: This command is valid during HiddenROM mode.

*4: The data “00h” is also acceptable.

Notes : • Address bits A²⁰to A12 = X = “H” or “L” for all address commands except or Program Address (PA), Sector

Address (SA), and Bank Address (BA).

• Bus operations are defined in “Simultaneous Operation Table” in “■FUNCTIONAL DESCRIPTION”.

• RA = Address of the memory location to be read

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A²⁰, A19, A18, A17, A16, A15, A14, A13, and

A¹²will uniquely select any sector.

BA = Bank Address (A²⁰to A15)

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• RD = Data read from location RA during the read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.

• SPA = Sector group address to be protected. Set sector group address (SGA) and (A⁶, A1, A0) = (0, 1, 0).

SD = Sector group protection verify data. Output 01h at protected sector group addresses and output

00h at unprotected sector group addresses.

• HRA = Address of the HiddenROM area

29PDS322TE (Top Boot Type)Word Mode:1F8000h to 1FFFFFh

29PDS322BE (Bottom Boot Type)Word Mode:000000h to 007FFFh

• HRBA =Bank Address of the HiddenROM area

29PDS322TE (Top Boot Type):A²⁰= A19 = A18 = A17 = A16 = A15 = 1

29PDS322BE (Bottom Boot Type):A²⁰= A19 = A18 = A17 = A16 = A15 = 0

• The system should generate the following address patterns:

Word Mode: 555h or 2AAh to addresses A¹⁰to A0

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

• The command combinations not described MBM29PDS322TE/BE command definitions are illegal.

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MBM29PDS322TE Sector Group Protection Verify Autoselect Codes Table

Type

A²⁰to A12

BA^*2

A6

VIL

A3

VIL

VIH

A2

VIL

VIH

A1

VIL

VIH

A0

VIL

VIH

VIL

VIH

Code (HEX)

04h

Manufacture’s Code

Device Code

Word

BA^*2

227Eh

2206h

Word

Extended Device

Code *³

BA^*2

2201h

Sector Group

Addresses

Sector Group Protection

V^IL

VIL

VIH

VIL

01h^*1

*1 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

*2 : When V^IDis applied, both Bank 1 and Bank 2 become Autoselect mode, which leads to the simultaneous

operation unable to be executed. Consequently, specifying the bank address is not demanded. However, the

bank address needs to be indicated when Autoselect mode is read out at command mode; because then it

becomes OK to activate simultaneous operation.

*3 : A read cycle at address (BA)01h outputs device code. When 227Eh was output, this indicates that there will

require two additional codes, called Extended Device Codes. Therefore, the system may continue reading out

these Extended Device Codes at the address of (BA)0Eh, as well as at (BA)0Fh.

Expanded Autoselect Code Table

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Type

Code

04h

Manufacturer’s

Code

0

1

0

227Eh

Device Code (W)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(W) 2206h

Extended

Device Code

2201h

(W)

Sector Group

Protection

01h

0

1

(W): Word mode

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MBM29PDS322BE Sector Group Protection Verify Autoselect Codes Table

Type

A²⁰to A12

BA^*2

A6

VIL

A3

VIL

VIH

A2

VIL

VIH

A1

VIL

VIH

A0

VIL

VIH

VIL

VIH

Code (HEX)

04h

Manufacture’s Code

Device Code

Word

BA^*2

227Eh

2206h

Word

Extended Device

Code *³

2200h

Sector Group

Addresses

Sector Group Protection

V^IL

VIL

VIH

VIL

01h^*1

*1 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

*2 : When V^IDis applied, both Bank 1 and Bank 2 become Autoselect mode, which leads to the simultaneous

operation unable to be executed. Consequently, specifying the bank address is not demanded. However, the

bank address needs to be indicated when Autoselect mode is read out at command mode; because then it

becomes OK to activate simultaneous operation.

* 3 : A read cycle at address (BA)01h outputs device code. When 227Eh was output, this indicates that there will

require two additional codes, called Extended Device Codes. Therefore, the system may continue reading out

these Extended Device Codes at the address of (BA)0Eh, as well as at (BA)0Fh.

Expanded Autoselect Code Table

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Type

Code

Manufacturer’s

Code

04h

0

1

0

Device Code (W) 227Eh

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2206h

2200h

(W)

Extended

Device Code

Sector Group

Protection

01h

0

1

(W): Word mode

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■ FLEXIBLE SECTOR-ERASE ARCHITECTURE

Sector Address Table (MBM29PDS322TE)

Sector Address

Sector

Size

(Kwords)

(×16)

Address Range

Bank Sector

Bank Address

A¹⁴

A13

A12

A20

0

1

A19

0

1

0

A18

0

1

0

1

0

A17

0

1

0

1

0

1

0

1

0

A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SA0

SA1

X

32

000000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

058000h to 05FFFFh

060000h to 067FFFh

068000h to 06FFFFh

070000h to 077FFFh

078000h to 07FFFFh

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

0A8000h to 0AFFFFh

0B0000h to 0B7FFFh

0B8000h to 0BFFFFh

0C0000h to 0C7FFFh

0C8000h to 0CFFFFh

0D0000h to 0D7FFFh

0D8000h to 0DFFFFh

0E0000h to 0E7FFFh

0E8000h to 0EFFFFh

0F0000h to 0F7FFFh

0F8000h to 0FFFFFh

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

(Continued)

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

Bank 2 SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

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(Continued)

Sector Address

Sector

(×16)

Address Range

Bank Sector

Bank Address

Size

A¹⁴

A13

A12

(Kwords)

A20

1

A19

0

1

A18

0

1

0

1

A17

0

1

0

1

0

1

0

1

A16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA35

SA36

X

0

X

0

X

0

32

4

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

158000h to 15FFFFh

160000h to 167FFFh

168000h to 16FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

1A8000h to 1AFFFFh

1B0000h to 1B7FFFh

1B8000h to 1BFFFFh

1C0000h to 1C7FFFh

1C8000h to 1CFFFFh

1D0000h to 1D7FFFh

1D8000h to 1DFFFFh

1E0000h to 1E7FFFh

1E8000h to 1EFFFFh

1F0000h to 1F7FFFh

1F8000h to 1F8FFFh

1F9000h to 1F9FFFh

1FA000h to 1FAFFFh

1FB000h to 1FBFFFh

1FC000h to 1FCFFFh

1FD000h to 1FDFFFh

1FE000h to 1FEFFFh

1FF000h to 1FFFFFh

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

Bank 2 SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

Bank 1 SA63

SA64

0

1

4

SA65

0

1

0

4

SA66

0

1

4

SA67

1

0

4

SA68

1

0

1

4

SA69

1

0

4

SA70

1

4

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Sector Address Table (MBM29PDS322BE)

Sector Address

Sector

Size

(Kwords)

(×16)

Address Range

Bank Sector

Bank Address

A¹⁴

A13

A12

A20

1

0

A19

1

0

1

A18

1

0

1

0

1

A17

1

0

1

0

1

0

1

0

1

A16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SA70

SA69

SA68

SA67

SA66

SA65

SA64

SA63

SA62

SA61

SA60

SA59

SA58

SA57

SA56

SA55

SA54

X

32

1F8000h to 1FFFFFh

1F0000h to 1F7FFFh

1E8000h to 1EFFFFh

1E0000h to 1E7FFFh

1D8000h to 1DFFFFh

1D0000h to 1D7FFFh

1C8000h to 1CFFFFh

1C0000h to 1C7FFFh

1B8000h to 1BFFFFh

1B0000h to 1B7FFFh

1A8000h to 1AFFFFh

1A0000h to 1A7FFFh

198000h to 19FFFFh

190000h to 197FFFh

188000h to 18FFFFh

180000h to 187FFFh

178000h to 17FFFFh

170000h to 177FFFh

168000h to 16FFFFh

160000h to 167FFFh

158000h to 15FFFFh

150000h to 157FFFh

148000h to 14FFFFh

140000h to 147FFFh

138000h to 13FFFFh

130000h to 137FFFh

128000h to 12FFFFh

120000h to 127FFFh

118000h to 11FFFFh

110000h to 117FFFh

108000h to 10FFFFh

100000h to 107FFFh

0F8000h to 0FFFFFh

0F0000h to 0F7FFFh

0E8000h to 0EFFFFh

0E0000h to 0E7FFFh

(Continued)

SA53

Bank 2

SA52

SA51

SA50

SA49

SA48

SA47

SA46

SA45

SA44

SA43

SA42

SA41

SA40

SA39

SA38

SA37

SA36

SA35

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(Continued)

Sector Address

Sector

(×16)

Address Range

Bank Sector

Bank Address

Size

A¹⁴

A13

A12

(Kwords)

A20

0

A19

1

0

A18

1

0

1

0

A17

0

1

0

1

0

1

0

A16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SA34

SA33

SA32

SA31

SA30

SA29

SA28

SA27

SA26

X

1

X

1

X

1

32

4

0D8000h to 0DFFFFh

0D0000h to 0D7FFFh

0C8000h to 0CFFFFh

0C0000h to 0C7FFFh

0B8000h to 0BFFFFh

0B0000h to 0B7FFFh

0A8000h to 0AFFFFh

0A0000h to 0A7FFFh

098000h to 09FFFFh

090000h to 097FFFh

088000h to 08FFFFh

080000h to 087FFFh

078000h to 07FFFFh

070000h to 077FFFh

068000h to 06FFFFh

060000h to 067FFFh

058000h to 05FFFFh

050000h to 057FFFh

048000h to 04FFFFh

040000h to 047FFFh

038000h to 03FFFFh

030000h to 037FFFh

028000h to 02FFFFh

020000h to 027FFFh

018000h to 01FFFFh

010000h to 017FFFh

008000h to 00FFFFh

007000h to 007FFFh

006000h to 006FFFh

005000h to 005FFFh

004000h to 004FFFh

003000h to 003FFFh

002000h to 002FFFh

001000h to 001FFFh

000000h to 000FFFh

SA25

Bank 2

SA24

SA23

SA22

SA21

SA20

SA19

SA18

SA17

SA16

SA15

SA14

SA13

SA12

SA11

SA10

SA9

SA8

Bank 1

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

0

4

1

0

1

4

1

0

4

0

1

4

0

1

0

4

0

1

4

0

4

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Sector Group Address Table (MBM29PDS322TE) (Top Boot Block)

Sector Group

A²⁰

A19

A18

A17

A16

A15

A14

A13

A12

Sectors

SGA0

0

X

SA0

0

1

SGA1

0

1

0

X

SA1 to SA3

1

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

SGA8

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

X

0

X

SA4 to SA7

SA8 to SA11

SA12 to SA15

SA16 to SA19

SA20 to SA23

SA24 to SA27

SA28 to SA31

SA32 to SA35

SA36 to SA39

SA40 to SA43

SA44 to SA47

SA48 to SA51

SA52 to SA55

SA56 to SA59

SGA16

1

0

1

X

SA60 to SA62

1

0

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

1

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Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

Sector Group Address Table (MBM29PDS322BE) (Bottom Boot Block)

Sector Group

SGA0

A²⁰

0

A19

A18

A17

A16

A15

A14

A13

A12

Sectors

SA0

0

SGA1

0

1

SA1

SGA2

0

1

0

SA2

SGA3

0

1

SA3

SGA4

0

1

0

SA4

SGA5

0

1

0

1

SA5

SGA6

0

1

0

SA6

SGA7

0

1

SA7

0

1

SGA8

0

1

0

X

SA8 to SA10

1

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

X

0

X

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SA35 to SA38

SA39 to SA42

SA43 to SA46

SA47 to SA50

SA51 to SA54

SA55 to SA58

SA59 to SA62

SA63 to SA66

SGA23

SGA24

1

0

1

X

SA67 to SA69

SA70

1

0

1

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Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

■ FUNCTIONAL DESCRIPTION

Simultaneous Operation

The device has a feature taht is capable of reading data from one bank of memory while a program or erase

operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional

features (read, program, erase, erase-suspend read, and erase-suspend program). The bank selection can be

selected by bank address (A²⁰to A15) with zero latency.

The device has two banks which contain

Bank 1 (4 KW × eight sectors, 32 KW × seven sectors) and Bank 2 (32 KW × fifty-six sectors).

The simultaneous operation cannot execute multi-function mode in the same bank. “Simultaneous Operation”

Table shows the possible combinations for simultaneous operation. (Refer to “Bank-to-Bank Read/Write Timing

Diagram” in “■TIMING DIAGRAM”.)

Simultaneous Operation Table

Case

Bank 1 Status

Read mode

Bank 2 Status

Read mode

1

2

3

4

5

6

7

Read mode

Autoselect mode

Program mode

Erase mode *

Read mode

Autoselect mode

Program mode

Erase mode *

Read mode

*: Erase operation may also be suspended to read from or program to a sector not being erased.

Read Mode

The device has two control functions to be satisfied for obtaining data at the outputs. CE is the power control

and should be used for a device selection. OE is the output control and should be used as the gate data to the

output pins if a device is selected.

Address access time (t^ACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (t^CE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time (t^OE) is the delay from the falling edge of OE to valid data at the output pins (assuming the

addresses have been stable for at least t^ACC-tOE time). When reading out data without changing addresses after

power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”.

Page Mode Read

The device is capable of fast Page mode read operation. This mode provides faster read access speed for

random locations within a page. The Page size of the device is 4 words, within the appropriate Page being

selected by the higher address bits A²⁰to A2 and the LSB bits A1 and A0 within that page. This is an asynchronous

operation with the microprocessor supplying the specific word location.

The random or initial page access is equal to t^ACCand subsequent Page read access (as long as the locations

specified by the microprocessor fall within that Page) is equivalent to t^PACC. Here again, CE selects the device

and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast

Page mode accesses are obtained by keeping A²⁰to A2 constant and changing A1 and A0 to select the specific

word, within that page.

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Standby Mode

There are two ways to implement the standby mode on the device, one using both the CE and RESET pins; the

other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC 0.3 V.

Under this condition, the current consumed is less than 5 μA Max During Embedded Algorithm operation, V^CC

active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either

of these standby modes.

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS 0.3 V (CE

= “H” or “L”). Under this condition the current consumed is less than 5 μA Max Once the RESET pin is taken

high, the device requires t^RHas wake up time for outputs to be valid for read access.

In the standby mode, the outputs are in the high impedance state, independently of the OE input.

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of the device

data. This mode can be useful in the application such as a handy terminal which requires low power consumption.

To activate this mode, the device automatically switches themselves to low power mode when the device ad-

dresses remain stable during access time of 150 ns. It is not necessary to control CE, WE, and OE on the mode.

Under the mode, the current consumed is typically 50 μA (CMOS Level).

During simultaneous operation, V^CCactive current (ICC2) is required.

Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,

the mode is canceled automatically, and the device reads the data for changed addresses.

Output Disable

With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins

to be in a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer

and type. This mode is intended for use by programming equipment for the purpose of automatically matching

the device to be programmed with its corresponding programming algorithm. This mode is functional over the

entire temperature range of the device.

To activate this mode, the programming equipment must force V^ID(10.0 V to 11.0 V) on address pin A9. Two

identifier bytes may then be sequenced from the device outputs by toggling address A⁰from VIL to VIH. All

addresses are DON’T CARES except A⁶, A3, A2, A1, and A0. (See “MBM29PDS322TE/BE User Bus Operations”

Table in “■DEVICE BUS OPERATION”.)

The manufacturer and device codes may also be read via the command register, for instances when the device

is erased or programmed in a system without access to high voltage on the A⁹pin. The command sequence is

illustrated in “MBM29PDS322TE/BE Command Definitions” Table in “■DEVICE BUS OPERATION”. (Refer to

Autoselect Command section.)

In the command Autoselect mode, the bank addresses BA; (A²⁰to A12) must point to a specific bank during the

third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while

array data can be read from the other bank.

A read cycle from address (BA)00h returns the manufacturer’s code (Fujitsu = 04h). And a read cycle from

address (BA)01h, (BA)0Eh to (BA)0Fh returns the device code. (See MBM29PDS322TE’s/BE’s “Sector Group

Protection Verify Autoselect Codes” Tables and “Expanded Autoselect Code” Tables in “■DEVICE BUS OPER-

ATION”.)

In case of applying V^IDon A9, since both Bank 1 and Bank 2 enter Autoselect mode, the simultaneous operation

can not be executed.

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Write

Device erasure and programming are accomplished via the command register. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The com-

mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

whichever happens first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Sector Group Protection

The device features hardware sector group protection. This feature will disable both program and erase opera-

tions in any combination of twenty five sector groups of memory. (See MBM29PDS322TE’s/BE’s “Sector Group

Address” Tables in “■FLEXIBLE SECTOR-ERASE ARCHITECTURE”.) The sector group protection feature is

enabled using programming equipment at the user’s site. The device is shipped with all sector groups unpro-

tected.

To activate this mode, the programming equipment must force V^IDon address pin A9 and control pin OE, (suggest

V^ID= 11.5 V), CE = VIL and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0). The sector group addresses (A20, A19, A18, A17,

A¹⁶, A15, A14, A13, and A12) should be set to the sector to be protected. “Sector Address” Tables (MBM29PDS322TE

and MBM29PDS322BE) in “■FLEXIBLE SECTOR-ERASE ARCHITECTURE” define the sector address for

each of the seventy one (71) individual sectors, and “Sector Group Address” Tables (MBM29PDS322TE and

MBM29PDS322BE) in “■FLEXIBLE SECTOR-ERASE ARCHITECTURE” define the sector group address for

each of the twenty five (25) individual group sectors. Programming of the protection circuitry begins on the falling

edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held

constant during the WE pulse. See “Sector Group Protection Timing Diagram” in “■TIMING DIAGRAM” and

“Sector Group Protection Algorithm” in “■FLOW CHARTS” for sector group protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V^IDon address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13,

and A¹²) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a

protected sector. Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order

addresses, except for A⁰, A1, A2, A3, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for

Autoselect manufacturer and device codes.

It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.

Performing a read operation at the address location XX02h, where the higher order addresses (A²⁰, A19, A18, A17,

A¹⁶, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected

sector group. See MBM29PDS322TE’s/BE’s “Sector Group Protection Verify Autoselect Codes” Tables and

“Expanded Autoselect Code” Tables in “■DEVICE BUS OPERATION” for Autoselect codes.

Temporary Sector Group Unprotection

This feature allows temporary unprotection of previously protected sector groups of the device in order to change

data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During

this mode, formerly protected sector groups can be programmed or erased by selecting the sector group ad-

dresses. Once the V^IDis taken away from the RESET pin, all the previously protected sector groups will be

protected again. Refer to “Temporary Sector Group Unprotection Timing Diagram” in “■TIMING DIAGRAM” and

“Temporary Sector Group Unprotection Algorithm” in “■FLOW CHARTS”.

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Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

Extended Sector Group Protection

In addition to normal sector group protection, the device has Extended Sector Group Protection as extended

function. This function enables to protect sector group by forcing V^IDon RESET pin and write a command

sequence. Unlike conventional procedure, it is not necessary to force V^IDand control timing for control pins. The

only RESET pin requires VID for sector group protection in this mode. The extended sector group protection

requires V^IDon RESET pin. With this condition, the operation is initiated by writing the set-up command (60h)

into the command register. Then, the sector group addresses pins (A²⁰, A19, A18, A17, A16, A15, A14, A13 and A12)

and (A⁶, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (recommend to set VIL

for the other addresses pins), and write extended sector group protection command (60h). A sector group is

typically protected in 250 μs. To verify programming of the protection circuitry, the sector group addresses pins

(A²⁰, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set and write a

command (40h). Following the command write, a logical “1” at device output DQ⁰will produce for protected

sector in the read operation. If the output is logical “0”, please repeat to write extended sector group protection

command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. (Refer to “Extended

Sector Group Protection Timing Diagram” in “■TIMING DIAGRAM” and “Extended Sector Group Protection

Algorithm” in “■FLOW CHARTS”.)

RESET

Hardware Reset

The device may be reset by driving the RESET pin to VIL. The RESET pin vs. a pulse requirement and has to

be kept low (V^IL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process

of being executed will be terminated and the internal state machine will be reset to the read mode “t^READY” after

the RESET pin is driven low. Furthermore, once the RESET pin goes high, the device requires an additional

“t^RH” before it will allow read access. When the RESET pin is low, the device will be in the standby mode for the

duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program

or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal

should be ignored during the RESET pulse. See “RESET, RY/BY Timing Diagram” in “■TIMING DIAGRAM” for

the timing diagram. Refer to Temporary Sector Group Unprotection for additional functionality.

Boot Block Sector Protection

The Write Protection function provides a hardware method of protecting certain boot sectors without using V^ID.

This function is one of two provided by the WP/ACC pin.

If the system asserts V^ILon the WP/ACC pin, the device disables program and erase functions in the two

“outermost” 4K word boot sectors independently of whether those sectors are protected or unprotected using

the method described in “Sector Protection/Unprotection”. The two outermost 4K word boot sectors are the two

sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the

highest addresses in a top-boot-congfigured device.

(MBM29PDS322TE: SA69 and SA70, MBM29PDS322BE: SA0 and SA1)

If the system asserts V^IHon the WP/ACC pin, the device reverts to whether the two outermost 4K word boot

sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two

sectors depends on whether they were last protected or unprotected using the method described in “Sector

protection/unprotection”.

Accelerated Program Operation

The device offers accelerated program operation which enables the programming in high speed. If the system

asserts V^ACCto the WP/ACC pin, the device automatically enters the acceleration mode and the time required

for program operation will reduce to about 60%. This function is primarily intended to allow high speed program,

so caution is needed as the sector group will temporarily be unprotected.

The system would use a fast program command sequence when programming during acceleration mode.

Set command to fast mode and reset command from fast mode are not necessary. When the device enters the

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Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

acceleration mode, the device automatically set to fast mode. Therefore, the present sequence could be used

for programming and detection of completion during acceleration mode.

Removing V^ACCfrom the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/

ACC pin while programming. See “Accelerated Program Timing Diagram” in “■TIMING DIAGRAM”.

Erase operation during Accalerated Program Operation is strictly prohibited.

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Retired ProductꢀDS05-20889-6E_July 31, 2007

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■ COMMAND DEFINITIONS

The device operations are selected by writing specific address and data sequences into the command register.

Some commands require Bank Address (BA) input. When command sequences are inputted to bank being read,

the commands have priority over reading. “MBM29PDS322TE/BE Command Definitions” Table in “■DEVICE

BUS OPERATION” defines the valid register command sequences. Note that the Erase Suspend (B0h) and

Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover, both

Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that

commands are always written at DQ⁷to DQ0 and DQ15 to DQ8 bits are ignored.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ⁵= 1) to Read/Reset mode, the Read/

Reset operation is initiated by writing the Read/Reset command sequence into the command register. Micro-

processor read cycles retrieve array data from the memory. The device remains enabled for reads until the

command register contents are altered.

The device willautomatically power-up inthe Read/Resetstate. Inthis case, acommandsequenceis notrequired

to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no

spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Character-

istics and Waveforms for the specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,

manufacture and device codes must be accessible while the device resides in the target system. PROM pro-

grammers typically access the signature codes by raising A⁹to a high voltage. However, multiplexing high voltage

onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming method-

ology. The operation is initiated by writing the Autoselect command sequence into the command register.

The Autoselect command sequence is initiated by firstly writing two unlock cycles. This is followed by a third

write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device

codes can be read from the bank, and actual data of memory cell can be read from the another bank.

Following the command write, a read cycle from address (BA)00h retrieves the manufacture code of 04h. A read

cycle at address (BA)01h returns 7Eh to indicate that this device uses extended device code. The successive

read cycle from (BA)0Eh to (BA)0Fh returns this extended device code for this device. (See MBM29PDS322TE’s/

BE’s “Sector Group Protection Verify Autoselect Codes” Tables and “Expanded Autoselect Code” Tables in

“■DEVICE BUS OPERATION”.)

The sector state (protection or unprotection) will be informed by address (BA)02h. Scanning the sector group

addresses (A²⁰, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a

logical “1” at device output DQ⁰for a protected sector group. The programming verification should be performed

by verify sector group protection on the protected sector. (See “MBM29PDS322TE/BE User Bus Operations”

Table in “■DEVICE BUS OPERATION”.)

The manufacture and device codes can be allowed to read from selected bank. To read the manufacture and

device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command

sequence into the register and then Autoselect command should be written into the bank to be read.

If the software (program code) for Autoselect command is stored into the Flash memory, the device and manu-

facture codes should be read from the other bank which doesn’t contain the software.

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To

execute the Autoselect command during the operation, writing Read/Reset command sequence must precede

the Autoselect command.

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Word Programming

The device is programmed on a word-by-word basis. Programming is a four bus cycle operation. There are two

“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are

latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of

CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming.

Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide

further controls or timings. The device automatically provides adequate internally generated program pulses

and verify programmed cell margin.

The system can determine the status of the program operation by using DQ⁷(Data Polling), DQ6 (Toggle Bit),

or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location being programmed.

The automatic programming operation is completed when the data on DQ⁷is equivalent to data written to this

bit at which the device returns to the read mode and addresses are no longer latched. (See “Hardware Sequence

Flags” Table.) Therefore the device requires that a valid address to the device be supplied by the system at this

particular moment. Hence Data Polling must be performed at the memory location which is being programmed.

If hardware reset occurs during the programming operation, it is impossible to guarantee the data being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only

erase operations can convert “0”s to “1”s.

“Embedded Program^TMAlgorithm” in “■FLOW CHARTS” illustrates the Embedded Program^TMAlgorithm using

typical command strings and bus operations.

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the device will automatically program and verify the entire memory for an all zero

data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls

or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling), DQ6 (Toggle Bit), or

RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command

sequence and terminates when the data on DQ⁷is “1” (See Write Operation Status section.) at which the device

returns to read the mode.

Chip Erase Time : Sector Erase Time × All sectors + Chip Program Time (Preprogramming)

“Embedded Erase^TMAlgorithm” in “■FLOW CHARTS” illustrates the Embedded Erase^TMAlgorithm using typical

command strings and bus operations.

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Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever

happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first.

After time-out of “t^TOW” from the rising edge of the last sector erase command, the sector erase operation begins.

Multiple sectors are erased concurrently by writing the six bus cycle operations on “MBM29PDS322TE/BE

Command Definitions” Table in “■DEVICE BUS OPERATION”. This sequence is followed with writes of the

Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between

writes must be less than “t^TOW” otherwise that command will not be accepted and erasure does not start. It is

recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts

can be re-enabled after the last Sector Erase command is written. A time-out of “t^TOW” from the rising edge of

last CE or WE whichever happens first will initiate the execution of the Sector Erase command(s). If another

falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-out window the timer is reset.

(Monitor DQ³to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.)

Resetting the device once execution has begun will corrupt the data in the sector. In that case, restart the erase

on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase

Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors

(0 to 70).

Sector erase does not require the user to program the device prior to erase. The device automatically programs

all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing

a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any

controls or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling), DQ6 (Toggle Bit), or

RY/BY.

The sector erase begins after the “t^TOW” time out from the rising edge of CE or WE whichever happens first for

the last sector erase command pulse and terminates when the data on DQ⁷is “1” (See Write Operation Status

section.) at which time the device returns to the read mode. Data polling and Toggle Bit must be performed at

an address within any of the sectors being erased.

Multiple Sector Erase Time : [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of Sector

Erase

In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not perform.

“Embedded Erase^TMAlgorithm” in “■FLOW CHARTS” illustrates the Embedded Erase^TMAlgorithm using typical

command strings and bus operations.

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Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt Sector Erase operation and then perform data reads

from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase

operation which includes the time-out period for sector erase. Writing the Erase Suspend command (B0h) during

the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase

operation.

Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being

erased or erase-suspended should be set when writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device takes a maximum

of “t^SPD” to suspend the erase operation. When the device has entered the erase-suspended mode, the

RY/BY output pin is at Hi-Z and the DQ7 bit is at logic “1”, and DQ6 stops toggling. The user must use the address

of the erasing sector for reading DQ⁶and DQ7 to determine if the erase operation is suspended. Further writes

of the Erase Suspend command are ignored.

When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode except that the data must be read from

sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the

device is in the erase-suspend-read mode will cause DQ²to toggle. (See the section on DQ2.)

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com-

mand sequence for Program. This program mode is known as the erase-suspend-program mode. Again, pro-

gramming in this mode is the same as programming in the regular Program mode except that the data must be

programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector

while the device is in the erase-suspend-program mode will cause DQ²to toggle. The end of the erase-suspended

Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which

is the same as the regular Program operation. Note that DQ⁷must be read from the Program address while DQ6

can be read from any address within bank being erase-suspended.

To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase

suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend

command is written after the chip has resumed erasing.

Extended Command

(1) Fast Mode

The device has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the

standard program command sequence by writing Fast Mode command into the command register. In this

mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program

command. (Do not write erase command in this mode.) The read operation is also executed after exiting this

mode. In continuous mode, do not write any command other than the continuous program/continuous mode

reset command. To exit this mode, it is necessary to write Fast Mode Reset command into the command

register. The first cycle must contain the bank address. (Refer to “Embedded Program^TMAlgorithm for Fast

Mode” in “■FLOW CHARTS”.) The V^CCactive current is required even CE = VIH during Fast Mode.

(2) Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program

Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to

“Embedded Program^TMAlgorithm for Fast Mode” in “■FLOW CHARTS”.)

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HiddenROM Region

The HiddenROM feature provides Flash memory region that the system may access through a new command

sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the

device with the ESN protected against modification. Once the HiddenROM region is protected, any further

modification of that region is not allowed. This ensures the security of the ESN once the product is shipped to

the field.

The HiddenROM region is 32 K words in length and is stored at the same address as the 4 KW ×8 sectors. The

MBM29PDS322TE occupies the address of the word mode 1F8000h to 1FFFFFh and the MBM29PDS322BE

type occupies the address of the word mode 000000h to 007FFFh. After the system writes the Enter HiddenROM

command sequence, the system reads the HiddenROM region by using the addresses normally occupied by

the boot sectors. That is, the device sends all commands that would normally be sent to the boot sectors to the

HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command

sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device

reverts to sending commands to the boot sectors.

When reading the HiddenROM region, either change addresses or change CE pin from “H” to “L”. The same

procedure should be taken (changing addresses or CE pin from “H” to “L”) after the system issues the Exit

HiddenROM command sequence to read actual data of memory cell.

HiddenROM Entry Command

The device has HiddenROM area with One Time Protect function. This area is to enter the security code and

to unable the change of the code once set. Program/erase is possible in this area until it becomes protected.

However once it is protected, it is impossible to unprotect, use this command with caution.

HiddenROM area is 32 K words and in the same address area as 4 KW sector. The address of top boot is

1F8000h to 1FFFFFh at word mode and the bottom boot is 000000h to 007FFFh at word mode. These areas

are normally the boot block area (4 KW ×8 sector). Therefore write the HiddenROM entry command sequence

to enter the HiddenROM area. This is called HiddenROM mode as the HiddenROM area appears.

Sector other than the boot block area could be read during HiddenROM mode. Read/program/erase of the

HiddenROM area is allowed during HiddenROM mode. Write the HiddenROM reset command sequence to exit

the HiddenROM mode. The bank address of the HiddenROM should be set on the third cycle of this reset

command sequence. Note that any other commands should not be issued than the HiddenROM program/

protection/reset commands during the HiddenROM mode. When you issue the other commands including the

suspend resume capability, send the HiddenROM reset command first to exit the HiddenROM mode and then

issue each command.

HiddenROM Program Command

To program data to the HiddenROM area, write the HiddenROM program command sequence during Hidden-

ROM mode. This command is the same as the program command in usual except to write the command during

HiddenROM mode. Therefore the detection of completion method is the same as described, using the DQ⁷data

poling, DQ⁶toggle bit and RY/BY pin. It is necessary to pay attention to the address to be programmed. If the

address other than the HiddenROM area is selected to program, data of the address will be changed.

During the write into the HiddenROM region, the program suspend command issuance is prohibited.

HiddenROM Erase Command

To erase the HiddenROM area, write the HiddenROM erase command sequence during HiddenROM mode.

Thiscommand is same asthe sector erasecommandin the pastexcept towrite thecommandduringHiddenROM

mode. Therefore the detection of completion method is the same as in the past, using the DQ⁷data poling, DQ6

toggle bit and RY/BY pin. It is necessary to pay attention to the sector address to be erased. If the sector address

other than the HiddenROM area is selected, the data of the sector will be changed.

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HiddenROM Protect Command

There are two methods to protect the HiddenROM area. One is to write the sector group protect setup command

(60h), set the sector address in the HiddenROM area and (A⁶, A3, A2,A1, A0) = (0,0,0,1,0), and write the sector

group protect command (60h) during the HiddenROM mode. The same command sequence could be used

because, it is just as the extension sector group protect in the past except that it is in the HiddenROM mode and

it does not apply high voltage to RESET pin. Please refer to “Function Explanation Extended Sector Group

Protection” for details of extension sector group protect setting.

The other method is to apply high voltage (V^ID) to A9 and OE, set the sector address in the HiddenROM area

and (A⁶, A3, A2, A1, A0) = (0, 0, 0, 1, 0), and apply the write pulse during the HiddenROM mode. To verify the

protect circuit, apply high voltage (V^ID) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address

in the HiddenROM area, and read. When “1” appears on DQ⁰, the protect setting is completed. “0” will appear

on DQ⁰if it is not protected. Please apply write pulse again. The same command sequence could be used for

the above method because other than the HiddenROM mode, it is the same with the sector group protect

previously mentioned. Refer to “Function Explanation Sector Group Protection” for details of the sector group

protect setting.

Other sector group will be effected if the address other than those for HiddenROM area is selected for the sector

group address. Once it is protected, protection cannot be cancelled, so please pay the closest attention.

Write Operation Status

Detailed in “Hardware Sequence Flags” Table are all the status flags that determine the status of the bank for

the current mode operation. The read operation from the bank which does not operate Embedded Algorithm

returns data of memory cells. These bits offer a method for determining whether a Embedded Algorithm is

properly completed. The information on DQ²is address sensitive. This means that if an address from an erasing

sector is consecutively read, then the DQ²bit will toggle. However DQ2 will not toggle if an address from a non-

erasing sector is consecutively read. This allows users to determine which sectors are in erase.

The status flag is not output from bank (non-busy bank) which does not execute Embedded Algorithm. For

example, there is bank (busy bank) , now executing Embedded Algorithm. When the read sequence is [1] <busy

bank>, [2] <non-busy bank>, [3] <busy bank>, the DQ⁶is toggling in the case of [1] and [3]. In case of [2], the

data of memory cells are outputted. In the erase-suspend read mode with the same read sequence, DQ⁶will

not be toggled in the [1] and [3].

In the erase suspend read mode, DQ²is toggled in the [1] and [3]. In case of [2], the data of memory cell is

outputted.

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Hardware Sequence Flags Table

Status

Embedded Program Algorithm

Embedded Erase Algorithm

DQ⁷

DQ6

DQ5 DQ3

DQ2

1

DQ⁷Toggle

0

1

0

1

Toggle

1

Toggle *¹

Erase Suspend Read

0

Toggle

Data

1 *²

(Erase Suspended Sector)

Erase

Erase Suspend Read

Suspended

Data

Data Data

(Non-Erase Suspended Sector)

Mode

In Progress

Erase Suspend Program

(Non-Erase Suspended Sector)

DQ⁷Toggle

0

Program Suspend Read

(Program Suspended Sector)

Data

Data Data

Data

Program

Suspende

Program Suspend Read

Mode

(Non-Program Suspended Sector)

Embedded Program Algorithm

DQ⁷Toggle

Toggle

1

0

1

Embedded Erase Algorithm

0

N/A

Exceeded

Time Limits

Erase

Erase Suspend Program

Suspended

DQ⁷Toggle

1

0

N/A

(Non-Erase Suspended Sector)

Mode

*1: Successive reads from the erasing or erase-suspend sector causes DQ²to toggle.

*2: Reading from non-erase suspend sector address will indicate logic “1” at the DQ²bit.

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DQ⁷

Data Polling

The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in

progress or completed. During the Embedded Program Algorithm an attempt to read device will produce a

complement of data last written to DQ⁷. Upon completion of the Embedded Program Algorithm, an attempt to

read device will produce true data last written to DQ⁷. During the Embedded Erase Algorithm, an attempt to read

device will produce a “0” at the DQ⁷output. Upon completion of the Embedded Erase Algorithm an attempt to

read device will produce a “1” on DQ⁷. The flowchart for Data Polling (DQ7) is shown in “Toggle Bit Algorithm”

in “■FLOW CHARTS”.

For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse

sequence.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. Data Polling must be performed at sector address of sectors being erased, not protected

sectors. Otherwise, the status may be invalid.

If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 μs, then

that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for

erasing are protected, Data Polling on DQ7 is active for approximately 400 μs, then the bank returns to read mode.

Once the Embedded Algorithm operation is close to completion, the device data pins (DQ⁷) may change asyn-

chronously while the output enable (OE) is asserted low. This means that device is driving status information

on DQ⁷at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the

system samples the DQ⁷output, it may read the status or valid data. Even if device has completed the Embedded

Algorithm operation and DQ⁷has a valid data, data outputs on DQ0 to DQ6 may be still invalid. The valid data

on DQ⁰to DQ7 will be read on the successive read attempts.

TheData PollingfeatureisactiveonlyduringtheEmbeddedProgrammingAlgorithm, EmbeddedEraseAlgorithm

or sector erase time-out. (See “Hardware Sequence Flags” Table.)

See “Toggle Bit I during Embedded Algorithm Operation Timing Diagram” in “■TIMING DIAGRAM” for the Data

Polling timing specifications and diagrams.

DQ⁶

Toggle Bit I

The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded

Algorithms are in progress or completed.

During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the

device will results in DQ⁶toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle

is completed, DQ⁶will stop toggling and valid data will be read on the next successive attempts. During pro-

gramming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.

For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written is protected, the toggle bit will toggle for about 1 μs and then stop

toggling with data unchanged. In erase, device will erase all selected sectors except for ones that are protected.

If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into

read mode, having data unchanged.

Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause

DQ⁶to toggle.

The system can use DQ⁶to determine whether a sector is actively erased or is erase-suspended. When a bank

is actively erased (that is, the Embedded Erase Algorithm is in progress), DQ⁶toggles. When a bank enters the

Erase Suspend mode, DQ⁶stops toggling. Successive read cycles during erase-suspend-program cause DQ6

to toggle.

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To operate toggle bit function properly, CE or OE must be high when bank address is changed.

See“Bank-to-BankRead/WriteTimingDiagram”in“■TIMINGDIAGRAM”for theToggleBitItimingspecifications

and diagrams.

DQ⁵

Exceeded Timing Limits

DQ⁵will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ⁵will produce a “1”. This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling is the only operating function of device under this condition.

The CE circuit will partially power down device under these conditions (to approximately 2 mA). The OE and

WE pins will control the output disable functions as described in “Simultaneous Operation” Table in “■FUNC-

TIONAL DESCRIPTION”.

The DQ⁵failure condition may also appear if a user tries to program a non blank location without pre-erase. In

this case the device locks out and never complete the Embedded Algorithm operation. Hence, the system never

read valid data on DQ⁷bit and DQ6 never stop toggling. Once device has exceeded timing limits, the DQ5 bit will

indicate a “1.” Please note that this is not a device failure condition since device was incorrectly used. If this

occurs, reset device with command sequence.

DQ³

Sector Erase Timer

After completion of the initial sector erase command sequence sector erase time-out will begin. DQ³will remain

low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command

sequence.

If Data Polling or the Toggle Bit I indicates device has been written with a valid erase command, DQ3 may be

used to determine if the sector erase timer window is still open. If DQ³is high (“1”) the internally controlled erase

cycle has begun.If DQ³is low (“0”), the device will accept additional sector erase commands. To insure the

command has been accepted, the system software should check the status of DQ³prior to and following each

subsequent Sector Erase command. If DQ³were high on the second status check, the command may not have

been accepted.

See “Hardware Sequence Flags” Table.

DQ²

Toggle Bit II

This toggle bit II, along with DQ⁶, can be used to determine whether the device is in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ²to toggle during the Embedded Erase Algorithm. If the

device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ²to toggle. When the device is in the erase-suspended-program mode, successive reads from the word

address of the non-erase suspended sector will indicate a logic “1” at the DQ²bit.

DQ⁶is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ⁷, is summarized

as follows:

For example, DQ²and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

(DQ²toggles while DQ6 does not.) See also and.

Furthermore, DQ²can also be used to determine which sector is being erased. When device is in the erase

mode, DQ²toggles if this bit is read from an erasing sector.

To operate toggle bit function properly, CE or OE must be high when bank address is changed.

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Reading Toggle Bits DQ⁶/DQ2

Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row

to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit

after the first read. After the second read, the system would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can

read array data on DQ⁷to DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system

also should note whether the value of DQ⁵is high (see the section on DQ5). If it is the system should then

determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ⁵

went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase

operation. If it is still toggling, the device did not complete the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ⁵has not

gone high. The system may continue to monitor the toggle bit and DQ⁵through successive read cycles, deter-

mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system

tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status

of the operation. (Refer to “Toggle Bit Algorithm” in “■FLOW CHARTS”.)

Toggle Bit Status Table

Mode

DQ⁷

DQ7

0

DQ6

DQ2

1

Program

Erase

Toggle

Toggle *¹

Erase-Suspend Read

(Erase-Suspended Sector)

1

Toggle

1 *²

Erase-Suspend Program

DQ⁷

Toggle

*1: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle.

*2: Reading from the non-erase suspend sector address will indicate logic “1” at the DQ²bit.

RY/BY

Ready/Busy

The device provides a RY/BY open-drain output pin as a way to indicate to the host system that Embedded

Algorithms are either in progress or has been completed. If output is low, device is busy with either a program

or erase operation. If output is high, device is ready to accept any read/write or erase operation. If the device is

placed in an Erase Suspend mode, RY/BY output will be high.

During programming, RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase

operation, RY/BY pin is driven low after the rising edge of the sixth write pulse. RY/BY pin will indicate a busy

condition during RESET pulse. Refer to “RY/BY Timing Diagram during Program/Erase Operation Timing Dia-

gram” and “RESET, RY/BY Timing Diagram” in “■TIMING DIAGRAM” for a detailed timing diagram. RY/BY pin

is pulled high in standby mode.

Since this is an open-drain output, the pull-up resistor needs to be V^CC; multiples of devices may be connected

to the best system via more than one RY/BY pin in parallel.

36

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

Data Protection

The device is designed to offer protection against accidental erasure or programming caused by spurious system

level signals that may exist during power transitions. During power up device automatically resets internal state

machine in Read mode. Also, with its control register architecture, alteration of memory contents only occurs

after successful completion of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent inadvertent write cycles resulting from V^CCpower-up

and power-down transitions or system noise.

Power On/Off Timing

The RESET pin must be held low during V^CCramp up to insure that device power up correctly.

(Refer to “Page Read Operation Timing Diagram” in “■TIMING DIAGRAM”.)

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

Sector Protection

Device user is able to protect each sector group individually to store and protect data.

Protection circuit voids both write and erase commands that are addressed to protected sectors.

Any commands to write or erase addressed to protected sector are ignore (see “ Sector Group Protection” in

“■FUNCTIONAL DESCRIPTION”).

37

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Storage Temperature

Symbol

Unit

Min

–55

–40

Max

+125

+85

Tstg

T^A

°C

Ambient Temperature with Power Applied

Voltage with Respect to Ground All pins except A⁹,

OE, and RESET *¹

VIN, VOUT

–0.5

VCC+0.5

V

Power Supply Voltage *¹

A⁹, OE, and RESET *²

WP/ACC *³

VCC

VIN

–0.5

+2.7

+11.0

+12.6

V

VACC

*1: Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot

V^SSto –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage

transitions, input or I/O pins may overshoot to V^CC+2.0 V for periods of up to 20 ns.

*2: Minimum DC input voltage on A⁹, OE and RESET pins is –0.5 V. During voltage transitions, A9, OE and RESET

pins may undershoot V^SSto –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage

(V^IN-VCC) does not exceed +9.0V. Maximum DC input voltage on A9, OE and RESET pins is +11.0 V which may

positive overshoot to +12.5 V for periods of up to 20 ns.

*3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot

V^SSto –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +12.6 V which may positive

overshoot to +13.0 V for periods of up to 20ns when Vcc is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING RANGES

Value

Parameter

Symbol

Unit

Min

–40

+1.8

Max

+85

Ambient Temperature

Power Supply Voltage

T^A

°C

V

V^CC

+2.2

Note: Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

38

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

■ MAXIMUM OVERSHOOT / MAXIMUM UNDERSHOOT

20 ns

0.2 × VCC

−0.5 V

−2.0 V

20 ns

Maximum Undershoot Waveform

20 ns

V

CC + 2.0 V

V

CC + 0.5 V

0.8 × VCC

20 ns

Maximum Overshoot Waveform 1

20 ns

+12.5 V

+11.0 V

VCC + 0.5 V

20 ns

Note: This waveform is applied for A9, OE and RESET

Maximum Overshoot Waveform 2

39

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

Value

Parameter

Symbol

Conditions

Unit

Min

–1.0

Max

+1.0

Input Leakage Current

Output Leakage Current

I^LI

VIN = VSS to VCC, VCC = VCC Max

VOUT = VSS to VCC, VCC = VCC Max

μA

I^LO

A⁹, OE, RESET Inputs Leakage

Current

VCC = VCC Max ,

A⁹, OE, RESET = 11.0 V

I^LIT

—

35

μA

CE = VIL, OE = VIH, f = 10 MHz

CE = VIL, OE = VIH, f = 1 MHz

CE = VIL, OE = VIH

—

28

3

mA

V^CCActive Current *¹

ICC1

V^CCActive Current *²

V^CCCurrent (Standby)

ICC2

ICC3

30

VCC = VCC Max, CE = VCC 0.3 V,

RESET = VCC 0.3 V

—

5

μA

VCC = VCC Max, WE/ACC = VCC

0.3 V, RESET = VSS 0.3 V

V^CCCurrent (Standby, Reset)

ICC4

ICC5

VCC = VCC Max, CE = VSS 0.3 V,

RESET = VCC 0.3 V

V^IN= VCC 0.3 V or VSS ± 0.3 V

V^CCCurrent

—

5

μA

(Automatic Sleep Mode) *³

V^CCActive Current *⁵

(Read-While-Program)

V^CCActive Current *⁵

(Read-While-Erase)

I^CC6

I^CC7

I^CC8

I^ACC

CE = VIL, OE = VIH

—

55

35

20

mA

V^CCActive Current

(Erase-Suspend-Program)

WP/ACC Accelerated Program

Current

VCC = VCC Max,

WP/ACC = VACC Max

Input Low Level

Input High Level

V^IL

V^IH

—

–0.5

0.2× VCC

V

0.8× VCC

VCC+0.3

Voltage for WP/ACC Sector

Protection/Unprotection and

Program Acceleration *⁴

VACC

—

8.5

12.5

V

Voltage for Autoselect and Sector

Protection (A⁹, OE, RESET) *⁴

VID

10.0

11.0

V

Output Low Voltage Level

Output High Voltage Level

Low V^CCLock-Out Voltage

V^OL

V^OH

VLKO

IOL = 100 μA, VCC = VCC Min

—

VCC–0.1

1.2

0.1

—

V

IOH = –100 μA

⎯

1.5

*1: The ICC current listed includes both the DC operating current and the frequency dependent component.

*2: I^CCis active while Embedded Algorithm (program or erase) is in progress.

*3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns.

*4: Applicable for only V^CCapplying.

*5: Embedded Algorithm (program or erase) is in progress. (@5 MHz)

40

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

2. AC Characteristics

• Read Only Operations Characteristics

Value(Note)

10 11

Min Max Min Max

Symbol

Parameter

Conditions

Unit

JEDEC

t^AVAV

Standard

Read Cycle Time

tRC

tACC

t^PRC

t^PACC

—

100

⎯

100

⎯

115

⎯

115

⎯

ns

CE = VIL,

OE = VIL

Address to Output Delay

Page Read Cycle Time

Page Address to Output Delay

t^AVQV

—

⎯

—

40

⎯

50

⎯

CE = VIL,

OE = VIL

—

40

50

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

tCE

tOE

tDF

OE = VIL

⎯

100

35

⎯

115

45

ns

—

30

Output Hold Time From Addresses,

CE or OE, Whichever Occurs First

t^AXQX

—

tOH

—

0

⎯

0

⎯

ns

RESET Pin Low to Read Mode

tREADY

⎯

20

⎯

20

μs

Note: Test Conditions:

Output Load: 30 pF (MBM29PDS322TE10/BE10)

100 pF (MBM29PDS322TE11/BE11)

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V or 2.0 V

Timing measurement reference level

Input: 1.0 V

Output: 1.0 V

Device

Under

Test

CL

Note : C^L= 30 pF including jig capacitance (MBM29PDS322TE10/BE10)

C^L= 100 pF including jig capacitance (MBM29PDS322TE11/BE11)

Test Conditions

41

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

• Write/Erase/Program Operations

Value

Symbol

Parameter

10

11

Unit

JEDEC Standard Min Typ Max Min Typ Max

Write Cycle Time

t^AVAV

t^AVWL

tWC

tAS

100

0

⎯

115

0

⎯

ns

Address Setup Time

Address Setup Time to OE Low During

Toggle Bit Polling

—

t^WLAX

—

t^ASO

tAH

15

60

0

⎯

15

60

0

⎯

ns

Address Hold Time

Address Hold Time from CE or OE High

During Toggle Bit Polling

t^AHT

Data Setup Time

Data Hold Time

t^DVWH

t^WHDX

tDS

tDH

60

0

⎯

16

1

⎯

60

0

⎯

16

1

⎯

ns

µs

s

Read

0

Output Enable

Hold Time

—

t^OEH

Toggle and Data Polling

10

20

0

10

20

0

CE High During Toggle Bit Polling

OE High During Toggle Bit Polling

Read Recover Time Before Write

CE Setup Time

—

tCEPH

tOEPH

tGHWL

tGHEL

tCS

t^GHWL

t^GHEL

tELWL

tWLEL

tWHEH

tEHWH

t^WLWH

tELEH

t^WHWL

tEHEL

t^WHWH1

tWHWH2

—

0

WE Setup Time

tWS

0

CE Hold Time

tCH

0

WE Hold Time

tWH

0

Write Pulse Width

tWP

60

⎯

50

500

4

60

⎯

50

500

4

CE Pulse Width

tCP

Write Pulse Width High

CE Pulse Width High

Programming Operation

Sector Erase Operation *¹

V^CCSetup Time

tWPH

tCPH

tWHWH1

tWHWH2

tVCS

⎯

µs

ns

µs

Rise Time to V^ID*²

Rise Time to V^ACC*³

—

tVIDR

tVACCR

tVLHT

tWPP

tOESP

—

Voltage Transition Time *²

Write Pulse Width *²

OE Setup Time to WE Active *²

—

100

4

100

4

—

(Continued)

42

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

(Continued)

Value

Symbol

Parameter

10

11

Unit

JEDEC Standard Min Typ Max Min Typ Max

CE Setup Time to WE Active *²

Recover Time from RY/BY

—

tCSP

tRB

4

0

—

4

0

—

µs

ns

µs

ns

RESET Pulse Width

tRP

500

200

—

500

200

—

RESET High Level Period Before Read

Program/Erase Valid to RY/BY Delay

Delay Time from Embedded Output Enable

Erase Time-out Time

tRH

—

tBUSY

t^EOE

t^TOW

t^SPD

t^PS

90

100

90

115

—

50

—

50

—

Erase Suspend Transition Time

Power On / Off Time

20

115

—

100

—

*1: This does not include the preprogramming time.

*2: This timing is for Sector Group Protection operation.

*3: This timing is for Accelerated Program operation.

43

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

■ ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Unit

Comments

Min

Typ

Max

Excludes programming time

prior to erasure

Sector Erase Time

—

1

10

s

Excludes system-level

overhead

Word Programming Time

—

16

360

μs

Excludes system-level

overhead

Chip Programming Time

Program/Erase Cycle

—

100

—

s

100,000

cycle

—

FBGA PIN CAPACITANCE

Parameter

Value

Unit

Symbol

Condition

Typ

Max

7.5

Input Capacitance

C^IN

C^OUT

C^IN2

CIN3

VIN = 0

6.0

8.5

pF

Output Capacitance

VOUT = 0

VIN = 0

12.0

9.0

Control Pin Capacitance

WP/ACC Pin Capacitance

7.5

13.0

16.0

Note: Test conditions T^A= 25°C, f = 1.0 MHz

44

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

■ TIMING DIAGRAM

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Must Be

Steady

Will Be

Steady

May

Change

from H to L

Will Be

Changing

from H to L

May

Change

from L to H

Will Be

Changing

from L to H

"H" or "L":

Any Change

Permitted

Changing,

State

Unknown

Does Not

Apply

Center Line is

High-

Impedance

"Off" State

t^RC

Address

Address Stable

tACC

CE

OE

tOE

tDF

tOEH

WE

tOH

tCE

High-Z

Output Valid

Outputs

Read Operation Timing Diagram

45

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

tRC

Address

Address Stable

tACC

CE

tRH

tRP

tRH

tCE

RESET

Outputs

tOH

High-Z

Outputs Valid

Hardware Reset/Read Operation Timing Diagram

46

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

A2 to A20

A0 to A1

Same Page Address

Aa

Ab

Ac

t^RC

tPRC

tACC

CE

OE

tCE

tOEH

tOE

tDF

tPACC

tOH

tPACC

tOH

WE

tOH

High-Z

Output

Da

Db

Dc

Page Read Operation Timing Diagram

47

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

3rd Bus Cycle

Data Polling

PA

Address

CE

PA

555h

tWC

tAS

tAH

tRC

tCS

tCH

tCE

OE

tWP

tOE

tWHWH1

tWPH

tGHWL

WE

tDH

tDS

tDF

tOH

A0h

PD

DQ7

DOUT

Data

Notes: • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ⁷is the output of the complement of the data written to the device.

• D^OUTis the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

Alternate WE Controlled Program Operation Timing Diagram

48

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

3rd Bus Cycle

Data Polling

Address

WE

PA

555h

tWC

tAH

tAS

tWS

tWH

OE

CE

tWHWH1

tCP

tCPH

tGHEL

tDS

tDH

A0h

PD

DQ7

DOUT

Data

Notes: • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ⁷is the output of the complement of the data written to the device.

• D^OUTis the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

Alternate CE Controlled Program Operation Timing Diagram

49

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

Address

CE

2AAh

555h

tWC

2AAh

SA *

tAH

tAS

tCS

tCH

OE

tWP

tGHWL

tWPH

WE

tDS

10h for Chip Erase

tDH

10h/

30h

AAh

55h

80h

AAh

55h

Data

tVCS

VCC

*: SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.

Chip/Sector Erase Operation Timing Diagram

50

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

CE

tCH

tDF

tOE

OE

tOEH

WE

tCE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

tWHWH1 or 2

DQ⁶to DQ0 =

Output Flag

DQ⁶to DQ0

Valid Data

DQ6 to DQ0

RY/BY

tEOE

tBUSY

*: DQ7 = Valid Data (The device has completed the Embedded operation).

Data Polling during Embedded Algorithm Operation Timing Diagram

51

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

CE

tOEH

WE

tOES

OE

tDH

*

DQ⁶=

Stop Toggle

DQ7 = DQ0

Data Valid

Data (DQ7 to DQ0)

DQ⁶= Toggle

DQ6 = Toggle

DQ6

tOE

*: DQ6 stops toggling (The device has completed the Embedded operation).

Toggle Bit I during Embedded Algorithm Operation Timing Diagram

52

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

Read

tRC

Command

tWC

Read

tRC

Command

tWC

Read

tRC

Read

tRC

BA2

(PA)

BA2

(PA)

BA1

Address

CE

BA1

(555h)

tAS

tACC

tAH

tAS

tAHT

tCE

tCEPH

tOE

OE

tGHWL

tOEH

tDF

tWP

tDS

WE

DQ

tDH

tDF

Valid

Output

Valid

Input

Valid

Output

Valid

Input

Valid

Output

Status

(A0h)

(PD)

Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1: Address corresponding to Bank 1.

BA2: Address corresponding to Bank 2.

Bank-to-Bank Read/Write Timing Diagram

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase Suspend

Read

Erase Suspend

Read

WE

Erase

Suspend

Program

Erase

Complete

DQ

6

2*

Toggle

DQ²and DQ6

with OE or CE

* : DQ2 is read from the erase-suspended sector.

DQ2 vs. DQ6

53

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

CE

Rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

tBUSY

RY/BY Timing Diagram during Program/Erase Operation Timing Diagram

WE

RESET

tRP

tRB

RY/BY

tREADY

RESET, RY/BY Timing Diagram

54

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

tPS

RESET

VIH

VCC

1.8 V

0 V

Valid Data In

Address

Data

Valid Data Out

tRH

tACC

Power On / Off Timing Diagram

55

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

A20, A19, A18

SPAX

SPAY

A17, A16, A15

A14, A13, A12

A6, A3, A2, A0

A1

VID

VIH

A9

tVLHT

VID

VIH

OE

tVLHT

tWPP

WE

tOESP

tCSP

CE

01h

Data

VCC

tOE

tVCS

SPAX: Sector Group Address to be protected

SPAY: Next Sector Group Address to be protected

Sector Group Protection Timing Diagram

56

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

VCC

tVIDR

tVCS

tVLHT

VID

VIH

RESET

CE

WE

tVLHT

Program or Erase Command Sequence

Unprotection Period

RY/BY

Temporary Sector Group Unprotection Timing Diagram

57

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

VCC

tVCS

tVLHT

RESET

tWC

tVIDR

Address

SPAX

SPAY

A6, A3,

A2, A0

A1

CE

OE

TIME-OUT

tWP

WE

60h

40h

01h

60h

Data

tOE

SPAX: Sector Group Address to be protected

SPAY: Next Sector Group Address to be protected

TIME-OUT: Time-Out window = 250 μs (Min)

Extended Sector Group Protection Timing Diagram

58

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

VCC

tVACCR

tVCS

tVLHT

VACC

VIH

WP/ACC

CE

WE

tVLHT

Program Command Sequence

Acceleration Period

RY/BY

Accelerated Program Timing Diagram

59

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

■ FLOW CHARTS

EMBEDDED ALGORITHM

Start

Write Program

Command Sequence

(See Below)

Data Polling

Embedded

Program

Algorithm

in program

No

Verify Data

?

Yes

No

Increment Address

Last Address

?

Yes

Programming Completed

Program Command Sequence (Address/Command):

555h/AAh

2AAh/55h

555h/A0h

Program Address/Program Data

Embedded Program^TMAlgorithm

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Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

EMBEDDED ALGORITHM

Start

Write Erase

Command Sequence

(See Below)

Data Polling

Embedded

Erase

Algorithm

in progress

No

Data = FFh

?

Yes

Erasure Completed

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

Chip Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

Sector Address

/30h

Sector Address

/30h

Additional sector

erase commands

are optional.

Sector Address

/30h

Embedded Erase^TMAlgorithm

61

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

Start

Read Byte

(DQ⁷to DQ0)

Addr. = VA

VA=Address for programming

=Any of the sector address within

the sector being erased during

sector erase or multiple sector

erases operation

Yes

DQ7 = Data?

No

=Any of the sector addresses

within the sector not being

protected during chip erase

operation.

No

DQ5 = 1?

Yes

Read Byte

(DQ⁷to DQ0)

Addr. = VA

Yes

DQ7 = Data?

*

No

Fail

Pass

*: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Data Polling Algorithm

62

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Start

VA=Bank address being executed

Embedded Algorithm.

Read DQ

7

to DQ

0

Addr. = VA

*1

Read DQ

7

to DQ

0

Addr. = VA

No

DQ

6

= Toggle?

Yes

No

DQ5

= 1?

Yes

*1, *2

Read DQ7 to DQ0

Addr. = VA

*1, *2

Read DQ

7

to DQ

0

Addr. = VA

No

DQ

6

= Toggle?

Yes

Fail

Pass

*1: Read toggle bit twice to determine whether it is toggling.

*2: Recheck toggle bit because it may stop toggling as DQ⁵changes to “1”.

Toggle Bit Algorithm

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Start

Setup Sector Group Addr.

A²⁰, A19, A18, A17, A16,

(

)

A15, A14, A13, A12

PLSCNT = 1

OE = VID, A9 = VID

CE = VIL, RESET = VIH

A6 = A3 = A2 = A0 = VIL, A1 = VIH

Activate WE Pulse

Increment PLSCNT

Time out 100 μs

WE = V^IH, CE = OE = VIL

(A9 should remain VID)

Read from Sector Group

Addr. = SPA, A¹= VIH

A6 = A3 = A2 = A0 = VIL

(

)

No

PLSCNT = 25?

Yes

No

Data = 01h?

Yes

Remove V^IDfrom A9

Write Reset Command

Protect Another Sector

Group?

No

Remove V^IDfrom A9

Write Reset Command

Device Failed

Sector Group Protection

Completed

Sector Group Protection Algorithm

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Start

RESET = V^ID

*1

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector Group

Unprotection Completed

*2

*1: All protected sector groups are unprotected.

*2: All previously protected sector groups are protected once again.

Temporary Sector Group Unprotection Algorithm

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Start

RESET = VID

Wait to 4 μs

Device is Operating in

No

Extended Sector Group

Temporary Sector Group

Protection Entry?

Unprotection Mode

Yes

To Setup Sector Group Protection

Write XXXh/60h

PLSCNT = 1

To Protect Secter Group

Write 60h to Secter Address

(A⁶= A3 = A2 = A0 = VIL, A1 = VIH)

Time out 250 μs

To Verify Sector Group Protection

Increment PLSCNT

No

Write 40h to Secter Address

(A⁶= A3 = A2 = A0 = VIL, A1 = VIH)

Read from Sector Group Address

(Addr. = SPA,

A⁶= A3 = A2 = A0 = VIL, A1 = VIH)

Setup Next Sector Address

No

Data = 01h?

PLSCNT = 25?

Yes

Protect Other Sector

Group?

Remove V^IDfrom RESET

Write Reset Command

No

Remove VID from RESET

Write Reset Command

Device Failed

Sector Protection

Completed

Extended Sector Group Protection Algorithm

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FAST MODE ALGORITHM

Start

555h/AAh

2AAh/55h

Set Fast Mode

555h/20h

XXXh/A0h

In Fast Program

Program Address/Program Data

Data Polling

No

Verify Data?

Yes

No

Last Address?

Yes

Increment Address

Programming Completed

XXXh/90h

XXXh/F0h

Reset Fast Mode

Embedded Program^TMAlgorithm for Fast Mode

67

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■ ORDERING INFORMATION

Part No.

Package

Access Time (ns)

Sector Architecture

MBM29PDS322TE10PBT

MBM29PDS322TE11PBT

63-pin plastic FBGA

(BGA-63P-M01)

100

115

Top sector

MBM29PDS322BE10PBT

MBM29PDS322BE11PBT

63-pin plastic FBGA

(BGA-63P-M01)

100

115

Bottom sector

MBM29PDS322

T

E

10

PBT

PACKAGE TYPE

PBT =63-Ball Fine pitch Ball Grid Array

Package (FBGA)

SPEED OPTION

See Product Selector Guide

DEVICE REVISION

BOOT CODE SECTOR ARCHITECTURE

T = Top sector

B = Bottom sector

DEVICE NUMBER/DESCRIPTION

MBM29PDS322

32 Mega-bit (2 M × 16-Bit) CMOS Flash Memory

1.8 V-only Read, Program, and Erase

68

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■ PACKAGE DIMENSION

63-pin plastic FBGA

(BGA-63P-M01)

11.00±0.10(.433±.004)

1.05 –⁺0⁰.^.1¹0⁵

(8.80(.346))

(7.20(.283))

.041 –⁺.^.0⁰0⁰4⁶

(Mounting height)

0.38±0.10

(.015±.004)

(Stand off)

(5.60(.220))

0.80(.031)TYP

8

7

6

5

4

3

2

1

(4.00(.157))

(5.60(.220))

7.00±0.10

(.276±.004)

M

L

K

J

H

G

F

E

D

C

B

A

INDEX AREA

INDEX BALL

63-ø0.45±0.05

(63-ø0.18±.002)

M

0.08(.003)

0.10(.004)

C

2001 FUJITSU LIMITED B63001S-c-2-2

Dimensions in mm (inches).

Note : The values in parentheses are reference values.

69

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MEMO

70

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Revision History

Revision DS05-20889-6E（July 31, 2007）

The following comment is added.

This product has been retired and is not recommended for new designs. Availability of this

document is retained for reference and historical purposes only.

71

Retired ProductꢀDS05-20889-6E_July 31, 2007

MBM29PDS322TE10/11/MBM29PDS322BE10/11

FUJITSU LIMITED

For further information please contact:

Japan

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

FUJITSU LIMITED

Marketing Division

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Electronic Devices

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3353

Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94088-3470, U.S.A.

Tel: +1-408-737-5600

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fme.fujitsu.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Singapore 556741

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Tel: +65-6281-0770

Fax: +65-6281-0220

http://www.fmal.fujitsu.com/

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

F0305

Retired ProductꢀDS05-20889-6E_July 31, 2007


型号：	MBM29PDS322BE10PBT
厂家：	SPANSION
描述：	Flash, 2MX16, 100ns, PBGA63, PLASTIC, FBGA-63 内存集成电路
文件：	总72页 (文件大小：379K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MBM29PDS322BE10PBT [SPANSION]

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