MBM29PL160TD90PFTR [SPANSION]
1MX16 FLASH 3V PROM, 90ns, PDSO48, PLASTIC, REVERSE, TSOP1-48;
| 型号： | MBM29PL160TD90PFTR |
| 厂家： | 
SPANSION |
| 描述： | 1MX16 FLASH 3V PROM, 90ns, PDSO48, PLASTIC, REVERSE, TSOP1-48 可编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总51页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
SPANSION Flash Memory
Data Sheet
September 2003
This document specifies SPANSIONTM memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSIONTM product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSIONTM memory
solutions.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20872-3E
PAGE MODE FLASH MEMORY
CMOS
16M (2M × 8/1M × 16) BIT
MBM29PL160TD/BD-75/90
■ DESCRIPTION
The MBM29PL160TD/BD is a 16 M-bit, 3.0 V-only Flash memory organized as 2 M bytes of 8 bits each or 1M
words of 16 bits each. The MBM29PL160TD/BD is offered in a 48-pin TSOP (1), and 44-pin SOP packages. The
device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V
VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM
programmers.
(Continued)
■ PRODUCT LINE UP
Part No.
VCC = 3.0 V
MBM29PL160TD/160BD
+0.6 V
–0.3 V
Ordering Part No.
-75
-90
Max Address Access Time (ns)
Max Page Address Access Time (ns)
Max CE Access Time (ns)
75
25
75
25
90
35
90
35
Max OE Access Time (ns)
■ PACKAGES
48-pin plastic TSOP (1)
Marking Side
48-pin plastic TSOP (1)
44-pin plastic SOP
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(FPT-44P-M16)
MBM29PL160TD/BD-75/90
(Continued)
The standard MBM29PL160TD/BD offers access times of 75 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29PL160TD/BD is pin and command set compatible with JEDEC standard E2PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the device is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29PL160TD/BD is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margins. Typically, each sector can be programmed and verified in about 2.0 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.
Any individual sector is typically erased and verified in 4.8 second (If already preprogrammed).
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29PL160TD/BD is erased when shipped from the
factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7
or by the Toggle Bit feature on DQ6 output pin. Once the end of a program or erase cycle has been comleted,
the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29PL160TD/BD memory electrically erases all bits
within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word
at a time using the EPROM programming mechanism of hot electron injection.
2
MBM29PL160TD/BD-75/90
■ FEATURES
• Single 3.0 V read, program and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with MASK ROM pinouts
48-pin TSOP (1) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type)
44-pin SOP (Package suffix: PF)
• Minimum 100,000 program/erase cycles
• High performance
25 ns maximum page access time (75 ns maximum random access time)
• An 8 words page read mode function
• Sector erase architecture
One 8 K word, two 4 K words, one 112 K word, and seven 128 K words sectors in word mode
One 16 K byte, two 8 K bytes, one 224 K byte, and seven 256 K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded programTM* Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Temporary sector unprotection
Temporary sector unprotection with the software command
• 5 V tolerant (Data, Address, and Control Signals)
• In accordance with CFI (Common Flash Memory Interface)
*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
3
MBM29PL160TD/BD-75/90
■ PIN ASSIGNMENTS
SOP
TSOP(1)
(Marking Side)
BYTE
N.C.
VSS
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
(Marking Side)
A16
A15
A14
A13
A12
A11
A10
A9
1
2
44
43
2
WE
A18
N.C.
A19
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
3
4
5
6
A17
A7
A6
A5
A8
3
4
5
6
7
8
42
41
40
39
38
37
7
8
A9
9
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A10
A11
A19
WE
N.C.
A18
A17
A7
VCC
VSS
Normal Bend
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
A4
A3
A12
A13
A6
A5
A4
A2
A1
9
36
35
34
33
A14
A15
A3
A2
10
11
12
A1
A0
VSS
N.C.
CE
A0
A16
(FPT-48P-M19)
(Marking Side)
CE
BYTE
VSS
OE
13
14
32
31
VSS
DQ15/A-1
DQ0
DQ7
15
16
30
29
CE
A0
N.C.
VSS
OE
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQ8
DQ1
DQ9
DQ14
DQ6
A1
A2
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VSS
17
28
A3
A4
DQ13
18
19
27
26
A5
A6
DQ2
DQ5
A7
A17
A18
N.C.
WE
A19
A8
DQ10
DQ12
20
21
22
25
24
23
Reverse Bend
VCC
VCC
DQ3
DQ4
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
DQ11
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
8
7
6
(FPT-44P-M16)
5
4
3
2
N.C.
1
(FPT-48P-M20)
4
MBM29PL160TD/BD-75/90
■ PIN DESCRIPTIONS
Pin name
A19 to A0, A-1
DQ15 to DQ0
CE
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
OE
Output Enable
WE
Write Enable
BYTE
VSS
Selects 8-bit or 16-bit mode
Device Ground
VCC
Device Power Supply (2.7 V to 3.6 V)
Pin Not Connected Internally
N.C.
5
MBM29PL160TD/BD-75/90
■ BLOCK DIAGRAM
DQ15 to DQ0
VCC
VSS
Input/Output
Buffers
Erase Voltage
Generator
State
Control
WE
BYTE
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
CE
OE
Y-Gating
Y-Decoder
X-Decoder
STB
Timer for
Program/Erase
Address
Latch
Low VCC Detector
Cell Matrix
A19 to A0
A-1
■ LOGIC SYMBOL
A-1
20
A19 to A0
16 or 8
DQ15 to DQ0
CE
OE
WE
BYTE
6
MBM29PL160TD/BD-75/90
■ DEVICE BUS OPERATIONS
MBM29PL160TD/BD User Bus Operation Table (BYTE = VIH)
Operation
Auto-Select Manufacture Code *1
Auto-Select Device Code *1
Read *3
CE
L
OE
L
WE
H
A0
L
A1
L
A6
L
A9
VID
VID
A9
X
DQ15 to DQ0
Code
Code
DOUT
L
L
H
H
A0
X
L
L
L
L
H
A1
X
A6
X
X
A6
L
Standby
H
L
X
X
High-Z
High-Z
DIN
Output Disable
H
H
VID
L
H
X
X
X
Write (Program/Erase)
Enable Sector Protection *2, *4
Verify Sector Protection *2, *4
L
L
A0
L
A1
H
H
A9
VID
VID
L
X
L
H
L
L
Code
Legend: L = VIL, H = VIH, X = VIL or VIH.
= pulse input. See “■DC CHARACTERISTICS” for voltage levels.
*1: Manufacturer and device codes may also be accessed via a command register write sequence. See
"MBM29PL160TD/BD Standard Command Definitions Table".
*2: Refer to the section on “Sector Protection” in ■FUNCTIONAL DESCRIPTION.
*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4: VCC = 3.3 V ±10%
MBM29PL160TD/BD User Bus Operation Table (BYTE = VIL)
DQ15/
A-1
Operation
CE OE WE
A0
A1
A6
A9
DQ7 to DQ0
Auto-Select Manufacture Code *1
Auto-Select Device Code *1
Read *3
L
L
L
H
L
L
L
L
L
L
H
H
H
X
H
L
L
L
H
A0
X
L
L
L
L
VID
VID
A9
X
Code
Code
DOUT
High-Z
High-Z
DIN
L
L
A-1
X
A1
X
A6
X
X
A6
L
Standby
X
Output Disable
H
H
VID
L
X
X
X
X
Write (Program/Erase)
Enable Sector Protection *2, *4
Verify Sector Protection *2, *4
A-1
L
A0
L
A1
H
H
A9
VID
VID
X
H
L
L
L
Code
Legend: L = VIL, H = VIH, X = VIL or VIH.
= pulse input. See “■DC CHARACTERISTICS” for voltage levels.
*1: Manufacturer and device codes may also be accessed via a command register write sequence. See
"MBM29PL160TD/BD Standard Command Definitions Table".
*2: Refer to the section on “Sector Protection” in ■FUNCTIONAL DESCRIPTION.
*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4: VCC = 3.3 V ±10%
7
MBM29PL160TD/BD-75/90
MBM29PL160TD/BD Standard Command Definitions Table
Fourth Bus
Read/Write
Cycle
First Bus Second Bus Third Bus
Write Cycle Write Cycle Write Cycle
Fifth Bus
Sixth Bus
Bus
Write
Cycles
Req'd
Command
Sequence
Write Cycle Write Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Word
Read/Reset *1
Read/Reset *2
1
3
XXXh F0h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
/Byte
Word
Byte
555h
AAh
2AAh
555h
2AAh
555h
2AAh
555h
2AAh
555h
2AAh
555h
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
55h
F0h RA*2 RD*2
AAAh
Word
Byte
555h
AAh
3
4
6
6
55h
55h
55h
55h
90h
A0h
80h
80h
IA*2
PA
ID*2
PD
—
—
—
—
—
—
—
—
Autoselect
AAAh
Word
Byte
555h
AAh
Byte/Word
Program
AAAh
Word
Byte
555h
AAh
555h
AAAh
555h
AAAh
2AAh
555h
2AAh
555h
555h
Chip Erase
AAh
AAh
55h
55h
10h
30h
AAAh
AAAh
Word
Byte
555h
AAh
Sector Erase
SA
AAAh
Sector Erase
Suspend
Erase can be suspended during sector erase with Addr (“H” or “L”), Data (B0h)
Erase can be resumed after suspend with Addr (“H” or “L”), Data (30h)
Sector Erase
Resume
Temporary
Unprotect
Enable
Word
Byte
Word
Byte
555h
AAAh
555h
AAAh
2AAh
555h
2AAh
555h
555h
AAAh
555h
AAAh
4
4
AAh
AAh
55h
55h
E0h XXXh 01h
E0h XXXh 00h
—
—
—
—
—
—
—
—
Temporary
Unprotect Dis-
able
*1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*2: The fourth bus cycle is only for read.
Notes : • Address bits A19 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA).
• Bus operations are defined in "MBM29PL160TD/BD User Bus Operation Tables (BYTE = VIH and
BYTE = VIL)".
• RA = Address of the memory location to be read.
IA = Autoselect read address that sets A6, A1, A0.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of
the WE pulse.
SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
• RD = Data read from location RA during read operation.
ID = Device code/manufacture code for the address located by IA.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
• The system should generate the following address patterns:
Word Mode: 555h or 2AAh to addresses A10 to A0
Byte Mode: AAAh or 555h to addresses A10 to A-1
• The command combinations not described in “MBM29PL160TD/BD Standard Command Definitions
Table” are illegal.
8
MBM29PL160TD/BD-75/90
MBM29PL160TD/BD Extended Command Definitions Table
Bus
Write
First Bus
Second Bus
Write Cycle
Third Bus
Fourth Bus
Read Cycle
Command
Sequence
Write Cycle
Write Cycle
Cycles
Req'd
Addr
Data
Addr
2AAh
555h
Data
Addr
Data
Addr
Data
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555h
AAAh
XXXh
XXXh
XXXh
XXXh
55h
555h
Set to Fast
3
2
2
2
AAh
55h
20h
—
—
Mode
AAAh
Fast Program *1
A0h
90h
98h
PA
PD
F0h *3
—
—
—
—
—
—
—
—
—
—
—
—
—
XXXh
XXXh
Reset from Fast
Mode *1
Query
—
Command *2
AAh
*1: This command is valid during fast mode.
*2: Addresses from system set to A6 to A0. The other addresses are “Don’t care”.
*3: The data “00h” is also acceptable.
MBM29PL160TD/BD Sector Protection Verify Autoselect Code Table
Code
A-1*1
Type
Manufacture’s Code
A19 to A12
A6
A1
A0
(HEX)
X
VIL
VIL
VIL
VIL
VIL
X
04h
Byte
Word
Byte
27h
MBM29PL160TD
MBM29PL160BD
X
X
VIL
VIL
VIL
VIL
VIH
VIH
2227h
45h
Device Code
VIL
X
Word
2245h
Sector
Addresses
VIH
VIH
VIL
VIH
VIL
VIL
01h*2
01h*3
Sector Protection
VIL
Temporary Sector Unprotection
*1: A-1 is for Byte mode.
X
VIL
*2: Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.
*3: Outputs 01h at temporary sector unprotect and outputs 00h at non temporary sector unprotect.
9
MBM29PL160TD/BD-75/90
Expanded Autoselect Code Table
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Type
Manufacture’s Code*
04h A-1/0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
(B)
(W) 2227h
27h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
MBM29PL160TD
0
0
1
0
0
0
1
0
Device
Code
(B)
45h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
MBM29PL160BD
(W)
2245h
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
Sector Protection*
01h A-1/0
01h A-1/0
Temporary Sector
Unprotection
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
(B): Byte mode
(W): Word mode
HI-Z: High-Z
* : In byte mode, DQ15 to DQ8 are High-Z and DQ15 is A-1, the lowest address.
10
MBM29PL160TD/BD-75/90
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
• One 8 K word, two 4 K words, one 112 K word, and seven 128 K words sectors in word mode.
• One 16 K byte, two 8 K bytes, one 224 K byte, and seven 256 K bytes sectors in byte mode.
• Individual-sector, multiple-sector, or bulk-erase capability.
• Individual or multiple-sector protection is user definable.
MBM29PL160TD Top Boot Sector Architecture
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
Sector Size
(× 8) Address Range
000000h to 03FFFFh
040000h to 07FFFFh
080000h to 0BFFFFh
0C0000h to 0FFFFFh
100000h to 13FFFFh
140000h to 16FFFFh
180000h to 1BFFFFh
1C0000h to 1F7FFFh
1F8000h to 1F9FFFh
1FA000h to 1FBFFFh
1FC000h to 1FFFFFh
(× 16) Address Range
00000h to 1FFFFh
20000h to 3FFFFh
40000h to 5FFFFh
60000h to 7FFFFh
80000h to 9FFFFh
A0000h to BFFFFh
C0000h to DFFFFh
E0000h to FBFFFh
FC000h to FCFFFh
FD000h to FDFFFh
FE000h to FFFFFh
256 Kbytes or 128 Kwords
256 Kbytes or 128 Kwords
256 Kbytes or 128 Kwords
256 Kbytes or 128 Kwords
256 Kbytes or 128 Kwords
256 Kbytes or 128 Kwords
256 Kbytes or 128 Kwords
224 Kbytes or 112 Kwords
8 Kbytes or 4 Kwords
8 Kbytes or 4 Kwords
16 Kbytes or 8 Kwords
MBM29PL160BD Bottom Boot Sector Architecture
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
Sector Size
(× 8) Address Range
000000h to 003FFFh
004000h to 005FFFh
006000h to 007FFFh
008000h to 03FFFFh
040000h to 07FFFFh
080000h to 0BFFFFh
0C0000h to 0FFFFFh
100000h to 13FFFFh
140000h to 17FFFFh
180000h to 1BFFFFh
1C0000h to 1FFFFFh
(× 16) Address Range
00000h to 01FFFh
02000h to 02FFFh
03000h to 03FFFh
04000h to 1FFFFh
20000h to 3FFFFh
40000h to 5FFFFh
60000h to 7FFFFh
80000h to 9FFFFh
A0000h to BFFFFh
C0000h to DFFFFh
E0000h to FFFFFh
16 Kbytes or 8 Kwords
8 Kbytes or 4 Kwords
8 Kbytes or 4 Kwords
224 Kbytes or 112 Kwords
256 Kbytes or 128 Kwords
256 Kbytes or 128 Kwords
256 Kbytes or 128 Kwords
256 Kbytes or 128 Kwords
256 Kbytes or 128 Kwords
256 Kbytes or 128 Kwords
256 Kbytes or 128 Kwords
11
MBM29PL160TD/BD-75/90
Sector Address Table (MBM29PL160TD)
Sector
Address
A19
A18
A17
A16
A15
A14
A13
A12
(× 8) Address Range (× 16) Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 03FFFFh
040000h to 07FFFFh
080000h to 0BFFFFh
0C0000h to 0FFFFFh
100000h to 13FFFFh
140000h to 16FFFFh
180000h to 1BFFFFh
1C0000h to 1F7FFFh
1F8000h to 1F9FFFh
1FA000h to 1FBFFFh
1FC000h to 1FFFFFh
00000h to 1FFFFh
20000h to 3FFFFh
40000h to 5FFFFh
60000h to 7FFFFh
80000h to 9FFFFh
A0000h to BFFFFh
C0000h to DFFFFh
E0000h to FBFFFh
FC000h to FCFFFh
FD000h to FDFFFh
FE000h to FFFFFh
00000 - 11011
1
1
1
1
1
1
1
1
1
0
0
1
0
1
X
Sector Address Table (MBM29PL160BD)
Sector
Address
A19
A18
A17
A16
A15
A14
A13
A12
(× 8) Address Range (× 16) Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
X
0
1
000000h to 003FFFh
004000h to 005FFFh
006000h to 007FFFh
008000h to 03FFFFh
040000h to 07FFFFh
080000h to 0BFFFFh
0C0000h to 0FFFFFh
100000h to 13FFFFh
140000h to 17FFFFh
180000h to 1BFFFFh
1C0000h to 1FFFFFh
00000h to 01FFFh
02000h to 02FFFh
03000h to 03FFFh
04000h to 1FFFFh
20000h to 3FFFFh
40000h to 5FFFFh
60000h to 7FFFFh
80000h to 9FFFFh
A0000h to BFFFFh
C0000h to DFFFFh
E0000h to FFFFFh
00100 - 11111
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
12
MBM29PL160TD/BD-75/90
Common Flash Memory Interface Code Table
Description
A0 to A6 DQ15 toDQ0
Description
A0 to A6 DQ15 toDQ0
10h
11h
12h
0051h
0052h
0059h
2Dh
2Eh
2Fh
30h
0000h
0000h
0040h
0000h
Query-unique ASCII string
“QRY”
Erase Block Region 1
Information
Primary OEM Command Set
2h : AMD/FJ standard type
13h
14h
0002h
0000h
31h
32h
33h
34h
0001h
0000h
0020h
0000h
Erase Block Region 2
Information
Address for Primary Extended
Table
15h
16h
0040h
0000h
Alternate OEM Command Set
(00h = not applicable)
17h
18h
0000h
0000h
35h
36h
37h
38h
0000h
0000h
0080h
0003h
Erase Block Region 3
Information
Address for Alternate OEM
Extended Table
19h
1Ah
0000h
0000h
VCC Min (write/erase)
DQ7 to DQ4 : 1 V,
DQ3 to DQ0 : 100 mV
39h
3Ah
3Bh
3Ch
0006h
0000h
0000h
0004h
1Bh
1Ch
0027h
0036h
Erase Block Region 4
Information
VCC Max (write/erase)
DQ7 to DQ4 : 1 V,
DQ3 to DQ0 : 100 mV
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string
“PRI”
VPP Min voltage
VPP Max voltage
1Dh
1Eh
0000h
0000h
Major version number, ASCII
Minor version number, ASCII
43h
44h
0031h
0030h
Typical timeout per single byte/
word write 2N µs
1Fh
20h
21h
22h
23h
24h
25h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
Address Sensitive Unlock
0 = Required
1 = Not Required
Typical timeout for Min size
buffer write 2N µs
45h
0000h
Typical timeout per individual
block erase 2N ms
Erase Suspend
0 = Not Supported
1 = To Read Only
2 = To Read & Write
46h
0002h
Typical timeout for full chip
erase 2N ms
Sector Protect
Max timeout for byte/word
write 2N times typical
0 = Not Supported
X = Number of sectors in per
group
47h
48h
0001h
0001h
Max timeout for buffer write
2N times typical
Sector Temporary Unprotect
00 = Not Supported
01 = Supported
Max timeout per individual
block erase 2N times typical
Max timeout for full chip erase
2N times typical
Device Size = 2N byte
Sector Protection Algorithm
Number of Sector for Bank 2
49h
4Ah
0004h
00h
26h
27h
0000h
0015h
Burst Mode Type
00 = Not supported
4Bh
00h
Flash Device Interface
description
28h
29h
0002h
0000h
Page Mode Type
00 = Not supported
01 = 4 word Page
02 = 8 word Page
Max number of byte in
multi-byte write = 2N
2Ah
2Bh
0000h
0000h
4Ch
02h
Number of Erase Block
Regions within device
2Ch
0004h
13
MBM29PL160TD/BD-75/90
■ FUNCTIONAL DESCRIPTION
Random Read Mode
The MBM29PL160TD/BD has two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins (Assuming the
addresses have been stable for at least tACC - tOE time). See "(1) AC Waveforms for Read Operations" in ■TIMING
DIAGRAM for timing specifications. When reading out a data without changing addresses after powe-up, it is
necessary to input hardware reset or to change CE pin from "H" to "L".
Page Read Mode
The MBM29PL160TD/BD is capable of fast Page read mode and is compatible with the Page mode MASK ROM
read operation. This mode provides faster read access speed for random locations within a page. The Page size
of the MBM29PL160TD/BD device is 8 words, or 16 bytes, within the appropriate Page being selected by the
higheraddress bits A2 to A0 (in the word mode) and A2 to A-1 (in the byte mode) determining the specific word/
byte within that page. This is an asynchronous operation with the microprocessor supplying the specific word
or byte location.
The rondom or initial page access is equal to tACC and subsequent Page read access (as long as the locations
specified by the microprocessor fall within that Page) is equivalent to tPACC. Here again, CE selects the device
and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast
Page mode accesses are obtained by keeping A19 to A3 constant and changing A2 to A0 to select the specific
word, or changing A2 to A-1 to select the specific byte, within that page. See "(2) AC Waveforms for Page Read
Mode Operations" in ■TIMING DIAGRAM for timing specifications.
Standby Mode
The MBM29PL160TD/BD has a standby mode, a CMOS standby mode (CE input held at VCC ±0.3 V.), when
the current consumed is less than 50 µA. During Embedded Algorithm operation, VCC Active current (ICC2) is
required even CE = “H”. The device can be read with standard access time (tCE) from standby modes.
In the standby mode, the outputs are in the high-impedance state, independent of the OE input. If the device
is deselected during erasure or programming, the device will draw active current until the operation is completed.
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29PL160TD/BD data. This mode can be used effectively with an application requesting low power
consumption such as handy terminals.
To activate this mode, MBM29PL160TD/BD automatically switches itself to low power mode when addresses
remain stable for 150 ns. It is not necessary to control CE, WE, and OE in this mode. During such mode, the
current consumed is typically 50 µA (CMOS Level).
Standard address access timings provide new data when addresses are changed. While in sleep mode, output
data is latched and always available to the system.
Output Disable
If the OE input is at a logic high level (VIH), output from the device is disabled. This will cause the output pins to
be in a High-Z state.
14
MBM29PL160TD/BD-75/90
Autoselect
The Autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. The intent is to allow programming equipment to automatically match the device to be programmed
with its corresponding programming algorithm. The Autoselect command may also be used to check the status
of write-protected sectors (See "MBM29PL160TD/BD Sector Protection Verify Autoselect Code Table" and
"Expanded Autoselect Code Table" in ■DEVICE BUS OPERATIONS). This mode is functional over the entire
temperature range of the device.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, and A6 (A-1). (See "MBM29PL160TD/BD User Bus Operation Table
(BYTE = VIH or BYTE = VIL)" in ■DEVICE BUS OPERATIONS.) (Recommend to set VIL for the other addresses
pins.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29PL160TD/BD is erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in "MBM29PL160TD/BD Standard Command Definitions Table" in ■DEVICE
BUS OPERATIONS (see “Autoselect Command” in ■COMMAND DEFINITIONS.
Word 0 (A0 = VIL) represents the manufacture’s code and word 1 (A0 = VIH) represents the device identifier code.
For the MBM29PL160TD/BD these two bytes are given in "Expanded Autoselect Code Table" (■DEVICE BUS
OPERATIONS). All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity
bit. In order to read the proper device codes when executing the Autoselect, A1 must be VIL. (See
"MBM29PL160TD/BD User Bus Operation Table (BYTE = VIH or BYTE = VIL)" in ■DEVICE BUS OPERATIONS.)
If BYTE = VIL (for byte mode), the device code is 27h (for top boot block) or 45h (for bottom boot block). If BYTE
= VIH (for word mode), the device code is 2227h (for top boot block) or 2245h (for bottom boot block).
In order to determine which sectors are write protected, A1 must be at VIH while running through the sector
addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ0 (DQ0 =1).
Write
Device erasure and programming are accomplished via the command register. The command register is written
by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of CE or
WE, whichever occurs later, while data is latched on the rising edge of CE or WE pulse, whichever occurs first.
Standard microprocessor write timings are used. See "(3) AC Waveforms for Alternate WE Controlled Program
Operations", "(4) AC Waveforms for Alternate CE Controlled Program Operations", and "(5) AC Waveforms for
Chip/Sector Erase Operations" in ■TIMING DIAGRAM.
Refer to ■AC CHARACTERISTICS and ■TIMING DIAGRAM for specific timing parameters.
Sector Protection
The MBM29PL160TD/BD features hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 10). The sector protection feature is enabled using programming
equipment at the user’s site. The device is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, CE =
VIL, A0 = A6 = VIL, A1 = VIH. The sector addresses pins (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to
the sector to be protected. "Sector Address Table (MBM29PL160TD)" and "Sector Address Table
(MBM29PL160BD)" in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector address for each of
the eleven (11) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE
pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the
WE pulse. See "(11) AC Waveforms for Sector Protection Timing Diagram" in ■TIMING DIAGRAM and "(5)
Sector Protection Algorithm" in ■FLOW CHART for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12)
15
MBM29PL160TD/BD-75/90
while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. Otherwise the
device will read 00h for an unprotected sector. In this mode, the lower order addresses, except for A0, A1, and
A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device
codes. A-1 requires to VIL in byte mode.
ItisalsopossibletodetermineifasectorisprotectedinthesystembywritinganAutoselectcommand. Performing
a read operation at the address location XX02h, where the higher order addresses pins (A19, A18, A17, A16, A15,
A14, A13, and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See
"MBM29PL160TD/BD Sector Protection Verify Autoselect Code Table" and "Expanded Autoselect Code Table"
in ■DEVICE BUS OPERATIONS for Autoselect codes.
Word/Byte Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29PL160TD/BD device. When
this pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ15
to DQ0. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ15/A-1 pin
becomes the lowest address bit and DQ14 to DQ8 bits are High-Z. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Refer to
"(8) Timing Diagram for Word Mode Configuration", "(9) Timing Diagram for Byte Mode Configuration", and "(10)
BYTE Timing Diagram for Write Operations" in ■TIMING DIAGRAM for the timing diagrams.
16
MBM29PL160TD/BD-75/90
■ COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in an improper sequence will reset the device to the
read mode. "MBM29PL160TD/BD Standard Command Definitions Table" in ■DEVICE BUS OPERATIONS
defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h)
commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands
are functionally equivalent, resetting the device to the read mode. Please note that commands are always written
at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read mode, the read/reset
operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The device remains enabled for reads until the command
register contents are altered.
Thedevicewillautomaticallypower-upintheRead/Resetstate. Inthiscase, acommandsequenceisnotrequired
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory contents occurs during the power transition. Refer to “Read Only Operations
Characteristics” in ■AC CHARACTRISTICS and ■TIMING DIAGRAM for specific timing parameters. (See "(1)
AC Waveforms for Read Operations" and “(2) AC Waveforms for Page Read Mode Operations” in ■TIMING
DIAGRAM.)
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufactures and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the last command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A
read cycle from address XX01h for ×16 (XX02h for ×8) retrieves the device code (MBM29PL160TD = 27h and
MBM29PL160BD = 45h for ×8 mode; MBM29PL160TD = 2227h and MBM29PL160BD = 2245h for ×16 mode).
(See "MBM29PL160TD/BD Sector Protection Verify Autoselect Code Table" and "Expanded Autoselect Code
Table" in ■DEVICE BUS OPERATIONS.)
All manufactures and device codes will exhibit odd parity with DQ7 defined as the parity bit.
The sector state (protection or unprotection) will be indicated by address XX02h for ×16 (XX04h for ×8).
Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce
a logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin
mode verification on the protected sector. (See "MBM29PL160TD/BD User Bus Operation Tables (BYTE = VIH
and BYTE = VIL)" in ■DEVICE BUS OPERATIONS.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command
sequence.
Word/Byte Programming
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the
rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens
first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system
is not required to provide further controls or timings. The device will automatically provide adequate internally
generated program pulses and verify the programmed cell margin. (See "(3) AC Waveforms for Alternate WE
17
MBM29PL160TD/BD-75/90
Controlled Program Operations" and "(4) AC Waveforms for Alternate CE Controlled Program Operations" in
■TIMING DIAGRAM.)
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the device return to the read mode and addresses are no longer latched. (See "Hardware
Sequence Flags Table".) Therefore, the device requires that a valid address be supplied by the system at this
time. Hence, Data Polling must be performed at the memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occures during the
programming operation, it is impossible to guarantee whether the data being written is correct or not.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
"(1) Embedded ProgramTM Algorithm" in ■FLOW CHART illustrates the Embedded ProgramTM Algorithm using
typical command strings and bus operations.
Chip Erase
Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide any controls
or timings during these operations.
The automatic erase begins on the rising edge of the last WE or OE pulse in the command sequence and
terminates when the data on DQ7 is “1” (See “Write Operation Status” section.) at which time the device returns
to read mode. (See "(5) AC Waveforms for Chip/Sector Erase Operations" in ■TIMING DIAGRAM.)
"(2) Embedded EraseTM Algorithm" in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
Sector Erase
Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up”
command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address
(any address location within the desired sector) is latched on the falling edge of WE, while the command (Data
= 30h) is latched on the rising edge of WE. After a time-out of 50 µs from the rising edge of the last sector erase
command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing six-bus cycle operations on "MBM29PL160TD/BD
Standard Command Definitions Table" in ■DEVICE BUS OPERATIONS. This sequence is followed with writes
of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between
writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is
recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts
can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of
the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs
within the 50 µs time-out window the timer is reset. Monitor DQ3 to determine if the sector erase timer window
is still open. (See section “DQ3, Sector Erase Timer”.) Any command other than Sector Erase or Erase Suspend
duringthistime-outperiodwillresetthedevicetothereadmode, ignoringthepreviouscommandstring. Resetting
the device once excution has begun will corrupt the data in the sector. In that case, restart the erase on those
sectors and allow them to complete. (Refer to “Write Operation Status” section for Sector Erase Timer operation.)
Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 10).
Sector erase does not require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram Function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
18
MBM29PL160TD/BD-75/90
controls or timings during these operations. (See "(5) AC Waveforms for Chip/Sector Erase Operations" in
■TIMING DIAGRAM.)
The automatic sector erase begins after the 50 µs time out from the rising edge of the WE or OE pulse for the
last sector erase command pulse and terminates when the data on DQ7 is “1” (See “Write Operation Status”
section) at which time the device returns to the read mode. Data polling must be performed at an address within
any of the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogramming) + Sector
Erase Time] × Number of Sector Erase.
"(2) Embedded EraseTM Algorithm" in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.
Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when
writing the Erase Suspend or Erase Resume commands.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the DQ7
bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading
DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend
command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on “DQ2”.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This Program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
beprogrammedtosectorsthatarenoterase-suspended. Successivelyreadingfromtheerase-suspendedsector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-
suspended Program operation is detected by the Toggle Bit (DQ6) which is the same as the regular Program
operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
19
MBM29PL160TD/BD-75/90
Extended Command
(1) Fast Mode
MBM29PL160TD/BDhasFastModefunction. Thismodedispenseswiththeinitialtwounlockcyclesrequired
in the standard program command sequence writing Fast Mode command into the command register. In this
mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program
command. In Fast Mode, do not write any command other than the fast program/fast mode reset command.
The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast
Mode Reset command into the command register. (Refer to "(7) Embedded Programming Algorithm for Fast
Mode" in ■FLOW CHART Extended algorithm.) The VCC active current is required even CE = VIH during Fast
Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to
"(7) Embedded Programming Algorithm for Fast Mode" in ■FLOW CHART.)
(3) Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29PL160TD/BD
devices in order to change data. The Temporary Sector Unprotection mode is activated by command register.
During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the mode is taken away using command register, all the previously protected sectors will
be protected again. (See "(5) Sector Protection Algorithm" in ■FLOW CHART.)
Write Operation Status
Hardware Sequence Flags Table
Status
DQ7
DQ7
0
DQ6
DQ5
0
DQ3
0
DQ2
1
Embedded Program Algorithm
Embedded/Erase Algorithm
Toggle
Toggle
0
1
Toggle
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
Data
0
0
Data
0
Toggle
Data
1 *2
In Progress
Erase
Erase Suspend Read
Suspend
Data
DQ7
Data
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Toggle *1
Embedded Program Algorithm
Embedded/Erase Algorithm
Erase Suspend Program
DQ7
0
Toggle
Toggle
Toggle
1
1
1
0
1
0
1
Exceeded
Time
Limits
N/A
N/A
DQ7
*1: Performing successive read operations from any address will cause DQ6 to toggle.
*2: Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”
at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
Notes: • DQ15 to DQ8 for ×16 are optional.
• DQ0 and DQ1 are reserve pins for future use.
• DQ4 is Fujitsu internal use only.
20
MBM29PL160TD/BD-75/90
DQ7
Data Polling
The MBM29PL160TD/BD device features Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in "(3) Data Polling Algorithm" (■FLOW CHART).
For chip erase and sector erase, Data Polling is valid after the rising edge of the sixth WE pulse in the six-write
pulse sequence. Data Polling must be performed at a sector address within any of the sectors being erased and
not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
closetobeingcompleted, theMBM29PL160TD/BDdatapins(DQ7)maychangeasynchronouslywhiletheoutput
enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of
time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the device has completed the Embedded Program Algorithm
operation and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7
to DQ0 will be read on successive read attempts.
TheDataPollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm,EmbeddedEraseAlgorithm
or sector erase time-out.
See "(6) AC Waveforms for Data Polling during Embedded Algorithm Operations" in ■TIMING DIAGRAM for
the Data Polling timing specifications and diagrams.
DQ6
Toggle Bit I
The MBM29PL160TD/BD also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data can be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six-
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about
100 µs and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
See "(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations" in ■TIMING DIAGRAM and
"(4) Toggle Bit Algorithm" in ■FLOW CHART for the Toggle Bit I timing specifications and diagrams.
21
MBM29PL160TD/BD-75/90
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the device under this
condition. The CE circuit will partially power down the device under these conditions. The OE and WE pins will
control the output disable functions as described in "MBM29PL160TD/BD User Bus Operation Tables (BYTE =
VIH and BYTE = VIL)" in ■DEVICE BUS OPERATIONS.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.
If this occurs, reset the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the
second status check, the command may not have been accepted.
See "Hardware Sequence Flags Table".
DQ2
Toggle Bit II
This Toggle Bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address
of the non-erase suspended sector will indicate a logic “1” at DQ2.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress.
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also "Toggle Bit Status Table" and "(12) DQ2 vs. DQ6" in ■TIMING
DIAGRAM.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
22
MBM29PL160TD/BD-75/90
Toggle Bit Status Table
Mode
DQ7
DQ7
0
DQ6
DQ2
1
Program
Erase
Toggle
Toggle
Toggle
Erase Suspend Read
1
1
Toggle
1 *2
(Erase Suspended Sector) *1
Erase-Suspend Program
DQ7
Toggle *1
*1: Performing successive read operations from any address will cause DQ6 to toggle.
*2: Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”
at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
Data Protection
The MBM29PL160TD/BD is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequence.
The device also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 2.3 V.
If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be
erased again prior to programming.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must
be a logical zero while OE is a logical one.
Power-up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to read mode on power-up.
Sector Protection
Device user is able to protect each sector individually to store and protect data. Protection circuit voids both
program and erase commands that are addressed to protected sectors.
Any commands to program or erase addressed to protected sector are ignored (see “Sector Protection” in
■FUNCTIONAL DESCRIPTION).
23
MBM29PL160TD/BD-75/90
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min
–55
–40
Max
+125
+85
Storage Temperature
Tstg
TA
°C
°C
Ambient Temperature with Power Applied
Voltage with respect to Ground All pins
except A9, OE *1, *2
VIN, VOUT
–0.5
+5.5
V
Power Supply Voltage *1
A9 and OE *3
VCC
VIN
–0.5
–0.5
+4.0
V
V
+13.0
*1: Voltage is defined on the basis of VSS = GND = 0 V.
*2: Minimum DC voltage on input or l/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot
VSS to
–2.0 V for periods of up to 20 ns. Maximum DC voltage on input and l/O pins is +6.0V. During voltage transitions,
input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns.
*3: Minimum DC input voltage on A9, OE pins is –0.5 V. During voltage transitions, A9, OE pins may undershoot VSS
to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE pins is +13.0 V which may overshoot
to +13.5 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Conditions
Unit
Min
–20
–40
2.7
Typ
Max
+70
+85
3.6
-75
-90
Ambient Temperature
TA
°C
Power Supply Voltages *
VCC
3.0
V
*: Voltage is defined on the basis of VSS = GND = 0 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
24
MBM29PL160TD/BD-75/90
■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
20 ns
20 ns
+0.6 V
–0.5 V
–2.0 V
20 ns
Maximum Undershoot Waveform
20 ns
+6.0 V
VCC +0.5 V
+2.0 V
20 ns
20 ns
Maximum Overshoot Waveform 1
20 ns
+13.5 V
+13.0 V
VCC +0.5 V
20 ns
20 ns
Note : This waveform is applied for A9, OE.
Maximum Overshoot Waveform 2
25
MBM29PL160TD/BD-75/90
■ DC CHARACTERISTICS
Value
Typ
—
Parameter
Symbol
Conditions
Unit
Min
–1.0
–1.0
Max
+1.0
+1.0
Input Leakage Current
Output Leakage Current
ILI
VIN = VSS to 5.5 V, VCC = VCC Max
VOUT = VSS to 5.5 V, VCC = VCC Max
µA
µA
ILO
—
A9, OE, RESET Inputs Leakage
Current
VCC = VCC Max,
A9, OE = 12.5 V
ILIT
—
—
35
µA
CE = VIL, OE = VIH, f = 5 MHz
CE = VIL, OE = VIH, f = 10 MHz
CE = VIL, OE = VIH
—
—
—
—
—
—
—
1
40
70
35
5
mA
mA
mA
µA
VCC Active Current *1
ICC1
VCC Active Current *2
VCC Current (Standby)
ICC2
ICC3
VCC = VCC Max, CE = VCC ±0.3 V
VCC Current
VCC = VCC Max, CE = VSS ±0.3 V,
VIN = VCC ±0.3 V or VSS ±0.3 V
ICC4
—
1
5
µA
(Automatic Sleep Mode) *3
30MHz
CE = VIL, OE = VIH
40MHz
—
—
—
—
—
—
12
15
mA
mA
V
VCC Active Current
(Page Read Mode)
ICC5
Input Low Level
VIL
—
—
–0.5
2.0
+0.8
5.5
Input High Level *5
VIH
V
Voltage for Autoselect, Sector
Protection (A9, OE) *4, *5
VID
—
11.5
12
12.5
V
Output Low Voltage Level
Output High Voltage Level
Low VCC Lock-Out Voltage
VOL
VOH1
VOH2
VLKO
IOL = 4.0 mA, VCC = VCC Min
IOH = –2.0 mA, VCC = VCC Min
IOH = –100 µA
—
2.4
—
—
0.45
—
V
V
V
V
VCC – 0.4
2.3
—
—
—
2.4
2.5
*1: The lCC current listed includes both the DC operating current and the frequency dependent component.
*2: lCC active while Embedded Erase or Embedded Program is in progress.
*3: Automatic sleep mode enables the low power mode when addresses remain stable for 150 ns.
*4: Applicable only for sector protection.
*5: Applicable only for VCC applying.
26
MBM29PL160TD/BD-75/90
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Value
Symbol
Condi-
tions
Parameter
-75
-90
Unit
JEDEC Standard
Min
Max
Min
Max
Read Cycle Time
tAVAV
tAVQV
—
tRC
tACC
tPRC
tPACC
—
75
90
ns
ns
ns
ns
CE = VIL,
OE = VIL
Address to Output Delay
Page Read Cycle Time
Page Address to Output Delay
75
90
—
25
35
CE = VIL,
OE = VIL
—
25
35
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
OE = VIL
75
25
20
20
90
35
30
30
ns
ns
ns
ns
—
—
—
Output Hold Time From Address, CE
or OE, Whichever Occurs First
tAXQX
—
tOH
—
—
4
5
ns
ns
tELFL
tELFH
CE to BYTE Switching Low or High
4
5
Note: Test Conditions: Output Load: 1 TTL gate and 30 pF (MBM29PL160TD/BD-75)
1 TTL gate and 100 pF (MBM29PL160TD/BD-90)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
3.3 V
Diode = 1N3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diode = 1N3064
or Equivalent
Notes: C
L
= 30 pF including jig capacitance (MBM29PL160TD/BD-75)
= 100 pF including jig capacitance (MBM29PL160TD/BD-90)
C
L
Test Conditions
27
MBM29PL160TD/BD-75/90
• Write (Erase/Program) Operations
Parameter
Value
Symbol
-75
-90
Unit
JEDEC Standard
Min Typ Max Min Typ Max
Write Cycle Time
tAVAV
tAVWL
tWLAX
tDVWH
tWHDX
—
tWC
tAS
75
0
90
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
tAH
45
35
0
45
45
0
tDS
Data Hold Time
tDH
tOES
Output Enable Setup Time
0
0
Read
0
0
Output Enable
Hold Time
—
tOEH
Toggle and Data Polling
10
0
10
0
Read Recover Time Before Write
tGHWL
tGHWL
tGHEL
Read Recover Time Before Write
(OE High to CE Low)
tGHEL
0
0
ns
CE Setup Time
tELWL
tWLEL
tWHEH
tEHWH
tWLWH
tELEH
tWHWL
tEHEL
tCS
tWS
tCH
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
s
WE Setup Time
CE Hold Time
0
0
WE Hold Time
tWH
tWP
tCP
0
0
Write Pulse Width
CE Pulse Width
Write Pulse Width High
CE Pulse Width High
35
35
20
20
35
35
30
30
tWPH
tCPH
Byte
8.6
12.6
4.8
8.6
12.6
4.8
Programming
Operation
tWHWH1
tWHWH1
Word
Sector Erase Operation *1
tWHWH2
—
tWHWH2
tVCS
VCC Setup Time
50
4
50
4
µs
µs
µs
µs
µs
ns
ns
ns
ns
Voltage Transition Time *2
—
tVLHT
tWPP
tOESP
tCSP
Write Pulse Width *2
—
100
4
100
4
OE Setup Time to WE Active *2
CE Setup Time to WE Active *2
Recover Time From RY/BY
BYTE Switching Low to Output High-Z
BYTE Switching High to Output Active
Delay Time from Embedded Output Enable
—
—
4
4
—
tRB
0
0
—
tFLQZ
tFHQV
tEOE
30
75
30
90
—
40
30
—
*1: This does not include the preprogramming time.
*2: This timing is for Sector Protection operation.
28
MBM29PL160TD/BD-75/90
■ TIMING DIAGRAM
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
Will Be
Change
from H to L
from H to L
May
Change
from L to H
Will Be
Change
from L to H
“H” or “L”:
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center Line is
High-
Impedance
“Off” State
(1) AC Waveforms for Read Operations
tRC
Address
Address Stable
tACC
CE
OE
tOE
tDF
tOEH
WE
tOH
tCE
High-Z
Outputs
Output Valid
29
MBM29PL160TD/BD-75/90
(2) AC Waveforms for Page Read Mode Operations
A3 to A19
Address Valid
A0 to A2
(A-1)
Aa
Ab
Ac
tRC
tPRC
tACC
tCE
CE
OE
WE
tOEH
tOE
tDF
tPACC
tPACC
tOH
tOH
tOH
High-Z
Outputs
Da
Db
Dc
30
MBM29PL160TD/BD-75/90
(3) AC Waveforms for Alternate WE Controlled Program Operations
3rd Bus Cycle
Data Polling
555h
PA
PA
Address
tWC
tRC
tAS
tAH
CE
tCH
tCS
tCE
OE
tOE
tWP
tWPH
tGHWL
tWHWH1
WE
tOH
tDS
tDH
PD
DOUT
DOUT
A0h
DQ7
Data
Notes: • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
31
MBM29PL160TD/BD-75/90
(4) AC Waveforms for Alternate CE Controlled Program Operations
3rd Bus Cycle
Data Polling
PA
PA
555h
Address
WE
tWC
tAH
tAS
tWS
tWH
OE
CE
tCP
tCPH
tWHWH1
tGHEL
tDS
tDH
PD
DOUT
DQ7
A0h
Data
Notes: • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
32
MBM29PL160TD/BD-75/90
(5) AC Waveforms for Chip/Sector Erase Operations
2AAh
555h
555h
SA*
2AAh
Address
555h
tWC
tAS
tAH
CE
tCS
tCH
OE
tWP
tWPH
tGHWL
WE
tDS
tDH
10h for Chip Erase
10h/
30h
AAh
AAh
55h
80h
55h
Data
tVCS
VCC
*: SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.
Note : These waveforms are for the ×16 mode. The addresses differ from ×8 mode.
33
MBM29PL160TD/BD-75/90
(6) AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tCH
tDF
tOE
OE
tOEH
WE
tCE
*
High-Z
High-Z
DQ7 =
Data
Data
DQ7
DQ7
Valid Data
tWHWH1 or 2
DQ6 to DQ0
Valid Data
DQ6 to DQ0 = Output Flag
DQ6 to DQ0
tEOE
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
CE
tOEH
WE
tOEH
tOES
OE
*
tDH
DQ6 =
Stop Toggling
DQ0 to DQ7
Data Valid
DQ6 = Toggle
DQ6 = Toggle
Data
DQ6
tOE
*: DQ6 = Stops toggling. (The device has completed the Embedded operation.)
34
MBM29PL160TD/BD-75/90
(8) Timing Diagram for Word Mode Configuration
CE
BYTE
DQ0 to DQ14
DQ0 to DQ7
DQ0 to DQ14
tELFH
tFHQV
DQ15
DQ15/A-1
A-1
(9) Timing Diagram for Byte Mode Configuration
CE
BYTE
tELFL
DQ0 to DQ14
DQ15/A-1
DQ0 to DQ14
DQ0 to DQ7
DQ15
tFLQZ
A-1
(10) BYTE Timing Diagram for Write Operations
Falling edge of the last WE signal
CE or WE
BYTE
Input
Valid
tSET
(tAS)
tHOLD
(tAH)
35
MBM29PL160TD/BD-75/90
(11) AC Waveforms for Sector Protection Timing Diagram
A19, A18, A17
A16, A15, A14
A13, A12
SAX
SAY
A0
A1
A6
VID
3 V
A9
tVLHT
VID
3 V
OE
tOESP
tWPP
tVLHT
tVLHT
tVLHT
WE
CE
tCSP
01h
Data
tVCS
tOE
VCC
SAX = Sector Address for initial sector
SAY = Sector Address for next sector
Note: A-1 is VIL on byte mode.
36
MBM29PL160TD/BD-75/90
(12) DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
WE
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
*
Toggle
DQ2 and DQ6
with OE or CE
*: DQ2 is read from the erase-suspended sector.
37
MBM29PL160TD/BD-75/90
■ FLOW CHART
(1) Embedded ProgramTM Algorithm
Start
Write Program Command
Sequence
(See Below)
Data Polling Device
No
Increment Address
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
Note : The sequence is applied for ×16 mode.
The addresses differ from ×8 mode.
38
MBM29PL160TD/BD-75/90
(2) Embedded EraseTM Algorithm
Start
Write Erase Command
Sequece
(See Below)
Data Polling or Toggle Bit
from Device
Erasure Completed
Individual Sector/Multiple Sector
Chip Erase Command Sequence
Erase Command Sequence
(Address/Command):
(Address/Command):
555h/AAh
555h/AAh
2AAh/55h
555h/80h
555h/AAh
2AAh/55h
555h/80h
555h/AAh
2AAh/55h
555h/10h
2AAh/55h
Sector Address/30h
Sector Address/30h
Additional sector
erase commands
are optional.
Sector Address/30h
Note : The sequence is applied for ×16 mode.
The addresses differ from ×8 mode.
39
MBM29PL160TD/BD-75/90
(3) Data Polling Algorithm
VA =Address for programming
=Any of the sector addresses
within the sector being erased
during sector erase or multiple
erases operation.
Start
Read Byte
(DQ7 to DQ0)
Addr. = VA
=Any of the sector addresses
within the sector not being
protected during sector erase or
multiple sector erases
Yes
DQ7 = Data?
operation.
No
No
DQ5 = 1?
Yes
Read Byte
(DQ7 to DQ0)
Addr. = VA
Yes
DQ7 = Data?
*
No
Fail
Pass
* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
40
MBM29PL160TD/BD-75/90
(4) Toggle Bit Algorithm
Start
*1
*1
Read
(DQ7 ~ DQ0)
Addr. = "H" or "L"
Read
(DQ7 ~ DQ0)
Addr. = "H" or "L"
No
DQ6 =
Toggle?
Yes
No
DQ5 = 1?
Yes
*1, *2
*1, *2
Read
(DQ7 ~ DQ0)
Addr. = "H" or "L"
Read
(DQ7 ~ DQ0)
Addr. = "H" or "L"
No
DQ6 =
Toggle?
Yes
Fail
Pass
*1 : Read toggle bit twice to determine whether it is toggling.
*2 : DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5
changing to “1”.
41
MBM29PL160TD/BD-75/90
(5) Sector Protection Algorithm
Start
Setup Sector Addr.
(A19, A18, A17, A16,
A15, A14, A13, A12)
PLSCNT = 1
OE = VID, A9 = VID
A6 = CE = VIL
A0 = VIL, A1 = VIH
Activate WE Pulse
Increment PLSCNT
Time out 100 µs
WE = VIH, CE = OE = VIL
(A9 should remain VID)
Read from Sector
( A1 = VIH, A0 = VIL,
Addr. = SA, A6 = VIL)*
No
No
PLSCNT = 25?
Yes
Data = 01h?
Yes
Yes
Remove VID from A9
Write Reset Command
Protect Another Sector?
No
Remove VID from A9
Device Failed
Write Reset Command
Sector Protection
Completed
* : A-1 is VIL on byte mode.
42
MBM29PL160TD/BD-75/90
(6) Temporary Sector Unprotection Algorithm
Start
Temporary Unprotect Enable
Command Write *1
Perform Erase or
Program Operations
Temporary Unprotect Disable
Command Write
Temporary Sector
Unprotection Completed
*2
*1: All protected sectors are unprotected.
*2: All previously protected sectors are protected once again.
43
MBM29PL160TD/BD-75/90
(7) Embedded Programming Algorithm for Fast Mode
555h/AAh
2AAh/55h
555h/20h
Set Fast Mode
XXXh/A0h
Program Address/Program Data
Data Polling Device
In Fast Program
No
Last Address
?
Increment Address
Yes
Programming Completed
XXXh/90h
XXXh/F0h
Reset Fast Mode
Note: The sequence is applied for ×16 mode.
The addresses differ from ×8 mode.
44
MBM29PL160TD/BD-75/90
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Typ
Parameter
Unit
s
Comments
Min
Max
Excludes programming time
prior to erasure
Sector Erase Time
—
4.8
60
Word Programming Time
Byte Programming Time
—
—
12.6
8.6
360
300
Excludes system-level
overhead
µs
Excludes system-level
overhead
Chip Programming Time
Erase/Program Cycle
—
18
—
140
—
s
100,000
cycle
■ PIN CAPACITANCE
Value
Unit
Parameter
Symbol
Test Setup
Typ
Max
Input Capacitance
CIN
VIN = 0
VOUT = 0
VIN = 0
6.0
8.5
8.0
7.5
pF
pF
pF
Output Capacitance
Control Pin Capacitance
COUT
CIN2
12.0
11.5
Notes: •Test conditions TA = +25°C, f = 1.0 MHz
•DQ15/A-1 pin capacitance is stipulated by output capacitance.
45
MBM29PL160TD/BD-75/90
■ ORDERING INFORMATION
Part No.
Package
Access Time (ns)
Sector Architecture
Top Sector
MBM29PL160TD-75PF
MBM29PL160TD-90PF
44-pin plastic SOP
(FPT-44P-M16)
75
90
48-pin plastic TSOP (1)
(FPT-48P-M19)
MBM29PL160TD-75PFTN
MBM29PL160TD-90PFTN
75
90
(Normal Bend)
48-pin plastic TSOP (1)
(FPT-48P-M20)
MBM29PL160TD-75PFTR
MBM29PL160TD-90PFTR
75
90
(Reverse Bend)
MBM29PL160BD-75PF
MBM29PL160BD-90PF
44-pin plastic SOP
(FPT-44P-M16)
75
90
48-pin plastic TSOP (1)
(FPT-48P-M19)
MBM29PL160BD-75PFTN
MBM29PL160BD-90PFTN
75
90
Bottom Sector
(Normal Bend)
48-pin plastic TSOP (1)
(FPT-48P-M20)
MBM29PL160BD-75PFTR
MBM29PL160BD-90PFTR
75
90
(Reverse Bend)
MBM29PL160
T
D
-75 PFTN
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP(1)) Normal Bend
PFTR = 48-Pin Thin Small Outline Package
(TSOP(1)) Reverse Bend
PF
= 44-Pin Small Outline Package (SOP)
SPEED OPTION
See Product Selector Guide
DEVICE REVISION
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29PL160
16 Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Page Mode Flash Memory
3.0 V-only Read, Write, and Erase
46
MBM29PL160TD/BD-75/90
■ PACKAGE DIMENSIONS
Note 1) * : Values do not include resin protrusion.
48-pin plastic TSOP (1)
(FPT-48P-M19)
Resin protrusion and gate protrusion are +0.15(.006)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
LEAD No.
1
48
INDEX
Details of "A" part
0.25(.010)
0~8˚
0.60±0.15
(.024±.006)
24
25
*
20.00±0.20
(.787±.008)
12.00±0.20
(.472±.008)
*18.40±0.20
(.724±.008)
1.10 –+00..0150
.043 –+..000024
(Mounting
height)
0.10±0.05
(.004±.002)
(Stand off height)
0.50(.020)
"A"
0.10(.004)
0.17 –+00..0083
0.22±0.05
(.009±.002)
M
0.10(.004)
.007 –+..000031
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003 FUJITSU LIMITED F48029S-c-6-7
(Continued)
47
MBM29PL160TD/BD-75/90
Note 1) * : Values do not include resin protrusion.
48-pin plastic TSOP (1)
(FPT-48P-M20)
Resin protrusion and gate protrusion are +0.15(.006)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
LEAD No.
1
48
Details of "A" part
INDEX
0.60±0.15
(.024±.006)
0~8˚
0.25(.010)
24
25
0.17 –+00..0083
.007 –+..000031
0.22±0.05
(.009±.002)
M
0.10(.004)
0.10±0.05
(.004±.002)
0.50(.020)
0.10(.004)
(Stand off height)
1.10 +–00..0150
"A"
* 18.40±0.20
(.724±.008)
.043 +–..000024
(Mounting height)
20.00±0.20
(.787±.008)
* 12.00±0.20(.472±.008)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003 FUJITSU LIMITED F48030S-c-6-7
(Continued)
48
MBM29PL160TD/BD-75/90
(Continued)
44-pin plastic SOP
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
(FPT-44P-M16)
*1 28.45 +–00..2205 1.120 –+..000180
0.17 –+00..0043
.007 +–..000021
44
23
16.00±0.20
(.630±.008)
Details of "A" part
*213.00±0.10
(.512±.004)
2.35±0.15
(Mounting height)
INDEX
(.093±.006)
0.25(.010)
"A"
1
22
0~8˚
0.42 –+00..0078
1.27(.050)
M
0.13(.005)
.017 +–..00002381
0.80±0.20
(.031±.008)
0.20 –+00..1150
.008 +–..000064
0.88±0.15
(Stand off)
(.035±.006)
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002 FUJITSU LIMITED F44023S-c-6-6
49
MBM29PL160TD/BD-75/90
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0306
FUJITSU LIMITED Printed in Japan
相关型号：
©2020 ICPDF网 联系我们和版权申明