S25FL004A0LMAI001 [SPANSION]
Flash, 4MX1, PDSO8, 0.208 INCH, PLASTIC, SOP-8;
| 型号： | S25FL004A0LMAI001 |
| 厂家： | 
SPANSION |
| 描述： | Flash, 4MX1, PDSO8, 0.208 INCH, PLASTIC, SOP-8 光电二极管 |
| 文件： | 总34页 (文件大小：1411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S25FL004A
Data Sheet (Retired Product)
S25FL004A Cover Sheet
This product has been retired and is not recommended for new designs. For new designs, S25FL040A supersedes
S25FL004A. Please refer to the S25FL040A for specifications and ordering information. Availability of this document is
retained for reference and historical purposes only.
Publication Number S25FL004A_00
Revision B
Amendment 3
Issue Date July 9, 2007
D a t a S h e e t ( R e t i r e d P r o d u c t )
This page left intentionally blank.
2
S25FL004A
S25FL004A_00_B3 July 9, 2007
S25FL004A
4 Megabit CMOS 3.0 Volt Flash Memory
with 50MHz SPI (Serial Peripheral Interface) Bus
Data Sheet
This product has been retired and is not recommended for designs. For new and current designs, S25FL040A supersedes
S25FL004A and is the factory-recommended migration path for this device. Please refer to the S25FL040A data sheet for
specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
Distinctive Characteristics
Package Option
Architectural Advantages
Single power supply operation
– Industry Standard Pinouts
– 8-pin SO package (208 mils)
– 8-Contact WSON Package (5 x 6 mm)
– Full voltage range: 2.7 to 3.6 V read and program operations
Memory Architecture
– Eight sectors with 512 Kb each
Performance Characteristics
Program
Speed
– Page Program (up to 256 bytes) in 1.5 ms (typical)
– Program operations are on a page by page basis
– 50 MHz clock rate (maximum)
Power Saving Standby Mode
Erase
– Standby Mode 20 µA (max)
– 0.5 s typical sector erase time
– Deep Power Down Mode 1.5 µA (typical)
– 3 s typical bulk erase time
Cycling Endurance
Memory Protection Features
– 100,000 cycles per sector typical
Memory Protection
Data Retention
– W# pin works in conjunction with Status Register Bits to protect
specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in status
register configure parts of memory as read-only
– 20 years typical
Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward
compatibility
Software Features
Process Technology
– SPI Bus Compatible Serial Interface
– Manufactured on 0.20 µm MirrorBitTM process technology
Publication Number S25FL004A_00
Revision B
Amendment 3
Issue Date July 9, 2007
D a t a S h e e t
General Description
The S25FL004A is a 3.0 Volt (2.7 V to 3.6 V), single-power-supply Flash memory device. The device consists
of 8 sectors, each with 512 Kb memory.
The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are
designed to be programmed in-system with the standard system 3.0 volt VCC supply.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device
supports Sector Erase and Bulk Erase commands.
Each device requires only a 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally
generated and regulated voltages are provided for the program operations. This device does not require a
VPP supply.
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S25FL004A_00_B3 July 9, 2007
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Table of Contents
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.
2.
3.
4.
5.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.
7.
Spansion SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Byte or Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sector Erase / Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Monitoring Write Operations Using the Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Hold Mode (HOLD#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.
9.
Sector Address Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Identification (RDID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write Status Register (WRSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.11 Deep Power Down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.12 Release from Deep Power Down (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10. Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11. Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
13. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
14. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
16. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
17. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
17.1 SOC008—8-pin Plastic Small Outline 208-mil Body Width Package . . . . . . . . . . . . . . . . . . 31
17.2 UNE008—USON 8L (5 x 6 mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
18. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Figures
Figure 2.1
Figure 2.2
Figure 6.1
Figure 6.2
Figure 7.1
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
8L USON (5 x 6 mm) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Hold Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Data Bytes (READ) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Data Bytes at Higher Speed (FAST_READ) Command Sequence . . . . . . . . . . . . . . . 16
Read Identification (RDID) Command Sequence and Data-Out Sequence . . . . . . . . . . . . . 17
Write Enable (WREN) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Status Register (RDSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Status Register (WRSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Page Program (PP) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sector Erase (SE) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9.10 Bulk Erase (BE) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9.11 Deep Power Down (DP) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9.12 Release from Deep Power Down (RES) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9.13 Release from Deep Power Down and Read Electronic Signature (RES)
Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10.1 Power-Up Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15.1 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16.1 SPI Mode 0 (0,0) Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16.2 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16.3 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . . 30
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Tables
Table 5.1
Table 7.1
Table 8.1
Table 8.2
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 10.1
Table 12.1
Table 13.1
Table 14.1
Table 15.1
Table 16.1
S25FL004A Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
S25FL004A Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
S25FL004A Device Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
S25FL004A Sector Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
S25FL004A Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power-Up Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Test Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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D a t a S h e e t
1. Block Diagram
SRAM
PS
X
D
E
C
Array - L
Array - R
Logic
RD
DATA PATH
IO
2. Connection Diagrams
Figure 2.1 16-pin Plastic Small Outline Package (SO)
VCC
8
1
2
CS#
SO
7
HOLD#
SCK
SI
3
W#
6
5
4
GND
Figure 2.2 8L USON (5 x 6 mm) Package
CS#
SO
VCC
8
7
6
1
2
HOLD#
SCK
W#
3
4
GND
SI
5
8
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3. Input/Output Descriptions
Signal Name
I/O
Description
SO (Signal Data
Output)
Output Transfers data serially out of the device on the falling edge of SCK.
SI (Serial Data
Input)
Transfers data serially into the device. Device latches commands, addresses, and
program data on SI on the rising edge of SCK.
Input
Provides serial interface timing. Latches commands, addresses, and data on SI on rising
edge of SCK. Triggers output on SO after the falling edge of SCK.
SCK (Serial Clock)
Input
Places device in active power mode when driven low. Deselects device and places SO
at high impedance when high. After power-up, device requires a falling edge on CS#
before any command is written. Device is in standby mode when a program, erase, or
CS# (Chip Select)
Input
Write Status Register operation is not in progress.
Pauses any serial communication with the device without deselecting it. When driven
HOLD# (Hold)
Input
Input
low, SO is at high impedance, and all input at SI and SCK are ignored. Requires that
CS# also be driven low.
Protects the memory area specified by Status Register bits BP2:BP0. When driven low,
prevents any program or erase command from altering the data in the protected
memory area.
W# (Write Protect)
VCC
Input
Input
Supply Voltage
Ground
GND
4. Logic Symbol
V
CC
SO
SI
SCK
CS#
W#
HOLD#
GND
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5. Ordering Information
The ordering part number is formed by a valid combination of the following:
S25FL
004
A
0L
M
A
I
00
1
PACKING TYPE (Note 1)
0
1
3
=
=
=
Tray
Tube
13” Tape and Reel
MODEL NUMBER (Additional Ordering Options)
00 No additional ordering options
=
TEMPERATURE RANGE
Industrial (–40°C to + 85°C)
I
=
PACKAGE MATERIALS
A
F
=
=
Standard
Lead (Pb)-free
PACKAGE TYPE
M
N
=
=
8-pin Plastic Small Outline package (SOC008)
8-contact USON Package (UNE008)
SPEED
0L
=
50 MHz
DEVICE TECHNOLOGY
A
=
0.20 µm MirrorBit™ Process Technology
DENSITY
004
=
4 Mbit
DEVICE FAMILY
S25FL
SpansionTM Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory
Table 5.1 S25FL004A Valid Combinations Table
S25FL004A Valid Combinations
Package &
Package Marking
(Note 2)
Base Ordering
Part Number
Model
Number
Speed Option
Temperature
Packing Type
MAI, MFI
NAI, NFI
FL004A + (Temp) +
(Note 3)
0, 1, 3
(Note 1)
S25FL004A
0L
00
Notes
1. Contact your local sales office for availability.
2. Package marking omits leading “S25” and speed, package, and model number form.
3. A for standard package (non-Pb free); F for Pb-free package.
5.1
Valid Combinations
Table 5.1 lists the valid combinations configurations planned to be supported in volume for this device.
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6. Spansion SPI Modes
A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices:
CPOL = 0, CPHA = 0 (Mode 0)
CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for
both modes.
When the bus master is in standby mode, SCK is as shown in Figure 6.2 for each of the two modes:
SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)
SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3)
Figure 6.1 Bus Master and Memory Devices on the SPI Bus
SO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SI
SCK
SCK SO SI
SCK SO SI
SCK SO SI
Bus Master
SPI Memory
SPI Memory
SPI Memory
Device
Device
Device
CS3 CS2 CS1
CS#
W# HOLD#
CS#
W# HOLD#
CS#
W# HOLD#
Note
The Write Protect (W#) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate.
Figure 6.2 SPI Modes Supported
CS#
CPOL CPHA
Mode 0
SCK
0
0
1
1
Mode 3
SCK
SI
MSB
SO
MSB
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7. Device Operations
All Spansion SPI devices (S25FL-A) accept and output data in bytes (8 bits at a time).
7.1
Byte or Page Programming
Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program
(PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up
to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation.
Programming means that bits can either be left at 0, or programmed from 1 to 0. Changing bits from 0 to 1
requires an erase operation.
7.2
7.3
7.4
Sector Erase / Bulk Erase
The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array
to 1. While bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a
sector-wide (SE) or array-wide (BE) level.
Monitoring Write Operations Using the Status Register
The host system can determine when a Write Status Register, program, or erase operation is complete by
monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command
provides the state of the WIP bit.
Active Power and Standby Power Modes
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the
device is disabled, but may still be in the Active Power mode until all program, erase, and Write Status
Register operations have completed. The device then goes into the Standby Power mode, and power
consumption drops to ISB. The Deep Power Down (DP) command provides additional data protection against
inadvertent signals. After writing the DP command, the device ignores any further program or erase
commands, and reduces its power consumption to IDP
.
7.5
Status Register
The Status Register contains the status and control bits that can be read or set by specific commands
(Table 9.2, S25FL004A Status Register on page 18):
Write In Progress (WIP): Indicates whether the device is performing a Write Status Register, program or
erase operation.
Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch.
Block Protect (BP2, BP1, BP0): Non-volatile bits that define memory area to be software-protected
against program and erase commands.
Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit
is set to 1 and the W# input is driven low. In this mode, the non-volatile bits of the Status Register (SRWD,
BP2, BP1, BP0) become read-only bits.
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7.6
Data Protection Modes
Spansion SPI Flash memory devices provide the following data protection methods:
The Write Enable (WREN) command: Must be written prior to any command that modifies data. The
WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up
or after the device completes the following commands:
– Page Program (PP)
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Status Register (WRSR)
Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the
memory array that can be read but not programmed or erased. Table 7.1 shows the sizes and address
ranges of protected areas that are defined by Status Register bits BP2:BP0.
Hardware Protected Mode (HPM): The Write Protect (W#) input and the Status Register Write Disable
(SRWD) bit together provide write protection.
Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands
consist of a clock pulse count that is a multiple of eight before executing them.
Table 7.1 S25FL004A Protected Area Sizes
Status Register
Block Protect Bits
Protected
Memory Array
Portion of
Total Memory
Area
Protected
Address Range
Unprotected
Unprotected
Sectors
BP2
BP1
0
BP0
Protected Sectors
(0)
Address Range
00000–7FFFF
00000–6FFFF
00000–5FFFF
00000–3FFFF
none
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
None
SA7:SA0
SA6:SA0
SA5:SA0
SA3:SA0
None
0
0
70000–7FFFF
60000–7FFFF
40000–7FFFF
00000–7FFFF
00000–7FFFF
00000–7FFFF
00000–7FFFF
(1) SA7
1/8
1/4
1/2
All
All
All
All
1
(2) SA7:SA6
(4) SA7:SA4
(8) SA7:SA0
(8) SA7:SA0
(8) SA7:SA0
(8) SA7:SA0
1
0
0
none
None
1
none
None
1
none
None
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7.7
Hold Mode (HOLD#)
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write
Status Register, program or erase operation that is currently in progress.
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see Figure 7.1 on page 14, standard
use). If the falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling
edge of SCK (non-standard use).
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-
standard use) See Figure 7.1.
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the
Hold mode.
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,
followed by driving CS# low.
Figure 7.1 Hold Mode Operation
SCK
HOLD#
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
8. Sector Address Table
Table 8.1 shows the size of the memory array, sectors, and pages. The device uses pages to cache the
program data before the data is programmed into the memory array. Each page or byte can be individually
programmed (bits are changed from 1 to 0). The data is erased (bits are changed from 0 to 1) on a sector- or
device-wide basis using the SE or BE commands. Table 8.2 shows the starting and ending address for each
sector. The complete set of sectors comprises the memory array of the Flash device.
Table 8.1 S25FL004A Device Organization
Each Device has
Each Sector has
Each Page has
524,288
2,048
8
65,536
256
256
—
bytes
pages
sectors
—
—
Table 8.2 S25FL004A Sector Address Table
Sector
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Address Range
70000h
60000h
50000h
40000h
30000h
20000h
10000h
00000h
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
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9. Command Definitions
The host system must shift all commands, addresses, and data in and out of the device, beginning with the
most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte
command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on
the rising edge of SCK. Table 9.4 on page 24 lists the complete set of commands.
Every command sequence begins with a one-byte command code. The command may be followed by
address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the
command sequence has been written.
The Read Data Bytes (READ), Read Status Register (RDSR), Read Data Bytes at Higher Speed
(FAST_READ) and Read Identification (RDID) command sequences are followed by a data output sequence
on SO. CS# can be driven high after any bit of the sequence is output to terminate the operation.
The Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable
(WREN), or Write Disable (WRDI) commands require that CS# be driven high at a byte boundary, otherwise
the command is not executed. Since a byte is composed of eight bits, CS# must therefore be driven high
when the number of clock pulses after CS# is driven low is an exact multiple of eight.
The device ignores any attempt to access the memory array during a Write Status Register, program, or
erase operation, and continues the operation uninterrupted.
9.1
Read Data Bytes (READ)
The Read Data Bytes (READ) command reads data from the memory array at the frequency (fSCK) presented
at the SCK input, with a maximum speed of 33 MHz. The host system must first select the device by driving
CS# low. The READ command is then written to SI, followed by a 3-byte address (A23-A0). Each bit is
latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a
frequency fSCK, on the falling edge of SCK.
Figure 9.1 and Table 9.4 detail the READ command sequence. The first byte specified can be at any location.
The device automatically increments to the next higher address after each byte of data is output. The entire
memory array can therefore be read with a single READ command. When the highest address is reached, the
address counter reverts to 00000h, allowing the read sequence to continue indefinitely.
The READ command is terminated by driving CS# high at any time during data output. The device rejects any
READ command issued while it is executing a program, erase, or Write Status Register operation, and
continues the operation uninterrupted.
Figure 9.1 Read Data Bytes (READ) Command Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
Mode 3
SCK
Mode 0
Command
24-Bit Address
23 22 21
2
0
1
3
SI
MSB
Data Out 1
Data Out 2
Hi-Z
SO
6
4
2
7
1 0
7
5
3
MSB
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D a t a S h e e t
9.2
Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ command reads data from the memory array at the frequency (fSCK) presented at the SCK
input, with a maximum speed of 50 MHz. The host system must first select the device by driving CS# low. The
FAST_READ command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each
bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at
a frequency fSCK, on the falling edge of SCK.
The FAST_READ command sequence is shown in Figure 9.2 and Table 9.4. The first byte specified can be
at any location. The device automatically increments to the next higher address after each byte of data is
output. The entire memory array can therefore be read with a single FAST_READ command. When the
highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue
indefinitely.
The FAST_READ command is terminated by driving CS# high at any time during data output. The device
rejects any FAST_READ command issued while it is executing a program, erase, or Write Status Register
operation, and continues the operation uninterrupted.
Figure 9.2 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence
CS#
33
0
1
2
5
6
7
8
9
29 30
32
38 39 40 41
44 45 46
42 43
Mode 3
31
34 35 36 37
3
4
10
28
47
SCK
Mode 0
24-Bit Address
Dummy Byte
Command
23
3
2
22 21
1
0
6
5
4
2
0
1
7
3
SI
Hi-Z
3
7
6
4
2
1
0
5
7
SO
MSB
MSB
DATA OUT 1
DATA OUT 2
9.3
Read Identification (RDID)
The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the
two-byte device identification, to the host system.
JEDEC assigns the manufacturer identification byte; for Spansion devices it is 01h. The device manufacturer
assigns the device identification: the first byte provides the memory type; the second byte indicates the
memory capacity. See Table 9.1 or Table 9.4 for device ID data.
The host system must first select the device by driving CS# low. The RDID command is then written to SI,
and each bit is latched on the rising edge of SCK. The 24-bit device identification data is output from the
memory array on SO at a frequency fSCK, on the falling edge of SCK.
The RDID command sequence is shown in Figure 9.3 and Table 9.4.
Driving CS# high after the device identification data has been read at least once terminates the READ_ID
command. Driving CS# high at any time during data output also terminates the RDID operation.
The device rejects any RDID command issued while it is executing a program, erase, or Write Status Register
operation, and continues the operation uninterrupted.
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D a t a S h e e t
Figure 9.3 Read Identification (RDID) Command Sequence and Data-Out Sequence
CS#
SCK
1
28
30
29
31
2
3
4
5
6
18
17
Mode 3
Mode 0
0
7
14 15 16
8
9
10 11
13
12
Command
SI
Manufacturer Identification
Device Identification
Hi-Z
0
1
3
2
14
13
SO
15
MSB
Table 9.1 Read Identification (RDID) Data-Out Sequence
Device Identification
Manufacturer Identification
Memory Type
Memory Capacity
01h
02h
12h
9.4
Write Enable (WREN)
The Write Enable (WREN) command (see Figure 9.4) sets the Write Enable Latch (WEL) bit to a 1, which
enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set
prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command.
The host system must first drive CS# low, write the WREN command, and then drive CS# high.
Figure 9.4 Write Enable (WREN) Command Sequence
CS#
6
5
7
0
1
2
3
4
Mode 3
SCK
SI
Mode 0
Command
Hi-Z
SO
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17
D a t a S h e e t
9.5
Write Disable (WRDI)
The Write Disable (WRDI) command (see Figure 9.5) resets the Write Enable Latch (WEL) bit to a 0, which
disables the device from accepting a Write Status Register, program, or erase command. The host system
must first drive CS# low, write the WRDI command, and then drive CS# high.
Any of following conditions resets the WEL bit:
Power-up
Write Disable (WRDI) command completion
Write Status Register (WRSR) command completion
Page Program (PP) command completion
Sector Erase (SE) command completion
Bulk Erase (BE) command completion
Figure 9.5 Write Disable (WRDI) Command Sequence
CS#
0
3
4
7
6
1 2
5
Mode 3
SCK
SI
Mode 0
Command
Hi-Z
SO
9.6
Read Status Register (RDSR)
The Read Status Register (RDSR) command outputs the state of the Status Register bits. Table 9.2 shows
the status register bits and their functions.
The RDSR command may be written at any time, even while a program, erase, or Write Status Register
operation is in progress. The host system should check the Write In Progress (WIP) bit before sending a new
command to the device if an operation is already in progress. Figure 9.6 shows the RDSR command
sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven
high.
Table 9.2 S25FL004A Status Register
Bit
Status Register Bit
Bit Function
Description
1 = Protects when W# is low
7
SRWD
Status Register Write Disable
0 = No protection, even when W# is low
6
5
4
3
2
—
—
—
Not used
Not used
—
BP2
BP1
BP0
000–111 = Protects upper half of address range in 5 sizes. See
Table 7.1 on page 13.
Block Protect
1 = Device accepts Write Status Register, program, or erase
commands
1
0
WEL
WIP
Write Enable Latch
Write in Progress
0 = Ignores Write Status Register, program, or erase commands
1 = Device Busy. A Write Status Register, program, or erase
operation is in progress
0 = Ready. Device is in standby mode and can accept commands.
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D a t a S h e e t
Figure 9.6 Read Status Register (RDSR) Command Sequence
CS#
SCK
7
0
2
3
4
5
6
9
11
12 13 14
15
1
8
10
Mode 3
Mode 0
Command
SI
Hi-Z
SO
6
4
2
6
5
7
5
3
1
0
4
2
7
0
7
3
1
MSB
MSB
Status Register Out
Status Register Out
The following describes the status and control bits of the Status Register.
Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Status Register,
program, or erase operation. This bit is read-only, and is controlled internally by the device. If WIP is 1, one of
these operations is in progress; if WIP is 0, no such operation is in progress.
Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Status
Register, program, or erase command. When set to 1, the device accepts these commands; when set to 0,
the device rejects the commands. This bit is set to 1 by writing the WREN command, and set to 0 by the
WRDI command, and is also automatically reset to 0 after the completion of a Write Status Register, program,
or erase operation. WEL cannot be directly set by the WRSR command.
Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against
any changes to the stored data. The Write Status Register (WRSR) command controls these bits, which are
non-volatile. When one or more of these bits is set to 1, the corresponding memory area (see Table 7.1
on page 13) is protected against Page Program (PP) and Sector Erase (SE) commands. If the Hardware
Protected mode is enabled, BP2:BP0 cannot be changed. The Bulk Erase (BE) command is executed only if
all Block Protect (BP2, BP1, BP0) bits are 0.
Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write
Protect (W#) signal. When SRWD is set to 1 and W# is driven low, the device enters the Hardware Protected
mode. The non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the
device ignores any Write Status Register (WRSR) command.
9.7
Write Status Register (WRSR)
The Write Status Register (WRSR) command changes the bits in the Status Register. A Write Enable
(WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to
writing the WRSR command. Table 9.2, S25FL004A Status Register on page 18 shows the status register
bits and their functions.
The host system must drive CS# low, write the WRSR command, and the appropriate data byte on SI
(Figure 9.7).
The WRSR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must
be used for that purpose. Bit 0 is a status bit controlled internally by the Flash device. Bits 6 and 5 are always
read as 0 and have no user significance.
The WRSR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit
and W# together place the device in the Hardware Protected Mode (HPM). The device ignores all WRSR
commands once it enters the Hardware Protected Mode (HPM). Table 9.3 on page 20 shows that W# must
be driven low and the SRWD bit must be 1 for this to occur.
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Figure 9.7 Write Status Register (WRSR) Command Sequence
CS#
SCK
8
9
10
12 13 14 15
11
4
6
7
Mode 3
0
1
2
3
5
Mode 0
Command
Register In
Status
7
6
5
4
3
2
1
0
SI
MSB
Hi-Z
SO
Table 9.3 Protection Modes
Write Protection of the Status
Register
Protected Area
(See Note)
Unprotected Area
(See Note)
W# Signal
SRWD Bit
Mode
1
1
0
1
0
0
Status Register is writable (if the WREN
command has set the WEL bit). The
values in the SRWD, BP2, BP1 and
BP0 bits can be changed.
Software
Protected
(SPM)
Protected against
program and erase
commands
Ready to accept Page
Program and Sector
Erase commands
Status Register is Hardware write
protected. The values in the SRWD,
BP2, BP1 and BP0 bits cannot be
changed.
Hardware
Protected
(HPM)
Protected against
program and erase
commands
Ready to accept Page
Program and Sector
Erase commands
0
1
Note
As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 7.1 on page 13.
Table 9.3 shows that neither W# or SRWD bit by themselves can enable HPM. The device can enter HPM
either by setting the SRWD bit after driving W# low, or by driving W# low after setting the SRWD bit.
However, the device disables HPM only when W# is driven high.
Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in
HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no
protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM).
If W# is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the Status
Register) can be used.
9.8
Page Program (PP)
The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the PP command, three address bytes, and at least one
data byte on SI. CS# must be driven low for the entire duration of the PP sequence. The command sequence
is shown in Figure 9.8 on page 21 and Table 9.4 on page 24.
The device programs only the last 256 data bytes sent to the device. If the number of data bytes exceeds this
limit, the bytes sent before the last 256 bytes are discarded, and the device begins programming the last 256
bytes sent at the starting address of the specified page. This may result in data being programmed into
different addresses within the same page than expected. If fewer than 256 data bytes are sent to device, they
are correctly programmed at the requested addresses.
The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the
device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of tPP. The Status Register may
be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP
bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute a Page Program (PP) command that specifies a page that is protected by the
Block Protect bits (BP2:BP0) (see Table 7.1 on page 13).
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D a t a S h e e t
Figure 9.8 Page Program (PP) Command Sequence
CS#
SCK
5
8
34
37 38 39
35 36
0
2
4
6
7
10
28 32 33
29 30 31
1
3
9
Mode 3
Mode 0
24-Bit Address
22 21
Data Byte 1
Command
4
3
2
3
2
1
0
7
6
5
1
0
23
SI
MSB
MSB
CS#
SCK
53 54 55
52
49 50 51
46
44 45
40
47 48
41 42 43
Data Byte 2
Data Byte 3
Data Byte 256
0
7
6
0
1
7
MSB
7
6
5
4
3
2
1
0
6
5
4
3
2
1
5
4
3
2
SI
MSB
MSB
9.9
Sector Erase (SE)
The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any
address within the sector (see Table 7.1 on page 13) is a valid address for the SE command. CS# must be
driven low for the entire duration of the SE sequence. The command sequence is shown in Figure 9.9 and
Table 9.4 on page 24.
The host system must drive CS# high after the device has latched the 8th bit of the SE command, otherwise
the device does not execute the command. The SE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of tSE. The Status Register may
be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP
bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute an SE command that specifies a sector that is protected by the Block Protect
bits (BP2:BP0) (see Table 7.1 on page 13).
Figure 9.9 Sector Erase (SE) Command Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
Mode 3
SCK
Mode 0
Command
24-bit Address
1
SI
23 22 21
MSB
3
2
0
Hi-Z
SO
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D a t a S h e e t
9.10 Bulk Erase (BE)
The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command
is required prior to writing the PP command.
The host system must drive CS# low, and then write the BE command on SI. CS# must be driven low for the
entire duration of the BE sequence. The command sequence is shown in Figure 9.10 and Table 9.4
on page 24.
The host system must drive CS# high after the device has latched the 8th bit of the CE command, otherwise
the device does not execute the command. The BE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of tBE. The Status Register may
be read to check the value of the Write In Progress (WIP) bit while the BE operation is in progress. The WIP
bit is 1 during the BE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see Table 7.1
on page 13). Otherwise, the device ignores the command.
Figure 9.10 Bulk Erase (BE) Command Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Command
SI
Hi-Z
SO
9.11 Deep Power Down (DP)
The Deep Power Down (DP) command provides the lowest power consumption mode of the device. It is
intended for periods when the device is not in active use, and ignores all commands except for the Release
from Deep Power Down (RES) command. The DP mode therefore provides the maximum data protection
against unintended write operations. The standard standby mode, which the device goes into automatically
when CS# is high (and all operations in progress are complete), should generally be used for the lowest
power consumption when the quickest return to device activity is required.
The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the
entire duration of the DP sequence. The command sequence is shown in Figure 9.11 on page 23 and
Table 9.4 on page 24.
The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise
the device does not execute the command. After a delay of tDP, the device enters the DP mode and current
reduces from ISB to IDP (see Table 14.1 on page 26).
Once the device has entered the DP mode, all commands are ignored except the RES command (which
releases the device from the DP mode). The RES command also provides the Electronic Signature of the
device to be output on SO, if desired (see sections 9.12 and 9.12.1).
DP mode automatically terminates when power is removed, and the device always powers up in the standard
standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write
Status Register operation, and continues the operation uninterrupted.
22
S25FL004A
S25FL004A_00_B3 July 9, 2007
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Figure 9.11 Deep Power Down (DP) Command Sequence
CS#
SCK
t
DP
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Command
SI
Hi-Z
SO
Standby Mode
Deep Power-down Mode
9.12 Release from Deep Power Down (RES)
The device requires the Release from Deep Power Down (RES) command to exit the Deep Power Down
mode. When the device is in the Deep Power Down mode, all commands except RES are ignored.
The host system must drive CS# low and write the RES command to SI. CS# must be driven low for the entire
duration of the sequence. The command sequence is shown in Figure 9.12 and Table 9.4 on page 24.
The host system must drive CS# high tRES(max) after the 8-bit RES command byte. The device transitions
from DP mode to the standby mode after a delay of tRES (see Table 16.1 on page 28). In the standby mode,
the device can execute any read or write command.
Figure 9.12 Release from Deep Power Down (RES) Command Sequence
CS#
7
0
2
3
5
1
4
6
Mode 3
SCK
Mode 0
tRES
Command
SI
Hi-Z
SO
Deep Power-down Mode
Standby Mode
July 9, 2007 S25FL004A_00_B3
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D a t a S h e e t
9.12.1
Release from Deep Power Down and Read Electronic Signature (RES)
The device features an 8-bit Electronic Signature, which can be read using the RES command. See
Figure 9.13 on page 24 and Table 9.4 on page 24 for the command sequence and signature value. The
Electronic Signature is not to be confused with the identification data obtained using the RDID command. The
device offers the Electronic Signature so that it can be used with previous devices that offered it; however, the
Electronic Signature should not be used for new designs, which should read the RDID data instead.
After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each
bit is latched on SI during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is
shifted out on the falling edge of SCK. The RES operation is terminated by driving CS# high after the
Electronic Signature is read at least once. Additional clock cycles on SCK with CS# low cause the device to
output the Electronic Signature repeatedly.
When CS# is driven high, the device transitions from DP mode to the standby mode after a delay of tRES, as
previously described. The RES command always provides access to the Electronic Signature of the device
and can be applied even if DP mode has not been entered.
Any RES command issued while an erase, program, or WRSR operation is in progress not executed, and the
operation continues uninterrupted.
Figure 9.13 Release from Deep Power Down and Read Electronic Signature (RES)
Command Sequence
CS#
2
28 29 30
31 32 33 34
1
8
36 37
9
35
38
0
3
4
5
6
7
10
SCK
t
RES
3 Dummy Bytes
Command
SI
3
1
0
2
23 22
MSB
21
Hi-Z
7
6
5
4
3
2
1
SO
0
MSB
Electronic ID out
Standby Mode
Deep Power-down Mode
Table 9.4 Command Definitions
One-Byte
Address
Bytes
Dummy
Byte
Data
Bytes
Operation
Command
Description
Read Data Bytes
Command Code
03H (0000 0011)
0BH (0000 1011)
9FH (1001 1111)
06H (0000 0110)
04H (0000 0100)
D8H (1101 1000)
C7H (1100 0111)
02H (0000 0010)
05H (0000 0101)
01H (0000 0001)
B9H (1011 1001)
ABH (1010 1011)
READ
3
3
0
0
0
3
0
3
0
0
0
0
0
1 to ∞
Read
FAST_READ Read Data Bytes at Higher Speed
1
1 to ∞
RDID
WREN
WRDI
SE
Read Identification (Note 1)
Write Enable
0
1 to 3
0
0
Write Control
Write Disable
0
0
Sector Erase
0
0
Erase
Program
BE
Bulk (Chip) Erase
0
0
PP
Page Program
0
1 to 256
RDSR
WRSR
DP
Read from Status Register
Write to Status Register
Deep Power Down
Release from Deep Power Down
0
1 to ∞
Status Register
0
1
0
0
0
0
Power Saving
RES
Release from Deep Power Down and
Read Electronic Signature (Note 2)
ABH (1010 1011)
0
3
1 to ∞
Notes
1. The S25FL004A has a manufacturer ID of 01h, and a device ID consisting of the memory type (02h) and the memory capacity (12h).
24
S25FL004A
S25FL004A_00_B3 July 9, 2007
D a t a S h e e t
2. The S25FL004A has an Electronic Signature ID of 12h.
10. Power-up and Power-down
During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied
on VCC, and must not be driven low to select the device until VCC reaches the allowable values as follows
(see Figure 10.1 on page 25 and Table 10.1 on page 25):
At power-up, VCC (min) plus a period of tPU
At power-down, VSS
A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements.
No Write Status Register, program, or erase command should be sent to the device until VCC rises to the VCC
min, plus a delay of tPU. At power-up, the device is in standby mode (not Deep Power Down mode) and the
WEL bit is reset (0).
Each device in the host system should have the VCC rail decoupled by a suitable capacitor close to the
package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the VCC feed.
When VCC drops from the operating voltage to below the minimum VCC threshold at power-down, all
operations are disabled and the device does not respond to any commands. Note that data corruption may
result if a power-down occurs while a Write Register, program, or erase operation is in progress.
Figure 10.1 Power-Up Timing Diagram
Vcc
(max)
cc
V
(min)
cc
V
tPU
Full Device Access
Time
Table 10.1 Power-Up Timing Characteristics
Symbol
Parameter
Min
2.7
10
Max
Unit
V
V
V
(minimum)
CC(min)
CC
t
V
(min) to device operation
CC
ms
PU
11. Initial Delivery State
The device is delivered with all bits set to 1 (each byte contains FFh) upon initial factory shipment. The Status
Register contains 00h (all Status Register bits are 0).
July 9, 2007 S25FL004A_00_B3
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D a t a S h e e t
12. Absolute Maximum Ratings
Do not stress the device beyond the ratings listed in this section, or serious, permanent damage to the device
may result. These are stress ratings only and device operation at these or any other conditions beyond those
indicated in this section and in the Operating Ranges on page 26 section of this document is not implied.
Device operation for extended periods at the limits listed in this section may affect device reliability.
Table 12.1 Absolute Maximum Ratings
Description
Ambient Storage Temperature
Voltage with Respect to Ground: All Inputs and I/Os
Rating
–65°C to +150°C
–0.3 V to 4.5 V
13. Operating Ranges
Table 13.1 Operating Ranges
Description
Rating
Ambient Operating Temperature (T )
A
Commerical
Industrial
0°C to +70°C
–40°C to +85°C
2.7 V to 3.6 V
Positive Power Supply
Voltage Range
Note
Operating ranges define those limits between which functionality of the device is guaranteed.
14. DC Characteristics
This section summarizes the DC Characteristics of the device. Designers should check that the operating
conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 15.1
on page 27, when relying on the quoted parameters.
Table 14.1 DC Characteristics (CMOS Compatible)
Parameter
Description
Test Conditions (See Note)
Min
Typ.
Max
Unit
VCC
Supply Voltage
2.7
3
3.6
V
SCK = 0.1 VCC/0.9VCC
33 MHz
9
12
13
mA
mA
ICC1
Active Read Current
VCC = 3.0V,
50 MHz
SCK = 0.1 VCC/0.9VCC
ICC2
ICC3
ICC4
ICC5
Active Page Program Current CS# = VCC
Active WRSR Current CS# = VCC
Active Sector Erase Current CS# = VCC
16.5
27
24
24
24
mA
mA
mA
mA
Active Bulk Erase Current
CS# = VCC
CC = 3.0 V
V
ISB
IDP
Standby Current
20
50
5
µA
µA
CS# = VCC
VCC = 3.0 V
CS# = VCC
Deep Power Down Current
1.5
ILI
ILO
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND to VCC
VIN = GND to VCC
1
1
µA
µA
V
VIL
–0.3
0.3 VCC
VCC + 0.5
0.4
VIH
VOL
VOH
Input High Voltage
0.7 VCC
V
Output Low Voltage
Output High Voltage
IOL = 1.6 mA, VCC = VCC min
IOH = –0.1 mA
V
VCC – 0.2
V
Note
Typical values are at T = 25°C and 3.0 V.
A
26
S25FL004A
S25FL004A_00_B3 July 9, 2007
D a t a S h e e t
15. Test Conditions
Figure 15.1 AC Measurements I/O Waveform
0.8 VCC
Input Levels
0.2 VCC
0.7 VCC
0.5 VCC
0.3 VCC
Input and Output
Table 15.1 Test Specifications
Symbol
Parameter
Min
Max
Unit
pF
ns
V
C
Load Capacitance
30
L
Input Rise and Fall Times
Input Pulse Voltage
5
0.2 V to 0.8 V
CC
CC
CC
Input Timing Reference Voltage
Output Timing Reference Voltage
0.3 V to 0.7 V
V
CC
0.5 V
V
CC
July 9, 2007 S25FL004A_00_B3
S25FL004A
27
D a t a S h e e t
16. AC Characteristics
Table 16.1 AC Characteristics
Typ
(Notes)
Max
(Notes)
Symbol
(Notes)
Parameter
Min
Unit
F
SCK Clock Frequency READ command
D.C.
33
50
MHz
SCK
SCK
CRT
SCK Clock Frequency for:
FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR
F
D.C.
MHz
t
Clock Rise Time (Slew Rate)
Clock Fall Time (Slew Rate)
SCK High Time
0.1
0.1
9
V/ns
V/ns
ns
t
CFT
t
WH
t
SCK Low Time
9
ns
WL
t
CS# High Time
100
5
ns
CS
t
(3)
(3)
(3)
(3)
CS# Setup Time
ns
CSS
t
CS# HOLD Time
5
ns
CSH
t
t
HOLD# Setup Time (relative to SCK)
HOLD# Hold Time (relative to SCK)
HOLD# Setup Time (relative to SCK)
HOLD# Hold Time (relative to SCK)
Output Valid
5
ns
HD
5
ns
CD
t
t
5
ns
HC
CH
5
ns
t
10
ns
V
t
Output Hold Time
0
5
5
ns
HO
t
Data in Hold Time
ns
HD:DAT
t
Data in Setup Time
ns
SU:DAT
t
Input Rise Time
5
ns
R
t
Input Fall Time
5
ns
F
t
(3)
HOLD# to Output Low Z
HOLD# to Output High Z
Output Disable Time
10
10
10
ns
LZ
t
(3)
(3)
ns
HZ
t
ns
DIS
t
(3)
(3)
Write Protect Setup Time
Write Protect Hold Time
Write Status Register Time
CS# High to Deep Power Down Mode
Release DP Mode
15
15
ns
WPS
WPH
t
ns
t
67
150
3
ms
μs
μs
ms
sec
sec
W
t
DP
t
30
RES
t
t
t
Page Programming Time
Sector Erase Time
1.5 (1)
0.5 (1)
3 (1)
3 (2)
3 (1)
24 (1)
PP
SE
BE
Bulk Erase Time
Notes
1. Typical program and erase times assume the following conditions: 25°C, V = 3.0V; 10,000 cycles; checkerboard data pattern
CC
2. Under worst-case conditions of 90°C; V = 2.7V; 100,000 cycles
CC
3. Not 100% tested
28
S25FL004A
S25FL004A_00_B3 July 9, 2007
D a t a S h e e t
Figure 16.1 SPI Mode 0 (0,0) Input Timing
tCS
CS#
SCK
SI
tCSH
tCSS
tCSS
tCSH
tSU:DAT
tCRT
tHD:DAT
tCFT
MSB IN
LSB IN
Hi-Z
SO
Figure 16.2 SPI Mode 0 (0,0) Output Timing
CS#
tWH
SCK
tV
tWL
tDIS
tV
tHO
tHO
SO
LSB OUT
Figure 16.3 HOLD# Timing
CS#
tHC
tHD
tCH
SCK
SO
tCD
tHZ
tLZ
SI
HOLD#
July 9, 2007 S25FL004A_00_B3
S25FL004A
29
D a t a S h e e t
Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1
W#
tWPS
tWPH
CS#
SCK
SI
Hi-Z
SO
30
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S25FL004A_00_B3 July 9, 2007
D a t a S h e e t
17. Physical Dimensions
17.1 SOC008—8-pin Plastic Small Outline 208-mil Body Width Package
3
4
0.20
C
A-B
D
H
D
A
5
SEE
DETAIL B
WITH
PLATING
b1
9
c
c1
3
4
E
E1
(b)
BASE
E1/2
7
E/2
METAL
SECTION A-A
0.33
D
C
e
b
q2
0.07 R MIN.
0.25
M
C
A-B
B
5
H
0.10
C
GAUGE
PLANE
A
0.10
C
A2
A
SEATING
PLANE
SEATING PLANE
A
q1
C
L2
A1
C
L
q
L1
DETAIL B
NOTES:
1.
2.
3.
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
PACKAGE SOC 008 (inches)
JEDEC
SOC 008 (mm)
DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
SYMBOL
MIN
MAX
0.085
0.0098
0.075
0.019
0.018
MIN
MAX
2.159
0.249
1.91
A
A1
A2
b
0.069
0.002
0.067
0.014
0.013
1.753
0.051
1.70
.
0.356
0.330
0.191
0.152
0.483
0.457
0.241
0.203
4.
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
b1
c
0.0075 0.0095
0.006 0.008
0.208 BSC
c1
D
5.283 BSC
5.
6.
DATUMS A AND B TO BE DETERMINED AT DATUM H.
E
0.315 BSC
0.208 BSC
.050 BSC
8.001 BSC
5.283 BSC
1.27 BSC
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
E1
e
7.
8.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
L
0.020
0.030
0.508
0.762
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
L1
L2
N
.055 REF
1.40 REF
0.25 BSC
8
.010 BSC
8
θ
0˚
5˚
8˚
15˚
0˚
0˚
5˚
8˚
9.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
θ1
θ2
15˚
0˚
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
3432 \ 16-038.03 \ 10.28.04
July 9, 2007 S25FL004A_00_B3
S25FL004A
31
D a t a S h e e t
17.2 UNE008—USON 8L (5 x 6 mm) No-Lead Package
NOTES:
QUAD FLAT NO LEAD PACKAGES (UNE) - PLASTIC
1. DIMENSIONING AND TOLERANCING CONFORMS TO
DIMENSIONS
NOM
ASME Y14.5M-1994.
SYMBOL
MIN
MAX
NOTE
2. ALL DIMENSIONS ARE IN MILLIMETERS, 0 IS IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
e
N
1.27 BSC
8
3
5
4. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP.
IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER
END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE
MEASURED IN THAT RADIUS AREA.
ND
L
4
0.55
0.35
3.90
3.30
0.60
0.65
0.45
4.10
3.50
b
0.40
4
D2
E2
D
4.00
5. ND REFERS TOT HE NUMBER OF TERMINALS ON D SIDE.
6. MAXIMUM PACKAGE WARPAGE IS 0.05 mm.
3.40
5.00 BSC
6.00 BSC
0.50
7. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP WILL BE LASER MARKED.
E
A
0.45
0.00
0.55
0.05
9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED
HEAT SINK SLUG AS WELL AS THE TERMINALS.
A1
K
0.02
0.20 MAX.
---
θ
0
12
2
3448\ 16-038.28 \ 04.15.05
32
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D a t a S h e e t
18. Revision History
Section
Revision A (March 1, 2005)
Global
Description
Initial release.
Revision A1 (March 28, 2005)
Updated Table 7.Removed Commercial Temperature Range. Changed WSON package
nomenclature to USON package; updated USON package dimensions. Added tray option for
Packing Type.
Global
Revision A2 (August 10, 2005)
Changed document status to Preliminary. 8-Contact USON Package not Pb-free. Changed Power
Saving Standby Mode to 20 µA (typical); Deep Power Down Mode to 1.5 µA; Typical Sector Erase
Time to 0.5 s; Typical Bulk Erase Time to 3 s.
Global
Ordering Information
DC Characteristics
AC Characteristics
Revision A3 (May 19, 2006)
Global
Changes in information and notations in Ordering Information table.
Information changes in the DC Characteristics table.
Information changes in the AC Characteristics table.
Removed Preliminary document status.
Revision A4 (June 29, 2006)
DC Characteristics
Revision B0 (August 31, 2006)
Global
Added typical specification and changed maximum specification for ICC2
.
Rewrote entire document for better flow and clarity. No specifications were changed.
Added migration text to cover sheet and first page document.
Revision B1 (January 23, 2007)
Global
Revision B2 (July 2, 2007)
Global
Added a sentence to Byte or Page Programming.
Revision B3 (July 9, 2007)
Global
Modified migration text to cover sheet and first page document. This product is now retired.
July 9, 2007 S25FL004A_00_B3
S25FL004A
33
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2005–2007 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, HD-SIM™
and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes
only and may be trademarks of their respective owners.
34
S25FL004A
S25FL004A_00_B3 July 9, 2007
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