S25FL128POXMFI011 [SPANSION]
Flash, 16MX8, PDSO16;
| 型号： | S25FL128POXMFI011 |
| 厂家： | 
SPANSION |
| 描述： | Flash, 16MX8, PDSO16 光电二极管 |
| 文件： | 总49页 (文件大小：1872K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S25FL128P
128 Megabit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Bus
Data Sheet
S25FL128P Cover Sheet
This product is not recommended for new and current designs. For new and current designs,
S25FL128S supersedes S25FL128P. This is the factory-recommended migration path. Please refer to
the S25FL128S data sheet for specifications and ordering information.
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S25FL128P_00
Revision 10
Issue Date May 16, 2012
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S25FL128P
S25FL128P_00_10 May 16, 2012
S25FL128P
128 Megabit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Bus
Data Sheet
This product is not recommended for new and current designs. For new and current designs, S25FL128S
supersedes S25FL128P. This is the factory-recommended migration path. Please refer to the S25FL128S
data sheet for specifications and ordering information.
Distinctive Characteristics
Process Technology
Architectural Advantages
Single power supply operation
– Manufactured on 0.09 µm MirrorBit® process technology
Package Option
– Full voltage range: 2.7V to 3.6V read and program operations
– Industry Standard Pinouts
– 16-pin SO package (300 mils)
– 8-Contact WSON Package (6 x 8 mm)
Memory Architecture
– 128Mb uniform 256 KB sector product
– 128Mb uniform 64 KB sector product
Program
Performance Characteristics
Speed
– Page Program (up to 256 bytes) in 1.5 ms (typical)
– Faster program time in Accelerated Programming mode
(8.5 V–9.5 V on #WP/ACC) in 1.2 ms (typical)
– 104 MHz clock rate (maximum)
Power Saving Standby Mode
– Standby Mode 200 µA (max)
Erase
– 2 s typical 256 KB sector erase time
– 0.5 s typical 64 KB sector erase time
– 128 s typical bulk erase time
– Deep Power Down Mode 3 µA (typical)
Memory Protection Features
Memory Protection
– Sector erase (SE) command (D8h) for 256 KB sectors; (20h or D8h)
for 64KB sectors
– Bulk erase command (C7h) for 256 KB sectors; (60h or C7h) for
64KB sectors
– WP#/ACC pin works in conjunction with Status Register Bits to
protect specified memory areas
Cycling Endurance
– 100,000 cycles per sector typical
Data Retention
– 256 KB uniform sector product:
Status Register Block Protection bits (BP2, BP1, BP0) in status
register configure parts of memory as read-only.
– 64KB uniform sector product:
Status Register Block Protection bits (BP3, BP2, BP1, BP0) in
status register configure parts of memory as read-only
– 20 years typical
Device ID
– RDID (9Fh), READ_ID (90h) and RES (ABh) commands to read
manufacturer and device ID information
Software Features
– RES command one-byte electronic signature for backward
compatibility
– SPI Bus Compatible Serial Interface
Hardware Features
x8 Parallel Programming Mode (for 16-pin SO package only)
General Description
The S25FL128P is a 3.0 Volt (2.7V to 3.6V), single-power-supply Flash memory device. The device consists
of 64 sectors of 256 KB memory, or 256 sectors of 64 KB memory.
The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are
designed to be programmed in-system with the standard system 3.0 volt VCC supply.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device
supports Sector Erase and Bulk Erase commands.
Each device requires only a 3.0 volt power supply (2.7V to 3.6V) for both read and write functions. Internally
generated and regulated voltages are provided for the program operations. This device requires a high
voltage supply to WP#/ACC pin for the Accelerated Programming mode.
Publication Number S25FL128P_00
Revision 10
Issue Date May 16, 2012
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro-
duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com-
binations offered may occur.
D a t a S h e e t
Table of Contents
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.
2.
3.
4.
5.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.
7.
Spansion SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Byte or Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sector Erase / Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Monitoring Write Operations Using the Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hold Mode (HOLD#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.
9.
Sector Address Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Parallel Mode (for 16-pin SO package only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10. Accelerated Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11. Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.1 Read Data Bytes (READ: 03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.2 Read Data Bytes at Higher Speed (FAST_READ: 0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.3 Read Identification (RDID: 9Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11.4 Read Manufacturer and Device ID (READ_ID: 90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
11.5 Write Enable (WREN: 06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.6 Write Disable (WRDI: 04h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.7 Read Status Register (RDSR: 05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.8 Write Status Register (WRSR: 01h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11.9 Page Program (PP: 02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.10 Sector Erase (SE: 20h, D8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.11 Bulk Erase (BE: C7h, 60h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11.12 Deep Power Down (DP: B9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.13 Release from Deep Power Down (RES: ABh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11.14 Release from Deep Power Down and Read Electronic Signature (RES: ABh) . . . . . . . . . . . 36
11.15 Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12. Program Acceleration via WP#/ACC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
13. Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
14. Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
15. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
16. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
17. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
18. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
19. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
20. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
20.1 SO3 016 wide — 16-pin Plastic Small Outline Package (300-mil Body Width) . . . . . . . . . . . 46
20.2 WNF008 — WSON 8-contact (6 x 8 mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . 47
21. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4
S25FL128P
S25FL128P_00_10 May 16, 2012
D a t a S h e e t
Figures
Figure 2.1
Figure 2.2
Figure 6.1
Figure 6.2
Figure 7.1
16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
8-Pin WSON Package (6 x 8 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Hold Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11.1 Read Data Bytes (READ) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11.2 Parallel Read Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11.3 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence . . . . . . . . . . . . . . . 21
Figure 11.4 Read Identification Command Sequence and Data Out Sequence. . . . . . . . . . . . . . . . . . . . 22
Figure 11.5 Parallel Read_ID Command Sequence and Data Out Sequence . . . . . . . . . . . . . . . . . . . . . 23
Figure 11.6 Serial READ_ID Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11.7 Parallel Read_ID Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11.8 Write Enable (WREN) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11.9 Write Disable (WRDI) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11.10 Read Status Register (RDSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11.11 Parallel Read Status Register (RDSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 11.12 Write Status Register (WRSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11.13 Parallel Write Status Register (WRSR) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11.14 Page Program (PP) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11.15 Parallel Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11.16 Sector Erase (SE) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11.17 Bulk Erase (BE) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11.18 Deep Power Down (DP) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11.19 Release from Deep Power Down (RES) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11.20 Serial Release from Deep Power Down and
Read Electronic Signature (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 11.21 Parallel Release from Deep Power Down and
Read Electronic Signature (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 12.1 ACC Program Acceleration Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 13.1 Power-Up Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13.2 Power-down and Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 15.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 15.2 Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 18.1 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 19.1 SPI Mode 0 (0,0) Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 19.2 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 19.3 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 19.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . . 45
May 16, 2012 S25FL128P_00_10
S25FL128P
5
D a t a S h e e t
Tables
Table 5.1
Table 7.1
Table 7.2
Table 8.1
Table 8.2
Table 8.3
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Table 12.1
Table 13.1
Table 15.1
Table 16.1
Table 17.1
Table 18.1
Table 19.1
S25FL128P Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
S25FL128P Protected Area Sizes (Uniform 256 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . . .13
S25FL128P Protected Area Sizes (Uniform 64 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . . . .13
S25FL128P Device Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
S25FL128P Sector Address Table (Uniform 256 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . .15
S25FL128P Sector Address Table (Uniform 64 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . . .16
Manufacturer & Device Identification, RDID (9Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
READ_ID Command and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
S25FL128P Status Register (Uniform 256 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
S25FL128P Status Register (Uniform 64 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
ACC Program Acceleration Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Power-Up / Power-Down Voltage and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
6
S25FL128P
S25FL128P_00_10 May 16, 2012
D a t a S h e e t
1. Block Diagram
SRAM
PS
X
D
E
C
Array - L
Array - R
Logic
RD
DATA PATH
IO
May 16, 2012 S25FL128P_00_10
S25FL128P
7
D a t a S h e e t
2. Connection Diagrams
Figure 2.1 16-pin Plastic Small Outline Package (SO)
16
15
14
SCK
1
2
3
HOLD#
VCC
SI
PO6
NC
PO2
PO1
PO0
13
12
4
5
PO5
PO4
6
11
PO3
GND
CS#
7
8
10
9
SO/PO7
WP#/ACC
Figure 2.2 8-Pin WSON Package (6 x 8 mm)
CS#
SO
VCC
8
7
6
1
2
HOLD#
WSON
WP#/ACC
GND
3
4
SCK
SI
5
Note:
There is an exposed central pad on the underside of the WSON package. This should not be connected to any voltage or signal line on the
PCB. Connecting the central pad to GND (V ) is possible, provided PCB routing ensures 0mV difference between voltage at the WSON
SS
GND (V ) lead and the central exposed pad.
SS
8
S25FL128P
S25FL128P_00_10 May 16, 2012
D a t a S h e e t
3. Input/Output Descriptions
Signal Name
SO (Signal Data Output)
I/O
Description
Output
Transfers data serially out of the device on the falling edge of SCK.
Transfers parallel data into the device on the rising edge of SCK or out of
the device on the falling edge of SCK.
PO[7–0] (Parallel Data Input/Output)
SI (Serial Data Input)
Input/Output
Input
Transfers data serially into the device. Device latches commands,
addresses, and program data on SI on the rising edge of SCK.
Provides serial interface timing. Latches commands, addresses, and data
on SI on rising edge of SCK. Triggers output on SO after the falling edge
of SCK.
SCK (Serial Clock)
CS# (Chip Select)
HOLD# (Hold)
Input
Input
Places device in active power mode when driven low. Deselects device
and places SO at high impedance when high. After power-up, device
requires a falling edge on CS# before any command is written. Device is
in standby mode when a program, erase, or Write Status Register
operation is not in progress.
Pauses any serial communication with the device without deselecting it.
When driven low, SO is at high impedance, and all input at SI and SCK
are ignored. Requires that CS# also be driven low.
Input
Input
When driven low, prevents any program or erase command from altering
the data in the protected memory area specified by Status Register bits
WP#/ACC
(Write Protect/Accelerated Programming)
(BP bits). If the system asserts V on this pin, accelerated
HH
programming operation is provided.
Supply Voltage
V
Input
Input
CC
GND
Ground
4. Logic Symbol
V
CC
SO
SI
PO[7-0] (For 16-pin SO package)
SCK
CS#
WP#/ACC
HOLD#
GND
May 16, 2012 S25FL128P_00_10
S25FL128P
9
D a t a S h e e t
5. Ordering Information
This product is not recommended for new and current designs. For new and current designs, S25FL128S
supersedes S25FL128P. This is the factory-recommended migration path. Please refer to the S25FL128S
data sheet for specifications and ordering information.
The ordering part number is formed by a valid combination of the following:
S25FL
128
P
0X
M
F
I
00
1
PACKING TYPE
0
1
3
=
=
=
Tray
Tube
13” Tape and Reel
MODEL NUMBER (Additional Ordering Options)
00
01
=
Uniform 64 KB sector product
Uniform 256 KB sector product
=
TEMPERATURE RANGE
Industrial (–40°C to + 85°C)
I
=
PACKAGE MATERIALS
Lead (Pb)-free
F
=
PACKAGE TYPE
M
N
=
16-pin SO package
=
8-pin WSON package
SPEED
0X
=
104 MHz
DEVICE TECHNOLOGY
P
=
0.09 µm MirrorBit® Process Technology
DENSITY
128
=
128 Mbit
DEVICE FAMILY
S25FL
Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory
Table 5.1 S25FL128P Valid Combinations Table
S25FL128P Valid Combinations
Package Marking
(See Note)
Base Ordering
Part Number
Package &
Temperature
Model
Number
Speed Option
0X
Packing Type
00
01
FL128P + I + F
FL128P + I + FL
S25FL128P
MFI, NFI
0, 1, 3
Note
Package marking omits leading “S25” and speed, package, and model number form.
5.1
Valid Combinations
Table 5.1 lists the valid combinations configurations planned to be supported in volume for this device.
10
S25FL128P
S25FL128P_00_10 May 16, 2012
D a t a S h e e t
6. Spansion SPI Modes
A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices:
CPOL = 0, CPHA = 0 (Mode 0)
CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for
both modes.
When the bus master is in standby mode, SCK is as shown in Figure 6.2 for each of the two modes:
SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)
SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3)
Figure 6.1 Bus Master and Memory Devices on the SPI Bus
SO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SI
SCK
SCK SO SI
SCK SO SI
SCK SO SI
Bus Master
SPI Memory
SPI Memory
SPI Memory
Device
Device
Device
CS3 CS2 CS1
HOLD#
CS#
HOLD#
CS#
HOLD#
CS#
WP#/ACC
WP#/ACC
WP#/ACC
Note
The Write Protect/Accelerated Programming (WP#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0)
as appropriate.
Figure 6.2 SPI Modes Supported
CS#
CPOL CPHA
Mode 0
SCK
0
0
1
1
Mode 3
SCK
SI
MSB
SO
MSB
May 16, 2012 S25FL128P_00_10
S25FL128P
11
D a t a S h e e t
7. Device Operations
All Spansion SPI devices (S25FL-P) accept and output data in bytes (8 bits at a time).
7.1
Byte or Page Programming
Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program
(PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up
to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation.
Programming means that bits can either be left at the current state (1 or 0), or programmed from 1 to 0.
Changing bits from 0 to 1 requires an erase operation. Before this can be applied, the bytes of the memory
need to be first erased to all 1’s (FFh) before any programming.
7.2
Sector Erase / Bulk Erase
The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array
to 1. While bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a
sector-wide (SE) or array-wide (BE) level. The memory array needs to be first erased to all 1's (FFh) before
any programming.
7.3
7.4
Monitoring Write Operations Using the Status Register
The host system can determine when a Write Status Register, program, or erase operation is complete by
monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command
provides the state of the WIP bit.
Active Power and Standby Power Modes
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the
device is disabled, but may still be in the Active Power mode until all program, erase, and Write Status
Register operations have completed. The device then goes into the Standby Power mode, and power
consumption drops to ISB. The Deep Power Down (DP) command provides additional data protection against
inadvertent signals. After writing the DP command, the device ignores any further program or erase
commands, and reduces its power consumption to IDP
.
7.5
Status Register
The Status Register contains the status and control bits that can be read or set by specific commands (see
Table Table 11.6, Command Definitions on page 38):
Write In Progress (WIP): Indicates whether the device is performing a Write Status Register, program or
erase operation.
Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch.
Block Protect (BP2, BP1, BP0 for uniform 256 KB sector product: BP3, BP2, BP1, BP0 for uniform
64 KB sector product): Non-volatile bits that define memory area to be software-protected against
program and erase commands.
Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit
is set to 1 and the WP#/ACC input is driven low. In this mode, the non-volatile bits of the Status Register
(SRWD, BP3, BP2, BP1, BP0) become read-only bits.
7.6
Data Protection Modes
Spansion SPI Flash memory devices provide the following data protection methods:
The Write Enable (WREN) command: Must be written prior to any command that modifies data. The
WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up
or after the device completes the following commands:
– Page Program (PP)
12
S25FL128P
S25FL128P_00_10 May 16, 2012
D a t a S h e e t
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Status Register (WRSR)
Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0 for uniform 256 KB sector product:
BP3, BP2, BP1, BP0 for uniform 64 KB sector product) bits define the section of the memory array that can
be read but not programmed or erased. Table 7.1 shows the sizes and address ranges of protected areas
that are defined by Status Register bits BP2:BP0 for uniform 256 KB sector product, BP3:BP0 for uniform
64 KB sector product).
Hardware Protected Mode (HPM): The Write Protect (WP#/ACC) input and the Status Register Write
Disable (SRWD) bit together provide write protection.
Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands
consist of a clock pulse count that is a multiple of eight before executing them.
Table 7.1 S25FL128P Protected Area Sizes (Uniform 256 KB sector)
Status Register
Block Protect Bits
Protected
Memory Array
Portion of
Total Memory
Area
Protected
Address Range
Unprotected
Unprotected
Sectors
BP2
BP1
0
BP0
Protected Sectors
(0)
Address Range
000000h-FFFFFFh
000000h-FBFFFFh
000000h-F7FFFFh
000000h-EFFFFFh
000000h-DFFFFFh
000000h-BFFFFFh
000000h-7FFFFFh
None
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
None
(64) SA63:SA0
(32) SA62:SA0
(16) SA61:SA0
(8) SA59:SA0
(4) SA55:SA0
(2) SA47:SA0
(1) SA31:SA0
(0)
0
0
FC0000h-FFFFFFh
F80000h-FFFFFFh
F00000h-FFFFFFh
E00000h-FFFFFFh
C00000h-FFFFFFh
800000h-FFFFFFh
000000h-FFFFFFh
(1) SA63
1/64
1/32
1/16
1/8
1
(2) SA63:SA62
(4) SA63:SA60
(8) SA63:SA56
(16) SA63:SA48
(32) SA63:SA32
(64) SA63:SA0
1
0
0
1/4
1
1/2
1
All
Table 7.2 S25FL128P Protected Area Sizes (Uniform 64 KB sector)
Status Register
Block Protect Bits
Protected
Portion of
Total Memory
Area
Memory Array
Protected
Address Range
Unprotected
Unprotected
Sectors
BP3
0
BP2
0
BP1
0
BP0
0
Protected Sectors
(0)
Address Range
None
000000h-FFFFFFh
000000h-FDFFFFh
000000h-FBFFFFh
000000h-F7FFFFh
000000h-EFFFFFh
000000h-DFFFFFh
000000h-BFFFFFh
000000h-7FFFFFh
None
(256) SA255:SA0
0
1/128
1/64
1/32
1/16
1/8
1/4
1/2
All
0
0
0
1
FE0000h-FFFFFFh
FC0000h-FFFFFFh
F80000h-FFFFFFh
F00000h-FFFFFFh
E00000h-FFFFFFh
C00000h-FFFFFFh
800000h-FFFFFFh
000000h-FFFFFFh
000000h-FFFFFFh
000000h-FFFFFFh
000000h-FFFFFFh
000000h-FFFFFFh
000000h-FFFFFFh
000000h-FFFFFFh
000000h-FFFFFFh
(2) SA255:SA254
(4) SA255:SA252
(8) SA255:SA248
(16) SA255:SA240
(32) SA255:SA224
(64) SA255:SA192
(128) SA255:SA128
(256) SA255:SA0
(256) SA255:SA0
(256) SA255:SA0
(256) SA255:SA0
(256) SA255:SA0
(256) SA255:SA0
(256) SA255:SA0
(256) SA255:SA0
(128) SA253:SA0
0
0
1
0
(64) SA251:SA0
0
0
1
1
(32) SA247:SA0
0
1
0
0
(16) SA239:SA0
0
1
0
1
(8) SA223:SA0
0
1
1
0
(4) SA191:SA0
0
1
1
1
(2) SA127:SA0
1
0
0
0
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
1
0
0
1
None
All
1
0
1
0
None
All
1
0
1
1
None
All
1
1
0
0
None
All
1
1
0
1
None
All
1
1
1
0
None
All
1
1
1
1
None
All
May 16, 2012 S25FL128P_00_10
S25FL128P
13
D a t a S h e e t
7.7
Hold Mode (HOLD#)
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write
Status Register, program or erase operation that is currently in progress.
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see Figure 7.1 on page 14, standard
use). If the falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling
edge of SCK (non-standard use).
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-
standard use) See Figure 7.1.
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the
Hold mode.
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,
followed by driving CS# low.
Figure 7.1 Hold Mode Operation
SCK
HOLD#
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
8. Sector Address Table
Table 8.1 shows the size of the memory array, sectors, and pages. The device uses pages to cache the
program data before the data is programmed into the memory array. Each page or byte can be individually
programmed (bits are changed from 1 to 0). The data is erased (bits are changed from 0 to 1) on a sector- or
device-wide basis using the SE or BE commands. Table 8.2 shows the starting and ending address for each
sector. The complete set of sectors comprises the memory array of the Flash device.
Table 8.1 S25FL128P Device Organization
Each Device has
Each Sector has
Each Page has
262144 (256 KB sector)
65536 (64 KB sector)
16,777,216
256
bytes
1024 (256 KB sector)
256 (64 KB sector)
65,536
—
—
pages
64 (256 KB sector)
256 (64 KB sector)
—
sectors
14
S25FL128P
S25FL128P_00_10 May 16, 2012
D a t a S h e e t
Table 8.2 S25FL128P Sector Address Table (Uniform 256 KB sector)
Sector
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
Address Range
FC0000h
Sector
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Address Range
7C0000h
FFFFFFh
FBFFFFh
F7FFFFh
F3FFFFh
EFFFFFh
EBFFFFh
E7FFFFh
E3FFFFh
DFFFFFh
DBFFFFh
D7FFFFh
D3FFFFh
CFFFFFh
CBFFFFh
C7FFFFh
C3FFFFh
BFFFFFh
BBFFFFh
B7FFFFh
B3FFFFh
AFFFFFh
ABFFFFh
A7FFFFh
A3FFFFh
9FFFFFh
9BFFFFh
97FFFFh
93FFFFh
8FFFFFh
8BFFFFh
87FFFFh
83FFFFh
7FFFFFh
7BFFFFh
77FFFFh
73FFFFh
6FFFFFh
6BFFFFh
67FFFFh
63FFFFh
5FFFFFh
5BFFFFh
57FFFFh
53FFFFh
4FFFFFh
4BFFFFh
47FFFFh
43FFFFh
3FFFFFh
3BFFFFh
37FFFFh
33FFFFh
2FFFFFh
2BFFFFh
27FFFFh
23FFFFh
1FFFFFh
1BFFFFh
17FFFFh
13FFFFh
0FFFFFh
0BFFFFh
07FFFFh
03FFFFh
F80000h
F40000h
F00000h
EC0000h
E80000h
E40000h
E00000h
DC0000h
D80000h
D40000h
D00000h
CC0000h
C80000h
C40000h
C00000h
BC0000h
B80000h
B40000h
B00000h
AC0000h
A80000h
A40000h
A00000h
9C0000h
980000h
940000h
900000h
8C0000h
880000h
840000h
800000h
780000h
740000h
700000h
6C0000h
680000h
640000h
600000h
5C0000h
580000h
540000h
500000h
4C0000h
480000h
440000h
400000h
3C0000h
380000h
340000h
300000h
2C0000h
280000h
240000h
200000h
1C0000h
180000h
140000h
100000h
0C0000h
080000h
040000h
000000h
8
7
6
5
4
3
2
1
0
May 16, 2012 S25FL128P_00_10
S25FL128P
15
D a t a S h e e t
Table 8.3 S25FL128P Sector Address Table (Uniform 64 KB sector) (Sheet 1 of 2)
Sector
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
Address Range
FF0000h
Sector
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
Address Range
CF0000h
Sector
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
Address Range
9F0000h
FFFFFFh
FEFFFFh
FDFFFFh
FCFFFFh
FBFFFFh
FAFFFFh
F9FFFFh
F8FFFFh
F7FFFFh
F6FFFFh
F5FFFFh
F4FFFFh
F3FFFFh
F2FFFFh
F1FFFFh
F0FFFFh
EFFFFFh
EEFFFFh
EDFFFFh
ECFFFFh
EBFFFFh
EAFFFFh
E9FFFFh
E8FFFFh
E7FFFFh
E6FFFFh
E5FFFFh
E4FFFFh
E3FFFFh
E2FFFFh
E1FFFFh
E0FFFFh
DFFFFFh
DEFFFFh
DDFFFFh
DCFFFFh
DBFFFFh
DAFFFFh
D9FFFFh
D8FFFFh
D7FFFFh
D6FFFFh
D5FFFFh
D4FFFFh
D3FFFFh
D2FFFFh
D1FFFFh
D0FFFFh
CFFFFFh
CEFFFFh
CDFFFFh
CCFFFFh
CBFFFFh
CAFFFFh
C9FFFFh
C8FFFFh
C7FFFFh
C6FFFFh
C5FFFFh
C4FFFFh
C3FFFFh
C2FFFFh
C1FFFFh
C0FFFFh
BFFFFFh
BEFFFFh
BDFFFFh
BCFFFFh
BBFFFFh
BAFFFFh
B9FFFFh
B8FFFFh
B7FFFFh
B6FFFFh
B5FFFFh
B4FFFFh
B3FFFFh
B2FFFFh
B1FFFFh
B0FFFFh
AFFFFFh
AEFFFFh
ADFFFFh
ACFFFFh
ABFFFFh
AAFFFFh
A9FFFFh
A8FFFFh
A7FFFFh
A6FFFFh
A5FFFFh
A4FFFFh
A3FFFFh
A2FFFFh
A1FFFFh
A0FFFFh
9FFFFFh
9EFFFFh
9DFFFFh
9CFFFFh
9BFFFFh
9AFFFFh
99FFFFh
98FFFFh
97FFFFh
96FFFFh
95FFFFh
94FFFFh
93FFFFh
92FFFFh
91FFFFh
90FFFFh
8FFFFFh
8EFFFFh
8DFFFFh
8CFFFFh
8BFFFFh
8AFFFFh
89FFFFh
88FFFFh
87FFFFh
86FFFFh
85FFFFh
84FFFFh
83FFFFh
82FFFFh
81FFFFh
80FFFFh
7FFFFFh
7EFFFFh
7DFFFFh
7CFFFFh
7BFFFFh
7AFFFFh
79FFFFh
78FFFFh
77FFFFh
76FFFFh
75FFFFh
74FFFFh
73FFFFh
72FFFFh
71FFFFh
70FFFFh
FE0000h
FD0000h
FC0000h
FB0000h
FA0000h
F90000h
F80000h
F70000h
F60000h
F50000h
F40000h
F30000h
F20000h
F10000h
F00000h
EF0000h
EE0000h
ED0000h
EC0000h
EB0000h
EA0000h
E90000h
E80000h
E70000h
E60000h
E50000h
E40000h
E30000h
E20000h
E10000h
E00000h
DF0000h
DE0000h
DD0000h
DC0000h
DB0000h
DA0000h
D90000h
D80000h
D70000h
D60000h
D50000h
D40000h
D30000h
D20000h
D10000h
D00000h
CE0000h
CD0000h
CC0000h
CB0000h
CA0000h
C90000h
C80000h
C70000h
C60000h
C50000h
C40000h
C30000h
C20000h
C10000h
C00000h
BF0000h
BE0000h
BD0000h
BC0000h
BB0000h
BA0000h
B90000h
B80000h
B70000h
B60000h
B50000h
B40000h
B30000h
B20000h
B10000h
B00000h
AF0000h
AE0000h
AD0000h
AC0000h
AB0000h
AA0000h
A90000h
A80000h
A70000h
A60000h
A50000h
A40000h
A30000h
A20000h
A10000h
A00000h
9E0000h
9D0000h
9C0000h
9B0000h
9A0000h
990000h
980000h
970000h
960000h
950000h
940000h
930000h
920000h
910000h
900000h
8F0000h
8E0000h
8D0000h
8C0000h
8B0000h
8A0000h
890000h
880000h
870000h
860000h
850000h
840000h
830000h
820000h
810000h
800000h
7F0000h
7E0000h
7D0000h
7C0000h
7B0000h
7A0000h
790000h
780000h
770000h
760000h
750000h
740000h
730000h
720000h
710000h
700000h
16
S25FL128P
S25FL128P_00_10 May 16, 2012
D a t a S h e e t
Table 8.3 S25FL128P Sector Address Table (Uniform 64 KB sector) (Sheet 2 of 2)
Sector
111
110
109
108
107
106
105
104
103
102
101
100
99
Address Range
6F0000h
Sector
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
Address Range
470000h
Sector
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Address Range
1F0000h
6FFFFFh
6EFFFFh
6DFFFFh
6CFFFFh
6BFFFFh
6AFFFFh
69FFFFh
68FFFFh
67FFFFh
66FFFFh
65FFFFh
64FFFFh
63FFFFh
62FFFFh
61FFFFh
60FFFFh
5FFFFFh
5EFFFFh
5DFFFFh
5CFFFFh
5BFFFFh
5AFFFFh
59FFFFh
58FFFFh
57FFFFh
56FFFFh
55FFFFh
54FFFFh
53FFFFh
52FFFFh
51FFFFh
50FFFFh
4FFFFFh
4EFFFFh
4DFFFFh
4CFFFFh
4BFFFFh
4AFFFFh
49FFFFh
48FFFFh
47FFFFh
46FFFFh
45FFFFh
44FFFFh
43FFFFh
42FFFFh
41FFFFh
40FFFFh
3FFFFFh
3EFFFFh
3DFFFFh
3CFFFFh
3BFFFFh
3AFFFFh
39FFFFh
38FFFFh
37FFFFh
36FFFFh
35FFFFh
34FFFFh
33FFFFh
32FFFFh
31FFFFh
30FFFFh
2FFFFFh
2EFFFFh
2DFFFFh
2CFFFFh
2BFFFFh
2AFFFFh
29FFFFh
28FFFFh
27FFFFh
26FFFFh
25FFFFh
24FFFFh
23FFFFh
22FFFFh
21FFFFh
20FFFFh
1FFFFFh
1EFFFFh
1DFFFFh
1CFFFFh
1BFFFFh
1AFFFFh
19FFFFh
18FFFFh
17FFFFh
16FFFFh
15FFFFh
14FFFFh
13FFFFh
12FFFFh
11FFFFh
10FFFFh
0FFFFFh
0EFFFFh
0DFFFFh
0CFFFFh
0BFFFFh
0AFFFFh
09FFFFh
08FFFFh
07FFFFh
06FFFFh
05FFFFh
04FFFFh
03FFFFh
02FFFFh
01FFFFh
00FFFFh
6E0000h
6D0000h
6C0000h
6B0000h
6A0000h
690000h
680000h
670000h
660000h
650000h
640000h
630000h
620000h
610000h
600000h
5F0000h
5E0000h
5D0000h
5C0000h
5B0000h
5A0000h
590000h
580000h
570000h
560000h
550000h
540000h
530000h
520000h
510000h
500000h
4F0000h
4E0000h
4D0000h
4C0000h
4B0000h
4A0000h
490000h
480000h
460000h
450000h
440000h
430000h
420000h
410000h
400000h
3F0000h
3E0000h
3D0000h
3C0000h
3B0000h
3A0000h
390000h
380000h
370000h
360000h
350000h
340000h
330000h
320000h
310000h
300000h
2F0000h
2E0000h
2D0000h
2C0000h
2B0000h
2A0000h
290000h
280000h
270000h
260000h
250000h
240000h
230000h
220000h
210000h
200000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
0F0000h
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
090000h
080000h
070000h
060000h
050000h
040000h
030000h
020000h
010000h
000000h
98
97
96
95
94
93
92
91
90
89
88
8
87
7
86
6
85
5
84
4
83
3
82
2
81
1
80
0
79
78
77
76
75
74
73
72
May 16, 2012 S25FL128P_00_10
S25FL128P
17
D a t a S h e e t
9. Parallel Mode (for 16-pin SO package only)
The parallel mode provides 8 bits of input/output to increase factory production throughput at the customer
manufacturing facilities. This function is recommended for increasing production throughput. Entering Parallel
mode requires issuing the Enter Parallel Mode command (55h). After writing the Parallel Mode Entry
command and pulling CS# high, the available commands are Read, Write Enable (WREN), Write Disable
(WRDI), Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Read
Status Register (RDSR), Release from Deep Power Down/Release from Deep Power Down and Read
Electronic Signature (RES), Deep Power Down (DP), Read Identification (RDID) and Read ID (READ_ID).
The flash memory will remain in Parallel mode until either the Parallel Mode Exit command (45h) is issued, or
until a power-down / power-up sequence has been completed, after which the flash memory will exit parallel
mode automatically and switch back to serial mode (no power-down will be necessary to switch back to serial
mode if the Parallel Mode Exit command is issued).
In parallel mode, the maximum SCK clock frequency is limited to 6 MHz for Read Data Bytes and 10 MHz for
other operations. PO[6-0] can be left unconnected if the Parallel Mode functions are not needed. Fast-Read
command is not applicable in Parallel mode.
10. Accelerated Programming Operation
The device offers accelerated program operations through the ACC function. This function is primarily
intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the
device uses the higher voltage on the pin to reduce the time required for program operations. Removing VHH
from the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at
VHH for operations other than accelerated programming, or device damage may result. In addition, the WP#/
ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.
18
S25FL128P
S25FL128P_00_10 May 16, 2012
D a t a S h e e t
11. Command Definitions
The host system must shift all commands, addresses, and data in and out of the device, beginning with the
most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte
command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on
the rising edge of SCK. Table 11.6 on page 38 lists the complete set of commands.
Every command sequence begins with a one-byte command code. The command may be followed by
address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the
command sequence has been written.
The Read Data Bytes (READ), Read Status Register (RDSR), Read Data Bytes at Higher Speed
(FAST_READ) and Read Identification (RDID) command sequences are followed by a data output sequence
on SO. CS# can be driven high after any bit of the sequence is output to terminate the operation.
The Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable
(WREN), or Write Disable (WRDI) commands require that CS# be driven high at a byte boundary, otherwise
the command is not executed. Since a byte is composed of eight bits, CS# must therefore be driven high
when the number of clock pulses after CS# is driven low is an exact multiple of eight.
The device ignores any attempt to access the memory array during a Write Status Register, program, or
erase operation, and continues the operation uninterrupted.
11.1 Read Data Bytes (READ: 03h)
11.1.1
Serial Mode
The Read Data Bytes (READ-Serial Mode) command reads data from the memory array at the frequency
(fSCK) presented at the SCK input, with a maximum speed of 40 MHz. The host system must first select the
device by driving CS# low. The READ command is then written to SI, followed by a 3-byte address (A23-A0).
Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on
SO at a frequency fSCK, on the falling edge of SCK.
Figure 11.1 and Table 11.6 detail the READ command sequence. The first byte specified can be at any
location. The device automatically increments to the next higher address after each byte of data is output.
The entire memory array can therefore be read with a single READ command. When the highest address is
reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely.
The READ command is terminated by driving CS# high at any time during data output. The device rejects any
READ command issued while it is executing a program, erase, or Write Status Register operation, and
continues the operation uninterrupted.
Figure 11.1 Read Data Bytes (READ) Command Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
Mode 3
SCK
Mode 0
Command
24-Bit Address
23 22 21
2
0
1
3
SI
MSB
Data Out 1
Data Out 2
Hi-Z
SO
6
4
2
7
1 0
7
5
3
MSB
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19
D a t a S h e e t
11.1.2
Parallel Mode
In parallel mode, the maximum SCK clock frequency is 6 MHz. The device requires a single clock cycle
instead of eight clock cycles to access the next data byte. The memory array output will be the same as in the
serial mode. The only difference is that a byte of data is output per clock cycle instead of a single bit. This
means that 256 bytes of data can be copied into the 256 byte wide page write buffer in 256 clock cycles
instead of in 2,048 clock cycles.
Figure 11.2 Parallel Read Instruction Sequence
CS#
SCK
24-Bit
Instruction
Address
SI
Data Out
High Impedance
PO[7-0]
Notes
1. 1st Byte = “03h”.
2. 2nd Byte = Address 1, MSB first (bits 23 through 16).
3. 3rd Byte = Address 2, MSB first (bits 15 through 8).
4. 4th Byte = Address 3, MSB first (bits 7 through 0).
5. From the 5th Byte, SO will output the array data.
6. In parallel mode, the maximum clock frequency (Fsck) is 6 MHz.
7. For parallel mode operation, the device requires an Enter Parallel Mode command (55h) before the READ command. An Exit Parallel
Mode (45h) command or a power-down / power-up sequence is required to exit the parallel mode.
20
S25FL128P
S25FL128P_00_10 May 16, 2012
D a t a S h e e t
11.2 Read Data Bytes at Higher Speed (FAST_READ: 0Bh)
The FAST_READ command reads data from the memory array at the frequency (fSCK) presented at the SCK
input, with a maximum speed of 104 MHz. The host system must first select the device by driving CS# low.
The FAST_READ command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte.
Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on
SO at a frequency fSCK, on the falling edge of SCK.
The FAST_READ command sequence is shown in Figure 11.3 and Table 11.6. The first byte specified can
be at any location. The device automatically increments to the next higher address after each byte of data is
output. The entire memory array can therefore be read with a single FAST_READ command. When the
highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue
indefinitely.
The FAST_READ command is terminated by driving CS# high at any time during data output. The device
rejects any FAST_READ command issued while it is executing a program, erase, or Write Status Register
operation, and continues the operation uninterrupted. Note that the FAST_READ command is not valid in
parallel mode.
Figure 11.3 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence
CS#
33
0
1
2
5
6
7
8
9
29 30
32
38 39 40 41
44 45 46
42 43
Mode 3
31
34 35 36 37
3
4
10
28
47
SCK
Mode 0
24-Bit Address
Dummy Byte
Command
23
3
2
22 21
1
0
6
5
4
2
0
1
7
3
SI
Hi-Z
3
7
6
4
2
1
0
5
7
SO
MSB
MSB
DATA OUT 1
DATA OUT 2
May 16, 2012 S25FL128P_00_10
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21
D a t a S h e e t
11.3 Read Identification (RDID: 9Fh)
11.3.1 Serial Mode
The Read Identification (RDID) instruction opcode allows the 8-bit manufacturer identification to be read,
follow by two bytes of device identification. The manufacturer identification is assigned by JEDEC. The device
identification is assigned by the device manufacturer.
Any Read Identification (RDID) instruction opcode issued while a program, erase, or write cycle is in progress
is not decoded and has no effect on execution of the program, erase, or write cycle that is in progress.
The device is first selected by driving the CS# chip select input pin to the logic low state. After this, the RDID
8-bit instruction opcode is shifted in onto the SI serial input pin. After the last bit of the RDID instruction
opcode is shifted into the device, a byte of manufacturer identification, two bytes of device identification and
two bytes of extended device identification will be shifted sequentially out of the SO serial output pin. Each bit
is shifted out during the falling edge of the SCK serial clock signal. The maximum clock frequency for the
RDID (9Fh) command is at 40 MHz (Normal Read).
The Read Identification (RDID) instruction sequence is terminated by driving the CS# chip select input pin to
the logic high state anytime during data output. After issuing any Read ID instruction opcodes (90h, 9Fh,
ABh), driving the CS# chip select input pin to the logic high state will automatically send the device into the
standby mode. Driving the CS# chip select input pin to the logic low state again will automatically send the
device out of the standby mode and into the active mode.
Figure 11.4 Read Identification Command Sequence and Data Out Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34
44 45 46 47
SCK
Instruction
SI
Extended Device Identification
Manufacturer / Device Identification
High Impedance
SO
23 22 21
MSB
3
2
1
0
15 14 13
MSB
3
2
1
0
22
S25FL128P
S25FL128P_00_10 May 16, 2012
D a t a S h e e t
11.3.2
Parallel Mode
In parallel mode, the maximum SCK clock frequency is 10 MHz. The device requires a single clock cycle
instead of eight clock cycles to access the next data byte. The method of memory content output will be the
same compared to the serial mode. The only difference is that a byte of data is output per clock cycle instead
of a single bit. In this case, the manufacturer identification will be output during the first byte cycle and the
device identification during the second and third byte cycles out of the PO7-PO0 serial output pins. To read ID
in parallel mode requires a Parallel Mode Entry command (55h) to be issued before the RDID command.
Once in the parallel mode, the flash memory will not exit parallel mode until a Parallel Mode Exit (45h)
command is given to the flash device, or upon power down/power up sequence.
Figure 11.5 Parallel Read_ID Command Sequence and Data Out Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
11 12
SCK
Instruction
SI
Manufacturer/Device Identification
High Impedance
Byte
0
Byte
1
Byte Byte
Byte
4
2
3
PO[7-0]
Table 11.1 Manufacturer & Device Identification, RDID (9Fh)
Manufacturer Identification
Device Identification
Extended Device Identification
Device
Byte 0
01h
Byte 1
20h
Byte 2
18h
Byte 3
03h
Byte 4
00h
Uniform 256 KB Sector
Uniform 64 KB Sector
01h
20h
18h
03h
01h
May 16, 2012 S25FL128P_00_10
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23
D a t a S h e e t
11.4 Read Manufacturer and Device ID (READ_ID: 90h)
11.4.1
Serial Mode
The READ_ID (90h) instruction identifies the Device Manufacturer ID and the Device ID. The instruction is
initiated by driving the CS# pin low and shifting in (via the SI input pin) the instruction code “90h” followed by
a 24-bit address of XXXXX0h. (X: High or Low) Following this, the Manufacturer ID and the Device ID are
shifted out on SO output pin starting after the falling edge of the SCK serial clock input signal. The
Manufacturer ID and the Device ID are always shifted out on the SO output pin with the MSB first, as shown
in Figure 11.6. If the 24-bit address is set to XXXXX1h, then the Device ID is read out first followed by the
Manufacturer ID. Note that the upper 23 bits of the address do not have to be 0’s and can be don’t cares.
Once the device is in READ_ID mode, the Manufacturer ID and Device ID output data toggles between
address 000000H and 000001H until terminated by a low to high transition on the CS# input pin. After the first
24-bit address is provided, the user must wait 16 clock cycles for both the Manufacturer ID and Device ID to
be output on the SO output pin. The maximum clock frequency for the READ_ID (90h) command is at
104MHz (Fast Read). Parallel Mode the maximum clock frequency is 10 Mhz.
The Manufacturer ID & Device ID is output continuously until terminated by a low to high transition on CS#
chip select input pin.
After issuing READ_ID instruction, driving the CS# chip select input pin to the logic high state will
automatically send the device into the standby mode. Driving the CS# chip select input pin to the logic low
state again will automatically send the device out of the standby mode and into the active mode.
Figure 11.6 Serial READ_ID Instruction Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
24-Bit Address
SI
23 22 21 20 19 18 17 16
High Impedance
15 14 13 12 11 10
9
8
90h
High Impedance
SO
CS#
SCK
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
24-Bit Address
SI
7
6
5
4
3
2
1
0
Manufacturer ID
Device ID
High Impedance
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
MSB
MSB
24
S25FL128P
S25FL128P_00_10 May 16, 2012
D a t a S h e e t
11.4.2
Parallel Mode
The maximum clock frequency allowed on the SCK input pin in parallel mode is 10 MHz. The Parallel Mode
Entry command (55h) must be issued before writing the READ_ID command. Once in the parallel mode, the
flash memory will not exit parallel mode until a Parallel Mode Exit (45h) command is given to the flash device,
or upon power-down/power-up sequence.
Figure 11.7 Parallel Read_ID Instruction Sequence
CS#
20 21 22 23 24 25 26
33 34
27 28 29 30 31 32
0
1
2
3
4
5
6
7
8
9
10
SCK
2 Dummy
Bytes
Instruction
ADD (1)
15 14 13
MSB
3
2
1
0
7
6
5
4
3
2
1
0
SI
90h
High Impedance
Byte
1
Byte
2
PO[7-0]
Manufacture ID
Device ID
Table 11.2 READ_ID Command and Data
Description
Address
00000h
00001h
Data
01h
Manufacturer Identification
Device Identification (Memory Capacity)
17h
11.5 Write Enable (WREN: 06h)
The Write Enable (WREN) command (see Figure 11.8) sets the Write Enable Latch (WEL) bit to a 1, which
enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set
prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command.
The host system must first drive CS# low, write the WREN command, and then drive CS# high.
Figure 11.8 Write Enable (WREN) Command Sequence
CS#
6
5
7
0
1
2
3
4
Mode 3
SCK
SI
Mode 0
Command
Hi-Z
SO/PO[7-0]
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25
D a t a S h e e t
11.6 Write Disable (WRDI: 04h)
The Write Disable (WRDI) command (see Figure 11.9) resets the Write Enable Latch (WEL) bit to a 0, which
disables the device from accepting a Write Status Register, program, or erase command. The host system
must first drive CS# low, write the WRDI command, and then drive CS# high.
Any of following conditions resets the WEL bit:
Power-up
Write Disable (WRDI) command completion
Write Status Register (WRSR) command completion
Page Program (PP) command completion
Sector Erase (SE) command completion
Bulk Erase (BE) command completion
Figure 11.9 Write Disable (WRDI) Command Sequence
CS#
0
3
4
7
6
1 2
5
Mode 3
SCK
SI
Mode 0
Command
Hi-Z
SO/PO[7-0]
11.7 Read Status Register (RDSR: 05h)
11.7.1 Serial Mode
The Read Status Register (RDSR) command outputs the state of the Status Register bits. Table 11.3 shows
the status register bits and their functions.
The RDSR command may be written at any time, even while a program, erase, or Write Status Register
operation is in progress. The host system should check the Write In Progress (WIP) bit before sending a new
command to the device if an operation is already in progress. Figure 11.10 shows the RDSR command
sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven
high.
Table 11.3 S25FL128P Status Register (Uniform 256 KB sector)
Bit
Status Register Bit
Bit Function
Description
1 = Protects when WP#/ACC is low
Status Register Write
Disable
7
SRWD
0 = No protection, even when WP#/ACC is low
6
5
4
3
2
Don’t Care
0
—
—
—
Not used
BP2
BP1
Block Protect
000–111 = Protects upper half of address range in 7 sizes.
BP0
1 = Device accepts Write Status Register, program, or erase commands
0 = Ignores Write Status Register, program, or erase commands
1
0
WEL
WIP
Write Enable Latch
Write in Progress
1 = Device Busy. A Write Status Register, program, or erase operation is
in progress
0 = Ready. Device is in standby mode and can accept commands.
26
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D a t a S h e e t
Table 11.4 S25FL128P Status Register (Uniform 64 KB sector)
Bit
Status Register Bit
Bit Function
Description
1 = Protects when WP#/ACC is low
Status Register Write
Disable
7
SRWD
0 = No protection, even when WP#/ACC is low
—
6
5
4
3
2
Don’t Care
BP3
—
BP2
Block Protect
0000–1111= Protects upper half of address range in 8 sizes.
BP1
BP0
1 = Device accepts Write Status Register, program, or erase commands
0 = Ignores Write Status Register, program, or erase commands
1
0
WEL
WIP
Write Enable Latch
Write in Progress
1 = Device Busy. A Write Status Register, program, or erase operation is
in progress
0 = Ready. Device is in standby mode and can accept commands.
Figure 11.10 Read Status Register (RDSR) Command Sequence
CS#
SCK
7
0
2
3
4
5
6
9
11
12 13 14
15
1
8
10
Mode 3
Mode 0
Command
SI
Hi-Z
SO
6
4
2
6
5
7
5
3
1
0
4
2
7
0
7
3
1
MSB
MSB
Status Register Out
Status Register Out
May 16, 2012 S25FL128P_00_10
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27
D a t a S h e e t
11.7.2
Parallel Mode
When the device is in Parallel Mode, the maximum SCK clock frequency is 10 MHz. The device requires a
single clock cycle instead of eight clock cycles to access the next data byte. The method of memory content
output will be the same compared to outside of Parallel Mode. The only difference is that a byte of data is
output per clock cycle instead of a single bit. The Status Register contents can be read out on the PO[7-0]
serial output pins continuously by applying multiples of clock cycles.
Figure 11.11 Parallel Read Status Register (RDSR) Instruction Sequence
CS#
7
0
2
3
4
5
6
9
11
10
12 13 14
1
8
Mode 3
SCK
Mode 0
Command
SI
PO[7-0]
Hi-Z
Byte Byte
Byte
n
1
2
Status Register Out
Notes
1. Instruction byte = 05h.
2. Under parallel mode, the fastest access clock frequency (Fsck) will be changed to a maximum of 10MHz (SCK pin clock frequency).
3. To read Status Register in parallel mode requires a Parallel Mode Entry command (55h) to be issued before the RDSR command. Once
in the parallel mode, the flash memory will not exit the parallel mode until a Parallel Mode Exit (45h) command is given to the flash device,
or upon power down / power up sequence.
11.7.3
Status Register Bit Descriptions
The following describes the status and control bits of the Status Register, and applies to both serial and
parallel modes.
Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Status Register,
program, or erase operation. This bit is read-only, and is controlled internally by the device. If WIP is 1, one of
these operations is in progress; if WIP is 0, no such operation is in progress.
Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Status
Register, program, or erase command. When set to 1, the device accepts these commands; when set to 0,
the device rejects the commands. This bit is set to 1 by writing the WREN command, and set to 0 by the
WRDI command, and is also automatically reset to 0 after the completion of a Write Status Register, program,
or erase operation. WEL cannot be directly set by the WRSR command.
Block Protect (BP2, BP1, BP0) bits for uniform 256KB sector product: (BP3, BP2, BP1, BP0) for
uniform 64KB sector product: Define the portion of the memory area that will be protected against any
changes to the stored data. The Write Status Register (WRSR) command controls these bits, which are non-
volatile. When one or more of these bits is set to 1, the corresponding memory area (see Table 7.1
on page 13) is protected against Page Program (PP) and Sector Erase (SE) commands. If the Hardware
Protected mode is enabled, BP2:BP0 (or BP3:BP0) cannot be changed. The Bulk Erase (BE) command is
executed only if all Block Protect bits are 0.
Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write
Protect (WP#/ACC) signal. When SRWD is set to 1 and WP#/ACC is driven low, the device enters the
Hardware Protected mode. The non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits and the device ignores any Write Status Register (WRSR) command.
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11.8 Write Status Register (WRSR: 01h)
The Write Status Register (WRSR) command changes the bits in the Status Register. A Write Enable
(WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to
writing the WRSR command. Table 11.3, S25FL128P Status Register (Uniform 256 KB sector) on page 26
shows the status register bits and their functions.
The host system must drive CS# low, write the WRSR command, and the appropriate data byte on SI
(Figure 11.12).
The WRSR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must
be used for that purpose. Bit 0 is a status bit controlled internally by the Flash device. Bits 6 and 5 are always
read as 0 and have no user significance.
The WRSR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit
and WP#/ACC together place the device in the Hardware Protected Mode (HPM). The device ignores all
WRSR commands once it enters the Hardware Protected Mode (HPM). Table 11.5 shows that WP#/ACC
must be driven low and the SRWD bit must be 1 for this to occur.
Figure 11.12 Write Status Register (WRSR) Command Sequence
CS#
8
9
10
12 13 14 15
11
4
6
7
Mode 3
0
1
2
3
5
SCK
Mode 0
Command
Register In
Status
7
6
5
4
3
2
1
0
SI
MSB
Hi-Z
SO
Figure 11.13 Parallel Write Status Register (WRSR) Command Sequence
CS#
8
9
10
12 13 14 15
11
4
6
7
Mode 3
0
1
2
3
5
SCK
Mode 0
Command
Register In
Status
SI
Byte 1
Hi-Z
PO[7-0]
Notes
1. Instruction byte = 01h
2. In parallel mode, the maximum access clock frequency (Fsck) is 10 MHz (SCK pin clock frequency).
3. Writing to the Status Register in parallel mode requires a Parallel Mode Entry command (55h) to be issued before the WRSR command.
Once in the parallel mode, the flash memory will not exit the parallel mode until a Parallel Mode Exit (45h) command is given to the flash
device, or upon power-down or power-up sequence.
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Table 11.5 Protection Modes
WP#/ACC
Signal
Protected Area
(See Note)
Unprotected Area
(See Note)
SRWD Bit
Mode
Write Protection of the Status Register
1
1
0
1
0
0
Status Register is writable (if the WREN
Software
Protected
(SPM)
Ready to accept Page
Program and Sector Erase
commands
command has set the WEL bit). The values in
the SRWD, BP2, BP1 and BP0 (or BP3, BP2,
BP1 and BP0) bits can be changed.
Protected against program
and erase commands
Status Register is Hardware write protected.
The values in the SRWD, BP2, BP1 and BP0
(or BP3, BP2, BP1 and BP0) bits cannot be
changed.
Hardware
Protected
(HPM)
Ready to accept Page
Program and Sector Erase
commands
Protected against program
and erase commands
0
1
Note
As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 7.1 on page 13.
Table 11.5 shows that neither WP#/ACC or SRWD bit by themselves can enable HPM. The device can enter
HPM either by setting the SRWD bit after driving WP#/ACC low, or by driving WP#/ACC low after setting the
SRWD bit. However, the device disables HPM only when WP#/ACC is driven high.
Note that HPM only protects against changes to the status register. Since BP2:BP0 (or BP3:BP0) cannot be
changed in HPM, the size of the protected area of the memory array cannot be changed. Note that HPM
provides no protection to the memory array area outside that specified by Block Protect bits (Software
Protected Mode, or SPM).
If WP#/ACC is permanently tied high, HPM can never be activated, and only the SPM (Block Protect bits of
the Status Register) can be used.
11.9 Page Program (PP: 02h)
11.9.1
Serial Mode
The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the PP command, three address bytes, and at least one
data byte on SI. CS# must be driven low for the entire duration of the PP sequence. The command sequence
is shown in Figure 11.14 and Table 11.6.
The device programs only the last 256 data bytes sent to the device. If the number of data bytes exceeds this
limit, the bytes sent before the last 256 bytes are discarded, and the device begins programming the last 256
bytes sent at the starting address of the specified page. This may result in data being programmed into
different addresses within the same page than expected. If fewer than 256 data bytes are sent to device, they
are correctly programmed at the requested addresses.
The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the
device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of tPP. The Status Register may
be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP
bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute a Page Program (PP) command that specifies a page that is protected by the
Block Protect bits (see Table 7.1 on page 13).
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Figure 11.14 Page Program (PP) Command Sequence
CS#
SCK
5
8
34
37 38 39
35 36
0
2
4
6
7
10
28 32 33
29 30 31
1
3
9
Mode 3
Mode 0
24-Bit Address
22 21
Data Byte 1
Command
4
3
2
3
2
1
0
7
6
5
1
0
23
SI
MSB
MSB
CS#
SCK
53 54 55
52
49 50 51
46
44 45
40
47 48
41 42 43
Data Byte 2
Data Byte 3
Data Byte 256
0
7
6
0
1
7
MSB
7
6
5
4
3
2
1
0
6
5
4
3
2
1
5
4
3
2
SI
MSB
MSB
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11.9.2
Parallel Mode
In parallel mode, the maximum SCK clock frequency is 10 MHz. The device requires a single clock cycle
instead of eight clock cycles to access the next data byte. The memory content input method is the same as
serial mode. The only difference is that a byte of data is input per clock cycle instead of a single bit. This
means that 256 bytes of data can be copied into the 256 byte wide page write buffer in 256 clock cycles
instead of in 2,048 clock cycles.
Figure 11.15 Parallel Page Program (PP) Instruction Sequence
CS#
n
16
23 24
31 32 33
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Address Byte 1
SCK
Address
Byte 2
Address
Byte 3
Instruction (02h)
23 22 21
MSB
17
15
7
20 19 18
16
8
0
SI
90h
Hi-Z
High-Z
Byte
n
Byte Byte
PO[7-0]
1
2
Notes
1. 1st Byte = “02h”.
2. 2nd Byte = Address 1, MSB first (bits 23 through 16).
3. 3rd Byte = Address 2, MSB first (bits 15 through 8).
4. 4th Byte = Address 3, MSB first (bits 7 through 0).
5. 5th Byte = first write data byte.
6. In parallel mode, the fastest access clock frequency (Fsck) is 10 MHz (SCK pin clock frequency).
7. Programming in parallel mode requires an “Parallel mode Entry” command (55h) before the program command. Once in the parallel
mode, the flash memory will not exit parallel mode until an “Exit Parallel Mode” (45h) command is given to the flash device, or upon power
down / power up sequence completion.
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11.10 Sector Erase (SE: 20h, D8h)
The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN
command is required prior to writing the SE command.
The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any
address within the sector (see Table 7.1 on page 13) is a valid address for the SE command. CS# must be
driven low for the entire duration of the SE sequence. The command sequence is shown in Figure 11.16 and
Table 11.6.
The host system must drive CS# high after the device has latched the 24th bit of the Address input, otherwise
the device does not execute the command. The SE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of tSE. The Status Register may
be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP
bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute an SE command that specifies a sector that is protected by the Block Protect
bits (see Table 7.1 on page 13).
Figure 11.16 Sector Erase (SE) Command Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
Mode 3
SCK
Mode 0
Command
24-bit Address
1
SI
23 22 21
MSB
3
2
0
Hi-Z
SO/PO[7-0]
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11.11 Bulk Erase (BE: C7h, 60h)
The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command
is required prior to writing the BE command.
For 64 KB sector devices, the bulk erase command may be written as either C7h or 60h. For 256 KB sector
devices, only the C7h command is valid.
The host system must drive CS# low, and then write the BE command on SI. CS# must be driven low for the
entire duration of the BE sequence. The command sequence is shown in Figure 11.17 and Table 11.6.
The host system must drive CS# high after the device has latched the 8th bit of the BE command, otherwise
the device does not execute the command. The BE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of tBE. The Status Register may
be read to check the value of the Write In Progress (WIP) bit while the BE operation is in progress. The WIP
bit is 1 during the BE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device only executes a BE command if all Block Protect bits (BP2:BP0 or BP3:BP0) are 0 (see Table 7.1
on page 13). Otherwise, the device ignores the command.
Figure 11.17 Bulk Erase (BE) Command Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Command
SI
Hi-Z
SO/PO[7-0]
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11.12 Deep Power Down (DP: B9h)
The Deep Power Down (DP) command provides the lowest power consumption mode of the device. It is
intended for periods when the device is not in active use, and ignores all commands except for the Release
from Deep Power Down (RES) command. The DP mode therefore provides the maximum data protection
against unintended write operations. The standard standby mode, which the device goes into automatically
when CS# is high (and all operations in progress are complete), should generally be used for the lowest
power consumption when the quickest return to device activity is required.
The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the
entire duration of the DP sequence. The command sequence is shown in Figure 11.18 and Table 11.6.
The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise
the device does not execute the command. After a delay of tDP, the device enters the DP mode and current
reduces from ISB to IDP (see Table 17.1 on page 41).
Once the device has entered the DP mode, all commands are ignored except the RES command (which
releases the device from the DP mode). The RES command also provides the Electronic Signature of the
device to be output on SO, if desired (see sections 11.13 and 11.14).
DP mode automatically terminates when power is removed, and the device always powers up in the standard
standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write
Status Register operation, and continues the operation uninterrupted.
Figure 11.18 Deep Power Down (DP) Command Sequence
CS#
t
DP
0
1
2
3
4
5
6
7
Mode 3
SCK
Mode 0
Command
SI
Hi-Z
SO/PO[7-0]
Standby Mode
Deep Power-down Mode
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35
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11.13 Release from Deep Power Down (RES: ABh)
The device requires the Release from Deep Power Down (RES) command to exit the Deep Power Down
mode. When the device is in the Deep Power Down mode, all commands except RES are ignored.
The host system must drive CS# low and write the RES command to SI. CS# must be driven low for the entire
duration of the sequence. The command sequence is shown in Figure 11.19 and Table 11.6.
The host system must drive CS# high tRES(max) after the 8-bit RES command byte. The device transitions
from DP mode to the standby mode after a delay of tRES (see Table 19.1 on page 43). In the standby mode,
the device can execute any read or write command.
Figure 11.19 Release from Deep Power Down (RES) Command Sequence
CS#
7
0
2
3
5
1
4
6
Mode 3
SCK
Mode 0
tRES
Command
SI
Hi-Z
SO/PO[7-0]
Deep Power-down Mode
Standby Mode
11.14 Release from Deep Power Down and Read Electronic Signature (RES: ABh)
11.14.1 Serial Mode
This command reads the old-style Electronic Signature from the SO serial output pin. See Figure 11.20 and
Table 11.6 for the command sequence and signature value. Please note that the Electronic Signature only
consists of the Device ID portion of the 16-bit JEDEC ID that is read by the Read Identifier (RDID) instruction.
The old style Electronic Signature is supported for backward compatibility, and should not be used for new
software designs, which should instead use the JEDEC 16-bit Electronic Signature by issuing the Read
Identifier (RDID) command.
The device is first selected by driving the CS# chip select input pin to the logic low state. The RES command
is shifted in followed by three dummy bytes onto the SI serial input pin. After the last bit of the three dummy
bytes is shifted into the device, a byte of Electronic Signature will be shifted out of the SO serial output pin.
Each bit is shifted out during the falling edge of the SCK serial clock signal. The maximum clock frequency for
the RES (ABh) command is at 104 MHz.
The Electronic Signature can be read repeatedly by applying multiples of eight clock cycles.
The RES instruction sequence is terminated by driving the CS# chip select input pin to the logic high state
anytime during data output. After issuing any Read ID commands (90h, 9Fh, ABh), driving the CS# chip
select input pin to the logic high state will automatically send the device into the standby mode. Driving the
CS# chip select input pin to the logic low state again will automatically send the device out of the standby
mode and into the active mode.
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Figure 11.20 Serial Release from Deep Power Down and
Read Electronic Signature (RES) Command Sequence
CS#
SCK
2
28 29 30
31 32 33 34
1
8
36 37
9
35
38
0
3
4
5
6
7
10
t
RES
3 Dummy Bytes
Command
SI
3
1
0
2
23 22
MSB
21
Hi-Z
7
6
5
4
3
2
1
SO
0
MSB
Electronic ID out
Standby Mode
Deep Power-down Mode
11.14.2 Parallel Mode
When the device is in parallel mode, the maximum SCK clock frequency is 10 MHz. The device requires a
single clock cycle instead of eight clock cycles to access the next data byte. The method of memory content
output will be the same compared to outside of parallel mode. The only difference is that a byte of data is
output per clock cycle instead of a single bit. In this case, the Electronic Signature will be output onto the
P0[7–0] parallel output pins.
Figure 11.21 Parallel Release from Deep Power Down and
Read Electronic Signature (RES) Command Sequence
CS#
SCK
2
28 29 30
31 32 33 34
1
8
36 37
35
9
38
0
3
4
5
6
7
10
t
RES
3 Dummy Bytes
Command
SI
3
1
0
2
23 22
MSB
21
Hi-Z
PO[7-0]
Byte
1
Electronic ID
Standby Mode
Deep Power-down Mode
Notes
1. In parallel mode, the maximum access clock frequency (Fsck) is 10 MHz (SCK pin clock frequency).
2. To release the device from Deep Power Down and read Electronic ID in parallel mode, a Parallel Mode Enter command (55h) must be issued before the RES
command. The device will not exit parallel mode until a Parallel Mode Exit command (45h) is written, or upon power-down or power-up sequence.
3. Byte 1 will output the Electronic Signature.
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11.15 Command Definitions
Table 11.6 Command Definitions
One-Byte
Address
Bytes
Dummy
Byte
Operation
Command
Description
Read Data Bytes
Command Code
03h (0000 0011)
0Bh (0000 1011)
9Fh (1001 1111)
90h (1001 0000)
06h (0000 0110)
04h (0000 0100)
Data Bytes
1 to ∞
1 to ∞
1 to 3
1 to ∞
0
READ
3
3
0
3
0
0
0
1
0
0
0
0
FAST_READ Read Data Bytes at Higher Speed
Read
RDID
READ_ID
WREN
Read Identification
Read Manufacturer ID and Device ID
Write Enable
Write Control
WRDI
Write Disable
0
20h (0010 0000) or
D8h (1101 1000)
64 KB Sector Erase (See Note)
256 KB Sector Erase
3
3
0
0
0
0
0
0
0
SE
BE
D8h (1101 1000)
Erase
Bulk (Chip) Erase, Uniform 64 KB
Sector Product (See Note)
C7h (1100 0111) or
60h (0110 0000)
Bulk (Chip) Erase, Uniform 256 KB
Sector Product
C7h (1100 0111)
0
0
0
Program
PP
RDSR
WRSR
Entry
Exit
Page Program
02h (0000 0010)
05h (0000 0101)
01h (0000 0001)
55h (0101 0101)
45h (0100 0101)
B9h (1011 1001)
ABh (1010 1011)
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1 to 256
Read from Status Register
Write to Status Register
Enter x8 Parallel Mode
Exit x8 Parallel Mode
Deep Power Down
1 to ∞
Status Register
1
0
0
0
0
Parallel Mode
Power Saving
DP
Release from Deep Power Down
RES
Release from Deep Power Down and
Read Electronic Signature
ABh (1010 1011)
0
3
1 to ∞
Note
For 64 KB sector devices, either command is valid and performs the same function.
12. Program Acceleration via WP#/ACC pin
The program acceleration function requires applying VHH to the WP#/ACC input, and then waiting a period of
tWC. Minimum tVHH rise and fall times is required for WP#/ACC to change to VHH from VIL or VIH. Removing
VHH from the WP#/ACC pin returns the device to normal operation after a period of tWC
.
Figure 12.1 ACC Program Acceleration Timing Requirements
VHH
tWC
tWC
VIL or VIH
VIL or VIH
ACC
tVHH
tVHH
Command OK
Command OK
Note
Only Read Status Register (RDSR) and Page Program (PP) operations are allow when ACC is at (V ).
HH
Table 12.1 ACC Program Acceleration Specifications
Parameter
Description
Min.
8.5
Max.
Unit
V
V
9.5
ACC Pin Voltage High
HH
t
250
ns
ACC Voltage Rise and Fall Time
VHH
ACC at VHH and VIL or VIH to First
command
t
5
ns
WC
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13. Power-up and Power-down
During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied
on VCC, and must not be driven low to select the device until VCC reaches the allowable values as follows
(see Figure 13.1 and Table 13.1):
At power-up, VCC (min.) plus a period of tPU
At power-down, VSS
A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements.
No Write Status Register, program, or erase command should be sent to the device until VCC rises to the VCC
minimum, plus a delay of tPU. At power-up, the device is in standby mode (not Deep Power Down mode) and
the WEL bit is reset (0).
Each device in the host system should have the VCC rail decoupled by a suitable capacitor close to the
package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the VCC feed.
When VCC drops from the operating voltage to below the minimum VCC threshold at power-down, all
operations are disabled and the device does not respond to any commands. Note that data corruption may
result if a power-down occurs while a Write Register, program, or erase operation is in progress.
Figure 13.1 Power-Up Timing Diagram
Vcc
(max)
cc
V
(min)
cc
V
tPU
Full Device Access
Time
Figure 13.2 Power-down and Voltage Drop
Vcc
V
(max)
CC
No Device Access Allowed
V
(min)
CC
Device Access
Allowed
t
PU
V
CC
(cut-off)
V
(low)
CC
t
PD
Time
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Table 13.1 Power-Up / Power-Down Voltage and Timing
Symbol
Parameter
(minimum operation voltage)
Min
2.7
2.4
Max
Unit
V
V
V
V
CC(min)
CC
CC
V
(cut-off)
(Cut off where re-initialization is needed)
V
CC
0.2
2.3
V
V
(Low voltage for initialization to occur at read/standby)
(Low voltage for initialization to occur at embedded)
CC
CC
V
(low)
V
CC
t
t
V
V
(min) to device operation
(low duration time)
300
µs
µs
PU
CC
CC
1.0
PD
14. Initial Delivery State
The device is delivered with all bits set to 1 (each byte contains FFh) upon initial factory shipment. The Status
Register contains 00h (all Status Register bits are 0).
15. Absolute Maximum Ratings
Do not stress the device beyond the ratings listed in this section, or serious, permanent damage to the device
may result. These are stress ratings only and device operation at these or any other conditions beyond those
indicated in this section and in the Operating Ranges section of this document is not implied. Device
operation for extended periods at the limits listed in this section may affect device reliability.
Table 15.1 Absolute Maximum Ratings
Description
Ambient Storage Temperature
Rating
–65°C to +150°C
Voltage with Respect to Ground: All Inputs and I/Os
–0.5V to V +0.5V
CC
Notes
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input at I/O pins may overshoot V to –2.0V for periods of
SS
up to 20 ns. See Figure 15.2. Maximum DC voltage on output and I/O pins is 3.6 V. During voltage transitions output pins may overshoot
to V + 2.0V for periods up to 20 ns. See Figure 15.2.
CC
2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
3. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not
implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 15.1 Maximum Negative Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
–2 V
20 ns
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Figure 15.2 Maximum Positive Overshoot Waveform
20 ns
V
CC +2.0 V
V
CC+0.5 V
2.0 V
20 ns
20 ns
16. Operating Ranges
Table 16.1 Operating Ranges
Description
Rating
Ambient Operating Temperature (T )
A
Industrial
–40°C to +85°C
2.7V to 3.6 V
Positive Power Supply
Voltage Range
Note
Operating ranges define those limits between which functionality of the device is guaranteed.
17. DC Characteristics
This section summarizes the DC Characteristics of the device. Designers should check that the operating
conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 18.1
on page 42, when relying on the quoted parameters.
Table 17.1 DC Characteristics (CMOS Compatible)
Parameter
Description
Supply Voltage
Test Conditions (See Note)
Min
Typ.
Max
Unit
V
2.7
3.6
V
CC
SCK = 0.1 V
/
CC
0.9V
104 MHz (Serial)
22
mA
CC
I
Active Read Current
CC1
40 MHz (Serial: Fast
Read Mode)
10
mA
SCK = 0.1 V
/
CC
0.9V
CC
3 MHz (Parallel Mode)
10
26
26
26
26
200
20
2
mA
mA
mA
mA
mA
µA
µA
µA
µA
V
I
I
I
I
Active Page Program Current CS# = V
CC
CC2
CC3
CC4
CC5
Active WRSR Current
Active Sector Erase Current
Active Bulk Erase Current
Standby Current
CS# = V
CS# = V
CS# = V
CC
CC
CC
I
V
V
V
V
= GND or V , CS# = V
CC
SB
IN
IN
IN
IN
CC
CC
I
Deep Power Down Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
= GND or V , CS# = V
3
DP
CC
I
= GND or V , V = V max
CC CC CC
LI
I
= GND to V , V = V max
2
LO
CC CC
CC
V
–0.3
0.3 V
CC
IL
V
Input High Voltage
0.7 V
V
+ 0.5
V
IH
CC
CC
V
Output Low Voltage
I
I
= 1.6 mA, V = V
CC CC min
0.4
V
OL
OH
OL
V
Output High Voltage
= –0.1 mA
V
– 0.6
CC
V
OH
Note
Typical values are at T = 25°C and 3.0 V.
A
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D a t a S h e e t
18. Test Conditions
Figure 18.1 AC Measurements I/O Waveform
0.8 VCC
Input Levels
0.2 VCC
0.7 VCC
0.5 VCC
0.3 VCC
Input and Output
Table 18.1 Test Specifications
Symbol
Parameter
Min
Max
Unit
pF
ns
V
C
Load Capacitance
30
L
Input Rise and Fall Times
Input Pulse Voltage
5
0.2 V to 0.8 V
CC
CC
CC
Input Timing Reference Voltage
Output Timing Reference Voltage
0.3 V to 0.7 V
V
CC
0.5 V
V
CC
42
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19. AC Characteristics
Table 19.1 AC Characteristics
Typ
Max
Symbol
Parameter
Min
(Notes)
(Notes)
Unit
40 (Serial)
6 (Parallel)
F
SCK Clock Frequency READ, RDID command
D.C.
MHz
SCK
SCK
CRT
SCK Clock Frequency for:
FAST_READ, READ_ID, PP, SE, BE, DP, RES, WREN, WRDI, RDSR,
WRSR (Note 4)
104 (Serial)
10 (Parallel)
F
D.C.
MHz
0.1 (Serial)
0.25 (Parallel)
t
Clock Rise Time (Slew Rate)
Clock Fall Time (Slew Rate)
SCK High Time
V/ns
V/ns
ns
0.1 (Serial)
0.25 (Parallel)
t
CFT
4.5 (Serial)
50 (Parallel)
t
WH
4.5 (Serial)
50 (Parallel)
t
SCK Low Time
ns
WL
50 (Serial)
20 (Parallel)
t
CS# High Time
ns
CS
t
CS# Setup Time (Note 3)
3
3
3
3
3
3
ns
ns
ns
ns
ns
ns
CSS
t
CS# HOLD Time (Note 3)
CSH
t
t
t
t
HOLD# Setup Time (relative to SCK) (Note 3)
HOLD# Non-Active Hold Time (relative to SCK) (Note 3)
HOLD# Non-Active Setup Time (relative to SCK)
HOLD# Hold Time (relative to SCK)
HD
CD
HC
CH
8 (Serial)
20 (Parallel)
t
Output Valid
0
0
ns
ns
ns
V
t
Output Hold Time
Data in Hold Time
HO
2 (Serial)
10 (Parallel)
t
HD:DAT
3 (Serial)
10 (Parallel)
t
Data in Setup Time
ns
SU:DAT
t
Input Rise Time
Input Fall Time
5
5
ns
ns
R
t
F
8 (Serial)
20 (Parallel)
t
HOLD# to Output Low Z (Note 3)
HOLD# to Output High Z (Note 3)
Output Disable Time (Note 3)
ns
ns
ns
LZ
8 (Serial)
20 (Parallel)
t
HZ
8 (Serial)
20 (Parallel)
t
DIS
t
Write Protect Setup Time (Notes 3, 5)
Write Protect Hold Time (Notes 3, 5)
Write Status Register Time
CS# High to Deep Power Down Mode
Release DP Mode
20
ns
ns
WPS
t
100
WPH
t
100
3
ms
µs
W
t
DP
t
30
µs
RES
t
t
t
t
t
Page Programming Time
1.2 (Note 1)
1.02 (Note 6)
0.5 (Note 1)
2 (Note 1)
3 (Note 2)
2.4 (Note 2)
3 (Note 2)
12 (Note 2)
768 (Note 2)
ms
ms
sec
sec
sec
PP
EP
SE
SE
BE
Page Programming Time (WP#/ACC = 9 V)
Sector Erase Time (64 KB)
Sector Erase Time (256 KB)
Bulk Erase Time
128 (Note 1)
Notes
1. Typical program and erase times assume the following conditions: 25°C, V = 3.0 V; 10,000 cycles; checkerboard data pattern
CC
2. Under worst-case conditions of 90°C; V = 2.7V; 100,000 cycles
CC
3. Not 100% tested.
4. FAST_READ is not valid in parallel mode.
5. Only applicable as a constraint for WRSR command when SRWD is set to a ‘1’.
6. For “00” data pattern at 25°C.
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D a t a S h e e t
Figure 19.1 SPI Mode 0 (0,0) Input Timing
tCS
CS#
SCK
SI
tCSH
tCSS
tCSS
tCSH
tSU:DAT
tCRT
tHD:DAT
tCFT
MSB IN
LSB IN
Hi-Z
SO
Figure 19.2 SPI Mode 0 (0,0) Output Timing
CS#
tWH
SCK
tV
tWL
tDIS
tV
tHO
tHO
SO
LSB OUT
44
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Figure 19.3 HOLD# Timing
CS#
tHC
tHD
tCH
SCK
SO
tCD
tHZ
tLZ
SI
HOLD#
Figure 19.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1
WP#/ACC
tWPS
tWPH
CS#
SCK
SI
Hi-Z
SO
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D a t a S h e e t
20. Physical Dimensions
20.1 SO3 016 wide — 16-pin Plastic Small Outline Package (300-mil Body Width)
46
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20.2 WNF008 — WSON 8-contact (6 x 8 mm) No-Lead Package
NOTES:
1. DIMENSIONING AND TOLERANCING CONFORMS TO
ASME Y14.5M - 1994.
PACKAGE
WNF008
2. ALL DIMENSIONS ARE IN MILLMETERS.
3. N IS THE TOTAL NUMBER OF TERMINALS.
SYMBOL
MIN
NOM
1.27 BSC.
8
MAX
NOTE
e
N
4
DIMENSION “b” APPLIES TO METALLIZED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL
TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE
OTHER END OF THE TERMINAL, THE DIMENSION “b”
SHOULD NT BE MEASURED IN THAT RADIUS AREA.
3
5
ND
L
4
0.45
0.35
4.70
5.70
0.50
0.55
0.45
4.90
5.90
b
0.40
4
5
ND REFER TO THE NUMBER OF TERMINALS ON D SIDE.
D2
E2
D
4.80
6. MAX. PACKAGE WARPAGE IS 0.05mm.
5.80
7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS.
6.00 BSC
8.00 BSC
0.75
8
9
PIN #1 ID ON TOP WILL BE LASER MARKED.
E
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED
HEAT SINK SLUG AS WELL AS THE TERMINALS.
A
0.70
0.00
0.80
0.05
A1
K
0.02
10 A MAXIMUM 0.15mm PULL BACK (L1) MAY BE PRESENT.
0.20 MIN.
---
L1
0.00
0.15
10
g1015 \ 16-038.30 \ 07.21.11
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21. Revision History
Section
Description
Revision 01 (January 12, 2007)
Initial release
Revision 02 (March 13, 2007)
Distinctive Characteristics
Changed standby mode current
S25FL128P Sector Address Table
(Uniform 64 KB sector)
Corrected addresses for sectors 0 and 32
Parallel Mode (for 16-pin SO package
only)
Added last sentence in section
Read Status Register (RDSR: 05h)
Page Program (PP: 02h)
Separated status register bit descriptions into an additional subsection
Modified Parallel Page Program (PP) Instruction Sequence figure to match format of other parallel
mode figures
Command Definitions
Changed code for Bulk Erase (BE) 256 KB product in table
Read Manufacturer and Device ID
(READ_ID: 90h)
Corrected SI and CLK in Parallel Read_ID Instruction Sequence figure
Absolute Maximum Ratings
DC Characteristics
Added overshoot and undershoot information
Changed maximum specifications for ICC1 (parallel mode), ISB, and IDP
Revision 03 (April 24, 2007)
Ordering Information
Changed Valid Combinations table
Revision 04 (July 2, 2007)
Device Operations
Added a sentence to Byte or Page programming
Added a sentence
Parallel Mode
(for 16-pin SO package only)
Revision 05 (November 4, 2008)
Ordering Information
Added Tray package type option
Added note 6
AC Characteristics
Modified Page Programming Time
Revision 06 (December 8, 2008)
Global
The data sheet went from a “Preliminary” designation to full production.
Revision 07 (May 26, 2009)
Table: Power-Up Timing Characteristics Modified table
Figure: Power-down and Voltage Drop
Revision 08 (September 8, 2009)
AC Characteristics
Added figure
Changed tCS CS# High Time minimum (serial) from 100 to 50 ns
Revision 09 (December 8, 2011)
Connection Diagrams
Added note to WSON package
Updated the tPU (max) value
Power-Up / Power-Down Voltage and
Timing Table
AC Characteristics Table
Physical Dimensions
Revision 10 (May 16, 2012)
Global
Updated the value of tEP
Updated the package outline drawing for packages SO3 016 and WNF008
Added text for recommending FL128S as migration device
48
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2007-2012 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™ and
combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used
are for informational purposes only and may be trademarks of their respective owners.
May 16, 2012 S25FL128P_00_10
S25FL128P
49
相关型号：
S25FL128P_12
128 Megabit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Bus
SPANSION
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