S25FL129P0XNFI003 [SPANSION]
Flash, 16MX8, PDSO8, 6 X 8 MM, LEAD FREE, PLASTIC, WSON-8;
| 型号： | S25FL129P0XNFI003 |
| 厂家： | 
SPANSION |
| 描述： | Flash, 16MX8, PDSO8, 6 X 8 MM, LEAD FREE, PLASTIC, WSON-8 光电二极管 |
| 文件： | 总69页 (文件大小：1095K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S25FL129P
128-Mbit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus
Data Sheet
S25FL129P Cover Sheet
This product is not recommended for new and current designs. For new and current designs,
S25FL128S supersedes S25FL129P. This is the factory-recommended migration path. Please refer to
the S25FL128S data sheet for specifications and ordering information.
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S25FL129P_00
Revision 09
Issue Date January 30, 2013
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or V range. Changes may also include those needed to clarify a
IO
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S25FL129P
S25FL129P_00_09 January 30, 2013
S25FL129P
128-Mbit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus
Data Sheet
This product is not recommended for new and current designs. For new and current designs, S25FL128S
supersedes S25FL129P. This is the factory-recommended migration path. Please refer to the S25FL128S
data sheet for specifications and ordering information.
Distinctive Characteristics
One time programmable (OTP) area for permanent, secure
Architectural Advantages
Single power supply operation
identification; can be programmed and locked at the factory
or by the customer
– Full voltage range: 2.7 to 3.6V read and write operations
CFI (Common Flash Interface) compliant: allows host system
Memory architecture
to identify and accommodate multiple flash devices
– Uniform 64 KB sectors
Process technology
– Top or bottom parameter block (Two 64-KB sectors broken
down into sixteen 4-KB sub-sectors each)
– Manufactured on 0.09 µm MirrorBit® process technology
Package option
– Uniform 256 KB sectors (no 4-KB sub-sectors)
– Industry Standard Pinouts
– 256-byte page size
– 16-pin SO package (300 mils)
– Backward compatible with the S25FL128P (uniform 256 KB sector)
device
– 8-contact WSON package (6 x 8 mm)
– 24-ball BGA (6 x 8 mm) package, 5 x 5 pin configuration
– 24-ball BGA (6 x 8 mm) package, 6 x 4 pin configuration
Program
– Page Program (up to 256 bytes) in 1.5 ms (typical)
– Program operations are on a page by page basis
– Accelerated programming mode via 9V W#/ACC pin
– Quad Page Programming
Performance Characteristics
Speed
– Normal READ (Serial): 40 MHz clock rate
– FAST_READ (Serial): 104 MHz clock rate (maximum)
– DUAL I/O FAST_READ: 80 MHz clock rate or
20 MB/s effective data rate
Erase
– Bulk erase function
– Sector erase (SE) command (D8h) for 64 KB and 256 KB sectors
– Sub-sector erase (P4E) command (20h) for 4 KB sectors
(for uniform 64-KB sector device only)
– QUAD I/O FAST_READ: 80 MHz clock rate or
40 MB/s effective data rate
– Sub-sector erase (P8E) command (40h) for 8 KB sectors
(for uniform 64-KB sector device only)
Power saving standby mode
– Standby Mode 80 µA (typical)
Cycling endurance
– 100,000 cycles per sector typical
Data retention
– Deep Power-Down Mode 3 µA (typical)
Memory Protection Features
– 20 years typical
Memory protection
Device ID
– W#/ACC pin works in conjunction with Status Register Bits to
protect specified memory areas
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward
compatibility
– Status Register Block Protection bits (BP2, BP1, BP0) in status
Publication Number S25FL129P_00
Revision 09
Issue Date January 30, 2013
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro-
duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com-
binations offered may occur.
D a t a S h e e t
General Description
The S25FL129P is a 3.0 Volt (2.7V to 3.6V), single-power-supply Flash memory device. The device is offered
in two configurations: 256 uniform 64 KB sectors with the two (Top or Bottom) 64 KB sectors further split up
into thirty-two 4 KB sub sectors, or 64 uniform 256 KB sectors. The S25FL129P device is backward
compatible with the S25FL128P (uniform 256 KB sector) device.
The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are
designed to be programmed in-system with the standard system 3.0-volt V supply.
CC
The S25FL129P device adds the following high-performance features using 5 new instructions:
Dual Output Read using both SI and SO pins as output pins at a clock rate of up to 80 MHz
Quad Output Read using SI, SO, W#/ACC and HOLD# pins as output pins at a clock rate of up to 80 MHz
Dual I/O High Performance Read using both SI and SO pins as input and output pins at a clock rate of up
to 80 MHz
Quad I/O High Performance Read using SI, SO, W#/ACC and HOLD# pins as input and output pins at a
clock rate of up to 80 MHz
Quad Page Programming using SI, SO, W#/ACC and HOLD# pins as input pins to program data at a clock
rate of up to 80 MHz
The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device
supports Sector Erase and Bulk Erase commands.
Each device requires only a 3.0-volt power supply (2.7V to 3.6V) for both read and write functions. Internally
generated and regulated voltages are provided for the program operations. This device requires a high
voltage supply to the W#/ACC pin to enable the Accelerated Programming mode.
The S25FL129P device also offers a One-Time Programmable area (OTP) of up to 128-bits (16 bytes) for
permanent secure identification and an additional 490 bytes of OTP space for other use. This OTP area can
be programmed or read using the OTPP or OTPR instructions.
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S25FL129P
S25FL129P_00_09 January 30, 2013
D a t a S h e e t
Table of Contents
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.
2.
3.
4.
5.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.
7.
Spansion SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Byte or Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Quad Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Dual and Quad I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Sector Erase / Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Monitoring Write Operations Using the Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.10 Hold Mode (HOLD#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.11 Accelerated Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.
9.
Sector Address Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Dual Output Read Mode (DOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Quad Output Read Mode (QOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DUAL I/O High Performance Read Mode (DIOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Quad I/O High Performance Read Mode (QIOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Read Identification (RDID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Read-ID (READ_ID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.10 Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.11 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.12 Read Configuration Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.13 Write Registers (WRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.14 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.15 QUAD Page Program (QPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.16 Parameter Sector Erase (P4E, P8E) (only applicable for the uniform 64 KB sector device). 45
9.17 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.18 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.19 Deep Power-Down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.20 Release from Deep Power-Down (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.21 Clear Status Register (CLSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.22 OTP Program (OTPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.23 Read OTP Data Bytes (OTPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10. OTP Regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1 Programming OTP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2 Reading OTP Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.3 Locking OTP Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11. Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12. Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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S25FL129P
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D a t a S h e e t
13. Program Acceleration via W#/ACC Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
14.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
15. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
16. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
17. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
18. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
18.1 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
19. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
19.1 SO3 016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width) . . . . . . . . . . 63
19.2 WSON 8-contact (6 x 8 mm) No-Lead Package (WNF008) . . . . . . . . . . . . . . . . . . . . . . . . . 64
19.3 FAB024 — 24-ball Ball Grid Array (6 x 8 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
19.4 FAC024 — 24-ball Ball Grid Array (6 x 8 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
20. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6
S25FL129P
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D a t a S h e e t
Figures
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 6.1
Figure 6.2
Figure 7.1
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8-contact WSON Package (6 x 8 mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 x 8 mm 24-ball BGA Package, 5 x 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 x 8 mm 24-ball BGA Package, 6 x 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Hold Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Data Bytes (READ) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Data Bytes at Higher Speed (FAST_READ) Command Sequence . . . . . . . . . . . . . . . 27
Dual Output Read Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Quad Output Read Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DUAL I/O High Performance Read Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Continuous Dual I/O High Performance Read Instruction Sequence . . . . . . . . . . . . . . . . . . 31
QUAD I/O High Performance Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Continuous QUAD I/O High Performance Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . 33
Read Identification (RDID) Command Sequence and Data-Out Sequence . . . . . . . . . . . . . 34
Figure 9.10 Read-ID (RDID) Command Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 9.11 Write Enable (WREN) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 9.12 Write Disable (WRDI) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 9.13 Read Status Register (RDSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 9.14 Read Configuration Register (RCR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 9.15 Write Registers (WRR) Instruction Sequence – 8 data bits. . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 9.16 Write Registers (WRR) Instruction Sequence – 16 data bits. . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 9.17 Page Program (PP) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 9.18 QUAD Page Program Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 9.19 Parameter Sector Erase (P4E, P8E) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 9.20 Sector Erase (SE) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 9.21 Bulk Erase (BE) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 9.22 Deep Power-Down (DP) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 9.23 Release from Deep Power-Down (RES) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . 49
Figure 9.24 Release from Deep Power-Down and RES Command Sequence . . . . . . . . . . . . . . . . . . . . 50
Figure 9.25 Clear Status Register (CLSR) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 9.26 OTP Program Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 9.27 Read OTP Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 10.1 OTP Memory Map - Part 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 10.2 OTP Memory Map - Part 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 11.1 Power-Up Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 11.2 Power-down and Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 13.1 ACC Program Acceleration Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 14.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 14.2 Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 17.1 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 18.1 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 18.2 SPI Mode 0 (0,0) Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 18.3 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 18.4 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 18.5 Write Protect Setup and Hold Timing during WRR when SRWD = 1 . . . . . . . . . . . . . . . . . . 62
January 30, 2013 S25FL129P_00_09
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D a t a S h e e t
Tables
Table 5.1
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 8.1
Table 8.2
Table 8.3
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.6
Table 9.7
Table 9.8
Table 9.9
Table 11.1
Table 13.1
Table 15.1
Table 16.1
Table 17.1
S25FL129P Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Configuration Register Table (Uniform 64 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Configuration Register Table (Uniform 256 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
TBPROT = 0 (Starts Protection from TOP of Array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
TBPROT = 1 (Starts Protection from BOTTOM of Array) . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
S25FL129P Sector Address Table (Uniform 256 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . .19
S25FL129P Sector Address Table (Uniform 64 KB sector, TBPARM=0) . . . . . . . . . . . . . . . .20
S25FL129P Sector Address Table (Uniform 64 KB sector, TBPARM=1) . . . . . . . . . . . . . . . .22
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Manufacturer and Device Identification - RDID (9Fh): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Product Group CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Product Group CFI System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Product Group CFI Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Product Group CFI Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . .36
READ_ID Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
S25FL129P Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Power-Up / Power-Down Voltage and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
ACC Program Acceleration Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
8
S25FL129P
S25FL129P_00_09 January 30, 2013
D a t a S h e e t
1. Block Diagram
SRAM
PS
X
D
E
C
Array - L
Array - R
Logic
RD
DATA PATH
IO
2. Connection Diagrams
Figure 2.1 16-pin Plastic Small Outline Package (SO)
16
15
14
SCK
1
2
3
HOLD#/IO3
VCC
SI/IO0
DNC
DNC
DNC
DNC
DNC
13
4
5
DNC
DNC
12
6
11
DNC
GND
CS#
7
10
9
SO/IO1
8
W#/ACC/IO2
Note
DNC = Do Not Connect (Reserved for future use)
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D a t a S h e e t
Figure 2.2 8-contact WSON Package (6 x 8 mm)
CS#
SO/IO1
VCC
8
7
6
1
2
HOLD#/IO3
WSON
W#/ACC/IO2
GND
3
4
SCK
SI/IO0
5
Note
There is an exposed central pad on the underside of the WSON package. This should not be connected to any voltage or signal line on the
PCB. Connecting the central pad to GND (VSS) is possible, provided PCB routing ensures 0mV difference between voltage at the WSON
GND (VSS) lead and the central exposed pad.
Figure 2.3 6 x 8 mm 24-ball BGA Package, 5 x 5 Pin Configuration
1
2
3
4
5
A
B
C
D
E
NC
NC
NC
NC
NC
NC
NC
NC
NC
SCK
CS#
GND
VCC
NC W#/ACC/IO2 NC
SO/IO1 SI/IO0 HOLD#/IO3 NC
NC
NC
NC
NC
Figure 2.4 6 x 8 mm 24-ball BGA Package, 6 x 4 Pin Configuration
A1
A2
NC
A3
NC
A4
NC
B4
NC
B2
B3
B1
NC
C1
NC
D1
SCK
C2
GND
C3
VCC
C4
CS#
D2
NC W#/ACC/IO2
D3 D4
SI/IO0 HOLD#/IO3
NC
E1
SO/IO1
E2
E3
E4
NC
NC
NC
NC
F1
F2
F3
F4
NC
NC
NC
NC
10
S25FL129P
S25FL129P_00_09 January 30, 2013
D a t a S h e e t
3. Input/Output Descriptions
Signal
I/O
Description
Serial Data Output: Transfers data serially out of the device on the falling edge of SCK.
Functions as an I/O pin in Dual and Quad I/O, and Quad Page Program modes.
SO/IO1
I/O
Serial Data Input: Transfers data serially into the device. Device latches commands,
addresses, and program data on SI on the rising edge of SCK. Functions as an I/O pin in Dual
and Quad I/O mode.
SI/IO0
SCK
I/O
Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on
rising edge of SCK. Triggers output on SO after the falling edge of SCK.
Input
Chip Select: Places device in active power mode when driven low. Deselects device and places
SO at high impedance when high. After power-up, device requires a falling edge on CS# before
any command is written. Device is in standby mode when a program, erase, or Write Status
Register operation is not in progress.
CS#
Input
Hold: Pauses any serial communication with the device without deselecting it. When driven low,
SO is at high impedance, and all input at SI and SCK are ignored. Requires that CS# also be
driven low. Functions as an I/O pin in Quad I/O mode.
HOLD#/IO3
I/O
I/O
Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When
driven low, prevents any program or erase command from altering the data in the protected
memory area. Functions as an I/O pin in Quad I/O mode.
W#/ACC/IO2
VCC
Input Supply Voltage
Input Ground
GND
4. Logic Symbol
V
CC
SO/IO1
SI/IO0
SCK
CS#
W#/ACC/IO2
HOLD#/IO3
GND
January 30, 2013 S25FL129P_00_09
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D a t a S h e e t
5. Ordering Information
This product is not recommended for new and current designs. For new and current designs, S25FL128S
supersedes S25FL129P. This is the factory-recommended migration path. Please refer to the S25FL128S
data sheet for specifications and ordering information.
The ordering part number is formed by a valid combination of the following:
S25FL
129
P
0X
M
F
I
00
1
Packing Type (Note 1)
0
1
3
=
=
=
Tray
Tube
13” Tape and Reel
Model Number (Additional Ordering Options)
31
30
21
20
01
00
=
=
=
=
=
=
6x4 pin configuration BGA package, Uniform 256 KB sectors
6x4 pin configuration BGA package, Uniform 64 KB sectors
5x5 pin configuration BGA package, Uniform 256 KB sectors
5x5 pin configuration BGA package, Uniform 64 KB sectors
SO/WSON package, Uniform 256 KB sectors
SO/WSON package, Uniform 64 KB sectors
Temperature Range
I
V
=
=
Industrial (–40°C to + 85°C)
Automotive In-Cabin (-40*C to + 105*C)
Package Materials
F
H
=
=
Lead (Pb)-free
Low-Halogen, Lead (Pb)-free
Package Type
M
N
B
=
=
=
16-pin SO package
8-contact WSON package
24-ball BGA 6 x 8 mm package, 1.00 mm pitch
Speed
0X
=
104 MHz
Device Technology
P
=
0.09 µm MirrorBit® Process Technology
Density
129
=
128 Mbit
Device Family
S25FL
Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory
5.1
Valid Combinations
Table 5.1 lists the valid combinations configurations planned to be supported in volume for this device.
Table 5.1 S25FL129P Valid Combinations Table
S25FL129P Valid Combinations
Base Ordering
Part Number
Package and
Temperature
Model
Number
Speed Option
Packing Type
Package Marking
FL129P + (Temp) + F
FL129P + (Temp) + FL
FL129P + (Temp) + F
FL129P + (Temp) + FL
00
MFI, NFI
0, 1, 3
MFV , NFV
01
S25FL129P
0X
20, 30
21, 31
BHI
0, 3
BHV
Note
1. Package Marking omits the leading “S25” and speed, package and model number.
12
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S25FL129P_00_09 January 30, 2013
D a t a S h e e t
6. Spansion SPI Modes
A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices:
CPOL = 0, CPHA = 0 (Mode 0)
CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for
both modes.
When the bus master is in standby mode, SCK is as shown in Figure 6.2 for each of the two modes:
SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)
SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3)
Figure 6.1 Bus Master and Memory Devices on the SPI Bus
SO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SI
SCK
SCK SO SI
SCK SO SI
SCK SO SI
Bus Master
SPI Memory
SPI Memory
SPI Memory
Device
Device
Device
CS3 CS2 CS1
CS#
HOLD#
CS#
HOLD#
CS#
HOLD#
W#/ACC
W#/ACC
W#/ACC
Note
The Write Protect/Accelerated Programming (W#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0)
as appropriate.
Figure 6.2 SPI Modes Supported
CS#
CPOL CPHA
Mode 0
SCK
0
0
1
1
Mode 3
SCK
SI
MSB
SO
MSB
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D a t a S h e e t
7. Device Operations
All Spansion SPI devices accept and output data in bytes (8 bits at a time). The SPI device is a slave device
that supports an inactive clock while CS# is held low.
7.1
Byte or Page Programming
Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program
(PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up
to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation.
Programming means that bits can either be left at 0, or programmed from 1 to 0. Changing bits from 0 to 1
requires an erase operation.
7.2
7.3
Quad Page Programming
The Quad Page Program (QPP) instruction allows up to 256 bytes of data to be programmed using 4 pins as
inputs at the same time, thus effectively quadrupling the data transfer rate, compared to the Page Program
(PP) instruction. The Write Enable Latch (WEL) bit must be set to a 1 using the Write Enable (WREN)
command prior to issuing the QPP command.
Dual and Quad I/O Mode
The S25FL129P device supports Dual and Quad I/O operation when using the Dual/Quad Output Read Mode
and the Dual/Quad I/O High Performance Mode instructions. Using the Dual or Quad I/O instructions allows
data to be transferred to or from the device at two to four times the rate of standard SPI devices. When
operating in the Dual or Quad I/O High Performance Mode (BBh or EBh instructions), data can be read at fast
speed using two or four data bits at a time, and the 3-byte address can be input two or four address bits at a
time.
7.4
Sector Erase / Bulk Erase
The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array
to 1. While bits can be individually programmed from 1 to 0, erasing bits from 0 to 1 must be done on a sector-
wide (SE) or array-wide (BE) level. In addition to the 64-KB Sector Erase (SE), the S25FL129P device also
offers 4-KB Parameter Sector Erase (P4E) and 8-KB Parameter Sector Erase (P8E) (only applicable for the
uniform 64 KB sector device).
7.5
7.6
Monitoring Write Operations Using the Status Register
The host system can determine when a Write Register, program, or erase operation is complete by
monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command
provides the state of the WIP bit. In addition, the S25FL129P device offers two additional bits in the Status
Register (P_ERR, E_ERR) to indicate whether a Program or Erase operation was a success or failure.
Active Power and Standby Power Modes
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the
device is disabled, but may still be in the Active Power mode until all program, erase, and Write Registers
operations have completed. The device then goes into the Standby Power mode, and power consumption
drops to I . The Deep Power-Down (DP) command provides additional data protection against inadvertent
SB
signals. After writing the DP command, the device ignores any further program or erase commands, and
reduces its power consumption to I
.
DP
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S25FL129P_00_09 January 30, 2013
D a t a S h e e t
7.7
Status Register
The Status Register contains the status and control bits that can be read or set by specific commands (see
Table 9.1 on page 25). These bits configure different protection configurations and supply information of
operation of the device. (for details see Table 9.8, S25FL129P Status Register on page 39):
Write In Progress (WIP): Indicates whether the device is performing a Write Registers, program or erase
operation.
Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch.
Block Protect (BP2, BP1, BP0): Non-volatile bits that define memory area to be software-protected
against program and erase commands.
Erase Error (E_ERR): The Erase Error Bit is used as an Erase operation success and failure check.
Program Error (P_ERR): The Program Error Bit is used as an program operation success and failure check.
Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit
is set to 1 and the W#/ACC input is driven low. In this mode, the non-volatile bits of the Status Register
(SRWD, BP2, BP1, BP0) become read-only bits.
7.8
Configuration Register
The Configuration Register contains the control bits that can be read or set by specific commands. These bits
configure different configurations and security features of the device.
The FREEZE bit locks the BP2-0 bits in Status Register and the TBPROT and TBPARM bits in the
Configuration Register. Note that once the FREEZE bit has been set to ‘1’, then it cannot be cleared to ‘0’
until a power-on-reset is executed. As long as the FREEZE bit is set to ‘0’, then the other bits of the
Configuration Register, including FREEZE bit, can be written to.
The QUAD bit is non-volatile and sets the pin out of the device to Quad mode; that is, W#/ACC becomes
IO2 and HOLD# becomes IO3. The instructions for Serial, Dual Output, and Dual I/O reads function as
normal. The W#/ACC and HOLD# functionality does not work when the device is set in Quad mode.
The TBPARM bit defines the logical location of the 4 KB parameter sectors. The parameter sectors consist
of thirty two 4 KB sectors. All sectors other than the parameter sectors are defined to be 64-KB uniform in
size. When TBPARM is set to a ‘1’, the 4 KB parameter sectors starts at the top of the array. When
TBPARM is set to a ‘0’, the 4 KB parameter sectors starts at the bottom of the array. Note that once this bit
is set to a '1', it cannot be changed back to '0'. (This function is not applicable to the uniform 256 KB sector
product.) The desired state of TBPARM must be selected during the initial configuration of the device
during system manufacture; before the first program or erase operation on the main Flash array. TBPARM
must not be programmed after programming or erasing is done in the main Flash array.
The BPNV bit defines whether or not the BP2-0 bits in the Status Register are volatile or non-volatile.
When BPNV is set to a ‘1’, the BP2-0 bits in the Status Register are volatile and will be reset to binary 111
after power on reset. When BPNV is set to a ‘0’, the BP2-0 bits in the Status Register are non-volatile. Note
that once this bit is set to a '1', it cannot be changed back to '0'.
The TBPROT bit defines the operation of the block protection bits BP2, BP1, and BP0 in the Status
Register. When TBPROT is set to a ‘0’, then the block protection is defined to start from the top of the array.
When TBPROT is set to a ‘1’, then the block protection is defined to start from the bottom of the array. Note
that once this bit is set to a '1', it cannot be changed back to '0'. The desired state of TBPROT must be
selected during the initial configuration of the device during system manufacture; before the first program
or erase operation on the main Flash array. TBPROT must not be programmed after programming or
erasing is done in the main Flash array.
January 30, 2013 S25FL129P_00_09
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15
D a t a S h e e t
Note: It is suggested that the Block Protection and Parameter sectors not be set to the same area of the
array; otherwise, the user cannot utilize the Parameter sectors if they are protected. The following matrix
shows the recommended settings.
TBPARM
TBPROT
Array Overview
Parameter Sectors - Bottom
BP Protection - Top (default)
0
0
0
1
1
0
Not recommended (Parameters and BP Protection are both Bottom)
Not recommended (parameters and BP Protection are both Top)
Parameter Sectors - Top of Array (high address)
BP Protection - Bottom of Array (low address)
1
1
Table 7.1 Configuration Register Table (Uniform 64 KB sector)
Bit
7
Bit Name
Bit Function
Description
NA
NA
-
-
Not Used
Not Used
6
1 = Bottom Array (low address)
0 = Top Array (high address) (Default)
5
4
3
TBPROT
NA
Configures start of block protection
-
Do Not Use
1 = Volatile
0 = Non-volatile (Default)
BPNV
Configures BP2-0 bits in the Status Register
1 = Top Array (high address)
0 = Bottom Array (low address) (Default)
2
1
0
TBPARM
QUAD
Configures Parameter sector location
Puts the device into Quad I/O mode
Locks BP2-0 bits in the Status Register
1 = Quad I/O
0 = Dual or Serial I/O (Default)
1 = Enabled
0 = Disabled (Default)
FREEZE
Note
(Default) indicates the value of each Configuration Register bit set upon initial factory shipment.
Table 7.2 Configuration Register Table (Uniform 256 KB sector)
Bit
7
Bit Name
N/A
Bit Function
Description
-
-
Not Used
Not Used
6
N/A
1 = Bottom Array (low address)
0 = Top Array (high address) (Default)
5
4
3
2
1
TBPROT
N/A
Configures start of block protection
-
Do Not Use
1 = Volatile
0 = Non-volatile (Default)
BPNV
N/A
Configures BP2-0 bits in the Status Register
-
Do not Use
1 = Quad I/O
0 = Dual or Serial I/O (Default)
QUAD
Puts the device into Quad I/O mode
1 = Enabled
0 = Disabled (Default)
0
FREEZE
Locks BP2-0 bits in the Status Register
Note
1. (Default) indicates the value of each Configuration Register bit set upon initial factory shipment.
16
S25FL129P
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D a t a S h e e t
7.9
Data Protection Modes
Spansion SPI Flash memory devices provide the following data protection methods:
The Write Enable (WREN) command: Must be written prior to any command that modifies data. The
WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up
or after the device completes the following commands:
– Page Program (PP)
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Register (WRR)
– Parameter 4 KB Sector Erase (P4E)
– Parameter 8 KB Sector Erase (P8E)
– Quad Page Programming (QPP)
– OTP Byte Programming (OTPP)
Software Protected Mode (SPM): The Block Protect BP2, BP1, BP0 bits define the section of the memory
array that can be read but not programmed or erased. Table 7.3 and Table 7.4 shows the sizes and
address ranges of protected areas that are defined by Status Register bits BP2:BP0.
Hardware Protected Mode (HPM): The Write Protect (W#/ACC) input and the Status Register Write
Disable (SRWD) bit together provide write protection.
Clock Pulse Count: The device verifies that all program, erase, and Write Register commands consist of
a clock pulse count that is a multiple of eight before executing them.
Table 7.3 TBPROT = 0 (Starts Protection from TOP of Array)
Status Register Block
Memory Array
Unprotected
Sectors
Protected Sectors
Protected
Address Range
Uniform
64 KB
Uniform
256 KB
Unprotected
Address Range
Uniform
64 KB
Uniform Protected Portion of
BP2
BP1
0
BP0
0
256 KB
Total Memory Area
0
0
0
0
1
1
1
1
None
0
0
000000h - FFFFFFh SA255:SA0 SA63:SA0
000000h - FBFFFFh SA251:SA0 SA62:SA0
0
0
1
FC0000h - FFFFFFh (4) SA255:SA252
F80000h - FFFFFFh (8) SA255:SA248
(1) SA63
1/64
1/32
1/16
1/8
1
0
(2)SA63:SA62 000000h - F7FFFFh SA247:SA0 SA61:SA0
1
1
F00000h - FFFFFFh (16) SA255:SA240 (4)SA63:SA60 000000h - EFFFFFh SA239:SA0 SA59:SA0
E00000h - FFFFFFh (32) SA255:SA224 (8)SA63:SA56 000000h - DFFFFFh SA223:SA0 SA55:SA0
C00000h - FFFFFFh (64)SA255:SA192 (16)SA63:SA48 000000h - BFFFFFh SA191:SA0 SA47:SA0
800000h - FFFFFFh (128)SA255:SA128 (32)SA63:SA32 000000h - 7FFFFFh SA127:SA0 SA31:SA0
0
0
0
1
1/4
1
0
1/2
1
1
000000h - FFFFFFh
(256)SA255:SA0
(64)SA63:SA0
None
None
None
All
Table 7.4 TBPROT = 1 (Starts Protection from BOTTOM of Array)
Status Register Block
Memory Array
Unprotected
Sectors
Protected Sectors
Protected
Address Range
Uniform
64 KB
Uniform
256 KB
Unprotected
Address Range
Uniform
64 KB
Uniform
256 KB
Protected Portion of
Total Memory Area
BP2
0
BP1
0
BP0
0
None
0
0
000000h - FFFFFFh SA0:SA255
040000h - FFFFFFh SA4:SA255
080000h - FFFFFFh SA8:SA255
SA0:SA63
SA1:SA63
SA2:SA63
0
0
0
1
000000h - 03FFFFh
000000h - 07FFFFh
000000h - 0FFFFFh
000000h - 1FFFFFh
000000h - 3FFFFFh
(4) SA0:SA3
(8) SA0:SA7
(16)SA0:SA15
(32)SA0:SA31
(64)SA0:SA63
(1) SA0
1/64
1/32
1/16
1/8
0
1
0
(2)SA0:SA1
(4)SA0:SA3
(8)SA0:SA7
0
1
1
100000h - FFFFFFh SA16:SA255 SA4:SA63
200000h - FFFFFFh SA32:SA255 SA8:SA63
1
0
0
1
0
1
(16)SA0:SA15 400000h - FFFFFFh SA64:SA255 SA16:SA63
1/4
1
1
0
000000h - 7FFFFFh (128)SA0:SA127 (32)SA0:SA31 800000h - FFFFFFh SA128:255
000000h - FFFFFFh (256)SA0:SA255 (64)SA0:SA63 None None
SA32:SA63
None
1/2
1
1
1
All
January 30, 2013 S25FL129P_00_09
S25FL129P
17
D a t a S h e e t
7.10 Hold Mode (HOLD#)
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write
Registers, program or erase operation that is currently in progress.
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see Figure 7.1, standard use). If the
falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling edge of
SCK (non-standard use).
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-
standard use) See Figure 7.1.
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the
Hold mode.
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,
followed by driving CS# low.
Note: The HOLD Mode feature is disabled during Quad I/O Mode.
Figure 7.1 Hold Mode Operation
SCK
HOLD#
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
7.11 Accelerated Programming Operation
The device offers accelerated program operations through the ACC function. This function is primarily
intended to allow faster manufacturing throughput at the factory. If the system asserts V on this pin, the
HH
device uses the higher voltage on the pin to reduce the time required for program operations. Removing V
HH
from the W#/ACC pin returns the device to normal operation. Note that the W#/ACC pin must not be at V
HH
for operations other than accelerated programming, or device damage may result. In addition, the W#/ACC
pin must not be left floating or unconnected; inconsistent behavior of the device may result.
Note: The ACC function is disabled during Quad I/O Mode.
18
S25FL129P
S25FL129P_00_09 January 30, 2013
D a t a S h e e t
8. Sector Address Table
The Sector Address tables show the size of the memory array, sectors, and pages. The device uses pages to
cache the program data before the data is programmed into the memory array. Each page or byte can be
individually programmed (bits are changed from 1 to 0). The data is erased (bits are changed from 0 to 1) on
a sub-sector, sector- or device-wide basis using the P4E/P8E (applicable only for the uniform 64 KB sector
device), SE or BE commands. Table 8.1 to Table 8.3 show the starting and ending address for each sector.
The complete set of sectors comprises the memory array of the Flash device.
Table 8.1 S25FL129P Sector Address Table (Uniform 256 KB sector)
Address Range
Start Address
Address Range
Start Address
Sector
Sector
End Address
FFFFFFh
FBFFFFh
F7FFFFh
F3FFFFh
EFFFFFh
EBFFFFh
E7FFFFh
E3FFFFh
DFFFFFh
DBFFFFh
D7FFFFh
D3FFFFh
CFFFFFh
CBFFFFh
C7FFFFh
C3FFFFh
BFFFFFh
BBFFFFh
B7FFFFh
B3FFFFh
AFFFFFh
ABFFFFh
A7FFFFh
A3FFFFh
9FFFFFh
9BFFFFh
97FFFFh
93FFFFh
8FFFFFh
8BFFFFh
87FFFFh
83FFFFh
End Address
7FFFFFh
7BFFFFh
77FFFFh
73FFFFh
6FFFFFh
6BFFFFh
67FFFFh
63FFFFh
5FFFFFh
5BFFFFh
57FFFFh
53FFFFh
4FFFFFh
4BFFFFh
47FFFFh
43FFFFh
3FFFFFh
3BFFFFh
37FFFFh
33FFFFh
2FFFFFh
2BFFFFh
27FFFFh
23FFFFh
1FFFFFh
1BFFFFh
17FFFFh
13FFFFh
0FFFFFh
0BFFFFh
07FFFFh
03FFFFh
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
FC0000h
F80000h
F40000h
F00000h
EC0000h
E80000h
E40000h
E00000h
DC0000h
D80000h
D40000h
D00000h
CC0000h
C80000h
C40000h
C00000h
BC0000h
B80000h
B40000h
B00000h
AC0000h
A80000h
A40000h
A00000h
9C0000h
980000h
940000h
900000h
8C0000h
880000h
840000h
800000h
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
7C0000h
780000h
740000h
700000h
6C0000h
680000h
640000h
600000h
5C0000h
580000h
540000h
500000h
4C0000h
480000h
440000h
400000h
3C0000h
380000h
340000h
300000h
2C0000h
280000h
240000h
200000h
1C0000h
180000h
140000h
100000h
0C0000h
080000h
040000h
000000h
8
7
6
5
4
3
2
1
0
January 30, 2013 S25FL129P_00_09
S25FL129P
19
D a t a S h e e t
Table 8.2 S25FL129P Sector Address Table (Uniform 64 KB sector, TBPARM=0) (Sheet 1 of 2)
Address Range
Start Address
Address Range
Start Address
Address Range
Start Address
Sector
Sector
Sector
End Address
6CFFFFh
6BFFFFh
6AFFFFh
69FFFFh
68FFFFh
67FFFFh
66FFFFh
65FFFFh
64FFFFh
63FFFFh
62FFFFh
61FFFFh
60FFFFh
5FFFFFh
5EFFFFh
5DFFFFh
5CFFFFh
5BFFFFh
5AFFFFh
59FFFFh
58FFFFh
57FFFFh
56FFFFh
55FFFFh
54FFFFh
53FFFFh
52FFFFh
51FFFFh
50FFFFh
4FFFFFh
4EFFFFh
4DFFFFh
4CFFFFh
4BFFFFh
4AFFFFh
49FFFFh
48FFFFh
47FFFFh
46FFFFh
45FFFFh
44FFFFh
43FFFFh
42FFFFh
41FFFFh
40FFFFh
3FFFFFh
3EFFFFh
End Address
3DFFFFh
3CFFFFh
3BFFFFh
3AFFFFh
39FFFFh
38FFFFh
37FFFFh
36FFFFh
35FFFFh
34FFFFh
33FFFFh
32FFFFh
31FFFFh
30FFFFh
2FFFFFh
2EFFFFh
2DFFFFh
2CFFFFh
2BFFFFh
2AFFFFh
29FFFFh
28FFFFh
27FFFFh
26FFFFh
25FFFFh
24FFFFh
23FFFFh
22FFFFh
21FFFFh
20FFFFh
1FFFFFh
1EFFFFh
1DFFFFh
1CFFFFh
1BFFFFh
1AFFFFh
19FFFFh
18FFFFh
17FFFFh
16FFFFh
15FFFFh
14FFFFh
13FFFFh
12FFFFh
11FFFFh
10FFFFh
0FFFFFh
End Address
0EFFFFh
0DFFFFh
0CFFFFh
0BFFFFh
0AFFFFh
09FFFFh
08FFFFh
07FFFFh
06FFFFh
05FFFFh
04FFFFh
03FFFFh
02FFFFh
01FFFFh
00FFFFh
01FFFFh
01EFFFh
01DFFFh
01CFFFh
01BFFFh
01AFFFh
019FFFh
018FFFh
017FFFh
016FFFh
015FFFh
014FFFh
013FFFh
012FFFh
011FFFh
010FFFh
00FFFFh
00EFFFh
00DFFFh
00CFFFh
00BFFFh
00AFFFh
009FFFh
008FFFh
007FFFh
006FFFh
005FFFh
004FFFh
003FFFh
002FFFh
001FFFh
000FFFh
SA108
SA107
SA106
SA105
SA104
SA103
SA102
SA101
SA100
SA99
SA98
SA97
SA96
SA95
SA94
SA93
SA92
SA91
SA90
SA89
SA88
SA87
SA86
SA85
SA84
SA83
SA82
SA81
SA80
SA79
SA78
SA77
SA76
SA75
SA74
SA73
SA72
SA71
SA70
SA69
SA68
SA67
SA66
SA65
SA64
SA63
SA62
6C0000h
6B0000h
6A0000h
690000h
680000h
670000h
660000h
650000h
640000h
630000h
620000h
610000h
600000h
5F0000h
5E0000h
5D0000h
5C0000h
5B0000h
5A0000h
590000h
580000h
570000h
560000h
550000h
540000h
530000h
520000h
510000h
500000h
4F0000h
4E0000h
4D0000h
4C0000h
4B0000h
4A0000h
490000h
480000h
470000h
460000h
450000h
440000h
430000h
420000h
410000h
400000h
3F0000h
3E0000h
SA61
SA60
SA59
SA58
SA57
SA56
SA55
SA54
SA53
SA52
SA51
SA50
SA49
SA48
SA47
SA46
SA45
SA44
SA43
SA42
SA41
SA40
SA39
SA38
SA37
SA36
SA35
SA34
SA33
SA32
SA31
SA30
SA29
SA28
SA27
SA26
SA25
SA24
SA23
SA22
SA21
SA20
SA19
SA18
SA17
SA16
SA15
3D0000h
3C0000h
3B0000h
3A0000h
390000h
380000h
370000h
360000h
350000h
340000h
330000h
320000h
310000h
300000h
2F0000h
2E0000h
2D0000h
2C0000h
2B0000h
2A0000h
290000h
280000h
270000h
260000h
250000h
240000h
230000h
220000h
210000h
200000h
1F0000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
0F0000h
SA14
SA13
SA12
SA11
SA10
SA9
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
090000h
080000h
070000h
060000h
050000h
040000h
030000h
020000h
010000h
000000h
01F000h
01E000h
01D000h
01C000h
01B000h
01A000h
019000h
018000h
017000h
016000h
015000h
014000h
013000h
012000h
011000h
010000h
00F000h
00E000h
00D000h
00C000h
00B000h
00A000h
009000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
SS31
SS30
SS29
SS28
SS27
SS26
SS25
SS24
SS23
SS22
SS21
SS20
SS19
SS18
SS17
SS16
SS15
SS14
SS13
SS12
SS11
SS10
SS9
SS8
SS7
SS6
SS5
SS4
SS3
SS2
SS1
SS0
20
S25FL129P
S25FL129P_00_09 January 30, 2013
D a t a S h e e t
Table 8.2 S25FL129P Sector Address Table (Uniform 64 KB sector, TBPARM=0) (Sheet 2 of 2)
Address Range
Start Address
Address Range
Start Address
Address Range
Start Address
Sector
Sector
Sector
End Address
FFFFFFh
FEFFFFh
FDFFFFh
FCFFFFh
FBFFFFh
FAFFFFh
F9FFFFh
F8FFFFh
F7FFFFh
F6FFFFh
F5FFFFh
F4FFFFh
F3FFFFh
F2FFFFh
F1FFFFh
F0FFFFh
EFFFFFh
EEFFFFh
EDFFFFh
ECFFFFh
EBFFFFh
EAFFFFh
E9FFFFh
E8FFFFh
E7FFFFh
E6FFFFh
E5FFFFh
E4FFFFh
E3FFFFh
E2FFFFh
E1FFFFh
E0FFFFh
DFFFFFh
DEFFFFh
DDFFFFh
DCFFFFh
DBFFFFh
DAFFFFh
D9FFFFh
D8FFFFh
D7FFFFh
D6FFFFh
D5FFFFh
D4FFFFh
D3FFFFh
D2FFFFh
D1FFFFh
D0FFFFh
CFFFFFh
End Address
CEFFFFh
CDFFFFh
CCFFFFh
CBFFFFh
CAFFFFh
C9FFFFh
C8FFFFh
C7FFFFh
C6FFFFh
C5FFFFh
C4FFFFh
C3FFFFh
C2FFFFh
C1FFFFh
C0FFFFh
BFFFFFh
BEFFFFh
BDFFFFh
BCFFFFh
BBFFFFh
BAFFFFh
B9FFFFh
B8FFFFh
B7FFFFh
B6FFFFh
B5FFFFh
B4FFFFh
B3FFFFh
B2FFFFh
B1FFFFh
B0FFFFh
AFFFFFh
AEFFFFh
ADFFFFh
ACFFFFh
ABFFFFh
AAFFFFh
A9FFFFh
A8FFFFh
A7FFFFh
A6FFFFh
A5FFFFh
A4FFFFh
A3FFFFh
A2FFFFh
A1FFFFh
A0FFFFh
9FFFFFh
9EFFFFh
End Address
9DFFFFh
9CFFFFh
9BFFFFh
9AFFFFh
99FFFFh
98FFFFh
97FFFFh
96FFFFh
95FFFFh
94FFFFh
93FFFFh
92FFFFh
91FFFFh
90FFFFh
8FFFFFh
8EFFFFh
8DFFFFh
8CFFFFh
8BFFFFh
8AFFFFh
89FFFFh
88FFFFh
87FFFFh
86FFFFh
85FFFFh
84FFFFh
83FFFFh
82FFFFh
81FFFFh
80FFFFh
7FFFFFh
7EFFFFh
7DFFFFh
7CFFFFh
7BFFFFh
7AFFFFh
79FFFFh
78FFFFh
77FFFFh
76FFFFh
75FFFFh
74FFFFh
73FFFFh
72FFFFh
71FFFFh
70FFFFh
6FFFFFh
6EFFFFh
6DFFFFh
SA255
SA254
SA253
SA252
SA251
SA250
SA249
SA248
SA247
SA246
SA245
SA244
SA243
SA242
SA241
SA240
SA239
SA238
SA237
SA236
SA235
SA234
SA233
SA232
SA231
SA230
SA229
SA228
SA227
SA226
SA225
SA224
SA223
SA222
SA221
SA220
SA219
SA218
SA217
SA216
SA215
SA214
SA213
SA212
SA211
SA210
SA209
SA208
SA207
FF0000h
FE0000h
FD0000h
FC0000h
FB0000h
FA0000h
F90000h
F80000h
F70000h
F60000h
F50000h
F40000h
F30000h
F20000h
F10000h
F00000h
EF0000h
EE0000h
ED0000h
EC0000h
EB0000h
EA0000h
E90000h
E80000h
E70000h
E60000h
E50000h
E40000h
E30000h
E20000h
E10000h
E00000h
DF0000h
DE0000h
DD0000h
DC0000h
DB0000h
DA0000h
D90000h
D80000h
D70000h
D60000h
D50000h
D40000h
D30000h
D20000h
D10000h
D00000h
CF0000h
SA206
SA205
SA204
SA203
SA202
SA201
SA200
SA199
SA198
SA197
SA196
SA195
SA194
SA193
SA192
SA191
SA190
SA189
SA188
SA187
SA186
SA185
SA184
SA183
SA182
SA181
SA180
SA179
SA178
SA177
SA176
SA175
SA174
SA173
SA172
SA171
SA170
SA169
SA168
SA167
SA166
SA165
SA164
SA163
SA162
SA161
SA160
SA159
SA158
CE0000h
CD0000h
CC0000h
CB0000h
CA0000h
C90000h
C80000h
C70000h
C60000h
C50000h
C40000h
C30000h
C20000h
C10000h
C00000h
BF0000h
BE0000h
BD0000h
BC0000h
BB0000h
BA0000h
B90000h
B80000h
B70000h
B60000h
B50000h
B40000h
B30000h
B20000h
B10000h
B00000h
AF0000h
AE0000h
AD0000h
AC0000h
AB0000h
AA0000h
A90000h
A80000h
A70000h
A60000h
A50000h
A40000h
A30000h
A20000h
A10000h
A00000h
9F0000h
9E0000h
SA157
SA156
SA155
SA154
SA153
SA152
SA151
SA150
SA149
SA148
SA147
SA146
SA145
SA144
SA143
SA142
SA141
SA140
SA139
SA138
SA137
SA136
SA135
SA134
SA133
SA132
SA131
SA130
SA129
SA128
SA127
SA126
SA125
SA124
SA123
SA122
SA121
SA120
SA119
SA118
SA117
SA116
SA115
SA114
SA113
SA112
SA111
SA110
SA109
9D0000h
9C0000h
9B0000h
9A0000h
990000h
980000h
970000h
960000h
950000h
940000h
930000h
920000h
910000h
900000h
8F0000h
8E0000h
8D0000h
8C0000h
8B0000h
8A0000h
890000h
880000h
870000h
860000h
850000h
840000h
830000h
820000h
810000h
800000h
7F0000h
7E0000h
7D0000h
7C0000h
7B0000h
7A0000h
790000h
780000h
770000h
760000h
750000h
740000h
730000h
720000h
710000h
700000h
6F0000h
6E0000h
6D0000h
Note
Sector SA0 is split up into sub-sectors SS0 - SS15 (dark gray shading)
Sector SA1 is split up into sub-sectors SS16 - SS31(light gray shading)
January 30, 2013 S25FL129P_00_09
S25FL129P
21
D a t a S h e e t
Table 8.3 S25FL129P Sector Address Table (Uniform 64 KB sector, TBPARM=1) (Sheet 1 of 2)
Address Range
Start Address
Address Range
Start Address
Address Range
Start Address
Sector
Sector
Sector
End Address
FFFFFFh
FFEFFFh
FFDFFFh
FFCFFFh
FFBFFFh
FFAFFFh
FF9FFFh
FF8FFFh
FF7FFFh
FF6FFFh
FF5FFFh
FF4FFFh
FF3FFFh
FF2FFFh
FF1FFFh
FF0FFFh
FEFFFFh
FEEFFFh
FEDFFFh
FECFFFh
FEBFFFh
FEAFFFh
FE9FFFh
FE8FFFh
FE7FFFh
FE6FFFh
FE5FFFh
FE4FFFh
FE3FFFh
FE2FFFh
FE1FFFh
FE0FFFh
FFFFFFh
FEFFFFh
FDFFFFh
FCFFFFh
FBFFFFh
FAFFFFh
F9FFFFh
F8FFFFh
F7FFFFh
F6FFFFh
F5FFFFh
F4FFFFh
F3FFFFh
F2FFFFh
F1FFFFh
F0FFFFh
End Address
EFFFFFh
EEFFFFh
EDFFFFh
ECFFFFh
EBFFFFh
EAFFFFh
E9FFFFh
E8FFFFh
E7FFFFh
E6FFFFh
E5FFFFh
E4FFFFh
E3FFFFh
E2FFFFh
E1FFFFh
E0FFFFh
DFFFFFh
DEFFFFh
DDFFFFh
DCFFFFh
DBFFFFh
DAFFFFh
D9FFFFh
D8FFFFh
D7FFFFh
D6FFFFh
D5FFFFh
D4FFFFh
D3FFFFh
D2FFFFh
D1FFFFh
D0FFFFh
CFFFFFh
CEFFFFh
CDFFFFh
CCFFFFh
CBFFFFh
CAFFFFh
C9FFFFh
C8FFFFh
C7FFFFh
C6FFFFh
C5FFFFh
C4FFFFh
C3FFFFh
C2FFFFh
C1FFFFh
C0FFFFh
End Address
BFFFFFh
BEFFFFh
BDFFFFh
BCFFFFh
BBFFFFh
BAFFFFh
B9FFFFh
B8FFFFh
B7FFFFh
B6FFFFh
B5FFFFh
B4FFFFh
B3FFFFh
B2FFFFh
B1FFFFh
B0FFFFh
AFFFFFh
AEFFFFh
ADFFFFh
ACFFFFh
ABFFFFh
AAFFFFh
A9FFFFh
A8FFFFh
A7FFFFh
A6FFFFh
A5FFFFh
A4FFFFh
A3FFFFh
A2FFFFh
A1FFFFh
A0FFFFh
9FFFFFh
9EFFFFh
9DFFFFh
9CFFFFh
9BFFFFh
9AFFFFh
99FFFFh
98FFFFh
97FFFFh
96FFFFh
95FFFFh
94FFFFh
93FFFFh
92FFFFh
91FFFFh
90FFFFh
SS31
SS30
SS29
SS28
SS27
SS26
SS25
SS24
SS23
SS22
SS21
SS20
SS19
SS18
SS17
SS16
SS15
SS14
SS13
SS12
SS11
SS10
SS9
FFF000h
FFE000h
FFD000h
FFC000h
FFB000h
FFA000h
FF9000h
FF8000h
FF7000h
FF6000h
FF5000h
FF4000h
FF3000h
FF2000h
FF1000h
FF0000h
FEF000h
FEE000h
FED000h
FEC000h
FEB000h
FEA000h
FE9000h
FE8000h
FE7000h
FE6000h
FE5000h
FE4000h
FE3000h
FE2000h
FE1000h
FE0000h
FF0000h
FE0000h
FD0000h
FC0000h
FB0000h
FA0000h
F90000h
F80000h
F70000h
F60000h
F50000h
F40000h
F30000h
F20000h
F10000h
F00000h
SA239
SA238
SA237
SA236
SA235
SA234
SA233
SA232
SA231
SA230
SA229
SA228
SA227
SA226
SA225
SA224
SA223
SA222
SA221
SA220
SA219
SA218
SA217
SA216
SA215
SA214
SA213
SA212
SA211
SA210
SA209
SA208
SA207
SA206
SA205
SA204
SA203
SA202
SA201
SA200
SA199
SA198
SA197
SA196
SA195
SA194
SA193
SA192
EF0000h
EE0000h
ED0000h
EC0000h
EB0000h
EA0000h
E90000h
E80000h
E70000h
E60000h
E50000h
E40000h
E30000h
E20000h
E10000h
E00000h
DF0000h
DE0000h
DD0000h
DC0000h
DB0000h
DA0000h
D90000h
D80000h
D70000h
D60000h
D50000h
D40000h
D30000h
D20000h
D10000h
D00000h
CF0000h
CE0000h
CD0000h
CC0000h
CB0000h
CA0000h
C90000h
C80000h
C70000h
C60000h
C50000h
C40000h
C30000h
C20000h
C10000h
C00000h
SA191
SA190
SA189
SA188
SA187
SA186
SA185
SA184
SA183
SA182
SA181
SA180
SA179
SA178
SA177
SA176
SA175
SA174
SA173
SA172
SA171
SA170
SA169
SA168
SA167
SA166
SA165
SA164
SA163
SA162
SA161
SA160
SA159
SA158
SA157
SA156
SA155
SA154
SA153
SA152
SA151
SA150
SA149
SA148
SA147
SA146
SA145
SA144
BF0000h
BE0000h
BD0000h
BC0000h
BB0000h
BA0000h
B90000h
B80000h
B70000h
B60000h
B50000h
B40000h
B30000h
B20000h
B10000h
B00000h
AF0000h
AE0000h
AD0000h
AC0000h
AB0000h
AA0000h
A90000h
A80000h
A70000h
A60000h
A50000h
A40000h
A30000h
A20000h
A10000h
A00000h
9F0000h
9E0000h
9D0000h
9C0000h
9B0000h
9A0000h
990000h
980000h
970000h
960000h
950000h
940000h
930000h
920000h
910000h
900000h
SS8
SS7
SS6
SS5
SS4
SS3
SS2
SS1
SS0
SA255
SA254
SA253
SA252
SA251
SA250
SA249
SA248
SA247
SA246
SA245
SA244
SA243
SA242
SA241
SA240
22
S25FL129P
S25FL129P_00_09 January 30, 2013
D a t a S h e e t
Table 8.3 S25FL129P Sector Address Table (Uniform 64 KB sector, TBPARM=1) (Sheet 2 of 2)
Address Range
Start Address
Address Range
Start Address
Address Range
Start Address
Sector
Sector
Sector
End Address
8FFFFFh
8EFFFFh
8DFFFFh
8CFFFFh
8BFFFFh
8AFFFFh
89FFFFh
88FFFFh
87FFFFh
86FFFFh
85FFFFh
84FFFFh
83FFFFh
82FFFFh
81FFFFh
80FFFFh
7FFFFFh
7EFFFFh
7DFFFFh
7CFFFFh
7BFFFFh
7AFFFFh
79FFFFh
78FFFFh
77FFFFh
76FFFFh
75FFFFh
74FFFFh
73FFFFh
72FFFFh
71FFFFh
70FFFFh
6FFFFFh
6EFFFFh
6DFFFFh
6CFFFFh
6BFFFFh
6AFFFFh
69FFFFh
68FFFFh
67FFFFh
66FFFFh
65FFFFh
64FFFFh
63FFFFh
62FFFFh
61FFFFh
60FFFFh
End Address
5FFFFFh
5EFFFFh
5DFFFFh
5CFFFFh
5BFFFFh
5AFFFFh
59FFFFh
58FFFFh
57FFFFh
56FFFFh
55FFFFh
54FFFFh
53FFFFh
52FFFFh
51FFFFh
50FFFFh
4FFFFFh
4EFFFFh
4DFFFFh
4CFFFFh
4BFFFFh
4AFFFFh
49FFFFh
48FFFFh
47FFFFh
46FFFFh
45FFFFh
44FFFFh
43FFFFh
42FFFFh
41FFFFh
40FFFFh
3FFFFFh
3EFFFFh
3DFFFFh
3CFFFFh
3BFFFFh
3AFFFFh
39FFFFh
38FFFFh
37FFFFh
36FFFFh
35FFFFh
34FFFFh
33FFFFh
32FFFFh
31FFFFh
30FFFFh
End Address
2FFFFFh
2EFFFFh
2DFFFFh
2CFFFFh
2BFFFFh
2AFFFFh
29FFFFh
28FFFFh
27FFFFh
26FFFFh
25FFFFh
24FFFFh
23FFFFh
22FFFFh
21FFFFh
20FFFFh
1FFFFFh
1EFFFFh
1DFFFFh
1CFFFFh
1BFFFFh
1AFFFFh
19FFFFh
18FFFFh
17FFFFh
16FFFFh
15FFFFh
14FFFFh
13FFFFh
12FFFFh
11FFFFh
10FFFFh
0FFFFFh
0EFFFFh
0DFFFFh
0CFFFFh
0BFFFFh
0AFFFFh
09FFFFh
08FFFFh
07FFFFh
06FFFFh
05FFFFh
04FFFFh
03FFFFh
02FFFFh
01FFFFh
00FFFFh
SA143
SA142
SA141
SA140
SA139
SA138
SA137
SA136
SA135
SA134
SA133
SA132
SA131
SA130
SA129
SA128
SA127
SA126
SA125
SA124
SA123
SA122
SA121
SA120
SA119
SA118
SA117
SA116
SA115
SA114
SA113
SA112
SA111
SA110
SA109
SA108
SA107
SA106
SA105
SA104
SA103
SA102
SA101
SA100
SA99
8F0000h
8E0000h
8D0000h
8C0000h
8B0000h
8A0000h
890000h
880000h
870000h
860000h
850000h
840000h
830000h
820000h
810000h
800000h
7F0000h
7E0000h
7D0000h
7C0000h
7B0000h
7A0000h
790000h
780000h
770000h
760000h
750000h
740000h
730000h
720000h
710000h
700000h
6F0000h
6E0000h
6D0000h
6C0000h
6B0000h
6A0000h
690000h
680000h
670000h
660000h
650000h
640000h
630000h
620000h
610000h
600000h
SA95
SA94
SA93
SA92
SA91
SA90
SA89
SA88
SA87
SA86
SA85
SA84
SA83
SA82
SA81
SA80
SA79
SA78
SA77
SA76
SA75
SA74
SA73
SA72
SA71
SA70
SA69
SA68
SA67
SA66
SA65
SA64
SA63
SA62
SA61
SA60
SA59
SA58
SA57
SA56
SA55
SA54
SA53
SA52
SA51
SA50
SA49
SA48
5F0000h
5E0000h
5D0000h
5C0000h
5B0000h
5A0000h
590000h
580000h
570000h
560000h
550000h
540000h
530000h
520000h
510000h
500000h
4F0000h
4E0000h
4D0000h
4C0000h
4B0000h
4A0000h
490000h
480000h
470000h
460000h
450000h
440000h
430000h
420000h
410000h
400000h
3F0000h
3E0000h
3D0000h
3C0000h
3B0000h
3A0000h
390000h
380000h
370000h
360000h
350000h
340000h
330000h
320000h
310000h
300000h
SA47
SA46
SA45
SA44
SA43
SA42
SA41
SA40
SA39
SA38
SA37
SA36
SA35
SA34
SA33
SA32
SA31
SA30
SA29
SA28
SA27
SA26
SA25
SA24
SA23
SA22
SA21
SA20
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
2F0000h
2E0000h
2D0000h
2C0000h
2B0000h
2A0000h
290000h
280000h
270000h
260000h
250000h
240000h
230000h
220000h
210000h
200000h
1F0000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
0F0000h
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
090000h
080000h
070000h
060000h
050000h
040000h
030000h
020000h
010000h
000000h
SA8
SA7
SA6
SA5
SA4
SA3
SA98
SA2
SA97
SA1
SA96
SA0
Note
Sector SA254 is split up into sub-sectors SS0 - SS15 (dark gray shading)
Sector SA255 is split up into sub-sectors SS16 - SS31(light gray shading)
January 30, 2013 S25FL129P_00_09
S25FL129P
23
D a t a S h e e t
9. Command Definitions
The host system must shift all commands, addresses, and data in and out of the device, beginning with the
most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte
command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on
the rising edge of SCK. Table 9.1 lists the complete set of commands.
Every command sequence begins with a one-byte command code. The command may be followed by
address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the
command sequence has been written.
The Read Data Bytes (READ), Read Data Bytes at Higher Speed (FAST_READ), Dual Output Read (DOR),
Quad Output Read (QOR), Dual I/O High Performance Read (DIOR), Quad I/O High Performance Read
(QIOR), Read Status Register (RDSR), Read Configuration Register (RCR), Read OTP Data (OTPR), Read
Manufacturer and Device ID (READ_ID), Read Identification (RDID) and Release from Deep Power-Down
and Read Electronic Signature (RES) command sequences are followed by a data output sequence on SO.
CS# can be driven high after any bit of the sequence is output to terminate the operation.
The Page Program (PP), Quad Page Program (QPP), 64 KB Sector Erase (SE), 4 KB Parameter Sector
Erase (P4E), 8 KB Parameter Sector Erase (P8E), Bulk Erase (BE), Write Status and Configuration Registers
(WRR), Program OTP space (OTPP), Write Enable (WREN), or Write Disable (WRDI) commands require that
CS# be driven high at a byte boundary, otherwise the command is not executed. Since a byte is composed of
eight bits, CS# must therefore be driven high when the number of clock pulses after CS# is driven low is an
exact multiple of eight.
The device ignores any attempt to access the memory array during a Write Registers, program, or erase
operation, and continues the operation uninterrupted.
The instruction set is listed in Table 9.1.
24
S25FL129P
S25FL129P_00_09 January 30, 2013
D a t a S h e e t
Table 9.1 Instruction Set
Mode
Bit
Cycle
Data
Byte
Cycle
One byte Command
Code
Address
Byte Cycle
Dummy
Byte Cycle
Operation
Command
Description
READ
FAST_READ
DOR
(03h) 0000 0011
(0Bh) 0000 1011
(3Bh) 0011 1011
(6Bh) 0110 1011
(BBh) 1011 1011
(EBh) 1110 1011
(9Fh) 1001 1111
(90h) 1001 0000
(06h) 0000 0110
(04h) 0000 0100
(20h) 0010 0000
(40h) 0100 0000
(D8h) 1101 1000
Read Data bytes
3
3
3
3
3
3
0
3
0
0
3
3
3
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
0
2
0
0
0
0
0
0
0
1 to ∞
1 to ∞
1 to ∞
1 to ∞
1 to ∞
1 to ∞
1 to 81
1 to ∞
0
Read Data bytes at Fast Speed
Dual Output Read
QOR
Quad Output Read
Read
DIOR
Dual I/O High Performance Read
Quad I/O High Performance Read
Read Identification
QIOR
RDID
READ_ID
WREN
WRDI
Read Manufacturer and Device Identification
Write Enable
Write Control
Erase
Write Disable
0
P4E (1)
P8E (1)
SE
4 KB Parameter Sector Erase
8 KB (two 4KB) Parameter Sector Erase
64 KB and 256 KB Sector Erase
0
0
0
(60h) 0110 0000 or
(C7h) 1100 0111
BE
Bulk Erase
0
0
0
0
PP
(02h) 0000 0010
(32h) 0011 0010
(05h) 0000 0101
(01h) 0000 0001
(35h) 0011 0101
Page Programming
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1 to 256
1 to 256
1 to ∞
1 to 2
Program
QPP
RDSR
WRR
RCR
Quad Page Programming
Read Status Register
Write (Status and Configuration) Register
Read Configuration Register (CFG)
Status and
Configuration
Register
1 to ∞
Reset the Erase and Program Fall Flag (SRS and
SR6) and restore normal operation)
CLSR
DP
(30h) 0011 0000
0
0
0
0
(B9h) 1011 1001
(ABh) 1010 1011
Deep Power-Down
0
0
0
0
0
0
0
0
Release from Deep Power-Down Mode
Power Saving
RES
Release from Deep Power-Down and Read
Electronic Signature
(ABh) 1010 1011
0
0
3
1 to ∞
OTPP
OTPR
(42h) 0100 0010
(4Bh) 0100 1011
Program one byte of data in OTP memory space
Read data in the OTP memory space
3
3
0
0
0
1
1
OTP
1 to ∞
Note
1. For uniform 64 KB sector device only.
January 30, 2013 S25FL129P_00_09
S25FL129P
25
D a t a S h e e t
9.1
Read Data Bytes (READ)
The Read Data Bytes (READ) command reads data from the memory array at the frequency (f ) presented at
R
the SCK input, with a maximum speed of 40 MHz. The host system must first select the device by driving CS#
low. The READ command is then written to SI, followed by a 3 byte address (A23-A0). Each bit is latched on
the rising edge of SCK. The memory array data, at that address, are output serially on SO at a frequency f ,
R
on the falling edge of SCK.
Figure 9.1 and Table 9.1 on page 25 detail the READ command sequence. The first address byte specified
can start at any location of the memory array. The device automatically increments to the next higher address
after each byte of data is output. The entire memory array can therefore be read with a single READ
command. When the highest address is reached, the address counter reverts to 00000h, allowing the read
sequence to continue indefinitely.
The READ command is terminated by driving CS# high at any time during data output. The device rejects any
READ command issued while it is executing a program, erase, or Write Registers operation, and continues
the operation uninterrupted.
Figure 9.1 Read Data Bytes (READ) Command Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
Mode 3
SCK
Mode 0
Command
24 Bit Address
23 22 21
2
0
1
3
SI
MSB
Data Out 1
Data Out 2
Hi-Z
SO
6
4
2
7
1 0
7
5
3
MSB
26
S25FL129P
S25FL129P_00_09 January 30, 2013
D a t a S h e e t
9.2
Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ command reads data from the memory array at the frequency (f ) presented at the SCK
C
input, with a maximum speed of 104 MHz. The host system must first select the device by driving CS# low.
The FAST_READ command is then written to SI, followed by a 3 byte address (A23-A0) and a dummy byte.
Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on
SO at a frequency f , on the falling edge of SCK.
C
The FAST_READ command sequence is shown in Figure 9.2 and Table 9.1 on page 25. The first address
byte specified can start at any location of the memory array. The device automatically increments to the next
higher address after each byte of data is output. The entire memory array can therefore be read with a single
FAST_READ command. When the highest address is reached, the address counter reverts to 000000h,
allowing the read sequence to continue indefinitely.
The FAST_READ command is terminated by driving CS# high at any time during data output. The device
rejects any FAST_READ command issued while it is executing a program, erase, or Write Registers
operation, and continues the operation uninterrupted.
Figure 9.2 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence
CS#
33
0
1
2
5
6
7
8
9
29 30
32
38 39 40 41
44 45 46
42 43
Mode 3
31
34 35 36 37
3
4
10
28
47
SCK
Mode 0
24 Bit Address
Dummy Byte
Command
23
3
2
22 21
1
0
6
5
4
2
0
1
7
3
SI
Hi-Z
3
7
6
4
2
1
0
5
7
SO
MSB
MSB
DATA OUT 1
DATA OUT 2
January 30, 2013 S25FL129P_00_09
S25FL129P
27
D a t a S h e e t
9.3
Dual Output Read Mode (DOR)
The Dual Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out
2 bits at a time using 2 pins (SI/IO0 and SO/IO1) instead of 1 bit, at a maximum frequency of 80 MHz. The
Dual Output Read mode effectively doubles the data transfer rate compared to the FAST_READ instruction.
The host system must first select the device by driving CS# low. The Dual Output Read command is then
written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge
of SCK. Then the memory contents, at the address that is given, are shifted out two bits at a time through the
IO0 (SI) and IO1 (SO) pins at a frequency f on the falling edge of SCK.
C
The Dual Output Read command sequence is shown in Figure 9.3 and Table 9.1 on page 25. The first
address byte specified can start at any location of the memory array. The device automatically increments to
the next higher address after each byte of data is output. The entire memory array can therefore be read with
a single Dual Output Read command. When the highest address is reached, the address counter reverts to
00000h, allowing the read sequence to continue indefinitely.
It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.
The Dual Output Read command is terminated by driving CS# high at any time during data output. The
device rejects any Dual Output Read command issued while it is executing a program, erase, or Write
Registers operation, and continues the operation uninterrupted.
Figure 9.3 Dual Output Read Instruction Sequence
CS#
0
1
2
5
6
7
8
9
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
3
4
10
SCK
24 Bit
Address
Instruction
Dummy Byte
SI Switches from Input to Output
SI/IO0
23 22 21
6
3
2
1
0
7
6
5
4
3
2
1
0
6
4
2
0
6
4
5
2
0
1
*
*
Hi-Z
3
5
3
1
7
7
7
SO/IO1
*
*
Byte 1
Byte 2
*MSB
28
S25FL129P
S25FL129P_00_09 January 30, 2013
D a t a S h e e t
9.4
Quad Output Read Mode (QOR)
The Quad Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out
4 bits at a time using 4 pins (SI/IO0, SO/IO1, W#/ACC/IO2 and HOLD#/IO3) instead of 1 bit, at a maximum
frequency of 80 MHz. The Quad Output Read mode effectively doubles the data transfer rate compared to the
Dual Output Read instruction, and is four times the data transfer rate of the FAST_READ instruction.
The host system must first select the device by driving CS# low. The Quad Output Read command is then
written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge
of SCK. Then the memory contents, at the address that are given, are shifted out four bits at a time through
IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#) pins at a frequency f on the falling edge of SCK.
C
The Quad Output Read command sequence is shown in Figure 9.4 and Table 9.1 on page 25. The first
address byte specified can start at any location of the memory array. The device automatically increments to
the next higher address after each byte of data is output. The entire memory array can therefore be read with
a single Quad Output Read command. When the highest address is reached, the address counter reverts to
00000h, allowing the read sequence to continue indefinitely.
It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.
The Quad Output Read command is terminated by driving CS# high at any time during data output. The
device rejects any Quad Output Read command issued while it is executing a program, erase, or Write
Registers operation, and continues the operation uninterrupted.
The Quad bit of Configuration Register must be set (CR Bit1 = 1) to enable the Quad mode capability of the
S25FL device.
Figure 9.4 Quad Output Read Instruction Sequence
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
0
1
2
3
4
5
6
7
8
9 10
SCK
24 Bit
Address
Instruction
Dummy Byte
SI Switches from Input to Output
SI/IO0
3
2
1
0
7
6
5
4
3
1
0
23 22 21
0
1
0
1
2
0
1
4
5
4
5
0
4
4
5
4
*
Hi-Z
Hi-Z
*
5
1
5
SO/IO1
W#/ACC/IO2
6
2
6
2
6
6
6
2
2
Hi-Z
3
3
3
7
7
7
3
7
7
HOLD#/IO3
*
*
*
*
*
DATA DATA DATA DATA
OUT 1 OUT 2 OUT 3 OUT 4
*MSB
January 30, 2013 S25FL129P_00_09
S25FL129P
29
D a t a S h e e t
9.5
DUAL I/O High Performance Read Mode (DIOR)
The Dual I/O High Performance Read instruction is similar to the Dual Output Read instruction, except that it
improves throughput by allowing input of the address bits (A23-A0) using two bits per SCK via two input pins
(SI/IO2 and SO/IO1), at a maximum frequency of 80 MHz.
The host system must first select the device by driving CS# low. The Dual I/O High Performance Read
command is then written to SI, followed by a 3-byte address (A23-A0) and a 1-byte Mode instruction, with two
bits latched on the rising edge of SCK. Then the memory contents, at the address that is given, are shifted out
two bits at a time through IO0 (SI) and IO1 (SO).
The DUAL I/O High Performance Read command sequence is shown in Figure 9.5 and Table 9.1
on page 25. The first address byte specified can start at any location of the memory array. The device
automatically increments to the next higher address after each byte of data is output. The entire memory
array can therefore be read with a single DUAL I/O High Performance Read command. When the highest
address is reached, the address counter reverts to 00000h, allowing the read sequence to continue
indefinitely.
In addition, address jumps can be done without exiting the Dual I/O High Performance Mode through the
setting of the Mode bits (after the Address (A23-0) sequence, as shown in Figure 9.5). This added feature
removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble
(bits 7-4) of the Mode bits control the length of the next Dual I/O High Performance instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are DON’T
CARE (“x”). If the Mode bits equal Axh, then the device remains in Dual I/O High Performance Read Mode
and the next address can be entered (after CS# is raised high and then asserted low) without requiring the
BBh instruction opcode, as shown in Figure 9.6, thus eliminating eight cycles for the instruction sequence.
However, if the Mode bits are any value other than Axh, then the next instruction (after CS# is raised high and
then asserted low) requires the instruction sequence, which is normal operation. The following sequences will
release the device from Dual I/O High Performance Read mode; after which, the device can accept standard
SPI instructions:
1. During the Dual I/O High Performance Instruction Sequence, if the Mode bits are any value other
than Axh, then the next time CS# is raised high and then asserted low, the device will be released
from Dual I/O High Performance Read mode.
2. Furthermore, during any operation, if CS# toggles high to low to high for eight cycles (or less) and
data input (IO0 and IO1) are not set for a valid instruction sequence, then the device will be
released from Dual I/O High Performance Read mode.
It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.
The read instruction can be terminated by driving the CS# pin to the logic high state. The CS# pin can be
driven high at any time during data output to terminate a read operation.
Figure 9.5 DUAL I/O High Performance Read Instruction Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
24 Bit
Address
Instruction
IO0 & IO1 Switches from Input to Output
2
2
6
4
5
6
2
6
4
5
6
4
5
0
1
0
1
20
21
2
0
1
22
0
1
SI/IO0
Hi-Z
3
3
3
7
3
7
7
23
7
SO/IO1
*
*
*
*
*
Mode Bits
Byte 1
Byte 2
*MSB
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D a t a S h e e t
Figure 9.6 Continuous Dual I/O High Performance Read Instruction Sequence
CS#
SCK
0
1
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
24 Bit
Address
IO0 & IO1 Switches from Input to Output
22 20
2
6
4
2
0
1
6
4
5
2
0
6
0
1
6
4
5
2
0
1
SI/IO0
SO/IO1
23
7
21
3
3
3
5
3
7
1
7
7
*
*
*
*
*
Mode Bits
Byte 1
Byte 2
*MSB
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D a t a S h e e t
9.6
Quad I/O High Performance Read Mode (QIOR)
The Quad I/O High Performance Read instruction is similar to the Quad Output Read instruction, except that
it further improves throughput by allowing input of the address bits (A23-A0) using 4 bits per SCK via four
input pins (SI/IO0, SO/IO1, W#/ACC/IO2 and HOLD#/IO3), at a maximum frequency of 80 MHz.
The host system must first select the device by driving CS# low. The Quad I/O High Performance Read
command is then written to SI, followed by a 3-byte address (A23-A0) and a 1-byte Mode instruction, with four
bits latched on the rising edge of SCK. Note that four dummy clocks are required prior to the data input. Then
the memory contents, at the address that is given, are shifted out four bits at a time through IO0 (SI), IO1
(SO), IO2 (W#/ACC), and IO3 (HOLD#).
The Quad I/O High Performance Read command sequence is shown in Figure 9.7 and Table 9.1 on page 25.
The first address byte specified can start at any location of the memory array. The device automatically
increments to the next higher address after each byte of data is output. The entire memory array can
therefore be read with a single Quad I/O High Performance Read command. When the highest address is
reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely.
In addition, address jumps can be done without exiting the Quad I/O High Performance Mode through the
setting of the Mode bits (after the Address (A23-0) sequence, as shown in Figure 9.7). This added feature the
removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble
(bits 7-4) of the Mode bits control the length of the next Quad I/O High Performance instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are DON'T
CARE (“x”). If the Mode bits equal Axh, then the device remains in Quad I/O High Performance Read Mode
and the next address can be entered (after CS# is raised high and then asserted low) without requiring the
EBh instruction opcode, as shown in Figure 9.8, thus eliminating eight cycles for the instruction sequence.
The following sequences will release the device from Quad I/O High Performance Read mode; after which,
the device can accept standard SPI instructions:
1. During the Quad I/O High Performance Instruction Sequence, if the Mode bits are any value other
than Axh, then the next time CS# is raised high and then asserted low the device will be released
from Quad I/O High Performance Read mode.
2. Furthermore, during any operation, if CS# toggles high to low to high for eight cycles (or less) and
data input (IO0, IO1, IO2, and IO3) are not set for a valid instruction sequence, then the device will
be released from Quad I/O High Performance Read mode.
It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.
The read instruction can be terminated by driving the CS# pin to the logic high state. The CS# pin can be
driven high at any time during data output to terminate a read operation.
Figure 9.7 QUAD I/O High Performance Instruction Sequence
CS#
0
1
2
3
4
5
6
7
8
9
13 14 15 16 17 18 19 20 21 22 23 24 25 26
SCK
24 Bit
Address
Instruction
IO’s Switches from Input to Output
SI/IO0
16
0
1
0
4
20
0
1
2
3
4
5
4
5
0
4
Hi-Z
5
17
18
19
1
5
6
21
22
1
2
3
SO/IO1
Hi-Z
Hi-Z
W#/ACC/IO2
6
6
6
2
2
7
7
3
3
7
HOLD#/IO3
23
7
*
*
*
*
*
DUMMY DUMMY
Mode Bits
Byte 1
Byte 2
*MSB
32
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D a t a S h e e t
Figure 9.8 Continuous QUAD I/O High Performance Instruction Sequence
CS#
SCK
0
1
4
5
6
7
8
9
10 11
12 13 14 15 16
24 Bit
Address
IO’s Switches from Input to Output
16
20
SI/IO0
0
0
4
0
4
4
5
0
1
4
5
17
21
22
5
6
1
2
3
1
5
6
1
2
3
SO/IO1
W#/ACC/IO2
18
6
2
6
2
7
7
3
3
HOLD#/IO3
7
19
7
23
*
*
*
*
*
DUMMY
DUMMY
Mode Bits
Byte 1
Byte 2
*MSB
9.7
Read Identification (RDID)
The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the
two-byte device identification and the bytes for the Common Flash Interface (CFI) tables. The manufacturer
identification is assigned by JEDEC; for Spansion devices, it is 01h. The device identification (2 bytes) and
CFI bytes are assigned by the device manufacturer.
See Table 9.2 on page 34 for device ID data.
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows vendor-specified software algorithms to be used for entire families of devices.
Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-
compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for
long-term compatibility. The system can read CFI information at the addresses given in Table 9.3.
The host system must first select the device by driving CS# low. The RDID command is then written to SI,
and each bit is latched on the rising edge of SCK. One byte of manufacture identification, two bytes of device
identification and sixty-six bytes of extended device identification are then output from the memory array on
SO at a frequency f , on the falling edge of SCK. The maximum clock frequency for the RDID (9Fh)
R
command is 50 MHz (Normal Read). The manufacturer ID and Device ID can be read repeatedly by applying
multiples of six hundred and forty eight clock cycles. The manufacturer ID, Device ID and CFI table can be
continuously read as long as CS# is held low with a clock input.
The RDID command sequence is shown in Figure 9.9 and Table 9.1 on page 25.
Driving CS# high after the device identification data has been read at least once terminates the RDID
command. Driving CS# high at any time during data output (for example, while reading the extended CFI
bytes), also terminates the RDID operation.
The device rejects any RDID command issued while it is executing a program, erase, or Write Registers
operation, and continues the operation uninterrupted.
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D a t a S h e e t
Figure 9.9 Read Identification (RDID) Command Sequence and Data-Out Sequence
CS#
SCK
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32
34
33
652 653 654 655
Instruction
SI
Extended Device Information
Manufacturer / Device Identification
20 21 22 23
High Impedance
644
645
646
647
0
1
2
24
25
26
SO
Table 9.2 Manufacturer and Device Identification - RDID (9Fh):
Manufacturer
Device Identification
Extended Device Identification
Identification
Byte 0
01h
Device
Byte 1
Byte 2
18h
Byte 3
4Dh
Byte 4
00h
Uniform 256 KB Sector
Uniform 64 KB Sector
20h
20h
01h
18h
4Dh
01h
Notes
1. Byte 0 is Manufacturer ID of Spansion.
2. Byte 1 and 2 is Device Id.
3. Byte 3 is Extended Device Information String Length, to indicate how many Extended Device Information bytes will follow.
4. Byte 4 indicates uniform 64 KB sector or uniform 256 KB sector device.
5. Bytes 5 and 6 are Spansion reserved (do not use).
6. For Bytes 07h-0Fh and 3Dh-3Fh, the data will be read as 0xFF.
7. Bytes 10h-50h are factory programmed per JEDEC standard.
Table 9.3 Product Group CFI Query Identification String
Byte
Data
Description
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
13h
14h
02h
00h
Primary OEM Command Set
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
00h
00h
Alternate OEM Command Set
(00h = none exists)
19h
1Ah
00h
00h
Address for Alternate OEM Extended Table
(00h = none exists)
34
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D a t a S h e e t
Table 9.4 Product Group CFI System Interface String
Byte
Data
Description
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
27h
36h
00h
00h
0Bh
0Bh
09h
11h
01h
01h
02h
V
V
V
V
CC Min. (erase/program): (D7-D4: Volt, D3-D0: 100 mV)
CC Max. (erase/program): (D7-D4: Volt, D3-D0: 100 mV)
PP Min. voltage (00h = no VPP pin present)
PP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte program 2N µs
Typical timeout for Min. size Page program 2N µs (00h = not supported)
Typical timeout per individual sector erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte program 2N times typical
Max. timeout for page program 2N times typical
Max. timeout per individual sector erase 2N times typical
Max. timeout for full chip erase 2N times typical
(00h = not supported)
26h
01h
Table 9.5 Product Group CFI Device Geometry Definition
Byte
27h
Data
18h
Description
Device Size = 2 N byte;
28h
05h
Flash Device Interface Description;
00h = x8 only
01h = x16 only
02h = x8/x16 capable
29h
05h
03h = x32 only
04h = Single I/O SPI, 3-byte address
05h = Multi I/O SPI, 3-byte address
2Ah
2Bh
08h
00h
Max. number of bytes in multi-byte write = 2N (00 = not supported)
02h (uniform 64 KB sector)
01h (uniform 256 KB sector)
Number of Erase Block Regions within device
1 = Uniform Device, 2 = Parameter Block
2Ch
1Fh (uniform 64 KB sector)
3Fh (uniform 256 KB sector)
2Dh
2Eh
2Fh
00h
Erase Block Region 1 Information (refer to CFI publication 100)
10h (uniform 64 KB sector)
00h (uniform 256 KB sector)
00h (uniform 64 KB sector)
04h (uniform 256 KB sector)
30h
31h
FDh (uniform 64 KB sector)
00h (uniform 256 KB sector)
32h
33h
00h
00h
Erase Block Region 2 Information (refer to CFI publication 100)
01h (uniform 64 KB sector)
00h (uniform 256 KB sector)
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
00h
00h
00h
00h
00h
00h
00h
00h
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
January 30, 2013 S25FL129P_00_09
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35
D a t a S h e e t
Table 9.6 Product Group CFI Primary Vendor-Specific Extended Query
Byte
40h
41h
42h
43h
44h
Data
50h
52h
49h
31h
33h
Description
Query-unique ASCII string “PRI”
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
00b = Required, 01b = Not Required
Process Technology (Bits 5-2)
0000b = 0.23 µm Floating Gate
0001b = 0.17 µm Floating Gate
0010b = 0.23 µm MirrorBit
45h
15h
0010b = 0.20 µm MirrorBit
0011b = 0.11 µm Floating Gate
0100b = 0.11 µm MirrorBit
0101b = 0.09 µm MirrorBit
1000b = 0.065 µm MirrorBit
Erase Suspend
0 = Not Supported, 1 = Read Only, 2 = Read and Write
46h
47h
48h
00h
04h
00h
Sector Protect
00 = Not Supported, X = Number of sectors in per smallest group
Temporary Sector Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect Scheme
04 = High Voltage Method
05 = Software Command Locking Method
08 = Advanced Sector Protection Method
49h
05h
Simultaneous Operation
00 = Not Supported, X = Number of Sectors outside Bank 1
4Ah
4Bh
00h
01h
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
4Ch
03h
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page,
03 = 256 Byte Page
ACC (Acceleration) Supply Minimum
00 = Not Supported, (D7-D4: Volt, D3-D0: 100 mV)
4Dh
4Eh
4Fh
50h
85h
95h
07h
00h
ACC (Acceleration) Supply Maximum
00 = Not Supported, (D7-D4: Volt, D3-D0: 100 mV)
W# Protection
07 = Uniform Device with Top or Bottom Write Protect (user select)
Program Suspend
00 = Not Supported, 01 = Supported
Note
CFI data related to VCC and time-outs may differ from actual VCC and time-outs of the product. Please consult the Ordering Information
tables to obtain the VCC range for particular part numbers. Please consult the AC Characteristics on page 60 for typical timeout
specifications.
36
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9.8
Read-ID (READ_ID)
The READ_ID instruction provides the S25FL129P manufacturer and device information and is provided as
an alternative to the Release from Deep Power-Down and Read Electronic Signature (RES), and the JEDEC
Read Identification (RDID) commands.
The instruction is initiated by driving the CS# pin low and shifting in (via the SI input pin) the instruction code
“90h” followed by a 24-bit address (which is either 00000h or 00001h). Following this, the Manufacturer ID
and the Device ID are shifted out on the SO output pin starting after the falling edge of the SCK serial clock
input signal. If the 24-bit address is set to 000000h, the Manufacturer ID is read out first followed by the
Device ID. If the 24-bit address is set to 000001h, then the Device ID is read out first followed by the
Manufacturer ID. The Manufacturer ID and the Device ID are always shifted out on the SO output pin with the
MSB first, as shown in Figure 9.10. Once the device is in Read-ID mode, the Manufacturer ID and Device ID
output data toggles between address 000000H and 000001H until terminated by a low to high transition on
the CS# input pin. The maximum clock frequency for the Read-ID (90h) command is at 104 MHz
(FAST_READ). The Manufacturer ID and Device ID is output continuously until terminated by a low to high
transition on CS# chip select input pin.
Figure 9.10 Read-ID (RDID) Command Timing Diagram
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Instruction
24-Bit Address
SI
23
21
2
22
3
1
0
MSB
Manufacture Identification
Device Identification
High Impedance
7
6
5
4
3
2
1
SO
0
Table 9.7 READ_ID Data-Out Sequence
Address
00000h
00001h
Data
01h
17h
Manufacturer Identification
Device Identification
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37
D a t a S h e e t
9.9
Write Enable (WREN)
The Write Enable (WREN) command (see Figure 9.11) sets the Write Enable Latch (WEL) bit to a 1, which
enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set
prior to every Page Program (PP), Quad Page Program (QPP), Parameter Sector Erase (P4E, P8E), Erase
(SE or BE), Write Registers (WRR) and OTP Program (OTPP) command.
The host system must first drive CS# low, write the WREN command, and then drive CS# high.
Figure 9.11 Write Enable (WREN) Command Sequence
CS#
6
7
0
1
2
3
4
5
Mode 3
SCK
SI
Mode 0
Command
Hi-Z
SO
9.10 Write Disable (WRDI)
The Write Disable (WRDI) command (see Figure 9.12) resets the Write Enable Latch (WEL) bit to a 0, which
disables the device from accepting a Page Program (PP), Quad Page Program (QPP), Parameter Sector
Erase (P4E, P8E), Erase (SE, BE), Write Registers (WRR) and OTP Program (OTPP) command. The host
system must first drive CS# low, write the WRDI command, and then drive CS# high.
Any of following conditions resets the WEL bit:
Power-up
Write Disable (WRDI) command completion
Write Registers (WRR) command completion
Page Program (PP) command completion
Quad Page Program (QPP) completion
Parameter Sector Erase (P4E, P8E) completion (applicable for the uniform 64 KB sector device only)
Sector Erase (SE) command completion
Bulk Erase (BE) command completion
OTP Program (OTPP) completion
Figure 9.12 Write Disable (WRDI) Command Sequence
CS#
0
3
4
7
6
1 2
5
Mode 3
SCK
SI
Mode 0
Command
Hi-Z
SO
38
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D a t a S h e e t
9.11 Read Status Register (RDSR)
The Read Status Register (RDSR) command outputs the state of the Status Register bits. Table 9.8 shows
the status register bits and their functions. The RDSR command may be written at any time, even while a
program, erase, or Write Registers operation is in progress. The host system should check the Write In
Progress (WIP) bit before sending a new command to the device if an operation is already in progress.
Figure 9.13 shows the RDSR command sequence, which also shows that it is possible to read the Status
Register continuously until CS# is driven high. The maximum clock frequency for the RDSR command is
104 MHz.
Table 9.8 S25FL129P Status Register
Bit
Status Register Bit
Bit Function
Description
1 = Protects when W#/ACC is low
7
SRWD
Status Register Write Disable
0 = No protection, even when W#/ACC is low
0 = No Error
6
5
P_ERR
E_ERR
Programming Error Occurred
Erase Error Occurred
1 = Error occurred
0 = No Error
1 = Error occurred
4
3
2
BP2
BP1
BP0
Block Protect
Protects selected Blocks from Program or Erase
1 = Device accepts Write Registers, program or erase commands
0 = Ignores Write Registers, program or erase commands
1
0
WEL
WIP
Write Enable Latch
Write in Progress
1 = Device Busy a Write Registers, program or erase operation is in
progress
0 = Ready. Device is in standby mode and can accept commands.
Figure 9.13 Read Status Register (RDSR) Command Sequence
CS#
SCK
7
0
2
3
4
5
6
9
11
12 13 14
15
1
8
10
Mode 3
Mode 0
Command
SI
Hi-Z
SO
6
4
2
6
5
7
5
3
1
0
4
2
7
0
7
3
1
MSB
MSB
Status Register Out
Status Register Out
The following describes the status and control bits of the Status Register.
Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Registers, program, or
erase operation. This bit is read-only, and is controlled internally by the device. If WIP is 1, one of these
operations is in progress; if WIP is 0, no such operation is in progress. This bit is a Read-only bit.
Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Registers,
program, or erase command. When set to 1, the device accepts these commands; when set to 0, the device
rejects the commands. This bit is set to 1 by writing the WREN command, and set to 0 by the WRDI
command, and is also automatically reset to 0 after the completion of a Write Registers, program, or erase
operation, and after a power down/power up sequence. WEL cannot be directly set by the WRR command.
Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against
any changes to the stored data. The Block Protection (BP2, BP1, BP0) bits are either volatile or non-volatile,
depending on the state of the non-volatile bit BPNV in the Configuration register. The Block Protection (BP2,
BP1, BP0) bits are written with the Write Registers (WRR) instruction. When one or more of the Block Protect
(BP2, BP1, BP0) bits is set to 1’s, the relevant memory area is protected against Page Program (PP),
January 30, 2013 S25FL129P_00_09
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D a t a S h e e t
Parameter Sector Erase (P4E, P8E), Sector Erase (SE), Quad Page Programming (QPP) and Bulk Erase
(BE) instructions. If the Hardware Protected mode is enabled, BP2:BP0 cannot be changed.
The Bulk Erase (BE) instruction can be executed only when the Block Protection (BP2, BP1, BP0) bits are set
to 0’s.
The default condition of the BP2-0 bits is binary 000 (all 0’s).
Erase Error bit (E_ERR): The Erase Error Bit is used as a Erase operation success and failure check. When
the Erase Error bit is set to a “1”, it indicates that there was an error which occurred in the last erase
operation. With the Erase Error bit set to a “1”, this bit is reset with the Clear Status Register (CLSR)
command.
Program Error bit (P_ERR): The Program Error Bit is used as a Program operation success and failure
check. When the Program Error bit is set to a “1”, it indicates that there was an error which occurred in the last
program operation. With the Program Error bit set to a “1”, this bit is reset with the Clear Status Register
(CLSR) command.
Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write
Protect (W#/ACC) signal. The Status Register Write Disable (SRWD) bit is operated in conjunction with the
Write Protect (W#/ACC) input pin. The Status Register Write Disable (SRWD) bit and the Write Protect (W#/
ACC) signal allow the device to be put in the Hardware Protected mode. With the Status Register Write
Disable (SRWD) bit set to a “1” and the W#/ACC driven to the logic low state, the device enters the Hardware
Protected mode; the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) and the nonvolatile bits
of the Configuration Register (TBPARM, TBPROT, BPNV and QUAD) become read-only bits and the Write
Registers (WRR) instruction opcode is no longer accepted for execution.
Note that the P_ERR and E_ERR bits will not be set to a 1 if the application writes to a protected memory
area.
9.12 Read Configuration Register (RCR)
The Read Configuration Register (RCR) instruction opcode allows the Configuration Register contents to be
read out of the SO serial output pin. The Configuration Register contents may be read at any time, even while
a program, erase, or write cycle is in progress. When one of these cycles is in progress, it is recommended to
the user to check the Write In Progress (WIP) bit of the Status Register before issuing a new instruction
opcode to the device. The Configuration Register originally shows 00h when the device is first shipped from
the factory to the customer. (Refer to Section 7.8 on page 15, Table 7.1 and Table 7.1 on page 16 for more
details.)
Figure 9.14 Read Configuration Register (RCR) Instruction Sequence
CS#
SCK
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
SI
Configuration Register Out
Configuration Register Out
High Impedance
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
SO
MSB
MSB
MSB
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9.13 Write Registers (WRR)
The Write Registers (WRR) command allows changing the bits in the Status and Configuration Registers. A
Write Enable (WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is
required prior to writing the WRR command. Table 9.8 shows the status register bits and their functions.
The host system must drive CS# low, then write the WRR command and the appropriate data byte on SI
Figure 9.15.
The WRR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must be
used for that purpose.
The Status Register consists of one data byte in length; similarly, the Configuration Register is also one data
byte in length. The CS# pin must be driven to the logic low state during the entire duration of the sequence.
The WRR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit
and W#/ACC pin together place the device in the Hardware Protected Mode (HPM). The device ignores all
WRR commands once it enters the Hardware Protected Mode (HPM). Table 9.9 shows that W#/ACC must be
driven low and the SRWD bit must be 1 for this to occur.
The Write Registers (WRR) instruction has no effect on the P/E Error and the WIP bits of the Status and
Configuration Registers. Any bit reserved for the future is always read as a ‘0’
The CS# chip select input pin must be driven to the logic high state after the eighth (see Figure 9.15) or
sixteenth (see Figure 9.16) bit of data has been latched in. If not, the Write Registers (WRR) instruction is not
executed. If CS# is driven high after the eighth cycle then only the Status Register is written to; otherwise,
after the sixteenth cycle both the Status and Configuration Registers are written to. As soon as the CS# chip
select input pin is driven to the logic high state, the self-timed Write Registers cycle is initiated. While the
Write Registers cycle is in progress, the Status Register may still be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is a ‘1’ during the self-timed Write Registers cycle, and is
a ‘0’ when it is completed. When the Write Registers cycle is completed, the Write Enable Latch (WEL) is set
to a ‘0’. The WRR command can operate at a maximum clock frequency of 104 MHz.
Figure 9.15 Write Registers (WRR) Instruction Sequence – 8 data bits
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
Instruction
Status Register In
SI
7
6
5
4
3
2
1
0
MSB
High Impedance
SO
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Figure 9.16 Write Registers (WRR) Instruction Sequence – 16 data bits
CS#
SCK
0
1
2
3
4
5
6
7
8
9
10 11 12 13
Status Register In
14 15
16 17 18 19 20 21
Configuration Register In
22
23
Instruction
7
6
5
4
3
2
1
0
SI
7
6
5
4
3
2
1
0
MSB
MSB
High Impedance
SO
Table 9.9 Protection Modes
Memory Content
W#/
ACC
SRWD
Bit
Mode
Write Protection of Registers
Protected Area
Unprotected Area
1
1
1
0
Status and Configuration Registers are
Writable (if WREN instruction has set the WEL
bit). The values in the SRWD, BP2, BP1, and
BP0 bits and those in the Configuration
Register can be changed
Protected against Page
Program, Parameter
Sector Erase, Sector
Erase, and Bulk Erase
Ready to accept Page
Program, Parameter
Sector Erase, and Sector
Erase instructions
Software
Protected
(SPM)
0
0
Status and Configuration Registers are
Hardware
Protected
(HPM)
Protected against Page
Program, Sector Erase,
and Bulk Erase
Ready to accept Page
Program, Sector Erase
instructions
Hardware Write Protected. The values in the
SRWD, BP2, BP1, and BP0 bits and those in
the Configuration Register cannot be changed
0
1
Note
As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 7.3 on page 17.
Table 9.9 shows that neither W#/ACC or SRWD bit by themselves can enable HPM. The device can enter
HPM either by setting the SRWD bit after driving W#/ACC low, or by driving W#/ACC low after setting the
SRWD bit. However, the device disables HPM only when W#/ACC is driven high.
Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in
HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no
protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM).
If W#/ACC is permanently tied high, HPM can never be activated, and only the SPM (Block Protect bits of the
Status Register) can be used.
The Status and Configuration registers originally default to 00h, when the device is first shipped from the
factory to the customer.
Note: HPM is disabled when the Quad I/O Mode is enabled (Quad bit = 1 in the Configuration Register).
W# becomes IO2; therefore, HPM cannot be utilized.
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9.14 Page Program (PP)
The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the PP command, three address bytes, and at least one
data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the currently selected page are programmed from the starting address of the same page
(from the address whose 8 least significant bits are all zero). CS# must be driven low for the entire duration of
the PP sequence. The command sequence is shown in Figure 9.17 and Table 9.1 on page 25.
The device programs only the last 256 data bytes sent to the device. If the 8 least significant address bits (A7-
A0) are not all zero, all transmitted data that goes beyond the end of the currently selected page are
programmed from the starting address of the same page (from the address whose 8 least significant bits are
all zero). If fewer than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effect on the other bytes in the same page.
The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the
device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t . The Status Register may
PP
be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP
bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute a Page Program (PP) command that specifies a page that is protected by the
Block Protect bits (BP2:BP0) (see Table 7.3 on page 17).
Figure 9.17 Page Program (PP) Command Sequence
CS#
5
8
34
37 38 39
35 36
0
2
4
6
7
10
28 32 33
29 30 31
1
3
9
Mode 3
Mode 0
SCK
SI
24 Bit Address
22 21
Data Byte 1
Command
4
3
2
3
2
1
0
7
6
5
1
0
23
MSB
MSB
CS#
SCK
53 54 55
52
49 50 51
46
44 45
40
47 48
41 42 43
Data Byte 2
Data Byte 3
Data Byte 256
0
7
6
0
1
7
MSB
7
6
5
4
3
2
1
0
6
5
4
3
2
1
5
4
3
2
SI
MSB
MSB
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9.15 QUAD Page Program (QPP)
The Quad Page Program instruction is similar to the Page Program instruction, except that the Quad Page
Program (QPP) instruction allows up to 256 bytes of data to be programmed at previously erased (FFh)
memory locations using four pins: IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#), instead of just one
pin (SI) as in the case of the Page Program (PP) instruction. This effectively increases the data transfer rate
by up to four times, as compared to the Page Program (PP) instruction. The QPP feature can improve
performance for PROM Programmer and applications that have slow clock speeds < 5 MHz. Systems with
faster clock speed will not realize much benefit for the QPP instruction since the inherent page program time
is much greater than the time it take to clock-in the data.
To use QPP, the Quad Enable Bit in the Configuration Register must be set (QUAD = 1). A Write Enable
instruction must be executed before the device will accept the Quad Page Program instruction (Status
Register-1, WEL = 1). The instruction is initiated by driving the CS# pin low then shifting the instruction code
“32h” followed by a 24 bit address (A23-A0) and at least one data byte, into the IO pins. The CS# pin must be
held low for the entire length of the instruction while data is being sent to the device. All other functions of
Quad Input Page Program are identical to standard Page Program. The QPP instruction sequence is shown
below.
Figure 9.18 QUAD Page Program Instruction Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCK
24 Bit
Address
Instruction
3
2
0
1
SI/IO0
0
4
5
6
1
0
4
5
4
5
6
22 21
0
1
0
1
23
4
5
*
1
2
3
SO/IO1
W#/ACC/IO2
2
6
6
2
2
3
7
7
3
3
7
HOLD#/IO3
7
*
*
*
*
Byte 1 Byte 2
Byte 3
Byte 4
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK
SI/IO0
0
0
0
0
4
5
4
5
0
0
0
4
5
4
5
4
5
4
5
0
4
5
0
0
0
4
5
4
5
4
5
4
5
0
4
5
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
SO/IO1
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
W#/ACC/IO2
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
HOLD#/IO3
7
*
*
*
*
*
*
*
*
*
*
*
*
Byte 5
Byte 6
Byte 7
Byte 8 Byte 9 Byte 10 Byte 11 Byte 12
Byte 253 Byte 254 Byte 255 Byte 256
*MSB
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9.16 Parameter Sector Erase (P4E, P8E) (only applicable for the uniform 64 KB
sector device)
The Parameter Sector Erase (P4E, P8E) command sets all bits at all addresses within a specified sector to a
logic 1 (FFh). A WREN command is required prior to writing the Parameter Sector Erase commands.
The host system must drive CS# low, and then write the P4E or P8E command, plus three address bytes on
SI. Any address within the sector (see Table 5.1 on page 12) is a valid address for the P4E or P8E command.
CS# must be driven low for the entire duration of the P4E/P8E sequence. The command sequence is shown
in Figure 9.19 and Table 9.1 on page 25.
The host system must drive CS# high after the device has latched the 24th bit of the P4E/P8E address,
otherwise the device does not execute the command. The parameter sector erase operation begins as soon
as CS# is driven high. The device internally controls the timing of the operation, which requires a period of
t
. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the
SE
parameter sector erase operation is in progress. The WIP bit is 1 during the P4E/P8E operation, and is 0
when the operation is completed. The device internally resets the Write Enable Latch to 0 before the
operation completes (the exact timing is not specified).
A Parameter Sector Erase (P4E, P8E) instruction applied to a sector that has been Write Protected through
the Block Protect Bits will not be executed.
The Parameter Sector Erase Command (P8E) erases two of the 4 KB Sectors in selected address space.
The Parameter Sector Erase Command (P8E) erases two sequential 4 KB Parameter Sectors in the selected
address space. The address LSB is disregarded so that two sequential 4 KB Parameter Sectors are erased.
The 24 Bit Address is any location within the first Sector to be erased (n), and the next sequential 4 KB
Parameter Sector will also be erased (n+1). The 4 KB parameter Sector will only be erased properly if n or
n+1 is a valid 4 KB parameter Sector. i.e. If n is not a valid 4K parameter Sector, then it will not be erased. If
n+1 is not a valid 4 KB parameter Sector, then it will not be erased.
Note: The P4E and P8E commands do not apply to the uniform 256 KB sector device.
Figure 9.19 Parameter Sector Erase (P4E, P8E) Instruction Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCK
SI
Instruction
24 Bit Address
23
3
2
1
0
22 21
20h or 40h
MSB
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9.17 Sector Erase (SE)
The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN
command is required prior to writing the SE command.
The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any
address within the sector (see Table 7.3 on page 17) is a valid address for the SE command. CS# must be
driven low for the entire duration of the SE sequence. The command sequence is shown in Figure 9.20 and
Table 9.1 on page 25.
The host system must drive CS# high after the device has latched the 24th bit of the SE address, otherwise
the device does not execute the command. The SE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t . The Status Register may
SE
be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP
bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device only executes a SE command for those sectors which are not protected by the Block Protect bits
(BP2:BP0) (see Table 7.3 on page 17). Otherwise, the device ignores the command.
A 64 KB sector erase (D8h) command issued on 4 KB or 8 KB erase sectors will erase all sectors in the
specified 64 KB region. However, please note that a 4 KB sector erase (20h) or 8 KB sector erase (40h)
command will not work on a 64 KB sector.
Figure 9.20 Sector Erase (SE) Command Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
Mode 3
SCK
Mode 0
Command
24 bit Address
1
SI
23 22 21
MSB
3
2
0
Hi-Z
SO
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9.18 Bulk Erase (BE)
The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command
is required prior to writing the BE command.
The host system must drive CS# low, and then write the BE command on SI. CS# must be driven low for the
entire duration of the BE sequence. The command sequence is shown in Figure 9.21 and Table 9.1
on page 25.
The host system must drive CS# high after the device has latched the 8th bit of the CE command, otherwise
the device does not execute the command. The BE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t . The Status Register may
BE
be read to check the value of the Write In Progress (WIP) bit while the BE operation is in progress. The WIP
bit is 1 during the BE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see Table 7.3
on page 17). Otherwise, the device ignores the command.
Figure 9.21 Bulk Erase (BE) Command Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Command
SI
Hi-Z
SO
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9.19 Deep Power-Down (DP)
The Deep Power-Down (DP) command provides the lowest power consumption mode of the device. It is
intended for periods when the device is not in active use, and ignores all commands except for the Release
from Deep Power-Down (RES) command. The DP mode therefore provides the maximum data protection
against unintended write operations. The standard standby mode, which the device goes into automatically
when CS# is high (and all operations in progress are complete), should generally be used for the lowest
power consumption when the quickest return to device activity is required.
The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the
entire duration of the DP sequence. The command sequence is shown in Figure 9.22 and Table 9.1
on page 25.
The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise
the device does not execute the command. After a delay of t the device enters the DP mode and current
DP,
reduces from I to I (see Table 16.1 on page 58).
SB
DP
Once the device has entered the DP mode, all commands are ignored except the RES command (which
releases the device from the DP mode). The RES command also provides the Electronic Signature of the
device to be output on SO, if desired (see Section 9.20 and 9.20.1).
DP mode automatically terminates when power is removed, and the device always powers up in the standard
standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write
Registers operation, and continues the operation uninterrupted.
Figure 9.22 Deep Power-Down (DP) Command Sequence
CS#
t
DP
0
1
2
3
4
5
6
7
Mode 3
SCK
Mode 0
Command
SI
Hi-Z
SO
Standby Mode
Deep Power-down Mode
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9.20 Release from Deep Power-Down (RES)
The device requires the Release from Deep Power-Down (RES) command to exit the Deep Power-Down
mode. When the device is in the Deep Power-Down mode, all commands except RES are ignored.
The host system must drive CS# low and write the RES command to SI. CS# must be driven low for the entire
duration of the sequence. The command sequence is shown in Figure 9.23 and Table 9.1 on page 25.
The host system must drive CS# high t
after the 8-bit RES command byte. The device transitions
RES(max)
from DP mode to the standby mode after a delay of t
can execute any read or write command.
(see Figure 18.1). In the standby mode, the device
RES
Note: The RES command dose not reset the Write Enable Latch (WEL) bit.
Figure 9.23 Release from Deep Power-Down (RES) Command Sequence
CS#
7
0
2
3
5
1
4
6
Mode 3
SCK
Mode 0
tRES
Command
SI
Hi-Z
SO
Deep Power-down Mode
Standby Mode
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D a t a S h e e t
9.20.1
Release from Deep Power-Down and Read Electronic Signature (RES)
The device features an 8-bit Electronic Signature, which can be read using the RES command. See
Figure 9.24 and Table 9.1 on page 25 for the command sequence and signature value. The Electronic
Signature is not to be confused with the identification data obtained using the RDID command. The device
offers the Electronic Signature so that it can be used with previous devices that offered it; however, the
Electronic Signature should not be used for new designs, which should read the RDID data instead.
After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each
bit is latched on SI during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is
shifted out on the falling edge of SCK. The RES operation is terminated by driving CS# high after the
Electronic Signature is read at least once. Additional clock cycles on SCK with CS# low cause the device to
output the Electronic Signature repeatedly.
When CS# is driven high, the device transitions from DP mode to the standby mode after a delay of t
, as
RES
previously described. The RES command always provides access to the Electronic Signature of the device
and can be applied even if DP mode has not been entered.
Any RES command issued while an erase, program, or Write Registers operation is in progress not executed,
and the operation continues uninterrupted.
Note: The RES command does not reset the Write Enable Latch (WEL) bit.
Figure 9.24 Release from Deep Power-Down and RES Command Sequence
CS#
2
28 29 30
31 32 33 34
1
8
36 37
35
9
38 39
0
3
4
5
6
7
10
SCK
t
RES
3 Dummy Bytes
Command
SI
3
1
0
2
23 22
MSB
21
Electronic ID
Hi-Z
7
6
5
4
3
2
1
0
SO
MSB
Deep Power-Down Mode
Standby Mode
9.21 Clear Status Register (CLSR)
The Clear Status Register command resets bit SR5 (Erase Fail Flag) and bit SR6 (Program Fail Flag). It is not
necessary to set the WEL bit before the Clear SR Fail Flags command is executed. The WEL bit will be
unchanged after this command is executed.
Figure 9.25 Clear Status Register (CLSR) Instruction Sequence
CS#
0
1
2
3
4
5
6
7
SCK
SI
Instruction
50
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9.22 OTP Program (OTPP)
The OTP Program command programs data in the OTP region, which is in a different address space from the
main array data. Refer to OTP Regions on page 52 for details on the OTP region. The protocol of the OTP
Program command is the same as the Page Program command, except that the OTP Program command
requires exactly one byte of data; otherwise, the command will be ignored. To program the OTP in bit
granularity, the rest of the bits within the data byte can be set to “1”.
The OTP memory space can be programmed one or more times, provided that the OTP memory space is not
locked (as described in “Locking OTP Regions”). Subsequent OTP programming can be performed only on
the unprogrammed bits (that is, “1” data).
Note: The Write Enable (WREN) command must precede the OTPP command before programming of the
OTP can occur.
Figure 9.26 OTP Program Instruction Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCK
SI
24 Bit
Instruction
Data Byte 1
Address
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
9.23 Read OTP Data Bytes (OTPR)
The Read OTP Data Bytes command reads data from the OTP region. Refer to “OTP Regions” for details on
the OTP region. The protocol of the Read OTP Data Bytes command is the same as the Fast Read Data
Bytes command except that it will not wrap to the starting address after the OTP address is at its maximum;
instead, the data will be indeterminate.
Figure 9.27 Read OTP Instruction Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
24 Bit
Address
Instruction
Dummy Byte
SI
23 22 21
3
2
1
0
7
6
5
4
3
2
1
0
DATA OUT 1
DATA OUT 2
High Impedance
SO
7
6
5
4
3
2
1
0
7
MSB
MSB
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10. OTP Regions
The OTP Regions are separately addressable from the main array and consists of two 8-byte (ESN), thirty
16-byte, and one 10-byte regions that can be individually locked.
The two 8-byte ESN region is a special order part (please contact your local Spansion sales representative
for further details). The two 8-byte regions enable permanent part identification through an Electronic
Serial Number (ESN). The customer can utilize the ESN to pair a Flash device with the system CPU/ASIC
to prevent system cloning. The Spansion factory programs and locks the lower 8-byte ESN with a 64-bit
randomly generated, unique number. The upper 8-byte ESN is left blank for customer use or, if special
ordered, Spansion can program (and lock) in a unique customer ID.
Lock Register ESN1
(Bit 0)
Lock Register ESN2
(Bit 1)
ESN1 Region Contains
0h
ESN2 Region Contains
Standard part
1h
1h
1h
0h
Factory/Customer
programmed pattern
Special order part
1h/0h
Unique random pattern
The thirty 16-byte and one 10-byte OTP regions are open for the customer usage.
The thirty 16-byte, one 10-byte, and upper 8-byte ESN OTP regions can be individually locked by the end
user. Once locked, the data cannot changed. The locking process is permanent and cannot be undone.
The following general conditions should be noted with respect to the OTP Regions:
On power-up, or following a hardware reset, or at the end of an OTPP or an OTPR command, the device
reverts to sending commands to the normal address space.
Reads or Programs outside of the OTP Regions will be ignored
The OTP Region is not accessible when the device is executing an Embedded Program or Embedded
Erase algorithm.
The ACC function is not available when accessing the OTP Regions.
The thirty 16-byte and one 10-byte OTP regions are left open for customer usage, but special care of the
OTP locking must be maintained, or else a malevolent user can permanently lock the OTP regions. This is
not a concern, if the OTP regions are not used.
10.1 Programming OTP Address Space
The protocol of the OTP Program command (42h) is the same as the Page Program command. Refer to
Table 9.1 for the command description and protocol. The OTP Program command can be issued multiple
times to any given OTP address, but this address space can never be erased. After a given OTP region is
programmed, it can be locked to prevent further programming with the OTP lock registers (refer to
Section 10.3). The valid address range for OTP Program is depicted in the figure below. OTP Program
operations outside the valid OTP address range will be ignored.
10.2 Reading OTP Data
The protocol of the OTP Read command (4Bh) is the same as that of the Fast Read command. Refer to
Table 9.1 for the command description and protocol. The valid address range for OTP Reads is depicted in
the figure below. OTP Read operations outside the valid OTP address range will yield indeterminate data.
10.3 Locking OTP Regions
In order to permanently lock the ESN and OTP regions, individual bits at the specified addresses can be set
to 1 to lock specific regions of OTP memory, as highlighted in Figures 10.1 and 10.2.
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Figure 10.1 OTP Memory Map - Part 1
ADDRESS
0x213h
OTP REGION
16 bytes (OTP16)
0x204h
0x203h
16 bytes (OTP15)
16 bytes (OTP14)
16 bytes (OTP13)
16 bytes (OTP12)
16 bytes (OTP11)
16 bytes (OTP10)
16 bytes (OTP9)
16 bytes (OTP8)
16 bytes (OTP7)
16 bytes (OTP6)
16 bytes (OTP5)
16 bytes (OTP4)
16 bytes (OTP3)
16 bytes (OTP2)
16 bytes (OTP1)
0x1F4h
0x1F3h
0x1E4h
0x1E3
0x1D4h
0x1D3h
0x1C4h
0x1C3h
0x1B4h
0x1B3h
0x1A4h
0x1A3h
0x194h
0x193h
0x184h
0x183h
0x174h
0x173h
0x164h
0x163h
0x154h
0x153h
Address
0x112h
Bit
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
Locks Region…
OTP1
0x144h
0x143h
OTP2
OTP3
OTP4
OTP5
OTP6
OTP7
OTP8
OTP9
OTP10
OTP11
OTP12
OTP13
OTP14
OTP15
OTP16
ESN1
0x134h
0x133h
0x124h
0x123h
0x113h
0x114h
0x113h
0x112h
0x111h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
8 bytes (ESN2)
0x10Ah
0x109h
8 bytes (ESN1)
Reserved
0x100h
0x102h
0x101h
0x100h
1
ESN2
Reserved
X
X
X
X
X
X
Bit 1 Bit 0
2 - 7
Notes
1. Bit 0 at address 0x100h locks ESN1 region.
2. Bit 1 at address 0x100h locks ESN2 region.
3. Bits 2-7 (“X”) are NOT programmable and will be ignored.
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Figure 10.2 OTP Memory Map - Part 2
ADDRESS
OTP REGION
0x2FFh
10 bytes (OTP31)
16 bytes (OTP30)
16 bytes (OTP29)
16 bytes (OTP28)
16 bytes (OTP27)
16 bytes (OTP26)
16 bytes (OTP25)
16 bytes (OTP24)
16 bytes (OTP23)
16 bytes (OTP22)
16 bytes (OTP21)
16 bytes (OTP20)
16 bytes (OTP19)
16 bytes (OTP18)
0x2F6h
0x2F5h
0x2E6h
0x2E5
0x2D6h
0x2D5h
0x2C6h
0x2C5h
0x2B6h
0x2B5h
0x2A6h
0x2A5h
0x296h
0x295h
0x286h
0x285h
0x276h
0x275h
0x266h
0x265h
Address
0x214h
Bit Locks Region…
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
OTP17
OTP18
OTP19
OTP20
OTP21
OTP22
OTP23
OTP24
OTP25
OTP26
OTP27
OTP28
OTP29
OTP30
OTP31
0x256h
0x255h
0x246h
0x245h
0x236h
0x235h
0x215h
0x226h
0x225h
16 bytes (OTP17)
0x216h
0x215h
0x214h
X
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved
Note
1. Bit 7 (“X”) at address 0x215h is NOT programmable and will be ignored.
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11. Power-up and Power-down
During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied
on V , and must not be driven low to select the device until V reaches the allowable values as follows
CC
CC
(see Figure 11.1 and Table 11.1 on page 56):
At power-up, V (min.) plus a period of t
CC
PU
At power-down, GND
A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements.
No Read, Write Registers, program, or erase command should be sent to the device until V rises to the
CC
V
min., plus a delay of t . At power-up, the device is in standby mode (not Deep Power-Down mode) and
CC
PU
the WEL bit is reset (0).
Each device in the host system should have the V rail decoupled by a suitable capacitor close to the
CC
package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the V feed.
CC
When V drops from the operating voltage to below the minimum V threshold at power-down, all
CC
CC
operations are disabled and the device does not respond to any commands. Note that data corruption may
result if a power-down occurs while a Write Registers, program, or erase operation is in progress.
Figure 11.1 Power-Up Timing Diagram
Vcc
(max)
cc
V
(min)
cc
V
tPU
Full Device Access
Time
Figure 11.2 Power-down and Voltage Drop
V
CC
(max)
V
CC
No Device Access Allowed
(min)
V
CC
Device Access
Allowed
t
PU
(cut-off)
V
CC
(low)
V
CC
t
PD
time
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Table 11.1 Power-Up / Power-Down Voltage and Timing
Symbol
VCC(min)
CC(cut-off)
Parameter
VCC (minimum operation voltage)
Min
2.7
2.4
Max
Unit
V
V
VCC (Cut off where re-initialization is needed)
V
0.2
2.3
V
VCC (Low voltage for initialization to occur at read/standby)
VCC (Low voltage for initialization to occur at embedded)
V
CC(low)
tPU
VCC(min.) to device operation
VCC (low duration time)
300
1.0
µs
µs
TPD
12. Initial Delivery State
The device is delivered with the memory array erased i.e. all bits are set to 1 (FFh) upon initial factory
shipment. The Status Register and Configuration Register contains 00h (all bits are set to 0).
The Lock Register (address 0x100h) is written to 0x01 and ESN1 (addresses 0x102h-0x109h) are written
with a 64-bit randomly generated, unique number (taken from Section 10. on page 52).
13. Program Acceleration via W#/ACC Pin
The program acceleration function requires applying V to the W#/ACC input, and then waiting a period of
HH
t
. Minimum t
rise and fall times is required for W#/ACC to change to V from V or V . Removing
WC
VHH HH IL IH
V
from the W#/ACC pin returns the device to normal operation after a period of t
.
HH
WC
Figure 13.1 ACC Program Acceleration Timing Requirements
V
HH
ACC
t
t
WC
WC
V
or V
IH
V
or V
IH
IL
IL
Command OK
t
VHH
t
VHH
Note
Only Read Status Register (RDSR) and Page Program (PP) operation are allow when ACC is at (VHH).
The W#/ACC pin is disabled during Quad I/O mode.
Table 13.1 ACC Program Acceleration Specifications
Symbol
VHH
Parameter
ACC Pin Voltage High
Min.
8.5
2.2
5
Max
Unit
9.5
V
tVHH
ACC Voltage Rise and Fall time
µs
µs
tWC
ACC at VHH and VIL or VIH to First command
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14. Electrical Specifications
14.1 Absolute Maximum Ratings
Description
Rating
-65°C to +150°C
-0.5V to VCC+0.5V
200 mA
Ambient Storage Temperature
Voltage with Respect to Ground: All Inputs and I/Os
Output Short Circuit Current (2)
Note
1. Minimum DC voltage on input or I/Os is -0.5V. During voltage transitions, inputs or I/Os may undershoot GND to -2.0V for periods of up to
20 ns. See Figure 14.1. Maximum DC voltage on input or I/Os is VCC + 0.5V. During voltage transitions inputs or I/Os may overshoot to
VCC + 2.0V for periods up to 20 ns. See Figure 14.2.
2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
3. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 14.1 Maximum Negative Overshoot Waveform
20 ns
20 ns
+0.8V
–0.5V
–2.0V
20 ns
Figure 14.2 Maximum Positive Overshoot Waveform
20 ns
VCC
+2.0V
VCC
+0.5V
2.0V
20 ns
20 ns
15. Operating Ranges
Table 15.1 Operating Ranges
Description
Rating
Industrial
–40°C to +85°C
–40°C to +105°C
2.7V to 3.6V
Ambient Operating Temperature (TA)
Automotive In-Cabin
Voltage Range
Positive Power Supply
Note
Operating ranges define those limits between which functionality of the device is guaranteed.
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16. DC Characteristics
This section summarizes the DC Characteristics of the device. Designers should check that the operating
conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 17.1
on page 59, when relying on the quoted parameters.
Table 16.1 DC Characteristics (CMOS Compatible)
Limits
Symbol
Parameter
Supply Voltage
Test Conditions
Unit
Min.
Typ*
Max
VCC
VHH
2.7
3.6
V
V
ACC Program Acceleration
Voltage
VCC = 2.7V to 3.6V
8.5
9.5
VIL
VIH
Input Low Voltage
Input High Voltage
-0.3
0.3 x VCC
V
V
0.7 x VCC
VCC +0.5
0.4
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 1.6 mA, VCC = VCC min.
IOH = -0.1 mA
V
V
VCC-0.6
V
CC = VCC Max,
ILI
Input Leakage Current
Output Leakage Current
2
2
µA
µA
V
IN = VCC or GND
V
CC = VCC Max,
ILO
V
IN = VCC or GND
At 80 MHz
(Dual or Quad)
38
Active Power Supply Current -
READ
(SO = Open)
ICC1
mA
At 104 MHz (Serial)
At 40 MHz (Serial)
25
12
Active Power Supply Current
(Page Program)
ICC2
ICC3
ICC4
ICC5
CS# = VCC
CS# = VCC
CS# = VCC
CS# = VCC
26
15
mA
mA
mA
mA
µA
Active Power Supply Current
(WRR)
Active Power Supply Current
(SE)
26
Active Power Supply Current
(BE)
26
Standby Current (Industrial
Temperature Range Parts)
80
80
3
200
CS# = VCC
;
ISB1
Standby Current
(Automotive In-Cabin
Temperature Range Parts)
SO + VIN = GND or VCC
250
10
µA
µA
CS# = VCC
;
IPD
Deep Power-down Current
SO + VIN = GND or VCC
*Typical values are at TAI = 25°C and VCC = 3V
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17. Test Conditions
Figure 17.1 AC Measurements I/O Waveform
0.8 VCC
Input Levels
0.2 VCC
0.7 VCC
0.5 VCC
0.3 VCC
Input and Output
Timing Reference levels
Table 17.1 Test Specifications
Symbol
Parameter
Min
Max
Unit
pF
ns
V
CL
Load Capacitance
30
Input Rise and Fall Times
Input Pulse Voltage
5
0.2 VCC to 0.8 VCC
0.3 VCC to 0.7 VCC
0.5 VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
V
V
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18. AC Characteristics
Figure 18.1 AC Characteristics
Symbol
(Notes)
Parameter
(Notes)
Min.
(Notes)
Typ
(Notes)
Max
(Notes)
Unit
MHz
MHz
SCK Clock Frequency for READ command
SCK Clock Frequency for RDID command
DC
DC
40
50
fR
SCK Clock Frequency for all others:
FAST_READ, PP, QPP, P4E, P8E, SE, BE, DP,
RES, WREN, WRDI, RDSR, WRR, READ_ID
104 (serial)
80 (dual/quad)
fC
DC
MHz
t
WH, tCH (5)
Clock High Time
4.5
4.5
0.1
0.1
ns
ns
t
WL, tCL (5)
CRT, tCLCH
CFT, tCHCL
Clock Low Time
t
Clock Rise Time (slew rate)
Clock Fall Time (slew rate)
V/ns
V/ns
t
10
50
CS# High Time (Read Instructions)
CS# High Time (Program/Erase)
tCS
ns
tCSS
tCSH
tSU:DAT
tHD:DAT
CS# Active Setup Time (relative to SCK)
CS# Active Hold Time (relative to SCK)
Data in Setup Time
3
3
3
2
ns
ns
ns
ns
Data in Hold Time
8 (Serial)Δ
9.5 (Dual/Quad)Δ
6.5 (Serial)∞
8 (Dual/Quad)∞
7 (Dual/Quad)Ω
tV
Clock Low to Output Valid
Output Hold Time
0
2
ns
tHO
ns
tDIS
tHLCH
tCHHH
tHHCH
tCHHL
tHZ
Output Disable Time
8
ns
ns
ns
ns
ns
ns
ns
ns
HOLD# Active Setup Time (relative to SCK)
HOLD# Active Hold Time (relative to SCK)
HOLD# Non Active Setup Time (relative to SCK)
HOLD# Non Active Hold Time (relative to SCK)
HOLD# enable to Output Invalid
3
3
3
3
8
8
tLZ
HOLD# disable to Output Valid
tWPS
W#/ACC Setup Time (4)
20
tWPH
tW
tPP
tEP
W#/ACC Hold Time (4)
100
ns
ms
ms
ms
sec
sec
ms
sec
µs
WRR Cycle Time
50
3
Page Programming (1)(2)
1.5
1.2
0.5
2
Page Programming (ACC = 9V) (1)(2)(3)
Sector Erase Time (64 KB) (1)(2)
Sector Erase Time (256 KB) (1)(2)
Parameter Sector Erase Time (4 KB or 8 KB) (1)(2)
Bulk Erase Time (1)(2)
2.4
2
tSE
8
tPE
tBE
tRES
tDP
tVHH
tWC
200
128
800
256
30
10
Deep Power-down to Standby Mode
Time to enter Deep Power-down Mode
ACC Voltage Rise and Fall time
ACC at VHH and VIL or VIH to first command
µs
2.2
5
µs
µs
Notes
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V; 10,000 cycles; checkerboard data pattern.
2. Under worst-case conditions of 85°C; VCC = 2.7V; 100,000 cycles.
3. Acceleration mode (9V ACC) only in Program mode, not Erase.
4. Only applicable as a constraint for WRR instruction when SRWD is set to a ‘1’.
5. tWH + tWL must be less than or equal to 1/fC.
6. Δ Full Vcc range (2.7 – 3.6V) and CL = 30 pF
7. ∞Regulated Vcc range (3.0 – 3.6V) and CL = 30 pF
8. ΩRegulated Vcc range (3.0 – 3.6V) and CL = 15 pF
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18.1 Capacitance
Symbol
Parameter
Test Conditions
OUT = 0V
IN = 0V
Min
Typ
Max
Unit
Input Capacitance
(applies to SCK, PO7-PO0, SI, CS#)
CIN
V
9.0
12.0
pF
Output Capacitance
(applies to PO7-PO0, SO)
COUT
V
12.0
16.0
pF
Figure 18.2 SPI Mode 0 (0,0) Input Timing
tCS
CS#
SCK
SI
tCSH
tCSS
tCSS
tCSH
tSU:DAT
tCRT
tHD:DAT
tCFT
MSB IN
LSB IN
Hi-Z
SO
Figure 18.3 SPI Mode 0 (0,0) Output Timing
CS#
tWH
SCK
tV
tWL
tDIS
tV
tHO
tHO
SO
LSB OUT
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Figure 18.4 HOLD# Timing
CS#
tHHCH
tHLCH
tCHHL
SCK
SO
tCHHH
tHZ
tLZ
SI
HOLD#
Figure 18.5 Write Protect Setup and Hold Timing during WRR when SRWD = 1
W#
tWPS
tWPH
CS#
SCK
SI
Hi-Z
SO
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19. Physical Dimensions
19.1
SO3 016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width)
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19.2 WSON 8-contact (6 x 8 mm) No-Lead Package (WNF008)
NOTES:
1. DIMENSIONING AND TOLERANCING CONFORMS TO
ASME Y14.5M - 1994.
PACKAGE
WNF008
2. ALL DIMENSIONS ARE IN MILLMETERS.
3. N IS THE TOTAL NUMBER OF TERMINALS.
SYMBOL
MIN
NOM
1.27 BSC.
8
MAX
NOTE
e
N
4
DIMENSION “b” APPLIES TO METALLIZED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL
TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE
OTHER END OF THE TERMINAL, THE DIMENSION “b”
SHOULD NT BE MEASURED IN THAT RADIUS AREA.
3
5
ND
L
4
0.45
0.35
4.70
5.70
0.50
0.55
0.45
4.90
5.90
b
0.40
4
5
ND REFER TO THE NUMBER OF TERMINALS ON D SIDE.
D2
E2
D
4.80
6. MAX. PACKAGE WARPAGE IS 0.05mm.
5.80
7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS.
6.00 BSC
8.00 BSC
0.75
8
9
PIN #1 ID ON TOP WILL BE LASER MARKED.
E
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED
HEAT SINK SLUG AS WELL AS THE TERMINALS.
A
0.70
0.00
0.80
0.05
A1
K
0.02
10 A MAXIMUM 0.15mm PULL BACK (L1) MAY BE PRESENT.
0.20 MIN.
---
L1
0.00
0.15
10
g1015 \ 16-038.30 \ 07.21.11
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19.3 FAB024 — 24-ball Ball Grid Array (6 x 8 mm) package
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19.4 FAC024 — 24-ball Ball Grid Array (6 x 8 mm) package
NOTES:
PACKAGE
JEDEC
FAC024
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASMEY14.5M-1994.
D x E
8.00 mm x 6.00 mm NOM
PACKAGE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
SYMBOL
A
MIN
NOM
---
MAX
NOTE
---
1.20
---
PROFILE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A1
0.25
0.70
---
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
A2
---
0.90
BODY THICKNESS
BODY SIZE
D
8.00 BSC.
6.00 BSC.
5.00 BSC.
3.00 BSC.
6
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
E
BODY SIZE
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MD
ME
N
4
DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE
CROWNS OF THE SOLDER BALLS.
24
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
Øb
e
0.35
0.40
0.45
BALL DIAMETER
1.00 BSC.
0.5/0.5
BALL PITCHL
SD/ SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
J
PACKAGE OUTLINE TYPE
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10 OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3642 F16-038.9 \ 09.10.09
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20. Revision History
Section
Description
Revision 01 (May 26, 2009)
Initial release.
Revision 02 (June 22, 2009)
Quad Page Programming
Corrected description.
Removed the Note in the bottom of the page.
Added Suggested cross setting table.
Configuration Register
Data Protection Modes
Corrected description for Software Protected Mode.
Added Note.
Accelerated Programming Operation
Corrected description.
Read Identification (RDID)
Added statement for operating clock frequency.
Corrected figure.
Read Status Register (RDSR)
Added statement for operating clock frequency.
Added reference section.
Read Configuration Register (RCR)
Added Note for Hardware Protect Mode.
Write Registers (WRR)
Removed all occurrences of Quad operations.
Corrected description.
Added Note.
Parameter Sector Erase (P4E, P8E)
Sector Erase (SE)
Corrected description.
Added Note.
Release from Deep Power-down
(RES)
Release from Deep Power-down and
Read Electronic Signature (RES)
Added Note.
Corrected description for ESN.
Added ESN table.
OTP Regions
Initial Delivery State
Added description for the Rock Register.
Corrected description of Note.
Added BGA package.
AC Characteristics
Physical Dimensions
Revision 03 (October 14, 2009)
Changed datasheet designation from Advanced Information to Preliminary
Changed all references to RDID clock rate from 40 to 50 MHz
Global
Added note regarding exposed central pad on bottom of package to the WSON connection diagram
Added “5 x 5 pin configuration” to Figure 2.3 title
Connection Diagrams
Added 6 x 4 pin configuration BGA connection diagram
Added 20, 21, 30, and 31 model numbers for BGA packages
Added Automotive In-Cabin temperature ordering option
Added Low-Halogen material option
Ordering Information
Valid Combinations
Changed valid BGA model number combinations to 20, 21, 30, and 31
Changed valid BGA material option to Low-Halogen
Added Automotive In-Cabin temperature valid combinations for all packages
Added Note 2 regarding contact factory for availability of Automotive In-Cabin temperature grade
parts
Physical Dimensions
DC Characteristics
AC Characteristics
Added FAC024 BGA package
Added Note 1 indicating that ICSB1 maximum value only applies to Industrial temperature grade parts
Added min and max values for Sector Erase Time (256 KB)
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D a t a S h e e t
Section
Revision 04 (November 2, 2009)
Ordering Information
Description
Removed Note 2
Added separate Standby Current values for Industrial and Automotive In-Cabin temperature range
parts.
DC Characteristics
Removed Note 1.
Revision 05 (August 12, 2010)
Global
The data sheet went from a “Preliminary” designation to full production.
Sector Address Table
Command Definitions
Read Identification
In Table 8.2, corrected the End Address of SS30 from 01E000h to 01EFFFh.
In Table 9.1, corrected the QIOR one byte command code from 1110 1111 to 1110 1011.
In Table 9.5 added CFI data of bytes 2Dh to 34h for the 256 KB sector products.
Clarified that the device only executes a SE command for those sectors which are not protected by
the Block Protect Bits.
Sector Erase
Operating Ranges
Added the Automotive In-Cabin range.
Revision 06 (October 1, 2010)
Clarified that TBPARM and TBPROT must be selected at the initial configuration of the device, before
any program or erase operations.
Configuration Register
Command Definitions
Sector Erase (SE)
In the Instruction Set table, corrected the CLSR Data Byte Cycle value from 1 to 0.
Clarified that a 64 KB sector erase command will work on 4 KB and 8 KB sectors.
Removed incomplete statement regarding internal state machine.
Clear Status Register
OTP Regions
Clarified that for locking OTP regions, setting the bit refers to changing the value from 0 to 1.
Revision 07 (May 16, 2012)
Global
Added text for recommending FL128S as migration device.
Revision 08 (September 21, 2012)
AC Characteristics
Changed Output Hold Time (tHO) to 2 ns (min).
Physical Dimensions
Revision 09 (January 30, 2013)
Updated the package outline drawing for SO3016 and WSON 6x8 packages.
Added “Typical” values column
Capacitance
Corrected “Max” values for CIN / COUT (Input / Output Capacitance)
68
S25FL129P
S25FL129P_00_09 January 30, 2013
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2009-2013 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™ and
combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used
are for informational purposes only and may be trademarks of their respective owners.
January 30, 2013 S25FL129P_00_09
S25FL129P
69
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