S25FS-S [SPANSION]
MirrorBit Flash Non-Volatile Memory;
| 型号： | S25FS-S |
| 厂家： | 
SPANSION |
| 描述： | MirrorBit Flash Non-Volatile Memory |
| 文件： | 总154页 (文件大小：8507K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S25FS-S Family
MirrorBit® Flash Non-Volatile Memory
1.8-Volt Single Supply with CMOS I/O
Serial Peripheral Interface with Multi-I/O
S25FS128S 128 Mbit (16 Mbyte)
S25FS256S 256 Mbit (32 Mbyte)
S25FS-S Family Cover Sheet
Data Sheet (Preliminary)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S25FS-S_00
Revision 04
Issue Date November 6, 2013
D a t a S h e e t ( P r e l i m i n a r y )
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S25FS-S Family
S25FS-S_00_04 November 6, 2013
S25FS-S Family
MirrorBit® Flash Non-Volatile Memory
1.8-Volt Single Supply with CMOS I/O
Serial Peripheral Interface with Multi-I/O
S25FS128S 128 Mbit (16 Mbyte)
S25FS256S 256 Mbit (32 Mbyte)
Data Sheet (Preliminary)
Features
Density
Security Features
– 128 Mbits (16 Mbytes)
– 256 Mbits (32 Mbytes)
– One-Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against program or
erase of a contiguous range of sectors
– Hardware and software control options
– Advanced Sector Protection (ASP)
Serial Peripheral Interface (SPI)
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 24- or 32-bit address options
– Serial Command subset and footprint compatible with S25FL-A,
S25FL-K, S25FL-P, and S25FL-S SPI families
– Multi I/O Command subset and footprint compatible with S25FL-P,
and S25FL-S SPI families
– Individual sector protection controlled by boot code or password
– Option for password control of read access
Technology
– Spansion 65 nm MirrorBit Technology with Eclipse™ Architecture
Read
Supply Voltage
– Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad I/O
– Modes: Burst Wrap, Continuous (XIP), QPI
– Serial Flash Discoverable Parameters (SFDP) and Common Flash
Interface (CFI), for configuration information
– 1.7V to 2.0V
Temperature Range
– Industrial (0°C to +85°C)
– Automotive (–40°C to +105°C)
Packages (All Pb-Free)
Program
– 256- or 512-byte Page Programming buffer
– Program suspend and resume
– 8-lead SOIC 208 mil (SOC008) - FS128S only
– WSON 6x5 mm (WND008) - FS128S only
– WSON 6x8 mm (WNH008) - FS256S only
– 16-lead SOIC 300 mil (SO3016- FS256S only)
– BGA-24 6x8 mm
– 5x5 ball (FAB024) footprint
– 4x6 ball (FAC024) footprint
– Known Good Die, and Known Tested Die
Erase
– Hybrid sector option
– Physical set of eight 4-kbyte sectors and one 32-kbyte sector at
the top or bottom of address space with all remaining sectors of
64 kbytes
– Uniform sector option
– Uniform 64-kbyte or 256-kbyte blocks for software compatibility
with higher density and future devices
– Erase suspend and resume
– Erase status evaluation
– 100,000 Program-Erase Cycles on any sector, minimum
– 20 Year Data Retention, typical
Publication Number S25FS-S_00
Revision 04
Issue Date November 6, 2013
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual-
ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document
may be revised by subsequent versions or modifications due to changes in technical specifications.
D a t a S h e e t ( P r e l i m i n a r y )
1. Performance Summary
Table 1.1 Maximum Read Rates
Clock Rate
(MHz)
Command
Mbytes / s
Read
50
6.25
16.5
33
Fast Read
Dual Read
Quad Read
133
133
133
66
Table 1.2 Maximum Read Rates DDR
Clock Rate
(MHz)
Command
Mbytes / s
DDR Quad I/O Read
80
80
Table 1.3 Typical Program and Erase Rates
Operation
kbytes / s
Page Programming (256-bytes Page Buffer)
712
1080
28
Page Programming (512-bytes Page Buffer)
4-kbyte Physical Sector Erase (Hybrid Sector Option
64-kbyte Physical Sector Erase (Hybrid Sector Option)
256-kbyte Sector Erase (Uniform Logical Sector Option
450
450
Table 1.4 Typical Current Consumption (–40°C to +85°C)
Operation
Current (mA)
Serial Read 50 MHz
Serial Read 133 MHz
Quad Read 133 MHz
Quad DDR Read 80 MHz
Program
10
20
60
70
60
Erase
60
Standby
0.07
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S25FS-S Family
S25FS-S_00_04 November 6, 2013
D a t a S h e e t ( P r e l i m i n a r y )
Table of Contents
Features
1.
Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
2.2
2.3
2.4
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Migration Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Other Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Hardware Interface
3.
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Input/Output Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Multiple Input / Output (MIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial Clock (SCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chip Select (CS#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial Input (SI) / IO0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial Output (SO) / IO1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Protect (WP#) / IO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
IO3 / RESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Voltage Supply (VDD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10 Supply and Signal Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11 Not Connected (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13 Do Not Use (DNU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.
5.
6.
7.
Signal Protocols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1
4.2
4.3
4.4
4.5
SPI Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Command Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Interface States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Configuration Register Effects on the Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1
5.2
5.3
5.4
5.5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Latch-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power-Up and Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1
6.2
6.3
6.4
6.5
Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SDR AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DDR AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Physical Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.1
7.2
7.3
7.4
SOIC 16-Lead Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8-Connector Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
FAB024 24-Ball BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FAC024 24-Ball BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Software Interface
8. Address Space Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.1
8.2
8.3
8.4
8.5
8.6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Flash Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ID-CFI Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
JEDEC JESD216 Serial Flash Discoverable Parameters (SFDP) Space. . . . . . . . . . . . . . . 57
OTP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
November 6, 2013 S25FS-S_00_04
S25FS-S Family
5
D a t a S h e e t ( P r e l i m i n a r y )
9.
Data Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.1
9.2
9.3
9.4
9.5
Secure Silicon Region (OTP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Write Enable Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Advanced Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Recommended Protection Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.1 Command Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.2 Identification Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
10.3 Register Access Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.4 Read Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
10.5 Program Flash Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
10.6 Erase Flash Array Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
10.7 One-Time Program Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.8 Advanced Sector Protection Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.9 Reset Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11. Embedded Algorithm Performance Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12. Software Interface Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.1 Command Summary by Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.3 Serial Flash Discoverable Parameters (SFDP) Address Map . . . . . . . . . . . . . . . . . . . . . . . 142
12.4 Device ID and Common Flash Interface (ID-CFI) Address Map . . . . . . . . . . . . . . . . . . . . . 143
12.5 Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Ordering Information
13. Ordering Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14. Contacting Spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
15. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6
S25FS-S Family
S25FS-S_00_04 November 6, 2013
D a t a S h e e t ( P r e l i m i n a r y )
Figures
Figure 3.1
Figure 3.2
Figure 3.3
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Figure 4.7
Figure 4.8
Figure 4.9
Bus Master and Memory Devices on the SPI Bus - Single Bit Data Path . . . . . . . . . . . . . . . 21
Bus Master and Memory Devices on the SPI Bus - Dual Bit Data Path . . . . . . . . . . . . . . . . 22
Bus Master and Memory Devices on the SPI Bus - Quad Bit Data Path. . . . . . . . . . . . . . . . 22
SPI SDR Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI DDR Modes Supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Stand Alone Instruction Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Single Bit Wide Input Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Single Bit Wide Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Single Bit Wide I/O Command without Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Single Bit Wide I/O Command with Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Dual I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Quad I/O Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4.10 Quad I/O Read Command in QPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4.11 DDR Quad I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4.12 DDR Quad I/O Read in QPI Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power-Down and Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Waveform Element Meanings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Input, Output, and Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Reset Low at the End of POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Reset High at the End of POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
POR Followed by hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Hardware Reset when Quad Mode is Not Enabled and IO3 / Reset# is Enabled . . . . . . . . . 39
Hardware Reset when Quad Mode and IO3 / Reset# are Enabled. . . . . . . . . . . . . . . . . . . . 40
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6.10 SPI Single Bit Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6.11 SPI Single Bit Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6.12 SPI SDR MIO Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6.13 WP# Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 6.14 SPI DDR Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 6.15 SPI DDR Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 6.16 SPI DDR Data Valid Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Figure 7.5
Figure 7.6
Figure 7.7
Figure 7.8
Figure 7.9
16-Lead SOIC Package (SO3016), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SOIC 16-Lead, 300-mil Body Width (SO3016) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8-Pin Plastic Small Outline Package (SOIC8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8-Connector Package (WSON 6x5), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SOIC 8-Lead, 208 mil Body Width (SOC008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
WSON 8-Contact 6x5 mm Leadless (WND008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
WSON 8-Contact 6x8 mm Leadless (WNH008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
24-Ball BGA, 5x5 Ball Footprint (FAB024), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Ball Grid Array 24-Ball 6x8 mm (FAB024) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 7.10 24-Ball BGA, 4x6 Ball Footprint (FAC024), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 7.11 Ball Grid Array 24-Ball 6 x 8 mm (FAC024). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 8.1
Figure 9.1
Figure 9.2
OTP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Sector Protection Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Advanced Sector Protection Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 10.1 Read Identification (RDID) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 10.2 Read Identification (RDID) QPI Mode Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 10.3 Read Quad Identification (RDQID) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 10.4 RSFDP Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 10.5 RSFDP QPI Mode Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
November 6, 2013 S25FS-S_00_04
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Figure 10.6 Read Status Register 1 (RDSR1) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 10.7 Read Status Register 1 (RDSR1) QPI Mode Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 10.8 Read Status Register 2 (RDSR2) Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 10.9 Read Configuration Register (RDCR) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 10.10 Write Registers (WRR) Command Sequence – 8-Data Bits . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 10.11 Write Registers (WRR) Command Sequence – 16-Data Bits . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 10.12 Write Registers (WRR) Command Sequence – 16-Data Bits QPI Mode. . . . . . . . . . . . . . . . 96
Figure 10.13 Write Enable (WREN) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 10.14 Write Enable (WREN) Command Sequence QPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 10.15 Write Disable (WRDI) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 10.16 Write Disable (WRDI) Command Sequence QPI Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 10.17 Clear Status Register (CLSR) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 10.18 Clear Status Register (CLSR) Command Sequence QPI Mode . . . . . . . . . . . . . . . . . . . . . . 99
Figure 10.19 Program NVDLR (PNVDLR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 10.20 Write VDLR (WVDLR) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 10.21 DLP Read (DLPRD) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 10.22 Enter 4-Byte Address Mode (4BAM B7h) Command Sequence . . . . . . . . . . . . . . . . . . . . . 100
Figure 10.23 Read Any Register Read Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 10.24 Read Any Register, QPI Mode, CR2[7] = 0, Command Sequence . . . . . . . . . . . . . . . . . . . 102
Figure 10.25 Read Any Register, QPI Mode, CR2[7] = 1 Command Sequence. . . . . . . . . . . . . . . . . . . . 102
Figure 10.26 Set Burst Length Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 10.27 Read Command Sequence (3-Byte Address, 03h or 13h) . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 10.28 Fast Read (FAST_READ) Command Sequence (3-Byte Address, 0Bh [CR2V[7]=0). . . . . 106
Figure 10.29 Dual I/O Read Command Sequence (3-Byte Address, BBh [CR2V[7]=0]) . . . . . . . . . . . . . 107
Figure 10.30 Dual I/O Read Command Sequence (4-Byte Address, BBh [CR2V[7]=1]) . . . . . . . . . . . . . 107
Figure 10.31 Dual I/O Continuous Read Command Sequence (4-Byte Address [CR2V[7]=1]) . . . . . . . . 108
Figure 10.32 Quad I/O Read Command Sequence (3-Byte Address, EBh [CR2V[7]=0]). . . . . . . . . . . . . 109
Figure 10.33 Quad I/O Read Command Sequence (3-Byte Address, EBh [CR2V[7]=0]) QPI Mode . . . . 109
Figure 10.34 Continuous Quad I/O Read Command Sequence (3-Byte Address). . . . . . . . . . . . . . . . . . 109
Figure 10.35 Quad I/O Read Command Sequence (4-Byte Address, ECh or EBh [CR2V[7]=1]) . . . . . . 110
Figure 10.36 Continuous Quad I/O Read Command Sequence (4-Byte Address). . . . . . . . . . . . . . . . . . 110
Figure 10.37 Quad I/O Read Command Sequence
(4-Byte Address, ECh or EBh [CR2V[7]=1]) QPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 10.38 DDR Quad I/O Read Initial Access (3-Byte Address, EDh [CR2V[7]=0) . . . . . . . . . . . . . . . 112
Figure 10.39 Continuous DDR Quad I/O Read Subsequent Access (3-Byte Address) . . . . . . . . . . . . . . 112
Figure 10.40 DDR Quad I/O Read Initial Access (4-Byte Address, EEh or EDh [CR2V[7]=1]) . . . . . . . . 112
Figure 10.41 DDR Quad I/O Read Initial Access
(4-Byte Address, EEh or EDh [CR2V[7]=1]) QPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 10.42 Continuous DDR Quad I/O Read Subsequent Access (4-Byte Address) . . . . . . . . . . . . . . 113
Figure 10.43 Page Program (PP 02h or 4PP 12h) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 10.44 Page Program (PP 02h or 4PP 12h) QPI Mode Command Sequence . . . . . . . . . . . . . . . . 114
Figure 10.45 Parameter Sector Erase (P4E 20h or 4P4E 21h) Command Sequence . . . . . . . . . . . . . . . 115
Figure 10.46 Parameter Sector Erase (P4E 20h or 4P4E 21h) QPI Mode Command Sequence . . . . . . 116
Figure 10.47 Sector Erase (SE D8h or 4SE DCh) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 10.48 Sector Erase (SE D8h or 4SE DCh) QPI Mode Command Sequence . . . . . . . . . . . . . . . . 117
Figure 10.49 Bulk Erase Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 10.50 Bulk Erase Command Sequence QPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 10.51 EES Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 10.52 EES QPI Mode Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 10.53 Program or Erase Suspend Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 10.54 Program or Erase Suspend Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 10.55 Program or Erase Suspend Command Sequence QPI Mode . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 10.56 Erase or Program Resume Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 10.57 Erase or Program Resume Command Sequence QPI Mode . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 10.58 ASPRD Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8
S25FS-S Family
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D a t a S h e e t ( P r e l i m i n a r y )
Figure 10.59 ASPP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 10.60 DYBRD Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 10.61 DYBRD QPI Mode Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 10.62 DYBWR Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 10.63 DYBWR QPI Mode Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 10.64 PPBRD Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 10.65 PPBP Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 10.66 PPB Erase Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 10.67 PPB Lock Register Read Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 10.68 PPB Lock Bit Write Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 10.69 Password Read Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 10.70 Password Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 10.71 Password Unlock Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 10.72 Software Reset Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 10.73 Software Reset Command Sequence QPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 10.74 Mode Bit Reset Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 10.75 Mode Bit Reset Command Sequence QPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
November 6, 2013 S25FS-S_00_04
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9
D a t a S h e e t ( P r e l i m i n a r y )
Tables
Table 1.1
Table 1.2
Table 1.3
Table 1.4
Table 2.1
Table 3.1
Table 4.1
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.6
Table 8.7
Table 8.8
Table 8.9
Table 8.5
Table 8.10
Table 8.11
Table 8.12
Table 8.13
Table 8.14
Table 8.15
Table 8.16
Table 8.17
Table 8.18
Table 8.19
Table 8.20
Table 8.21
Table 8.22
Table 8.23
Table 8.24
Table 8.25
Table 8.26
Table 8.27
Table 8.28
Table 8.29
Table 8.30
Table 8.31
Table 8.32
Table 8.33
Table 9.1
Table 9.2
Table 9.3
Table 10.1
Table 10.2
Maximum Read Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Maximum Read Rates DDR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical Program and Erase Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical Current Consumption (–40°C to +85°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Spansion SPI Families Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Interface States Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Latch-Up Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FS-S Power-Up / Power-Down Voltage and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FS-S DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Hardware Reset Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC Characteristics 80 MHz Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
S25FS256S Sector Address Map, Bottom 4-kB Sectors, 64-kB Physical Uniform Sectors . 55
S25FS256S Sector Address Map, Top 4-kB Sectors, 64-kB Physical Uniform Sectors . . . . 55
S25FS256S Sector Address Map, Uniform 64-kB Physical Sectors . . . . . . . . . . . . . . . . . . . 55
S25FS256S Sector Address Map, Bottom 4-kB Sectors, 256-kB Logical Uniform Sectors . 55
S25FS256S Sector Address Map, Uniform 256-kB Logical Sectors . . . . . . . . . . . . . . . . . . . 56
S25FS128S Sector and Memory Address Map, Bottom 4-kB Sectors . . . . . . . . . . . . . . . . . 56
S25FS128S Sector and Memory Address Map, Top 4-kB Sectors . . . . . . . . . . . . . . . . . . . . 56
S25FS128S Sector and Memory Address Map, Uniform 64-kB Blocks . . . . . . . . . . . . . . . . 56
S25FS256S Sector Address Map, Top 4-kB Sectors, 256-kB Logical Uniform Sectors . . . . 56
S25FS128S Sector Address Map, Bottom 4-kB Sectors, 256-kB Logical Uniform Sectors . 57
S25FS128S Sector Address Map, Top 4-kB Sectors, 256-kB Logical Uniform Sectors . . . . 57
S25FS128S Sector and Memory Address Map, Uniform 256-kB Blocks . . . . . . . . . . . . . . . 57
OTP Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Status Register 1 Non-Volatile (SR1NV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Status Register 1 Volatile (SR1V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Status Register 2 Volatile (SR2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Configuration Register 1 Non-Volatile (CR1NV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Configuration Register 1 Volatile (CR1V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Configuration Register 2 Non-Volatile (CR2NV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Latency Code (Cycles) Versus Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Configuration Register 2 Volatile (CR2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Configuration Register 3 Non-Volatile (CR3NV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Configuration Register 3 Volatile (CR3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Configuration Register 4 Non-Volatile (CR4NV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Output Impedance Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Configuration Register 4 Volatile (CR4V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ASP Register (ASPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Password Register (PASS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PPB Lock Register (PPBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PPB Access Register (PPBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DYB Access Register (DYBAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Non-Volatile Data Learning Register (NVDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Volatile Data Learning Register (VDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Upper Array Start of Protection (TBPROT_O = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Lower Array Start of Protection (TBPROT_O = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Sector Protection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
S25FS-S Family Command Set (sorted by function). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Block Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
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Table 10.3
Table 10.4
Table 10.5
Table 11.1
Table 11.2
Table 12.1
Table 12.2
Table 12.3
Table 12.4
Table 12.5
Table 12.6
Table 12.7
Table 12.8
Table 12.9
Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Example Burst Wrap Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Commands Allowed During Program or Erase Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Program and Erase Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Program or Erase Suspend AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
S25FS-S Family Command Set (sorted by instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Status Register 1 Non-Volatile (SR1NV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Status Register 1 Volatile (SR1V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Status Register 2 Volatile (SR2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Configuration Register 1 Non-Volatile (CR1NV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Configuration Register 1 Volatile (CR1V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Configuration Register 2 Non-Volatile (CR2NV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Configuration Register 2 Volatile (CR2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Configuration Register 3 Non-Volatile (CR3NV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 12.10 Configuration Register 3 Volatile (CR3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 12.11 Configuration Register 4 Non-Volatile (CR4NV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 12.12 Configuration Register 4 Volatile (CR4V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 12.13 ASP Register (ASPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 12.14 Password Register (PASS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 12.15 PPB Lock Register (PPBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 12.16 PPB Access Register (PPBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 12.17 DYB Access Register (DYBAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 12.18 Non-Volatile Data Learning Register (NVDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 12.19 Volatile Data Learning Register (VDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 12.20 SFDP Overview Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 12.21 SFDP Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 12.22 Manufacturer and Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 12.23 CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 12.24 CFI System Interface String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 12.25 Device Geometry Definition for Bottom Boot Initial Delivery State . . . . . . . . . . . . . . . . . . . 145
Table 12.26 CFI Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 12.27 CFI Alternate Vendor-Specific Extended Query Header . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 12.28 CFI Alternate Vendor-Specific Extended Query Parameter 0 . . . . . . . . . . . . . . . . . . . . . . . 147
Table 12.29 CFI Alternate Vendor-Specific Extended Query Parameter 80h Address Options . . . . . . . 147
Table 12.30 CFI Alternate Vendor-Specific Extended Query Parameter 84h Suspend Commands. . . . 148
Table 12.31 CFI Alternate Vendor-Specific Extended Query Parameter 88h Data Protection . . . . . . . . 148
Table 12.32 CFI Alternate Vendor-Specific Extended Query Parameter 8Ch Reset Timing. . . . . . . . . . 148
Table 12.33 CFI Alternate Vendor-Specific Extended Query Parameter F0h RFU. . . . . . . . . . . . . . . . . 149
Table 12.34 CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP. . . . . . . . . 149
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2. Overview
2.1
General Description
The Spansion S25FS-S family devices are flash non-volatile memory products using:
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
TheS25FS-S family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single
bit serial input and output (Single I/O or SIO) is supported as well as optional 2-bit (Dual I/O or DIO) and 4-bit
wide Quad I/O (QIO) or Quad Peripheral Interface (QPI) serial commands. This multiple width interface is
called SPI Multi-I/O or MIO. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI
that transfer address and read data on both edges of the clock.
The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512 bytes to be
programmed in one operation, resulting in faster effective programming and erase than prior generation SPI
program or erase algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using S25FS-S family
devices at the higher clock rates supported, with Quad or DDR Quad commands, the instruction read transfer
rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories, while reducing
signal count dramatically.
The S25FS-S family products offer high densities coupled with the flexibility and fast performance required by
a variety of mobile or embedded applications. They are an excellent solution for systems with limited space,
signal connections, and power. They are ideal for code shadowing to RAM, executing code directly (XIP), and
storing reprogrammable data.
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2.2
2.2.1
Migration Notes
Features Comparison
The S25FS-S family is command subset and footprint compatible with prior generation FL-S, FL-K, and FL-P
families. However, the power supply and interface voltages are nominal 1.8V.
Table 2.1 Spansion SPI Families Comparison
Parameter
FS-S
FL-S
65 nm
FL-K
FL-P
Technology Node
65 nm
90 nm
90 nm
Architecture
MirrorBit Eclipse
128 Mb, 256 Mb
x1, x2, x4
MirrorBit Eclipse
128 Mb, 256 Mb, 512 Mb, 1 Gb
x1, x2, x4
Floating Gate
4 Mb - 128 Mb
x1, x2, x4
MirrorBit
Density
32 Mb - 256 Mb
x1, x2, x4
Bus Width
Supply Voltage
1.7V - 2.0V
2.7V - 3.6V / 1.65V - 3.6V V
6 MB/s (50 MHz)
17 MB/s (133 MHz)
26 MB/s (104 MHz)
52 MB/s (104 MHz)
66 MB/s (66 MHz)
256B / 512B
2.7V - 3.6V
2.7V - 3.6V
IO
Normal Read Speed (SDR)
Fast Read Speed (SDR)
Dual Read Speed (SDR)
Quad Read Speed (SDR)
Quad Read Speed (DDR)
Program Buffer Size
Erase Sector Size
Parameter Sector Size
6 MB/s (50 MHz)
16.5 MB/s (133 MHz)
33 MB/s (133 MHz)
66 MB/s (133 MHz)
80 MB/s (80 MHz)
256B / 512B
6 MB/s (50 MHz)
13 MB/s (104 MHz)
26 MB/s (104 MHz)
52 MB/s (104 MHz)
6 MB/s (40 MHz)
13 MB/s (104 MHz)
20 MB/s (80 MHz)
40 MB/s (80 MHz)
256B
4 kB / 32 kB / 64 kB
4 kB
256B
64 kB / 256 kB
4 kB
64 kB / 256 kB
4 kB (option)
64 kB / 256 kB
4 kB (option)
136 kB/s (4 kB)
437 kB/s (64 kB)
Sector Erase Rate (typ.)
500 kB/s
500 kB/s
130 kB/s
170 kB/s
0.71 MB/s (256B)
1.08 MB/s (512B)
1.2 MB/s (256B)
1.5 MB/s (512B)
Page Programming Rate (typ.)
365 kB/s
OTP
1024B
1024B
768B (3x256B)
506B
Advanced Sector Protection
Auto Boot Mode
Yes
Yes
No
No
No
Yes
No
Yes
No
Erase Suspend/Resume
Program Suspend/Resume
Operating Temperature
Yes
Yes
Yes
Yes
No
No
Yes
–40°C to +85°C / +105°C
–40°C to +85°C / +105°C
–40°C to +85°C°
–40°C to +85°C / +105°C
Notes:
1. The 256B program page option only for 128-Mb and 256-Mb density FL-S devices.
2. The FL-P column indicates FL129P MIO SPI device (for 128-Mb density), FL128P does not support MIO, OTP, or 4-kB sectors.
3. 64-kB Sector Erase option only for 128-Mb/256-Mb density FL-P, FL-S and FS-S devices.
4. The FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.
5. 512-Mb/1-Gb FL-S devices support 256-kB sector only.
6. Only 128-Mb/256-Mb density FL-S devices have 4-kB parameter sector option.
7. Refer to individual data sheets for further details.
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2.2.2
Known Differences from Prior Generations
2.2.2.1
Error Reporting
FL-K and FL-P memories either do not have error status bits or do not set them if program or erase is
attempted on a protected sector. The FS-S and FL-S families do have error reporting status bits for program
and erase operations. These can be set when there is an internal failure to program or erase, or when there is
an attempt to program or erase a protected sector. In these cases the program or erase operation did not
complete as requested by the command. The P_ERR or E_ERR bits and the WIP bit will be set to and
remain 1 in SR1V. The clear Status Register command must be sent to clear the errors and return the device
to standby state.
2.2.2.2
2.2.2.3
Secure Silicon Region (OTP)
The FS-S size and format (address map) of the One-Time Program area is different from FL-K and FL-P
generations. The method for protecting each portion of the OTP area is different. For additional details see
Secure Silicon Region (OTP) on page 76.
Configuration Register Freeze Bit
The Configuration Register 1 Freeze bit CR1V[0], locks the state of the Block Protection bits (SR1NV[4:2] and
SR1V[4:2]), TBPARM_O bit (CR1NV[2]), and TBPROT_O bit (CR1NV[5]), as in prior generations. In the
FS-S and FL-S families the Freeze bit also locks the state of the Configuration Register 1 BPNV_O bit
(CR1NV[3]), and the Secure Silicon Region (OTP) area.
2.2.2.4
Sector Erase Commands
The command for erasing a 4-kbyte sector is supported only for use on 4-kbyte parameter sectors at the top
or bottom of the FS-S device address space.
The command for erasing an 8-kbyte area (two 4-kbyte sectors) is not supported.
The command for erasing a 32-kbyte area (eight 4-kbyte sectors) is not supported.
The Sector Erase command (SE) for FS-S 64-kbyte sectors is supported when the configuration option for
uniform 64-kbyte sector is selected or, when the hybrid configuration option for 4-kbyte parameter sectors
with 64-kbyte uniform sectors is used. When the hybrid option is in use, the 64-kbyte erase command may be
used to erase the 32-kbyte of address space adjacent to the group of eight 4-kbyte sectors. The 64-kbyte
erase command in this case is erasing the 64-kbyte sector that is partially overlaid by the group of eight
4-kbyte sectors without affecting the 4-kbyte sectors. This provides erase control over the 32 kbytes of
address space without also forcing the erase of the 4-kbyte sectors. This is different behavior than
implemented in the FL-S family. In the FL-S family, the 64-kbyte Sector Erase command can be applied to a
64-kbyte block of 4-kbyte sectors to erase the entire block of parameter sectors in a single operation. In the
FS-S, the parameter sectors do not fill an entire 64-kbyte block so only the 4-kbyte Parameter Sector Erase
(20h) is used to erase parameter sectors.
The erase command for a 256-kbyte sector replaces the 64-kbyte erase command when the configuration
option for 256-kbyte uniform logical sectors is used.
2.2.2.5
2.2.2.6
Deep Power-Down
The Deep Power-Down (DPD) function is not supported in the FS-S and FL-S family devices.
WRR Single Register Write
In some legacy SPI devices, a Write Registers (WRR) command with only one data byte would update Status
Register 1 and clear some bits in Configuration Register 1, including the Quad Mode bit. This could result in
unintended exit from Quad Mode. The S25FS-S family only updates Status Register 1 when a single data
byte is provided. The Configuration Register 1 is not modified in this case.
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2.2.2.7
Other Legacy Commands Not Supported
Autoboot Related Commands
Bank Address Related Commands
Dual Output Read
Quad Output Read
Quad Page Program (QPP) - replaced by Page Program in QPI Mode
DDR Fast Read
DDR Dual I/O Read
2.2.2.8
New Features
The FS-S family introduces new features to Spansion SPI category memories:
Single 1.8V power supply for core and I/O voltage.
Configurable initial read latency (number of dummy cycles) for faster initial access time or higher clock rate
read commands
Quad Peripheral Interface (QPI, 4-4-4) read mode in which all transfers are 4 bits wide, including
instructions
JEDEC JESD216 standard, Serial Flash Discoverable Parameters (SFDP) that provide device feature and
configuration information.
Evaluate Erase Status command to determine if the last erase operation on a sector completed
successfully. This command can be used to detect incomplete erase due to power loss or other causes.
This command can be helpful to Flash File System software in file system recovery after a power loss.
Advanced Sector Protection (ASP) Permanent Protection. A bit is added to the ASP register to provide the
option to make protection of the Persistent Protection Bits (PPB) permanent. Also, when one of the two
ASP protection modes is selected, all OTP configuration bits in all registers are protected from further
programming so that all OTP configuration settings are made permanent. The OTP address space is not
protected by the selection of an ASP protection mode. The Freeze bit (CR1V[0]) may be used to protect the
OTP Address Space.
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2.3
Glossary
BCD
A value in which each 4-bit nibble represents a decimal numeral.
(Binary Coded Decimal)
All information transferred between the host system and memory during one period while
CS# is low. This includes the instruction (sometimes called an operation code or opcode)
and any required address, mode bits, latency cycles, or data.
Command
DDP
Two die stacked within the same package to increase the memory capacity of a single
package. Often also referred to as a Multi-Chip Package (MCP).
(Dual Die Package)
DDR
When input and output are latched on every edge of SCK.
(Double Data Rate)
The name for a type of Electrical Erase Programmable Read Only Memory (EEPROM)
that erases large blocks of memory bits in parallel, making the erase operation much
faster than early EEPROM.
Flash
High
A signal voltage level ≥ VIH or a logic level representing a binary one (1).
The 8-bit code indicating the function to be performed by a command (sometimes called
an operation code or opcode). The instruction is always the first 8 bits transferred from
host system to the memory in any command.
Instruction
Low
A signal voltage level ≤ VIL or a logic level representing a binary zero (0).
LSB
Generally the right most bit, with the lowest order of magnitude value, within a group of
bits of a register or data value.
(Least Significant Bit)
MSB
Generally the left most bit, with the highest order of magnitude value, within a group of bits
of a register or data value.
(Most Significant Bit)
N/A
A value is not relevant to situation described.
(Not Applicable)
Non-Volatile
No power is needed to maintain data stored in the memory.
Ordering Part Number. The alphanumeric string specifying the memory device type,
density, package, factory non-volatile configuration, etc. used to select the desired device.
OPN
512-byte or 256-byte aligned and length group of data. The size assigned for a page
depends on the Ordering Part Number.
Page
PCB
Printed Circuit Board.
Are in the format: Register_name[bit_number] or Register_name[bit_range_MSB:
bit_range_LSB]
Register Bit References
SDR
When input is latched on the rising edge and output on the falling edge of SCK.
(Single Data Rate)
Erase unit size; depending on device model and sector location this may be 4 kbytes,
64 kbytes or 256 kbytes.
Sector
An operation that changes data within volatile or non-volatile registers bits or non-volatile
flash memory. When changing non-volatile data, an erase and reprogramming of any
unchanged non-volatile data is done, as part of the operation, such that the non-volatile
data is modified by the write operation, in the same way that volatile data is modified – as
a single operation. The non-volatile data appears to the host system to be updated by the
single write command, without the need for separate commands for erase and reprogram
of adjacent, but unaffected data.
Write
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2.4
2.4.1
Other Resources
Links to software
http://www.spansion.com/Support/Pages/Support.aspx
2.4.2
2.4.3
Links to application notes
http://www.spansion.com/Support/TechnicalDocuments/Pages/ApplicationNotes.aspx
Specification Bulletins
Specification bulletins provide information on temporary differences in feature description or parametric
variance since the publication of the last full data sheet. Contact your local sales office for details. Obtain the
latest list of company locations and contact information at:
http://www.spansion.com/About/Pages/Locations.aspx
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Hardware Interface
Serial Peripheral Interface with Multiple Input / Output (SPI-MIO)
Many memory devices connect to their host system with separate parallel control, address, and data signals
that require a large number of signal connections and larger package size. The large number of connections
increase power consumption due to so many signals switching and the larger package increases cost.
The S25FS-S family reduces the number of signals for connection to the host system by serially transferring
all control, address, and data information over 4 to 6 signals. This reduces the cost of the memory package,
reduces signal switching power, and either reduces the host connection count or frees host connectors for
use in providing other features.
The S25FS-S family uses the industry standard single bit Serial Peripheral Interface (SPI) and also supports
optional extension commands for 2-bit (Dual) and 4-bit (Quad) wide serial transfers. This multiple width
interface is called SPI Multi-I/O or SPI-MIO.
3. Signal Descriptions
3.1
Input/Output Summary
Table 3.1 Signal List
Signal Name
SCK
Type
Input
Input
I/O
Description
Serial Clock.
Chip Select.
CS#
SI / IO0
SO / IO1
Serial Input for single bit data commands or IO0 for Dual or Quad commands.
Serial Output for single bit data commands. IO1 for Dual or Quad commands.
I/O
Write Protect when not in Quad Mode (CR1V[1] = 0 and SR1NV[7] = 1).
IO2 when in Quad Mode (CR1V[1] = 1).
The signal has an internal pull-up resistor and may be left unconnected in the host
system if not used for Quad commands or write protection. If write protection is enabled
by SR1NV[7] = 1 and CR1V[1] = 0, the host system is required to drive WP# high or low
during a WRR or WRAR command.
WP# / IO2
I/O
I/O
IO3 in Quad-I/O mode, when Configuration Register 1 QUAD bit, CR1V[1] =1, and CS# is
low.
IO3 /
RESET#
RESET# when enabled by CR2V[5]=1 and not in Quad-I/O mode, CR1V[1] = 0, or when
enabled in Quad Mode, CR1V[1] = 1 and CS# is high.
The signal has an internal pull-up resistor and may be left unconnected in the host
system if not used for Quad commands or RESET#.
VDD
VSS
Supply
Supply
Power Supply.
Ground.
Not Connected. No device internal signal is connected to the package connector nor is
there any future plan to use the connector for a signal. The connection may safely be
used for routing space for a signal on a Printed Circuit Board (PCB). However, any signal
NC
Unused
connected to an NC must not have voltage levels higher than VDD
.
Reserved for Future Use. No device internal signal is currently connected to the
package connector but there is potential future use of the connector for a signal. It is
recommended to not use RFU connectors for PCB routing channels so that the PCB may
take advantage of future enhanced features in compatible footprint devices.
RFU
Reserved
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Spansion for test or other purposes and is not intended for
connection to any host system signal. Any DNU signal related function will be inactive
when the signal is at VIL. The signal has an internal pull-down resistor and may be left
unconnected in the host system or may be tied to VSS. Do not use these connections for
PCB signal routing channels. Do not connect any host system signal to this connection.
DNU
Reserved
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3.2
Multiple Input / Output (MIO)
Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only
on the Serial Input (SI) signal. Data may be sent back to the host serially on the Serial Output (SO) signal.
Dual or Quad Input / Output (I/O) commands send instructions to the memory only on the SI/IO0 signal.
Address or data is sent from the host to the memory as bit pairs on IO0 and IO1 or four bit (nibble) groups on
IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or four bit (nibble)
groups on IO0, IO1, IO2, and IO3.
QPI Mode transfers all instructions, address, and data from the host to the memory as four bit (nibble) groups
on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as four bit (nibble) groups on IO0, IO1, IO2,
and IO3.
3.3
3.4
Serial Clock (SCK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data
input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in
SDR commands, and after every edge in DDR commands.
Chip Select (CS#)
The Chip Select signal indicates when a command is transferring information to or from the device and the
other signals are relevant for the memory device.
When the CS# signal is at the logic high state, the device is not selected and all input signals are ignored and
all output signals are high impedance. The device will be in the Standby Power mode, unless an internal
embedded operation is in progress. An embedded operation is indicated by the Status Register 1
Write-In-Progress bit (SR1V[1]) set to 1, until the operation is completed. Some example embedded
operations are: Program, Erase, or Write Registers (WRR) operations.
Driving the CS# input to the logic low state enables the device, placing it in the Active Power mode. After
power-up, a falling edge on CS# is required prior to the start of any command.
3.5
3.6
3.7
Serial Input (SI) / IO0
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data
to be programmed. Values are latched on the rising edge of serial SCK clock signal.
SI becomes IO0 - an input and output during Dual and Quad commands for receiving instructions, addresses,
and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out
data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
Serial Output (SO) / IO1
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of
the serial SCK clock signal.
SO becomes IO1 - an input and output during Dual and Quad commands for receiving addresses, and data to
be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the
falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
Write Protect (WP#) / IO2
When WP# is driven Low (VIL), during a WRR or WRAR command and while the Status Register Write
Disable (SRWD_NV) bit of Status Register 1 (SR1NV[7]) is set to a 1, it is not possible to write to Status
Register 1 or Configuration Register 1 related registers. In this situation, a WRR command is ignored, a
WRAR command selecting SR1NV, SR1V, CR1NV, or CR1V is ignored, and no error is set.
This prevents any alteration of the Block Protection settings. As a consequence, all the data bytes in the
memory area that are protected by the Block Protection feature are also hardware protected against data
modification if WP# is Low during a WRR or WRAR command with SRWD_NV set to 1.
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The WP# function is not available when the Quad Mode is enabled (CR1V[1]=1). The WP# function is
replaced by IO2 for input and output during Quad Mode for receiving addresses, and data to be programmed
(values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK,
in SDR commands, and on every edge of SCK, in DDR commands).
WP# has an internal pull-up resistance; when unconnected, WP# is at VIH and may be left unconnected in the
host system if not used for Quad Mode or protection.
3.8
IO3 / RESET#
IO3 is used for input and output during Quad Mode (CR1V[1]=1) for receiving addresses, and data to be
programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling
edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
The IO3 / RESET# signal may also be used to initiate the hardware reset function when the reset feature is
enabled by writing Configuration Register 2 non-volatile bit 5 (CR2V[5]=1). The input is only treated as
RESET# when the device is not in Quad-I/O mode, CR1V[1] = 0, or when CS# is high. When Quad I/O mode
is in use, CR1V[1]=1, and the device is selected with CS# low, the IO3 / RESET# is used only as IO3 for
information transfer. When CS# is high, the IO3 / RESET# is not in use for information transfer and is used as
the RESET# input. By conditioning the reset operation on CS# high during Quad Mode, the reset function
remains available during Quad Mode.
When the system enters a reset condition, the CS# signal must be driven high as part of the reset process
and the IO3 / RESET# signal is driven low. When CS# goes high the IO3 / RESET# input transitions from
being IO3 to being the RESET# input. The reset condition is then detected when CS# remains high and the
IO3 / RESET# signal remains low for tRP. If a reset is not intended, the system is required to actively drive
IO3 / Reset# to high along with CS# being driven high at the end of a transfer of data to the memory.
Following transfers of data to the host system, the memory will drive IO3 high during tCS. This will ensure that
IO3 / Reset is not left floating or being pulled slowly to high by the internal or an external passive pull-up.
Thus, an unintended reset is not triggered by the IO3 / RESET# not being recognized as high before the end
of tRP
.
The IO3 / RESET# signal is unused when the reset feature is disabled (CR2V[5]=0).
The IO3 / RESET# signal has an internal pull-up resistor and may be left unconnected in the host system if
not used for Quad Mode or the reset function. The internal pull-up will hold IO3 / RESET high after the host
system has actively driven the signal high and then stops driving the signal.
Note that IO3 / RESET# cannot be shared by more than one SPI-MIO memory if any of them are operating in
Quad I/O mode as IO3 being driven to or from one selected memory may look like a reset signal to a second
non-selected memory sharing the same IO3 / RESET# signal.
3.9
Voltage Supply (V )
DD
VDD is the voltage source for all device internal logic. It is the single voltage used for all device internal
functions including read, program, and erase.
3.10 Supply and Signal Ground (V )
SS
VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output
drivers.
3.11 Not Connected (NC)
No device internal signal is connected to the package connector nor is there any future plan to use the
connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit
Board (PCB).
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3.12 Reserved for Future Use (RFU)
No device internal signal is currently connected to the package connector but there is potential future use of
the connector. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may
take advantage of future enhanced features in compatible footprint devices.
3.13 Do Not Use (DNU)
A device internal signal may be connected to the package connector. The connection may be used by
Spansion for test or other purposes and is not intended for connection to any host system signal. Any DNU
signal related function will be inactive when the signal is at VIL. The signal has an internal pull-down resistor
and may be left unconnected in the host system or may be tied to VSS. Do not use these connections for PCB
signal routing channels. Do not connect any host system signal to these connections.
3.14 Block Diagrams
Figure 3.1 Bus Master and Memory Devices on the SPI Bus - Single Bit Data Path
RESET#
RESET#
WP#
WP#
SI
SO
SI
SO
SCK
SCK
CS2#
CS2#
CS1#
CS1#
FS-S
Flash
FS-S
Flash
SPI
Bus Master
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Figure 3.2 Bus Master and Memory Devices on the SPI Bus - Dual Bit Data Path
RESET#
RESET#
WP#
WP#
IO1
IO1
IO0
IO0
SCK
SCK
CS2#
CS2#
CS1#
CS1#
FS-S
Flash
FS-S
Flash
SPI
Bus Master
Figure 3.3 Bus Master and Memory Devices on the SPI Bus - Quad Bit Data Path
IO3 / RESET#
RESET# / IO3
IO2
IO2
IO1
IO1
IO0
IO0
SCK
SCK
CS1#
CS1#
FS-S
Flash
SPI
Bus Master
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4. Signal Protocols
4.1
4.1.1
SPI Clock Modes
Single Data Rate (SDR)
The S25FS-S family can be driven by an embedded microcontroller (bus master) in either of the two following
clocking modes.
Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0
Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and
the output data is always available from the falling edge of the SCK clock signal.
The difference between the two modes is the clock polarity when the bus master is in standby mode and not
transferring any data.
SCK will stay at logic low state with CPOL = 0, CPHA = 0
SCK will stay at logic high state with CPOL = 1, CPHA = 1
Figure 4.1 SPI SDR Modes Supported
CPOL=0_CPHA=0_SCLK
CPOL=1_CPHA=1_SCLK
CS#
SI
MSB
SO
MSB
Timing diagrams throughout the remainder of the document are generally shown as both Mode 0 and 3 by
showing SCK as both high and low at the fall of CS#. In some cases a timing diagram may show only Mode 0
with SCK low at the fall of CS#. In such a case, Mode 0 timing simply means the clock is high at the fall of
CS# so no SCK rising edge set up or hold time to the falling edge of CS# is needed for Mode 0.
SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In Mode 0
the beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling
edge of SCK because SCK is already low at the beginning of a command.
4.1.2
Double Data Rate (DDR)
Mode 0 and Mode 3 are also supported for DDR commands. In DDR commands, the instruction bits are
always latched on the rising edge of clock, the same as in SDR commands. However, the address and input
data that follow the instruction are latched on both the rising and falling edges of SCK. The first address bit is
latched on the first rising edge of SCK following the falling edge at the end of the last instruction bit. The first
bit of output data is driven on the falling edge at the end of the last access latency (dummy) cycle.
SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to
the next falling edge of SCK. In Mode 0 the beginning of the first SCK cycle in a command is measured from
the falling edge of CS# to the first falling edge of SCK because SCK is already low at the beginning of a
command.
Figure 4.2 SPI DDR Modes Supported
CPOL=0_CPHA=0_SCLK
CPOL=1_CPHA=1_SCLK
CS#
Transfer_Phase
Instruction
Inst. 7
Address
Mode
Dummy / DLP
SI
Inst. 0 A31 A30
A0 M7 M6
M0
SO
DLP7
DLP0
D0 D1
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4.2
Command Protocol
All communication between the host system and S25FS-S family memory devices is in the form of units
called commands.
All commands begin with an 8-bit instruction that selects the type of information transfer or device operation
to be performed. Commands may also have an address, instruction modifier, latency period, data transfer to
the memory, or data transfer from the memory. All instruction, address, and data information is transferred
sequentially between the host system and memory device.
Command protocols are also classified by a numerical nomenclature using three numbers to reference the
transfer width of three command phases:
instruction;
address and instruction modifier (Continuous Read mode bits);
data.
Single bit wide commands start with an instruction and may provide an address or data, all sent only on the SI
signal. Data may be sent back to the host serially on the SO signal. This is referenced as a 1-1-1 command
protocol for single bit width instruction, single bit width address and modifier, single bit data.
Dual or Quad Input / Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and
IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on
IO0 and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. This is referenced as 1-2-2 for Dual I/O
and 1-4-4 for Quad I/O command protocols.
The S25FS-S family also supports a QPI Mode in which all information is transferred in 4-bit width, including
the instruction, address, modifier, and data. This is referenced as a 4-4-4 command protocol.
Commands are structured as follows:
Each command begins with CS# going low and ends with CS# returning high. The memory device is
selected by the host driving the Chip Select (CS#) signal low throughout a command.
The Serial Clock (SCK) marks the transfer of each bit or group of bits between the host and memory.
Each command begins with an 8-bit (byte) instruction. The instruction selects the type of information
transfer or device operation to be performed. The instruction transfers occur on SCK rising edges.
However, some read commands are modified by a prior read command, such that the instruction is implied
from the earlier command. This is called Continuous Read mode. When the device is in Continuous Read
mode, the instruction bits are not transmitted at the beginning of the command because the instruction is
the same as the read command that initiated the Continuous Read mode. In Continuous Read mode the
command will begin with the read address. Thus, Continuous Read mode removes eight instruction bits
from each read command in a series of same type read commands.
The instruction may be stand alone or may be followed by address bits to select a location within one of
several address spaces in the device. The instruction determines the address space used. The address
may be either a 24-bit or a 32-bit, byte boundary, address. The address transfers occur on SCK rising
edge, in SDR commands, or on every SCK edge, in DDR commands.
In legacy SPI mode, the width of all transfers following the instruction are determined by the instruction
sent. Following transfers may continue to be single bit serial on only the SI or Serial Output (SO) signals,
they may be done in two bit groups per (dual) transfer on the IO0 and IO1 signals, or they may be done in
4-bit groups per (quad) transfer on the IO0-IO3 signals. Within the dual or quad groups the least significant
bit is on IO0. More significant bits are placed in significance order on each higher numbered IO signal.
Single bits or parallel bit groups are transferred in most to least significant bit order.
In QPI Mode, the width of all transfers is a 4-bit wide (Quad) transfer on the IO0-IO3 signals.
Dual and Quad I/O read instructions send an instruction modifier called Continuous Read mode bits,
following the address, to indicate whether the next command will be of the same type with an implied,
rather than an explicit, instruction. These mode bits initiate or end the Continuous Read mode. In
Continuous Read mode, the next command thus does not provide an instruction byte, only a new address
and mode bits. This reduces the time needed to send each command when the same command type is
repeated in a sequence of commands. The mode bit transfers occur on SCK rising edge, in SDR
commands, or on every SCK edge, in DDR commands.
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The address or mode bits may be followed by write data to be stored in the memory device or by a read
latency period before read data is returned to the host.
Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR
commands.
SCK continues to toggle during any read access latency period. The latency may be zero to several SCK
cycles (also referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are
driven from the outputs on SCK falling edge at the end of the last read latency cycle. The first read data
bits are considered transferred to the host on the following SCK rising edge. Each following transfer occurs
on the next SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
If the command returns read data to the host, the device continues sending data transfers until the host
takes the CS# signal high. The CS# signal can be driven high after any transfer in the read data sequence.
This will terminate the command.
At the end of a command that does not return data, the host drives the CS# input high. The CS# signal
must go high after the eighth bit, of a stand alone instruction or, of the last write data byte that is
transferred. That is, the CS# signal must be driven high when the number of bits after the CS# signal was
driven low is an exact multiple of eight bits. If the CS# signal does not go high exactly at the eight bit
boundary of the instruction or write data, the command is rejected and not executed.
All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSB) first.
The data bits are shifted in and out of the device MSB first. All data is transferred in byte units with the
lowest address byte sent first. The following bytes of data are sent in lowest to highest byte address order
i.e. the byte address increments.
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded
operations) are ignored. The embedded operation will continue to execute without any affect. A very
limited set of commands are accepted during an embedded operation. These are discussed in the
individual command descriptions.
Depending on the command, the time for execution varies. A command to read status information from an
executing command is available to determine when the command completes execution and whether the
command was successful.
4.2.1
Command Sequence Examples
Figure 4.3 Stand Alone Instruction Command
CS#
SCLK
SI
SO
7
6
5
4
3
2
1
0
Phase
Instruction
Figure 4.4 Single Bit Wide Input Command
CS#
SCLK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Input Data
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D a t a S h e e t ( P r e l i m i n a r y )
Figure 4.5 Single Bit Wide Output Command
CS#
SCLK
SI
7
6
6
6
5
4
3
2
1
0
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
Phase
Instruction
Data1
Data2
Figure 4.6 Single Bit Wide I/O Command without Latency
CS#
SCLK
SI
7
5
4
3
2
1
0
31
1
0
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
Phase
Instruction
Address
Data1
Data2
Figure 4.7 Single Bit Wide I/O Command with Latency
CS#
SCLK
SI
7
5
4
3
2
1
0
31
1
0
SO
7
6
5
4
3
2
1
Phase
Instruction
Address
Dummy Cycles
Data1
Figure 4.8 Dual I/O Command
CS#
SCK
IO0
7
6
5
4
3
2
1
0
30
31
2
3
0
1
6
7
4
5
2
3
0
1
6
4
2
3
0
1
6
7
4
5
2
0
IO1
7
5
3
1
Phase
Instruction
Address
Mode
Dum
Data1
Data2
Figure 4.9 Quad I/O Command
CS#
SCLK
IO0
7
6
5
4
3
2
1
0
28
29
30
31
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
IO1
1
2
3
IO2
IO3
Phase
Instruction
Address Mode
Dummy
D1
D2
D3
D4
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Figure 4.10 Quad I/O Read Command in QPI Mode
CS#
SCLK
IO0
4
5
6
7
0
1
2
3
28
29
30
31
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO1
IO2
IO3
Phase
Instruct.
Address
Mode
Dummy
D1
D2
D3
D4
Figure 4.11 DDR Quad I/O Read
CS#
SCLK
IO0
7
6
5
4
3
2
1
0
28 24 20 16 12 8
29 25 21 17 13 9
4
5
0
1
2
3
4
5
6
7
0
1
2
3
7
6
6
6
6
5
5
5
5
4
4
4
4
3
2
2
2
2
1
0
0
0
0
4
0
1
2
3
4
5
6
7
0
1
2
3
IO1
7
7
7
3
3
3
1
1
1
5
6
7
IO2
30 26 22 18 14 10 6
31 27 23 19 15 11 7
Address
IO3
Phase
Instruction
Mode
Dummy
DLP
D1 D2
Figure 4.12 DDR Quad I/O Read in QPI Mode
CS#
SCLK
IO0
4
5
6
7
0
28 24 20 16 12
29 25 21 17 13
8
9
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
7
7
7
7
6
6
6
6
5
5
5
5
4
3
2
2
2
2
1
0
4
0
1
2
3
4
5
6
7
0
1
2
3
IO1
1
4
4
4
3
3
3
1
1
1
0
0
0
5
6
7
IO2
2
3
30 26 22 18 14 10
31 27 23 19 15 11
Address
IO3
Phase
Instruct.
Mode
Dummy
DLP
D1
D2
Additional sequence diagrams, specific to each command, are provided in Commands on page 85
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4.3
Interface States
This section describes the input and output signal levels as related to the SPI interface behavior.
Table 4.1 Interface States Summary
IO3 /
RESET#
Interface State
V
SCK
CS#
WP# / IO2
SO / IO1
SI / IO0
DD
Power-Off
<V (low)
X
X
X
X
X
X
X
X
Z
Z
Z
Z
Z
Z
Z
X
X
DD
Low-Power Hardware Data Protection
Power-On (Cold) Reset
<V (cut-off)
DD
≥V (min)
X
HH
X
X
X
X
DD
Hardware (Warm) Reset Non-Quad Mode
Hardware (Warm) Reset Quad Mode
Interface Standby
≥V (min)
X
HL
HL
X
X
X
DD
≥V (min)
X
HH
HH
HL
X
X
DD
≥V (min)
X
X
X
DD
Instruction Cycle (Legacy SPI)
≥V (min)
HT
HH
HV
HV
DD
Single Input Cycle
Host to Memory Transfer
≥V (min)
HT
HT
HT
HL
HL
HL
HH
HH
HH
X
X
X
Z
Z
HV
X
DD
Single Latency (Dummy) Cycle
≥V (min)
DD
Single Output Cycle
Memory to Host Transfer
≥V (min)
MV
X
DD
Dual Input Cycle
Host to Memory Transfer
≥V (min)
HT
HT
HT
HL
HL
HL
HH
HH
HH
X
X
X
HV
X
HV
X
DD
Dual Latency (Dummy) Cycle
≥V (min)
DD
Dual Output Cycle
Memory to Host Transfer
≥V (min)
MV
MV
DD
Quad Input Cycle
Host to Memory Transfer
≥V (min)
HT
HT
HT
HL
HL
HL
HV
X
HV
X
HV
X
HV
X
DD
Quad Latency (Dummy) Cycle
≥V (min)
DD
Quad Output Cycle
Memory to Host Transfer
≥V (min)
MV
MV
MV
MV
DD
DDR Quad Input Cycle
Host to Memory Transfer
≥V (min)
HT
HT
HT
HL
HL
HL
HV
MV or Z
MV
HV
MV or Z
MV
HV
MV or Z
MV
HV
MV or Z
MV
DD
DDR Latency (Dummy) Cycle
≥V (min)
DD
DDR Quad Output Cycle
Memory to Host Transfer
≥V (min)
DD
Legend
Z
= No driver - floating signal
HL = Host driving V
HH = Host driving V
IL
IH
HV = Either HL or HH
= HL or HH or Z
HT = Toggling between HL and HH
X
ML = Memory driving V
MH = Memory driving V
MV = Either ML or MH
IL
IH
4.3.1
Power-Off
When the core supply voltage is at or below the VDD (Low) voltage, the device is considered to be powered off.
The device does not react to external signals, and is prevented from performing any program or erase
operation.
4.3.2
Low-Power Hardware Data Protection
When VDD is less than VDD (Cut-off) the memory device will ignore commands to ensure that program and
erase operations can not start when the core supply voltage is out of the operating range.
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4.3.3
4.3.4
4.3.5
Power-On (Cold) Reset
When the core voltage supply remains at or below the VDD (Low) voltage for ≥ tPD time, then rises to ≥ VDD
(Minimum) the device will begin its Power-On Reset (POR) process. POR continues until the end of tPU. During
tPU the device does not react to external input signals nor drive any outputs. Following the end of tPU the
device transitions to the Interface Standby state and can accept commands. For additional information on
POR see Power-On (Cold) Reset on page 38
Hardware (Warm) Reset
A configuration option is provided to allow IO3 to be used as a hardware reset input when the device is not in
Quad Mode or when it is in Quad Mode and CS# is high. When IO3 / RESET# is driven low for tRP time the
device starts the hardware reset process. The process continues for tRPH time. Following the end of both tRPH
and the reset hold time following the rise of RESET# (tRH) the device transitions to the Interface Standby state
and can accept commands. For additional information on hardware reset see Reset on page 38
Interface Standby
When CS# is high the SPI interface is in standby state. Inputs other than RESET# are ignored. The interface
waits for the beginning of a new command. The next interface state is Instruction Cycle when CS# goes low
to begin a new command.
While in interface standby state the memory device draws standby current (ISB) if no embedded algorithm is
in progress. If an embedded algorithm is in progress, the related current is drawn until the end of the
algorithm when the entire device returns to standby current draw.
4.3.6
Instruction Cycle (Legacy SPI Mode)
When the host drives the MSB of an instruction and CS# goes low, on the next rising edge of SCK the device
captures the MSB of the instruction that begins the new command. On each following rising edge of SCK the
device captures the next lower significance bit of the 8-bit instruction. The host keeps CS# low, and drives the
Write Protect (WP#) and IO3/RESET signals as needed for the instruction. However, WP# is only relevant
during instruction cycles of a WRR or WRAR command and is otherwise ignored. IO3/RESET# is driven high
when the device is not in Quad Mode (CR1V[1]=0) or QPI Mode (CR2V[6]=0) and hardware reset is not
required.
Each instruction selects the address space that is operated on and the transfer format used during the
remainder of the command. The transfer format may be Single, Dual I/O, Quad I/O, or DDR Quad I/O. The
expected next interface state depends on the instruction received.
Some commands are stand alone, needing no address or data transfer to or from the memory. The host
returns CS# high after the rising edge of SCK for the eighth bit of the instruction in such commands. The next
interface state in this case is Interface Standby.
4.3.7
4.3.8
Instruction Cycle (QPI Mode)
In QPI Mode, when CR2V[6]=1, instructions are transferred 4 bits per cycle. In this mode, instruction cycles
are the same as a Quad Input Cycle. See Quad Input Cycle - Host to Memory Transfer on page 30.
Single Input Cycle - Host to Memory Transfer
Several commands transfer information after the instruction on the single Serial Input (SI) signal from host to
the memory device. The host keeps RESET# high, CS# low, and drives SI as needed for the command. The
memory does not drive the Serial Output (SO) signal.
The expected next interface state depends on the instruction. Some instructions continue sending address or
data to the memory using additional Single Input Cycles. Others may transition to Single Latency, or directly
to Single, Dual, or Quad Output Cycle states.
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4.3.9
Single Latency (Dummy) Cycle
Read commands may have zero to several latency cycles during which read data is read from the main flash
memory array before transfer to the host. The number of latency cycles are determined by the Latency Code
in the Configuration Register (CR2V[3:0]). During the latency cycles, the host keeps RESET# high, CS# low.
The Write Protect (WP#) signal is ignored. The host may drive the SI signal during these cycles or the host
may leave SI floating. The memory does not use any data driven on SI / I/O0 or other I/O signals during the
latency cycles. The memory does not drive the Serial Output (SO) or I/O signals during the latency cycles.
The next interface state depends on the command structure i.e. the number of latency cycles, and whether
the read is single, dual, or quad width.
4.3.10
4.3.11
4.3.12
Single Output Cycle - Memory to Host Transfer
Several commands transfer information back to the host on the single Serial Output (SO) signal. The host
keeps RESET# high, CS# low. The Write Protect (WP#) signal is ignored. The memory ignores the Serial
Input (SI) signal. The memory drives SO with data.
The next interface state continues to be Single Output Cycle until the host returns CS# to high ending the
command.
Dual Input Cycle - Host to Memory Transfer
The Read Dual I/O command transfers two address or mode bits to the memory in each cycle. The host
keeps RESET# high, CS# low. The Write Protect (WP#) signal is ignored. The host drives address on SI / IO0
and SO / IO1.
The next interface state following the delivery of address and mode bits is a Dual Latency Cycle if there are
latency cycles needed or Dual Output Cycle if no latency is required.
Dual Latency (Dummy) Cycle
Read commands may have zero to several latency cycles during which read data is read from the main flash
memory array before transfer to the host. The number of latency cycles are determined by the Latency Code
in the Configuration Register (CR2V[3:0]). During the latency cycles, the host keeps RESET# high, CS# low.
The Write Protect (WP#) signal is ignored. The host may drive the SI / IO0 and SO / IO1 signals during these
cycles or the host may leave SI / IO0 and SO / IO1 floating. The memory does not use any data driven on
SI / IO0 and SO / IO1 during the latency cycles. The host must stop driving SI / IO0 and SO / IO1 on the
falling edge at the end of the last latency cycle. It is recommended that the host stop driving them during all
latency cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive
at the end of the latency cycles. This prevents driver conflict between host and memory when the signal
direction changes. The memory does not drive the SI / IO0 and SO / IO1 signals during the latency cycles.
The next interface state following the last latency cycle is a Dual Output Cycle.
4.3.13
4.3.14
Dual Output Cycle - Memory to Host Transfer
The Read Dual Output and Read Dual I/O return data to the host two bits in each cycle. The host keeps
RESET# high, CS# low. The Write Protect (WP#) signal is ignored. The memory drives data on the SI / IO0
and SO / IO1 signals during the Dual Output Cycles.
The next interface state continues to be Dual Output Cycle until the host returns CS# to high ending the
command.
Quad Input Cycle - Host to Memory Transfer
The Quad I/O Read command transfers four address or mode bits to the memory in each cycle. In QPI Mode
the Quad I/O Read and Page Program commands transfer four data bits to the memory in each cycle,
including the instruction cycles. The host keeps CS# low, and drives the IO signals.
For Quad I/O Read the next interface state following the delivery of address and mode bits is a Quad Latency
Cycle if there are latency cycles needed or Quad Output Cycle if no latency is required. For QPI Mode Page
Program, the host returns CS# high following the delivery of data to be programmed and the interface returns
to standby state.
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4.3.15
Quad Latency (Dummy) Cycle
Read commands may have zero to several latency cycles during which read data is read from the main flash
memory array before transfer to the host. The number of latency cycles are determined by the Latency Code
in the Configuration Register (CR2V[3:0]). During the latency cycles, the host keeps CS# low. The host may
drive the IO signals during these cycles or the host may leave the IO floating. The memory does not use any
data driven on IO during the latency cycles. The host must stop driving the IO signals on the falling edge at
the end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles so
that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the
latency cycles. This prevents driver conflict between host and memory when the signal direction changes.
The memory does not drive the IO signals during the latency cycles.
The next interface state following the last latency cycle is a Quad Output Cycle.
4.3.16
4.3.17
4.3.18
Quad Output Cycle - Memory to Host Transfer
The Quad I/O Read returns data to the host four bits in each cycle. The host keeps CS# low. The memory
drives data on IO0-IO3 signals during the Quad Output Cycles.
The next interface state continues to be Quad Output Cycle until the host returns CS# to high ending the
command.
DDR Quad Input Cycle - Host to Memory Transfer
The DDR Quad I/O Read command sends address, and mode bits to the memory on all the IO signals. Four
bits are transferred on the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps
CS# low.
The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.
DDR Latency Cycle
DDR Read commands may have one to several latency cycles during which read data is read from the main
flash memory array before transfer to the host. The number of latency cycles are determined by the Latency
Code in the Configuration Register (CR2V[3:0]). During the latency cycles, the host keeps CS# low. The host
may not drive the IO signals during these cycles. So that there is sufficient time for the host drivers to turn off
before the memory begins to drive. This prevents driver conflict between host and memory when the signal
direction changes. The memory has an option to drive all the IO signals with a Data Learning Pattern (DLP)
during the last 4 latency cycles. The DLP option should not be enabled when there are fewer than five latency
cycles so that there is at least one cycle of high impedance for turn around of the IO signals before the
memory begins driving the DLP. When there are more than 4 cycles of latency the memory does not drive the
IO signals until the last four cycles of latency.
The next interface state following the last latency cycle is a DDR Single, or Quad Output Cycle, depending on
the instruction.
4.3.19
DDR Quad Output Cycle - Memory to Host Transfer
The DDR Quad I/O Read command returns bits to the host on all the IO signals. Four bits are transferred on
the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps CS# low.
The next interface state continues to be DDR Quad Output Cycle until the host returns CS# to high ending the
command.
4.4
Configuration Register Effects on the Interface
The Configuration Register 2 volatile bits 3 to 0 (CR2V[3:0]) select the variable latency for all array read
commands except Read and Read SDFP (RSFDP). Read always has zero latency cycles. RSFDP always
has 8 latency cycles. The variable latency is also used in the OTPR, and RDAR commands.
The Configuration Register bit 1 (CR1V[1]) selects whether Quad Mode is enabled to switch WP# to IO2
function, RESET# to IO3 function, and thus allow Quad I/O Read and QPI Mode commands. Quad Mode
must also be selected to allow DDR Quad I/O Read commands.
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4.5
Data Protection
Some basic protection against unintended changes to stored data are provided and controlled purely by the
hardware design. These are described below. Other software managed protection methods are discussed in
the software section of this document.
4.5.1
Power-Up
When the core supply voltage is at or below the VDD (Low) voltage, the device is considered to be powered off.
The device does not react to external signals, and is prevented from performing any program or erase
operation. Program and erase operations continue to be prevented during the Power-On Reset (POR)
because no command is accepted until the exit from POR to the Interface Standby state.
4.5.2
4.5.3
Low Power
When VDD is less than VDD (Cut-off) the memory device will ignore commands to ensure that program and
erase operations can not start when the core supply voltage is out of the operating range.
Clock Pulse Count
The device verifies that all non-volatile memory and register data modifying commands consist of a clock
pulse count that is a multiple of eight bit transfers (byte boundary) before executing them. A command not
ending on an 8-bit (byte) boundary is ignored and no error status is set for the command.
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5. Electrical Specifications
5.1
Absolute Maximum Ratings
Table 5.1 Absolute Maximum Ratings
Storage Temperature Plastic Packages
Ambient Temperature with Power Applied
–65°C to +150°C
–65°C to +125°C
–0.5 V to +2.5V
V
DD
Input voltage with respect to Ground (V ) (Note 1)
SS
–0.5 V to V + 0.5V
DD
Output Short Circuit Current (Note 2)
100 mA
Notes:
1. See Section 5.3.3, Input Signal Overshoot on page 33 for allowed maximums during signal transition.
2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
3. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
5.2
5.3
Latch-Up Characteristics
Table 5.2 Latch-Up Specification
Description
Input voltage with respect to V on all input only connections
Min
-1.0
-1.0
-100
Max
Unit
V
V
V
+ 1.0
SS
DD
DD
Input voltage with respect to V on all I/O connections
+ 1.0
V
SS
V
Current
+100
mA
DD
Note:
1. Excludes power supply V . Test conditions: V = 1.8 V, one connection at a time tested, connections not being tested are at V .
SS
DD
DD
Operating Ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
5.3.1
Power Supply Voltages
VDD ………………………………............................... 1.7V to 2.0V
5.3.2
Temperature Ranges
Industrial (I) Devices
Ambient Temperature (TA)....................................... –40°C to +85°C
Automotive (A) Infotainment Devices
Ambient Temperature (TA)....................................... –40°C to +105°C
Automotive operating and performance parameters will be determined by device characterization and may
vary from standard industrial temperature range devices as currently shown in this specification.
5.3.3
Input Signal Overshoot
During DC conditions, input or I/O signals should remain equal to or between VSS and VDD. During voltage
transitions, inputs or I/Os may overshoot VSS to -1.0V or overshoot to VDD +1.0V, for periods up to 20 ns.
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Figure 5.1 Maximum Negative Overshoot Waveform
VSS to VDD
- 1.0V
≤ 20 ns
Figure 5.2 Maximum Positive Overshoot Waveform
≤ 20 ns
VDD + 1.0V
VSS to VDD
5.4
Power-Up and Power-Down
The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on
VDD) until VDD reaches the correct value as follows:
VDD (min) at power-up, and then for a further delay of tPU
VSS at power-down
A simple pull-up resistor on Chip Select (CS#) can usually be used to insure safe and proper power-up and
power-down.
The device ignores all instructions until a time delay of tPU has elapsed after the moment that VDD rises above
the minimum VDD threshold (see Figure 5.3). However, correct operation of the device is not guaranteed if
VDD returns below VDD (min) during tPU. No command should be sent to the device until the end of tPU
.
The device draws IPOR during tPU. After power-up (tPU), the device is in Standby mode, draws CMOS standby
current (ISB), and the WEL bit is reset.
During power-down or voltage drops below VDD(cut-off), the voltage must drop below VDD(low) for a period of
tPD for the part to initialize correctly on power-up. See Figure 5.4. If during a voltage drop the VDD stays
above VDD(cut-off) the part will stay initialized and will work correctly when VDD is again above VDD(min). In
the event Power-On Reset (POR) did not complete correctly after power-up, the assertion of the RESET#
signal or receiving a software reset command (RESET) will restart the POR process.
Normal precautions must be taken for supply rail decoupling to stabilize the VDD supply at the device. Each
device in a system should have the VDD rail decoupled by a suitable capacitor close to the package supply
connection (this capacitor is generally of the order of 0.1 µf).
Table 5.3 FS-S Power-Up / Power-Down Voltage and Timing
Symbol
(min)
Parameter
(minimum operation voltage)
Min
1.7
1.5
0.7
Max
Unit
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
V
(cut-off)
(Cut 0ff where re-initialization is needed)
(low voltage for initialization to occur)
(min) to Read operation
V
DD
V
(low)
V
DD
t
t
300
µs
µs
PU
PD
(low) time
10.0
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Figure 5.3 Power-Up
VDD (Max)
VDD (Min)
tPU
Full Device Access
Time
Figure 5.4 Power-Down and Voltage Drop
V
(Max)
DD
No Device Access Allowed
V
(Min)
DD
Device
Access Allowed
tPU
V
(Cut-off)
DD
V
(Low)
DD
tPD
Time
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5.5
DC Characteristics
Applicable within operating ranges.
Table 5.4 FS-S DC Characteristics
Symbol
Parameter
Input Low Voltage
Test Conditions
Min
Typ (1)
Max
0.3xV
Unit
V
V
-0.5
IL
IH
DD
V
Input High Voltage
0.7xV
V
+0.4
DD
V
DD
V
Output Low Voltage
Output High Voltage
Input Leakage Current
Output Leakage Current
I
I
= 0.1 mA
0.2
V
OL
OH
OL
V
= –0.1 mA
V
- 0.2
DD
V
OH
I
V
V
= V Max, V = V or V , CS# = V
2
2
µA
µA
LI
DD
DD
DD
IN
IH
SS
IH
I
= V Max, V = V or V , CS# = V
DD IN IH SS
LO
IH
Serial SDR@50 MHz
Serial SDR@133 MHz
Quad SDR@133 MHz
Quad DDR@80 MHz
10
20
60
70
18
30
65
90
Active Power Supply Current
(READ) (2)
I
mA
CC1
Active Power Supply Current
(Page Program)
I
I
CS# = V
CS# = V
60
60
100
100
mA
mA
CC2
DD
DD
Active Power Supply Current
(WRR or WRAR)
CC3
I
I
Active Power Supply Current (SE) CS# = V
Active Power Supply Current (BE) CS# = V
60
60
100
100
mA
mA
CC4
DD
DD
CC5
I
IO3/RESET#, CS# = V ; SI, SCK = V or
DD DD
SB
Standby Current
70
70
100
300
80
µA
µA
(Industrial)
V
, Industrial Temp
SS
I
IO3/RESET#, CS# = V ; SI, SCK = V or
DD DD
SB
Standby Current
(Automotive)
V
, Automotive Temp
SS
IO3/RESET#, CS# = V ; SI,
DD
I
Power-On Reset Current
mA
POR
SCK = V or V
DD
SS
Notes:
1. Typical values are at T = 25°C and V = 1.8V.
AI
DD
2. Outputs unconnected during read data return. Output switching current is not included.
5.5.1
Active Power and Standby Power Modes
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the
device is disabled, but may still be in an Active Power mode until all program, erase, and write operations
have completed. The device then goes into the Standby Power mode, and power consumption drops to ISB
.
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6. Timing Specifications
6.1
Key to Switching Waveforms
Figure 6.1 Waveform Element Meanings
Valid at logic high or low
Input
High Impedance
Any change permitted Logic high Logic low
Symbol
Output Valid at logic high or low
Changing, state unknown
Logic low
High Impedance
Logic high
6.2
AC Test Conditions
Figure 6.2 Test Setup
Device
Under
Test
C
L
Table 6.1 AC Measurement Conditions
Symbol
Parameter
Min
Max
Unit
pF
V
Load Capacitance
Input Pulse Voltage
30
0.2xV
0.8 V
DD
DD
Input Slew Rate
0.23
0.9
1.25
5
V/ns
ns
C
L
Input Rise and Fall Times
Input Timing Ref Voltage
0.5 V
0.5 V
V
DD
DD
Output Timing Ref
Voltage
V
Notes:
1. Input slew rate measured from input pulse min to max at V max. Example: (1.9V x 0.8) - (1.9V x 0.2) = 1.14V; 1.14V/1.25V/ns = 0.9 ns
DD
rise or fall time.
2. AC characteristics tables assume clock and data signals have the same slew rate (slope).
Figure 6.3 Input, Output, and Timing Reference Levels
Input Levels
Output Levels
VDD + 0.4V
VDD - 0.2V
0.7 x VDD
Timing Reference Level
0.5 x VDD
0.3 x VDD
0.2V
- 0.5V
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6.2.1
Capacitance Characteristics
Table 6.2 Capacitance
Parameter
Test Conditions
1 MHz
Min
Max
8
Unit
pF
C
Input Capacitance (applies to SCK, CS#, IO3/RESET#)
Output Capacitance (applies to All I/O)
IN
C
1 MHz
8
pF
OUT
Note:
1. Parameter values are not 100% tested. For more details, please refer to the IBIS models.
6.3
6.3.1
Reset
Power-On (Cold) Reset
The device executes a Power-On Reset (POR) process until a time delay of tPU has elapsed after the
moment that VDD rises above the minimum VDD threshold. See Figure 5.3 on page 35, Table 5.3 on page 34.
The device must not be selected (CS# to go high with VDD) during power-up (tPU), i.e. no commands may be
sent to the device until the end of tPU
.
The IO3 / RESET# signal functions as the RESET# input when CS# is high for more than tCS time or when
Quad Mode is not enabled CR1V[1]=0.
RESET# is ignored during POR. If RESET# is low during POR and remains low through and beyond the end
of tPU, CS# must remain high until tRH after RESET# returns high. RESET# must return high for greater than
tRS before returning low to initiate a hardware reset.
Figure 6.4 Reset Low at the End of POR
VCC
tPU
RESET#
CS#
If RESET# is low at tPU end
CS# must be high at tPU end
tRH
Figure 6.5 Reset High at the End of POR
VCC
RESET#
CS#
tPU
If RESET# is high at tPU end
tPU
CS# may stay high or go low at tPU end
Figure 6.6 POR Followed by hardware reset
VCC
RESET#
CS#
tPU
tPU
tRS
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6.3.2
IO3 / RESET# Input Initiated Hardware (Warm) Reset
The IO3 / RESET# signal functions as the RESET# input when CS# is high for more than tCS time or when
Quad Mode is not enabled CR1V[1]=0. The IO3 / RESET# input has an internal pull-up to VDD and may be
left unconnected if Quad Mode is not used. The tCS delay after CS# goes high gives the memory or host
system time to drive IO3 high after its use as a Quad Mode I/O signal while CS# was low. The internal pull-up
to VDD will then hold IO3 / RESET# high until the host system begins driving IO3 / RESET#. The
IO3 / RESET# input is ignored while CS# remains high during tCS, to avoid an unintended Reset operation. If
CS# is driven low to start a new command, IO3 / RESET# is used as IO3.
When the device is not in Quad Mode or, when CS# is high, and IO3 / RESET# transitions from VIH to VIL
for > tRP, following tCS, the device will reset register states in the same manner as Power-On Reset but, does
not go through the full reset process that is performed during POR. The hardware reset process requires a
period of tRPH to complete. If the POR process did not complete correctly for any reason during power-up
(tPU), RESET# going low will initiate the full POR process instead of the hardware reset process and will
require tPU to complete the POR process.
The RESET command is independent of the state of IO3 / RESET#. If IO3 / RESET# is high or unconnected,
and the RESET instruction is issued, the device will perform software reset.
Additional IO3 RESET# Notes:
IO3 / RESET# must be high for tRS following tPU or tRPH, before going low again to initiate a hardware
reset.
When IO3 / RESET# is driven low for at least a minimum period of time (tRP), following tCS, the device
terminates any operation in progress, makes all outputs high impedance, and ignores all read/write
commands for the duration of tRPH. The device resets the interface to standby state.
If Quad Mode and the IO3 / RESET# feature are enabled, the host system should not drive IO3 low during
tCS, to avoid driver contention on IO3. Immediately following commands that transfer data to the host in
Quad Mode, e.g. Quad I/O Read, the memory drives IO3 / Reset high during tCS, to avoid an unintended
Reset operation. Immediately following commands that transfer data to the memory in Quad Mode, e.g.
Page Program, the host system should drive IO3 / Reset high during tCS, to avoid an unintended Reset
operation.
If Quad Mode is not enabled, and if CS# is low at the time IO3 / RESET# is asserted low, CS# must return
high during tRPH before it can be asserted low again after tRH
.
Table 6.3 Hardware Reset Parameters
Parameter
Description
Reset Setup - Prior Reset end and RESET# high before RESET# low
Reset Pulse Hold - RESET# low to CS# low
RESET# Pulse Width
Limit
Min
Min
Min
Min
Time
50
Unit
ns
t
RS
t
35
µs
RPH
t
200
50
ns
RP
t
Reset Hold - RESET# high before CS# low
ns
RH
Notes:
1. IO3 / RESET# Low is ignored during power-up (t ). If Reset# is asserted during the end of t , the device will remain in the reset state
PU
PU
and t will determine when CS# may go Low.
RH
2. If Quad Mode is enabled, IO3 / RESET# Low is ignored during t
.
CS
3. Sum of t and t must be equal to or greater than t .
RPH
RP
RH
Figure 6.7 Hardware Reset when Quad Mode is Not Enabled and IO3 / Reset# is Enabled
tRP
Any prior reset
tRPH
IO3_RESET#
CS#
tRH
tRH
tRS
tRPH
November 6, 2013 S25FS-S_00_04
S25FS-S Family
39
D a t a S h e e t ( P r e l i m i n a r y )
Figure 6.8 Hardware Reset when Quad Mode and IO3 / Reset# are Enabled
tDIS
tRP
IO3_RESET#
Reset Pulse
tCS
tRH
tRPH
CS#
Prior access using IO3 for data
6.4
SDR AC Characteristics
Table 6.4 AC Characteristics
Symbol
Parameter
SCK Clock Frequency for READ and 4READ
Min
Typ
Max
Unit
F
F
F
DC
DC
DC
50
MHz
SCK, R
SCK, C
SCK, D
instructions
SCK Clock Frequency for FAST_READ,
4FAST_READ, and the following Dual and Quad
commands: QOR, 4QOR, DIOR, 4DIOR, QIOR,
4QIOR
133
MHz
MHz
SCK Clock Frequency for the following DDR
commands: QIOR, 4QIOR
80
P
SCK Clock Period
1/ F
SCK
∞
SCK
t
, t
Clock High Time
50% P
50% P
-5%
50% P
+5%
+5%
ns
ns
WH CH
SCK
SCK
SCK
t
, t
Clock Low Time
-5%
50% P
WL CL
SCK
t
, t
Clock Rise Time (slew rate)
Clock Fall Time (slew rate)
0.1
0.1
V/ns
V/ns
CRT CLCH
t
, t
CFT CHCL
CS# High Time (Read Instructions)
10
20 (5)
50
CS# High Time (Read Instructions when Reset
feature and Quad Mode are both enabled)
CS# High Time (Program/Erase instructions)
t
ns
CS
t
CS# Active Setup Time (relative to SCK)
CS# Active Hold Time (relative to SCK)
Data in Setup Time
2
3
2
3
ns
ns
ns
ns
CSS
t
CSH
t
SU
t
Data in Hold Time
HD
8 (2)
6 (3)
t
Clock Low to Output Valid
Output Hold Time
ns
ns
V
t
1
HO
Output Disable Time (4)
Output Disable Time (when Reset feature and Quad
Mode are both enabled)
8
t
ns
DIS
20 (5)
t
WP# Setup Time (1)
WP# Hold Time (1)
20
ns
ns
WPS
t
100
WPH
Notes:
1. Only applicable as a constraint for WRR or WRAR instruction when SRWD is set to a 1.
2. Full V range and CL=30 pF.
DD
3. Full V range and CL=15 pF.
DD
4. Output High-Z is defined as the point where data is no longer driven.
5.
t
and t
require additional time when the Reset feature and Quad Mode are enabled (CR2V[5]=1 and CR1V[1]=1).
CS
DIS
40
S25FS-S Family
S25FS-S_00_04 November 6, 2013
D a t a S h e e t ( P r e l i m i n a r y )
6.4.1
Clock Timing
Figure 6.9 Clock Timing
PSCK
tCL
tCH
VIH min
VDD / 2
VIL max
tCFT
tCRT
6.4.2
Input / Output Timing
Figure 6.10 SPI Single Bit Input Timing
tCS
CS#
tCSH
tCSH
tCSS
tCSS
SCK
tSU
tHD
MSB IN
SI
LSB IN
SO
Figure 6.11 SPI Single Bit Output Timing
tCS
CS#
SCK
SI
tV
tHO
tDIS
SO
MSB OUT
LSB OUT
Figure 6.12 SPI SDR MIO Timing
tCS
CS#
tCSH
tCSS
tCSH
tCSS
SCLK
IO
tSU
tHD
tV
tHO
tV
tDIS
MSB IN
LSB IN
MSB OUT
LSB OUT
November 6, 2013 S25FS-S_00_04
S25FS-S Family
41
D a t a S h e e t ( P r e l i m i n a r y )
Figure 6.13 WP# Input Timing
CS#
tWPS
7
tWPH
WP#
SCLK
SI
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
WRR or WRAR Instruction
Input Data
6.5
DDR AC Characteristics
.
Table 6.5 AC Characteristics 80 MHz Operation
Symbol
Parameter
Min
Typ
Max
Unit
F
SCK Clock Frequency for DDR READ instruction
SCK Clock Period for DDR READ instruction
DC
80
MHz
ns
SCK, R
SCK, R
P
12.5
∞
t
Clock Rise Time (slew rate)
Clock Fall Time (slew rate)
Clock High Time
1.5
1.5
V/ns
V/ns
ns
crt
t
cft
t
, t
50% P
-5%
-5%
50% P
50% P
+5%
+5%
WH CH
SCK
SCK
SCK
SCK
t
, t
Clock Low Time
50% P
ns
WL CL
CS# High Time (Read Instructions)
CS# High Time (Read Instructions when Reset
feature is enabled)
10
20
t
ns
CS
t
CS# Active Setup Time (relative to SCK)
CS# Active Hold Time (relative to SCK)
IO in Setup Time
2
ns
ns
ns
ns
ns
ns
CSS
t
3
CSH
t
1.5
1.5
1.5
1.5
SU
t
IO in Hold Time
HD
t
Clock Low to Output Valid
Output Hold Time
6 (1)
V
t
HO
Output Disable Time
Output Disable Time (when Reset feature is
enabled)
8
20
t
ns
DIS
t
Time uncertainty due to variation in V
Time uncertainty due to variation in V
First IO to last IO data valid time
130
130
400
1.5
1.5
80
ps
ps
ps
ns
ns
ps
IHTU
IH
IL
t
ILTU
t
IO_skew
t
Output Rise Time given 1.8V swing and 2.0v/ns slew
Output Fall Time given 1.8V swing and 2.0v/ns slew
Clock to data valid jitter
IORT
t
IOFT
ΔT
V
Notes:
1. CL=15 pF.
2. Output slew rate is measured between 20% and 80% of V
.
DD
42
S25FS-S Family
S25FS-S_00_04 November 6, 2013
D a t a S h e e t ( P r e l i m i n a r y )
6.5.1
DDR Input Timing
Figure 6.14 SPI DDR Input Timing
tCS
CS#
SCK
tCSH
tCSH
tCSS
tCSS
tHD
tSU
MSB IN
tHD
tSU
SI_or_IO
SO
LSB IN
6.5.2
DDR Output Timing
Figure 6.15 SPI DDR Output Timing
tCS
CS#
SCK
SI
tHO
tV tV
tDIS
SO_or_IO
MSB
LSB
Figure 6.16 SPI DDR Data Valid Window
tIHTU tILTU
tCL
tCH
tCL
SCK
tV
tV
tV
tIO_SKEW
tV
tIORT_or_tIOFT
Slow D2
IO0
IO1
IO2
IO3
.
Slow D1
Fast D1
tDV
Fast D2
D2
IO_valid
D1
1. Data Valid calculation at 80 MHz:
DV = tCH(min) – tIORT – tIO_SKEW – tIHTU - ΔtV
tDV = 5.62 ns – 1.5 ns – 400 ps – 130 ps – 80 ps
DV = 3.51 ns (56% of the total half clock in the worst case scenario)
t
t
November 6, 2013 S25FS-S_00_04
S25FS-S Family
43
D a t a S h e e t ( P r e l i m i n a r y )
7. Physical Interface
7.1
7.1.1
SOIC 16-Lead Package
SOIC 16 Connection Diagram
Figure 7.1 16-Lead SOIC Package (SO3016), Top View
16
15
14
SCK
1
2
3
IO3/RESET#
VDD
SI/IO0
RFU
RFU
NC
13
4
5
DNU
DNU
12
NC
RFU
6
11
DNU
VSS
CS#
7
10
9
SO/IO1
8
WP#/IO2
Note:
1. The RESET# input has an internal pull-up and may be left unconnected in the system if Quad Mode and hardware reset are not in use.
44
S25FS-S Family
S25FS-S_00_04 November 6, 2013
D a t a S h e e t ( P r e l i m i n a r y )
7.1.2
SOIC 16 Physical Diagram
Figure 7.2 SOIC 16-Lead, 300-mil Body Width (SO3016)
November 6, 2013 S25FS-S_00_04
S25FS-S Family
45
D a t a S h e e t ( P r e l i m i n a r y )
7.2
7.2.1
8-Connector Packages
8-Connector Diagrams
Figure 7.3 8-Pin Plastic Small Outline Package (SOIC8)
8
VDD
1
2
CS#
7
SO / IO1
IO3 / RESET#
SCK
SOIC
3
6
5
WP# / IO2
4
VSS
SI / IO0
Figure 7.4 8-Connector Package (WSON 6x5), Top View
CS#
SO/IO1
WP#/IO2
VSS
VDD
8
7
6
1
2
IO3/RESET#
WSON
3
4
SCK
SI/IO0
5
Note:
1. The RESET# input has an internal pull-up and may be left unconnected in the system if Quad Mode and hardware reset are not in use.
46
S25FS-S Family
S25FS-S_00_04 November 6, 2013
D a t a S h e e t ( P r e l i m i n a r y )
7.2.2
8-Connector Physical Diagrams
Figure 7.5 SOIC 8-Lead, 208 mil Body Width (SOC008)
NOTES:
1.
2.
3.
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
PACKAGE SOC 008 (inches)
SOC 008 (mm)
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
JEDEC
DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
SYMBOL
MIN
MAX
0.085
0.0098
0.075
0.019
0.018
MIN
MAX
2.159
0.249
1.91
A
A1
A2
b
0.069
0.002
0.067
0.014
0.013
1.753
0.051
1.70
0.356
0.330
0.191
0.152
0.483
0.457
0.241
0.203
4.
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
b1
c
0.0075 0.0095
0.006 0.008
0.208 BSC
c1
D
5.283 BSC
5.
6.
DATUMS A AND B TO BE DETERMINED AT DATUM H.
E
0.315 BSC
0.208 BSC
.050 BSC
8.001 BSC
5.283 BSC
1.27 BSC
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
E1
e
7.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
L
0.020
0.030
0.508
0.762
8.
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
L1
L2
N
.049 REF
1.25 REF
0.25 BSC
8
.010 BSC
8
θ
0˚
5˚
8˚
15˚
0˚
0˚
5˚
8˚
9.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
θ1
θ2
15˚
0˚
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
3602 \ 16-038.03 \ 9.1.6
November 6, 2013 S25FS-S_00_04
S25FS-S Family
47
D a t a S h e e t ( P r e l i m i n a r y )
Figure 7.6 WSON 8-Contact 6x5 mm Leadless (WND008)
NOTES:
WND008
PACKAGE
1. DIMENSIONING AND TOLERANCING CONFORMS TO
SYMBOL
MIN
NOM
1.27 BSC.
8
MAX
NOTES
ASME Y14.5M - 1994.
e
N
2. ALL DIMENSIONS ARE IN MILLMETERS.
3. N IS THE TOTAL NUMBER OF TERMINALS.
3
5
ND
L
4
4
DIMENSION “b” APPLIES TO METALLIZED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL
TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE
OTHER END OF THE TERMINAL, THE DIMENSION “b”
SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
0.55
0.35
3.90
3.30
0.60
0.65
0.45
4.10
3.50
b
0.40
4
D2
E2
D
4.00
3.40
5
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
5.00 BSC
6.00 BSC
0.75
6. MAX. PACKAGE WARPAGE IS 0.05mm.
E
7. MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
A
0.70
0.00
0.80
0.05
8
9
PIN #1 ID ON TOP WILL BE LASER MARKED.
A1
K
0.02
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED
HEAT SINK SLUG AS WELL AS THE TERMINALS.
0.20 MIN.
g1071 \ 16-038.30 \ 02.22.12
48
S25FS-S Family
S25FS-S_00_04 November 6, 2013
D a t a S h e e t ( P r e l i m i n a r y )
Figure 7.7 WSON 8-Contact 6x8 mm Leadless (WNH008)
NOTES:
PACKAGE
WNH008
1. DIMENSIONING AND TOLERANCING CONFORMS TO
ASME Y14.5M - 1994.
SYMBOL
MIN
NOM
1.27 BSC.
8
MAX
NOTE
e
N
2. ALL DIMENSIONS ARE IN MILLMETERS.
3. N IS THE TOTAL NUMBER OF TERMINALS.
3
5
ND
L
4
4
DIMENSION “b” APPLIES TO METALLIZED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL
TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE
OTHER END OF THE TERMINAL, THE DIMENSION “b”
SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
0.45
0.35
3.90
3.30
0.50
0.55
0.45
4.10
3.50
b
0.40
4
D2
E2
D
4.00
3.40
5
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
6.00 BSC
8.00 BSC
0.75
6. MAX. PACKAGE WARPAGE IS 0.05mm.
E
7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS.
A
0.70
0.00
0.80
0.05
8
9
PIN #1 ID ON TOP WILL BE LASER MARKED.
A1
K
---
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED
HEAT SINK SLUG AS WELL AS THE TERMINALS.
0.20 MIN.
g1021 \ 16-038.30 \ 10.28.11
November 6, 2013 S25FS-S_00_04
S25FS-S Family
49
D a t a S h e e t ( P r e l i m i n a r y )
7.3
7.3.1
FAB024 24-Ball BGA Package
Connection Diagrams
Figure 7.8 24-Ball BGA, 5x5 Ball Footprint (FAB024), Top View
1
2
3
4
5
A
B
C
D
E
NC
NC
VSS
RFU
VDD
NC
NC
NC
NC
NC
DNU
DNU
DNU
NC
SCK
CS#
RFU WP#/IO2
SO/IO1 SI/IO0
IO3/
RESET#
NC
NC
RFU
Notes:
1. Signal connections are in the same relative positions as FAC024 BGA, allowing a single PCB footprint to use either package.
2. The RESET# input has an internal pull-up and may be left unconnected in the system if Quad Mode and hardware reset are not in use.
50
S25FS-S Family
S25FS-S_00_04 November 6, 2013
D a t a S h e e t ( P r e l i m i n a r y )
7.3.2
Physical Diagram
Figure 7.9 Ball Grid Array 24-Ball 6x8 mm (FAB024)
November 6, 2013 S25FS-S_00_04
S25FS-S Family
51
D a t a S h e e t ( P r e l i m i n a r y )
7.4
7.4.1
FAC024 24-Ball BGA Package
Connection Diagram
Figure 7.10 24-Ball BGA, 4x6 Ball Footprint (FAC024), Top View
1
2
3
4
A
B
C
D
NC
NC
NC
VSS
RFU
VDD
DNU
DNU
DNU
SCK
CS#
RFU WP#/IO2
SO/IO1 SI/IO0
IO3/
RESET#
E
F
NC
NC
NC
NC
NC
NC
RFU
NC
Notes:
1. Signal connections are in the same relative positions as FAB024 BGA, allowing a single PCB footprint to use either package.
2. The RESET# input has an internal pull-up and may be left unconnected in the system if Quad Mode and hardware reset are not in use.
52
S25FS-S Family
S25FS-S_00_04 November 6, 2013
D a t a S h e e t ( P r e l i m i n a r y )
7.4.2
Physical Diagram
Figure 7.11 Ball Grid Array 24-Ball 6 x 8 mm (FAC024)
NOTES:
PACKAGE
JEDEC
FAC024
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
D x E
8.00 mm x 6.00 mm NOM
PACKAGE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
A
A1
A2
D
---
1.20
---
PROFILE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
0.25
0.70
---
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
---
0.90
BODY THICKNESS
BODY SIZE
8.00 BSC.
6.00 BSC.
5.00 BSC.
3.00 BSC.
6
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
E
BODY SIZE
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MD
ME
N
4
DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE
CROWNS OF THE SOLDER BALLS.
24
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
Øb
e
0.35
0.40
0.45
BALL DIAMETER
1.00 BSC.
0.5/0.5
BALL PITCHL
SD/ SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
J
PACKAGE OUTLINE TYPE
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10 OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3642 F16-038.9 \ 09.10.09
7.4.3
Special Handling Instructions for FBGA Packages
Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
November 6, 2013 S25FS-S_00_04
S25FS-S Family
53
D a t a S h e e t ( P r e l i m i n a r y )
Software Interface
This section discusses the features and behaviors most relevant to host system software that interacts with
S25FS-S family memory devices.
8. Address Space Maps
8.1
8.1.1
Overview
Extended Address
The S25FS-S family supports 32-bit (4-byte) addresses to enable higher density devices than allowed by
previous generation (legacy) SPI devices that supported only 24-bit (3-byte) addresses. A 24-bit, byte
resolution, address can access only 16-Mbytes (128-Mbits) maximum density. A 32-bit, byte resolution,
address allows direct addressing of up to a 4-Gbytes (32-Gbits) address space.
Legacy commands continue to support 24-bit addresses for backward software compatibility. Extended 32-bit
addresses are enabled in two ways:
Extended address mode — a volatile Configuration Register bit that changes all legacy commands to
expect 32 bits of address supplied from the host system.
4-byte address commands — that perform both legacy and new functions, which always expect 32-bit
address.
The default condition for extended address mode, after power-up or reset, is controlled by a non-volatile
configuration bit. The default extended address mode may be set for 24- or 32-bit addresses. This enables
legacy software compatible access to the first 128 Mbits of a device or for the device to start directly in 32-bit
address mode.
The 128-Mbit density member of the S25FS-S family supports the extended address features in the same
way but in essence ignores bits 31 to 24 of any address because the main flash array only needs 24 bits of
address. This enables simple migration from the 128-Mb density to higher density devices without changing
the address handling aspects of software.
8.1.2
Multiple Address Spaces
Many commands operate on the main flash memory array. Some commands operate on address spaces
separate from the main flash array. Each separate address space uses the full 24- or 32-bit address but may
only define a small portion of the available address space.
8.2
Flash Memory Array
The main flash array is divided into erase units called physical sectors.
The FS-S family physical sectors may be configured as a hybrid combination of eight 4-kB parameter sectors
at the top or bottom of the address space with all but one of the remaining sectors being uniform size.
Because the group of eight 4-kB parameter sectors is in total smaller than a uniform sector, the group of 4-kB
physical sectors respectively overlay (replace) the top or bottom 32 kB of the highest or lowest address
uniform sector.
The Parameter Sector Erase commands (20h or 21h) must be used to erase the 4-kB sectors individually.
The Sector (uniform block) Erase commands (D8h or DCh) must be used to erase any of the remaining
sectors, including the portion of highest or lowest address sector that is not overlaid by the parameter sectors.
The uniform block erase command has no effect on parameter sectors.
Configuration Register 1 non-volatile bit 2 (CR1NV[2]) equal to 0 overlays the parameter sectors at the
bottom of the lowest address uniform sector. CR1NV[2] = 1 overlays the parameter sectors at the top of the
highest address uniform sector. See Section 8.6, Registers on page 59 for more information.
There is also a configuration option to remove the 4-kB parameter sectors from the address map so that all
sectors are uniform size. Configuration Register 3 volatile bit 3 (CR3V[3]) equal to 0 selects the hybrid sector
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architecture with 4-kB parameter sectors. CR3V[3]=1 selects the uniform sector architecture without
parameter sectors. Uniform physical sectors are 64 kB in FS128S and FS256S.
Both devices also may be configured to use the Sector (uniform block) Erase commands to erase 256-kB
logical blocks rather than individual 64-kB physical sectors. This configuration option (CR3V[1]=1) allows
lower density devices to emulate the same Sector Erase behavior as higher density members of the family
that use 256-kB physical sectors. This can simplify software migration to the higher density members of the
family.
Table 8.1 S25FS256S Sector Address Map, Bottom 4-kB Sectors, 64-kB Physical Uniform Sectors
Address Range
Sector Size (kbyte)
Sector Count
Sector Range
Notes
(Byte Address)
00000000h-00000FFFh
:
SA00
:
4
8
1
SA07
SA08
SA09
:
00007000h-00007FFFh
00008000h-0000FFFFh
00010000h-0001FFFFh
:
Sector Starting Address
—
32
64
Sector Ending Address
511
SA519
01FF0000h-01FFFFFFh
Table 8.2 S25FS256S Sector Address Map, Top 4-kB Sectors, 64-kB Physical Uniform Sectors
Address Range
Sector Size (kbyte)
Sector Count
Sector Range
Notes
(Byte Address)
0000000h-000FFFFh
:
SA00
:
64
32
4
511
1
SA510
SA511
SA512
:
01FE0000h-01FEFFFFh
01FF0000h-01FF7FFFh
01FF8000h-01FF8FFFh
:
Sector Starting Address
—
Sector Ending Address
8
SA519
01FFF000h-01FFFFFFh
Table 8.3 S25FS256S Sector Address Map, Uniform 64-kB Physical Sectors
Sector Size (kbyte)
Sector Count
Sector Range
Address Range (8-bit)
0000000h-000FFFFh
:
Notes
SA00
:
Sector Starting Address
—
64
512
Sector Ending Address
SA511
1FF0000h-1FFFFFFh
Table 8.4 S25FS256S Sector Address Map, Bottom 4-kB Sectors, 256-kB Logical Uniform Sectors
Address Range
Sector Size (kbyte)
Sector Count
Sector Range
Notes
(Byte Address)
00000000h-00000FFFh
:
SA00
:
4
8
1
SA07
SA08
SA09
:
00007000h-00007FFFh
00008000h-0003FFFFh
00040000h-0007FFFFh
:
Sector Starting Address
—
224
256
Sector Ending Address
127
SA135
01FC0000h-01FFFFFFh
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Table 8.5 S25FS256S Sector Address Map, Top 4-kB Sectors, 256-kB Logical Uniform Sectors
Address Range
Sector Size (kbyte)
Sector Count
Sector Range
Notes
(Byte Address)
0000000h-003FFFFh
:
SA00
:
256
224
4
127
1
SA126
SA127
SA128
:
01F80000h-01FBFFFFh
01FC0000h-01FC7FFFh
01FF8000h-01FF8FFFh
:
Sector Starting Address
—
Sector Ending Address
8
SA135
01FFF000h-01FFFFFFh
Table 8.6 S25FS256S Sector Address Map, Uniform 256-kB Logical Sectors
Sector Size (kbyte)
Sector Count
Sector Range
Address Range (8-bit)
00000000h-0003FFFFh
:
Notes
SA00
:
Sector Starting Address
—
256
128
Sector Ending Address
SA127
01FC0000h-01FFFFFFh
Table 8.7 S25FS128S Sector and Memory Address Map, Bottom 4-kB Sectors
Address Range
Sector Size (kbyte)
Sector Count
Sector Range
Notes
(Byte Address)
00000000h-00000FFFh
:
SA00
:
4
8
1
SA07
SA08
SA09
:
00007000h-00007FFFh
00008000h-0000FFFFh
00010000h-0001FFFFh
:
Sector Starting Address
—
32
64
Sector Ending Address
255
SA263
00FF0000h-00FFFFFFh
Table 8.8 S25FS128S Sector and Memory Address Map, Top 4-kB Sectors
Address Range
Sector Size (kbyte)
Sector Count
Sector Range
Notes
(Byte Address)
0000000h-000FFFFh
:
SA00
:
64
32
4
255
1
SA254
SA255
SA256
:
00FE0000h-00FEFFFFh
00FF0000h - 00FF7FFFh
00FF8000h - 00FF8FFFh
:
Sector Starting Address
—
Sector Ending Address
8
SA263
00FFF000h-00FFFFFFh
Table 8.9 S25FS128S Sector and Memory Address Map, Uniform 64-kB Blocks
Address Range
Sector Size (kbyte)
Sector Count
Sector Range
Notes
(Byte Address)
0000000h-0000FFFFh,
:
SA00
:
Sector Starting Address
—
64
256
Sector Ending Address
SA255
00FF0000h-0FFFFFFh
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Table 8.10 S25FS128S Sector Address Map, Bottom 4-kB Sectors, 256-kB Logical Uniform Sectors
Address Range
Sector Size (kbyte)
Sector Count
Sector Range
Notes
(Byte Address)
00000000h-00000FFFh
:
SA00
:
4
8
1
SA07
SA08
SA09
:
00007000h-00007FFFh
00008000h-0003FFFFh
00040000h-0007FFFFh
:
Sector Starting Address
—
224
256
Sector Ending Address
63
SA71
00FC0000h-00FFFFFFh
Table 8.11 S25FS128S Sector Address Map, Top 4-kB Sectors, 256-kB Logical Uniform Sectors
Address Range
Sector Size (kbyte)
Sector Count
Sector Range
Notes
(Byte Address)
00000000h-0003FFFFh
:
SA00
:
256
224
4
63
1
SA62
SA63
SA64
:
00F80000h-00FBFFFFh
00FC0000h-00FF7FFFh
00FF8000h-00FF8FFFh
:
Sector Starting Address
—
Sector Ending Address
8
SA71
00FFF000h-00FFFFFFh
Table 8.12 S25FS128S Sector and Memory Address Map, Uniform 256-kB Blocks
Address Range
Sector Size (kbyte)
Sector Count
Sector Range
Notes
(Byte Address)
00000000h-0003FFFFh
:
SA00
:
Sector Starting Address
—
256
64
Sector Ending Address
SA63
00FC0000h-00FFFFFFh
Note: These are condensed tables that use a couple of sectors as references. There are address ranges that
are not explicitly listed. All 4-kB sectors have the pattern XXXX000h-XXXXFFFh. All 64-kB sectors have the
pattern XXX0000h-XXXFFFFh. All 256-kB sectors have the pattern XX00000h-XX3FFFFh, XX40000h-
XX7FFFFh, XX80000h-XXCFFFFh, or XXD0000h-XXFFFFFh.
8.3
8.4
ID-CFI Address Space
The RDID command (9Fh) reads information from a separate flash memory address space for device
identification (ID) and Common Flash Interface (CFI) information. See Section 12.4, Device ID and Common
Flash Interface (ID-CFI) Address Map on page 143 for the tables defining the contents of the ID-CFI address
space. The ID-CFI address space is programmed by Spansion and read-only for the host system.
JEDEC JESD216 Serial Flash Discoverable Parameters (SFDP) Space.
The RSFDP command (5Ah) reads information from a separate flash memory address space for device
identification, feature, and configuration information, in accord with the JEDEC JESD216 standard for Serial
Flash Discoverable Parameters. The ID-CFI address space is incorporated as one of the SFDP parameters.
See Section 12.3, Serial Flash Discoverable Parameters (SFDP) Address Map on page 142 for the tables
defining the contents of the SFDP address space. The SFDP address space is programmed by Spansion and
read-only for the host system.
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8.5
OTP Address Space
Each FS-S family memory device has a 1024-byte One-Time Program (OTP) address space that is separate
from the main flash array. The OTP area is divided into 32, individually lockable, 32-byte aligned and length
regions.
In the 32-byte region starting at address zero:
The 16 lowest address bytes are programmed by Spansion with a 128-bit random number. Only Spansion
is able to program zeros in these bytes. Programming ones in these byte locations is ignored and does not
affect the value programmed by Spansion. Attempting to program any zero in these byte locations will fail
and set P_ERR.
The next 4 higher address bytes (OTP Lock Bytes) are used to provide one bit per OTP region to
permanently protect each region from programming. The bytes are erased when shipped from Spansion.
After an OTP region is programmed, it can be locked to prevent further programming, by programming the
related protection bit in the OTP Lock Bytes.
The next higher 12 bytes of the lowest address region are Reserved for Future Use (RFU). The bits in
these RFU bytes may be programmed by the host system but it must be understood that a future device
may use those bits for protection of a larger OTP space. The bytes are erased when shipped from
Spansion.
The remaining regions are erased when shipped from Spansion, and are available for programming of
additional permanent data.
Refer to Figure 8.1, OTP Address Space on page 58 for a pictorial representation of the OTP memory space.
The OTP memory space is intended for increased system security. OTP values, such as the random number
programmed by Spansion, can be used to “mate” a flash component with the system CPU/ASIC to prevent
device substitution.
The Configuration Register FREEZE (CR1V[0]) bit protects the entire OTP memory space from programming
when set to 1. This allows trusted boot code to control programming of OTP regions then set the FREEZE bit
to prevent further OTP memory space programming during the remainder of normal power-on system
operation.
Figure 8.1 OTP Address Space
32-byte OTP Region 31
32-byte OTP Region 30
32-byte OTP Region 29
When programmed to 0, each
lock bit protects its related
32-byte OTP region from any
further programming
.
.
.
32-byte OTP Region 3
32-byte OTP Region 2
32-byte OTP Region 1
32-byte OTP Region 0
Region 0 Expanded View
...
Reserved
16-byte Random Number
Lock Bits 31 to 0
Byte 0h
Byte 10h
Byte 1Fh
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Table 8.13 OTP Address Map
Region
Byte Address Range (Hex)
Contents
Initial Delivery State (Hex)
Least Significant Byte of
Spansion Programmed Random
Number
000
...
Spansion Programmed Random
Number
...
Most Significant Byte of
Spansion Programmed Random
Number
00F
Region 0
Region Locking Bits
Byte 10 [bit 0] locks region 0
from programming when = 0
...
010 to 013
All Bytes = FF
Byte 13 [bit 7] locks region
31from programming when = 0
014 to 01F
020 to 03F
040 to 05F
...
Reserved for Future Use (RFU)
Available for User Programming
Available for User Programming
Available for User Programming
Available for User Programming
All Bytes = FF
All Bytes = FF
All Bytes = FF
All Bytes = FF
All Bytes = FF
Region 1
Region 2
...
Region 31
3E0 to 3FF
8.6
Registers
Registers are small groups of memory cells used to configure how the S25FS-S family memory device
operates or to report the status of device operations. The registers are accessed by specific commands. The
commands (and hexadecimal instruction codes) used for each register are noted in each register description.
In legacy SPI memory devices the individual register bits could be a mixture of volatile, non-volatile, or One-
Time Programmable (OTP) bits within the same register. In some configuration options the type of a register
bit could change e.g. from non-volatile to volatile.
The S25FS-S family uses separate non-volatile or volatile memory cell groups (areas) to implement the
different register bit types. However, the legacy registers and commands continue to appear and behave as
they always have for legacy software compatibility. There is a non-volatile and a volatile version of each
legacy register when that legacy register has volatile bits or when the command to read the legacy register
has zero read latency. When such a register is read the volatile version of the register is delivered. During
Power-On Reset (POR), hardware reset, or software reset, the non-volatile version of a register is copied to
the volatile version to provide the default state of the volatile register. When non-volatile register bits are
written the non-volatile version of the register is erased and programmed with the new bit values and the
volatile version of the register is updated with the new contents of the non-volatile version. When OTP bits are
programmed the non-volatile version of the register is programmed and the appropriate bits are updated in
the volatile version of the register. When volatile register bits are written, only the volatile version of the
register has the appropriate bits updated.
The type for each bit is noted in each register description. The default state shown for each bit refers to the
state after Power-On Reset, hardware reset, or software reset if the bit is volatile. If the bit is non-volatile or
OTP, the default state is the value of the bit when the device is shipped from Spansion. Non-Volatile bits have
the same cycling (erase and program) endurance as the main flash array.
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8.6.1
Status Register 1
8.6.1.1
Status Register 1 Non-Volatile (SR1NV)
Related Commands: Write Registers (WRR 01h), Read Any Register (RDAR 65h), Write Any Register
(WRAR 71h)
Table 8.14 Status Register 1 Non-Volatile (SR1NV)
Bits
Field Name
Function
Type
Default State
Description
1 = Locks state of SRWD, BP, and Configuration
Register 1 bits when WP# is low by not executing WRR
or WRAR commands that would affect SR1NV, SR1V,
CR1NV, or CR1V.
StatusRegister
Write Disable
Default
7
SRWD_NV
Non-Volatile
0
0 = No protection, even when WP# is low.
Programming
Error Default
Non-Volatile
Read Only
Provides the default state for the Programming Error
Status. Not user programmable.
6
5
P_ERR_D
E_ERR_D
0
0
Erase Error
Default
Non-Volatile
Read Only
Provides the default state for the Erase Error Status. Not
user programmable.
4
3
BP_NV2
BP_NV1
Protects the selected range of sectors (Block) from
Program or Erase when the BP bits are configured as
non-volatile (CR1NV[3]=0). Programmed to 111b when
BP bits are configured to volatile (CR1NV[3]=1).- after
which these bits are no longer user programmable.
Block
Protection
Non-Volatile
Non-Volatile
000b
2
1
0
BP_NV0
WEL_D
WIP_D
Non-Volatile
Read Only
Provides the default state for the WEL Status. Not user
programmable.
WEL Default
WIP Default
0
0
Non-Volatile
Read Only
Provides the default state for the WIP Status. Not user
programmable.
Status Register Write Non-Volatile (SRWD_NV) SR1NV[7]: Places the device in the Hardware Protected
mode when this bit is set to 1 and the WP# input is driven low. In this mode, the Write Registers (WRR) and
Write Any Register (WRAR) commands (that select Status Register 1 or Configuration Register 1) are
ignored and not accepted for execution, effectively locking the state of the Status Register 1 and
Configuration Register 1 (SR1NV, SR1V, CR1NV, or CR1V) bits, by making the registers read-only. If WP# is
high, Status Register 1 and Configuration Register 1 may be changed by the WRR or WRAR commands. If
SRWD_NV is 0, WP# has no effect and Status Register 1 and Configuration Register 1 may be changed by
the WRR or WRAR commands. WP# has no effect on the writing of any other registers. The SRWD_NV bit
has the same non-volatile endurance as the main flash array. The SRWD (SR1V[7]) bit serves only as a copy
of the SRWD_NV bit to provide zero read latency.
Program Error Default (P_ERR_D) SR1NV[6]: Provides the default state for the Programming Error Status
in SR1V[6]. This bit is not user programmable.
Erase Error (E_ERR) SR1V[5]: Provides the default state for the Erase Error Status in SR1V[5]. This bit is
not user programmable.
Block Protection (BP_NV2, BP_NV1, BP_NV0) SR1NV[4:2]: These bits define the main flash array area to
be software-protected against Program and Erase commands. The BP bits are selected as either volatile or
non-volatile, depending on the state of the BP non-volatile bit (BPNV_O) in the Configuration Register
CR1NV[3]. When CR1NV[3]=0 the non-volatile version of the BP bits (SR1NV[4:2]) are used to control Block
Protection and the WRR command writes SR1NV[4:2] and updates SR1V[4:2] to the same value. When
CR1NV[3]=1 the volatile version of the BP bits (SR1V[4:2]) are used to control Block Protection and the WRR
command writes SR1V[4:2] and does not affect SR1NV[4:2]. When one or more of the BP bits is set to 1, the
relevant memory area is protected against Program and Erase. The Bulk Erase (BE) command can be
executed only when the BP bits are cleared to 0’s. See Section 9.3, Block Protection on page 77 for a
description of how the BP bit values select the memory array area protected. The non-volatile version of the
BP bits have the same non-volatile endurance as the main flash array.
Write Enable Latch Default (WEL_D) SR1NV[1]: Provides the default state for the WEL Status in SR1V[1].
This bit is programmed by Spansion and is not user programmable.
Write-In-Progress Default (WIP_D) SR1NV[0]: Provides the default state for the WIP Status in SR1V[0].
This bit is programmed by Spansion and is not user programmable.
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8.6.1.2
Status Register 1 Volatile (SR1V)
Related Commands: Read Status Register (RDSR1 05h), Write Registers (WRR 01h), Write Enable (WREN
06h), Write Disable (WRDI 04h), Clear Status Register (CLSR 30h or 82h), Read Any Register (RDAR 65h),
Write Any Register (WRAR 71h). This is the register displayed by the RDSR1 command.
Table 8.15 Status Register 1 Volatile (SR1V)
Field
Name
Bits
Function
Type
Default State
Description
Volatile copy of SR1NV[7].
StatusRegister
Write Disable
Volatile
Read Only
7
6
5
SRWD
1 = Error occurred.
0 = No Error.
Programming
Error Occurred
Volatile
Read Only
P_ERR
E_ERR
1= Error occurred.
0 = No Error.
Erase Error
Occurred
Volatile
Read Only
4
3
BP2
BP1
Protects selected range of sectors (Block) from Program
or Erase when the BP bits are configured as volatile
(CR1NV[3]=1). Volatile copy of SR1NV[4:2] when BP
bits are configured as non-volatile. User writable when
BP bits are configured as volatile.
Block
Protection
Volatile
Volatile
Volatile
2
BP0
SR1NV
1 = Device accepts Write Registers (WRR and WRAR),
Program, or Erase commands.
0 = Device ignores Write Registers (WRR and WRAR),
Program, or Erase commands.
Write Enable
Latch
1
WEL
This bit is not affected by WRR or WRAR, only WREN
and WRDI commands affect this bit.
1= Device Busy, an embedded operation is in progress
such as Program or Erase.
Write-In-
Progress
Volatile
Read Only
0 = Ready Device is in Standby mode and can accept
commands.
0
WIP
This bit is not affected by WRR or WRAR, it only
provides WIP status.
Status Register Write (SRWD) SR1V[7]: SRWD is a volatile copy of SR1NV[7]. This bit tracks any changes
to the non-volatile version of this bit.
Program Error (P_ERR) SR1V[6]: The Program Error bit is used as a program operation success or failure
indication. When the Program Error bit is set to a 1 it indicates that there was an error in the last program
operation. This bit will also be set when the user attempts to program within a protected main memory sector,
or program within a locked OTP region. When the Program Error bit is set to a 1 this bit can be cleared to 0
with the Clear Status Register (CLSR) command. This is a read-only bit and is not affected by the WRR or
WRAR commands.
Erase Error (E_ERR) SR1V[5]: The Erase Error bit is used as an Erase operation success or failure
indication. When the Erase Error bit is set to a 1 it indicates that there was an error in the last erase operation.
This bit will also be set when the user attempts to erase an individual protected main memory sector. The
Bulk Erase command will not set E_ERR if a protected sector is found during the command execution. When
the Erase Error bit is set to a 1 this bit can be cleared to 0 with the Clear Status Register (CLSR) command.
This is a read-only bit and is not affected by the WRR or WRAR commands.
Block Protection (BP2, BP1, BP0) SR1V[4:2]: These bits define the main flash array area to be software
protected against program and Erase commands. The BP bits are selected as either volatile or non-volatile,
depending on the state of the BP non-volatile bit (BPNV_O) in the Configuration Register CR1NV[3]. When
CR1NV[3]=0 the non-volatile version of the BP bits (SR1NV[4:2]) are used to control Block Protection and the
WRR command writes SR1NV[4:2] and updates SR1V[4:2] to the same value. When CR1NV[3]=1 the volatile
version of the BP bits (SR1V[4:2]) are used to control Block Protection and the WRR command writes
SR1V[4:2] and does not affect SR1NV[4:2]. When one or more of the BP bits is set to 1, the relevant memory
area is protected against program and erase. The Bulk Erase (BE) command can be executed only when the
BP bits are cleared to 0’s. See Section 9.3, Block Protection on page 77 for a description of how the BP bit
values select the memory array area protected.
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Write Enable Latch (WEL) SR1V[1]: The WEL bit must be set to 1 to enable program, write, or erase
operations as a means to provide protection against inadvertent changes to memory or register values. The
Write Enable (WREN) command execution sets the Write Enable Latch to a 1 to allow any program, erase, or
write commands to execute afterwards. The Write Disable (WRDI) command can be used to set the Write
Enable Latch to a 1 to prevent all program, erase, and write commands from execution. The WEL bit is
cleared to 0 at the end of any successful program, write, or erase operation. Following a failed operation the
WEL bit may remain set and should be cleared with a WRDI command following a CLSR command. After a
power-down / power-up sequence, hardware reset, or software reset, the Write Enable Latch is set to a 0 The
WRR or WRAR command does not affect this bit.
Write-In-Progress (WIP) SR1V[0]: Indicates whether the device is performing a program, write, erase
operation, or any other operation, during which a new operation command will be ignored. When the bit is set
to a 1 the device is busy performing an operation. While WIP is 1, only Read Status (RDSR1 or RDSR2),
Read Any Register (RDAR), Erase Suspend (ERSP), Program Suspend (PGSP), Clear Status Register
(CLSR), and software reset (RESET) commands are accepted. ERSP and PGSP will only be accepted if
memory array erase or program operations are in progress. The Status Register E_ERR and P_ERR bits are
updated while WIP =1. When P_ERR or E_ERR bits are set to 1, the WIP bit will remain set to 1 indicating the
device remains busy and unable to receive new operation commands. A Clear Status Register (CLSR)
command must be received to return the device to standby mode. When the WIP bit is cleared to 0 no
operation is in progress. This is a read-only bit.
8.6.2
Status Register 2 Volatile (SR2V)
Related Commands: Read Status Register 2 (RDSR2 07h), Read Any Register (RDAR 65h).
Status Register 2 does not have user programmable non-volatile bits, all defined bits are volatile read only
status. The default state of these bits are set by hardware.
Table 8.16 Status Register 2 Volatile (SR2V)
Bits
7
Field Name
RFU
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Type
Default State
Description
Reserved for Future Use.
0
0
0
0
0
6
RFU
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
5
RFU
4
RFU
3
RFU
1 = Sector Erase Status command result =
Erase Completed.
0 = Sector Erase Status command result =
Erase Not Completed.
Volatile
Read Only
2
ESTAT
Erase Status
0
1 = In Erase Suspend mode.
0 = Not in Erase Suspend mode.
Volatile
Read Only
1
0
ES
PS
EraseSuspend
0
0
1 = In Program Suspend mode.
0 = Not in Program Suspend mode.
Program
Suspend
Volatile
Read Only
Erase Status (ESTAT) SR2V[2]: The Erase Status bit indicates whether the sector, selected by an
immediately preceding Erase Status command, completed the last Erase command on that sector. The Erase
Status command must be issued immediately before reading SR2V to get valid Erase Status. Reading SR2V
during a program or erase suspend does not provide valid Erase Status. The Erase Status bit can be used by
system software to detect any sector that failed its last erase operation. This can be used to detect erase
operations failed due to loss of power during the erase operation.
Erase Suspend (ES) SR2V[1]: The Erase Suspend bit is used to determine when the device is in Erase
Suspend mode. This is a status bit that cannot be written by the user. When Erase Suspend bit is set to 1, the
device is in Erase Suspend mode. When Erase Suspend bit is cleared to 0, the device is not in erase
suspend mode. Refer to Section 10.6.5, Program or Erase Suspend (PES 85h, 75h, B0h) on page 120 for
details about the Erase Suspend/Resume commands.
Program Suspend (PS) SR2V[0]: The Program Suspend bit is used to determine when the device is in
Program Suspend mode. This is a status bit that cannot be written by the user. When Program Suspend bit is
set to 1, the device is in Program Suspend mode. When the Program Suspend bit is cleared to 0, the device
is not in Program Suspend mode. Refer to Section 10.6.5, Program or Erase Suspend (PES 85h, 75h, B0h)
on page 120 for details.
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8.6.3
Configuration Register 1
Configuration Register 1 controls certain interface and data protection functions. The register bits can be
changed using the WRR command with sixteen input cycles or with the WRAR command.
8.6.3.1
Configuration Register 1 Non-Volatile (CR1NV)
Related Commands: Write Registers (WRR 01h), Read Any Register (RDAR 65h), Write Any Register
(WRAR 71h).
Table 8.17 Configuration Register 1 Non-Volatile (CR1NV)
Default
State
Bits
Field Name
Function
Type
Description
7
6
RFU
RFU
0
0
Reserved for Future
Use
Non-Volatile
Reserved.
Configures Start of
Block Protection
1 = BP starts at bottom (Low address).
0 = BP starts at top (High address).
5
TBPROT_O
OTP
0
Reserved for Future
Use
4
3
RFU
RFU
OTP
0
0
Reserved.
Configures BP2-0 in
Status Register
1 = Volatile.
0 = Non-Volatile.
BPNV_O
Configures
Parameter Sectors
location
1 = 4-kB physical sectors at top, (high address).
0 = 4-kB physical sectors at bottom (Low address).
RFU in uniform sector configuration.
2
TBPARM_O
OTP
0
1
0
QUAD_NV
FREEZE_D
Quad Non-Volatile
FREEZE Default
Non-Volatile
0
0
Provides the default state for the QUAD bit.
Non-Volatile
Read Only
Provides the default state for the Freeze bit. Not user
programmable.
Top or Bottom Protection (TBPROT_O) CR1NV[5]: This bit defines the operation of the Block Protection
bits BP2, BP1, and BP0 in the Status Register. As described in the Status Register section, the BP2-0 bits
allow the user to optionally protect a portion of the array, ranging from 1/64, ¼, ½, etc., up to the entire array.
When TBPROT_O is set to a 0 the Block Protection is defined to start from the top (maximum address) of the
array. When TBPROT_O is set to a 1 the Block Protection is defined to start from the bottom (zero address)
of the array. The TBPROT_O bit is OTP and set to a 0 when shipped from Spansion. If TBPROT_O is
programmed to 1, writing the bit with a 0 does not change the value or set the Program Error bit (P_ERR in
SR1V[6]).
The desired state of TBPROT_O must be selected during the initial configuration of the device during system
manufacture; before the first program or erase operation on the main flash array. TBPROT_O must not be
programmed after programming or erasing is done in the main flash array.
CR1NV[4]: Reserved for Future Use.
Block Protection Non-Volatile (BPNV_O) CR1NV[3]: The BPNV_O bit defines whether the BP_NV 2-0 bits
or the BP 2-0 bits in the Status Register are selected to control the Block Protection feature. The BPNV_O bit
is OTP and cleared to a 0 with the BP_NV bits cleared to “000” when shipped from Spansion. When BPNV_O
is set to a 0 the BP_NV 2-0 bits in the Status Register are selected to control the block protection and are
written by the WRR command. The time required to write the BP_NV bits is tW. When BPNV is set to a 1 the
BP2-0 bits in the Status Register are selected to control the block protection and the BP_NV 2-0 bits will be
programmed to binary “111”. This will cause the BP 2-0 bits to be set to binary 111 after POR, hardware
reset, or command reset. When BPNV is set to a 1, the WRR command writes only the volatile version of the
BP bits (SR1V[4:2]). The non-volatile version of the BP bits (SR1NV[4:2]) are no longer affected by the WRR
command. This allows the BP bits to be written an unlimited number of times because they are volatile and
the time to write the volatile BP bits is the much faster tCS volatile register write time. If BPNV_O is
programmed to 1, writing the bit with a 0 does not change the value or set the Program Error bit (P_ERR in
SR1V[6]).
TBPARM_O CR1NV[2]: TBPARM_O defines the logical location of the parameter block. The parameter
block consists of eight 4-kB parameter sectors, which replace a 32 kB portion of the highest or lowest address
sector. When TBPARM_O is set to a 1 the parameter block is in the top of the memory array address space.
When TBPARM_O is set to a 0 the parameter block is at the Bottom of the array. TBPARM_O is OTP and set
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to a 0 when it ships from Spansion. If TBPARM_O is programmed to 1, writing the bit with a 0 does not
change the value or set the Program Error bit (P_ERR in SR1V[6]).
The desired state of TBPARM_O must be selected during the initial configuration of the device during system
manufacture; before the first program or erase operation on the main flash array. TBPARM_O must not be
programmed after programming or erasing is done in the main flash array.
TBPROT_O can be set or cleared independent of the TBPARM_O bit. Therefore, the user can elect to store
parameter information from the bottom of the array and protect boot code starting at the top of the array, or
vice versa. Or, the user can elect to store and protect the parameter information starting from the top or
bottom together.
When the memory array is configured as uniform sectors, the TBPARM_O bit is Reserved for Future Use
(RFU) and has no effect because all sectors are uniform size.
Quad Data Width Non-Volatile (QUAD_NV) CR1NV[1]: Provides the default state for the Quad bit in
CR1V[1]. The WRR or WRAR command affects this bit. Non-Volatile selection of QPI Mode, by programming
CR2NV[6] =1, will also program QUAD_NV =1 to change the non-volatile default to Quad data width mode.
While QPI Mode is selected by CR2V[6]=1, the Quad_NV bit cannot be cleared to 0.
Freeze Protection Default (FREEZE) CR1NV[0]: Provides the default state for the FREEZE bit in CR1V[0].
This bit is not user programmable.
8.6.3.2
Configuration Register 1 Volatile (CR1V)
Related Commands: Read Configuration Register (RDCR 35h), Write Registers (WRR 01h), Read Any
Register (RDAR 65h), Write Any Register (WRAR 71h). This is the register displayed by the RDCR
command.
Table 8.18 Configuration Register 1 Volatile (CR1V)
Default
State
Bits
Field Name
Function
Type
Description
7
6
RFU
RFU
Reserved for Future
Use
Volatile
Reserved.
Volatile copy of
TBPROT_O
Volatile
Read Only
Not user writable.
See CR1NV[5] TBPROT_O.
5
4
3
2
1
TBPROT
RFU
Reserved for Future
Use
RFU
Reserved.
Volatile copy of
BPNV_O
Volatile
Read Only
Not user writable.
See CR1NV[3] BPNV_O.
BPNV
CR1NV
Volatile copy of
TBPARM_O
Volatile
Read Only
Not user writable.
See CR1NV[2] TBPARM_O.
TBPARM
QUAD
1 = Quad.
0 = Dual or Serial.
Quad I/O Mode
Volatile
Volatile
Lock current state of Block Protection control bits, and
OTP regions.
1 = Block Protection and OTP locked.
0 = Block Protection and OTP unlocked.
Lock-Down Block
Protection until next
power cycle
0
FREEZE
TBPROT, BPNV, and TBPARM CR1V[5,3,2]: These bits are volatile copies of the related non-volatile bits of
CR1NV. These bits track any changes to the related non-volatile version of these bits.
Quad Data Width (QUAD) CR1V[1]: When set to 1, this bit switches the data width of the device to 4-bit
Quad Mode. That is, WP# becomes IO2 and IO3 / RESET# becomes an active I/O signal when CS# is low or
the RESET# input when CS# is high. The WP# input is not monitored for its normal function and is internally
set to high (inactive). The commands for Serial, and Dual I/O Read still function normally but, there is no need
to drive the WP# input for those commands when switching between commands using different data path
widths. Similarly, there is no requirement to drive the IO3 / RESET# during those commands (while CS# is
low). The QUAD bit must be set to 1 when using the Quad I/O Read, DDR Quad I/O Read, QPI Mode
(CR2V[6] = 1), and Read Quad ID commands. While QPI Mode is selected by CR2V[6]=1, the Quad bit
cannot be cleared to 0. The WRR command writes the non-volatile version of the Quad bit (CR1NV[1]), which
also causes an update to the volatile version CR1V[1]. The WRR command can not write the volatile version
CR1V[1] without first affecting the non-volatile version CR1NV[1]. The WRAR command must be used when
it is desired to write the volatile Quad bit CR1V[1] without affecting the non-volatile version CR1NV[1].
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Freeze Protection (FREEZE) CR1V[0]: The Freeze bit, when set to 1, locks the current state of the Block
Protection control bits and OTP area:
BPNV_2-0 bits in the non-volatile Status Register 1 (SR1NV[4:2])
BP 2-0 bits in the volatile Status Register 1 (SR1V[4:2])
TBPROT_O, TBPARM_O, and BPNV_O bits in the non-volatile Configuration Register (CR1NV[53, 2])
TBPROT, TBPARM, and BPNV bits in the volatile Configuration Register (CR1V[5, 3, 2]) are indirectly
protected in that they are shadows of the related CR1NV OTP bits and are read only
the entire OTP memory space
Any attempt to change the above listed bits while FREEZE = 1 is prevented:
The WRR command does not affect the listed bits and no error status is set.
The WRAR command does not affect the listed bits and no error status is set.
The OTPP command, with an address within the OTP area, fails and the P-ERR status is set.
As long as the FREEZE bit remains cleared to logic 0 the Block Protection control bits and FREEZE are
writable, and the OTP address space is programmable.
Once the FREEZE bit has been written to a logic 1 it can only be cleared to a logic 0 by a power-off to power-
on cycle or a hardware reset. Software reset will not affect the state of the FREEZE bit.
The CR1V[0] FREEZE bit is volatile and the default state of FREEZE after power-on comes from FREEZE_D
in CR1NV[0]. The FREEZE bit can be set in parallel with updating other values in CR1V by a single WRR or
WRAR command.
The FREEZE bit does not prevent the WRR or WRAR commands from changing the SRWD_NV (SR1NV[7]),
Quad_NV (CR1NV[1]), or QUAD (CR1V[1]) bits.
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8.6.4
Configuration Register 2
Configuration Register 2 controls certain interface functions. The register bits can be read and changed using
the Read Any Register and Write Any Register commands. The non-volatile version of the register provides
the ability to set the POR, hardware reset, or software reset state of the controls. These configuration bits are
OTP and may only have their default state changed to the opposite value one time during system
configuration. The volatile version of the register controls the feature behavior during normal operation.
8.6.4.1
Configuration Register 2 Non-Volatile (CR2NV)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).
Table 8.19 Configuration Register 2 Non-Volatile (CR2NV)
Default
State
Bits
Field Name
Function
Type
Description
1 = 4-byte address.
0 = 3-byte address.
7
AL_NV
Address Length
0
1 = Enabled - QPI (4-4-4) protocol in use.
6
5
QA_NV
QPI
0
0
0 = Disabled - Legacy SPI protocols in use, instruction is
always serial on SI.
1 = Enabled - IO3 is used as RESET# input when CS# is
high or Quad Mode is disabled CR1V[1]=1.
0 = Disabled - IO3 has no alternate function, hardware
reset is disabled.
IO3R_NV
RFU
IO3 Reset
Reserved
OTP
4
3
2
1
0
0
1
0
0
0
Reserved For Future Use.
0 to 15 latency (dummy) cycles following read address
or continuous mode bits.
Note that bit 3 has a default value of 1 and may be
programmed one time to 0 but cannot be returned to 1.
RL_NV
Read Latency
Address Length Non-Volatile CR2NV[7]: This bit controls the POR, hardware reset, or software reset state
of the expected address length for all commands that require address and are not fixed 3-byte only or 4-byte
(32-bit) only address. Most commands that need an address are legacy SPI commands that traditionally used
3-byte (24-bit) address. For device densities greater than 128 Mbit a 4-byte address is required to access the
entire memory array. The address length configuration bit is used to change most 3-byte address commands
to expect 4-byte address. See Table 10.1, S25FS-S Family Command Set (sorted by function) on page 88 for
command address length. The use of 4-byte address length also applies to the 128-Mbit member of the
S25FS-S family so that the same 4-byte address hardware and software interface may be used for all family
members to simplify migration between densities. The 128-Mbit member of the S25FS-S family simply
ignores the content of the fourth, high order, address byte. This non-volatile address length configuration bit
enables the device to start immediately (boot) in 4-byte address mode rather than the legacy 3-byte address
mode.
QPI Non-Volatile CR2NV[6]: This bit controls the POR, hardware reset, or software reset state of the
expected instruction width for all commands. Legacy SPI commands always send the instruction one bit wide
(serial I/O) on the SI (IO0) signal. The S25FS-S family also supports the QPI Mode in which all transfers
between the host system and memory are 4-bits wide on IO0 to IO3, including all instructions. This non-
volatile QPI configuration bit enables the device to start immediately (boot) in QPI Mode rather than the
legacy serial instruction mode. When this bit is programmed to QPI Mode, the QUAD_NV bit is also
programmed to Quad Mode (CR1NV[1]=1). The recommended procedure for moving to QPI Mode is to first
use the WRAR command to set CR2V[6]=1, QPI Mode. The volatile register write for QPI Mode has a short
and well defined time (tCS) to switch the device interface into QPI Mode. Following commands can then be
immediately sent in QPI protocol. The WRAR command can be used to program CR2NV[6]=1, followed by
polling of SR1V[0] to know when the programming operation is completed. Similarly, to exit QPI Mode, the
WRAR command is used to clear CR2V[6]=0. CR2NV[6] cannot be erased to 0 because it is OTP.
IO3 Reset Non-Volatile CR2NV[5]: This bit controls the POR, hardware reset, or software reset state of the
IO3 signal behavior. Most legacy SPI devices do not have a hardware reset input signal due to the limited
signal count and connections available in traditional SPI device packages. The S25FS-S family provides the
option to use the IO3 signal as a hardware reset input when the IO3 signal is not in use for transferring
information between the host system and the memory. This non-volatile IO3 Reset configuration bit enables
the device to start immediately (boot) with IO3 enabled for use as a RESET# signal.
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Read Latency Non-Volatile CR2NV[3:0]: This bit controls the POR, hardware reset, or software reset state
of the Read Latency (dummy cycle) delay in all variable latency read commands. The following read
commands have a variable latency period between the end of address or mode and the beginning of read
data returning to the host:
Fast Read
Dual I/O Read
Quad I/O Read
DDR Quad I/O Read
OTPR
RDAR
This Non-Volatile Read Latency configuration bit sets the number of read latency (dummy cycles) in use so
the device can start immediately (boot) with an appropriate read latency for the host system.
Table 8.20 Latency Code (Cycles) Versus Frequency
Read Command Maximum Frequency (MHz)
Fast Read (1-1-1)
OTPR (1-1-1)
RDAR (1-1-1)
RDAR (4-4-4)
Quad I/O (1-4-4)
QPI (4-4-4)
DDR Quad I/O (1-4-4)
Latency
Cycles
Dual I/O (1-2-2)
DDR QPI (4-4-4) (Note 4)
Mode Cycles = 0
Mode Cycles = 4
Mode Cycles = 2
Mode Cycles = 1
0
1
50
80
40
53
N/A
22
34
45
57
68
80
80
80
80
80
80
80
80
80
80
66
92
2
80
104
116
129
133
133
133
133
133
133
133
133
133
133
133
66
3
92
80
4
104
116
129
133
133
133
133
133
133
133
133
133
92
5
104
116
129
133
133
133
133
133
133
133
133
6
7
8
9
10
11
12
13
14
15
Notes:
1. SCK frequency > 133 MHz SDR, or 80 MHz DDR is not supported by this family of devices.
2. The Dual I/O, Quad I/O, QPI, DDR Quad I/O, and DDR QPI, command protocols include Continuous Read mode bits following the
address. The clock cycles for these bits are not counted as part of the latency cycles shown in the table. Example: the legacy
Quad I/O command has 2 Continuous Read mode cycles following the address. Therefore, the legacy Quad I/O command without
additional read latency is supported only up to the frequency shown in the table for a read latency of 0 cycles. By increasing the variable
read latency the frequency of the Quad I/O command can be increased to allow operation up to the maximum supported 133 MHz
frequency.
3. Other read commands have fixed latency, e.g. Read always has zero read latency. RSFDP always has eight cycles of latency.
4. DDR QPI is only supported for Latency Cycles 1 through 5 and for clock frequency of up to 68 MHz.
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8.6.4.2
Configuration Register 2 Volatile (CR2V)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h), 4BAM.
Table 8.21 Configuration Register 2 Volatile (CR2V)
Default
State
Bits
Field Name
Function
Type
Description
1 = 4 byte address.
0 = 3 byte address.
7
AL
Address Length
1 = Enabled - QPI (4-4-4) protocol in use.
0 = Disabled - Legacy SPI protocols in use, instruction is
always serial on SI.
6
5
QA
QPI
1 = Enabled - IO3 is used as RESET# input when CS# is
high or Quad Mode is disabled CR1V[1]=1.
0 = Disabled - IO3 has no alternate function, hardware
reset is disabled.
IO3R_S
RFU
IO3 Reset
Reserved
Volatile
CR2NV
4
3
2
1
0
Reserved for Future Use.
0 to 15 latency (dummy) cycles following read address
or continuous mode bits.
RL
Read Latency
Address Length CR2V[7]: This bit controls the expected address length for all commands that require
address and are not fixed 3-byte only or 4-byte (32-bit) only address. See Table 10.1, S25FS-S Family
Command Set (sorted by function) on page 88 for command address length. This volatile Address Length
configuration bit enables the address length to be changed during normal operation. The 4-byte address
mode (4BAM) command directly sets this bit into 4-byte address mode.
QPI CR2V[6]: This bit controls the expected instruction width for all commands. This volatile QPI
configuration bit enables the device to enter and exit QPI Mode during normal operation. When this bit is set
to QPI Mode, the Quad bit is also set to Quad Mode (CR1V[1]=1). When this bit is cleared to legacy SPI
mode, the Quad bit is not affected.
IO3 Reset CR2V[5]: This bit controls the IO3 / RESET# signal behavior. This volatile IO3 Reset configuration
bit enables the use of IO3 as a RESET# input during normal operation.
Read Latency CR2V[3:0]: This bit controls the read latency (dummy cycle) delay in variable latency read
commands These volatile configuration bits enable the user to adjust the read latency during normal
operation to optimize the latency for different commands or, at different operating frequencies, as needed.
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8.6.5
Configuration Register 3
Configuration Register 3 controls certain command behaviors. The register bits can be read and changed
using the Read Any Register and Write Any Register commands. The non-volatile register provides the POR,
hardware reset, or software reset state of the controls. These configuration bits are OTP and may be
programmed to their opposite state one time during system configuration if needed. The volatile version of
Configuration Register 3 allows the configuration to be changed during system operation or testing.
8.6.5.1
Configuration Register 3 Non-Volatile (CR3NV)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).
Table 8.22 Configuration Register 3 Non-Volatile (CR3NV)
Default
State
Bits
Field Name
Function
Type
Description
Reserved for Future Use.
7
6
RFU
RFU
Reserved
Reserved
0
0
Reserved for Future Use.
1 = Blank Check during erase enabled.
0 = Blank Check disabled.
5
4
3
2
1
0
BC_NV
02h_NV
20h_NV
30h_NV
D8h_NV
F0h_NV
Blank Check
Page Buffer Wrap
4-kB Erase
0
0
0
0
0
0
1 = Wrap at 512 bytes.
0 = Wrap at 256 bytes.
1 = 4-kB Erase disabled (Uniform Sector Architecture).
0 = 4-kB Erase enabled (Hybrid Sector Architecture).
OTP
1 = 30h is Erase or Program Resume command.
0 = 30h is clear status command.
Clear Status /
Resume Select
1 = 256-kB Erase.
0 = 64-kB Erase.
Block Erase Size
1 = F0h software reset is enabled.
0 = F0h software reset is disabled (ignored).
Legacy Software
Reset Enable
Blank Check Non-Volatile CR3NV[5]: This bit controls the POR, hardware reset, or software reset state of
the blank check during erase feature.
02h Non-Volatile CR3NV[4]: This bit controls the POR, hardware reset, or software reset state of the Page
Programming Buffer address wrap point.
20h Non-Volatile CR3NV[3]: This bit controls the POR, hardware reset, or software reset state of the
availability of 4-kB parameter sectors in the main flash array address map.
30h Non-Volatile CR3NV[2]: This bit controls the POR, hardware reset, or software reset state of the 30h
instruction code is used.
D8h Non-Volatile CR3NV[1]: This bit controls the POR, hardware reset, or software reset state of the
configuration for the size of the area erased by the D8h or DCh instructions.
F0h Non-Volatile CR3NV[0]: This bit controls the POR, hardware reset, or software reset state of the
availability of the Spansion legacy FL-S family software reset instruction.
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8.6.5.2
Configuration Register 3 Volatile (CR3V)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).
Table 8.23 Configuration Register 3 Volatile (CR3V)
Default
State
Bits
Field Name
Function
Type
Description
Reserved for Future Use.
7
6
RFU
RFU
Reserved
Reserved
Reserved for Future Use.
1 = Blank Check during erase enabled.
0 = Blank Check disabled.
Volatile
5
4
3
2
1
0
BC_V
02h_V
20h_V
30h_V
D8h_V
F0h_V
Blank Check
Page Buffer Wrap
4-kB Erase
1 = Wrap at 512 bytes.
0 = Wrap at 256 bytes.
1 = 4-kB Erase disabled (Uniform Sector Architecture).
0 = 4-kB Erase enabled (Hybrid Sector Architecture).
Volatile,
Read Only
CR3NV
1 = 30h is Erase or Program Resume command.
0 = 30h is Clear Status command.
Clear Status /
Resume Select
1 = 256-kB Erase.
0 = 64-kB Erase.
Block Erase Size
Volatile
1 = F0h software reset is enabled.
0 = F0h software reset is disabled (ignored).
Legacy Software
Reset Enable
Blank Check Volatile CR3V[5]: This bit controls the blank check during erase feature. When this feature is
enabled an erase command first evaluates the Erase Status of the sector. If the sector is found to have not
completed its last erase successfully, the sector is unconditionally erased. If the last erase was successful,
the sector is read to determine if the sector is still erased (blank). The erase operation is started immediately
after finding any programmed zero. If the sector is already blank (no programmed zero bit found) the
remainder of the erase operation is skipped. This can dramatically reduce erase time when sectors being
erased do not need the erase operation. When enabled the blank check feature is used within the parameter
erase, Sector Erase, and Bulk Erase commands. When blank check is disabled an Erase command
unconditionally starts the Erase operation.
02h Volatile CR3V[4]: This bit controls the Page Programming Buffer address wrap point. Legacy SPI
devices generally have used a 256-byte Page Programming Buffer and defined that if data is loaded into the
buffer beyond the 255-byte location, the address at which additional bytes are loaded would be wrapped to
address zero of the buffer. The S25FS-S family provides a 512-byte Page Programming Buffer that can
increase programming performance. For legacy software compatibility, this configuration bit provides the
option to continue the wrapping behavior at the 256-byte boundary or to enable full use of the available
512-byte buffer by not wrapping the load address at the 256-byte boundary.
20h Volatile CR3V[3]: This bit controls the availability of 4-kB parameter sectors in the main flash array
address map. The parameter sectors can overlay the highest or lowest 32-kB address range of the device or
they can be removed from the address map so that all sectors are uniform size. This bit shall not be written to
a value different than the value of CR3NV[3]. The value of CR3V[3] may only be changed by writing
CR3NV[3].
30h Volatile CR3V[2]: This bit controls how the 30h instruction code is used. The instruction may be used as
a Clear Status command or as an alternate Program / Erase Resume command. This allows software
compatibility with either Spansion legacy SPI devices or alternate vendor devices.
D8h Volatile CR3V[1]: This bit controls the area erased by the D8h or DCh instructions. The instruction can
be used to erase 64-kB physical sectors or 256-kB size and aligned blocks. The option to erase 256-kB
blocks in the lower density family members allows for consistent software behavior across all densities that
can ease migration between different densities.
F0h Volatile CR3V[0]: This bit controls the availability of the Spansion legacy FL-S family software reset
instruction. The S25FS-S family supports the industry common 66h + 99h instruction sequence for software
reset. This configuration bit allows the option to continue use of the legacy F0h single command for software
reset.
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8.6.6
Configuration Register 4
Configuration Register 4 controls the main Flash Array Read commands burst wrap behavior. The burst wrap
configuration does not affect commands reading from areas other than the main flash array e.g. read
commands for registers or OTP array. The non-volatile version of the register provides the ability to set the
start up (boot) state of the controls as the contents are copied to the volatile version of the register during the
POR, hardware reset, or software reset. The volatile version of the register controls the feature behavior
during normal operation. The register bits can be read and changed using the Read Any Register and Write
Any Register commands. The volatile version of the register can also be written by the Set Burst Length
(C0h) command.
8.6.6.1
Configuration Register 4 Non-Volatile (CR4NV)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).
Table 8.24 Configuration Register 4 Non-Volatile (CR4NV)
Default
State
Bits
Field Name
OI_O
Function
Output Impedance
Wrap Enable
Type
Description
7
6
5
0
0
0
See Table 8.25, Output Impedance Control on page 71.
0 = Wrap Enabled.
1 = Wrap Disabled.
4
WE_O
1
OTP
3
2
1
RFU
RFU
Reserved
Reserved
0
0
0
Reserved for Future Use.
Reserved for Future Use.
00 = 8-byte wrap.
01 = 16-byte wrap.
10 = 32-byte wrap.
11 = 64-byte wrap.
WL_O
Wrap Length
0
0
Output Impedance Non-Volatile CR4NV[7:5]: These bits control the POR, hardware reset, or software
reset state of the IO signal output impedance (drive strength). Multiple drive strength are available to help
match the output impedance with the system printed circuit board environment to minimize overshoot and
ringing. These non-volatile output impedance configuration bits enable the device to start immediately (boot)
with the appropriate drive strength.
Table 8.25 Output Impedance Control
CR4NV[7:5]
Impedance Selection
Typical Impedance to V
(Ohms)
Typical Impedance to V
(Ohms)
Notes
SS
DD
000
001
010
011
100
101
110
111
47
124
71
47
34
26
22
18
45
105
64
45
35
28
24
21
Factory Default
Wrap Enable Non-Volatile CR4NV[4]: This bit controls the POR, hardware reset, or software reset state of
the Wrap Enable. The commands affected by Wrap Enable are: Quad I/O Read, and DDR Quad I/O Read.
This configuration bit enables the device to start immediately (boot) in wrapped burst read mode rather than
the legacy sequential read mode.
Wrap Length Non-Volatile CR4NV[1:0]: These bits controls the POR, hardware reset, or software reset
state of the wrapped read length and alignment. These non-volatile configuration bits enable the device to
start immediately (boot) in wrapped burst read mode rather than the legacy sequential read mode.
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8.6.6.2
Configuration Register 4 Volatile (CR4V)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h), Set Burst Length
(SBL C0h).
Table 8.26 Configuration Register 4 Volatile (CR4V)
Default
State
Bits
Field Name
Function
Output Impedance
Wrap Enable
Type
Description
7
6
5
OI
See Table 8.25, Output Impedance Control on page 71.
0 = Wrap Enabled.
1 = Wrap Disabled.
4
WE
Volatile
CR4NV
3
2
1
RFU
RFU
Reserved
Reserved
Reserved for Future Use.
Reserved for Future Use.
00 = 8-byte wrap.
01 = 16-byte wrap.
10 = 32-byte wrap.
11 = 64-byte wrap.
WL
Wrap Length
0
Output Impedance CR2V[7:5]: These bits control the IO signal output impedance (drive strength). This
volatile output impedance configuration bit enables the user to adjust the drive strength during normal
operation.
Wrap Enable CR4V[4]: This bit controls the burst wrap feature. This volatile configuration bit enables the
device to enter and exit burst wrapped read mode during normal operation.
Wrap Length CR4V[1:0]: These bits controls the wrapped read length and alignment during normal
operation. These volatile configuration bits enable the user to adjust the burst wrapped read length during
normal operation.
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8.6.7
ASP Register (ASPR)
Related Commands: ASP Read (ASPRD 2Bh) and ASP Program (ASPP 2Fh), Read Any Register (RDAR
65h), Write Any Register (WRAR 71h).
The ASP register is a 16-bit OTP memory location used to permanently configure the behavior of Advanced
Sector Protection (ASP) features. ASPR does not have user programmable volatile bits, all defined bits are
OTP.
The default state of the ASPR bits are programmed by Spansion.
Table 8.27 ASP Register (ASPR)
Default
State
Bits
15 to 9
8
Field Name
RFU
Function
Reserved
Reserved
Type
OTP
OTP
Description
1
Reserved for Future Use.
Reserved for Future Use.
RFU
1
7
6
5
4
3
RFU
RFU
RFU
RFU
RFU
Reserved
Reserved
Reserved
Reserved
Reserved
OTP
OTP
OTP
RFU
RFU
1
1
1
1
1
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
Password
Protection Mode
Lock Bit
0 = Password Protection mode permanently enabled.
1 = Password Protection mode not permanently enabled.
2
PWDMLB
OTP
1
Persistent
Protection Mode
Lock Bit
0 = Persistent Protection mode permanently enabled.
1 = Persistent Protection mode not permanently enabled.
1
0
PSTMLB
RFU
OTP
RFU
1
1
Reserved
Reserved for Future Use.
Password Protection Mode Lock Bit (PWDMLB) ASPR[2]: When programmed to 0, the Password
Protection mode is permanently selected.
Persistent Protection Mode Lock Bit (PSTMLB) ASPR[1]: When programmed to 0, the Persistent
Protection mode is permanently selected.
PWDMLB (ASPR[2]) and PSTMLB (ASPR[1]) are mutually exclusive, only one may be programmed to 0.
ASPR bits may only be programmed while ASPR[2:1] = 11b. Attempting to program ASPR bits when
ASPR[2:1] is not = 11b will result in a programming error with P_ERR (SR1V[6]) set to 1. After the ASP
protection mode is selected by programming ASPR[2:1] = 10b or 01b, the state of all ASPR bits are locked
and permanently protected from further programming. Attempting to program ASPR[2:1] = 00b will result in a
programming error with P_ERR (SR1V[6]) set to 1.
Similarly, OTP configuration bits listed in the ASP Register description (ASP Register on page 81), may only
be programmed while ASPR[2:1] = 11b. The OTP configuration must be selected before selecting the ASP
protection mode. The OTP configuration bits are permanently protected from further change when the ASP
protection mode is selected. Attempting to program these OTP configuration bits when ASPR[2:1] is not =
11b will result in a programming error with P_ERR (SR1V[6]) set to 1.
The ASP protection mode should be selected during system configuration to ensure that a malicious program
does not select an undesired protection mode at a later time. By locking all the protection configuration via the
ASP mode selection, later alteration of the protection methods by malicious programs is prevented.
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8.6.8
Password Register (PASS)
Related Commands: Password Read (PASSRD E7h) and Password Program (PASSP E8h), Read Any
Register (RDAR 65h), Write Any Register (WRAR 71h). The PASS register is a 64-bit OTP memory location
used to permanently define a password for the Advanced Sector Protection (ASP) feature. PASS does not
have user programmable volatile bits, all defined bits are OTP. A volatile copy of PASS is used to satisfy read
latency requirements but the volatile register is not user writable or further described.
Table 8.28 Password Register (PASS)
Field
Name
Bits
Function
Type
Default State
Description
Non-Volatile OTP storage of 64-bit password. The password is
no longer readable after the password protection mode is
selected by programming ASP register bit 2 to 0.
Hidden
Password
FFFFFFFF-
FFFFFFFFh
63 to 0
PWD
OTP
8.6.9
PPB Lock Register (PPBL)
Related Commands: PPB Lock Read (PLBRD A7h, PLBWR A6h), Read Any Register (RDAR 65h).
PPBL does not have separate user programmable non-volatile bits, all defined bits are volatile read only
status. The default state of the RFU bits is set by hardware. The default state of the PPBLOCK bit is defined
by the ASP protection mode bits in ASPR[2:1]. There is no non-volatile version of the PPBL register.
The PPBLOCK bit is used to protect the PPB bits. When PPBL[0] = 0, the PPB bits can not be programmed.
Table 8.29 PPB Lock Register (PPBL)
Bits
Field Name
Function
Type
Default State
Description
Reserved for Future Use
7 to 1
RFU
Reserved
Volatile
00h
ASPR[2:1] = 1xb = Persistent
Protection Mode = 1
ASPR[2:1] = 01b = Password
Protection Mode = 0
0 = PPB array protected.
1 = PPB array may be programmed or erased.
Volatile
Read
Only
0
PPBLOCK Protect PPB Array
8.6.10
PPB Access Register (PPBAR)
Related Commands: PPB Read (PPBRD FCh or 4PPBRD E2h), PPB Program (PPBP FDh or 4PPBP E3h),
PPB Erase (PPBE E4h).
PPBAR does not have user writable volatile bits, all PPB array bits are non-volatile. The default state of the
PPB array is erased to FFh by Spansion. There is no volatile version of the PPBAR register.
Table 8.30 PPB Access Register (PPBAR)
Bits
Field Name
Function
Type
Default State
Description
00h = PPB for the sector addressed by the PPBRD or
PPBP command is programmed to 0, protecting that
sector from program or erase operations.
FFh = PPB for the sector addressed by the PPBRD
command is 1, not protecting that sector from program
or erase operations.
Read or Program
per sector PPB
7 to 0
PPB
Non-Volatile
FFh
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8.6.11
DYB Access Register (DYBAR)
Related Commands: DYB Read (DYBRD FAh or 4DYBRD E0h) and DYB Write (DYBWR FBh or 4DYBWR
E1h).
DYBAR does not have user programmable non-volatile bits, all bits are a representation of the volatile bits in
the DYB array. The default state of the DYB array bits is set by hardware. There is no non-volatile version of
the DYBAR register.
Table 8.31 DYB Access Register (DYBAR)
Bits
Field Name
Function
Type
Default State
Description
00h = DYB for the sector addressed by the DYBRD or DYBWR
command is cleared to 0, protecting that sector from program or
erase operations.
FFh = DYB for the sector addressed by the DYBRD or DYBWR
command is set to 1, not protecting that sector from program or
erase operations.
Read or Write
per sector DYB
7 to 0
DYB
Volatile
FFh
8.6.12
SPI DDR Data Learning Registers
Related Commands: Program NVDLR (PNVDLR 43h), Write VDLR (WVDLR 4Ah), Data Learning Pattern
Read (DLPRD 41h), Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).
The Data Learning Pattern (DLP) resides in an 8-bit Non-Volatile Data Learning Register (NVDLR) as well as
an 8-bit Volatile Data Learning Register (VDLR). When shipped from Spansion, the NVDLR value is 00h.
Once programmed, the NVDLR cannot be reprogrammed or erased; a copy of the data pattern in the NVDLR
will also be written to the VDLR. The VDLR can be written to at any time, but on reset or power cycles the
data pattern will revert back to what is in the NVDLR. During the learning phase described in the SPI DDR
modes, the DLP will come from the VDLR. Each IO will output the same DLP value for every clock edge. For
example, if the DLP is 34h (or binary 00110100) then during the first clock edge all IO’s will output 0;
subsequently, the 2nd clock edge all I/O’s will output 0, the 3rd will output 1, etc.
When the VDLR value is 00h, no preamble data pattern is presented during the dummy phase in the DDR
commands.
Table 8.32 Non-Volatile Data Learning Register (NVDLR)
Bits
Field Name
Function
Type
Default State
Description
OTP value that may be transferred to the host during DDR read
command latency (dummy) cycles to provide a training pattern to
help the host more accurately center the data capture point in the
received data bits.
Non-Volatile
Data Learning
Pattern
7 to 0
NVDLP
OTP
00h
Table 8.33 Volatile Data Learning Register (VDLR)
Bits
Field Name
Function
Type
Default State
Description
Takes the
value of
NVDLR
Volatile Data
Learning
Pattern
Volatile copy of the NVDLP used to enable and deliver the Data
Learning Pattern (DLP) to the outputs. The VDLP may be changed
7 to 0
VDLP
Volatile
during POR by the host during system operation.
or Reset
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9. Data Protection
9.1
Secure Silicon Region (OTP)
The device has a 1024 byte One-Time Program (OTP) address space that is separate from the main flash
array. The OTP area is divided into 32, individually lockable, 32-byte aligned and length regions.
The OTP memory space is intended for increased system security. OTP values can “mate” a flash
component with the system CPU/ASIC to prevent device substitution. See OTP Address Space on page 58,
OTP Program (OTPP 42h) on page 123, and OTP Read (OTPR 4Bh) on page 123.
9.1.1
Reading OTP Memory Space
The OTP Read command uses the same protocol as Fast Read. OTP Read operations outside the valid 1-kB
OTP address range will yield indeterminate data.
9.1.2
Programming OTP Memory Space
The protocol of the OTP programming command is the same as Page Program. The OTP Program command
can be issued multiple times to any given OTP address, but this address space can never be erased.
The valid address range for OTP Program is depicted in Figure 8.1, OTP Address Space on page 58. OTP
Program operations outside the valid OTP address range will be ignored, without P_ERR in SR1V set to 1.
OTP Program operations within the valid OTP address range, while FREEZE = 1, will fail with P_ERR in
SR1V set to 1. The OTP address space is not protected by the selection of an ASP Protection mode. The
Freeze bit (CR1V[0]) may be used to protect the OTP Address Space.
9.1.3
9.1.4
Spansion Programmed Random Number
Spansion standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to
0xF) with a 128-bit random number using the Linear Congruential Random Number Method. The seed value
for the algorithm is a random number concatenated with the day and time of tester insertion.
Lock Bytes
The LSB of each Lock byte protects the lowest address region related to the byte, the MSB protects the
highest address region related to the byte. The next higher address byte similarly protects the next higher 8
regions. The LSB bit of the lowest address Lock Byte protects the higher address 16 bytes of the lowest
address region. In other words, the LSB of location 0x10 protects all the Lock Bytes and RFU bytes in the
lowest address region from further programming. See OTP Address Space on page 58.
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9.2
Write Enable Command
The Write Enable (WREN) command must be written prior to any command that modifies non-volatile data.
The WREN command sets the Write Enable Latch (WEL) bit. The WEL bit is cleared to 0 (disables writes)
during power-up, hardware reset, or after the device completes the following commands:
Reset
Page Program (PP or 4PP)
Parameter 4-kB Erase (P4E or 4P4E)
Sector Erase (SE or 4SE)
Bulk Erase (BE)
Write Disable (WRDI)
Write Registers (WRR)
Write Any Register (WRAR)
OTP Byte Programming (OTPP)
Advanced Sector Protection Register Program (ASPP)
Persistent Protection Bit Program (PPBP)
Persistent Protection Bit Erase (PPBE)
Password Program (PASSP)
Program Non-Volatile Data Learning Register (PNVDLR)
9.3
Block Protection
The Block Protect bits (Status Register bits BP2, BP1, BP0) in combination with the Configuration Register
TBPROT_O bit can be used to protect an address range of the main flash array from program and erase
operations. The size of the range is determined by the value of the BP bits and the upper or lower starting
point of the range is selected by the TBPROT_O bit of the Configuration Register (CR1NV[5]).
Table 9.1 Upper Array Start of Protection (TBPROT_O = 0)
Status Register Content
BP1
Protected Memory (kbytes)
Protected Fraction
of Memory Array
FS128S
128 Mb
FS256S
256 Mb
BP2
BP0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
0
0
Upper 64th
Upper 32nd
Upper 16th
Upper 8th
Upper 4th
Upper Half
All Sectors
256
512
512
1024
2048
4096
8192
16384
32768
1024
2048
4096
8192
16384
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Table 9.2 Lower Array Start of Protection (TBPROT_O = 1)
Status Register Content
Protected Memory (kbytes)
Protected Fraction
of Memory Array
FS128S
128 Mb
FS256S
256 Mb
BP2
BP1
BP0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
0
0
Lower 64th
Lower 32nd
Lower 16th
Lower 8th
Lower 4th
Lower Half
All Sectors
256
512
512
1024
2048
4096
8192
16384
32768
1024
2048
4096
8192
16384
When Block Protection is enabled (i.e., any BP2-0 are set to 1), Advanced Sector Protection (ASP) can still
be used to protect sectors not protected by the Block Protection scheme. In the case that both ASP and Block
Protection are used on the same sector the logical OR of ASP and Block Protection related to the sector is
used.
9.3.1
9.3.2
Freeze Bit
Bit 0 of Configuration Register 1 (CR1V[0]) is the FREEZE bit. The Freeze bit, when set to 1, locks the current
state of the Block Protection control bits and OTP area until the next power off-on cycle. Additional details in
Configuration Register 1 Volatile (CR1V) on page 64.
Write Protect Signal
The Write Protect (WP#) input in combination with the Status Register Write Disable (SRWD) bit (SR1NV[7])
provide hardware input signal controlled protection. When WP# is Low and SRWD is set to 1
Status Register 1 (SR1NV and SR1V) and Configuration Register 1 (CR1NV and CR1V) are protected from
alteration. This prevents disabling or changing the protection defined by the Block Protect bits. See Status
Register 1 on page 60.
9.4
Advanced Sector Protection
Advanced Sector Protection (ASP) is the name used for a set of independent hardware and software
methods used to disable or enable programming or erase operations, individually, in any or all sectors.
Every main flash array sector has a non-volatile Persistent Protection Bit (PPB) and a volatile Dynamic
Protection Bit (DYB) associated with it. When either bit is 0, the sector is protected from program and erase
operations. The PPB bits are protected from program and erase when the volatile PPB Lock bit is 0. There
are two methods for managing the state of the PPB Lock bit: Password Protection and Persistent Protection.
An overview of these methods is shown in Figure 9.2, Advanced Sector Protection Overview on page 80.
Block Protection and ASP protection settings for each sector are logically ORed to define the protection for
each sector i.e. if either mechanism is protecting a sector the sector cannot be programmed or erased. Refer
to Block Protection on page 77 for full details of the BP2-0 bits.
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Figure 9.1 Sector Protection Control
Dynamic
Protection
Bits Array
(DYB)
Persistent
Protection
Bits Array
(PPB)
Flash
Memory
Array
Sector 0
Sector 0
Sector 0
Sector 1
Sector 1
Sector 1
Block
Protection
Logic
Sector N
Sector N
Sector N
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Figure 9.2 Advanced Sector Protection Overview
Power On / Reset
ASPR[2]=0
ASPR[1]=0
No
No
Yes
Yes
Default
Persistent Protection
Persistent Protection
Password Protection
ASPR Bits Locked
ASPR Bits Are
Programmable
ASPR Bits Locked
PPBLOCK = 0
PPB Bits Locked
PPBLOCK = 1
PPB Bits Erasable
and Programmable
No
No
PPB Lock Bit Write
Password Unlock
Yes
Yes
PPBLOCK = 1
PPB Bits Erasable
and Programmable
PPBLOCK = 0
PPB Bits Locked
Default Mode allows
ASPR to be programmed
to permanently select
the Protection mode.
No
PPB Lock Bit Write
The default mode otherwise
acts the same as the
Yes
Persistent Protection Mode.
Persistent Protection
Mode does not
protect the PPB after
power up. The bits may
be changed. A PPB
Lock Bit write command
protects the PPB bits
until the next power-off
or reset.
Password Protection
Mode protects the
PPB after power up.
A password unlock
command will enable
changes to PPB. A PPB
Lock Bit write command
turns protection back on.
After one of the protection
modes is selected, ASPR
is no longer programmable,
making the selected protection
mode permanent.
The Persistent Protection method sets the PPB Lock bit to 1 during POR, or hardware reset so that the PPB
bits are unprotected by a device reset. There is a command to clear the PPB Lock bit to 0 to protect the PPB.
There is no command in the Persistent Protection method to set the PPB Lock bit to 1, therefore the PPB
Lock bit will remain at 0 until the next power-off or hardware reset. The Persistent Protection method allows
boot code the option of changing sector protection by programming or erasing the PPB, then protecting the
PPB from further change for the remainder of normal system operation by clearing the PPB Lock bit to 0. This
is sometimes called Boot-code controlled sector protection.
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The Password method clears the PPB Lock bit to 0 during POR, or hardware reset to protect the PPB. A 64-
bit password may be permanently programmed and hidden for the password method. A command can be
used to provide a password for comparison with the hidden password. If the password matches, the PPB
Lock bit is set to 1 to unprotect the PPB. A command can be used to clear the PPB Lock bit to 0. This method
requires use of a password to control PPB protection.
The selection of the PPB Lock bit management method is made by programming OTP bits in the ASP
Register so as to permanently select the method used.
9.4.1
ASP Register
The ASP register is used to permanently configure the behavior of Advanced Sector Protection (ASP)
features. See Table 8.27, ASP Register (ASPR) on page 73.
As shipped from the factory, all devices default ASP to the Persistent Protection mode, with all sectors
unprotected, when power is applied. The device programmer or host system must then choose which sector
protection method to use. Programming either of the, one-time programmable, Protection Mode Lock bits,
locks the part permanently in the selected mode:
ASPR[2:1] = “11” = No ASP mode selected, Persistent Protection mode is the default.
ASPR[2:1] = “10” = Persistent Protection mode permanently selected.
ASPR[2:1] = “01” = Password Protection mode permanently selected.
ASPR[2:1] = “00” is an Illegal condition, attempting to program more than one bit to zero results in a
programming failure.
ASP register programming rules:
If the password mode is chosen, the password must be programmed prior to setting the Protection Mode
Lock bits.
Once the Protection mode is selected, the following OTP Configuration Register bits are permanently
protected from programming and no further changes to the OTP register bits is allowed:
– CR1NV[5:2]
– CR2NV
– CR3NV
– CR4NV
– ASPR
– PASS
– NVDLR
– If an attempt to change any of the registers above, after the ASP mode is selected, the operation will
fail and P_ERR (SR1V[6]) will be set to 1.
The programming time of the ASP register is the same as the typical page programming time. The system
can determine the status of the ASP register programming operation by reading the WIP bit in the Status
Register. See Status Register 1 on page 60 for information on WIP.
See Sector Protection States Summary on page 83.
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9.4.2
Persistent Protection Bits
The Persistent Protection Bits (PPB) are located in a separate non-volatile flash array. One of the PPB bits is
related to each sector. When a PPB is 0, its related sector is protected from program and erase operations.
The PPB are programmed individually but must be erased as a group, similar to the way individual words may
be programmed in the main array but an entire sector must be erased at the same time. The PPB have the
same program and erase endurance as the main flash memory array. Preprogramming and verification prior
to erasure are handled by the device.
Programming a PPB bit requires the typical page programming time. Erasing all the PPBs requires typical
Sector Erase time. During PPB bit programming and PPB bit erasing, status is available by reading the Status
Register. Reading of a PPB bit requires the initial access time of the device.
Notes:
1. Each PPB is individually programmed to 0 and all are erased to 1 in parallel.
2. If the PPB Lock bit is 0, the PPB Program or PPB Erase command does not execute and fails
without programming or erasing the PPB.
3. The state of the PPB for a given sector can be verified by using the PPB Read command.
9.4.3
9.4.4
Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYB only
control the protection for sectors that have their PPB set to 1. By issuing the DYB Write command, a DYB is
cleared to 0 or set to 1, thus placing each sector in the protected or unprotected state respectively. This
feature allows software to easily protect sectors against inadvertent changes, yet does not prevent the easy
removal of protection when changes are needed. The DYBs can be set or cleared as often as needed as they
are volatile bits.
PPB Lock Bit (PPBL[0])
The PPB Lock Bit is a volatile bit for protecting all PPB bits. When cleared to 0, it locks all PPBs, when set to
1, it allows the PPBs to be changed. See Section 8.6.9, PPB Lock Register (PPBL) on page 74 for more
information.
The PLBWR command is used to clear the PPB Lock bit to 0. The PPB Lock Bit must be cleared to 0 only
after all the PPBs are configured to the desired settings.
In Persistent Protection mode, the PPB Lock is set to 1 during POR or a hardware reset. When cleared to 0,
no software command sequence can set the PPB Lock bit to 1, only another hardware reset or power-up can
set the PPB Lock bit.
In the Password Protection mode, the PPB Lock bit is cleared to 0 during POR or a hardware reset. The PPB
Lock bit can only be set to 1 by the Password Unlock command.
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9.4.5
Sector Protection States Summary
Each sector can be in one of the following protection states:
Unlocked — The sector is unprotected and protection can be changed by a simple command. The
protection state defaults to unprotected when the device is shipped from Spansion.
Dynamically Locked — A sector is protected and protection can be changed by a simple command. The
protection state is not saved across a power cycle or reset.
Persistently Locked — A sector is protected and protection can only be changed if the PPB Lock bit is set
to 1. The protection state is non-volatile and saved across a power cycle or reset. Changing the protection
state requires programming and or erase of the PPB bits.
Table 9.3 Sector Protection States
Protection Bit Values
Sector State
PPB Lock
PPB
DYB
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
Unprotected – PPB and DYB are changeable.
Protected – PPB and DYB are changeable.
0
1
Protected – PPB and DYB are changeable.
0
Protected – PPB and DYB are changeable.
1
Unprotected – PPB not changeable, DYB is changeable.
Protected – PPB not changeable, DYB is changeable.
Protected – PPB not changeable, DYB is changeable.
Protected – PPB not changeable, DYB is changeable.
0
1
0
9.4.6
9.4.7
Persistent Protection Mode
The Persistent Protection method sets the PPB Lock bit to 1 during POR or hardware reset so that the PPB
bits are unprotected by a device hardware reset. Software reset does not affect the PPB Lock bit. The
PLBWR command can clear the PPB Lock bit to 0 to protect the PPB. There is no command to set the PPB
Lock bit therefore the PPB Lock bit will remain at 0 until the next power-off or hardware reset.
Password Protection Mode
Password Protection mode allows an even higher level of security than the Persistent Sector Protection
mode, by requiring a 64-bit password for unlocking the PPB Lock bit. In addition to this password
requirement, after power-up and hardware reset, the PPB Lock bit is cleared to 0 to ensure protection at
power-up. Successful execution of the Password Unlock command by entering the entire password sets the
PPB Lock bit to 1, allowing for sector PPB modifications.
Password Protection Notes:
Once the Password is programmed and verified, the Password mode (ASPR[2]=0) must be set in order to
prevent reading the password.
The Password Program Command is only capable of programming 0s. Programming a 1 after a cell is
programmed as a 0 results in the cell left as a 0 with no programming error set.
The password is all 1s when shipped from Spansion. It is located in its own memory space and is
accessible through the use of the Password Program, Password Read, RDAR, and WRAR commands.
All 64-bit password combinations are valid as a password.
The Password mode, once programmed, prevents reading the 64-bit password and further password
programming. All further program and read commands to the password region are disabled and these
commands are ignored or return undefined data. There is no means to verify what the password is after the
Password Mode Lock bit is selected. Password verification is only allowed before selecting the Password
Protection mode.
The Protection Mode Lock bits are not erasable.
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The exact password must be entered in order for the unlocking function to occur. If the password unlock
command provided password does not match the hidden internal password, the unlock operation fails in
the same manner as a programming operation on a protected sector. The P_ERR bit is set to 1, the WIP bit
remains set, and the PPB Lock bit remains cleared to 0.
The Password Unlock command cannot be accepted any faster than once every 100 µs 20 µs. This
makes it take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit
combinations in an attempt to correctly match a password. The Read Status Register 1 command may be
used to read the WIP bit to determine when the device has completed the password unlock command or is
ready to accept a new password command. When a valid password is provided the password unlock
command does not insert the 100 µs delay before returning the WIP bit to 0.
If the password is lost after selecting the Password mode, there is no way to set the PPB Lock bit.
9.5
Recommended Protection Process
During system manufacture, the flash device configuration should be defined by:
1. Programming the OTP configuration bits in CR1NV[5, 3:2], CR2NV, CR3NV, and CR4NV as
desired.
2. Program the Secure Silicon Region (OTP area) as desired.
3. Program the PPB bits as desired via the PPBP command.
4. Program the Non-Volatile Data Learning Pattern (NVDLR) if it will be used in DDR read
commands.
5. Program the Password register (PASS) if password protection will be used.
6. Program the ASP Register as desired, including the selection of the persistent or password ASP
protection mode in ASPR[2:1]. It is very important to explicitly select a protection mode so that later
accidental or malicious programming of the ASP register and OTP configuration is prevented. This
is to ensure that only the intended OTP protection and configuration features are enabled.
During system power-up and boot code execution:
1. Trusted boot code can determine whether there is any need to program additional SSR (OTP area)
information. If no SSR changes are needed the FREEZE bit (CR1V[0]) can be set to 1 to protect
the SSR from changes during the remainder of normal system operation while power remains on.
2. If the Persistent Protection mode is in use, trusted boot code can determine whether there is any
need to modify the persistent (PPB) sector protection via the PPBP or PPBE commands. If no PPB
changes are needed the PPBLOCK bit can be cleared to 0 via the PPBL to protect the PPB bits
from changes during the remainder of normal system operation while power remains on.
3. The Dynamic (DYB) Sector Protection bits can be written as desired via the DYBAR.
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10. Commands
All communication between the host system and S25FS-S family memory devices is in the form of units
called commands.
All commands begin with an instruction that selects the type of information transfer or device operation to be
performed. Commands may also have an address, instruction modifier, latency period, data transfer to the
memory, or data transfer from the memory. All instruction, address, and data information is transferred
sequentially between the host system and memory device.
Command protocols are also classified by a numerical nomenclature using three numbers to reference the
transfer width of three command phases:
instruction;
address and instruction modifier (mode);
data.
Single bit wide commands start with an instruction and may provide an address or data, all sent only on the SI
signal. Data may be sent back to the host serially on the SO signal. This is referenced as a 1-1-1 command
protocol for single bit width instruction, single bit width address and modifier, single bit data.
Dual or Quad Input / Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and
IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on
IO0 and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. This is referenced as 1-2-2 for Dual I/O
and 1-4-4 for Quad I/O command protocols.
The S25FS-S family also supports a QPI Mode in which all information is transferred in 4-bit width, including
the instruction, address, modifier, and data. This is referenced as a 4-4-4 command protocol.
Commands are structured as follows:
Each command begins with an eight bit (byte) instruction. However, some read commands are modified by
a prior read command, such that the instruction is implied from the earlier command. This is called
Continuous Read mode. When the device is in Continuous Read mode, the instruction bits are not
transmitted at the beginning of the command because the instruction is the same as the read command
that initiated the Continuous Read mode. In Continuous Read mode the command will begin with the read
address. Thus, Continuous Read mode removes eight instruction bits from each read command in a series
of same type read commands.
The instruction may be stand alone or may be followed by address bits to select a location within one of
several address spaces in the device. The address may be either a 24-bit or 32-bit, byte boundary,
address.
The Serial Peripheral Interface with Multiple IO provides the option for each transfer of address and data
information to be done one, two, or four bits in parallel. This enables a trade off between the number of
signal connections (IO bus width) and the speed of information transfer. If the host system can support a
two or four bit wide IO bus the memory performance can be increased by using the instructions that
provide parallel 2-bit (dual) or parallel 4-bit (quad) transfers.
In legacy SPI Multiple IO mode, the width of all transfers following the instruction are determined by the
instruction sent. Following transfers may continue to be single bit serial on only the SI or Serial Output (SO)
signals, they may be done in two bit groups per (dual) transfer on the IO0 and IO1 signals, or they may be
done in 4-bit groups per (quad) transfer on the IO0-IO3 signals. Within the dual or quad groups the least
significant bit is on IO0. More significant bits are placed in significance order on each higher numbered IO
signal. Single bits or parallel bit groups are transferred in most to least significant bit order.
In QPI Mode, the width of all transfers, including instructions, is a 4-bit wide (quad) transfer on the IO0-IO3
signals.
Dual I/O and Quad I/O read instructions send an instruction modifier called mode bits, following the
address, to indicate that the next command will be of the same type with an implied, rather than an explicit,
instruction. The next command thus does not provide an instruction byte, only a new address and mode
bits. This reduces the time needed to send each command when the same command type is repeated in a
sequence of commands.
The address or mode bits may be followed by write data to be stored in the memory device or by a read
latency period before read data is returned to the host.
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Read latency may be zero to several SCK cycles (also referred to as dummy cycles).
All instruction, address, mode, and data information is transferred in byte granularity. Addresses are shifted
into the device with the most significant byte first. All data is transferred with the lowest address byte sent
first. Following bytes of data are sent in lowest to highest byte address order i.e. the byte address
increments.
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded
operations) are ignored. The embedded operation will continue to execute without any affect. A very
limited set of commands are accepted during an embedded operation. These are discussed in the
individual command descriptions. While a program, erase, or write operation is in progress, it is
recommended to check that the Write-In Progress (WIP) bit is 0 before issuing most commands to the
device, to ensure the new command can be accepted.
Depending on the command, the time for execution varies. A command to read status information from an
executing command is available to determine when the command completes execution and whether the
command was successful.
Although host software in some cases is used to directly control the SPI interface signals, the hardware
interfaces of the host system and the memory device generally handle the details of signal relationships
and timing. For this reason, signal relationships and timing are not covered in detail within this software
interface focused section of the document. Instead, the focus is on the logical sequence of bits transferred
in each command rather than the signal timing and relationships. Following are some general signal
relationship descriptions to keep in mind. For additional information on the bit level format and signal timing
relationships of commands, see Command Protocol on page 24.
– The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI) - SI for single
bit wide transfers. The memory drives Serial Output (SO) for single bit read transfers. The host and
memory alternately drive the IO0-IO3 signals during Dual and Quad transfers.
– All commands begin with the host selecting the memory by driving CS# low before the first rising edge
of SCK. CS# is kept low throughout a command and when CS# is returned high the command ends.
Generally, CS# remains low for eight bit transfer multiples to transfer byte granularity information.
Some commands will not be accepted if CS# is returned high not at an 8-bit boundary.
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10.1 Command Set Summary
10.1.1 Extended Addressing
To accommodate addressing above 128 Mb, there are two options:
1. Instructions that always require a 4-byte address, used to access up to 32 Gb of memory:
Command Name
4READ
Function
Read
Instruction (Hex)
13
0C
BC
EC
EE
12
4FAST_READ
4DIOR
Read Fast
Dual I/O Read
Quad I/O Read
DDR Quad I/O Read
Page Program
Parameter 4-kB Erase
Erase 64/256 kB
DYB Read
4QIOR
4DDRQIOR
4PP
4P4E
21
4SE
DC
E0
E1
E2
E3
4DYBRD
4DYBWR
4PPBRD
4PPBP
DYBWR
PPB Read
PPB Program
2. A 4-byte address mode for backward compatibility to the 3-byte address instructions. The standard
3-byte instructions can be used in conjunction with a 4-byte address mode controlled by the
Address Length configuration bit (CR2V[7]). The default value of CR2V[7] is loaded from
CR2NV[7] (following power-up, hardware reset, or software reset), to enable default 3-byte (24-bit)
or 4-byte (32-bit) addressing. When the address length (CR2V[7]) set to 1, the legacy commands
are changed to require 4-bytes (32-bits) for the address field. The following instructions can be
used in conjunction with the 4-byte address mode configuration to switch from 3 bytes to 4 bytes of
address field.
Command Name
READ
Function
Read
Instruction (Hex)
03
0B
BB
EB
ED
02
FAST_READ
DIOR
Read Fast
Dual I/O Read
Quad I/O Read
DDR Quad I/O Read)
Page Program
Parameter 4-kB Erase
Erase 64 / 256 kB
Read Any Register
Write Any Register
Evaluate Erase Status
OTP Program
OTP Read
QIOR
DDRQIOR
PP
P4E
20
SE
D8
65
RDAR
WRAR
EES
71
D0
42
OTPP
OTPR
4B
FA
FB
FC
FD
DYBRD
DYBWR
PPBRD
PPBP
DYB Read
DYBWR
PPB Read
PPB Program
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10.1.2
Command Summary by Function
Table 10.1 S25FS-S Family Command Set (sorted by function) (Sheet 1 of 2)
Instruction Maximum Address
Command
Name
Function
Command Description
Value
(Hex)
Frequency
(MHz)
Length
(Bytes)
QPI
RDID
RSFDP
RDQID
RDSR1
RDSR2
RDCR
RDAR
WRR
Read ID (JEDEC Manufacturer ID and JEDEC CFI)
Read JEDEC Serial Flash Discoverable Parameters
Read Quad ID
9F
5A
AF
05
07
35
65
01
04
06
71
133
50
0
Yes
Yes
Yes
Yes
No
Read
Device ID
3
133
133
133
133
133
133
133
133
133
0
Read Status Register 1
0
Read Status Register 2
0
Read Configuration Register 1
Read Any Register
0
3 or 4
0
No
Yes
Yes
Yes
Yes
Yes
Write Register (Status 1, Configuration 1)
Write Disable
WRDI
0
WREN
WRAR
Write Enable
0
Write Any Register
3 or 4
Clear Status Register 1 - Erase/Prog. Fail Reset
This command may be disabled and the instruction value
instead used for a program / erase resume command - see
Configuration Register 3 on page 69
CLSR
30
133
0
Yes
Register
Access
Clear Status Register 1 (alternate instruction) -
Erase/Prog. Fail Reset
CLSR
82
133
0
Yes
4BAM
SBL
Enter 4-byte Address Mode
Set Burst Length
B7
C0
D0
41
133
133
133
133
133
133
50
0
No
No
Yes
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
0
3 or 4
0
EES
Evaluate Erase Status
Data Learning Pattern Read
Program NV Data Learning Register
Write Volatile Data Learning Register
Read
DLPRD
PNVDLR
WVDLR
READ
43
0
4A
03
0
3 or 4
4
4READ
FAST_READ
Read
13
50
Fast Read
0B
0C
BB
BC
EB
EC
ED
EE
02
133
133
66
3 or 4
4
4FAST_READ Fast Read
Read
Flash
Array
DIOR
4DIOR
Dual I/O Read
3 or 4
4
Dual I/O Read
66
QIOR
Quad I/O Read
133
133
80
3 or 4
4
4QIOR
DDRQIOR
4DDRQIOR
PP
Quad I/O Read
DDR Quad I/O Read
DDR Quad I/O Read
Page Program
3 or 4
4
80
Program
Flash
Array
133
3 or 4
4PP
Page Program
12
133
4
Yes
P4E
4P4E
SE
Parameter 4-kB Sector Erase
Parameter 4-kB Sector Erase
Erase 64 kB or 256 kB
Erase 64 kB or 256 kB
Bulk Erase
20
21
133
133
133
133
133
133
3 or 4
Yes
Yes
Yes
Yes
Yes
Yes
4
Erase
Flash
Array
D8
DC
60
3 or 4
4SE
BE
4
0
0
BE
Bulk Erase (alternate instruction)
C7
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Table 10.1 S25FS-S Family Command Set (sorted by function) (Sheet 2 of 2)
Instruction Maximum Address
Command
Name
Function
Command Description
Erase / Program Suspend
Value
(Hex)
Frequency
(MHz)
Length
(Bytes)
QPI
EPS
EPS
EPS
EPR
EPR
75
85
B0
7A
8A
133
133
133
133
133
0
0
0
0
0
Yes
Yes
Yes
Yes
Yes
Erase / Program Suspend (alternate instruction)
Erase / Program Suspend (alternate instruction)
Erase / Program Resume
Erase
/Program
Erase / Program Resume (alternate instruction)
Suspend
/Resume
Erase / Program Resume (alternate instruction)
This command may be disabled and the instruction value
instead used for a clear status command - see
Configuration Register 3 on page 69
EPR
30
133
0
Yes
One-Time
Program
Array
OTPP
OTPR
OTP Program
OTP Read
42
4B
133
133
3 or 4
3 or 4
No
No
DYBRD
4DYBRD
DYBWR
4DYBWR
PPBRD
4PPBRD
PPBP
DYB Read
FA
E0
FB
E1
FC
E2
FD
E3
E4
2B
2F
A7
A6
E7
E8
E9
66
133
133
133
133
133
133
133
133
133
133
133
133
133
133
133
133
133
133
133
133
3 or 4
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
No
Yes
DYB Read
4
DYB Write
3 or 4
DYB Write
4
PPB Read
3 or 4
PPB Read
4
PPB Program
PPB Program
PPB Erase
3 or 4
Advanced
Sector
Protection
4PPBP
PPBE
4
0
0
0
0
0
0
0
0
0
0
0
0
ASPRD
ASPP
ASP Read
ASP Program
PPB Lock Bit Read
PPB Lock Bit Write
Password Read
Password Program
Password Unlock
Software Reset Enable
Software Reset
Legacy Software Reset
Mode Bit Reset
PLBRD
PLBWR
PASSRD
PASSP
PASSU
RSTEN
RST
99
F0
FF
Reset
RESET
MBR
Note:
1. Commands not supported in QPI Mode have undefined behavior if sent when the device is in QPI Mode.
10.1.3
10.1.4
Read Device Identification
There are multiple commands to read information about the device manufacturer, device type, and device
features. SPI memories from different vendors have used different commands and formats for reading
information about the memories. The S25FS-S family supports the three device information commands.
Register Read or Write
There are multiple registers for reporting embedded operation status or controlling device configuration
options. There are commands for reading or writing these registers. Registers contain both volatile and non-
volatile bits. Non-Volatile bits in registers are automatically erased and programmed as a single (write)
operation.
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10.1.4.1 Monitoring Operation Status
The host system can determine when a write, program, erase, suspend or other embedded operation is
complete by monitoring the Write-In-Progress (WIP) bit in the Status Register. The Read from
Status Register 1 command or Read Any Register command provides the state of the WIP bit. The program
error (P_ERR) and erase error (E_ERR) bits in the Status Register indicate whether the most recent program
or erase command has not completed successfully. When P_ERR or E_ERR bits are set to 1, the WIP bit will
remain set to one indicating the device remains busy and unable to receive most new operation commands.
Only Status Read (RDSR1 05h), Read Any Register (RDAR 65h), Status Clear (CLSR 30h or 82h), and
Software Reset (RSTEN 66h, RST 99h or RESET F0h) are valid commands when P_ERR or E_ERR is set to
1. A Clear Status Register (CLSR) followed by a Write Disable (WRDI) command must be sent to return the
device to standby state. Clear Status Register clears the WIP, P_ERR, and E_ERR bits. WRDI clears the
WEL bit. Alternatively, hardware reset, or software reset (RST or RESET) may be used to return the device to
standby state.
10.1.4.2 Configuration
There are commands to read, write, and protect registers that control interface path width, interface timing,
interface address length, and some aspects of data protection.
10.1.5
Read Flash Array
Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from
incrementally higher byte addresses until the host ends the data transfer by driving CS# input High. If the byte
address reaches the maximum address of the memory array, the read will continue at address zero of the
array.
There are several different read commands to specify different access latency and data path widths. Double
Data Rate (DDR) commands also define the address and data bit relationship to both SCK edges:
The Read command provides a single address bit per SCK rising edge on the SI signal with read data
returning a single bit per SCK falling edge on the SO signal. This command has zero latency between the
address and the returning data but is limited to a maximum SCK rate of 50MHz.
Other read commands have a latency period between the address and returning data but can operate at
higher SCK frequencies. The latency depends on a Configuration Register read latency value.
The Fast Read command provides a single address bit per SCK rising edge on the SI signal with read data
returning a single bit per SCK falling edge on the SO signal.
Dual or Quad I/O Read commands provide address two bits or four bits per SCK rising edge with read data
returning two bits, or four bits of data per SCK falling edge on the IO0-IO3 signals.
Quad Double Data Rate read commands provide address four bits per every SCK edge with read data
returning four bits of data per every SCK edge on the IO0-IO3 signals.
10.1.6
10.1.7
Program Flash Array
Programming data requires two commands: Write Enable (WREN), and Page Program (PP). The Page
Program command accepts from 1 byte up to 256 or 512 consecutive bytes of data (page) to be programmed
in one operation. Programming means that bits can either be left at 1, or programmed from 1 to 0. Changing
bits from 0 to 1 requires an erase operation.
Erase Flash Array
The Parameter Sector Erase, Sector Erase, or Bulk Erase commands set all the bits in a sector or the entire
memory array to 1. A bit needs to be first erased to 1 before programming can change it to a 0. While bits can
be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide or array-
wide (bulk) level. The Write Enable (WREN) command must precede an erase command.
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10.1.8
10.1.9
OTP, Block Protection, and Advanced Sector Protection
There are commands to read and program a separate One-Time Programmable (OTP) array for permanent
data such as a serial number. There are commands to control a contiguous group (block) of flash memory
array sectors that are protected from program and erase operations. There are commands to control which
individual flash memory array sectors are protected from program and erase operations.
Reset
There are commands to reset to the default conditions present after power-on to the device. However, the
software reset commands do not affect the current state of the FREEZE or PPB Lock bits. In all other
respects a software reset is the same as a hardware reset.
There is a command to reset (exit from) the Continuous Read mode.
10.1.10 Reserved
Some instructions are reserved for future use. In this generation of the S25FS-S family some of these
command instructions may be unused and not affect device operation, some may have undefined results.
Some commands are reserved to ensure that a legacy or alternate source device command is allowed
without effect. This allows legacy software to issue some commands that are not relevant for the current
generation S25FS-S family with the assurance these commands do not cause some unexpected action.
Some commands are reserved for use in special versions of the FS-S not addressed by this document or for
a future generation. This allows new host memory controller designs to plan the flexibility to issue these
command instructions. The command format is defined if known at the time this document revision is
published.
10.2 Identification Commands
10.2.1
Read Identification (RDID 9Fh)
The Read Identification (RDID) command provides read access to manufacturer identification, device
identification, and Common Flash Interface (CFI) information. The manufacturer identification is assigned by
JEDEC. The CFI structure is defined by JEDEC standard. The device identification and CFI values are
assigned by Spansion.
The JEDEC Common Flash Interface (CFI) specification defines a device information structure, which allows
a vendor-specified software flash management program (driver) to be used for entire families of flash devices.
Software support can then be device-independent, JEDEC manufacturer ID independent, forward and
backward-compatible for the specified flash device families. System vendors can standardize their flash
drivers for long-term software compatibility by using the CFI values to configure a family driver from the CFI
information of the device in use.
Any RDID command issued while a program, erase, or write cycle is in progress is ignored and has no effect
on execution of the program, erase, or write cycle that is in progress.
The RDID instruction is shifted on SI. After the last bit of the RDID instruction is shifted into the device, a byte
of manufacturer identification, two bytes of device identification, extended device identification, and CFI
information will be shifted sequentially out on SO. As a whole this information is referred to as ID-CFI. See
Device ID and Common Flash Interface (ID-CFI) Address Map on page 143 for the detail description of the
ID-CFI contents.
Continued shifting of output beyond the end of the defined ID-CFI address space will provide undefined data.
The RDID command sequence is terminated by driving CS# to the logic high state anytime during data
output.
The maximum clock frequency for the RDID command is 133 MHz.
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Figure 10.1 Read Identification (RDID) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Data1
DataN
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3 and the
returning data is shifted out on IO0-IO3.
Figure 10.2 Read Identification (RDID) QPI Mode Command
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruction
D1
D2
D3
D4
D5
10.2.2
Read Quad Identification (RDQID AFh)
The Read Quad Identification (RDQID) command provides read access to manufacturer identification, device
identification, and Common Flash Interface (CFI) information. This command is an alternate way of reading
the same information provided by the RDID command while in QPI Mode. In all other respects the command
behaves the same as the RDID command.
The command is recognized only when the device is in QPI Mode (CR2V[6]=1). The instruction is shifted in
on IO0-IO3. After the last bit of the instruction is shifted into the device, a byte of manufacturer identification,
two bytes of device identification, extended device identification, and CFI information will be shifted
sequentially out on IO0-IO3. As a whole this information is referred to as ID-CFI. See Device ID and Common
Flash Interface (ID-CFI) Address Map on page 143 for the detail description of the ID-CFI contents.
Continued shifting of output beyond the end of the defined ID-CFI address space will provide undefined data.
The command sequence is terminated by driving CS# to the logic high state anytime during data output.
The maximum clock frequency for the command is 133 MHz.
Figure 10.3 Read Quad Identification (RDQID) Command Sequence
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruction
D1
D2
D3
D4
D5
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10.2.3
Read Serial Flash Discoverable Parameters (RSFDP 5Ah)
The command is initiated by shifting on SI the instruction code “5Ah”, followed by a 24-bit address of
000000h, followed by 8 dummy cycles. The SFDP bytes are then shifted out on SO starting at the falling edge
of SCK after the dummy cycles. The SFDP bytes are always shifted out with the MSB first. If the 24-bit
address is set to any other value, the selected location in the SFDP space is the starting point of the data
read. This enables random access to any parameter in the SFDP space. The RSFDP command is supported
up to 50 MHz.
Figure 10.4 RSFDP Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
23
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Address
Dummy Cycles
Data1
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3 and the
returning data is shifted out on IO0-IO3.
Figure 10.5 RSFDP QPI Mode Command Sequence
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
20
21
22
23
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruct.
Address
Dummy
D1
D2
D3
D4
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10.3 Register Access Commands
10.3.1
Read Status Register 1 (RDSR1 05h)
The Read Status Register 1 (RDSR1) command allows the Status Register 1 contents to be read from SO.
The volatile version of Status Register 1 (SR1V) contents may be read at any time, even while a program,
erase, or write operation is in progress. It is possible to read Status Register 1 continuously by providing
multiples of eight clock cycles. The status is updated for each eight cycle read. The maximum clock frequency
for the RDSR1 (05h) command is 133 MHz.
Figure 10.6 Read Status Register 1 (RDSR1) Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Status
Updated Status
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3 and the
returning data is shifted out on IO0-IO3, two clock cycles per byte.
Figure 10.7 Read Status Register 1 (RDSR1) QPI Mode Command
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruct.
D1
D2
D3
D4
D5
10.3.2
Read Status Register 2 (RDSR2 07h)
The Read Status Register 2 (RDSR2) command allows the Status Register 2 contents to be read from SO.
The Status Register 2 contents may be read at any time, even while a program, erase, or write operation is in
progress. It is possible to read the Status Register 2 continuously by providing multiples of eight clock cycles.
The status is updated for each eight cycle read. The maximum clock frequency for the RDSR2 command is
133 MHz.
Figure 10.8 Read Status Register 2 (RDSR2) Command
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Status
Updated Status
In QPI Mode, Status Register 2 may be read via the Read Any Register command, see Read Any Register
(RDAR 65h) on page 101
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10.3.3
Read Configuration Register (RDCR 35h)
The Read Configuration Register (RDCR) command allows the volatile Configuration Register (CR1V)
contents to be read from SO. It is possible to read CR1V continuously by providing multiples of eight clock
cycles. The Configuration Register contents may be read at any time, even while a program, erase, or write
operation is in progress.
Figure 10.9 Read Configuration Register (RDCR) Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Register Read
Repeat Register Read
In QPI Mode, Configuration Register 1 may be read via the Read Any Register command, see
Section 10.3.12, Read Any Register (RDAR 65h) on page 101
10.3.4
Write Registers (WRR 01h)
The Write Registers (WRR) command allows new values to be written to both the Status Register 1 and
Configuration Register 1. Before the Write Registers (WRR) command can be accepted by the device, a
Write Enable (WREN) command must be received. After the Write Enable (WREN) command has been
decoded successfully, the device will set the Write Enable Latch (WEL) in the Status Register to enable any
write operations.
The Write Registers (WRR) command is entered by shifting the instruction and the data bytes on SI. The
Status Register is one data byte in length.
The WRR operation first erases the register then programs the new value as a single operation. The Write
Registers (WRR) command will set the P_ERR or E_ERR bits if there is a failure in the WRR operation. See
Status Register 1 Volatile (SR1V) on page 61 for a description of the error bits. Any Status or Configuration
Register bit reserved for the future must be written as a 0.
CS# must be driven to the logic high state after the eighth or sixteenth bit of data has been latched. If not, the
Write Registers (WRR) command is not executed. If CS# is driven high after the eighth cycle then only the
Status Register 1 is written; otherwise, after the sixteenth cycle both the Status and Configuration Registers
are written.
As soon as CS# is driven to the logic high state, the self-timed Write Registers (WRR) operation is initiated.
While the Write Registers (WRR) operation is in progress, the Status Register may still be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed Write
Registers (WRR) operation, and is a 0 when it is completed. When the Write Registers (WRR) operation is
completed, the Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for the WRR command
is 133 MHz.
This command is also supported in QPI Mode. In QPI Mode the instruction and data is shifted in on IO0-IO3,
two clock cycles per byte.
Figure 10.10 Write Registers (WRR) Command Sequence – 8-Data Bits
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Input Status Register 1
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Figure 10.11 Write Registers (WRR) Command Sequence – 16-Data Bits
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Input Status Register 1
Input Configuration Register 1
Figure 10.12 Write Registers (WRR) Command Sequence – 16-Data Bits QPI Mode
CS#
SCLK
IO0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO1
IO2
IO3
Phase
Instruct.
Input Status
Input Config
The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1,
and BP0) bits in either the non-volatile Status Register 1 or in the volatile Status Register 1, to define the size
of the area that is to be treated as read-only. The BPNV_O bit (CR1NV[3]) controls whether WRR writes the
non-volatile or volatile version of Status Register 1. When CR1NV[3]=0 WRR writes SR1NV[4:2]. When
CR1NV[3]=1 WRR writes SR1V[4:2].
The Write Registers (WRR) command also allows the user to set the Status Register Write Disable (SRWD)
bit to a 1 or a 0. The Status Register Write Disable (SRWD) bit and Write Protect (WP#) signal allow the BP
bits to be hardware protected.
When the Status Register Write Disable (SRWD) bit of the Status Register is a 0 (its initial delivery state), it is
possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been
set by a Write Enable (WREN) command, regardless of the whether Write Protect (WP#) signal is driven to
the logic high or logic low state.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to a 1, two cases need to be
considered, depending on the state of Write Protect (WP#):
If Write Protect (WP#) signal is driven to the logic high state, it is possible to write to the Status and
Configuration Registers provided that the Write Enable Latch (WEL) bit has previously been set to a 1 by
initiating a Write Enable (WREN) command.
If Write Protect (WP#) signal is driven to the logic low state, it is not possible to write to the Status and
Configuration Registers even if the Write Enable Latch (WEL) bit has previously been set to a 1 by a Write
Enable (WREN) command. Attempts to write to the Status and Configuration Registers are rejected, not
accepted for execution, and no error indication is provided. As a consequence, all the data bytes in the
memory area that are protected by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also
hardware protected by WP#.
The WP# hardware protection can be provided:
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (WP#) signal to the logic
low state;
or by driving Write Protect (WP#) signal to the logic low state after setting the Status Register Write Disable
(SRWD) bit to a 1.
The only way to release the hardware protection is to pull the Write Protect (WP#) signal to the logic high
state. If WP# is permanently tied high, hardware protection of the BP bits can never be activated.
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Table 10.2 Block Protection Modes
Memory Content
SRWD
Bit
WP#
Mode
Write Protection of Registers
Protected Area
Unprotected Area
1
1
0
1
0
0
Status and Configuration Registers are Writable (if Protected against
WREN command has set the WEL bit). The values Page Program,
in the SRWD, BP2, BP1, and BP0 bits and those in Sector Erase, and
Ready to accept
Page Program, and
Sector Erase
Software
Protected
the Configuration Register can be changed.
Bulk Erase.
commands.
Status and Configuration Registers are Hardware Protected against
Ready to accept
Page Program or
Erase commands.
Hardware
Protected
Write Protected. The values in the SRWD, BP2, Page Program,
BP1, and BP0 bits and those in the Configuration Sector Erase, and
Register cannot be changed. Bulk Erase.
0
1
Notes:
1. The Status Register originally shows 00h when the device is first shipped from Spansion to the customer.
2. Hardware protection is disabled when Quad Mode is enabled (CR1V[1] = 1). WP# becomes IO2; therefore, it cannot be utilized.
10.3.5
Write Enable (WREN 06h)
The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit of the Status Register 1
(SR1V[1]) to a 0. The Write Enable Latch (WEL) bit must be set to a 1 by issuing the Write Enable (WREN)
command to enable write, program and erase commands.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on
SI. Without CS# being driven to the logic high state after the eighth bit of the instruction byte has been latched
in on SI, the write enable operation will not be executed.
Figure 10.13 Write Enable (WREN) Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
Phase
Instruction
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock
cycles per byte.
Figure 10.14 Write Enable (WREN) Command Sequence QPI Mode
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruction
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10.3.6
Write Disable (WRDI 04h)
The Write Disable (WRDI) command clears the Write Enable Latch (WEL) bit of the Status Register 1
(SR1V[1]) to a 1.
The Write Enable Latch (WEL) bit may be cleared to a 0 by issuing the Write Disable (WRDI) command to
disable Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Registers (WRR or WRAR), OTP
Program (OTPP), and other commands, that require WEL be set to 1 for execution. The WRDI command can
be used by the user to protect memory areas against inadvertent writes that can possibly corrupt the contents
of the memory. The WRDI command is ignored during an embedded operation while WIP bit =1.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on
SI. Without CS# being driven to the logic high state after the eighth bit of the instruction byte has been latched
in on SI, the write disable operation will not be executed.
Figure 10.15 Write Disable (WRDI) Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
Phase
Instruction
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock
cycles per byte.
Figure 10.16 Write Disable (WRDI) Command Sequence QPI Mode
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruction
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10.3.7
Clear Status Register (CLSR 30h or 82h)
The Clear Status Register command resets bit SR1V[5] (Erase Fail Flag) and bit SR1V[6] (Program Fail
Flag). It is not necessary to set the WEL bit before a Clear Status Register command is executed. The Clear
Status Register command will be accepted even when the device remains busy with WIP set to 1, as the
device does remain busy when either error bit is set. The WEL bit will be unchanged after this command is
executed.
The legacy Clear Status Register (CLSR 30h) instruction may be disabled and the 30h instruction value
instead used for a program / erase resume command - see Configuration Register 3 on page 69. The Clear
Status Register alternate instruction (CLSR 82h) is always available to clear the Status Register.
Figure 10.17 Clear Status Register (CLSR) Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
Phase
Instruction
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock
cycles per byte.
Figure 10.18 Clear Status Register (CLSR) Command Sequence QPI Mode
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruction
10.3.8
Program NVDLR (PNVDLR 43h)
Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded successfully, the device will set the Write Enable Latch (WEL) to enable the PNVDLR operation.
The PNVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic high state after the eighth bit of data has been latched. If not, the PNVDLR
command is not executed. As soon as CS# is driven to the logic high state, the self-timed PNVDLR operation
is initiated. While the PNVDLR operation is in progress, the Status Register may be read to check the value of
the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PNVDLR cycle,
and is a 0. when it is completed. The PNVDLR operation can report a program error in the P_ERR bit of the
Status Register. When the PNVDLR operation is completed, the Write Enable Latch (WEL) is set to a 0. The
maximum clock frequency for the PNVDLR command is 133 MHz.
Figure 10.19 Program NVDLR (PNVDLR) Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Input Data
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10.3.9
Write VDLR (WVDLR 4Ah)
Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded successfully, the device will set the Write Enable Latch (WEL) to enable WVDLR operation.
The WVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic high state after the eighth bit of data has been latched. If not, the WVDLR
command is not executed. As soon as CS# is driven to the logic high state, the WVDLR operation is initiated
with no delays. The maximum clock frequency for the PNVDLR command is 133 MHz.
Figure 10.20 Write VDLR (WVDLR) Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Input Data
10.3.10 Data Learning Pattern Read (DLPRD 41h)
The instruction is shifted on SI, then the 8-bit DLP is shifted out on SO. It is possible to read the DLP
continuously by providing multiples of eight clock cycles. The maximum operating clock frequency for the
DLPRD command is 133 MHz.
Figure 10.21 DLP Read (DLPRD) Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Register Read
Repeat Register Read
10.3.11 Enter 4-Byte Address Mode (4BAM B7h)
The enter 4-byte Address Mode (4BAM) command sets the volatile Address Length bit (CR2V[7]) to 1 to
change most 3-byte address commands to require 4 bytes of address. The Read SFDP (RSFDP) command
is the only 3-byte command that is not affected by the Address Length bit. RSFDP is required by the JEDEC
JESD216 standard to always have only 3 bytes of address.
A hardware or software reset is required to exit the 4-byte address mode.
Figure 10.22 Enter 4-Byte Address Mode (4BAM B7h) Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
Phase
Instruction
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10.3.12 Read Any Register (RDAR 65h)
The Read Any Register (RDAR) command provides a way to read all device registers - non-volatile and
volatile. The instruction is followed by a 3- or 4-byte address (depending on the address length configuration
CR2V[7], followed by a number of latency (dummy) cycles set by CR2V[3:0]. Then the selected register
contents are returned. If the read access is continued the same addressed register contents are returned until
the command is terminated - only one register is read by each RDAR command.
Reading undefined locations provides undefined data.
The RDAR command may be used during embedded operations to read Status Register 1 (SR1V).
The RDAR command is not used for reading registers that act as a window into a larger array: PPBAR, and
DYBAR. There are separate commands required to select and read the location in the array accessed.
The RDAR command will read invalid data from the PASS register locations if the ASP Password protection
mode is selected by programming ASPR[2] to 0.
Table 10.3 Register Address Map
Byte Address (Hex)
00000000
00000001
00000002
00000003
00000004
00000005
...
Register Name
SR1NV
N/A
Description
CR1NV
CR2NV
CR3NV
CR4NV
N/A
Non-Volatile Status and Configuration Registers
00000010
...
NVDLR
N/A
Non-Volatile Data Learning Register
Non-Volatile Password Register
Non-Volatile
00000020
00000021
00000022
00000023
00000024
00000025
00000026
00000027
...
PASS[7:0]
PASS[15:8]
PASS[23:16]
PASS[31:24]
PASS[39:32]
PASS[47:40]
PASS[55:48]
PASS[63:56]
N/A
00000030
00000031
...
ASPR[7:0]
ASPR[15:8]
N/A
00800000
00800001
00800002
00800003
00800004
00800005
...
SR1V
SR2V
CR1V
Volatile Status and Configuration Registers
CR2V
CR3V
CR4V
N/A
00800010
...
VDLR
Volatile Data Learning Register
Volatile PPB Lock Register
N/A
00800040
...
PPBL
N/A
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Figure 10.23 Read Any Register Read Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
7
6
5
4
3
2
1
0
Phase
Instruction
Address
Dummy Cycles
Data1
Note:
1. A = MSB of address = 23 for Address length CR2V[7] = 0, or 31 for CR2V[7]=1
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock
cycles per byte.
Figure 10.24 Read Any Register, QPI Mode, CR2[7] = 0, Command Sequence
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
20
21
22
23
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruct.
Address
Dummy
D1
D2
D3
D4
Figure 10.25 Read Any Register, QPI Mode, CR2[7] = 1 Command Sequence
CS#
SCLK
IO0
4
5
6
7
0
1
2
3
28
29
30
31
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO1
IO2
IO3
Phase
Instruct.
Address
Dummy
D1
D2
D3
D4
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10.3.13 Write Any Register (WRAR 71h)
The Write Any Register (WRAR) command provides a way to write any device register - non-volatile or
volatile. The instruction is followed by a 3- or 4-byte address (depending on the address length configuration
CR2V[7], followed by one byte of data to write in the address selected register.
Before the WRAR command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable
any write operations. The WIP bit in SR1V may be checked to determine when the operation is completed.
The P_ERR and E_ERR bits in SR1V may be checked to determine if any error occurred during the
operation.
Some registers have a mixture of bit types and individual rules controlling which bits may be modified. Some
bits are read only, some are OTP.
Read only bits are never modified and the related bits in the WRAR command data byte are ignored without
setting a program or erase error indication (P_ERR or E_ERR in SR1V). Hence, the value of these bits in the
WRAR data byte do not matter.
OTP bits may only be programmed to the level opposite of their default state. Writing of OTP bits back to their
default state is ignored and no error is set.
Non-Volatile bits which are changed by the WRAR data, require non-volatile register write time (tW) to be
updated. The update process involves an erase and a program operation on the non-volatile register bits. If
either the erase or program portion of the update fails the related error bit and WIP in SR1V will be set to 1.
Volatile bits which are changed by the WRAR data, require the volatile register write time (tCS) to be updated.
Status Register 1 may be repeatedly read (polled) to monitor the Write-In-Progress (WIP) bit (SR1V[0]) and
the error bits (SR1V[6,5]) to determine when the register write is completed or failed. If there is a write failure,
the clear status command is used to clear the error status and enable the device to return to standby state.
However, the PPBL register can not be written by the WRAR command. Only the PPB Lock Bit Write
(PLBWR) command can write the PPBL register.
The command sequence and behavior is the same as the PP or 4PP command with only a single byte of data
provided. See Section 10.5.2, Page Program (PP 02h or 4PP 12h) on page 114.
The address map of the registers is the same as shown for Section 10.3.12, Read Any Register (RDAR 65h)
on page 101.
10.3.14 Set Burst Length (SBL C0h)
The Set Burst Length (SBL) command is used to configure the Burst Wrap feature. Burst Wrap is used in
conjunction with Quad I/O Read and DDR Quad I/O Read, in legacy SPI or QPI Mode, to access a fixed
length and alignment of data. Certain applications can benefit from this feature by improving the overall
system code execution performance. The Burst Wrap feature allows applications that use cache, to start
filling a cache line with instruction or data from a critical address first, then fill the remainder of the cache line
afterwards within a fixed length (8/16/32/64-bytes) of data, without issuing multiple read commands.
The Set Burst Length (SBL) command writes the CR4V register to enable or disable the wrapped read feature
and set the wrap boundary. When enabled the wrapped read feature changes the related read commands
from sequentially reading until the command ends, to reading sequentially wrapped within a group of bytes.
When CR4V[4]=1, the wrap mode is not enabled and unlimited length sequential read is performed.
When CR4V[4]=0, the wrap mode is enabled and a fixed length and aligned group of 8, 16, 32, or 64 bytes is
read starting at the byte address provided by the read command and wrapping around at the group alignment
boundary.
The group of bytes is of length and aligned on an 8-, 16-, 32-, or 64-byte boundary. CR4V[1:0] selects the
boundary. See Configuration Register 4 Volatile (CR4V) on page 72.
The starting address of the read command selects the group of bytes and the first data returned is the
addressed byte. Bytes are then read sequentially until the end of the group boundary is reached. If the read
continues the address wraps to the beginning of the group and continues to read sequentially. This wrapped
read sequence continues until the command is ended by CS# returning high.
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Table 10.4 Example Burst Wrap Sequences
Wrap
Boundary
(Bytes)
CR4V[4,1:0]
Value (Hex)
Start Address
Address Sequence (Hex)
(Hex)
1X
00
00
01
01
Sequential
XXXXXX03
XXXXXX00
XXXXXX07
XXXXXX02
XXXXXX0C
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, ...
00, 01, 02, 03, 04, 05, 06, 07, 00, 01, 02, ...
8
8
07, 00, 01, 02, 03, 04, 05, 06, 07, 00, 01, ...
16
16
02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, ...
0C, 0D, 0E, 0F, 00, 01, 02, 03, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, ...
0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00,
01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, ...
02
02
32
32
XXXXXX0A
XXXXXX1E
1E, 1F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, ...
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A,
1B, 1C, 1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, 30, 31,
32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 00, 01, 02 ...
03
03
64
64
XXXXXX03
XXXXXX2E
2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 00, 01, 02, 03, 04, 05,
06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C,
1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, ...
The Power-On Reset, hardware reset, or software reset default burst length can be changed by programming
CR4NV with the desired value using the WRAR command.
Figure 10.26 Set Burst Length Command Sequence
CS#
SCLK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Input Data
10.4 Read Memory Array Commands
Read commands for the main flash array provide many options for prior generation SPI compatibility or
enhanced performance SPI:
Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate
commands (SDR).
Some SDR commands transfer address one bit per rising edge of SCK and return data 1bit of data per
rising edge of SCK. These are called Single width commands.
Some SDR commands transfer both address and data two or four bits per rising edge of SCK. These are
called Dual I/O for two bits, Quad I/O, and QPI for four bits. QPI also transfers instruction four bits per rising
edge.
Some commands transfer address and data on both the rising edge and falling edge of SCK. These are
called Double Data Rate (DDR) commands.
There are DDR commands for 4 bits of address or data per SCK edge. These are called Quad I/O DDR
and QPI DDR for four bit per edge transfer.
All of these commands, except QPI Read, begin with an instruction code that is transferred one bit per SCK
rising edge. QPI Read transfers the instruction four bits per SCK rising edge.The instruction is followed by
either a 3- or 4-byte address transferred at SDR or DDR. Commands transferring address or data 2 or 4 bits
per clock edge are called Multiple I/O (MIO) commands. For S25FS-S family devices at 256-Mbits or higher
density, the traditional SPI 3-byte addresses are unable to directly address all locations in the memory array.
Separate 4-byte address read commands are provided for access to the entire address space. These devices
may be configured to take a 4-byte address from the host system with the traditional 3-byte address
commands. The 4-byte address mode for traditional commands is activated by setting the Address Length bit
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in Configuration Register 2 to 0. In the FS128S, higher order address bits above A23 in the 4 byte address
commands, or commands using 4-byte address mode are not relevant and are ignored because the flash
array is only 128 Mbits in size.
The Quad I/O and QPI commands provide a performance improvement option controlled by mode bits that
are sent following the address bits. The mode bits indicate whether the command following the end of the
current read will be another read of the same type, without an instruction at the beginning of the read. These
mode bits give the option to eliminate the instruction cycles when doing a series of Quad Read accesses.
Some commands require delay cycles following the address or mode bits to allow time to access the memory
array - read latency. The delay or read latency cycles are traditionally called dummy cycles. The dummy
cycles are ignored by the memory thus any data provided by the host during these cycles is “don’t care” and
the host may also leave the SI signal at high impedance during the dummy cycles. When MIO commands are
used the host must stop driving the IO signals (outputs are high impedance) before the end of last dummy
cycle. When DDR commands are used the host must not drive the I/O signals during any dummy cycle. The
number of dummy cycles varies with the SCK frequency or performance option selected via the Configuration
Register 2 (CR2V[3:0]) Latency Code. Dummy cycles are measured from SCK falling edge to next SCK
falling edge. SPI outputs are traditionally driven to a new value on the falling edge of each SCK. Zero dummy
cycles means the returning data is driven by the memory on the same falling edge of SCK that the host stops
driving address or mode bits.
The DDR commands may optionally have an 8-edge Data Learning Pattern (DLP) driven by the memory, on
all data outputs, in the dummy cycles immediately before the start of data. The DLP can help the host
memory controller determine the phase shift from SCK to data edges so that the memory controller can
capture data at the center of the data eye.
When using SDR I/O commands at higher SCK frequencies (>50 MHz), an LC that provides one or more
dummy cycles should be selected to allow additional time for the host to stop driving before the memory starts
driving data, to minimize I/O driver conflict. When using DDR I/O commands with the DLP enabled, an LC
that provides five or more dummy cycles should be selected to allow one cycle of additional time for the host
to stop driving before the memory starts driving the 4-cycle DLP.
Each read command ends when CS# is returned High at any point during data return. CS# must not be
returned High during the mode or dummy cycles before data returns as this may cause mode bits to be
captured incorrectly; making it indeterminate as to whether the device remains in Continuous Read mode.
10.4.1
Read (Read 03h or 4READ 13h)
The instruction
03h (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or
03h (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or
13h is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, are shifted out on SO. The maximum operating clock
frequency for the Read command is 50 MHz.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
Figure 10.27 Read Command Sequence (3-Byte Address, 03h or 13h)
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
A
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Address
Data1
DataN
Note:
1. A = MSB of address = 23 for CR2V[7]=0, or 31 for CR2V[7]=1 or command 13h.
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10.4.2
Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch)
The instruction
0Bh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or
0Bh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or
0Ch is followed by a 4-byte address (A31-A0)
The address is followed by dummy cycles depending on the latency code set in the Configuration Register
CR2V[3:0]. The dummy cycles allow the device internal circuits additional time for accessing the initial
address location. During the dummy cycles the data value on SO is “don’t care” and may be high impedance.
Then the memory contents, at the address given, are shifted out on SO.
The maximum operating clock frequency for Fast Read command is 133 MHz.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
Figure 10.28 Fast Read (FAST_READ) Command Sequence (3-Byte Address, 0Bh [CR2V[7]=0)
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
A
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Address
Dummy Cycles
Data1
Note:
1. A = MSB of address = 23 for CR2V[7]=0, or 31 for CR2V[7]=1 or command 0Ch.
10.4.3
Dual I/O Read (DIOR BBh or 4DIOR BCh)
The instruction
BBh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or
BBh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or
BCh is followed by a 4-byte address (A31-A0)
The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). This
command takes input of the address and returns read data two bits per SCK rising edge. In some
applications, the reduced address input and data output time might allow for code execution in place (XIP) i.e.
directly from the memory device.
The maximum operating clock frequency for Dual I/O Read is 133 MHz.
The Dual I/O Read command has Continuous Read mode bits that follow the address so, a series of Dual I/O
Read commands may eliminate the 8-bit instruction after the first Dual I/O Read command sends a mode bit
pattern of Axh that indicates the following command will also be a Dual I/O Read command. The first Dual I/O
Read command in a series starts with the 8-bit instruction, followed by address, followed by four cycles of
mode bits, followed by an optional latency period. If the mode bit pattern is Axh the next command is
assumed to be an additional Dual I/O Read command that does not provide instruction bits. That command
starts with address, followed by mode bits, followed by optional latency.
Variable latency may be added after the mode bits are shifted into SI and SO before data begins shifting out
of IO0 and IO1. This latency period (dummy cycles) allows the device internal circuitry enough time to access
data at the initial address. During the dummy cycles, the data value on SI and SO are “don’t care” and may be
high impedance. The number of dummy cycles is determined by the frequency of SCK. The latency is
configured in CR2V[3:0].
The Continuous Read feature removes the need for the instruction bits in a sequence of read accesses and
greatly improves code execution (XIP) performance. The upper nibble (bits 7-4) of the Mode bits control the
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length of the next Dual I/O Read command through the inclusion or exclusion of the first byte instruction code.
The lower nibble (bits 3-0) of the Mode bits are “don’t care” (“x”) and may be high impedance. If the Mode bits
equal Axh, then the device remains in Dual I/O Continuous Read mode and the next address can be entered
(after CS# is raised high and then asserted low) without the BBh or BCh instruction, as shown in Figure 10.31
on page 108; thus, eliminating eight cycles of the command sequence. The following sequences will release
the device from Dual I/O Continuous Read mode; after which, the device can accept standard SPI
commands:
1. During the Dual I/O Continuous Read command sequence, if the Mode bits are any value other
than Axh, then the next time CS# is raised high the device will be released from Dual I/O con ti no
us read mode.
2. Send the Mode Reset command.
Note that the four mode bit cycles are part of the device’s internal circuitry latency time to access the initial
address after the last address cycle that is clocked into IO0 (SI) and IO1 (SO).
It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out
clock. At higher clock speeds the time available to turn off the host outputs before the memory device begins
to drive (bus turn around) is diminished. It is allowed and may be helpful in preventing I/O signal contention,
for the host system to turn off the I/O signal outputs (make them high impedance) during the last two “don’t
care” mode cycles or during any dummy cycles.
Following the latency period the memory content, at the address given, is shifted out two bits at a time
through IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK
signal.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
Figure 10.29 Dual I/O Read Command Sequence (3-Byte Address, BBh [CR2V[7]=0])
CS#
SCK
IO0
IO1
7
6
5
4
3
2
1
0
22
23
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
Phase
Instruction
Address
Mode
Dum
Data1
Data2
Note:
1. Least significant 4 bits of Mode are don’t care and it is optional for the host to drive these bits. The host may turn off drive during these
cycles to increase bus turn around time between Mode bits from host and returning data from the memory.
Figure 10.30 Dual I/O Read Command Sequence (4-Byte Address, BBh [CR2V[7]=1])
CS#
SCK
IO0
IO1
7
6
5
4
3
2
1
0
30
31
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
Phase
Instruction
Address
Mode
Dum
Data1
Data2
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Figure 10.31 Dual I/O Continuous Read Command Sequence (4-Byte Address [CR2V[7]=1])
CS#
SCK
IO0
6
7
4
5
2
3
0
1
30
31
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
IO1
Phase
DataN
Address
Mode
Dum
Data1
Data2
10.4.4
Quad I/O Read (QIOR EBh or 4QIOR ECh)
The instruction
EBh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or
EBh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or
ECh is followed by a 4-byte address (A31-A0)
The Quad I/O Read command improves throughput with four I/O signals — IO0-IO3. It allows input of the
address bits four bits per serial SCK clock. In some applications, the reduced instruction overhead might
allow for code execution (XIP) directly from S25FS-S family devices. The Quad bit of the Configuration
Register must be set (CR1V[1]=1) to enable the Quad capability of S25FS-S family devices.
The maximum operating clock frequency for Quad I/O Read is 133MHz.
For the Quad I/O Read command, there is a latency required after the mode bits (described below) before
data begins shifting out of IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal
circuitry enough time to access data at the initial address. During latency cycles, the data value on IO0-IO3
are “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of
SCK. The latency is configured in CR2V[3:0].
Following the latency period, the memory contents at the address given, is shifted out four bits at a time
through IO0-IO3. Each nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK
signal.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled
through the setting of the Mode bits (after the address sequence, as shown in Figure 10.32 on page 109 or
Figure 10.35 on page 110). This added feature removes the need for the instruction sequence and greatly
improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next
Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits
3-0) of the Mode bits are “don’t care” (“x”). If the Mode bits equal Axh, then the device remains in Quad I/O
High Performance Read mode and the next address can be entered (after CS# is raised high and then
asserted low) without requiring the EBh or ECh instruction, as shown in Figure 10.34 on page 109 or
Figure 10.36 on page 110; thus, eliminating eight cycles for the command sequence. The following
sequences will release the device from Quad I/O High Performance Read mode; after which, the device can
accept standard SPI commands:
1. During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh,
then the next time CS# is raised high the device will be released from Quad I/O High Performance
Read mode.
2. Send the Mode Reset command.
Note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the device’s
internal circuitry latency time to access the initial address after the last address cycle that is clocked into IO0-
IO3.
It is important that the IO0-IO3 signals be set to high-impedance at or before the falling edge of the first data
out clock. At higher clock speeds the time available to turn off the host outputs before the memory device
begins to drive (bus turn around) is diminished. It is allowed and may be helpful in preventing IO0-IO3 signal
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contention, for the host system to turn off the IO0-IO3 signal outputs (make them high impedance) during the
last “don’t care” mode cycle or during any dummy cycles.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
In QPI Mode (CR2V[6]=1) the Quad I/O instructions are sent 4 bits per SCK rising edge. The remainder of the
command protocol is identical to the Quad I/O commands.
Figure 10.32 Quad I/O Read Command Sequence (3-Byte Address, EBh [CR2V[7]=0])
CS#
SCLK
IO0
IO1
7
6
5
4
3
2
1
0
20
21
22
23
4
5
6
7
0
1
2
3
4
5
6
7
0
1
0
1
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruction
Address Mode
Dummy
D1
D2
D3
D4
Figure 10.33 Quad I/O Read Command Sequence (3-Byte Address, EBh [CR2V[7]=0]) QPI Mode
CS#
SCLK
IO0
4
5
6
7
0
1
2
3
20
21
22
23
4
5
6
7
0
1
2
3
4
5
6
7
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO1
IO2
0
1
IO3
Phase
Instruct.
Address
Mode
Dummy
D1
D2
D3
D4
Figure 10.34 Continuous Quad I/O Read Command Sequence (3-Byte Address)
CS#
SCK
IO0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
20
21
22
23
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
1
1
6
7
7
7
4
5
5
5
2
3
3
3
0
1
1
1
IO1
IO2
IO3
Phase
DN-1
DN
Address
Mode
Dummy
D1
D2
D3
D4
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Figure 10.35 Quad I/O Read Command Sequence (4-Byte Address, ECh or EBh [CR2V[7]=1])
CS#
SCK
IO0
7
6
5
4
3
2
1
0
28
29
30
31
4
5
6
7
0
1
2
3
4
5
6
7
0
1
0
1
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO1
IO2
IO3
Phase
Instruction
Address Mode
Dummy
D1
D2
D3
D4
Figure 10.36 Continuous Quad I/O Read Command Sequence (4-Byte Address)
CS#
SCK
IO0
4
5
6
7
0
4
5
6
7
0
1
2
3
28
29
30
31
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
1
1
6
7
7
7
4
5
5
5
2
3
3
3
0
1
1
1
IO1
1
2
3
IO2
IO3
Phase
Note:
DN-1
DN
Address
Mode
Dummy
D1
D2
D3
D4
1. The same sequence is used in QPI Mode
Figure 10.37 Quad I/O Read Command Sequence
(4-Byte Address, ECh or EBh [CR2V[7]=1]) QPI Mode
CS#
SCLK
IO0
4
5
6
7
0
1
2
3
28
29
30
31
4
5
6
7
0
1
2
3
4
5
6
7
4
5
6
7
0
1
2
3
4
5
6
7
0
4
5
6
7
0
1
2
3
4
0
IO1
1
2
3
5
6
7
1
2
3
IO2
IO3
Phase
Instruct.
Address
Mode
Dummy
D1
D2
D3
D4
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10.4.5
DDR Quad I/O Read (EDh, EEh)
The DDR Quad I/O Read command improves throughput with four I/O signals - IO0-IO3. It is similar to the
Quad I/O Read command but allows input of the address four bits on every edge of the clock. In some
applications, the reduced instruction overhead might allow for code execution (XIP) directly from S25FS-S
family devices. The Quad bit of the Configuration Register must be set (CR1V[1]=1) to enable the Quad
capability.
The instruction
EDh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or
EDh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or
EEh is followed by a 4-byte address (A31-A0)
The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a
DDR fashion, with four bits at a time on each clock edge through IO0-IO3.
The maximum operating clock frequency for DDR Quad I/O Read command is 80 MHz.
For DDR Quad I/O Read, there is a latency required after the last address and mode bits are shifted into the
IO0-IO3 signals before data begins shifting out of IO0-IO3. This latency period (dummy cycles) allows the
device’s internal circuitry enough time to access the initial address. During these latency cycles, the data
value on IO0-IO3 are “don’t care” and may be high impedance. When the Data Learning Pattern (DLP) is
enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must be left
high impedance by the host so that the memory device can drive the DLP during the dummy cycles.
The number of dummy cycles is determined by the frequency of SCK. The latency is configured in CR2V[3:0].
Mode bits allow a series of Quad I/O DDR commands to eliminate the 8-bit instruction after the first command
sends a complementary mode bit pattern, as shown in Figure 10.38 and Figure 10.40. This feature removes
the need for the 8-bit SDR instruction sequence and dramatically reduces initial access times (improves XIP
performance). The Mode bits control the length of the next DDR Quad I/O Read operation through the
inclusion or exclusion of the first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0])
of the Mode bits are complementary (i.e. 5h and Ah) the device transitions to Continuous DDR Quad I/O
Read mode and the next address can be entered (after CS# is raised high and then asserted low) without
requiring the EDh or EEh instruction, as shown in Figure 10.39 on page 112 and Figure 10.42 on page 113
thus, eliminating eight cycles from the command sequence. The following sequences will release the device
from Continuous DDR Quad I/O Read mode; after which, the device can accept standard SPI commands:
1. During the DDR Quad I/O Read Command Sequence, if the Mode bits are not complementary the
next time CS# is raised high and then asserted low the device will be released from DDR Quad I/O
Read mode.
2. Send the Mode Reset command.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
Note that the memory devices may drive the IOs with a preamble prior to the first data value. The preamble is
a Data Learning Pattern (DLP) that is used by the host controller to optimize data capture at higher
frequencies. The preamble drives the IO bus for the four clock cycles immediately before data is output. The
host must be sure to stop driving the IO bus prior to the time that the memory starts outputting the preamble.
The preamble is intended to give the host controller an indication about the round trip time from when the host
drives a clock edge to when the corresponding data value returns from the memory device. The host
controller will skew the data capture point during the preamble period to optimize timing margins and then use
the same skew time to capture the data during the rest of the read operation. The optimized capture point will
be determined during the preamble period of every read operation. This optimization strategy is intended to
compensate for both the PVT (process, voltage, temperature) of both the memory device and the host
controller as well as any system level delays caused by flight time on the PCB.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP
of 34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four SIOs). This
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pattern was chosen to cover both “DC” and “AC” data transition scenarios. The two DC transition scenarios
include data low for a long period of time (two half clocks) followed by a high going transition (001) and the
complementary low going transition (110). The two AC transition scenarios include data low for a short period
of time (one half clock) followed by a high going transition (101) and the complementary low going transition
(010). The DC transitions will typically occur with a starting point closer to the supply rail than the AC
transitions that may not have fully settled to their steady state (DC) levels. In many cases the DC transitions
will bound the beginning of the data valid period and the AC transitions will bound the ending of the data valid
period. These transitions will allow the host controller to identify the beginning and ending of the valid data
eye. Once the data eye has been characterized the optimal data capture point can be chosen. See SPI DDR
Data Learning Registers on page 75 for more details.
In QPI Mode (CR2V[6]=1) the DDR Quad I/O instructions are sent 4 bits per SCK rising edge. The remainder
of the command protocol is identical to the DDR Quad I/O commands.
Figure 10.38 DDR Quad I/O Read Initial Access (3-Byte Address, EDh [CR2V[7]=0)
CS#
SCK
IO0
IO1
7
6
5
4
3
2
1
0
20 16 12 8
21 17 13 9
22 18 14 10
23 19 15 11
Address
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruction
Mode
Dummy
DLP
D1 D2
Figure 10.39 Continuous DDR Quad I/O Read Subsequent Access (3-Byte Address)
CS#
SCK
IO0
20 16 12
21 17 13
8
9
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO1
IO2
22 18 14 10
23 19 15 11
Address
IO3
Phase
Mode
Dummy
D1
D2
D3
D4
D5
Figure 10.40 DDR Quad I/O Read Initial Access (4-Byte Address, EEh or EDh [CR2V[7]=1])
CS#
SCK
IO0
7
6
5
4
3
2
1
0
28 24 20 16 12 8
29 25 21 17 13 9
4
5
0
1
2
3
4
5
6
7
0
1
2
3
6
6
6
6
5 4
5 4
5 4
5 4
3
3
2
2
2
2
1 0
1 0
1 0
1 0
4
5
6
7
0
4
5
6
7
0
1
2
3
IO1
1
2
3
IO2
30 26 22 18 14 10 6
31 27 23 19 15 11 7
Address
3
IO3
3
Phase
Note:
Instruction
Mode
Dummy
DLP
D1 D2
1. Example DLP of 34h (or 00110100).
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Figure 10.41 DDR Quad I/O Read Initial Access
(4-Byte Address, EEh or EDh [CR2V[7]=1]) QPI Mode
CS#
SCLK
IO0
4
5
6
7
0
1
2
3
28 24 20 16 12
29 25 21 17 13
8
9
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO1
IO2
30 26 22 18 14 10
31 27 23 19 15 11
Address
IO3
Phase
Instruct.
Mode
Dummy
DLP
D1
D2
Note:
1. Example DLP of 34h (or 00110100).
Figure 10.42 Continuous DDR Quad I/O Read Subsequent Access (4-Byte Address)
CS#
SCK
IO0
28 24 20 16 12
29 25 21 17 13
8
9
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
6
6
6
6
5 4
5 4
5 4
5 4
3
3
3
3
2
2
2
2
1 0
1 0
1 0
1 0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO1
IO2
30 26 22 18 14 10
31 27 23 19 15 11
Address
IO3
Phase
Note:
Mode
Dummy
DLP
D1
D2
1. Example DLP of 34h (or 00110100).
10.5 Program Flash Array Commands
10.5.1 Program Granularity
10.5.1.1 Page Programming
Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming
command to move data from the buffer to the memory array. This sets an upper limit on the amount of data
that can be programmed with a single programming command. Page Programming allows up to a page size
(either 256 or 512 bytes) to be programmed in one operation. The page size is determined by the
Configuration Register bit CR3V[4]. The page is aligned on the page size address boundary. It is possible to
program from one bit up to a page size in each Page programming operation. It is recommended that a
multiple of 16-byte length and aligned Program Blocks be written. For the very best performance,
programming should be done in full pages of 512 bytes aligned on 512-byte boundaries with each Page being
programmed only once.
10.5.1.2 Single Byte Programming
Single Byte Programming allows full backward compatibility to the legacy standard SPI Page Programming
(PP) command by allowing a single byte to be programmed anywhere in the memory array.
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10.5.2
Page Program (PP 02h or 4PP 12h)
The Page Program (PP) command allows bytes to be programmed in the memory (changing bits from 1 to 0).
Before the Page Program (PP) commands can be accepted by the device, a Write Enable (WREN) command
must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded
successfully, the device sets the Write Enable Latch (WEL) in the Status Register to enable any write
operations.
The instruction
02h (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or
02h (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or
12h is followed by a 4-byte address (A31-A0)
and at least one data byte on SI. Depending on CR3V[4], the page size can either be 256 or 512 bytes. Up to
a page can be provided on SI after the 3-byte address with instruction 02h or 4-byte address with instruction
12h has been provided.
If more data is sent to the device than the space between the starting address and the page aligned end
boundary, the data loading sequence will wrap from the last byte in the page to the zero byte location of the
same page and begin overwriting any data previously loaded in the page. The last page worth of data is
programmed in the page. This is a result of the device being equipped with a page program buffer that is only
page size in length. If less than a page of data is sent to the device, these data bytes will be programmed in
sequence, starting at the provided address within the page, without having any affect on the other bytes of the
same page.
Using the Page Program (PP) command to load an entire page, within the page boundary, will save overall
programming time versus loading less than a page into the program buffer.
The programming process is managed by the flash memory device internal control logic. After a programming
command is issued, the programming operation status can be checked using the Read Status Register 1
command. The WIP bit (SR1V[0]) will indicate when the programming operation is completed. The P_ERR bit
(SR1V[6]) will indicate if an error occurs in the programming operation that prevents successful completion of
programming. This includes attempted programming of a protected area.
Figure 10.43 Page Program (PP 02h or 4PP 12h) Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
A
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Address
Input Data1
Input Data2
Note:
1. A = MSB of address = A23 for PP 02h, or A31 for 4PP 12h.
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock
cycles per byte.
Figure 10.44 Page Program (PP 02h or 4PP 12h) QPI Mode Command Sequence
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
A-3
A-2
A-1
A
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
5
IO2
6
7
IO3
Phase
Instruct.
Address
Input D1
Input D2
Input D3
Input D4
Note:
1. A = MSB of address = A23 for PP 02h, or A31 for 4PP 12h.
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10.6 Erase Flash Array Commands
10.6.1
Parameter 4-kB Sector Erase (P4E 20h or 4P4E 21h)
The main flash array address map may be configured to overlay 4-kB parameter sectors over the lowest
address portion of the lowest address uniform sector (bottom parameter sectors) or over the highest address
portion of the highest address uniform sector (top parameter sectors). The main flash array address map may
also be configured to have only uniform size sectors. The parameter sector configuration is controlled by the
configuration bit CR3V[3]. The P4E and 4P4E commands are ignored when the device is configured for
uniform sectors only (CR3V[3]=1).
The parameter 4-kB Sector Erase commands set all the bits of a 4-kB parameter sector to 1 (all bytes are
FFh). Before the P4E or 4P4E command can be accepted by the device, a Write Enable (WREN) command
must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register
to enable any write operations.
The instruction
20h [CR2V[7]=0] is followed by a 3-byte address (A23-A0), or
20h [CR2V[7]=1] is followed by a 4-byte address (A31-A0), or
21h is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of the address has
been latched in on SI. This will initiate the beginning of internal erase cycle, which involves the pre-
programming and erase of the chosen sector of the flash memory array. If CS# is not driven high after the last
bit of address, the Sector Erase operation will not be executed.
As soon as CS# is driven high, the internal erase cycle will be initiated. With the internal erase cycle in
progress, the user can read the value of the Write-In Progress (WIP) bit to determine when the operation has
been completed. The WIP bit will indicate a 1. when the erase cycle is in progress and a 0 when the erase
cycle has been completed.
A P4E or 4P4E command applied to a sector that has been write protected through the Block Protection bits
or ASP, will not be executed and will set the E_ERR status. A P4E command applied to a sector that is larger
than 4 kbytes will not be executed and will not set the E_ERR status.
Figure 10.45 Parameter Sector Erase (P4E 20h or 4P4E 21h) Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
A
1
0
Phase
Instruction
Address
Note:
1. A = MSB of address = A23 for P4E 20h with CR2V[7]=0, or A31 for P4E 20h with CR2V[7]=1 or 4P4E 21h.
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock
cycles per byte.
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Figure 10.46 Parameter Sector Erase (P4E 20h or 4P4E 21h) QPI Mode Command Sequence
CS#
SCLK
IO0
4
5
6
7
0
1
2
3
A-3
A-2
A-1
A
4
0
1
2
3
IO1
5
IO2
6
7
IO3
Phase
Instructtion
Address
Note:
1. A = MSB of address = A23 for P4E 20h with CR2V[7]=0, or A31 for P4E 20h with CR2V[7]=1 or 4P4E 21h.
10.6.2
Sector Erase (SE D8h or 4SE DCh)
The Sector Erase (SE) command sets all bits in the addressed sector to 1 (all bytes are FFh). Before the
Sector Erase (SE) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable
any write operations.
The instruction
D8h [CR2V[7]=0] is followed by a 3-byte address (A23-A0), or
D8h [CR2V[7]=1] is followed by a 4-byte address (A31-A0), or
DCh is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of address has been
latched in on SI. This will initiate the erase cycle, which involves the pre-programming and erase of the
chosen sector. If CS# is not driven high after the last bit of address, the Sector Erase operation will not be
executed.
As soon as CS# is driven into the logic high state, the internal erase cycle will be initiated. With the internal
erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if the
operation has been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a 0 when
the erase cycle has been completed.
A Sector Erase (SE) command applied to a sector that has been Write Protected through the Block Protection
bits or ASP, will not be executed and will set the E_ERR status.
A device configuration option (CR3V[1]) determines whether the SE command erases 64 kbytes or
256 kbytes. The option to use this command to always erase 256 kbytes provides for software compatibility
with higher density and future S25FS family devices.
A device configuration option (CR3V[3]) determines whether 4-kB parameter sectors are in use. When
CR3V[3] = 0, 4-kB parameter sectors overlay a portion of the highest or lowest address 32 kB of the device
address space. If a Sector Erase command is applied to a 64-kB sector that is overlaid by 4-kB sectors, the
overlaid 4-kB sectors are not affected by the erase. Only the visible (non-overlaid) portion of the 64-kB sector
appears erased. Similarly if a Sector Erase command is applied to a 256-kB range that is overlaid by 4-kB
sectors, the overlaid 4-kB sectors are not affected by the erase. When CR3V[3] = 1, there are no 4-kB
parameter sectors in the device address space and the Sector Erase command always operates on fully
visible 64-kB or 256-kB sectors.
ASP has a PPB and a DYB protection bit for each physical sector, including any 4-kB sectors. If a Sector
Erase command is applied to a 256-kB range that includes a 64-kB protected physical sector, the erase will
not be executed on the 256-kB range and will set the E_ERR status.
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Figure 10.47 Sector Erase (SE D8h or 4SE DCh) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
Phase
Instruction
Address
Note:
1. A = MSB of address = A23 for SE D8h with CR2V[7]=0, or A31 for SE D8h with CR2V[7]=1 or 4P4E DCh.
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock
cycles per byte.
Figure 10.48 Sector Erase (SE D8h or 4SE DCh) QPI Mode Command Sequence
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
A-3
A-2
A-1
A
4
0
1
2
3
5
IO2
6
7
IO3
Phase
Instructtion
Address
Note:
1. A = MSB of address = A23 for P4E 20h with CR2V[7]=0, or A31 for P4E 20h with CR2V[7]=1 or 4P4E 21h.
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10.6.3
Bulk Erase (BE 60h or C7h)
The Bulk Erase (BE) command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array.
Before the BE command can be accepted by the device, a Write Enable (WREN) command must be issued
and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any
write operations.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on
SI. This will initiate the erase cycle, which involves the pre-programming and erase of the entire flash memory
array. If CS# is not driven high after the last bit of instruction, the BE operation will not be executed.
As soon as CS# is driven into the logic high state, the erase cycle will be initiated. With the erase cycle in
progress, the user can read the value of the Write-In Progress (WIP) bit to determine when the operation has
been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase
cycle has been completed.
A BE command can be executed only when the Block Protection (BP2, BP1, BP0) bits are set to 0s. If the BP
bits are not 0, the BE command is not executed and E_ERR is not set. The BE command will skip any sectors
protected by the DYB or PPB and the E_ERR status will not be set.
Figure 10.49 Bulk Erase Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
Phase
Instruction
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock
cycles per byte.
Figure 10.50 Bulk Erase Command Sequence QPI Mode
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruction
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10.6.4
Evaluate Erase Status (EES D0h)
The Evaluate Erase Status (EES) command verifies that the last erase operation on the addressed sector
was completed successfully. If the selected sector was successfully erased the Erase Status bit (SR2V[2]) is
set to 1. If the selected sector was not completely erased SR2V[2] is 0.
The EES command can be used to detect erase operations failed due to loss of power, reset, or failure during
the erase operation.
The EES instruction is followed by a 3- or 4-byte address, depending on the address length configuration
(CR2V[7]). The EES command requires tEES to complete and update the Erase Status in SR2V. The WIP bit
(SR1V[0]) may be read using the RDSR1 (05h) command, to determine when the EES command is finished.
Then the RDSR2 (07h) or the RDAR (65h) command can be used to read SR2V[2]. If a sector is found not
erased with SR2V[2]=0, the sector must be erased again to ensure reliable storage of data in the sector.
The Write Enable command (to set the WEL bit) is not required before the EES command. However, the WEL
bit is set by the device itself and cleared at the end of the operation, as visible in SR1V[1] when reading
status.
Figure 10.51 EES Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
A
1
0
Phase
Instruction
Address
Note:
1. A = MSB of address = A23 for CR2V[7]=0, or A31 for CR2V[7]=1.
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock
cycles per byte.
Figure 10.52 EES QPI Mode Command Sequence
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
A-3
A-2
A-1
A
4
0
1
2
3
5
IO2
6
7
IO3
Phase
Note:
Instructtion
Address
1. A = MSB of address = A23 for CR2V[7]=0, or A31 for CR2V[7]=1.
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10.6.5
Program or Erase Suspend (PES 85h, 75h, B0h)
There are three instruction codes for Program or Erase Suspend (PES) to enable legacy and alternate source
software compatibility.
The PES command allows the system to interrupt a programming or erase operation and then read from any
other non-erase-suspended sector or non-program-suspended-page. Program or Erase Suspend is valid only
during a programming or Sector Erase operation. A Bulk Erase operation cannot be suspended.
The Write-In-Progress (WIP) bit in Status Register 1 (SR1V[0]) must be checked to know when the
programming or erase operation has stopped. The Program Suspend Status bit in the Status Register 2
(SR2[0]) can be used to determine if a programming operation has been suspended or was completed at the
time WIP changes to 0. The Erase Suspend Status bit in the Status Register 2 (SR2[1]) can be used to
determine if an erase operation has been suspended or was completed at the time WIP changes to 0. The
time required for the suspend operation to complete is tSL, see Table 11.2, Program or Erase Suspend AC
Parameters on page 134.
An Erase can be suspended to allow a program operation or a read operation. During an erase suspend, the
DYB array may be read to examine sector protection and written to remove or restore protection on a sector
to be programmed.
A program operation may be suspended to allow a read operation.
A new erase operation is not allowed with an already suspended erase or program operation. An erase
command is ignored in this situation.
Table 10.5 Commands Allowed During Program or Erase Suspend (Sheet 1 of 2)
Allowed
During
Erase
Allowed
During
Program
Suspend
Instruction
Code
(Hex)
Instruction
Name
Comment
Suspend
Required for array program during erase suspend. Only allowed if there is no
other program suspended program operation (SR2V[0]=0). A program
command will be ignored while there is a suspended program. If a program
command is sent for a location within an erase suspended sector the program
operation will fail with the P_ERR bit set.
PP
02
X
READ
RDSR1
RDAR
03
05
65
06
X
X
X
X
X
X
X
All array reads allowed in suspend.
Needed to read WIP to determine end of suspend process.
Alternate way to read WIP to determine end of suspend process.
Required for program command within erase suspend.
WREN
Needed to read suspend status to determine whether the operation is
suspended or complete.
RDSR2
4PP
07
X
X
Required for array program during erase suspend. Only allowed if there is no
other program suspended program operation (SR2V[0]=0). A program
command will be ignored while there is a suspended program. If a program
command is sent for a location within an erase suspended sector the program
operation will fail with the P_ERR bit set.
12
X
4READ
CLSR
CLSR
EPR
13
30
82
30
X
X
X
X
X
X
All array reads allowed in suspend.
Clear status may be used if a program operation fails during erase suspend.
Note the instruction is only valid if enabled for clear status by CR4NV[2=1].
Clear status may be used if a program operation fails during erase suspend.
Required to resume from erase or program suspend. Note the command must
be enabled for use as a resume command by CR4NV[2]=0.
EPR
EPR
7A
8A
66
99
0B
0C
7A
8A
BB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Required to resume from erase or program suspend.
Required to resume from erase or program suspend.
Reset allowed anytime.
RSTEN
RST
Reset allowed anytime.
FAST_READ
4FAST_READ
EPR
All array reads allowed in suspend.
All array reads allowed in suspend.
Required to resume from erase suspend.
Required to resume from erase suspend.
All array reads allowed in suspend.
EPR
DIOR
X
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Table 10.5 Commands Allowed During Program or Erase Suspend (Sheet 2 of 2)
Allowed
During
Erase
Allowed
During
Program
Suspend
Instruction
Code
(Hex)
Instruction
Name
Comment
Suspend
4DIOR
BC
FA
X
X
X
All array reads allowed in suspend.
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
DYBRD
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
DYBWR
PPBRD
FB
FC
E0
E1
E2
X
X
X
X
X
Allowed for checking Persistent Protection before attempting a program
command during erase suspend.
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
4DYBRD
4DYBWR
4PPBRD
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
Allowed for checking Persistent Protection before attempting a program
command during erase suspend.
QIOR
4QIOR
EB
EC
ED
EE
F0
X
X
X
X
X
X
X
X
X
X
X
X
All array reads allowed in suspend.
All array reads allowed in suspend.
All array reads allowed in suspend.
All array reads allowed in suspend.
Reset allowed anytime.
DDRQIOR
4DDRQIOR
RESET
MBR
FF
May need to reset a read operation during suspend.
Reading at any address within an erase-suspended sector or program-suspended page produces
undetermined data.
The WRR, WRAR, or PPB Erase commands are not allowed during Erase or Program Suspend, it is
therefore not possible to alter the Block Protection or PPB bits during Erase Suspend. If there are sectors that
may need programming during Erase suspend, these sectors should be protected only by DYB bits that can
be turned off during Erase Suspend.
After an erase-suspended program operation is complete, the device returns to the erase-suspend mode.
The system can determine the status of the program operation by reading the WIP bit in the Status Register,
just as in the standard program operation.
Figure 10.53 Program or Erase Suspend Command Sequence
tSL
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4 3 2 1 0
7
6
5
4 3 2 1 0
Phase
Phase
Suspend Instruction
Read Status Instruction
Status
Instr. During Suspend
Repeat Status Read Until Suspended
Figure 10.54 Program or Erase Suspend Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
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This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock
cycles per byte.
Figure 10.55 Program or Erase Suspend Command Sequence QPI Mode
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruction
10.6.6
Erase or Program Resume (EPR 7Ah, 8Ah, 30h)
There are three instruction codes for Erase or Program Resume (EPR) to enable legacy and alternate source
software compatibility.
After program or read operations are completed during a program or erase suspend the Erase or Program
Resume command is sent to continue the suspended operation.
After an Erase or Program Resume command is issued, the WIP bit in the Status Register 1 will be set to a 1
and the programming operation will resume if one is suspended. If no program operation is suspended the
suspended erase operation will resume. If there is no suspended program or erase operation the resume
command is ignored.
Program or erase operations may be interrupted as often as necessary e.g. a program suspend command
could immediately follow a program resume command but, in order for a program or erase operation to
progress to completion there must be some periods of time between resume and the next suspend command
greater than or equal to tRS. See Table 11.2, Program or Erase Suspend AC Parameters on page 134.
An Erase or Program Resume command must be written to resume a suspended operation.
Figure 10.56 Erase or Program Resume Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
Phase
Instruction
Figure 10.57 Erase or Program Resume Command Sequence QPI Mode
CS#
SCLK
IO0
4
5
6
7
0
1
2
3
IO1
IO2
IO3
Phase
Instruction
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10.7 One-Time Program Array Commands
10.7.1
OTP Program (OTPP 42h)
The OTP Program command programs data in the One-Time Program region, which is in a different address
space from the main array data. The OTP region is 1024 bytes so, the address bits from A31 to A10 must be
0 for this command. Refer to OTP Address Space on page 58 for details on the OTP region.
Before the OTP Program command can be accepted by the device, a Write Enable (WREN) command must
be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to
enable any write operations. The WIP bit in SR1V may be checked to determine when the operation is
completed. The P_ERR bit in SR1V may be checked to determine if any error occurred during the operation.
To program the OTP array in bit granularity, the rest of the bits within a data byte can be set to 1.
Each region in the OTP memory space can be programmed one or more times, provided that the region is not
locked. Attempting to program 0s in a region that is locked will fail with the P_ERR bit in SR1V set to 1.
Programming ones, even in a protected area does not cause an error and does not set P_ERR. Subsequent
OTP programming can be performed only on the un-programmed bits (that is, 1 data).
The protocol of the OTP Program command is the same as the Page Program command. See Page Program
(PP 02h or 4PP 12h) on page 114 for the command sequence.
10.7.2
OTP Read (OTPR 4Bh)
The OTP Read command reads data from the OTP region. The OTP region is 1024 bytes so, the address bits
from A31 to A10 must be zero for this command. Refer to OTP Address Space on page 58 for details on the
OTP region. The protocol of the OTP Read command is similar to the Fast Read command except that it will
not wrap to the starting address after the OTP address is at its maximum; instead, the data beyond the
maximum OTP address will be undefined. The OTP Read command read latency is set by the latency value
in CR2V[3:0].
See Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch) on page 106 for the command sequence.
10.8 Advanced Sector Protection Commands
10.8.1
ASP Read (ASPRD 2Bh)
The ASP Read instruction 2Bh is shifted into SI by the rising edge of the SCK signal. Then the 16-bit ASP
register contents are shifted out on the serial output SO, least significant byte first. Each bit is shifted out at
the SCK frequency by the falling edge of the SCK signal. It is possible to read the ASP register continuously
by providing multiples of 16 clock cycles. The maximum operating clock frequency for the ASP Read
(ASPRD) command is 133 MHz.
Figure 10.58 ASPRD Command
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Output ASPR Low Byte
Output ASPR High Byte
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10.8.2
ASP Program (ASPP 2Fh)
Before the ASP Program (ASPP) command can be accepted by the device, a Write Enable (WREN)
command must be issued. After the Write Enable (WREN) command has been decoded, the device will set
the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The ASPP command is entered by driving CS# to the logic low state, followed by the instruction and two data
bytes on SI, least significant byte first. The ASP Register is two data bytes in length.
The ASPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same
manner as any other programming operation.
CS# input must be driven to the logic high state after the sixteenth bit of data has been latched in. If not, the
ASPP command is not executed. As soon as CS# is driven to the logic high state, the self-timed ASPP
operation is initiated. While the ASPP operation is in progress, the Status Register may be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed ASPP
operation, and is a 0 when it is completed. When the ASPP operation is completed, the Write Enable Latch
(WEL) is set to a 0.
Figure 10.59 ASPP Command
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Input ASPR Low Byte
Input ASPR High Byte
Instruction
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10.8.3
DYB Read (DYBRD FAh or 4DYBRD E0h)
The instruction is latched into SI by the rising edge of the SCK signal. The instruction is followed by the 24 or
32-bit address, depending on the address length configuration CR2V[7], selecting location zero within the
desired sector. Note, the high order address bits not used by a particular density device must be zero. Then
the 8-bit DYB access register contents are shifted out on the serial output SO. Each bit is shifted out at the
SCK frequency by the falling edge of the SCK signal. It is possible to read the same DYB access register
continuously by providing multiples of eight clock cycles. The address of the DYB register does not increment
so this is not a means to read the entire DYB array. Each location must be read with a separate DYB Read
command. The maximum operating clock frequency for READ command is 133 MHz.
Figure 10.60 DYBRD Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
A
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Notes:
Instruction
Address
Register
Repeat Register
1. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FAh.
2. A = MSB of address = 31 with command E0h.
This command is also supported in QPI Mode. In QPI Mode the instruction and address is shifted in on IO0-
IO3 and returning data is shifted out on IO0-IO3.
Figure 10.61 DYBRD QPI Mode Command Sequence
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
A-3
A-2
A-1
A
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
IO2
IO3
7
Address
Phase
Instruction
Output DYBAR
Notes:
1. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FAh.
2. A = MSB of address = 31 with command E0h.
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10.8.4
DYB Write (DYBWR FBh or 4DYBWR E1h)
Before the DYB Write (DYBWR) command can be accepted by the device, a Write Enable (WREN) command
must be issued. After the Write Enable (WREN) command has been decoded, the device will set the Write
Enable Latch (WEL) in the Status Register to enable any write operations.
The DYBWR command is entered by driving CS# to the logic low state, followed by the instruction, followed
by the 24- or 32-bit address, depending on the address length configuration CR2V[7], selecting location zero
within the desired sector (note, the high order address bits not used by a particular density device must be
zero), then the data byte on SI. The DYB Access Register is one data byte in length. The data value must be
00h to protect or FFh to unprotect the selected sector.
The DYBWR command affects the P_ERR and WIP bits of the Status and Configuration Registers in the
same manner as any other programming operation. CS# must be driven to the logic high state after the eighth
bit of data has been latched in. As soon as CS# is driven to the logic high state, the self-timed DYBWR
operation is initiated. While the DYBWR operation is in progress, the Status Register may be read to check
the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed
DYBWR operation, and is a 0 when it is completed. When the DYBWR operation is completed, the Write
Enable Latch (WEL) is set to a 0.
Figure 10.62 DYBWR Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
A
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Address
Input Data
Notes:
1. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FBh.
2. A = MSB of address = 31 with command E1h.
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock
cycles per byte.
Figure 10.63 DYBWR QPI Mode Command Sequence
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
A-3
A-2
A-1
A
4
0
1
2
3
4
5
6
7
0
1
2
3
5
IO2
6
7
IO3
Phase
Instruction
Address
Input DYBAR
Note
1. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FBh.
2. A = MSB of address = 31 with command E1h
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10.8.5
PPB Read (PPBRD FCh or 4PPBRD E2h)
The instruction E2h is shifted into SI by the rising edges of the SCK signal, followed by the 24- or 32-bit
address, depending on the address length configuration CR2V[7], selecting location zero within the desired
sector (note, the high order address bits not used by a particular density device must be zero). Then the 8-bit
PPB access register contents are shifted out on SO.
It is possible to read the same PPB access register continuously by providing multiples of eight clock cycles.
The address of the PPB register does not increment so this is not a means to read the entire PPB array. Each
location must be read with a separate PPB Read command. The maximum operating clock frequency for the
PPB Read command is 133 MHz.
Figure 10.64 PPBRD Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
A
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Notes:
Instruction
Address
Register
Repeat Register
1. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FCh.
2. A = MSB of address = 31 with command E2h.
10.8.6
PPB Program (PPBP FDh or 4PPBP E3h)
Before the PPB Program (PPBP) command can be accepted by the device, a Write Enable (WREN)
command must be issued. After the Write Enable (WREN) command has been decoded, the device will set
the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The PPBP command is entered by driving CS# to the logic low state, followed by the instruction, followed by
the 24- or 32-bit address, depending on the address length configuration CR2V[7], selecting location zero
within the desired sector (note, the high order address bits not used by a particular density device must be
zero).
The PPBP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same
manner as any other programming operation.
CS# must be driven to the logic high state after the last bit of address has been latched in. If not, the PPBP
command is not executed. As soon as CS# is driven to the logic high state, the self-timed PPBP operation is
initiated. While the PPBP operation is in progress, the Status Register may be read to check the value of the
Write-In Progress (WIP) bit. The WIP bit is a 1 during the self-timed PPBP operation, and is a 0 when it is
completed. When the PPBP operation is completed, the Write Enable Latch (WEL) is set to a 0.
Figure 10.65 PPBP Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
A
1
0
Phase
Notes:
Instruction
Address
1. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FDh.
2. A = MSB of address = 31 with command E3h.
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10.8.7
PPB Erase (PPBE E4h)
The PPB Erase (PPBE) command sets all PPB bits to 1. Before the PPB Erase command can be accepted by
the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the
Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction E4h is shifted into SI by the rising edges of the SCK signal.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on
SI. This will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of
the entire PPB memory array. Without CS# being driven to the logic high state after the eighth bit of the
instruction, the PPB erase operation will not be executed.
With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to
check if the operation has been completed. The WIP bit will indicate a 1 when the erase cycle is in progress
and a 0 when the erase cycle has been completed. Erase suspend is not allowed during PPB Erase.
Figure 10.66 PPB Erase Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
Phase
Instruction
10.8.8
PPB Lock Bit Read (PLBRD A7h)
The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO. It is
possible to read the PPB lock register continuously by providing multiples of eight clock cycles. The PPB Lock
Register contents may only be read when the device is in standby state with no other operation in progress. It
is recommended to check the Write-In Progress (WIP) bit of the Status Register before issuing a new
command to the device.
Figure 10.67 PPB Lock Register Read Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Repeat Register Read
Register Read
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10.8.9
PPB Lock Bit Write (PLBWR A6h)
The PPB Lock Bit Write (PLBWR) command clears the PPB Lock Register to zero. Before the PLBWR
command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by
the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The PLBWR command is entered by driving CS# to the logic low state, followed by the instruction.
CS# must be driven to the logic high state after the eighth bit of instruction has been latched in. If not, the
PLBWR command is not executed. As soon as CS# is driven to the logic high state, the self-timed PLBWR
operation is initiated. While the PLBWR operation is in progress, the Status Register may still be read to
check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed
PLBWR operation, and is a 0 when it is completed. When the PLBWR operation is completed, the Write
Enable Latch (WEL) is set to a 0. The maximum clock frequency for the PLBWR command is 133 MHz.
Figure 10.68 PPB Lock Bit Write Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
Phase
Instruction
10.8.10 Password Read (PASSRD E7h)
The correct password value may be read only after it is programmed and before the Password mode has
been selected by programming the Password Protection mode bit to 0 in the ASP Register (ASP[2]). After the
Password Protection mode is selected the password is no longer readable, the PASSRD command will
output undefined data.
The PASSRD command is shifted into SI. Then the 64-bit Password is shifted out on the serial output SO,
least significant byte first, most significant bit of each byte first. Each bit is shifted out at the SCK frequency by
the falling edge of the SCK signal. It is possible to read the Password continuously by providing multiples of
64 clock cycles. The maximum operating clock frequency for the PASSRD command is 133 MHz.
Figure 10.69 Password Read Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Phase
Instruction
Data1
DataN
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10.8.11 Password Program (PASSP E8h)
Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded, the device sets the Write Enable Latch (WEL) to enable the PASSP operation.
The password can only be programmed before the Password mode is selected by programming the
Password Protection mode bit to 0 in the ASP Register (ASP[2]). After the Password Protection mode is
selected the PASSP command is ignored.
The PASSP command is entered by driving CS# to the logic low state, followed by the instruction and the
password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is
sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the
PASSP command is not executed. As soon as CS# is driven to the logic high state, the self-timed PASSP
operation is initiated. While the PASSP operation is in progress, the Status Register may be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PASSP
cycle, and is a 0 when it is completed. The PASSP command can report a program error in the P_ERR bit of
the Status Register. When the PASSP operation is completed, the Write Enable Latch (WEL) is set to a 0.
The maximum clock frequency for the PASSP command is 133 MHz.
Figure 10.70 Password Program Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Input Password Low Byte
Input Password High Byte
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10.8.12 Password Unlock (PASSU E9h)
The PASSU command is entered by driving CS# to the logic low state, followed by the instruction and the
password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is
sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the
PASSU command is not executed. As soon as CS# is driven to the logic high state, the self-timed PASSU
operation is initiated. While the PASSU operation is in progress, the Status Register may be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PASSU
cycle, and is a 0 when it is completed.
If the PASSU command supplied password does not match the hidden password in the Password Register,
an error is reported by setting the P_ERR bit to 1. The WIP bit of the Status Register also remains set to 1. It
is necessary to use the CLSR command to clear the Status Register, the RESET command to software reset
the device, or drive the RESET# input low to initiate a hardware reset, in order to return the P_ERR and WIP
bits to 0. This returns the device to standby state, ready for new commands such as a retry of the PASSU
command.
If the password does match, the PPB Lock bit is set to 1. The maximum clock frequency for the PASSU
command is 133 MHz.
Figure 10.71 Password Unlock Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase
Instruction
Input Password Low Byte
Input Password High Byte
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10.9 Reset Commands
Software controlled Reset commands restore the device to its initial power-up state, by reloading volatile
registers from non-volatile default values. However, the volatile FREEZE bit in the Configuration Register
CR1V[0] and the volatile PPB Lock bit in the PPB Lock Register are not changed by a software reset. The
software reset cannot be used to circumvent the FREEZE or PPB Lock bit protection mechanisms for the
other security configuration bits.
The Freeze bit and the PPB Lock bit will remain set at their last value prior to the software reset. To clear the
FREEZE bit and set the PPB Lock bit to its protection mode selected power-on state, a full power-on-reset
sequence or hardware reset must be done.
The non-volatile bits in the Configuration Register (CR1NV), TBPROT_O, TBPARM, and BPNV_O, retain
their previous state after a software reset.
The Block Protection bits BP2, BP1, and BP0, in the Status Register (SR1V) will only be reset to their default
value if FREEZE = 0.
A reset command (RST or RESET) is executed when CS# is brought high at the end of the instruction and
requires tRPH time to execute.
In the case of a previous Power-Up Reset (POR) failure to complete, a reset command triggers a full power-
up sequence requiring tPU to complete.
Figure 10.72 Software Reset Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
Phase
Instruction
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock
cycles per byte.
Figure 10.73 Software Reset Command Sequence QPI Mode
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruction
10.9.1
10.9.2
Software Reset Enable (RSTEN 66h)
The Reset Enable (RSTEN) command is required immediately before a Reset command (RST) such that a
software reset is a sequence of the two commands. Any command other than RST following the RSTEN
command, will clear the reset enable condition and prevent a later RST command from being recognized.
Software Reset (RST 99h)
The Reset (RST) command immediately following a RSTEN command, initiates the software reset process.
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10.9.3
10.9.4
Legacy Software Reset (RESET F0h)
The Legacy Software Reset (RESET) is a single command that initiates the software reset process. This
command is disabled by default but can be enabled by programming CR3V[0]=1, for software compatibility
with Spansion legacy FL-S devices.
Mode Bit Reset (MBR FFh)
The Mode Bit Reset (MBR) command is used to return the device from continuous high performance read
mode back to normal standby awaiting any new command. Because some device packages lack a hardware
RESET# input and a device that is in a continuous high performance read mode may not recognize any
normal SPI command, a system hardware reset or software reset command may not be recognized by the
device. It is recommended to use the MBR command after a system reset when the RESET# signal is not
available or, before sending a software reset, to ensure the device is released from continuous high
performance read mode.
The MBR command sends 1s on SI or IO0 for 8 SCK cycles. IO1 to IO3 are “don’t care” during these cycles.
Figure 10.74 Mode Bit Reset Command Sequence
CS#
SCK
SI
SO
7
6
5
4
3
2
1
0
Phase
Instruction
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock
cycles per byte.
Figure 10.75 Mode Bit Reset Command Sequence QPI Mode
CS#
SCLK
IO0
IO1
4
5
6
7
0
1
2
3
IO2
IO3
Phase
Instruction
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11. Embedded Algorithm Performance Tables
The Joint Electron Device Engineering Council (JEDEC) standard JESD22-A117 defines the procedural
requirements for performing valid endurance and retention tests based on a qualification specification. This
methodology is intended to determine the ability of a flash device to sustain repeated data changes without
failure (program/erase endurance) and to retain data for the expected life (data retention). Endurance and
retention qualification specifications are specified in JESD47 or may be developed using knowledge-based
methods as in JESD94.
Table 11.1 Program and Erase Performance
Symbol
Parameter
Non-Volatile Register Write Time
Min
Typ (2)
Max
Unit
t
145
750
ms
W
Page Programming (512 bytes)
Page Programming (256 bytes)
475
360
1080
1080
t
t
µs
PP
Sector Erase Time (64-kB or 4-kB physical sectors)
Sector Erase Time (256-kB logical sectors = 4x64K physical sectors)
Bulk Erase Time (S25FS128S)
145
580
36
725
2900
180
360
25
ms
ms
sec
sec
SE
t
t
(1)
(1)
BE
Bulk Erase Time (S25FS256S)
72
BE
Evaluate Erase Status Time (64-kB or 4-kB physical sectors)
Evaluate Erase Status Time (256-kB physical or logical sectors)
Erase per sector
20
t
µs
EES
80
100
100,000
cycles
Notes:
1. Not 100% tested.
2. Typical program and erase times assume the following conditions: 25°C, V = 1.8V; random data pattern.
DD
3. The programming time for any OTP programming command is the same as t . This includes OTPP 42h, PNVDLR 43h, ASPP 2Fh, and
PP
PASSP E8h.
4. The programming time for the PPBP E3h command is the same as t . The erase time for PPBE E4h command is the same as t
.
SE
PP
5. Data retention of 20 years is based on 1k erase cycles or less.
Table 11.2 Program or Erase Suspend AC Parameters
Parameter
Typical
Max
Unit
Comments
The time from Suspend command until the WIP
bit is 0.
Suspend Latency (t
)
40
µs
SL
Minimum is the time needed to issue the next
Suspend command but ≥ typical periods are
needed for Program or Erase to progress to
completion.
Resume to next Program Suspend (t
)
100
µs
RS
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12. Software Interface Reference
12.1 Command Summary by Instruction
Table 12.1 S25FS-S Family Command Set (sorted by instruction)
Instruction Maximum Address
Command
Name
Command Description
Write Register (Status 1, Configuration 1)
Value
(Hex)
Frequency
(MHz)
Length
(Bytes)
QPI
WRR
PP
01
02
03
04
05
06
07
12
13
20
21
133
133
50
0
Yes
Yes
No
Page Program
3 or 4
READ
WRDI
RDSR1
WREN
RDSR2
4PP
Read
3 or 4
Write Disable
133
133
133
133
133
50
0
Yes
Yes
Yes
No
Read Status Register 1
Write Enable
0
0
Read Status Register 2
Page Program
0
4
4
Yes
No
4READ
P4E
Read
Parameter 4-kB Sector Erase
Parameter 4-kB Sector Erase
133
133
3 or 4
4
Yes
Yes
4P4E
Clear Status Register 1 - Erase/Prog. Fail Reset
This command may be disabled and the instruction value instead used
for a program / erase resume command - see Configuration Register 3
on page 69
CLSR
EPR
30
30
133
133
0
0
Yes
Yes
Erase / Program Resume (alternate instruction)
This command may be disabled and the instruction value instead used
for a clear status command - see Configuration Register 3 on page 69
RDCR
DLPRD
OTPP
Read Configuration Register 1
Data Learning Pattern Read
OTP Program
35
41
42
43
60
65
66
71
75
82
85
99
0B
0C
2B
2F
4A
4B
5A
7A
8A
9F
A6
A7
AF
B0
133
133
133
133
133
133
133
133
133
133
133
133
133
133
133
133
133
133
50
0
No
No
0
3 or 4
No
PNVDLR
BE
Program NV Data Learning Register
Bulk Erase
0
No
0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
RDAR
RSTEN
WRAR
EPS
Read Any Register
3 or 4
Software Reset Enable
0
Write Any Register
3 or 4
Erase / Program Suspend
Clear Status Register 1 (alternate instruction) - Erase/Prog. Fail Reset
Erase / Program Suspend (alternate instruction)
Software Reset
0
CLSR
0
EPS
0
RST
0
FAST_READ
Fast Read
3 or 4
4FAST_READ Fast Read
4
No
ASPRD
ASPP
WVDLR
OTPR
RSFDP
EPR
ASP Read
0
No
ASP Program
0
No
Write Volatile Data Learning Register
OTP Read
0
No
3 or 4
No
Read JEDEC Serial Flash Discoverable Parameters
Erase / Program Resume
3
0
0
0
0
0
0
0
Yes
Yes
Yes
Yes
No
133
133
133
133
133
133
133
EPR
Erase / Program Resume (alternate instruction)
Read ID (JEDEC Manufacturer ID and JEDEC CFI)
PPB Lock Bit Write
RDID
PLBWR
PLBRD
RDQID
EPS
PPB Lock Bit Read
No
Read Quad ID
Yes
Yes
Erase / Program Suspend (alternate instruction)
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Table 12.1 S25FS-S Family Command Set (sorted by instruction)
Instruction Maximum Address
Command
Name
Command Description
Enter 4-byte Address Mode
Value
(Hex)
Frequency
(MHz)
Length
(Bytes)
QPI
4BAM
DIOR
B7
BB
BC
C0
C7
D0
D8
DC
E0
E1
E2
E3
E4
E7
E8
E9
EB
EC
ED
EE
F0
133
66
0
No
No
Dual I/O Read
3 or 4
4DIOR
SBL
Dual I/O Read
66
4
No
Set Burst Length
Bulk Erase (alternate instruction)
Evaluate Erase Status
Erase 64 kB or 256 kB
Erase 64 kB or 256 kB
DYB Read
133
133
133
133
133
133
133
133
133
133
133
133
133
133
133
80
0
No
BE
0
Yes
Yes
Yes
Yes
Yes
Yes
No
EES
3 or 4
SE
3 or 4
4SE
4
4DYBRD
4DYBWR
4PPBRD
4PPBP
PPBE
4
DYB Write
4
PPB Read
4
PPB Program
4
No
PPB Erase
0
0
No
PASSRD
PASSP
PASSU
QIOR
Password Read
Password Program
Password Unlock
Quad I/O Read
Quad I/O Read
DDR Quad I/O Read
DDR Quad I/O Read
Legacy Software Reset
DYB Read
No
0
No
0
No
3 or 4
4
Yes
Yes
Yes
Yes
No
4QIOR
DDRQIOR
4DDRQIOR
RESET
DYBRD
DYBWR
PPBRD
PPBP
3 or 4
4
80
133
133
133
133
133
133
0
FA
FB
FC
FD
FF
3 or 4
3 or 4
3 or 4
3 or 4
0
Yes
Yes
No
DYB Write
PPB Read
PPB Program
No
MBR
Mode Bit Reset
Yes
12.2 Registers
The register maps are copied in this section as a quick reference. See Registers on page 59 for the full
description of the register contents.
Table 12.2 Status Register 1 Non-Volatile (SR1NV)
Bits
Field Name
Function
Type
Default State
Description
1 = Locks state of SRWD, BP, and Configuration
Register 1 bits when WP# is low by not executing WRR
or WRAR commands that would affect SR1NV, SR1V,
CR1NV, or CR1V.
StatusRegister
Write Disable
Default
7
SRWD_NV
Non-Volatile
0
0 = No protection, even when WP# is low.
Programming
Error Default
Non-Volatile
Read Only
Provides the default state for the Programming Error
Status. Not user programmable.
6
5
P_ERR_D
E_ERR_D
0
0
Erase Error
Default
Non-Volatile
Read Only
Provides the default state for the Erase Error Status. Not
user programmable.
4
3
BP_NV2
BP_NV1
Protects the selected range of sectors (Block) from
Program or Erase when the BP bits are configured as
non-volatile (CR1NV[3]=0). Programmed to 111b when
BP bits are configured to volatile (CR1NV[3]=1).- after
which these bits are no longer user programmable.
Block
Protection
Non-Volatile
Non-Volatile
000b
2
1
0
BP_NV0
WEL_D
WIP_D
Non-Volatile
Read Only
Provides the default state for the WEL Status. Not user
programmable.
WEL Default
WIP Default
0
0
Non-Volatile
Read Only
Provides the default state for the WIP Status. Not user
programmable.
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Table 12.3 Status Register 1 Volatile (SR1V)
Field
Name
Bits
Function
Type
Default State
Description
Volatile copy of SR1NV[7].
StatusRegister
Write Disable
Volatile
Read Only
7
6
5
SRWD
P_ERR
E_ERR
1 = Error occurred.
0 = No Error.
Programming
Error Occurred
Volatile
Read Only
1= Error occurred.
0 = No Error.
Erase Error
Occurred
Volatile
Read Only
4
3
BP2
BP1
Protects selected range of sectors (Block) from Program
or Erase when the BP bits are configured as volatile
(CR1NV[3]=1). Volatile copy of SR1NV[4:2] when BP
bits are configured as non-volatile. User writable when
BP bits are configured as volatile.
Block
Protection
Volatile
Volatile
Volatile
2
BP0
SR1NV
1 = Device accepts Write Registers (WRR and WRAR),
Program, or Erase commands.
0 = Device ignores Write Registers (WRR and WRAR),
Program, or Erase commands.
Write Enable
Latch
1
WEL
This bit is not affected by WRR or WRAR, only WREN
and WRDI commands affect this bit.
1= Device Busy, an embedded operation is in progress
such as Program or Erase.
Write-In-
Progress
Volatile
Read Only
0 = Ready Device is in Standby mode and can accept
commands.
0
WIP
This bit is not affected by WRR or WRAR, it only
provides WIP status.
Table 12.4 Status Register 2 Volatile (SR2V)
Bits
Field Name
Function
Type
Default State
Description
Reserved for Future Use.
7
6
5
4
3
RFU
RFU
RFU
RFU
RFU
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
1 = Sector Erase Status command result =
Erase Completed.
0 = Sector Erase Status command result =
Erase Not Completed.
Volatile
Read Only
2
ESTAT
Erase Status
0
1 = In Erase Suspend mode.
0 = Not in Erase Suspend mode.
Volatile
Read Only
1
0
ES
PS
EraseSuspend
0
0
1 = In Program Suspend mode.
0 = Not in Program Suspend mode.
Program
Suspend
Volatile
Read Only
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Table 12.5 Configuration Register 1 Non-Volatile (CR1NV)
Default
State
Bits
Field Name
Function
Type
Description
7
6
RFU
RFU
0
0
Reserved for Future
Use
Non-Volatile
Reserved.
Configures Start of
Block Protection
1 = BP starts at bottom (Low address).
0 = BP starts at top (High address).
5
TBPROT_O
OTP
0
Reserved for Future
Use
4
3
RFU
RFU
OTP
0
0
Reserved.
Configures BP2-0 in
Status Register
1 = Volatile.
0 = Non-Volatile.
BPNV_O
Configures
Parameter Sectors
location
1 = 4-kB physical sectors at top, (high address).
0 = 4-kB physical sectors at bottom (Low address).
RFU in uniform sector configuration.
2
TBPARM_O
OTP
0
1
0
QUAD_NV
FREEZE_D
Quad Non-Volatile
FREEZE Default
Non-Volatile
0
0
Provides the default state for the QUAD bit.
Non-Volatile
Read Only
Provides the default state for the Freeze bit. Not user
programmable.
Table 12.6 Configuration Register 1 Volatile (CR1V)
Default
State
Bits
Field Name
Function
Type
Description
7
6
RFU
RFU
Reserved for Future
Use
Volatile
Reserved.
Volatile copy of
TBPROT_O
Volatile
Read Only
Not user writable.
See CR1NV[5] TBPROT_O.
5
4
3
2
1
TBPROT
RFU
Reserved for Future
Use
RFU
Reserved.
Volatile copy of
BPNV_O
Volatile
Read Only
Not user writable.
See CR1NV[3] BPNV_O.
BPNV
CR1NV
Volatile copy of
TBPARM_O
Volatile
Read Only
Not user writable.
See CR1NV[2] TBPARM_O.
TBPARM
QUAD
1 = Quad.
0 = Dual or Serial.
Quad I/O Mode
Volatile
Volatile
Lock current state of Block Protection control bits, and
OTP regions.
1 = Block Protection and OTP locked.
0 = Block Protection and OTP unlocked.
Lock-Down Block
Protection until next
power cycle
0
FREEZE
Table 12.7 Configuration Register 2 Non-Volatile (CR2NV)
Default
State
Bits
Field Name
Function
Type
Description
1 = 4-byte address.
0 = 3-byte address.
7
AL_NV
Address Length
0
1 = Enabled - QPI (4-4-4) protocol in use.
6
5
QA_NV
QPI
0
0
0 = Disabled - Legacy SPI protocols in use, instruction is
always serial on SI.
1 = Enabled - IO3 is used as RESET# input when CS# is
high or Quad Mode is disabled CR1V[1]=1.
0 = Disabled - IO3 has no alternate function, hardware
reset is disabled.
IO3R_NV
RFU
IO3 Reset
Reserved
OTP
4
3
2
1
0
0
1
0
0
0
Reserved For Future Use.
0 to 15 latency (dummy) cycles following read address
or continuous mode bits.
Note that bit 3 has a default value of 1 and may be
programmed one time to 0 but cannot be returned to 1.
RL_NV
Read Latency
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Table 12.8 Configuration Register 2 Volatile (CR2V)
Default
State
Bits
Field Name
Function
Type
Description
1 = 4 byte address.
0 = 3 byte address.
7
AL
Address Length
1 = Enabled - QPI (4-4-4) protocol in use.
6
5
QA
QPI
0 = Disabled - Legacy SPI protocols in use, instruction is
always serial on SI.
1 = Enabled - IO3 is used as RESET# input when CS# is
high or Quad Mode is disabled CR1V[1]=1.
0 = Disabled - IO3 has no alternate function, hardware
reset is disabled.
IO3R_S
RFU
IO3 Reset
Reserved
Volatile
CR2NV
4
3
2
1
0
Reserved for Future Use.
0 to 15 latency (dummy) cycles following read address
or continuous mode bits.
RL
Read Latency
Table 12.9 Configuration Register 3 Non-Volatile (CR3NV)
Default
State
Bits
Field Name
Function
Type
Description
Reserved for Future Use.
7
6
RFU
RFU
Reserved
Reserved
0
0
Reserved for Future Use.
1 = Blank Check during erase enabled.
0 = Blank Check disabled.
5
4
3
2
1
0
BC_NV
02h_NV
20h_NV
30h_NV
D8h_NV
F0h_NV
Blank Check
Page Buffer Wrap
4-kB Erase
0
0
0
0
0
0
1 = Wrap at 512 bytes.
0 = Wrap at 256 bytes.
1 = 4-kB Erase disabled (Uniform Sector Architecture).
0 = 4-kB Erase enabled (Hybrid Sector Architecture).
OTP
1 = 30h is Erase or Program Resume command.
0 = 30h is clear status command.
Clear Status /
Resume Select
1 = 256-kB Erase.
0 = 64-kB Erase.
Block Erase Size
1 = F0h software reset is enabled.
0 = F0h software reset is disabled (ignored).
Legacy Software
Reset Enable
Table 12.10 Configuration Register 3 Volatile (CR3V)
Default
State
Bits
Field Name
Function
Type
Description
Reserved for Future Use.
7
6
RFU
RFU
Reserved
Reserved
Reserved for Future Use.
1 = Blank Check during erase enabled.
0 = Blank Check disabled.
Volatile
5
4
3
2
1
0
BC_V
02h_V
20h_V
30h_V
D8h_V
F0h_V
Blank Check
Page Buffer Wrap
4-kB Erase
1 = Wrap at 512 bytes.
0 = Wrap at 256 bytes.
1 = 4-kB Erase disabled (Uniform Sector Architecture).
0 = 4-kB Erase enabled (Hybrid Sector Architecture).
Volatile,
Read Only
CR3NV
1 = 30h is Erase or Program Resume command.
0 = 30h is Clear Status command.
Clear Status /
Resume Select
1 = 256-kB Erase.
0 = 64-kB Erase.
Block Erase Size
Volatile
1 = F0h software reset is enabled.
0 = F0h software reset is disabled (ignored).
Legacy Software
Reset Enable
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Table 12.11 Configuration Register 4 Non-Volatile (CR4NV)
Default
State
Bits
Field Name
OI_O
Function
Output Impedance
Wrap Enable
Type
Description
7
6
5
0
0
0
See Table 8.25, Output Impedance Control on page 71.
0 = Wrap Enabled.
1 = Wrap Disabled.
4
WE_O
1
OTP
3
2
1
RFU
RFU
Reserved
Reserved
0
0
0
Reserved for Future Use.
Reserved for Future Use.
00 = 8-byte wrap.
01 = 16-byte wrap.
10 = 32-byte wrap.
11 = 64-byte wrap.
WL_O
Wrap Length
0
0
Table 12.12 Configuration Register 4 Volatile (CR4V)
Default
State
Bits
Field Name
Function
Output Impedance
Wrap Enable
Type
Description
7
6
5
OI
See Table 8.25, Output Impedance Control on page 71.
0 = Wrap Enabled.
1 = Wrap Disabled.
4
WE
Volatile
CR4NV
3
2
1
RFU
RFU
Reserved
Reserved
Reserved for Future Use.
Reserved for Future Use.
00 = 8-byte wrap.
01 = 16-byte wrap.
10 = 32-byte wrap.
11 = 64-byte wrap.
WL
Wrap Length
0
Table 12.13 ASP Register (ASPR)
Default
Type
Bits
15 to 9
8
Field Name
RFU
Function
Reserved
Reserved
Description
State
OTP
OTP
1
1
Reserved for Future Use.
Reserved for Future Use.
RFU
7
6
5
4
3
RFU
RFU
RFU
RFU
RFU
Reserved
Reserved
Reserved
Reserved
Reserved
OTP
OTP
OTP
RFU
RFU
1
1
1
1
1
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
Password
Protection Mode
Lock Bit
0 = Password Protection mode permanently enabled.
1 = Password Protection mode not permanently enabled.
2
PWDMLB
OTP
1
Persistent
Protection Mode
Lock Bit
0 = Persistent Protection mode permanently enabled.
1 = Persistent Protection mode not permanently enabled.
1
0
PSTMLB
RFU
OTP
RFU
1
1
Reserved
Reserved for Future Use.
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Table 12.14 Password Register (PASS)
Field
Name
Bits
Function
Type
Default State
Description
Non-Volatile OTP storage of 64-bit password. The password is
no longer readable after the password protection mode is
selected by programming ASP register bit 2 to 0.
Hidden
Password
FFFFFFFF-
FFFFFFFFh
63 to 0
PWD
OTP
Table 12.15 PPB Lock Register (PPBL)
Bits
Field Name
Function
Reserved
Type
Default State
Description
Reserved for Future Use
7 to 1
RFU
Volatile
00h
ASPR[2:1] = 1xb = Persistent
Protection Mode = 1
ASPR[2:1] = 01b = Password
Protection Mode = 0
0 = PPB array protected.
1 = PPB array may be programmed or erased.
Volatile
Read
Only
0
PPBLOCK Protect PPB Array
Table 12.16 PPB Access Register (PPBAR)
Bits
Field Name
Function
Type
Default State
Description
00h = PPB for the sector addressed by the PPBRD or
PPBP command is programmed to 0, protecting that
sector from program or erase operations.
FFh = PPB for the sector addressed by the PPBRD
command is 1, not protecting that sector from program
or erase operations.
Read or Program
per sector PPB
7 to 0
PPB
Non-Volatile
FFh
Table 12.17 DYB Access Register (DYBAR)
Bits
Field Name
Function
Type
Default State
Description
00h = DYB for the sector addressed by the DYBRD or DYBWR
command is cleared to 0, protecting that sector from program or
erase operations.
FFh = DYB for the sector addressed by the DYBRD or DYBWR
command is set to 1, not protecting that sector from program or
erase operations.
Read or Write
per sector DYB
7 to 0
DYB
Volatile
FFh
Table 12.18 Non-Volatile Data Learning Register (NVDLR)
Bits
Field Name
Function
Type
Default State
Description
OTP value that may be transferred to the host during DDR read
command latency (dummy) cycles to provide a training pattern to
help the host more accurately center the data capture point in the
received data bits.
Non-Volatile
Data Learning
Pattern
7 to 0
NVDLP
OTP
00h
Table 12.19 Volatile Data Learning Register (VDLR)
Bits
Field Name
Function
Type
Default State
Description
Takes the
value of
NVDLR
Volatile Data
Learning
Pattern
Volatile copy of the NVDLP used to enable and deliver the Data
Learning Pattern (DLP) to the outputs. The VDLP may be changed
7 to 0
VDLP
Volatile
during POR by the host during system operation.
or Reset
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12.3 Serial Flash Discoverable Parameters (SFDP) Address Map
The SFDP address space has a header starting at address zero that identifies the SFDP data structure and
provides a pointer to each parameter. One parameter is mandated by the JEDEC JESD216 standard.
Spansion provides an additional parameter by pointing to the ID-CFI address space i.e. the ID-CFI address
space is a sub-set of the SFDP address space. The JEDEC parameter is located within the ID-CFI address
space and is thus both a CFI parameter and an SFDP parameter. In this way both SFDP and ID-CFI
information can be accessed by either the RSFDP or RDID commands.
Table 12.20 SFDP Overview Map
Relative Byte
Address Offset
SFDP Dword
Address
Description
0000h
,,,
00h
...
Location zero within SFDP space - start of SFDP header.
Remainder of SFDP header followed by undefined space.
Location zero within ID-CFI space - start of ID-CFI.
ID-CFI parameters.
1000h
...
400h
...
1120h
448h
Start of SFDP JEDEC parameter which is also part of a CFI parameter.
Remainder of SFDP JEDEC parameter followed by either more CFI parameters or undefined
space.
...
...
12.3.1
Field Definitions
Table 12.21 SFDP Header
Relative Byte
Address Offset
SFDP Dword
Address
Data
Description
This is the entry point for Read SFDP (5Ah) command i.e. location zero within
00h
53h
SFDP space
ASCII “S”
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
46h
44h
50h
00h
01h
01h
FFh
00h
00h
01h
09h
ASCII “F”
ASCII “D”
ASCII “P”
SFDP Minor Revision
SFDP Major Revision
01h
02h
Number of Parameter Headers (zero based, 01h = 2 parameters)
Unused
Manufacturer ID (JEDEC SFDP Mandatory Parameter)
Parameter Minor Revision
Parameter Major Revision
Parameter Table Length (in double words = Dwords = 4 byte units)
Parameter Table Pointer Byte 0 (Dword = 4-byte aligned)
JEDEC parameter byte offset = 1120h = 448h Dword address
0Ch
48h
0Dh
0Eh
0Fh
10h
11h
12h
13h
04h
00h
FFh
01h
00h
01h
51h
Parameter Table Pointer Byte 1
Parameter Table Pointer Byte 2
Unused
03h
04h
Manufacturer ID (Spansion)
Parameter Minor Revision
Parameter Major Revision
Parameter Table Length (in double words = Dwords = 4-byte units)
Parameter Table Pointer Byte 0 (Dword = 4-byte aligned)
Entry point for ID-CFI parameter is byte offset = 1000h relative to SFDP location
zero. 1000h Bytes = 400h Dwords
14h
00h
05h
15h
16h
17h
04h
00h
FFh
Parameter Table Pointer Byte 1
Parameter Table Pointer Byte 2
Unused
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12.4 Device ID and Common Flash Interface (ID-CFI) Address Map
12.4.1
Field Definitions
Table 12.22 Manufacturer and Device ID
Byte Address
Data
Description
Manufacturer ID for Spansion
00h
01h
20h (128 Mb)
02h (256 Mb)
01h
02h
Device ID Most Significant Byte - Memory Interface Type
Device ID Least Significant Byte - Density
18h (128 Mb)
19h (256 Mb)
ID-CFI Length - number bytes following. Adding this value to the
current location of 03h gives the address of the last valid location in
the ID-CFI legacy address map. The legacy CFI address map ends
with the Primary Vendor-Specific Extended Query. The original
legacy length is maintained for backward software compatibility.
However, the CFI Query Identification String also includes a pointer
to the Alternate Vendor-Specific Extended Query that contains
additional information related to the FS-S family.
03h
04h
4Dh
Physical Sector Architecture
The S25FS-S family may be configured with or without 4-kB
parameter sectors in addition to the uniform sectors.
00h (Uniform 256-kB physical sectors)
01h (Uniform 64-kB physical sectors)
05h
06h
81h (S25FS-S Family)
xxh
Family ID
ASCII characters for Model
Refer to Ordering Information on page 151 for the model number
definitions.
07h
08h
xxh
xxh
Reserved
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
xxh
xxh
xxh
xxh
xxh
xxh
xxh
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 12.23 CFI Query Identification String
Byte Address
Data
Description
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
13h
14h
02h
00h
Primary OEM Command Set
FL-P backward compatible command set ID
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
53h
46h
Alternate OEM Command Set
ASCII characters “FS” for SPI (F) interface, S Technology
19h
1Ah
51h
00h
Address for Alternate OEM Extended Table
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Table 12.24 CFI System Interface String
Byte Address
Data
17h
19h
00h
00h
09h
Description
1Bh
1Ch
1Dh
1Eh
1Fh
V
V
V
V
Min. (erase/program): 100 millivolts BCD
Max. (erase/program): 100 millivolts BCD
DD
DD
PP
PP
Min. voltage (00h = no V present)
PP
Max. voltage (00h = no V present)
PP
Typical timeout per single byte program 2N µs
Typical timeout for Min. size Page program 2N µs
(00h = not supported)
20h
21h
09h
08h (4 kB or 64 kB)
0Ah (256 kB)
Typical timeout per individual Sector Erase 2N ms
0Fh (128 Mb)
10h (256 Mb)
22h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
24h
25h
02h
02h
03h
Max. timeout for byte program 2N times typical
Max. timeout for page program 2N times typical
Max. timeout per individual Sector Erase 2N times typical
Max. timeout for full chip erase 2N times typical
(00h = not supported)
26h
03h
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Table 12.25 Device Geometry Definition for Bottom Boot Initial Delivery State
Byte Address
Data
Description
18h (128 Mb)
19h (256 Mb)
27h
28h
Device Size = 2N bytes;
02h
01h
Flash Device Interface Description;
0000h = x8 only
0001h = x16 only
0002h = x8/x16 capable
0003h = x32 only
29h
0004h = Single I/O SPI, 3-byte address
0005h = Multi I/O SPI, 3-byte address
0102h = Multi I/O SPI, 3- or 4-byte address
2Ah
2Bh
08h
00h
Max. number of bytes in multi-byte write = 2N
0000 = not supported
0008h = 256B page
Number of Erase Block Regions within device
1 = Uniform Device, >1 = Boot Device
2Ch
03h
2Dh
2Eh
2Fh
30h
31h
32h
33h
07h
00h
10h
00h
00h
00h
80h
Erase Block Region 1 Information (refer to JEDEC JEP137)
8 sectors = 8-1 = 0007h
4-kB sectors = 256 bytes x 0010h
Erase Block Region 2 Information (refer to JEDEC JEP137)
128 Mb and 256 Mb:
1 sector = 1-1 = 0000h
32-kB sector = 256 bytes x 0080h
00h (128 Mb)
00h (256 Mb)
34h
35h
FEh
Erase Block Region 3 Information
128 Mb and 256 Mb:
00h (128 Mb)
01h (256 Mb)
36h
255 sectors = 255-1 = 00FEh (128 Mb)
511 sectors = 511-1 = 01FEh (256 Mb)
64-kB sectors = 0100h x 256 bytes
37h
00h
01h (128 Mb)
01h (256 Mb)
38h
39h thru 3Fh
FFh
RFU
Note:
1. FS-S devices are user configurable to have either a hybrid sector architecture (with eight 4-kB sectors and all remaining sectors are
uniform 64 kB or 256 kB) or a uniform sector architecture with all sectors uniform 64 kB or 256 kB. FS-S devices are also user
configurable to have the 4-kB parameter sectors at the top of memory address space. The CFI geometry information of the above table is
relevant only to the initial delivery state. All devices are initially shipped from Spansion with the hybrid sector architecture with the 4-kB
sectors located at the bottom of the array address map. However, the device configuration TBPARM bit CR1NV[2] may be programed to
invert the sector map to place the 4-kB sectors at the top of the array address map. The 20h_NV bit (CR3NV[3} may be programmed to
remove the 4-kB sectors from the address map. The flash device driver software must examine the TBPARM and 20h_NV bits to
determine if the sector map was inverted or hybrid sectors removed at a later time.
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Table 12.26 CFI Primary Vendor-Specific Extended Query
Byte Address
Data
50h
52h
49h
31h
33h
Description
40h
41h
42h
43h
44h
Query-unique ASCII string “PRI”
Major version number = 1, ASCII
Minor version number = 3, ASCII
Address Sensitive Unlock (Bits 1-0)
00b = Required, 01b = Not Required
Process Technology (Bits 5-2)
0000b = 0.23 µm Floating Gate
0001b = 0.17 µm Floating Gate
0010b = 0.23 µm MirrorBit
45h
21h
0011b = 0.11 µm Floating Gate
0100b = 0.11 µm MirrorBit
0101b = 0.09 µm MirrorBit
1000b = 0.065 µm MirrorBit
Erase Suspend
0 = Not Supported
1 = Read Only
46h
02h
2 = Read and Program
Sector Protect
47h
48h
01h
00h
00 = Not Supported
X = Number of sectors in group
Temporary Sector Unprotect
00 = Not Supported
01 = Supported
Sector Protect/Unprotect Scheme
04 = High Voltage Method
49h
08h
05 = Software Command Locking Method
08 = Advanced Sector Protection Method
Simultaneous Operation
00 = Not Supported
4Ah
4Bh
00h
01h
X = Number of Sectors
Burst Mode (Synchronous sequential read) support
00 = Not Supported
01 = Supported
Page Mode Type, initial delivery configuration, user configurable for 512B page
00 = Not Supported
01 = 4 Word Read Page
02 = 8-Read Word Page
4Ch
03h
03 = 256-byte Program Page
04 = 512-byte Program Page
ACC (Acceleration) Supply Minimum
00 = Not Supported, 100 mV
4Dh
4Eh
00h
00h
ACC (Acceleration) Supply Maximum
00 = Not Supported, 100 mV
WP# Protection
01 = Whole Chip
4Fh
50h
07h
01h
04 = Uniform Device with Bottom WP Protect
05 = Uniform Device with Top WP Protect
07 = Uniform Device with Top or Bottom Write Protect (user configurable)
Program Suspend
00 = Not Supported
01 = Supported
The Alternate Vendor-Specific Extended Query provides information related to the expanded command set
provided by the FS-S family. The alternate query parameters use a format in which each parameter begins
with an identifier byte and a parameter length byte. Driver software can check each parameter ID and can use
the length value to skip to the next parameter if the parameter is not needed or not recognized by the
software.
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Table 12.27 CFI Alternate Vendor-Specific Extended Query Header
Byte Address
Data
41h
4Ch
54h
32h
30h
Description
51h
52h
53h
54h
55h
Query-unique ASCII string “ALT”
Major version number = 2, ASCII
Minor version number = 0, ASCII
Table 12.28 CFI Alternate Vendor-Specific Extended Query Parameter 0
Parameter Relative
Byte Address
Offset
Data
Description
00h
01h
00h
10h
Parameter ID (Ordering Part Number)
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
03h
04h
05h
06h
53h
32h
35h
46h
53h
ASCII “S” for manufacturer (Spansion)
ASCII “25” for Product Characters (Single Die SPI)
ASCII “FS” for Interface Characters (SPI 1.8 Volt)
31h (128 Mb)
32h (256 Mb)
07h
08h
09h
32h (128 Mb)
35h (256 Mb)
ASCII characters for density
38h (128 Mb)
36h (256 Mb)
0Ah
0Bh
0Ch
0Dh
0Eh
53h
FFh
FFh
FFh
FFh
FFh
ASCII “S” for Technology (65 nm MirrorBit)
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
0Fh
10h
11h
xxh
xxh
ASCII characters for Model
Refer to Ordering Information on page 151 for the model number definitions.
Table 12.29 CFI Alternate Vendor-Specific Extended Query Parameter 80h Address Options
Parameter Relative
Byte Address
Offset
Data
Description
00h
01h
80h
01h
Parameter ID (Ordering Part Number)
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
Bits 7:5 - Reserved = 111b
Bit 4 - Address Length Bit in CR2V[7] - Yes= 0b
Bit 3 - AutoBoot support - No = 1b
Bit 2 - 4 byte address instructions supported - Yes= 0b
Bit 1 - Bank address + 3-byte address instructions supported - No = 1b
Bit 0 - 3-byte address instructions supported - No = 1b
02h
EBh
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Table 12.30 CFI Alternate Vendor-Specific Extended Query Parameter 84h Suspend Commands
Parameter Relative
Byte Address
Data
Description
Offset
00h
84h
08h
Parameter ID (Suspend Commands
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
01h
02h
03h
04h
05h
06h
07h
08h
09h
75h
28h
7Ah
64h
75h
28h
7Ah
64h
Program suspend instruction code
Program suspend latency maximum (µs)
Program resume instruction code
Program resume to next suspend typical (µs)
Erase suspend instruction code
Erase suspend latency maximum (µs)
Erase resume instruction code
Erase resume to next suspend typical (µs)
Table 12.31 CFI Alternate Vendor-Specific Extended Query Parameter 88h Data Protection
Parameter Relative
Byte Address
Offset
Data
Description
00h
01h
02h
88h
04h
0Ah
Parameter ID (Data Protection)
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
OTP size 2N bytes, FFh = not supported
OTP address map format,
03h
01h
01h = FL-S and FS-S format
FFh = not supported
Block Protect Type, model dependent
00h = FL-P, FL-S, FS-S
04h
05h
xxh
xxh
FFh = not supported
Advanced Sector Protection type, model dependent
01h = FL-S and FS-S ASP.
Table 12.32 CFI Alternate Vendor-Specific Extended Query Parameter 8Ch Reset Timing
Parameter Relative
Byte Address
Offset
Data
Description
00h
01h
8Ch
06h
Parameter ID (Reset Timing)
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
03h
96h
01h
POR maximum value
POR maximum exponent 2N µs
Hardware Reset maximum value, FFh = not supported (the initial delivery state has
hardware reset disabled but it may be enabled by the user at a later time)
04h
23h
05h
06h
07h
00h
23h
00h
Hardware Reset maximum exponent 2N µs
Software Reset maximum value, FFh = not supported
Software Reset maximum exponent 2N µs
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Table 12.33 CFI Alternate Vendor-Specific Extended Query Parameter F0h RFU
Parameter Relative
Byte Address
Offset
Data
Description
00h
01h
F0h
0Fh
Parameter ID (RFU)
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
...
FFh
FFh
FFh
RFU
RFU
RFU
10h
This parameter type (Parameter ID F0h) may appear multiple times and have a different length each time.
The parameter is used to reserve space in the ID-CFI map or to force space (pad) to align a following
parameter to a required boundary.
Table 12.34 CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP (Sheet 1 of 2)
Parameter
Relative Byte
SFDP Relative
Dword
Data
Description
Address Offset Address Offset
00h
01h
N/A
N/A
A5h
3Ch
CFI Parameter ID (JEDEC SFDP)
Parameter Length (The number of following bytes in this parameter. Adding this
value to the current location value +1 = the first byte of the next parameter).
Start of SFDP JEDEC parameter
Bits 7:5 = unused = 111b
Bit 4 = 06h is Status Register write instruction = 1
Bit 3 = 00h must be written to Status Register to enable program and erase = 1
Bit 2 = Program Buffer > 64 bytes = 1
02h
03h
FFh
FFh
Bits 1:0 = Uniform 4-kB erase unavailable = 11b
00h
Uniform 4-kB erase opcode = not supported = FFh
JEDEC SFDP
Parameter
Dword-1
Bit 23 = Unused = 1b
Bit 22 = Supports Quad Out (1-1-4) Read = No = 0b
Bit 21 = Supports Quad I/O (1-4-4) Read = Yes = 1b
Bit 20 = Supports Dual I/O (1-2-2) Read = Yes = 1b
Bit19 = Supports DDR 0= No, 1 = Yes
B2h
(FSxxxSAG)
04h
BAh
(FSxxxSDS)
Bit 18:17 = Number of Address Bytes, 3 or 4 = 01b
Bit 16 = Supports Dual Out (1-1-2) Read = No = 0b
05h
06h
07h
08h
FFH
FFh
FFh
FFh
Bits 31:24 = Unused = FFh
Density in bits, zero based
01h
JEDEC SFDP
Parameter
Dword-2
07h (128 Mb)
0Fh (256 Mb)
09h
Bits 7:5 = number of Quad I/O (1-4-4) Mode cycles = 010b
Bits 4:0 = number of Quad I/O Dummy cycles = 01000b (Initial Delivery State)
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
48h
EBh
FFh
FFh
FFh
FFh
88h
BBh
02h
Quad I/O instruction code
JEDEC SFDP
Parameter
Dword-3
Bits 23:21 = number of Quad Out (1-1-4) Mode cycles = 111b
Bits 20:16 = number of Quad Out Dummy cycles = 11111b
Quad Out instruction code
Bits 7:5 = number of Dual Out (1-1-2) Mode cycles = 111b
Bits 4:0 = number of Dual Out Dummy cycles = 11111b
03h
Dual Out instruction code
JEDEC SFDP
Parameter
Dword-4
Bits 23:21 = number of Dual I/O (1-2-2) Mode cycles = 100b
Bits 20:16 = number of Dual I/O Dummy cycles = 01000b (Initial Delivery State)
Dual I/O instruction code
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Table 12.34 CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP (Sheet 2 of 2)
Parameter
Relative Byte
SFDP Relative
Dword
Data
Description
Address Offset Address Offset
Bits 7:5 RFU = 111b
Bit 4 = QPI supported = Yes = 1b
Bits 3:1 RFU = 11b
Bit 0 = Dual All not supported = 0b
12h
F6h
04h
JEDEC SFDP
Parameter
Dword-5
14h
13h
FFh
FFh
FFh
FFh
FFh
Bits 15:8 = RFU = FFh
Bits 23:16 = RFU = FFh
Bits 31:24 = RFU = FFh
Bits 7:0 = RFU = FFh
Bits 15:8 = RFU = FFh
15h
16h
05h
17h
18h
JEDEC SFDP
Parameter
Dword-6
Bits 23:21 = number of Dual All Mode cycles = 111b
Bits 20:16 = number of Dual All Dummy cycles = 11111b
FFh
19h
1Ah
1Bh
FFh
FFh
FFh
Dual All instruction code
Bits 7:0 = RFU = FFh
Bits 15:8 = RFU = FFh
06h
JEDEC SFDP
Parameter
Dword-7
Bits 23:21 = number of QPI Mode cycles = 010b
Bits 20:16 = number of QPI Dummy cycles = 01000b
1Ch
48h
1Dh
1Eh
1Fh
EBh
0Ch
20h
QPI Mode (4-4-4) instruction code
Sector type 1 size 2N Bytes = 4-kB = 0Ch for Hybrid (Initial Delivery State)
07h
Sector type 1 instruction
JEDEC SFDP
Parameter
Dword-8
10h (128 Mb)
10h (256 Mb)
20h
Sector type 2 size 2N Bytes = 64 kB = 10h for 128 Mb and 256 Mb
21h
22h
23h
24h
25h
D8
Sector type 2 instruction
00h
FFh
00h
FFh
Sector type 3 size 2N Bytes = not supported = 00h
Sector type 3 instruction = not supported = FFh
Sector type 4 size 2N Bytes = not supported = 00h
Sector type 4 instruction = not supported = FFh
08h
JEDEC SFDP
Parameter
Dword-9
12.5 Initial Delivery State
The device is shipped from Spansion with non-volatile bits set as follows:
The entire memory array is erased: i.e. all bits are set to 1 (each byte contains FFh).
The OTP address space has the first 16 bytes programmed to a random number. All other bytes are erased
to FFh.
The SFDP address space contains the values as defined in the description of the SFDP address space.
The ID-CFI address space contains the values as defined in the description of the ID-CFI address space.
The Status Register 1 Non-Volatile contains 00h (all SR1NV bits are cleared to 0’s).
The Configuration Register 1 Non-Volatile contains 00h.
The Configuration Register 2 Non-Volatile contains 08h.
The Configuration Register 3 Non-Volatile contains 00h.
The Configuration Register 4 Non-Volatile contains 10h.
The Password Register contains FFFFFFFF-FFFFFFFFh
All PPB bits are 1.
The ASP Register bits are FFFFh
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Ordering Information
13. Ordering Part Number
The ordering part number is formed by a valid combination of the following:
S25FS
256
S
AG
M
F
I
00
1
Packing Type
0
1
3
=
=
=
Tray
Tube
13” Tape and Reel
Model Number (Additional Ordering Options)
00
10
20
30
1D
=
=
=
=
=
SOIC16 / WSON footprint, 64-kB Physical Sector
SOIC8 / WSON, 64-kB Physical Sector
5x5 ball BGA footprint, 64-kB Physical Sector
4x6 ball BGA footprint, 64-kB Physical Sector
SOIC8, 64-kB Physical Sector, DDR
Temperature Range
I
V
=
=
Industrial (–40°C to + 85°C)
Automotive In-Cabin (–40°C to + 105°C)
Package Materials
F
H
=
=
Lead (Pb)-free
Low-Halogen, Lead (Pb)-free
Package Type
M
N
B
=
=
=
16-pin SOIC / 8-Lead SOIC
8-contact WSON 6 x 8 mm / WSON 6 x 5 mm
24-ball BGA 6 x 8 mm package, 1.00 mm pitch
Speed
AG
DS
=
=
133 MHz
80 MHz DDR
Device Technology
S
=
0.065 µm MirrorBit Process Technology
Density
128
256
=
=
128 Mbit
256 Mbit
Device Family
S25FS
Spansion Memory 1.8 Volt-only, Serial Peripheral Interface (SPI) Flash
Memory
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Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
Valid Combinations
Base Ordering
Part Number
Speed
Option
Package and
Temperature
Model Number
Packing Type
Package Marking
AG
AG
AG
DS
DS
DS
AG
AG
AG
DS
DS
DS
MFI, MFV
NFI, NFV
BHI, BHV
MFI, MFV
NFI, NFV
BHI, BHV
MFI, MFV
NFI, NFV
BHI, BHV
MFI, MFV
NFI, NFV
BHI, BHV
10
10
0, 1, 3
0, 1, 3
0, 3
FS128S + (Temp) + F + (Model Number)
FS128S + A + (Temp) + F + (Model Number)
FS128S + A + (Temp) + H + (Model Number)
FS128S + (Temp) + F + (Model Number)
FS128S + D + (Temp) + F + (Model Number)
FS128S + D + (Temp) + H + (Model Number)
FS256S + A + (Temp) + F + (Model Number)
FS256S + A + (Temp) + F + (Model Number)
FS256S + A + (Temp) + H + (Model Number)
FS256S + D + (Temp) + F + (Model Number)
FS256S + D + (Temp) + F + (Model Number)
FS256S + D + (Temp) + H + (Model Number)
20, 30
1D
S25FS128S
0, 1, 3
0, 1, 3
0, 3
10
20, 30
00
0, 1, 3
0, 1, 3
0, 3
00
20, 30
00
S25FS256S
0, 1, 3
0, 1, 3
0, 3
00
20, 30
14. Contacting Spansion
Obtain the latest list of company locations and contact information at
http://www.spansion.com/About/Pages/Locations.aspx.
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15. Revision History
Section
Description
Revision 01 (April 5, 2013)
Initial release
Revision 02 (April 8, 2013)
Initial Delivery State
Revision 03 (August 22, 2013)
Global
Corrected information on Configuration Register 2
Replaced ‘Quad All’ with ‘QPI’
Performance Summary
Migration Notes
Typical Program and Erase Rates table: corrected kbytes / s
Spansion SPI Families Comparison table: corrected Page Programming Rate (typ.) for FS-S
FS-S DC Characteristics table: added ISB (Automotive)
AC Characteristics table: updated Parameter for FSCK, C
DC Characteristics
SDR AC Characteristics
Latency Code (Cycles) Versus Frequency table:
updated table
Registers
added Note 4
Embedded Algorithm Performance
Tables
Program and Erase Performance table: corrected Typ and Max values for tPP
Added 1D and 5D to Model Number
Ordering Information
Revision 04 (November 6, 2013)
Global
Valid Combinations table: corrected Model Number for S25FS128S
Changed data sheet designation from “Advance Information” to “Preliminary”
Changed USON to WSON
Added figure: 8-Pin Plastic Small Outline Package (SOIC8)
Updated figure: 8-Connector Package (WSON 6x5)
Physical Interface
Removed figure: VSOP Thin 8-Lead, 208 mil Body Width, (SOV008)
Configuration Register 4
Ordering Information
Updated Output Impedance Control table
Updated Model Numbers and Package Type
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2013 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™ and
combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used
are for informational purposes only and may be trademarks of their respective owners.
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