S29AL016M90TFIR22 [SPANSION]
16 MEGABIT (2M X 8 BIT / I M X 16 BIT) 3.0 VOLT ONLY BOOT SECTOR FLASH MEMORY; 16兆位（ 2M ×8位/ IMX 16位）， 3.0伏只引导扇区闪存
| 型号： | S29AL016M90TFIR22 |
| 厂家： | 
SPANSION |
| 描述： | 16 MEGABIT (2M X 8 BIT / I M X 16 BIT) 3.0 VOLT ONLY BOOT SECTOR FLASH MEMORY |
| 文件： | 总59页 (文件大小：2056K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S29AL016M
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
3.0 Volt-only Boot Sector Flash Memory
featuring MirrorBitTM technology
DATASHEET
Data Sheet
Distinctive Characteristics
Architectural Advantages
— 400 nA standby mode current
— 15 mA read current
Single power supply operation
— 3 V for read, erase, and program operations
— 40 mA program/erase current
— 400 nA Automatic Sleep mode current
Manufactured on 0.23 µm MirrorBitTM process
technology
SecSiTM (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
Package options
— 48-ball Fine-pitch BGA
— 64-ball Fortified BGA
— 48-pin TSOP
Software Features
— May be programmed and locked at the factory or by
the customer
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-
one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and thirty-
one 32 Kword sectors (word mode)
Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
Hardware Features
Top or bottom boot block configurations available
100,000 erase cycle typical per sector
20-year typical data retention
— Sector Protection: hardware-level method of
preventing write operations within a sector
— Temporary Sector Unprotect: VID-level method of
changing code in locked sectors
Performance Characteristics
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) indicates program or
erase cycle completion
High performance
— 90 ns access time
— 0.7 s typical sector erase time
Low power consumption (typical values at 5 MHz)
Publication Number S29AL016M_00 Revision A Amendment 4 Issue Date April 21, 2004
General Description
The S29AL016M is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152
bytes or 1,048,576 words. The device is offered in a 48-ball Fine-pitch BGA, 64-
ball Fortified BGA, and 48-pin TSOP packages. The word-wide data (x16) appears
on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. The device re-
quires only a single 3.0 volt power supply for both read and write functions,
designed to be programmed in-system with the standard system 3.0 volt V sup-
CC
ply. The device can also be programmed in standard EPROM programmers.
The device offers access times of 90 and 100 ns. To eliminate bus contention the
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
The device is entirely command set compatible with the JEDEC single-power-
supply Flash standard. Commands are written to the device using standard
microprocessor write timing. Write cycles also internally latch addresses and data
needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation has begun, the host system need only poll
the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/
Busy# (RY/BY#) output to determine whether the operation is complete. To
facilitate programming, an Unlock Bypass mode reduces command sequence
overhead by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low V detector that automati-
CC
cally inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause an
erase operation in a given sector to read or program any other sector and then
complete the erase operation. The Program Suspend/Program Resume fea-
ture enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would thus also reset the de-
vice, enabling the host system to read boot-up firmware from the Flash memory
device.
The device reduces power consumption in the standby mode when it detects
specific voltage levels on CE# and RESET#, or when addresses have been stable
for a specified period of time.
The SecSi™ (Secured Silicon) Sector provides a 128-word/256-byte area for
code or data that can be permanently protected. Once this sector is protected, no
further changes within the sector can occur.
MirrorBit flash technology combines years of Flash memory manufacturing expe-
rience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via hot-hole
assisted erase. The data is programmed using hot electron injection.
3
S29AL016M
S29AL016M_00A4 April 21, 2004
Table of Contents
Figure 5. Erase Operation .................................................. 30
Program Suspend/Program Resume Command Sequence ......30
Figure 6. Program Suspend/Program Resume ....................... 31
Command Definitions Tables ........................................................... 32
Command Definitions (x16 Mode, BYTE# = VIH).................... 32
Command Definitions (x8 Mode, BYTE# = VIL)...................... 33
S29AL016M 2
General Description 3
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 11
Table 1. S29AL016M Device Bus Operations .........................11
Word/Byte Configuration ....................................................................11
Write Operation Status . . . . . . . . . . . . . . . . . . . . .34
DQ7: Data# Polling .............................................................................. 34
Figure 7. Data# Polling Algorithm ....................................... 35
RY/BY#: Ready/Busy# ..........................................................................35
DQ6: Toggle Bit I .................................................................................. 36
DQ2: Toggle Bit II ................................................................................ 36
Reading Toggle Bits DQ6/DQ2 .........................................................37
Figure 8. Toggle Bit Algorithm ............................................ 38
DQ5: Exceeded Timing Limits ..........................................................38
DQ3: Sector Erase Timer .................................................................. 39
Table 12. Write Operation Status ....................................... 39
Absolute Maximum Ratings . . . . . . . . . . . . . . . . .40
Figure 9. Maximum Negative Overshoot Waveform................ 40
Figure 10. Maximum Positive Overshoot Waveform................ 40
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 40
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 41
Requirements for Reading Array Data ............................................11
Writing Commands/Command Sequences ................................... 12
Program and Erase Operation Status .............................................. 12
Standby Mode ......................................................................................... 12
Automatic Sleep Mode ......................................................................... 13
RESET#: Hardware Reset Pin ............................................................ 13
Output Disable Mode ........................................................................... 13
Table 2. Sector Address Tables (Model 01, Top Boot Device) ...14
Table 3. Sector Address Tables (Model 02, Bottom Boot Device) .
15
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 11. Test Setup........................................................ 42
Table 13. Test Specifications ............................................. 42
Figure 12. Input Waveforms and Measurement Levels............ 42
Autoselect Mode ................................................................................... 15
Table 4. Autoselect Codes (High Voltage Method) ..................16
Sector Protection/Unprotection .......................................................16
Temporary Sector Unprotect ........................................................... 17
Figure 1. Temporary Sector Unprotect Operation................... 17
Figure 2. In-System Single High Voltage Sector Protect/
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .43
Read Operations ................................................................................... 43
Figure 13. Read Operations Timings .................................... 43
Hardware Reset (RESET#) ................................................................44
Figure 14. RESET# Timings................................................ 44
Erase/Program Operations ................................................................ 45
Figure 15. Program Operation Timings................................. 46
Figure 16. Chip/Sector Erase Operation Timings.................... 47
Figure 17. Data# Polling Timings
(During Embedded Algorithms)........................................... 48
Figure 18. Toggle Bit Timings
(During Embedded Algorithms)........................................... 48
Figure 19. DQ2 vs. DQ6 for Erase and
Unprotect Algorithms ........................................................ 18
SecSi (Secured Silicon) Sector Flash Memory Region ................19
Table 5. SecSi Sector Addressing ........................................19
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ...........................................................................19
Figure 3. SecSi Sector Protect Verify ................................... 20
Common Flash Memory Interface (CFI) .......................................20
Table 6. CFI Query Identification String ...............................21
Table 7. System Interface String .........................................22
Table 8. Device Geometry Definition ....................................22
Table 9. Primary Vendor-Specific Extended Query .................23
Hardware Data Protection ................................................................ 23
Low VCC Write Inhibit ....................................................................... 23
Write Pulse “Glitch” Protection ...................................................... 23
Logical Inhibit .........................................................................................24
Power-Up Write Inhibit .....................................................................24
Command Definitions . . . . . . . . . . . . . . . . . . . . . .24
Reading Array Data .............................................................................24
Reset Command ...................................................................................24
Autoselect Command Sequence ...................................................... 25
Word/Byte Program Command Sequence ................................... 25
Erase Suspend Operations ................................................. 49
Figure 20. Temporary Sector Unprotect/Timing Diagram ........ 49
Figure 21. Sector Protect/Unprotect Timing Diagram.............. 50
Figure 22. Alternate CE# Controlled Write Operation Timings.. 52
Erase and Programming Performance . . . . . . . . .53
TSOP Pin and BGA Package Capacitance . . . . . 53
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .54
TS 048—48-Pin Standard TSOP ...................................................... 54
TSR048—48-Pin Reverse TSOP ...................................................... 55
FBA048—48-Ball Fine-Pitch Ball Grid Array (BGA)
6 x 8 mm Package ................................................................................. 56
LAA064—64-Ball Fortified Ball Grid Array (BGA)
13 x 11 mm Package ............................................................................... 57
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . 58
Unlock Bypass Command Sequence ...............................................26
Figure 4. Program Operation .............................................. 27
Chip Erase Command Sequence ...................................................... 27
Sector Erase Command Sequence ..................................................28
Erase Suspend/Erase Resume Commands ....................................28
April 21, 2004 S29AL016M_00A4
S29AL016M
4
Product Selector Guide
Family Part Number
S29AL016M
90
Speed Option
Full Voltage Range: VCC = 2.7–3.6 V
100
100
100
25
Max access time (ns)
Max CE# access time (ns)
Max OE# access time (ns)
90
90
25
Notes:
1. See “AC Characteristics” for full specifications.
2. Contact sales office or representative for availability and ordering information.
Block Diagram
DQ15–DQ0 (A-1)
RY/BY#
VCC
VSS
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
Control
WE#
BYTE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A19–A0
5
S29AL016M
S29AL016M_00A4 April 21, 2004
Connection Diagrams
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
NC
Standard TSOP
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
OE#
VSS
CE#
A0
April 21, 2004 S29AL016M_00A4
S29AL016M
6
Connection Diagrams
Fine-pitch BGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
A13
A12
A14
A15
A16
BYTE# DQ15/A-1 VSS
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
NC
D4
E4
F4
G4
H4
WE#
RESET#
A19
DQ5
DQ12
VCC
DQ4
A3
B3
NC
C3
D3
NC
E3
F3
G3
H3
RY/BY#
A18
DQ2
DQ10
DQ11
DQ3
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
CE#
OE#
VSS
7
S29AL016M
S29AL016M_00A4 April 21, 2004
Connection Diagrams
64-Ball Fortified BGA
Top View, Balls Facing Down
A8
NC
B8
NC
C8
NC
D8
NC
E8
F8
G8
NC
H8
NC
VSS
NC
A7
B7
C7
D7
E7
F7
G7
H7
A12
A14
A15
A16
BYTE# DQ15/A-1
VSS
A13
A6
A9
B6
A8
C6
D6
E6
F6
G6
H6
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
NC
D5
E5
F5
G5
H5
RESET#
A19
DQ5
DQ12
VCC
DQ4
WE#
A4
B4
NC
C4
D4
NC
E4
F4
G4
H4
RY/BY#
A18
DQ2
DQ10
DQ11
DQ3
A3
A7
B3
C3
A6
D3
A5
E3
F3
G3
H3
A17
DQ0
DQ8
DQ9
DQ1
A2
A3
B2
A4
C2
A2
D2
A1
E2
A0
F2
G2
H2
VSS
CE#
OE#
A1
NC
B1
NC
C1
NC
D1
NC
E1
F1
G1
NC
H1
NC
NC
NC
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(TSOP, BGA, SSOP, PDIP, PLCC). The package and/or data integrity may be
compromised if the package body is exposed to temperatures above 150°C for
prolonged periods of time.
April 21, 2004 S29AL016M_00A4
S29AL016M
8
Pin Configuration
A19–A0
DQ14–DQ0
DQ15/A-1
=
=
=
20 addresses
15 data inputs/outputs
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
BYTE#
CE#
=
=
=
=
=
=
=
Selects 8-bit or 16-bit mode
Chip enable
OE#
WE#
RESET#
RY/BY#
Output enable
Write enable
Hardware reset pin
Ready/Busy output
3.0 volt-only single power supply
V
CC
(see Product Selector Guide for speed
options and voltage supply tolerances)
V
NC
=
=
Device ground
Pin not connected internally
SS
Logic Symbol
20
A19–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
RESET#
BYTE#
RY/BY#
9
S29AL016M
S29AL016M_00A4 April 21, 2004
Ordering Information
Standard Products
Spansion standard products are available in several packages and operating
ranges. The order number (Valid Combination) is formed by a combination of the
elements below.
S29AL016M 90
T
A
I
01
2
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape & Reel
13” Tape & Reel
ADDITIONAL ORDERING OPTIONS
01
R1
02
R2
=
=
=
=
x8/x16, VCC= 2.7–3.6 V, top boot sector device
x8/x16, VCC= 3.0–3.6 V, top boot sector device
x8/x16, VCC= 2.7–3.6 V, bottom boot sector device
x8/x16, VCC= 3.0–3.6 V, bottom boot sector device
TEMPERATURE RANGE
I
=
Industrial (–40
°
C to +85 C)
°
PACKAGE MATERIAL SET
A
F
=
=
Standard
Pb-free
PACKAGE TYPE
T
B
F
=
=
=
Thin Small Outline Package (TSOP) Standard Pinout
Fine-Pitch Ball Grid Array (BGA)
Fortified Ball Grid Array (BGA)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29AL016M
16 Megabit (2M x 8-Bit/1M x 16-Bit) MirrorBitTM Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations for BGA Packages
for TSOP Packages
Package
Order Number
Package
01
R1
02
R2
BAI
BFI
S29AL016M90
S29AL016M10
TAI
TFI
01
R1
02
R2
FBA048
LAA064
TS048
S29AL016M90
S29AL016M10
FAI
FFI
Note: Characters 1-16 of the OPN represent the TSOP
package marking. For example, the package marking for
OPN S29AL016M90TAI010 is “S29AL016M90TAI01”
Note: Characters 4-16 of the OPN represent the BGA pack-
age marking. For example the package marking for OPN
S29AL016M90BAI010 is “AL016M90BAI01”
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this
device. Consult your local sales office to confirm availability of specific valid com-
binations and to check on newly released combinations.
April 21, 2004 S29AL016M_00A4
S29AL016M
10
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
function of the device. Table 1 lists the device bus operations, the inputs and con-
trol levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1. S29AL016M Device Bus Operations
DQ8–DQ15
BYTE#
= V
Addresses
(Note 1)
DQ0– BYTE#
Operation
CE# OE# WE# RESET#
DQ7
DOUT
DIN
= V
IH
IL
Read
Write
L
L
L
H
L
H
H
AIN
AIN
DOUT
DIN
DQ8–DQ14 = High-Z,
DQ15 = A-1
H
VCC
0.3 V
VCC
0.3 V
Standby
X
X
X
High-Z High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Protect (Note 2)
L
H
L
VID
DIN
X
X
Sector Address,
A6 = H, A1 = H,
A0 = L
Sector Unprotect (Note 2)
L
H
X
L
VID
VID
DIN
DIN
X
X
Temporary Sector
Unprotect
X
X
AIN
DIN
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT
= Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in
the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only
data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/
O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins
to V . CE# is the power control and selects the device. OE# is the output control
IL
and gates array data to the output pins. WE# should remain at V . The BYTE#
IH
pin determines whether the device outputs array data in words or bytes.
11
S29AL016M
S29AL016M_00A4 April 21, 2004
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the com-
mand register contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read Operations
table for timing specifications and to Figure 13 for the timing diagram. I
in the
CC1
DC Characteristics table represents the active current specification for reading
array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to V , and OE# to V .
IL
IH
For program operations, the BYTE# pin determines whether the device accepts
program data in bytes or words. Refer to “Word Configuration” for more
information.
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The “Word Program Command
Sequence” section has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Tables 2 and 3 indicate the address space that each sector occupies. A “sector
address” consists of the address bits required to uniquely select a sector. The
“Command Definitions” section has details on erasing a sector or the entire chip,
or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the
autoselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7–DQ0. Standard read
cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
in the DC Characteristics table represents the active current specification for
CC2
the write mode. The “AC Characteristics” section contains timing specification ta-
bles and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the
operation by reading the status bits on DQ7–DQ0. Standard read cycle timings
and I read specifications apply. Refer to “Write Operation Status” for more in-
CC
formation, and to “AC Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
April 21, 2004 S29AL016M_00A4
S29AL016M
12
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V 0.3 V. (Note that this is a more restricted voltage range than
V .) If CE# and RESET# are held at V , but not within V 0.3 V, the device
will be in the standby mode, but the standby current will be greater. The device
CC
IH
IH
CC
requires standard access time (t ) for read access when the device is in either
CE
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
In the DC Characteristics table, I
specification.
and I
represents the standby current
CC4
CC3
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The
device automatically enables this mode when addresses remain stable for t
+
ACC
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE#
control signals. Standard address access timings provide new data when
addresses are changed. While in sleep mode, output data is latched and always
available to the system. I
in the DC Characteristics table represents the
CC4
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the system drives the RESET# pin to V for at least a period of
IL
t , the device immediately terminates any operation in progress, tristates all
RP
data output pins, and ignores all read/write attempts for the duration of the RE-
SET# pulse. The device also resets the internal state machine to reading array
data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V ±0.3 V, the device draws CMOS standby current (I
). If RESET# is held
SS
CC4
at V but not within V ±0.3 V, the standby current will be greater.
IL
SS
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of t
(during Embedded Algorithms). The system can thus monitor
READY
RY/BY# to determine whether the reset operation is complete. If RESET# is as-
serted when a program or erase operation is not executing (RY/BY# pin is “1”),
the reset operation is completed within a time of t
(not during Embedded
READY
Algorithms). The system can read data t after the RESET# pin returns to V .
RH
IH
Refer to the AC Characteristics tables for RESET# parameters and to Figure 14
for the timing diagram.
Output Disable Mode
When the OE# input is at V , output from the device is disabled. The output pins
IH
are placed in the high impedance state.
13
S29AL016M
S29AL016M_00A4 April 21, 2004
Table 2. Sector Address Tables (Model 01, Top Boot Device)
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Byte Mode (x8)
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1F7FFF
1F8000–1F9FFF
1FA000–1FBFFF
1FC000–1FFFFF
Word Mode (x16)
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FBFFF
0FC000–0FCFFF
0FD000–0FDFFF
0FE000–0FFFFF
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
8/4
16/8
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section.
April 21, 2004 S29AL016M_00A4
S29AL016M
14
Table 3. Sector Address Tables (Model 02, Bottom Boot Device)
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Byte Mode (x8)
000000–003FFF
004000–005FFF
006000–007FFF
008000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
Word Mode (x16)
000000–001FFF
002000–002FFF
003000–003FFF
004000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16/8
8/4
SA2
8/4
SA3
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
protection verification, through identifier codes output on DQ7–DQ0. This mode
is primarily intended for programming equipment to automatically match a device
15
S29AL016M
S29AL016M_00A4 April 21, 2004
to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires V (11.5 V
ID
to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in
Table 4. In addition, when verifying sector protection, the sector address must
appear on the appropriate highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t care. When all necessary bits
have been set as required, the programming equipment may then read the cor-
responding identifier code on DQ7-DQ0.
To access the autoselect codes in-system, the host system can issue the autose-
lect command via the command register, as shown in Tables 10–11. This method
does not require V . See “Command Definitions” for details on using the autose-
ID
lect mode.
Table 4. Autoselect Codes (High Voltage Method)
A19 A11
to to
Mode CE# OE# WE# A12 A10 A9
A8
to
A7
A5
to
DQ8
to
DQ7
to
DQ0
Description
A6
A2 A1 A0 DQ15
Manufacturer ID
(Spansion Products)
L
L
L
L
H
H
X
X
VID
X
X
L
X
X
L
L
X
01h
C4h
Device ID:
S29AL016M
(Model 01)
Word
Byte
Word
22h
X
X
VID
L
L
L
H
L
L
L
L
H
H
X
C4h
49h
(Top Boot Block)
Device ID:
S29AL016M
(Model 02)
(Bottom Boot
Block)
22h
X
X
VID
X
X
L
H
Byte
L
L
L
L
H
H
X
49h
X
X
01h (protected)
Sector Protection
Verification
SA
X
X
X
VID
X
X
L
X
X
H
L
L
00h
(unprotected)
83 (factory
locked
03h (not
SecSi Sector Indicator Bit
(DQ7)
L
L
H
VID
H
H
X
factory locked)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Tables 10–11.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase opera-
tions in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected sectors.
The device is normally shipped with all sectors unprotected. However, the Ex-
pressFlash™ Service offers the option of programming and protecting sectors at
the factory prior to shipping the device. Contact a sales office or representative
for details.
It is possible to determine whether a sector is protected or unprotected. See “Au-
toselect Mode” for details.
April 21, 2004 S29AL016M_00A4
S29AL016M
16
Sector protection and unprotection requires V on the RESET# pin only, and can
ID
be implemented either in-system or via programming equipment. Figure 2 shows
the algorithms and Figure 23 shows the timing diagram. This method uses stan-
dard microprocessor bus cycle timing. For sector unprotect, all unprotected
sectors must first be protected prior to the first sector unprotect write cycle.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to
change data in-system. The Sector Unprotect mode is activated by setting the
RESET# pin to V . During this mode, formerly protected sectors can be pro-
ID
grammed or erased by selecting the sector addresses. Once V is removed from
ID
the RESET# pin, all the previously protected sectors are protected again. Figure
shows the algorithm, and Figure 22 shows the timing diagrams, for this feature.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Figure 1. Temporary Sector Unprotect Operation
17
S29AL016M
S29AL016M_00A4 April 21, 2004
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
Wait 1 ms
Wait 1 ms
unprotect address
No
First Write
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
No
from RESET#
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
In-System Single
High Voltage
from RESET#
In-System Single
High Voltage
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
Algorithm
Sector Unprotect
complete
Figure 2. In-System Single High Voltage Sector Protect/Unprotect Algorithms
April 21, 2004 S29AL016M_00A4 S29AL016M
18
SecSi (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that
enables permanent part identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indica-
tor Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped
from the factory. This bit is permanently set at the factory and cannot be
changed, which prevents cloning of a factory locked part. This ensures the secu-
rity of the ESN once the product is shipped to the field.
The device is offered with the SecSi Sector either customer lockable (standard
shipping option) or factory locked (contact a sales office or representative for or-
dering information). The customer-lockable version is shipped with the SecSi
Sector unprotected, allowing customers to program the sector after receiving
the device. The customer-lockable version also has the SecSi Sector Indicator
Bit permanently set to a “0.” The factory-locked version is always protected
when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indi-
cator Bit permanently set to a “1.” Thus, the SecSi Sector Indicator Bit prevents
customer-lockable devices from being used to replace devices that are factory
locked. Note that the ACC function and unlock bypass modes are not available
when the SecSi Sector is enabled.
The SecSi sector address space in this device is allocated as follows:
Table 5. SecSi Sector Addressing
SecSi Sector Address Range
Customer
Lockable
ESN Factory
Locked
ExpressFlash
Factory Locked
x16
x8
0F8000h–
0F8007h
0F8000h–
0F800Fh
ESN or determined
by customer
ESN
Determined by
customer
0F8008h–
0F807Fh
0F8010h–
0F80FFh
Determined
by customer
Unavailable
The system accesses the SecSi Sector through a command sequence (see “En-
ter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has
written the Enter SecSi Sector command sequence, it may read the SecSi Sector
by using the addresses normally occupied by the first sector (SA0). This mode of
operation continues until the system issues the Exit SecSi Sector command se-
quence, or until power is removed from the device. On power-up, or following a
hardware reset, the device reverts to sending commands to sector SA0.
Customer Lockable: SecSi Sector NOT Programmed or Protected
At the Factory
Unless otherwise specified, the device is shipped such that the customer may
program and protect the 256-byte SecSi sector.
The system may program the SecSi Sector using the write-buffer, accelerated
and/or unlock bypass methods, in addition to the standard programming com-
mand sequence. See Command Definitions.
Programming and protecting the SecSi Sector must be used with caution since,
once protected, there is no procedure available for unprotecting the SecSi Sec-
tor area and none of the bits in the SecSi Sector memory space can be modified
in any way.
The SecSi Sector area can be protected using one of the following procedures:
Write the three-cycle Enter SecSi Sector Region command sequence, and
then follow the in-system sector protect algorithm as shown in Figure 2, ex-
19
S29AL016M
S29AL016M_00A4 April 21, 2004
cept that RESET# may be at either V or V . This allows in-system protec-
IH
ID
tion of the SecSi Sector without raising any device pin to a high voltage. Note
that this method is only applicable to the SecSi Sector.
To verify the protect/unprotect status of the SecSi Sector, follow the algo-
rithm shown in Figure 3.
Once the SecSi Sector is programmed, locked and verified, the system must
write the Exit SecSi Sector Region command sequence to return to reading and
writing within the remainder of the array.
Factory Locked: SecSi Sector Programmed and Protected At the
Factory
In devices with an ESN, the SecSi Sector is protected when the device is shipped
from the factory. The SecSi Sector cannot be modified in any way. An ESN Fac-
tory Locked device has a 16-byte random ESN at addresses 0F8000h–0F8007h.
Please contact your local sales office or representative for details on ordering ESN
Factory Locked devices.
Customers may opt to have their code programmed by the manufacturer
through the ExpressFlash service (Express Flash Factory Locked). The devices
are then shipped from the factory with the SecSi Sector permanently locked.
Contact an sales office or representative for details on using the ExpressFlash
service.
START
If data = 00h,
RESET# =
SecSi Sector is
unprotected.
VIH or VID
If data = 01h,
SecSi Sector is
protected.
Wait 1 ms
Write 60h to
any address
Remove VIH or VID
from RESET#
Write 40h to SecSi
Sector address
with A6 = 0,
Write reset
command
A1 = 1, A0 = 0
SecSi Sector
Protect Verify
complete
Read from SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
Figure 3. SecSi Sector Protect Verify
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
April 21, 2004 S29AL016M_00A4
S29AL016M
20
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The system can read CFI information
at the addresses given in Tables 6–9. In word mode, the upper address bits (A7–
MSB) must be all zeros. To terminate reading CFI data, the system must write
the reset command.
The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 6–9. The system must write the reset
command to return the device to the read/reset mode.
For further information, please refer to the CFI Specification and CFI Publication
100, available online at http://www.amd.com/flash/cfi. Alternatively, contact an
sales office or representative for copies of these documents.
Table 6. CFI Query Identification String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
21
S29AL016M
S29AL016M_00A4 April 21, 2004
Table 7. System Interface String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0027h
0036h
0000h
0000h
0007h
0000h
000Ah
0000h
0001h
0000h
0004h
0000h
VCC Min. (write/erase). D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase). D7–D4: volt, D3–D0: 100 millivolt
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Reserved for future use
Max. timeout for buffer write 2N times typical (00h = not supported)
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Note: CFI data related to timeouts may differ from actual timeouts of the product. Consult the Ordering the Erase and
Programming Performance table for timeout guidelines.
Table 8. Device Geometry Definition
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
27h
4Eh
0015h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0004h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0000h
0000h
0040h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
0001h
0000h
0020h
0000h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0080h
0000h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
001Eh
0000h
0000h
0001h
April 21, 2004 S29AL016M_00A4
S29AL016M
22
Table 9. Primary Vendor-Specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bit 1–0)
0b = Required, 1b = Not Required
45h
8Ah
0008h
Process Technology (Bits 7–2)
0010b = 0.23 µm MirrorBit
Erase Suspend
46h
47h
48h
49h
4Ah
4Bh
4Ch
8Ch
8Eh
90h
92h
94h
96h
98h
0002h
0001h
0001h
0004h
0000h
0000h
0000h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = Standard Mode
Simultaneous Operation
00 = Not Supported, 01 = Supported
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Tables 10–11 for
command definitions). In addition, the following hardware data protection mea-
sures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during V
transitions, or from system noise.
power-up and power-down
CC
Low V
Write Inhibit
CC
When V is less than V
, the device does not accept any write cycles. This pro-
LKO
CC
tects data during V power-up and power-down. The command register and all
CC
internal program/erase circuits are disabled, and the device resets. Subsequent
writes are ignored until V
is greater than V
. The system must provide the
CC
LKO
proper signals to the control pins to prevent unintentional writes when V
is
CC
greater than V
.
LKO
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
23
S29AL016M
S29AL016M_00A4 April 21, 2004
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V , CE# = V or WE# =
IL
IH
V . To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
IH
logical one.
Power-Up Write Inhibit
If WE# = CE# = V and OE# = V during power up, the device does not accept
IL
IH
commands on the rising edge of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Tables 10–11 define the valid register com-
mand sequences. Note that writing incorrect address and data values or writing
them in the improper sequence may place the device in an unknown state. A
reset command is then required to set the device for the next operation.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the “AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the
Erase Suspend mode. The system can read array data using the standard read
timings, except that if it reads at an address within erase-suspended sectors,
the device outputs status data. After completing a programming operation in
the Erase Suspend mode, the system may once again read array data with the
same exception. See “Erase Suspend/Erase Resume Commands” for more in-
formation on this mode.
The system must issue the reset command to re-enable the device for reading
array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data” in the “Device Bus Operations”
section for more information. The Read Operations table provides the read pa-
rameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to reading array data.
Address bits are don’t care for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the device to read-
ing array data (also applies to programming in Erase Suspend mode). Once
programming begins, however, the device ignores reset commands until the op-
eration is complete.
April 21, 2004 S29AL016M_00A4
S29AL016M
24
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to reading array data (also applies to autoselect during Erase
Suspend).
If DQ5 goes high during a program or erase operation, writing the reset command
returns the device to reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manu-
facturer and devices codes, and determine whether or not a sector is protected.
Tables 10–11 show the address and data requirements. This method is an alter-
native to that shown in Table 4, which is intended for PROM programmers and
requires V on address bit A9.
ID
The autoselect command sequence is initiated by writing two unlock cycles, fol-
lowed by the autoselect command. The device then enters the autoselect mode,
and the system may read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at
address XX01h returns the device code. A read cycle containing a sector address
(SA) and the address XX02h in word mode (or XX04h in byte mode) returns
XX01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 2 and
3 for valid sector addresses.
The system must write the reset command to exit the autoselect mode and return
to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte, depending on the state
of the BYTE# pin. Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write cycles, followed by
the program set-up command. The program address and data are written next,
which in turn initiate the Embedded Program algorithm. The system is not re-
quired to provide further controls or timings. The device automatically
generates the program pulses and verifies the programmed cell margin. Tables
10–11 show the address and data requirements for the program command se-
quence. Note that the SecSi Sector, autoselect, and CFI functions are
unavailable when a program operation is in progress.
When the Embedded Program algorithm is complete, the device then returns to
reading array data and addresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See
“Write Operation Status” for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately terminates the program-
ming operation. The Program command sequence should be reinitiated once the
device has reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. Program-
ming to the same address multiple times without intervening erases is limited.
For such application requirements, please contact your local Spansion represen-
tative. Any bit in a word or byte cannot be programmed from “0” back to a
“1”. Attempting to do so may halt the operation and set DQ5 to “1,” or cause the
Data# Polling algorithm to indicate the operation was successful. However, a suc-
25
S29AL016M
S29AL016M_00A4 April 21, 2004
ceeding read will show that the data is still “0”. Only erase operations can convert
a “0” to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the
device faster than using the standard program command sequence. The unlock
bypass command sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-cycle unlock bypass program
command sequence is all that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program command, A0h; the second
cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required
in the standard program command sequence, resulting in faster total program-
ming time. Tables 10–11 show the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle
must contain the data 90h; the second cycle the data 00h. Addresses are don’t
care for both cycles. The device then returns to reading array data.
Figure 4 illustrates the algorithm for the program operation. See the Erase/Pro-
gram Operations table in “AC Characteristics” for parameters, and to Figure 17
for timing diagrams.
April 21, 2004 S29AL016M_00A4
S29AL016M
26
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
Programming
Completed
Notes: See Tables 10 and 11 for program command sequence.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Tables 10–11 show the address and data
requirements for the chip erase command sequence. Note that the SecSi Sector,
autoselect, and CFI functions are unavailable when an erase operation is in
progress.
Any commands written to the chip during the Embedded Erase algorithm are ig-
nored. Note that a hardware reset during the chip erase operation immediately
terminates the operation. The Chip Erase command sequence should be reiniti-
ated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. See “Autoselect Command Sequence” for information on these
status bits. When the Embedded Erase algorithm is complete, the device returns
to reading array data and addresses are no longer latched.
27
S29AL016M
S29AL016M_00A4 April 21, 2004
Figure 5 illustrates the algorithm for the erase operation. See the Erase/Program
Operations tables in “AC Characteristics” for parameters, and to Figure 18 for tim-
ing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the address of the sector to be
erased, and the sector erase command. Tables 10–11 show the address and data
requirements for the sector erase command sequence. Note that the SecSi Sec-
tor, autoselect, and CFI functions are unavailable when an erase operation is
in progress.
The device does not require the system to preprogram the memory prior to erase.
The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs begins.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 µs, otherwise the last
address and command might not be accepted, and erasure may begin. It is rec-
ommended that processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase commands
can be assumed to be less than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase Suspend during the time-out
period resets the device to reading array data. The system must rewrite the
command sequence and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed
out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the
rising edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the operation. The Sector Erase
command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to
“Write Operation Status” for information on these status bits.)
Figure 5 illustrates the algorithm for the erase operation. Refer to the Erase/Pro-
gram Operations tables in the “AC Characteristics” section for parameters, and to
Figure 18 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase oper-
ation and then read data from, or program data to, any sector not selected for
erasure. This command is valid only during the sector erase operation, including
the 50 µs time-out period during the sector erase command sequence. The Erase
April 21, 2004 S29AL016M_00A4
S29AL016M
28
Suspend command is ignored if written during the chip erase operation or Em-
bedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the time-out period and suspends
the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend
command.
When the Erase Suspend command is written during a sector erase operation, the
device requires a maximum of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during the sector erase time-out,
the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the system can read array data
from or program data to any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal read and write timings and
command definitions apply. Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and
DQ2 together, to determine if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these status bits.
After an erase-suspended program operation is complete, the system can once
again read array data within non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard program operation. See “Write Operation Status” for more
information.
The system may also write the autoselect command sequence when the device
is in the Erase Suspend mode. The device allows reading autoselect codes even
at addresses within erasing sectors, since the codes are not stored in the memory
array. When the device exits the autoselect mode, the device reverts to the Erase
Suspend mode, and is ready for another valid operation. See “Autoselect Com-
mand Sequence” for more information.
The system must write the Erase Resume command (address bits are “don’t
care”) to exit the erase suspend mode and continue the sector erase operation.
Further writes of the Resume command are ignored. Another Erase Suspend
command can be written after the device has resumed erasing.
Note: During an erase operation, this flash device performs multiple internal op-
erations that are invisible to the system. When an erase operation is suspended,
any of the internal operations that were not fully completed must be restarted.
As such, if this flash device is continually issued suspend/resume commands in
rapid succession, erase progress will be impeded as a function of the number of
suspends. The result will be a longer cumulative erase time than without sus-
pends. Note that the additional suspends do not affect device reliability or future
performance. In most systems rapid erase/suspend activity occurs only briefly.
In such cases, erase performance will not be significantly impacted.
29
S29AL016M
S29AL016M_00A4 April 21, 2004
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Tables 10–11 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 5. Erase Operation
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming
operation so that data can be read from any non-suspended sector. When the
Program Suspend command is written during a programming process, the de-
vice halts the program operation within 15 µs maximum (5 µs typical) and
updates the status bits. Addresses are not required when writing the Program
Suspend command.
After the programming operation has been suspended, the system can read
array data from any non-suspended sector. The Program Suspend command
may also be issued during a programming operation while an erase is sus-
pended. In this case, data may be read from any addresses not in Erase
Suspend or Program Suspend. If a read is needed from the SecSi Sector area
(One-time Program area), then user must use the proper command sequences
to enter and exit this region.
The system may also write the autoselect command sequence when the device
is in the Program Suspend mode. The system can read as many autoselect
codes as required. When the device exits the autoselect mode, the device re-
verts to the Program Suspend mode, and is ready for another valid operation.
See Autoselect Command Sequence for more information.
After the Program Resume command is written, the device reverts to program-
ming. The system can determine the status of the program operation using the
April 21, 2004 S29AL016M_00A4
S29AL016M
30
DQ7 or DQ6 status bits, just as in the standard program operation. See Write
Operation Status for more information.
The system must write the Program Resume command (address bits are don’t
care) to exit the Program Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ignored. Another Program
Suspend command can be written after the device has resume programming.
Program Operation
Sequence in Progress
Write Program Suspend
Write address/data
XXXh/B0h
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Wait 15 ms
Autoselect and SecSi Sector
Read data as
required
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Done
No
reading?
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Figure 6. Program Suspend/Program Resume
31
S29AL016M
S29AL016M_00A4 April 21, 2004
Command Definitions Tables
Table 10. Command Definitions (x16 Mode, BYTE# = VIH
)
Bus Cycles (Notes 2–5)
Third Fourth
Command
Sequence
(Note 1)
First
Second
Fifth
Sixth
Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
6
6
4
RA
XXX
555
555
555
555
RD
F0
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
555
90
90
90
90
X00
X01
X01
X41
0001
Device ID, Top Boot (Note 8)
Device ID, Bottom Boot (Note 8)
SecSi™ Sector Factory Protect
22C4
2249
(Note 9)
Sector Group Protect Verify
(Note 9)
4
555
AA
2AA
55
555
90
(SA)X02
00/01
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
2
2
6
6
1
1
1
555
555
555
555
XXX
XXX
555
555
XXX
XXX
55
AA
AA
AA
AA
A0
90
AA
AA
B0
30
98
2AA
2AA
2AA
2AA
PA
55
55
55
55
PD
00
55
55
555
555
555
555
88
90
A0
20
XXX
PA
00
PD
Unlock Bypass
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
Chip Erase
XXX
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend (Note 12)
Program/Erase Resume (Note 13)
CFI Query (Note 14)
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A19–A15 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
9. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
2. All values are in hexadecimal.
10. Unlock Bypass command is required prior to Unlock
Bypass Program command.
3. Shaded cells indicate read cycles. All others are write
cycles.
11. Unlock Bypass Reset command is required to return to
read mode when device is in unlock bypass mode.
4. During unlock and command cycles, when lower address
bits are 555 or 2AA as shown in table, address bits above
A11 and data bits above DQ7 are don’t care.
12. System may read and program in non-erasing sectors, or
enter autoselect mode, when in Erase Suspend mode.
Erase Suspend command is valid only during a sector
erase operation.
5. No unlock or command cycles required when device is in
read mode.
6. Reset command is required to return to read mode (or to
erase-suspend-read mode if previously in Erase Suspend)
when device is in autoselect mode, or if DQ5 goes high
while device is providing status information.
13. Erase Resume command is valid only during Erase
Suspend mode.
14. Command is valid when device is ready to read array data
or when device is in autoselect mode.
7. Fourth cycle of the autoselect command sequence is a
read cycle. Data bits DQ15–DQ8 are don’t care. See
Autoselect Command Sequence section for more
information.
8. Device ID must be read in three cycles.
April 21, 2004 S29AL016M_00A4
S29AL016M
32
Table 11. Command Definitions (x8 Mode, BYTE# = VIL)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
6
RA
RD
F0
XXX
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
90
90
X00
X02
01
C4
Device ID, Top Boot (Note 8)
Device ID, Bottom Boot (Note
8)
6
4
4
AAA
AAA
AAA
AA
AA
AA
555
555
555
55
55
55
AAA
AAA
AAA
90
90
90
X02
X44
49
SecSi™ Sector Factory Protect
(Note 9)
00/01
Sector Group Protect Verify
(Note 9)
(SA)X04
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
2
2
6
6
1
1
1
AAA
AAA
AAA
AAA
XXX
XXX
AAA
AAA
XXX
XXX
AA
AA
AA
AA
AA
A0
90
AA
AA
B0
30
98
555
555
555
555
PA
55
55
55
55
PD
00
55
55
AAA
AAA
AAA
AAA
88
90
A0
20
XXX
PA
00
PD
Unlock Bypass
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
Chip Erase
XXX
555
555
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Program/Erase Suspend (Note 12)
Program/Erase Resume (Note 13)
CFI Query (Note 14)
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A19–A15 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
10. Unlock Bypass command is required prior to Unlock
Bypass Program command.
2. All values are in hexadecimal.
11. Unlock Bypass Reset command is required to return to
read mode when device is in unlock bypass mode.
3. Shaded cells indicate read cycles. All others are write
cycles.
12. System may read and program in non-erasing sectors, or
enter autoselect mode, when in Erase Suspend mode.
Erase Suspend command is valid only during a sector
erase operation.
4. During unlock and command cycles, when lower address
bits are 555 or AAA as shown in table, address bits above
A11 are don’t care.
5. No unlock or command cycles required when device is in
read mode.
13. Erase Resume command is valid only during Erase
Suspend mode.
6. Reset command is required to return to read mode (or to
erase-suspend-read mode if previously in Erase Suspend)
when device is in autoselect mode, or if DQ5 goes high
while device is providing status information.
14. Command is valid when device is ready to read array data
or when device is in autoselect mode.
7. Fourth cycle of autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See Autoselect
Command Sequence section or more information.
8. Device ID must be read in three cycles.
9. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
33
S29AL016M
S29AL016M_00A4 April 21, 2004
Write Operation Status
The device provides several bits to determine the status of a write operation:
DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 12 and the following subsections
describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method
for determining whether a program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Algorithm is in progress or completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final WE# pulse in the program
or erase command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading array data.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to
the complement/true datum output described for the Embedded Program algo-
rithm: the erase function changes all the bits in a sector to “1”; prior to this, the
device outputs the “complement,” or “0.” The system must provide an address
within any of the sectors selected for erasure to read valid status information on
DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
device returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the complement to true data,
it can read valid data at DQ7–DQ0 on the following read cycles. This is because
DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is
asserted low. Figure 19, Data# Polling Timings (During Embedded Algorithms),
in the “AC Characteristics” section illustrates this.
Table 12 shows the outputs for Data# Polling on DQ7. Figure 7 shows the Data#
Polling algorithm.
April 21, 2004 S29AL016M_00A4
S29AL016M
34
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid
address is an address within any sector selected for erasure. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simulta-
neously with DQ5.
Figure 7. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Em-
bedded Algorithm is in progress or complete. The RY/BY# status is valid after the
rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an
open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to V
.
CC
35
S29AL016M
S29AL016M_00A4 April 21, 2004
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Table 12 shows the outputs for RY/BY#. Figures 13, 14, 17 and 18 show RY/BY#
for read, reset, program, and erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. (The system may use either OE# or CE#
to control the read cycles.) When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table 12 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit
algorithm in flowchart form, and the section “Reading Toggle Bits DQ6/DQ2” ex-
plains the algorithm. Figure 20 in the “AC Characteristics” section shows the
toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 12 to compare outputs for DQ2 and DQ6.
April 21, 2004 S29AL016M_00A4
S29AL016M
36
Figure 8 shows the toggle bit algorithm in flowchart form, and the section “Read-
ing Toggle Bits DQ6/DQ2” explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the
differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8 for the following discussion. Whenever the system initially be-
gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note
and store the value of the toggle bit after the first read. After the second read,
the system would compare the new value of the toggle bit with the first. If the
toggle bit is not toggling, the device has completed the program or erase op-
eration. The system can read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of Figure 8).
37
S29AL016M
S29AL016M_00A4 April 21, 2004
START
Read DQ7–DQ0
(Note 1)
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
(Notes
1, 2)
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Figure 8. Toggle Bit Algorithm
Notes:
1. Read toggle bit twice to determine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified inter-
nal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was not successfully
completed.
The DQ5 failure condition may appear if the system tries to program a “1” to a
location that is previously programmed to “0.” Only an erase operation can
April 21, 2004 S29AL016M_00A4
S29AL016M
38
change a “0” back to a “1.” Under this condition, the device halts the opera-
tion, and when the operation has exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the reset command to return
the device to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not an erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches from “0” to “1.” The system
may ignore DQ3 if the system can guarantee that the time between additional
sector erase commands will always be less than 50 µs. See also the “Sector
Erase Command Sequence” section.
After the sector erase command sequence is written, the system should read the
status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally
controlled erase cycle has begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is complete. If DQ3 is “0”, the device
will accept additional sector erase commands. To ensure the command has been
accepted, the system software should check the status of DQ3 prior to and fol-
lowing each subsequent sector erase command. If DQ3 is high on the second
status check, the last command might not have been accepted. Table 12 shows
the outputs for DQ3.
Table 12. Write Operation Status
DQ7
(Note
2)
DQ5
(Note 1)
DQ2
(Note 2)
Operation
DQ6
DQ3
N/A
1
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Program-
Program-
Suspend Read
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Invalid (not allowed)
Data
1
1
1
Program
Suspend
Mode
Suspended Sector
Non-Program
Suspended Sector
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Erase
Suspend Reading within Non-Erase Suspended
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing
limits. See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
39
S29AL016M
S29AL016M_00A4 April 21, 2004
Absolute Maximum Ratings
Storage Temperature, Plastic Packages. . . . . . . . . . . . . . . . .–65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . .–65°C to +125°C
Voltage with Respect to Ground
V
(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
CC
A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1). . . . . . . . . . . . . . . . . . . . . –0.5 V to V +0.5 V
CC
Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions,
input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure
9. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns.
See Figure 10.
2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage
transitions, A9, OE#, and RESET# may overshoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 9. Maximum DC input voltage on pin A9 is +12.5 V which
may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this data sheet is not implied. Exposure of the device to absolute maximum rating con-
ditions for extended periods may affect device reliability.
20 ns
20 ns
20 ns
VCC
+2.0 V
+0.8 V
VCC
–0.5 V
–2.0 V
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 9. Maximum Negative
Overshoot Waveform
Figure 10. Maximum Positive
Overshoot Waveform
Operating Ranges
Industrial (I) Devices
Ambient Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
A
V
Supply Voltages
CC
CC
CC
V
V
for full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7 V to 3.6 V
for regulated range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.0 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is
guaranteed.
April 21, 2004 S29AL016M_00A4
S29AL016M
40
DC Characteristics
CMOS Compatible
Parameter
Description
Test Conditions
VIN = VSS to VCC
Min
Typ
Max
Unit
,
ILI
Input Load Current
1.0
µA
VCC = VCC max
ILIT
A9 Input Load Current
Reset Leakage Current
VCC = VCC max; A9 = 12.5 V
35
35
µA
µA
I
V
= V
; RESET# = 12.5 V
CC max
LR
CC
VOUT = VSS to VCC
VCC = VCC max
,
ILO
Output Leakage Current
1.0
µA
10 MHz
5 MHz
1 MHz
10 MHz
5 MHz
1 MHz
35
15
50
20
10
50
20
10
CE# = VIL, OE#= VIH,
Byte Mode
2.5
35
mA
VCC Active Read Current
(Notes 1, 2)
ICC1
CE# = VIL, OE#= VIH,
Word Mode
15
2.5
VCC Active Write Current
(Notes 2, 3, 5)
ICC2
ICC3
ICC4
CE# = VIL, OE# = VIH
40
0.4
0.8
60
5
mA
µA
µA
VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC 0.3 V
VCC Standby Current During Reset
RESET# = VSS 0.3 V
(Notes 2, 4)
5
Automatic Sleep Mode
(Notes 2, 4, 6)
VIH = VCC 0.3 V;
-0.1 < VIL 0.3 V
ICC5
0.4
5
µA
≤
VIL
Input Low Voltage (Notes 6, 7)
Input High Voltage (Notes 6, 7)
-0.5
0.6
V
V
VIH
0.7 VCC
VCC + 0.5
Voltage for Autoselect and
Temporary Sector Unprotect
VID
VCC = 3.3 V
11.5
12.5
0.45
V
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
IOH = -2.0 mA, VCC = VCC min
IOH = -100 µA, VCC = VCC min
V
V
VOH1
VOH2
VLKO
0.85 x VCC
VCC–0.4
2.3
Output High Voltage
Low VCC Lock-Out Voltage (Note 4)
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum I specifications are tested with V = V max.
CC
CC
CC
3. I active while Embedded Erase or Embedded Program is in progress.
CC
4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA.
5. Automatic sleep mode enables the low power mode when addresses remain stable for t
6. Not 100% tested.
+ 30 ns.
ACC
7. V voltage requirements.
CC
41
S29AL016M
S29AL016M_00A4 April 21, 2004
Test Conditions
Table 13. Test Specifications
3.3 V
Test Condition
Output Load
90, 100
Unit
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
6.2 kΩ
L
0.0 or VCC
Input timing measurement
reference levels
0.5 VCC
0.5 VCC
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
VCC
0.5 VCC
0.5 VCC
Input
Measurement Level
Output
0.0 V
Figure 12. Input Waveforms and Measurement Levels
April 21, 2004 S29AL016M_00A4
S29AL016M
42
AC Characteristics
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
Min
90
100
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
90
100
ns
CE# = VIL
OE# = VIL
tAVQV
tACC
Address to Output Delay
Max
90
90
100
100
ns
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
OE# = VIL
Max
Max
Max
Max
Min
ns
ns
ns
ns
ns
Output Enable to Output Delay
25
20
20
0
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Read
Output Enable
Hold Time (Note 1)
tOEH
Toggle and
Data# Polling
Min
Min
10
0
ns
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
tAXQX
tOH
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 13 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operations Timings
43
S29AL016M
S29AL016M_00A4 April 21, 2004
AC Characteristics
Hardware Reset (RESET#)
Parameter
Test
JEDEC
Std
Description
Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms) to
Read or Write (See Note)
tREADY
Max
Max
20
µs
RESET# Pin Low (NOT During Embedded Algorithms)
to Read or Write (See Note)
tREADY
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
RESET# High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 14. RESET# Timings
April 21, 2004 S29AL016M_00A4
S29AL016M
44
AC Characteristics
Erase/Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
Description
90
100
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
90
100
tAVWL
tWLAX
tDVWH
tWHDX
0
45
35
0
ns
tAH
ns
tDS
ns
tDH
tOES
Data Hold Time
ns
Output Enable Setup Time
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Min
Min
Max
Max
0
0
ns
ns
ns
ns
µs
sec
µs
ns
ns
µs
CE# Hold Time
tWLWH
tWHWL
tWHWH1
tWHWH2
tWP
Write Pulse Width
35
30
18
1
tWPH
tWHWH1
tWHWH2
tVCS
Write Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
VCC Setup Time (Note 1)
Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
Program Valid Before Status Polling (Note 3)
50
0
tRB
tBUSY
tPOLL
90
100
4
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once
programming has resumed (that is, the program resume command has been written). If the suspend command was issued
after tPOLL, status data is available immediately after programming has resumed. See Figure 15.
45
S29AL016M
S29AL016M_00A4 April 21, 2004
AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tPOLL
tWP
WE#
Data
tWPH
tWHWH1
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 15. Program Operation Timings
April 21, 2004 S29AL016M_00A4
S29AL016M
46
AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
Figure 16. Chip/Sector Erase Operation Timings
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AC Characteristics
tRC
VA
Addresses
VA
VA
tACC
tCE
tPOLL
CE#
tCH
tOE
OE#
tOEH
tDF
tOH
WE#
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 17. Data# Polling Timings
(During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 18. Toggle Bit Timings
(During Embedded Algorithms)
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AC Characteristics
Enter
Erase
Suspend
Enter Erase
Suspend Program
Embedded
Erase
Resume
Erasing
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 19. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Note: Not 100% tested.
12 V
RESET#
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 20. Temporary Sector Unprotect/Timing Diagram
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S29AL016M
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AC Characteristics
V
ID
V
IH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Protect/Unprotect
Verify
40h
Data
60h
60h
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 21. Sector Protect/Unprotect Timing Diagram
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AC Characteristics
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
tAVAV
tAVEL
Std
tWC
tAS
Description
90
100
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
90
100
0
45
35
0
ns
tELAX
tDVEH
tEHDX
tAH
ns
tDS
tDH
tOES
ns
Data Hold Time
ns
Output Enable Setup Time
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tWS
tWH
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
Min
0
0
ns
ns
ns
ns
µs
sec
ns
WE# Hold Time
tCP
CE# Pulse Width
35
25
18
0.7
50
tEHEL
tCPH
CE# Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
tWHWH1
tWHWH2
tWHWH1
tWHWH2
tRH
Program Valid Before Status Polling
(Note 3)
tPOLL
Max
4
µs
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once
programming has resumed (that is, the program resume command has been written). If the suspend command was issued
after tPOLL, status data is available immediately after programming has resumed. See Figure 22.
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AC Characteristics
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
OE#
tPOLL
tGHEL
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tDS
tBUSY
tDH
DQ7#,
DQ15
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to
the device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
Figure 22. Alternate CE# Controlled Write Operation Timings
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Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
0.7
32
18
18
36
19
7.5
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
s
Byte Programming Time
Word Programming Time
µs
µs
s
Excludes system level
overhead (Note 5)
Byte Mode
Word Mode
Chip Programming Time
(Note 3)
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 10,000 cycles, checkerboard data
pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Tables 2–3 for further information on command definitions.
TSOP Pin and BGA Package Capacitance
Unit
pF
pF
pF
pF
pF
pF
Parameter Symbol
Parameter Description
Test Setup
Typ
6
Max
7.5
5.0
12
TSOP
BGA
CIN
Input Capacitance
VIN = 0
4.2
8.5
5.4
7.5
3.9
TSOP
BGA
COUT
Output Capacitance
VOUT = 0
VIN = 0
6.5
9
TSOP
BGA
CIN2
Control Pin Capacitance
4.7
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
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Physical Dimensions
TS 048—48-Pin Standard TSOP
Dwg rev AA; 10/99
Note: BSC is an ANSI standard for Basic Space Centering.
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Physical Dimensions
TSR048—48-Pin Reverse TSOP
Dwg rev AA; 10/99
Note: BSC is an ANSI standard for Basic Space Centering.
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Physical Dimensions
FBA048—48-Ball Fine-Pitch Ball Grid Array (BGA)
6 x 8 mm Package
Dwg rev AF; 10/99
Note: BSC is an ANSI standard for Basic Space Centering.
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Physical Dimensions
LAA064—64-Ball Fortified Ball Grid Array (BGA)
13 x 11 mm Package
Note: BSC is an ANSI standard for Basic Space Centering.
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S29AL016M
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Revision Summary
Revision A (January 30, 2004)
Initial release.
Revision A + 1 (February 20, 2004)
Product Selector Guide
Removed regulated voltage range for the Speed Option.
Ordering Information
Included explanations of the package markings for TSOP and BGA packages.
Word/Byte Program Sequence
Added guidance for programming the same address multiple times without inter-
vening erases.
Operating Ranges
Removed reference to regulated voltage ranges.
AC Characteristics (Read Options table)
The timing specifications for t
and t
were tightened to 20 ns.
EHQZ
GHQZ
Erase and Programming Performance table
Added the byte programming time specification.
Revision A + 2 (February 25, 2004)
Product Selector Guide
Added Tray and 13” Tape and Reel to the Packing Type.
Removed “2” from end of package marking.
Revision A + 3 (March 24, 2004)
Table 7, “System Interface String”
Changed description to RFU for 23h word/46h byte mode.
Added additional information to description for 24h word/28h byte mode.
Removed references to V in note.
CC
CMOS Compatible
Updated the Min and Max for V and the Min for V
IL
IH.
Corrected test conditions for I
CC5.
Figure 12, “Input Waveforms and Measurement Levels”
Added V to figure.
CC
BYTE# Timings for Read Operations and BYTE# Timings for Write
Operations
Removed figures.
Erase/Program Operations
Updated t
100 ns speed option to have 100 ns Min.
BUSY
Alternate CE# Controlled Erase/Program Operations
Added t parameter to table.
RH
Connection Diagrams
Deleted the Reverse TSOP diagram.
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Revision A + 4 (April 19, 2004)
Product Selector Guide
Added regulated voltage range for the Speed Option.
Operating Ranges
Added regulated voltage ranges.
Erase/Program Operations Table
Changed t
from min to max.
BUSY
Erase and Programming Performance Table
Added cycling conditions to Note 1 and Note 2.
Trademarks and Notice
The contents of this document are subject to change without notice.This document may contain information on a Spansion product under development by
FASL LLC. FASL LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is
without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of
third-party rights, or any other warranty, express, implied, or statutory. FASL LLC assumes no liability for any damages of any kind arising out of the use of
the information in this document.
Copyright © 2004 FASL LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL
LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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April 21, 2004 S29AL016M_00A4
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60
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16 MEGABIT (2M X 8 BIT / I M X 16 BIT) 3.0 VOLT ONLY BOOT SECTOR FLASH MEMORY
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