S29CD032G0JQAM110 [SPANSION]
32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O; 32兆位（ 1M ×32位） ， 16兆位（ 512K ×32位）， 2.5伏只突发模式，双启动，同步读/写快闪记忆体与VersatileI / O
| 型号： | S29CD032G0JQAM110 |
| 厂家： | 
SPANSION |
| 描述： | 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| 文件： | 总87页 (文件大小：2161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S29CD-G Flash Family
S29CD032G, S29CD016G
32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit)
2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/
Write Flash Memory with VersatileI/O™ featuring 170 nm
Process Technology
PRELIMINARY
Data Sheet
Notice to Readers: This document states the current technical specifications
regarding the Spansion product(s) described herein. The Preliminary status of
this document indicates that product qualification has been completed, and
that initial production has begun. Due to the phases of the manufacturing
process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical
specifications.
Note: This document supercedes datasheet information for the S29CD016G revision A4, and
S29CD032G revision B0. The S29CD-G device is the factory-recommended migration path.
Please refer to specifications and ordering information found in this document.
Publication Number S29CD-G_00 Revision B Amendment 0 Issue Date November 14, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
P r e l i m i n a r y
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, includ-
ing development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to
highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more spe-
cific products, but has not committed any design to production. Information presented in a
document with this designation is likely to change, and in some cases, development on the prod-
uct may discontinue. Spansion LLC therefore places the following conditions upon Advance
Information content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product
life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these as-
pects of production under consideration. Spansion places the following conditions upon
Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-
tions due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance In-
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or VIO range. Changes
may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
ii
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
S29CD-G Flash Family
S29CD032G, S29CD016G
32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit)
2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/
Write Flash Memory with VersatileI/O™ featuring 170 nm
Process Technology
PRELIMINARY
Data Sheet
Distinctive Characteristics
— Standby mode: CMOS: 60 µA max
1 million write cycles per sector typical
20 year data retention typical
VersatileI/O™ control
— Generates data output voltages and tolerates data
input voltages as determined by the voltage on the
Architecture Advantages
Simultaneous Read/Write operations
— Read data from one bank while executing erase/
program functions in other bank
— Zero latency between read and write operations
— Two bank architecture: large bank/small bank
75%/25%
V
IO pin
— 1.65 V to 3.60 V compatible I/O signals
User-Defined x32 Data Bus
Dual Boot Block
Software Features
— Top and bottom boot sectors in the same device
Flexible sector architecture
Persistent Sector Protection
— Locks combinations of individual sectors and sector
groups to prevent program or erase operations
within that sector (requires only VCC levels)
Password Sector Protection
— Locks combinations of individual sectors and sector
groups to prevent program or erase operations
within that sector using a user-definable 64-bit
password
Supports Common Flash Interface (CFI)
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
Data# Polling and toggle bits
— CD032G: Eight 2K Double Word, Sixty-two 16K
Double Word, and Eight 2K Double Word sectors
— CD016G: Eight 2K Double Word, Thirty-two 16K
Double Word, and Eight 2K Double Word sectors
Secured Silicon Sector (256 Bytes)
— Factory locked and identifiable: 16 bytes for secure,
random factory Electronic Serial Number; Also know
as Electronic Marking
Manufactured on 170 nm Process Technology
Programmable Burst interface
— Interfaces to any high performance processor
— Linear Burst Read Operation: 2, 4, and 8 double
word linear burst with or without wrap around
Program Operation
— Provides a software method of detecting program or
erase operation completion
— Performs synchronous and asynchronous write
operations of burst configuration register settings
independently
Hardware Features
Program Suspend/Resume & Erase Suspend/
Resume
Single power supply operation
— Optimized for 2.5 to 2.75 volt read, erase, and
program operations
Compatibility with JEDEC standards (JC42.4)
— Software compatible with single-power supply Flash
— Backward-compatible with AMD/Fujitsu Am29LV/
MBM29LV and Am29F/MBM29F flash memories
— Suspends program or erase operations to allow
reading, programming, or erasing in same bank
Hardware Reset (RESET#), Ready/Busy# (RY/
BY#), and Write Protect (WP#) inputs
ACC input
— Accelerates programming time for higher throughput
during system production
Package options
— 80-pin PQFP
— 80-ball Fortified BGA
— Pb-free package option also available
— Known Good Die
Performance Characteristics
High performance read access
— Initial/random access times of 48 ns (32 Mb) and 54
ns (16 Mb)
— Burst access times of 7.5 ns (32 Mb) or 9 ns (16Mb)
Ultra low power consumption
— Burst Mode Read: 90 mA @ 75 MHz max
— Program/Erase: 50 mA max
Publication Number S29CD-G_00 Revision B Amendment 0 Issue Date November 14, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
P r e l i m i n a r y
General Description
The S29CD-G Flash Family is a burst mode, Dual Boot, Simultaneous Read/Write family of Flash
Memory with VersatileI/O™ manufactured on 170 nm Process Technology.
The S29CD032G is a 32 Megabit, 2.6 Volt-only (2.50 V - 2.75 V) single power supply burst mode
flash memory device that can be configured for 1,048,576 double words.
The S29CD016G is a 16 Megabit, 2.6 Volt-only (2.50 V - 2.75 V) single power supply burst mode
flash memory device that can be configured for 524,288 double words.
To eliminate bus contention, each device has separate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls. Additional control inputs are required for synchronous burst oper-
ations: Load Burst Address Valid (ADV#), and Clock (CLK).
Each device requires only a single 2.6 Volt-only (2.50 V – 2.75 V) for both read and write func-
tions. A 12.0-volt VPP is not required for program or erase operations, although an acceleration
pin is available if faster programming performance is required.
The device is entirely command set compatible with the JEDEC single-power-supply Flash stan-
dard. The software command set is compatible with the command sets of the 5 V Am29F or
MBM29F and 3 V Am29LV or MBM29LV Flash families. Commands are written to the command
register using standard microprocessor write timing. Register contents serve as inputs to an in-
ternal state-machine that controls the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the programming and erase operations. Reading
data out of the device is similar to reading from other Flash or EPROM devices.
The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles
to program data instead of four.
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the
memory space into two banks. The device can begin programming or erasing in one bank, and
then simultaneously read from the other bank, with zero latency. This releases the system from
waiting for the completion of program or erase operations. See Simultaneous Read/Write Opera-
tions Overview.
The device provides a 256-byte Secured Silicon Sector that contains Electronic Marking Infor-
mation for easy device traceability.
In addition, the device features several levels of sector protection, which can disable both the pro-
gram and erase operations in certain sectors or sector groups: Persistent Sector Protection is
a command sector protection method that replaces the old 12 V controlled protection method;
Password Sector Protection is a highly sophisticated protection method that requires a pass-
word before changes to certain sectors or sector groups are permitted; WP# Hardware
Protection prevents program or erase in the two outermost 8 Kbytes sectors of the larger bank.
The device defaults to the Persistent Sector Protection mode. The customer must then choose if
the Standard or Password Protection method is most desirable. The WP# Hardware Protection
feature is always available, independent of the other protection method chosen.
The VersatileI/O™ (VCCQ) feature allows the output voltage generated on the device to be de-
termined based on the VIO level. This feature allows this device to operate in the 1.8 V I/O
environment, driving and receiving signals to and from other 1.8 V devices on the same bus.
The host system can detect whether a program or erase operation is complete by observing the
RY/BY# pin, by reading the DQ7 (Data# Polling), or DQ6 (toggle) status bits. After a program
or erase cycle is completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without
affecting the data contents of other sectors. The device is fully erased when shipped from the
factory.
2
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Hardware data protection measures include a low VCC detector that automatically inhibits write
operations during power transitions. The password and software sector protection feature
disables both program and erase operations in any combination of sectors of memory. This can
be achieved in-system at VCC level.
The Program/Erase Suspend/Erase Resume feature enables the user to put erase on hold
for any period of time to read data from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state
machine to reading array data.
The device offers two power-saving features. When addresses are stable for a specified amount
of time, the device enters the automatic sleep mode. The system can also place the device into
the standby mode. Power consumption is greatly reduced in both these modes.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effectiveness. The device electrically erases all
bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed
using hot electron injection.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
3
P r e l i m i n a r y
Table of Contents
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Diagram of Simultaneous Read/Write Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PRQ080–80-Lead Plastic Quad Flat Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Special Package Handling Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
LAA080–80-ball Fortified Ball Grid Array (13 x 11 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
S29CD032G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
S29CD016G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Memory Map and Sector Protect Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Device Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VersatileI/O™ (VIO) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Requirements for Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Simultaneous Read/Write Operations Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Overview ........................................................................................................................................................................................24
Program/Erase Suspend and Simultaneous Operation .....................................................................................................24
Common Flash Interface (CFI) and Password Program/Verify and Simultaneous Operation .............................24
Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Accelerated Program and Erase Operations .......................................................................................................................25
Autoselect Functions ...................................................................................................................................................................25
Automatic Sleep Mode (ASM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Standby Mode ................................................................................................................................................................................25
RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Asynchronous Read Operation (Non-Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Synchronous (Burst) Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Linear Burst Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CE# Control in Linear Mode .................................................................................................................................................. 28
ADV# Control In Linear Mode .............................................................................................................................................. 28
RESET# Control in Linear Mode ............................................................................................................................................ 29
OE# Control in Linear Mode .................................................................................................................................................. 29
IND/WAIT# Operation in Linear Mode .............................................................................................................................. 29
Burst Access Timing Control ...................................................................................................................................................30
Initial Burst Access Delay Control .........................................................................................................................................30
Burst CLK Edge Data Delivery ................................................................................................................................................30
Burst Data Hold Control ...........................................................................................................................................................30
Asserting RESET# During A Burst Access ............................................................................................................................31
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Initial Access Delay Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Sector and Sector Groups .........................................................................................................................................................33
Persistent Sector Protection ....................................................................................................................................................33
Password Sector Protection .....................................................................................................................................................33
WP# Hardware Protection ......................................................................................................................................................33
Persistent Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Persistent Protection Bit (PPB) ................................................................................................................................................34
Persistent Protection Bit Lock (PPB Lock) ..........................................................................................................................34
Dynamic Protection Bit (DYB) ................................................................................................................................................34
Persistent Sector Protection Mode Locking Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Password Protection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Password and Password Mode Locking Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
64-bit Password ............................................................................................................................................................................36
Write Protect (WP#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Secured Silicon OTP Sector and Simultaneous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Persistent Protection Bit Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Low VCC Write Inhibit ...............................................................................................................................................................37
Write Pulse Glitch Protection ...................................................................................................................................................38
Logical Inhibit .................................................................................................................................................................................38
Power-Up Write Inhibit .............................................................................................................................................................38
VCC and VIO Power-up And Power-down Sequencing ....................................................................................................38
Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Reading Array Data in Non-burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Reading Array Data in Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Autoselect Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Accelerated Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Unlock Bypass Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Unlock Bypass Entry Command ..............................................................................................................................................45
Unlock Bypass Program Command ........................................................................................................................................45
Unlock Bypass Chip Erase Command .................................................................................................................................. 46
Unlock Bypass CFI Command ................................................................................................................................................. 46
Unlock Bypass Reset Command ............................................................................................................................................. 46
Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Sector Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Sector Erase and Program Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Sector Erase and Program Suspend Operation Mechanics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Sector Erase and Program Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Configuration Register Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Configuration Register Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Common Flash Interface (CFI) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Password Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Password Verify Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Password Protection Mode Locking Bit Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Persistent Sector Protection Mode Locking Bit Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
PPB Lock Bit Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
DYB Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Password Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
PPB Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
All PPB Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DYB Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PPB Lock Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DYB Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PPB Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PPB Lock Bit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Non-volatile Protection Bit Program And Erase Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
5
P r e l i m i n a r y
DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Industrial (I) Devices ...................................................................................................................................................................63
Extended (E) Devices ..................................................................................................................................................................63
V
V
CC Supply Voltages ....................................................................................................................................................................63
IO Supply Voltages .....................................................................................................................................................................63
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Zero Power Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
VCC and VIO Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Asynchronous Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Burst Mode Read for 32 Mb & 16 Mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Alternate CE# Controlled Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
PQFP and Fortified BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Tables
Table 1. 32 Mb Memory Map and Sector Protect Groups for Ordering Option 00, Top Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2. 32 Mb Memory Map and Sector Protect Groups for Ordering Option 01, Bottom Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3. 16 Mb, Memory Map and Sector Protect Groups for Ordering Option 00, Top Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 4. 16 Mb, Memory Map and Sector Protect Groups for Ordering Option 00, Bottom Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 5. Device Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 6. Allowable Conditions for Simultaneous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 7. S29CD-G Flash Family Autoselect Codes (High Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 8. 32- Bit Linear and Burst Data Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 9. Valid Configuration Register Bit Definition for IND/WAIT#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 10. Burst Initial Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 11. Configuration Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 12. Configuration Register After Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 13. Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 14. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 15. CFI System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 16. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 17. CFI Primary Vendor-Specific Extended Query. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18. Allowed Operations During Erase/Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 19. Memory Array Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 20. Sector Protection Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 21. Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 22. Test Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
7
P r e l i m i n a r y
Figures
Figure 1.
Asynchronous Read Operation............................................................................................................................................................................ 27
End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation ...........................................................................29
Initial Burst Delay Control.....................................................................................................................................................................................30
Program Operation.................................................................................................................................................................................................. 45
Erase Operation ........................................................................................................................................................................................................48
Data# Polling Algorithm.......................................................................................................................................................................................... 57
Toggle Bit Algorithm................................................................................................................................................................................................60
Maximum Negative Overshoot Waveform ......................................................................................................................................................62
Maximum Positive Overshoot Waveform.........................................................................................................................................................62
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
I
Current vs. Time (Showing Active and Automatic Sleep Currents)................................................................................................ 65
CC1
Typical I
vs. Frequency...................................................................................................................................................................................... 65
CC1
Test Setup....................................................................................................................................................................................................................66
Input Waveforms and Measurement Levels .....................................................................................................................................................66
V
and V Power-up Diagram.......................................................................................................................................................................... 67
IO
CC
Conventional Read Operations Timings............................................................................................................................................................68
Burst Mode Read.......................................................................................................................................................................................................70
Asynchronous Command Write Timing............................................................................................................................................................70
Synchronous Command Write/Read Timing..................................................................................................................................................... 71
RESET# Timings......................................................................................................................................................................................................... 72
WP# Timing................................................................................................................................................................................................................ 72
Chip/Sector Erase Operation Timings................................................................................................................................................................ 74
Back-to-Back Cycle Timings .................................................................................................................................................................................. 74
Data# Polling Timings (During Embedded Algorithms)................................................................................................................................ 75
Toggle Bit Timings (During Embedded Algorithms)....................................................................................................................................... 75
DQ2 vs. DQ6 for Erase/Erase Suspend Operations...................................................................................................................................... 76
Synchronous Data Polling Timing/Toggle Bit Timings.................................................................................................................................... 76
Sector Protect/Unprotect Timing Diagram ...................................................................................................................................................... 77
Alternate CE# Controlled Write Operation Timings...................................................................................................................................78
8
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Product Selector Guide
S29CD-G Flash Family
(S29CD032G, S29CD016G)
Part Number
V
V
= 2.5 – 2.75 V
= 1.65 – 2.75 V
CC
IO
Standard Voltage Range:
Synchronous/Burst or Asynchronous
0R
0P
(66 MHz)
0M
(56 MHz)
0J
Speed Option (Clock Rate)
(75 MHz)
(32 Mb Only)
(40 MHz)
Max Initial/Asynchronous Access Time, ns (t
Max Burst Access Delay (ns)
)
48
54
64
67
17
ACC
9 FBGA/
9.5 PQFP
10 FBGA/
10 PQFP
7.5 FBGA
Max Clock Rate (MHz)
75
3
66
3
56
3
40
2
Min Initial Clock Delay (clock cycles)
Max CE# Access, ns (t
)
52
58
20
69
71
28
CE
Max OE# Access, ns (t
)
OE
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
9
P r e l i m i n a r y
Ordering Information
The order number (Valid Combination) is formed by the following:
S29CD032G 0J
F
A
I
0
0
0
Packing Type
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
Additional Ordering Options (16th Character) Top or
Bottom Boot
0
1
=
=
Top Boot
Bottom Boot
Additional Ordering Options (15th Character) Mask
Revision
0
1
2
=
=
=
A
A1 (16 Mb only) with 7E, 36, 01/00 Autoselect ID
A1 (16 Mb only) with 7E, 08, 01/00 Autoselect ID
Temperature Range and Quality Grade
A
=
=
=
=
Industrial (–40°C to +85°C), GT grade
I
Industrial (–40°C to +85°C)
M
N
Extended (–40°C to +125°C), GT grade
Extended (–40°C to +125°C)
Material Set
A
F
=
=
Standard
Pb-free Option
Package Type
Q
F
=
=
Plastic Quad Flat Package (PQFP)
Fortified Ball Grid Array, 1.0 mm pitch package
Clock Frequency
0J
=
=
=
=
40 MHz
56 MHz
66 MHz
75 MHz (32 Mb Only)
0M
0P
0R
Device Number/description
S29CD032G/S29CD016G
32 or 16 Megabit (1 M or 512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode,
Dual Boot, Simultaneous Read/Write Flash Memory
Manufactured on 110 nm floating gate technology
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of
specific valid combinations and to check on newly released combinations.
Valid Combinations
QAI, QFI,
QAN, QFN
S29CD032G
S29CD016G
0R (32 MB Only), 0P, 0M, 0J
00, 01
FAI, FFI, FAN, FFN
1. The ordering part number that appears on BGA packages omits the leading “S29”.
2. Contact your local sales representative for GT grade options.
3. Refer to the KGD data sheet supplement for die/wafer sales.
10
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Block Diagram
VCC
VSS
DQmax–DQ0
Amax–A0
Erase Voltage
Generator
Input/Output
Buffers
VIO
WE#
RESET#
ACC
State
Control
WP#
WORD#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
CE#
OE#
Y-Decoder
Y-Gating
VCC
Detector
Timer
Cell Matrix
X-Decoder
Burst
State
Control
Burst
Address
Counter
ADV#
CLK
IND/
WAIT#
Amax–A0
DQmax–DQ0
Amax–A0
Note: Address bus is A19–A0 for 32 Mb device, A18–A0 for 16 Mb device. Data bus is D31–DQ0.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
11
P r e l i m i n a r y
Block Diagram of Simultaneous Read/Write Circuit
OE#
V
V
CC
SS
Upper Bank Address
A –A0
max
Upper Bank
X-Decoder
A –A0
max
STATE
CONTROL
&
RESET#
WE#
Status
DQ –DQ0
max
COMMAND
REGISTER
CE#
Control
ADV#
DQ –DQ0
max
X-Decoder
Lower Bank
A –A0
max
Lower Bank Address
Note: Address bus is A19–A0 for 32 Mb device, A18–A0 for 16 Mb device. Data bus is D31–DQ0.
12
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Connection Diagrams
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
DQ16
DQ17
DQ18
DQ19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ15
DQ14
DQ13
DQ12
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V
V
V
CCQ
SS
V
SS
CCQ
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
80-Pin PQFP
V
V
V
CCQ
SS
V
SS
CCQ
DQ28
DQ29
DQ30
DQ31
MCH
A0
DQ3
DQ2
DQ1
DQ0
A19 (32 Mb) / NC (16 Mb)
A18
A17
A16
A1
A2
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Note: On 16 Mb device, pin 44 (A19) is NC.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
13
P r e l i m i n a r y
Physical Dimensions
PRQ080–80-Lead Plastic Quad Flat Package
6
D
3
D1
0.20 MIN. FLAT SHOULDER
PIN S
D3
PIN R
7˚
TYP.
0˚MIN.
0.30 0.05 R
PIN ONE I.D.
A
GAGE
PLANE
0.25
7˚
TYP.
L
E3
3
ccc
C
b
4
0˚-7˚
E1
6
-A-
-B-
aaa
M
A B S D S
C
E
DETAIL X
SEE NOTE 3
b
PIN P
-D-
SEE DETAIL X
PIN Q
c
e
BASIC
SECTION S-S
2
S
A2
A
-A-
-C-
A1
SEATING PLANE
S
NOTES:
PACKAGE
PQR 080
JEDEC
MO-108(B)CB-1
NOTES
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO
ANSI Y14.5M-1982.
SYMBOL
MIN
--
NOM
--
MAX
3.35
--
2. DATUM PLANE -A- IS LOCATED AT THE MOLD PARTING LINE
AND IS COINCIDENT WITH THE BOTTOM OF THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY.
A
A1
A2
b
0.25
2.70
0.30
0.15
17.00
13.90
--
--
2.80
--
2.90
0.45
0.23
17.40
14.10
--
3. DIMENSIONS "D1" AND "E1" DO NOT INCLUD MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE.
SEE NOTE 4
DIMENSIONS "D1" AND "E1" INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT DATUM PLANE -A-
c
--
D
17.20
14.00
12.0
0.80
23.20
20.00
18.40
0.20
0.10
0.88
24
4. DIMENSION "B" DOES NOT INCLUDE DAMBAR PROTRUSION.
5. CONTROLLING DIMENSIONS: MILLIMETER.
D1
D3
e
SEE NOTE 3
REFERENCE
6. DIMENSIONS "D" AND "E" ARE MEASURED FROM BOTH
INNERMOST AND OUTERMOST POINTS.
--
--
BASIC, SEE NOTE 7
7. DEVIATION FROM LEAD-TIP TRUE POSITION SHALL BE WITHIN
0.0076 mm FOR PITCH ꢀ 0.5 mm AND WITHIN 0.04 FOR
PITCH < 0.5 mm.
E
23.00
19.90
--
23.40
20.10
--
E1
E3
aaa
ccc
L
SEE NOTE 3
REFERENCE
8. LEAD COPLANARITY SHALL BE WITHIN: (REFER TO 06-500)
1 - 0.10 mm FOR DEVICES WITH LEAD PITCH OF 0.65 - 0.80 mm
2 - 0.076 mm FOR DEVICES WITH LEAD PITCH OF 0.50 mm.
COPLANARITY IS MEASURED PER SPECIFICATION 06-500.
---
---
0.73
1.03
9. HALF SPAN (CENTER OF PACKAGE TO LEAD TIP) SHALL BE
WITHIN 0.0085".
P
Q
40
R
64
S
80
3213\38.4C
14
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Connection Diagrams
80-Ball Fortified BGA
A8
A2
B8
A1
C8
A0
D8
E8
F8
G8
H8
J8
K8
DQ29
VCCQ
VSS
VCCQ
DQ20
DQ16
MCH
A7
A3
B7
A4
C7
D7
E7
F7
G7
H7
J7
K7
MCH
DQ30
DQ26
DQ24
DQ23
DQ18 IND/WAIT# NC
A6
A6
B6
A5
C6
A7
D6
E6
F6
G6
H6
J6
K6
DQ19
OE#
WE#
DQ31
DQ28
DQ25
DQ21
A5
B5
A8
C5
NC
D5
NC
E5
F5
G5
H5
J5
K5
VSS
DQ27
RY/BY#
DQ22
DQ17
CE#
VCC
A4
B4
A9
C4
D4
NC
E4
F4
G4
H4
J4
K4
ACC
A10
DQ1
DQ5
DQ9
WP#
NC
VSS
A3
B3
C3
D3
E3
F3
G3
H3
J3
K3
VCC
A12
A11 A19 (32 Mb)/ DQ2
NC (16 Mb)
DQ6
DQ10
DQ11
ADV#
CLK
A2
B2
C2
D2
E2
F2
G2
H2
J2
K2
A14
A13
A18
DQ0
DQ4
DQ7
DQ8
DQ12
DQ14 RESET#
A1
B1
C1
D1
E1
F1
G1
H1
J1
K1
A15
A16
A17
DQ3
VCCQ
VSS
VCCQ
DQ13
DQ15
VCCQ
Note: On 16 Mb device, ball D3 (A19) is NC.
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (BGA). The package
and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
15
P r e l i m i n a r y
Physical Dimensions
LAA080–80-ball Fortified Ball Grid Array (13 x 11 mm)
D1
0.20
2X
C
D
A
eD
K
J
H
G
F
E
D
C
B
A
8
7
6
5
4
3
2
1
7
SE
eE
E
E1
A1 CORNER ID.
(INK OR LASER)
B
A1
CORNER
6
NXφb
SD
0.20
2X
C
7
1.00 0.5
TOP VIEW
φ0.25
φ0.10
M
C
C
A B
A1
CORNER
M
BOTTOM VIEW
0.25
C
A
A2
A1
SEATING PLANE
C
0.15
C
SIDE VIEW
NOTES:
PACKAGE
JEDEC
LAA 080
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
N/A
NOTE
13.00 x 11.00 mm
PACKAGE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010
(EXCEPT AS NOTED).
SYMBOL
A
MIN
--
NOM
--
MAX
1.40
--
PROFILE HEIGHT
STANDOFF
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A1
0.40
0.60
--
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D"
DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX
SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF
SOLDER BALLS.
A2
--
--
BODY THICKNESS
BODY SIZE
D
13.00 BSC.
11.00 BSC.
9.00 BSC.
7.00 BSC.
10
E
BODY SIZE
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER
OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D
OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW , SD OR SE = e/2
E1
MD
ME
N
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
8
80
φb
0.50
0.60
0.70
BALL DIAMETER
8. N/A
eD
1.00 BSC.
1.00 BSC.
0.50 BSC
BALL PITCH - D DIRECTION
BALL PITCH - E DIRECTION
SOLDER BALL PLACEMENT
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
eE
SD/SE
3214\38.12C
16
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Pin Configuration
A0–A19
=
20-bit address bus for 32 Mb device, (19-bit for 16
Mb). A9 supports 12 V autoselect inputs.
DQ0–DQ31
CE#
=
=
32-bit data inputs/outputs/float
Chip Enable Input. This signal is asynchronous
relative to CLK for the burst mode.
OE#
WE#
=
=
Output Enable Input. This signal is asynchronous
relative to CLK for the burst mode.
Write enable. This signal is asynchronous relative to
CLK for the burst mode.
VSS
NC
RY/BY#
=
=
=
Device ground
Pin not connected internally
Ready/Busy output and open drain. When RY/BY# =
VOH, the device is ready to accept read operations
and commands. When RY/BY# = VOL, the device is
either executing an embedded algorithm or the
device is executing a hardware reset operation.
Clock Input that can be tied to the system or
microprocessor clock and provides the fundamental
timing and internal operating frequency.
Load Burst Address input. Indicates that the valid
address is present on the address inputs.
CLK
=
ADV#
IND#
=
=
End of burst indicator for finite bursts only. IND is low
when the last word in the burst sequence is at the
data outputs.
WAIT#
WP#
=
=
Provides data valid feedback only when the burst
length is set to continuous.
Write Protect input. When WP# = VOL, the two
outermost bootblock sector in the 75% bank are
write protected regardless of other sector protection
configurations.
ACC
=
Acceleration input. When taken to 12 V, program and
erase operations are accelerated. When not used for
acceleration, ACC = VSS to VCC.
VIO (VCCQ
VCC
)
=
=
Output Buffer Power Supply (1.65 V to 2.75 V)
Chip Power Supply (2.5 V to 2.75 V) or (3.00 V to
3.60 V)
RESET#
MCH
=
=
Hardware reset input
Must Connect High (to VCC)
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
17
P r e l i m i n a r y
Logic Symbols
S29CD032G
20
A0–A19
32
DQ0–DQ31
CLK
CE#
OE#
WE#
IND/WAIT#
RY/BY#
RESET#
ADV#
ACC
WP#
V
(V
)
IO
CCQ
S29CD016G
19
A0–A18
32
DQ0–DQ31
CLK
CE#
OE#
WE#
IND/WAIT#
RY/BY#
RESET#
ADV#
ACC
WP#
V
(V
)
IO
CCQ
18
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Memory Map and Sector Protect Groups
The following tables lists the address ranges for all sectors and sector groups, and the sector
sizes.
Table 23. 32 Mb Memory Map and Sector Protect Groups for Ordering Option 00, Top Boot
Sector
Group
Note 4
x32
Address Range
(A19:A0)
Sector
Size
(KDwords)
Sector
Group
Note 4
x32
Sector
Size
(KDwords)
Sector
Sector
Address Range
(A19:A0)
Bank 0, Small Bank Note 2
Bank 1, Large Bank Note 2
SA0
Note 1
SG0
00000h–007FFh
2
SA23
40000h–43FFFh
16
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SG1
SG2
SG3
SG4
SG5
SG6
SG7
00800h–00FFFh
01000h–017FFh
01800h–01FFFh
02000h–027FFh
02800h–02FFFh
03000h–037FFh
03800h–03FFFh
04000h–07FFFh
08000h–0BFFFh
0C000h–0FFFFh
10000h–13FFFh
14000h–17FFFh
18000h–1BFFFh
1C000h–1FFFFh
20000h–23FFFh
24000h–27FFFh
28000h–2BFFFh
2C000h–2FFFFh
30000h–33FFFh
34000h–37FFFh
38000h–3BFFFh
3C000h–3FFFFh
2
2
2
2
2
2
2
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
44000h–47FFFh
48000h–4BFFFh
4C000h–4FFFFh
50000h–53FFFh
54000h–57FFFh
58000h–5BFFFh
5C000h–5FFFFh
60000h–63FFFh
64000h–67FFFh
68000h–6BFFFh
6C000h–6FFFFh
70000h–73FFFh
74000h–77FFFh
78000h–7BFFFh
7C000h–7FFFFh
80000h–83FFFh
84000h–87FFFh
88000h–8BFFFh
8C000h–8FFFFh
90000h–93FFFh
94000h–97FFFh
98000h–9BFFFh
9C000h–9FFFFh
A0000h–A3FFFh
A4000h–A7FFFh
A8000h–ABFFFh
AC000h–AFFFFh
B0000h–B3FFFh
B4000h–B7FFFh
B8000h–BBFFFh
BC000h–BFFFFh
C0000h–C3FFFh
C4000h–C7FFFh
C8000h–CBFFFh
CC000h–CFFFFh
D0000h–D3FFFh
D4000h–D7FFFh
D8000h–DBFFFh
DC000h–DFFFFh
E0000h–E3FFFh
E4000h–E7FFFh
E8000h–EBFFFh
EC000h–EFFFFh
F0000h–F3FFFh
F4000h–F7FFFh
F8000h–FBFFFh
FC000h–FC7FFh
FC800h–FCFFFh
FD000h–FD7FFh
FD800h–FDFFFh
FE000h–FE7FFh
FE800h–FEFFFh
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2
SG12
SG13
SG14
SG15
SG16
SG17
SG18
SG19
SG20
SG21
SG8
SG9
SG10
SG11
SG22
SG23
SG24
SG25
SG26
SG27
SG28
SG29
2
2
2
2
2
SA76
Note 3
SA77
Note 3
SG30
SG31
FF000h–FF7FFh
FF800h–FFFFFh
2
2
Notes:
1. Secured Silicon Sector overlays this sector when enabled.
2. The bank address is determined by A19 and A18. BA = 00 for Bank 0 and BA = 01, 10, or 11 for Bank 1.
3. This sector has the additional WP# pin sector protection feature.
4. Sector groups are for Sector Protection.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
19
P r e l i m i n a r y
Table 24. 32 Mb Memory Map and Sector Protect Groups for Ordering Option 01, Bottom Boot
Sector
Group
Note 4
x32
Address Range
(A19:A0)
Sector
Size
(KDwords)
Sector
Group Address Range
Note 4 (A19:A0)
x32
Sector
Size
(KDwords)
Sector
Sector
Bank 0, Large Bank Note 2
Bank 1, Small Bank (Note 2)
SA0 Note 1
SA1 Note 1
SA2
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
00000h–007FFh
00800h–00FFFh
01000h–017FFh
01800h–01FFFh
02000h–027FFh
02800h–02FFFh
03000h–037FFh
03800h–03FFFh
04000h–07FFFh
08000h–0BFFFh
0C000h–0FFFFh
10000h–13FFFh
14000h–17FFFh
18000h–1BFFFh
1C000h–1FFFFh
20000h–23FFFh
24000h–27FFFh
28000h–2BFFFh
2C000h–2FFFFh
30000h–33FFFh
34000h–37FFFh
38000h–3BFFFh
2
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
C0000h–C3FFFh
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2
2
C4000h–C7FFFh
SG20
2
2
C8000h–CBFFFh
CC000h–CFFFFh
D0000h–D3FFFh
SA3
SA4
2
SA5
SA6
2
2
D4000h–D7FFFh
D8000h–DBFFFh
SG21
SA7
2
DC000h–DFFFFh
E0000h–E3FFFh
E4000h–E7FFFh
SA8
SA9
16
16
16
16
16
16
16
16
16
16
16
16
16
16
SG8
SG22
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
E8000h–EBFFFh
EC000h–EFFFFh
F0000h–F3FFFh
SG9
SG23
F4000h–F7FFFh
F8000h–FBFFFh
FC000h–FC7FFh
FC800h–FCFFFh
FD000h–FD7FFh
FD800h–FDFFFh
FE000h–FE7FFh
FE800h–FEFFFh
FF000h–FF7FFh
SG24
SG25
SG26
SG27
SG28
SG29
SG30
2
SG10
SG11
SG12
2
2
2
2
2
SA77
Note 3
SA22
3C000h–3FFFFh
16
SG31
FF800h–FFFFFh
2
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
40000h–43FFFh
44000h–47FFFh
48000h–4BFFFh
4C000h–4FFFFh
50000h–53FFFh
54000h–57FFFh
58000h–5BFFFh
5C000h–5FFFFh
60000h–63FFFh
64000h–67FFFh
68000h–6BFFFh
70000h–73FFFh
74000h–77FFFh
78000h–7BFFFh
7C000h–7FFFFh
80000h–83FFFh
84000h–87FFFh
88000h–8BFFFh
8C000h–8FFFFh
90000h–93FFFh
94000h–97FFFh
98000h–9BFFFh
9C000h–9FFFFh
A0000h–A3FFFh
A4000h–A7FFFh
A8000h–ABFFFh
AC000h–AFFFFh
B0000h–B3FFFh
B4000h–B7FFFh
B8000h–BBFFFh
BC000h–BFFFFh
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
SG13
SG14
SG15
SG16
SG17
SG18
SG19
Notes:
1. This sector has the additional WP# pin sector protection feature.
2. The bank address is determined by A19 and A18. BA = 00, 01, or 10 for Bank 0 and BA = 11 for Bank 1.
3. Secured Silicon Sector overlays this sector when enabled.
4. Sector groups are for Sector Protection.
20
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Table 25. 16 Mb, Memory Map and Sector Protect Groups for Ordering Option 00, Top Boot
x32
Address Range
(A18:A0)
x32
Address Range
(A18:A0)
Sector
Group
Sector Size
(KDwords)
Sector
Group
Sector Size
(KDwords)
Sector
Sector
Bank 0
,
Small Bank Note 2
00000h–007FFh
00800h–00FFFh
01000h–017FFh
01800h–01FFFh
02000h–027FFh
02800h–02FFFh
03000h–037FFh
03800h–03FFFh
04000h–07FFFh
08000h–0BFFFh
0C000h–0FFFFh
10000h–13FFFh
14000h–17FFFh
18000h–1BFFFh
1C000h–1FFFFh
Bank 1, Large Bank Note 2
SA0 Note 1
SA1
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
2
2
SA15
SA16
20000h–23FFFh
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2
24000h–27FFFh
SG10
SA2
2
SA17
28000h–2BFFFh
SA3
2
SA18
2C000h–2FFFFh
30000h–33FFFh
SA4
2
SA19
SA5
2
SA20
34000h–37FFFh
SG11
SA6
2
SA21
38000h–3BFFFh
SA7
2
SA22
3C000h–3FFFFh
40000h–43FFFh
SA8
16
16
16
16
16
16
16
SA23
SA9
SG8
SA24
44000h–47FFFh
SG12
SA10
SA11
SA12
SA13
SA14
SA25
48000h–4BFFFh
SA26
4C000h–4FFFFh
50000h–53FFFh
SA27
SG9
SA28
54000h–57FFFh
SG13
SA29
58000h–5BFFFh
SA30
5C000h–5FFFFh
60000h–63FFFh
SA31
SA32
64000h–67FFFh
SG14
SA33
68000h–6BFFFh
SA34
6C000h–6FFFFh
70000h–73FFFh
SA35
SA36
SG15
74000h–77FFFh
78000h–7BFFFh
7C000h–7C7FFh
7C800h–7CFFFh
7D000h–7D7FFh
7D800h–7DFFFh
7E000h–7E7FFh
7E800h–7EFFFh
7F000h–7F7FFh
7F800h–7FFFFh
SA37
SA38
SG16
SG17
SG18
SG19
SG20
SG21
SG22
SG23
SA39
2
SA40
2
SA41
2
SA42
2
SA43
2
SA44 Note 2
SA45 Note 2
2
2
Notes:
1. Secured Silicon Sector overlays this sector when enabled.
2. The bank address is determined by A18 and A17. BA = 00 for Bank 1 and BA = 01, 10, or 11 for Bank 2.
3. This sector has the additional WP# pin sector protection feature.
4. Sector groups are for Sector Protection.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
21
P r e l i m i n a r y
Table 26. 16 Mb, Memory Map and Sector Protect Groups for Ordering Option 00, Bottom Boot
Sector
Group
Note 4
x32
Address Range
(A19:A0)
Sector
Size
(KDwords)
Sector
Group
Note 4
x32
Sector
Size
(KDwords)
Sector
Sector
Address Range
(A19:A0)
Bank 0, Large Bank Note 2
Bank 1, Small Bank Note 2
SA0 Note 1
SA1 Note 1
SA2
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
00000h–007FFh
00800h–00FFFh
01000h–017FFh
01800h–01FFFh
02000h–027FFh
02800h–02FFFh
03000h–037FFh
03800h–03FFFh
04000h–07FFFh
08000h–0BFFFh
0C000h–0FFFFh
10000h–13FFFh
14000h–17FFFh
18000h–1BFFFh
1C000h–1FFFFh
20000h–23FFFh
24000h–27FFFh
28000h–2BFFFh
2C000h–2FFFFh
30000h–33FFFh
34000h–37FFFh
38000h–3BFFFh
3C000h–3FFFFh
40000h–43FFFh
44000h–47FFFh
48000h–4BFFFh
4C000h–4FFFFh
50000h–53FFFh
54000h–57FFFh
58000h–5BFFFh
5C000h–5FFFFh
60000h–63FFFh
64000h–67FFFh
68000h–6BFFFh
6C000h–6FFFFh
2
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
70000h–73FFFh
16
16
16
2
2
SG15
74000h–77FFFh
78000h–7BFFFh
7C000h–7C7FFh
7C800h–7CFFFh
7D000h–7D7FFh
7D800h–7DFFFh
7E000h–7E7FFh
7E800h–7EFFFh
7F000h–7F7FFh
7F800h–7FFFFh
2
2
SA3
SG16
SG17
SG18
SG19
SG20
SG21
SG22
SG23
SA4
2
2
SA5
SA6
2
2
2
2
SA7
2
2
SA8
SA9
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2
2
SG8
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
2
SG9
SG10
SG11
SG12
SG13
SG14
Notes:
1. This sector has the additional WP# pin sector protection feature.
2. The bank address is determined by A18 and A17. BA = 00 for Bank 1 and BA = 01, 10, or 11 for Bank 2.
3. Secured Silicon Sector overlays this sector when enabled.
4. Sector groups are for Sector Protection.
22
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Device Operations
This section describes the requirements and use of the device bus operations, which are initiated
through the internal command register. The command register itself does not occupy any addres-
sable memory location. The register is composed of latches that store the commands, along with
the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. Table 27 lists the device bus operations, the inputs and control levels they require,
and the resulting output. The following subsections describe each of these operations in further
detail.
Table 27. Device Bus Operation
Data
(DQ0–DQ31)
Operation
CE# OE# WE# RESET# CLK
ADV#
Addresses
Read
L
L
L
H
L
H
H
X
X
X
X
A
A
D
OUT
IN
IN
Asynchronous Write
Synchronous Write
H
D
IN
IN
L
H
L
H
A
D
IN
Standby (CE#)
Output Disable
Reset
H
L
X
H
X
X
H
X
H
H
L
X
X
X
X
X
X
X
HIGH Z
HIGH Z
HIGH Z
HIGH Z
X
X
00000001h, (protected)
A6 = H
Sector Address,
PPB Protection Status (Note 2)
L
L
H
H
X
X
A9 = V ,
ID
00000000h (unprotect)
A6 = L
A7 – A0 = 02h
Burst Read Operations
Load Starting Burst Address
L
L
X
L
H
H
H
H
A
X
IN
Advance Burst to next address
with appropriate Data presented
on the Data bus
H
X
Burst Data Out
Terminate Current Burst
Read Cycle
H
X
X
X
H
H
H
L
X
X
X
X
HIGH Z
HIGH Z
Terminate Current Burst
Read Cycle with RESET#
X
Terminate Current Burst
Read Cycle;
Start New Burst Read Cycle
L
H
H
H
A
X
IN
Legend: L = Logic Low = V , H = Logic High = V , X = Don’t care.
IL
IH
Notes:
1. WP# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block.
2. DQ0 reflects the sector PPB (or sector group PPB) and DQ1 reflects the DYB
VersatileI/O™ (V ) Control
IO
The VersatileI/O (VIO) control allows the host system to set the voltage levels that the device gen-
erates at its data outputs and the voltages tolerated at its data inputs to the same voltage level
that is asserted on the VIO pin.
The output voltage generated on the device is determined based on the VIO (VCCQ) level. For the
2.6 V VCC Mask Option, a VIO of 1.65 V – 1.95 V allows the device to interface with I/Os lower
than 2.5 V. Vcc = VIO (2.5 V to 2.75V) make the device appear as a 2.5 V only.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is
the power control and selects the device. OE# is the output control and gates array data to the
output pins. WE# should remain at VIH.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
23
P r e l i m i n a r y
The internal state machine is set for reading array data upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the memory content occurs during the power
transition. No command is necessary in this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the command register con-
tents are altered.
Address access time (tACC) is the delay from stable addresses to valid output data. The chip en-
able access time (tCE) is the delay from stable addresses and stable CE# to valid data at the
output pins. The output enable access time (tOE) is the delay from the falling edge of OE# to valid
data at the output pins (assuming the addresses were stable for at least tACC–tOE time and CE#
is asserted for at least tCE–tOE time).
See Reading Array Data in Non-burst Mode and Reading Array Data in Burst Mode for more infor-
mation. Refer to the Asynchronous Read Operations table for timing specifications and to
Figure 15 for the timing diagram. ICC1 in the DC Characteristics table represents the active cur-
rent specification for reading array data.
Simultaneous Read/Write Operations Overview
Overview
The Simultaneous Read/Write feature allows embedded program or embedded erase operation to
be executed in the Small Bank, while reading from the Large Bank. The opposite case is not valid.
Table 28. Allowable Conditions for Simultaneous Operation
Small Bank
Embedded Erase
Large Bank
Burst (Synchronous) Read or
Asynchronous Read
Burst (Synchronous) Read or
Asynchronous Read
Embedded Program
Note:
Please refer to the Memory Map Table 23, Table 24, Table 25, and Table 26 for Small and Large Bank assignments.
Program/Erase Suspend and Simultaneous Operation
There is no restriction to implementing a program-suspend or erase-suspend during a simulta-
neous operation.
Common Flash Interface (CFI) and Password Program/Verify
and Simultaneous Operation
Simultaneous read/write operation is disabled during the CFI and Password Program/Verify oper-
ation, including PPB program/erase and unlocking a password operation. Only array data can be
read in the Large Bank during a simultaneous operation.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and
erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device
enters the Unlock Bypass mode, only two write cycles are required to program a word or byte,
instead of four. See Sector Erase and Program Suspend Command on page 47 for details on pro-
gramming data to the device using both standard and Unlock Bypass command sequences.
24
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
An erase operation can erase one sector, multiple sectors, or the entire device. Table 23, Table 24,
Table 25, and Table 26 indicate the address space that each sector occupies. A sector address
consists of the address bits required to uniquely select a sector. See Command Definitions on
page 42 for details on erasing a sector or the entire chip, or suspending/resuming the erase
operation.
When in Synchronous read mode configuration, the device is able to perform both asynchronous
and synchronous write operations. CLK and ADV# address latch is supported in synchronous pro-
gramming mode. During a synchronous write operation, to write a command or command
sequence, (which includes programming data to the device and erasing sectors of memory), the
system must drive ADV# and CE# to VIL, and OE# to VIH when providing an address to the de-
vice, and drive WE# and CE# to VIL, and CE# to VIH, when writing commands or data.
Accelerated Program and Erase Operations
The device offers accelerated program/erase operations through the ACC pin. When the system
asserts VHH (12V) on the ACC pin, the device automatically enters the Unlock Bypass mode. The
system may then write the two-cycle Unlock Bypass program command sequence to do acceler-
ated programming. The device uses the higher voltage on the ACC pin to accelerate the operation.
A sector that is being protected with the WP# pin is protected during accelerated program or
Erase.
Note: The ACC pin must not be at V
result.
during any operation other than accelerated programming, or device damage can
HH
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode.
The system can then read autoselect codes from the internal register (which is separate from the
memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. See Autoselect
Mode on page 26 and Autoselect Command on page 43 for more information.
Automatic Sleep Mode (ASM)
The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous
mode, the device automatically enables this mode when addresses remain stable for tACC + 60
ns. The automatic sleep mode is independent of the CE#, WE# and OE# control signals. Standard
address access timings provide new data when addresses are changed. While in sleep mode, out-
put data is latched and always available to the system. While in synchronous mode, the device
automatically enables this mode when either the first active CLK level is greater than tACC or the
CLK runs slower than 5 MHz. Note that a new burst operation is required to provide new data.
ICC8 in DC Characteristics on page 64 represents the automatic sleep mode current specification.
Standby Mode
When the system is not responding or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at
Vcc ± 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to
read data.
If the device is deselected during erasure or programming, the device draws active current until
the operation is completed.
ICC5 in DC Characteristics on page 64 represents the standby current specification.
Caution: entering the standby mode via the RESET# pin also resets the device to the read mode
and floats the data I/O pins. Furthermore, entering ICC7 during a program or erase operation
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
25
P r e l i m i n a r y
leaves erroneous data in the address locations being operated on at the time of the RESET# pulse.
These locations require updating after the device resumes standard operations. See RESET#:
Hardware Reset Pin on page 26 for further discussion of the RESET# pin and its functions.
RESET#: Hardware Reset Pin
The RESET# pin is an active low signal that is used to reset the device under any circumstances.
A logic 0 on this pin forces the device out of any mode that is currently executing back to the reset
state. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the device. To avoid a potential bus contention during a system reset, the device is isolated
from the DQ data bus by tristating the data output pins for the duration of the RESET pulse. All
pins are don’t cares during the reset operation.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains low until the
reset operation is internally complete. This action requires between 1 µs and 7µs for either Chip
Erase or Sector Erase. The RY/BY# pin can be used to determine when the reset operation is com-
plete. Otherwise, allow for the maximum reset time of 11 µs. If RESET# is asserted when a
program or erase operation is not executing (RY/BY# = 1), the reset operation completes within
500 ns. The Simultaneous Read/Write feature of this device allows the user to read a bank after
500 ns if the bank was in the read/reset mode at the time RESET# was asserted. If one of the
banks was in the middle of either a program or erase operation when RESET# was asserted, the
user must wait 11 µs before accessing that bank.
Asserting RESET# during a program or erase operation leaves erroneous data stored in the ad-
dress locations being operated on at the time of device reset. These locations need updating after
the reset operation is complete. See Figure 19, RESET# Timings, on page 72 for timing
specifications.
Asserting RESET# active during VCC and VIO power up is required to guarantee proper device ini-
tialization until VCC and VIO reaches steady state voltages.
Output Disable Mode
See Table 27 on page 23 Device Bus Operation for OE# Operation in Output Disable Mode.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection ver-
ification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for
programming equipment to automatically match a device to be programmed with its correspond-
ing programming algorithm. However, the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Ad-
dress pins A6, A1, and A0 must be as shown in Table 24 on page 20 (top boot devices) or Table 25
on page 21 (bottom boot devices). In addition, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order address bits (see Table 23 on page 19
through Table 26 on page 22). Table 29 shows the remaining address bits that are don’t care.
When all necessary bits are set as required, the programming equipment may then read the
corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via
the command. This method does not require VID. See Command Definitions on page 42 for details
on using the autoselect mode.
26
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Table 29. S29CD-G Flash Family Autoselect Codes (High Voltage Method)
A19
A5
DQ7
to
Description
CE# OE# WE# to A10 A9 A8 A7 A6 to A3 A2 A1 A0
A11
X
A4
X
DQ0
Manufacturer ID: Spansion
L
L
L
L
H
H
X
X
V
V
X
X
X
L
L
L
X
L
X
L
L
L
L
0001h
007Eh
ID
ID
Read Cycle 1
X
X
H
0036h (16Mb)
0009h (32Mb)
Read Cycle 2
V
ID
L
L
H
X
X
X
L
L
L
H
H
H
L
0000h
Ordering Option 00
Read Cycle 3
L
L
L
L
H
H
X
X
X
V
V
X
X
L
L
L
L
L
L
H
L
H
L
H
H
H
L
ID
ID
0001h
Ordering Option 01
0000h (unprotected)
0001h (protected)
PPB Protection Status
SA
Legend: L = Logic Low = V , H = Logic High = V
, SA = Sector Address, X = Don’t care.
IL
IH
Note: The autoselect codes can also be accessed in-system via command sequences. See Table 40 on page 48 and Table 42
on page 55.
Asynchronous Read Operation (Non-Burst)
The device has two control functions which must be satisfied in order to obtain data at the out-
puts. CE# is the power control and is used for device selection. OE# is the output control and is
used to gate data to the output pins if the device is selected. The device is powered-up in an asyn-
chronous read mode. In the asynchronous mode the device has two control functions which must
be satisfied in order to obtain data at the outputs. CE# is the power control and is used for device
selection. OE# is the output control and is used to gate data to the output pins if the device is
selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The
chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data
at the output pins. The output enable access time is the delay from the falling edge of OE# to
valid data at the output pins (assuming the addresses are stable for at least tACC–tOE time).
CE#
CLK
ADV#
Addresses
Data
Address 0
Address 1
Address 2
Address 3
D0
D1
D2
D3
D3
OE#
WE#
VIH
Float
Float
VOH
IND/WAIT#
Note: Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.
Figure 1. Asynchronous Read Operation
Synchronous (Burst) Read Operation
The device is capable of performing burst read operations to improve total system data through-
put. The 2, 4, and 8 double word accesses are configurable as linear burst accesses. All burst
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
27
P r e l i m i n a r y
operations provide wrap around linear burst accesses. Additional options for all burst modes in-
clude initial access delay configurations (2–16 CLKs) Device configuration for burst mode
operation is accomplished by writing the Configuration Register with the desired burst configura-
tion information. Once the Configuration Register is written to enable burst mode operation, all
subsequent reads from the array are returned using the burst mode protocols. Like the main
memory access, the Secured Silicon Sector memory is accessed with the same burst or asynchro-
nous timing as defined in the Configuration Register. However, the user must recognize burst
operations past the 256 byte Secured Silicon boundary returns invalid data.
Burst read operations occur only to the main flash memory arrays. The Configuration Register and
protection bits are treated as single cycle reads, even when burst mode is enabled. Read opera-
tions to these locations results in the data remaining valid while OE# is at VIL, regardless of the
number of CLK cycles applied to the device.
Linear Burst Read Operations
Linear burst read mode reads either 2, 4, or 8 double words (1 double word = 32 bits). (See
Table 30 for all valid burst output sequences). The IND/WAIT# pin transitions active (VIL) during
the last transfer of data during a linear burst read before a wrap around, indicating that the sys-
tem should initiate another ADV# to start the next burst access. If the system continues to clock
the device, the next access wraps around to the starting address of the previous burst access.
The IND/WAIT# signal remains inactive (floating) when not active. See Table 30 for a complete
32 data bus interface order.
Table 30. 32- Bit Linear and Burst Data Order
Data Transfer Sequence (Independent of the WORD# pin) Output Data Sequence (Initial Access Address)
0-1 (A0 = 0)
Two Linear Data Transfers
1-0 (A0 = 1)
0-1-2-3 (A0:A-1/A1-A0 = 00)
1-2-3-0 (A0:A-1/A1-A0 = 01)
2-3-0-1 (A:A-1/A1-A0 = 10)
Four Linear Data Transfers
3-0-1-2 (A0:A-1/A1-A0 = 11)
0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000)
1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001)
2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010)
3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011)
4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100)
Eight Linear Data Transfers
5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101)
6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110)
7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111)
CE# Control in Linear Mode
The CE# (Chip Enable) pin enables the device during read mode operations. CE# must meet the
required burst read setup times for burst cycle initiation. If CE# is taken to VIH at any time during
the burst linear or burst cycle, the device immediately exits the burst sequence and floats the DQ
bus signal. Restarting a burst cycle is accomplished by taking CE# and ADV# to VIL.
ADV# Control In Linear Mode
The ADV# (Address Valid) pin is used to initiate a linear burst cycle at the clock edge when CE#
and ADV# are at VIL and the device is configured for either linear burst mode operation. A burst
access is initiated and the address is latched on the first rising CLK edge when ADV# is active or
upon a rising ADV# edge, whichever occurs first. If the ADV# signal is taken to VIL prior to the
end of a linear burst sequence, the previous address is discarded and subsequent burst transfers
are invalid until ADV# transitions to VIH before a clock edge, which initiates a new burst sequence.
28
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
RESET# Control in Linear Mode
The RESET# pin immediately halts the linear burst access when taken to VIL. The DQ data bus
signal float. Additionally, the Configuration Register contents are reset back to the default condi-
tion where the device is placed in asynchronous access mode.
OE# Control in Linear Mode
The OE# (Output Enable) pin is used to enable the linear burst data on the DQ data bus pin. De-
asserting the OE# pin to VIH during a burst operation floats the data bus. However, the device
continues to operate internally as if the burst sequence continues until the linear burst is com-
plete. The OE# pin does not halt the burst sequence, this is accomplished by either taking CE#
to VIH or re-issuing a new ADV# pulse. The DQ bus remains in the float state until OE# is taken
to VIL.
IND/WAIT# Operation in Linear Mode
The IND/WAIT#, or End of Burst Indicator signal (when in linear modes), informs the system that
the last address of a burst sequence is on the DQ data bus. For example, if a 2-double-word linear
burst access is enabled using a 16-bit DQ bus (WORD# = VIL), the IND/WAIT# signal transitions
active on the second access. If the same scenario is used, the IND/WAIT# signal has the same
delay and setup timing as the DQ pins. Also, the IND/WAIT# signal is controlled by the OE# sig-
nal. If OE# is at VIH, the IND/WAIT# signal floats and is not driven. If OE# is at VIL, the IND/
WAIT# signal is driven at VIH until it transitions to VIL indicating the end of burst sequence. The
IND/WAIT# signal timing and duration is (See Configuration Register on page 31 for more infor-
mation). The following table lists the valid combinations of the Configuration Register bits that
impact the IND/WAIT# timing.
Table 31. Valid Configuration Register Bit Definition for IND/WAIT#
DOC WC CC
Definition
0
0
0
1
1
1
IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLD edge
IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge
V
V
IH
CE#
CLK
IL
3 Clock Delay
ADV#
Address 1 Latched
Address 2
Address 1
Addresses
Data
Invalid
D1
D2
D3
D0
OE#
IND/WAIT#
Note: Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay configuration, linear address,
4-doubleword burst, output on rising CLD edge, data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wrap-
around.
Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
29
P r e l i m i n a r y
Burst Access Timing Control
In addition to the IND/WAIT# signal control, burst controls exist in the Control Register for initial
access delay, delivery of data on the CLK edge, and the length of time data is held.
Initial Burst Access Delay Control
The device contains options for initial access delay of a burst access. The initial access delay has
no effect on asynchronous read operations.
Burst Initial Access Delay is defined as the number of clock cycles that must elapse from the first
valid clock edge after ADV# assertion (or the rising edge of ADV#) until the first valid CLK edge
when the data is valid.
The burst access is initiated and the address is latched on the first rising CLK edge when ADV#
is active or upon a rising ADV# edge, whichever comes first. (Table 32 describes the initial access
delay configurations.)
Table 32. Burst Initial Access Delay
Initial Burst Access (CLK cycles)
CR13
CR12
CR11
CR10
40 MHz (0J), 56 MHz (0M), 66 MHz (0P),
75 MHz (0R, 32 Mb only)
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
1st CLK
2nd CLK
3rd CLK
4th CLK
5th CLK
CLK
ADV#
Address 1 Latched
Valid Address
Addresses
Three CLK Delay
DQ31-DQ03
DQ31-DQ04
D0
D1
D0
D2
D1
D3
D2
D4
D3
Four CLK Delay
Five CLK Delay
DQ31-DQ05
D0
D1
D2
Notes:
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
3. CR [13-10] = 1 or three clock cycles
4. CR [13-10] = 2 or four clock cycles
5. CR [13-10] = 3 or five clock cycles
Figure 3. Initial Burst Delay Control
Burst CLK Edge Data Delivery
The device delivers data on the rising of CLK. Bit 6 in the Control Register (CR6) is set to 1, and
is the default configuration.
Burst Data Hold Control
The device is capable of holding data for one CLKs. The default configuration is to hold data for
one CLK and is the only valid state.
30
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Asserting RESET# During A Burst Access
If RESET# is asserted low during a burst access, the burst access is immediately terminated and
the device defaults back to asynchronous read mode. See Hardware Reset (RESET#) on page 71
for more information on the RESET# function.
Configuration Register
The device contains a Configuration Register for configuring read accesses. The Configuration
Register is accessed by the Configuration Register Read and the Configuration Register Write com-
mands. The Configuration Register does not occupy any addressable memory location, but rather,
is accessed by the Configuration Register commands. The Configuration Register is readable any
time, however, writing the Configuration Register is restricted to times when the Embedded Algo-
rithm™ is not active. If the user attempts to write the Configuration Register while the Embedded
Algorithm™ is active, the write operation is ignored and the contents of the Configuration Register
remain unchanged.
The Configuration Register is a 16 bit data field which is accessed by DQ15–DQ0. During a read
operation, DQ31–DQ16 returns all zeroes. Table 33 shows the Configuration Register. Also, Con-
figuration Register reads operate the same as Autoselect command reads. When the command is
issued, the bank address is latched along with the command. Reads operations to the bank that
was specified during the Configuration Register read command return Configuration Register con-
tents. Read operations to the other bank return flash memory data. Either bank address is
permitted when writing the Configuration Register read command.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
31
P r e l i m i n a r y
Table 33. Configuration Register Definitions
CR15
CR14
CR13
CR12
CR11
CR10
CR9
CR8
RM
ASD
IAD3
IAD2
IAD1
IAD0
DOC
WC
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
BS
CC
Reserved
Reserved
Reserved
BL2
BL1
BL0
Configuration Register
CR15 = Read Mode (RM)
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
CR14 = Reserved for Future Enhancements
0 = ASM enable
1 = ASM disable
CR13–CR10 = Automatic Sleep Mode Disable
Speed Options 40, 56, and 66 MHz:
0000 = 2 CLK cycle initial burst access delay
0001 = 3 CLK cycle initial burst access delay
0010 = 4 CLK cycle initial burst access delay
0011 = 5 CLK cycle initial burst access delay
0100 = 6 CLK cycle initial burst access delay
0101 = 7 CLK cycle initial burst access delay
0110 = 8 CLK cycle initial burst access delay
0111 = 9 CLK cycle initial burst access delay—Default
CR9 = Data Output Configuration (DOC)
0 = Hold Data for 1-CLK cycle—Default
1 = Reserved
CR8 = IND/WAIT# Configuration (WC)
0 = IND/WAIT# Asserted During Delay—Default
1 = IND/WAIT# Asserted One Data Cycle Before Delay
CR7 = Burst Sequence (BS)
0 = Reserved
1 = Linear Burst Order—Default
CR6 = Clock Configuration (CC)
0 = Reserved
1 = Burst Starts and Data Output on Rising Clock Edge—Default
CR5–CR3 = Reserved For Future Enhancements (R)
These bits are reserved for future use. Set these bits to 0.
CR2–CR0 = Burst Length (BL2–BL0)
000 = Reserved, burst accesses disabled (asynchronous reads only)
001 = 64 bit (8-byte) Burst Data Transfer - x32 Linear
010 = 128 bit (16-byte) Burst Data Transfer - x32 Linear
011 = 256 bit (32-byte) Burst Data Transfer - x32 Linear (device default)
100 = Reserved, burst accesses disabled (asynchronous reads only)
101 = Reserved, burst accesses disabled (asynchronous reads only)
110 = Reserved, burst accesses disabled (asynchronous reads only)
32
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Table 34. Configuration Register After Device Reset
CR15
RM
1
CR14
Reserve
0
CR13
IAD3
0
CR12
IAD2
1
CR11
IAD1
1
CR10
IAD0
1
CR9
DOC
0
CR8
WC
0
CR7
BS
1
CR6
CC
1
CR5
Reserve
0
CR4
Reserve
0
CR3
Reserve
0
CR2
BL2
1
CR1
BL1
0
CR0
BL0
0
Initial Access Delay Configuration
The frequency configuration informs the device of the number of clocks that must elapse after
ADV# is driven active before data is available. This value is determined by the input clock
frequency.
Sector Protection
The device features several levels of sector protection, which can disable both the program and
erase operations in certain sectors or sector groups
Sector and Sector Groups
The distinction between sectors and sector groups is fundamental to sector protection. Sector are
individual sectors that can be individually sector protected/unprotected. These are the outermost
4 Kword boot sectors, that is, SA0 to SA7 and SA70 to SA77. See Table 35 on page 35, Table 23
on page 19, Table 24 on page 20, Table 25 on page 21, and Table 26 on page 22.
Sector groups are a collection of three or four adjacent 32 kword sectors. For example, sector
group SG8 is comprised of sector SA8 to SA10. When any sector in a sector group is protected/
unprotected, every sector in that group is protection/unprotected. See Table 35, Table 23,
Table 24, Table 25, and Table 26.
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled protection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before changes to certain sec-
tors or sector groups are permitted.
WP# Hardware Protection
A write protect pin that can prevent program or erase to the two outermost 8 Kbytes sectors in
the 75% bank.
All parts default to operate in the Persistent Sector Protection mode. The customer must then
choose if the Persistent or Password Protection method is most desirable. There are two one-time
programmable non-volatile bits that define which sector protection method is used. If the cus-
tomer decides to continue using the Persistent Sector Protection method, they must set the
Persistent Sector Protection Mode Locking Bit. This permanently sets the part to operate
only using Persistent Sector Protection. If the customer decides to use the password method, they
must set the Password Mode Locking Bit. This permanently sets the part to operate only using
password sector protection.
It is important to remember that setting either the Persistent Sector Protection Mode Lock-
ing Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not
possible to switch between the two methods once a locking bit is set. It is important that one
mode is explicitly selected when the device is first programmed, rather than relying on
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
33
P r e l i m i n a r y
the default mode alone. This is so that it is not possible for a system program or virus to later
set the Password Mode Locking Bit, which would cause an unexpected shift from the default Per-
sistent Sector Protection Mode into the Password Protection Mode.
The WP# Hardware Protection feature is always available, independent of the software managed
protection method chosen.
Persistent Sector Protection
The Persistent Sector Protection method replaces the old 12 V controlled protection method while
at the same time enhancing flexibility by providing three different sector protection states:
Persistently Locked—A sector is protected and cannot be changed.
Dynamically Locked—The sector is protected and can be changed by a simple command
Unlocked—The sector is unprotected and can be changed by a simple command
In order to achieve these states, three types of bits are going to be used:
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to a maximum of four sectors (see the
sector address tables for specific sector protection groupings). All 8 Kbyte boot-block sectors have
individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually
modifiable through the PPB Write Command.
Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB eras-
ing. All PPBs erase in parallel, unlike programming where individual PPBs are programmable. It is the
responsibility of the user to perform the preprogramming operation. Otherwise, an already erased sec-
tor PPBs has the potential of being over-erased. There is no hardware mechanism to prevent sector
PPBs over-erasure.
Persistent Protection Bit Lock (PPB Lock)
A global volatile bit. When set to 1, the PPBs cannot be changed. When cleared (0), the PPBs are
changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or
hardware reset. There is no command sequence to unlock the PPB Lock.
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware reset, the con-
tents of all DYBs is 0. Each DYB is individually modifiable through the DYB Write Command.
When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is
defaulted to power up in the cleared state – meaning the PPBs are changeable.
When the device is first powered on the DYBs power up cleared (sectors not protected). The Pro-
tection State for each sector is determined by the logical OR of the PPB and the DYB related to
that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector
is protected or unprotected. By issuing the DYB Write command sequences, the DYBs is set or
cleared, thus placing each sector in the protected or unprotected state. These are the so-called
Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to
switch back and forth between the protected and unprotected conditions. This allows software to
easily protect sectors against inadvertent changes yet does not prevent the easy removal of pro-
tection when changes are needed. The DYBs maybe set or cleared as often as needed.
The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain state
across power cycles because they are Non-Volatile. Individual PPBs are set with a command but
must all be cleared as a group through a complex sequence of program and erasing commands.
The PPBs are limited to 100 erase cycles.
The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the de-
sired settings, the PPB Lock may be set to 1. Setting the PPB Lock disables all program and erase
34
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
commands to the Non-Volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into the current
state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can
determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded.
If no changes are needed then the boot code can set the PPB Lock to disable any further changes
to the PPBs during system operation.
The WP# write protect pin adds a final level of hardware protection to the two outermost 8 Kbytes
sectors in the 75% bank. When this pin is low it is not possible to change the contents of these
two sectors.
It is possible to have sectors that have been persistently locked, and sectors that are left in the
dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect
some of them, a simple DYB Write command sequence is all that is necessary. The DYB write com-
mand for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively.
If there is a need to change the status of the persistently locked sectors, a few more steps are
required. First, the PPB Lock bit must be disabled by either putting the device through a power-
cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting
the PPB lock bit once again, locks the PPBs and the device operates normally again.
Note: To achieve the best protection, it’s recommended to execute the PPB lock bit set command early
in the boot code, and protect the boot code by holding WP# = V .
IL
Table 35. Sector Protection Schemes
DYB
0
PPB
0
PPB Lock
Sector State
Unprotected—PPB and DYB are changeable
0
1
0
0
0
1
1
1
0
0
Unprotected—PPB not changeable, DYB is changeable
0
1
1
0
Protected—PPB and DYB are changeable
1
1
0
1
1
0
Protected—PPB not changeable, DYB is changeable
1
1
Table 35 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status
of the sector.
In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection
can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector
can be dynamically locked or unlocked. The DYB then controls whether or not the sector is pro-
tected or unprotected.
If the user attempts to program or erase a protected sector, the device ignores the command and
returns to read mode. A program command to a protected sector enables status polling for ap-
proximately 1 µs before the device returns to read mode without having modified the contents of
the protected sector. An erase command to a protected sector enables status polling for approx-
imately 50 µs after which the device returns to read mode without having erased the protected
sector.
The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a
DYB/PPB/PPB lock verify command to the device.
Persistent Sector Protection Mode Locking Bit
Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guar-
antee that the device remain in software sector protection. Once set, the Persistent Sector
Protection locking bit prevents programming of the password protection mode locking bit. This
guarantees that an unauthorized user could not place the device in password protection mode.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
35
P r e l i m i n a r y
Password Protection Mode
The Password Sector Protection Mode method allows an even higher level of security than the Per-
sistent Sector Protection Mode. There are two main differences between the Persistent Sector
Protection and the Password Sector Protection Mode:
When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to
the locked state, rather than cleared to the unlocked state.
The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the
device.
The Password Sector Protection method is otherwise identical to the Persistent Sector Protection
method.
A 64-bit password is the only additional tool utilized in this method.
The password is stored in a one-time programmable (OTP) region of the flash memory. Once
the Password Mode Locking Bit is set, the password is permanently set with no means to read,
program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock com-
mand must be written to the flash, along with a password. The flash device internally compares
the given password with the pre-programmed password. If they match, the PPB Lock bit is
cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There
is a built-in 2 µs delay for each password check. This delay is intended to stop any efforts to run
a program that tries all possible combinations in order to crack the password.
Password and Password Mode Locking Bit
In order to select the Password sector protection scheme, the customer must first program the
password. One method of choosing a password would be to correlate it to the unique Electronic
Serial Number (ESN) of the particular flash device. Another method could generate a database
where all the passwords are stored, each of which correlates to a serial number on the device.
Each ESN is different for every flash device; therefore each password should be different for every
flash device. While programming in the password region, the customer may perform Password
Verify operations.
Once the desired password is programmed in, the customer must then set the Password Mode
Locking Bit. This operation achieves two objectives:
1) It permanently sets the device to operate using the Password Protection Mode. It is not possible
to reverse this function.
2) It also disables all further commands to the password region. All program, and read operations
are ignored.
Both of these objectives are important, and if not carefully considered, may lead to unrecoverable
errors. The user must be sure that the Password Protection method is desired when setting the
Password Mode Locking Bit. More importantly, the user must be sure that the password is correct
when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled,
there is no means to verify what the password is afterwards. If the password is lost after setting
the Password Mode Locking Bit, there is no way to clear the PPB Lock bit.
The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus
and further password programming. The Password Mode Locking Bit is not erasable. Once Pass-
word Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled
from programming, guaranteeing that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through the use of the
Password Program and Verify commands (see Password Verify Command). The password function
36
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password
Verify command from reading the contents of the password on the pins of the device.
Write Protect (WP#)
The device features a hardware protection option using a write protect pin that prevents program-
ming or erasing, regardless of the state of the sector’s Persistent or Dynamic Protection Bits. The
WP# pin is associated with the two outermost 8Kbytes sectors in the 75% bank. The WP# pin has
no effect on any other sector. When WP# is taken to VIL, programming and erase operations of
the two outermost 8 Kbytes sectors in the 75% bank are disabled. By taking WP# back to VIH,
the two outermost 8 Kbytes sectors are enabled for program and erase operations, depending
upon the status of the individual sector Persistent or Dynamic Protection Bits. If either of the two
outermost sectors Persistent or Dynamic Protection Bits are programmed, program or erase op-
erations are inhibited. If the sector Persistent or Dynamic Protection Bits are both erased, the two
sectors are available for programming or erasing as long as WP# remains at VIH. The user must
hold the WP# pin at either VIH or VIL during the entire program or erase operation of the two
outermost sectors in the 75% bank.
Secured Silicon OTP Sector and Simultaneous Operation
The Secured Silicon Sector is 256 Kbytes and is located in the Small Bank. For S29CD016G and
S29CD032G devices. Spansion programs and permanently locks the Secured Silicon sector with
Unique device identification. Please contact your sales representative for the Electronic Marking
information.
Since the Secured Silicon is permanent protected by Spansion, during Simultaneous Operation,
the Secured Silicon sector cannot be erased or reprogrammed.
Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password
Mode Locking Bit after power-up reset. If the Password Mode Locking Bit is set, which indicates
the device is in Password Protection Mode, the PPB Lock Bit is also set after a hardware reset (RE-
SET# asserted) or a power-up reset. The ONLY means for clearing the PPB Lock Bit in Password
Protection Mode is to issue the Password Unlock command. Successful execution of the Password
Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RE-
SET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets
the PPB Lock Bit back to a 1.
If the Password Mode Locking Bit is not set, indicating Persistent Sector Protection Mode, the PPB
Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB
Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hard-
ware or power-up reset. The Password Unlock command is ignored in Persistent Sector Protection
Mode.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes. In addition, the following hardware data protection mea-
sures prevent accidental erasure or programming, which might otherwise be caused by spurious
system level signals during VCC power-up and power-down transitions, or from system noise.
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during
VCC power-up and power-down. The command register and all internal erase/program circuits are
disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
37
P r e l i m i n a r y
system must provide the proper signals to the control pins to prevent unintentional writes when
VCC is greater than VLKO
.
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#, or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate
a write cycle, CE# and WE# must be a logical zero (VIL) while OE# is a logical one (VIH).
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power-up, the device does not accept commands on
the rising edge of WE#. The internal state machine is automatically reset to reading array data
on power-up.
V
and V Power-up And Power-down Sequencing
IO
CC
The device imposes no restrictions on VCC and VIO power-up or power-down sequencing. Assert-
ing RESET# to VIL is required during the entire VCC and VIO power sequence until the respective
supplies reach the operating voltages. Once, VCC and VIO attain the operating voltages, de-asser-
tion of RESET# to VIH is permitted.
38
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software inter-
rogation handshake, which allows specific vendor-specified software algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-
dent, and forward- and backward-compatible for the specified flash device families. Flash vendors
can standardize existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address 55h in word mode (or address AAh in byte mode), any time the device is ready to read
array data. The system can read CFI information at the addresses given in Tables 13–16. To ter-
minate reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode.
The device enters the CFI query mode, and the system can read CFI data at the addresses given
in Tables 13–16. The system must write the reset command to return the device to the autoselect
mode.
For further information, please refer to the CFI Specification and CFI Publication 100, available
via the World Wide Web at http://www.spansion.com. Alternatively, contact an AMD representa-
tive for copies of these documents.
Table 36. CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string QRY
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Table 37. CFI System Interface String
Addresses
Data
Description
V
Min. (write/erase)
CC
1Bh
1Ch
0023h
DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt
V
Max. (write/erase)
CC
0027h
DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0004h
0000h
0009h
0000h
0005h
0000h
0007h
0000h
V
V
Min. voltage (00h = no V pin present)
PP
PP
Max. voltage (00h = no V pin present)
PP
PP
Typical timeout per single word/doubleword program 2N µs
Typical timeout for Min. size buffer program 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for word/doubleword program 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
39
P r e l i m i n a r y
Table 38. Device Geometry Definition
Addresses
Data
0016h Device Size = 2N byte
Flash Device Interface description (for complete description, please refer to CFI publication 100)
Description
27h
0000 = x8-only asynchronous interface
0001 = x16-only asynchronous interface
0002 = supports x8 and x16 via BYTE# with asynchronous interface
0003 = x 32-only asynchronous interface
28h
29h
0005h
0000h
0005 = supports x16 and x32 via WORD# with asynchronous interface
2Ah
2Bh
0000h Max. number of byte in multi-byte program = 2N
0000h (00h = not supported)
2Ch
0003h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h Erase Block Region 1 Information
0020h (refer to the CFI specification or CFI publication 100)
0000h
31h
32h
33h
34h
003Dh*
0000h Erase Block Region 2 Information
0000h (refer to the CFI specification or CFI publication 100)
0001h
35h
36h
37h
38h
0007h
0000h Erase Block Region 3 Information
0020h (refer to the CFI specification or CFI publication 100)
0000h
39h
3Ah
3Bh
3Ch
0000h
0000h Erase Block Region 4 Information
0000h (refer to the CFI specification or CFI publication 100)
0000h
* On 16 Mb device, data at address 31h is 1Dh.
40
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Table 39. CFI Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string PRI
43h
44h
0031h
0033h
Major version number, ASCII (reflects modifications to the silicon)
Minor version number, ASCII (reflects modifications to the CFI table)
Address Sensitive Unlock (DQ1, DQ0)
00 = Required, 01 = Not Required
Silicon Revision Number (DQ5–DQ2
0000 = CS49
45h
0004h
0001 = CS59
0010 = CS99
0011 = CS69
0100 = CS119
Erase Suspend (1 byte)
00 = Not Supported
01 = To Read Only
46h
0002h
02 = To Read and Write
Sector Protect (1 byte)
47h
48h
0001h
0000h
00 = Not Supported, X = Number of sectors in per group
Temporary Sector Unprotect
00h = Not Supported, 01h = Supported
Sector Protect/Unprotect scheme (1 byte)
01 =29F040 mode, 02 = 29F016 mode
03 = 29F400 mode, 04 = 29LV800 mode
05 = 29BDS640 mode (Software Command Locking)
06 = BDD160 mode (New Sector Protect)
07 = 29LV800 + PDL128 (New Sector Protect) mode
49h
0006h
Simultaneous Read/Write (1 byte)
4Ah
4Bh
4Ch
4Dh
4Eh
0037h
0001h
0000h
00B5h
00C5h
00h = Not Supported, X = Number of sectors in all banks except Bank 1
Burst Mode Type
00h = Not Supported, 01h = Supported
Page Mode Type
00h = Not Supported, 01h = 4 Word Page, 02h = 8 Word Page
ACC (Acceleration) Supply Minimum
00h = Not Supported (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD)
ACC (Acceleration) Supply Maximum
00h = Not Supported, (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD)
Top/Bottom Boot Sector Flag (1 byte)
00h = Uniform device, no WP# control,
01h = 8 x 8 Kb sectors at top and bottom with WP# control
02h = Bottom boot device
4Fh
0001h
03h = Top boot device
04h = Uniform, Bottom WP# Protect
05h = Uniform, Top WP# Protect
If the number of erase block regions = 1, then ignore this field
Program Suspend
00 = Not Supported
01 = Supported
50h
51h
57h
0001h
0000h
0002h
Write Buffer Size
2(N+1) word(s)
Bank Organization (1 byte)
00 = If data at 4Ah is zero
XX = Number of banks
Bank 1 Region Information (1 byte)
XX = Number of Sectors in Bank 1
58h
59h
5Ah
5Bh
0017h
0037h
0000h
0000h
Bank 2 Region Information (1 byte)
XX = Number of Sectors in Bank 2
Bank 3 Region Information (1 byte)
XX = Number of Sectors in Bank 3
Bank 4 Region Information (1 byte)
XX = Number of Sectors in Bank 4
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
41
P r e l i m i n a r y
Command Definitions
Writing specific address and data commands or sequences into the command register initiates
device operations. Table 41 on page 54 and Table 42 on page 55 define the valid register com-
mand sequences. Writing incorrect address and data values or writing them in the improper
sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is
latched on the rising edge of WE# or CE#, whichever happens first. See AC Characteristics on
page 67 for timing diagrams.
Reading Array Data in Non-burst Mode
The device is automatically set to reading array data after device power-up. No commands are
required to retrieve data. The device is also ready to read array data after completing an Embed-
ded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.
The system can read array data using the standard read timings, except that if it reads at an ad-
dress within erase-suspended sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the system may once again read array data
with the same exception. See Sector Erase and Program Suspend Command on page 47 for more
information on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5
goes high, or while in the autoselect mode. See PPB Lock Bit Set Command on page 51.
Asynchronous Read Operation (Non-Burst) on page 27 for more information. See Sector Erase and
Program Resume Command on page 49 for more information on this mode.
Reading Array Data in Burst Mode
The device is capable of very fast Burst mode read operations. The configuration register sets the
read configuration, burst order, frequency configuration, and burst length.
Upon power on, the device defaults to the asynchronous mode. In this mode, CLK, and ADV# are
ignored. The device operates like a conventional Flash device. Data is available tACC/tCE nanosec-
onds after address becomes stable, CE# become asserted. The device enters the burst mode by
enabling synchronous burst reads in the configuration register. The device exits burst mode by
disabling synchronous burst reads in the configuration register. (See Command Definitions on
page 42). The RESET# command does not terminate the Burst mode. System reset (power on
reset) terminates the Burst mode.
The device has the regular control pins, i.e. Chip Enable (CE#), Write Enable (WE#), and Output
Enable (OE#) to control normal read and write operations. Moreover, three additional control pins
were added to allow easy interface with minimal glue logic to a wide range of microprocessors /
microcontrollers for high performance Burst read capability. These additional pins are Address
Valid (ADV#) and Clock (CLK). CE#, OE#, and WE# are asynchronous (relative to CLK). The Burst
mode read operation is a synchronous operation tied to the edge of the clock. The microprocessor
/ microcontroller supplies only the initial address, all subsequent addresses are automatically
generated by the device with a timing defined by the Configuration Register definition. The Burst
read cycle consists of an address phase and a corresponding data phase.
During the address phase, the Address Valid (ADV#) pin is asserted (taken Low) for one clock
period. Together with the edge of the CLK, the starting burst address is loaded into the internal
Burst Address Counter. The internal Burst Address Counter can be configured to either 2, 4, and
8 double word linear burst, with or without wrap around. See Initial Access Delay
Configuration on page 33.
42
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
During the data phase, the first burst data is available after the initial access time delay defined
in the Configuration Register. For subsequent burst data, every rising (or falling) edge of the CLK
triggers the output data with the burst output delay and sequence defined in the Configuration
Register.
Table 41 on page 54 and Table 42 on page 55 show all the commands executed by the device.
The device automatically powers up in the read/reset state. It is not necessary to issue a read/
reset command after power-up or hardware reset.
Read/Reset Command
After power-up or hardware reset, the device automatically enter the read state. It is not neces-
sary to issue the reset command after power-up or hardware reset. Standard microprocessor
cycles retrieve array data, however, after power-up, only asynchronous accesses are permitted
since the Configuration Register is at its reset state with burst accesses disabled.
The Reset command is executed when the user needs to exit any of the other user command se-
quences (such as autoselect, program, chip erase, etc.) to return to reading array data. There is
no latency between executing the Reset command and reading array data.
The Reset command does not disable the Secured Silicon sector if it is enabled. This function is
only accomplished by issuing the Secured Silicon Sector Exit command.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents.
As such, manufacturer and device codes must be accessible while the device resides in the target
system. PROM programmers typically access the signature codes by raising A9 to VID. However,
multiplexing high voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect Command operation to supplement traditional PROM program-
ming methodology. The operation is initiated by writing the Autoselect command sequence into
the command register. The bank address (BA) is latched during the autoselect command se-
quence write operation to distinguish which bank the Autoselect command references. Reading
the other bank after the Autoselect command is written results in reading array data from the
other bank and the specified address. Following the command write, a read cycle from address
(BA)XX00h retrieves the manufacturer code of (BA)XX01h. Three sequential read cycles at ad-
dresses (BA) XX01h, (BA) XX0Eh, and (BA) XX0Fh read the three-byte device ID (see Table 41).
(The Autoselect Command requires the user to execute the Read/Reset command to return the
device back to reading the array contents.)
Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writ-
ing two unlock write cycles, followed by the program set-up command. The program address and
data are written next, which in turn initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device automatically generates the program
pulses and verifies the programmed cell margin. Table 41 on page 54 and Table 42 on page 55
show the address and data requirements for the program command sequence.
During the Embedded Program algorithm, the system can determine the status of the program
operation by using DQ7, DQ6, or RY/BY#. (See Write Operation Status on page 56 for informa-
tion on these status bits.) When the Embedded Program algorithm is complete, the device returns
to reading array data and addresses are no longer latched. Note that an address change is re-
quired to begin read valid array data.
Except for Program Suspend, any commands written to the device during the Embedded Program
Algorithm are ignored. Note that a hardware reset immediately terminates the programming
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
43
P r e l i m i n a r y
operation. The command sequence should be reinitiated once that bank returns to reading array
data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be pro-
grammed from a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1,
or cause the Data# Polling algorithm to indicate the operation was successful. However, a suc-
ceeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1.
Accelerated Program Command
The Accelerated Chip Program mode is designed to improve the Word or Double Word program-
ming speed. Improving the programming speed is accomplished by using the ACC pin to supply
both the wordline voltage and the bitline current instead of using the VPP pump and drain pump,
which is limited to 2.5 mA. Because the external ACC pin is capable of supplying significantly large
amounts of current compared to the drain pump, all 32 bits are available for programming with
a single programming pulse. This is an enormous improvement over the standard 5-bit program-
ming. If the user is able to supply an external power supply and connect it to the ACC pin,
significant time savings are realized.
In order to enter the Accelerated Program mode, the ACC pin must first be taken to VHH (12 V ±
0.5 V) and followed by the one-cycle command with the program address and data to follow. The
Accelerated Chip Program command is only executed when the device is in Unlock Bypass mode
and during normal read/reset operating mode.
In this mode, the write protection function is bypassed unless the PPB Lock Bit = 1.
The Accelerated Program command is not permitted if the Secured Silicon sector is enabled.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using
the standard program command sequence. The unlock bypass command sequence is initiated by
first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass pro-
gram command sequence is all that is required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the pro-
gram address and data. Additional data is programmed in the same manner. This mode dispenses
with the initial two unlock cycles required in the standard program command sequence, resulting
in faster total programming time. Table 39 on page 41 and Table 41 on page 54 show the require-
ments for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the
data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.
Figure 4 on page 45 illustrates the algorithm for the program operation. See Erase/Program
Operations on page 73 for parameters, and to Figure 21 on page 74 and Figure 22 on page 74
for timing diagrams.
44
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Table 41 and Table 42 for program command sequence.
Figure 4. Program Operation
Unlock Bypass Entry Command
The Unlock Bypass command, once issued, is used to bypass the unlock sequence for program,
chip erase, and CFI commands. This feature permits slow PROM programmers to significantly im-
prove programming/erase throughput since the command sequence often requires microseconds
to execute a single write operation. Therefore, once the Unlock Bypass command is issued, only
the two-cycle program and erase bypass commands are required. The Unlock Bypass Command
is ignored if the Secured Silicon sector is enabled. To return back to normal operation, the Unlock
Bypass Reset Command must be issued.
The following four sections describe the commands that may be executed within the unlock by-
pass mode.
Unlock Bypass Program Command
The Unlock Bypass Program command is a two-cycle command that consists of the actual pro-
gram command (A0h) and the program address/data combination. This command does not
require the two-cycle unlock sequence since the Unlock Bypass command was previously issued.
As with the standard program command, multiple Unlock Bypass Program commands can be is-
sued once the Unlock Bypass command is issued.
To return back to standard read operations, the Unlock Bypass Reset command must be issued.
The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
45
P r e l i m i n a r y
Unlock Bypass Chip Erase Command
The Unlock Bypass Chip Erase command is a 2-cycle command that consists of the erase setup
command (80h) and the actual chip erase command (10h). This command does not require the
two-cycle unlock sequence since the Unlock Bypass command was previously issued. Unlike the
standard erase command, there is no Unlock Bypass Erase Suspend or Erase Resume commands.
To return back to standard read operations, the Unlock Bypass Reset command must be issued.
The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled.
Unlock Bypass CFI Command
The Unlock Bypass CFI command is available for PROM programmers and target systems to read
the CFI codes while in Unlock Bypass mode. See Common Flash Interface (CFI) Command on
page 50 for specific CFI codes.
To return back to standard read operations, the Unlock Bypass Reset command must be issued.
The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled.
Unlock Bypass Reset Command
The Unlock Bypass Reset command places the device in standard read/reset operating mode.
Once executed, normal read operations and user command sequences are available for execution.
The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled.
Chip Erase Command
The Chip Erase command is used to erase the entire flash memory contents of the chip by issuing
a single command. Chip erase is a six-bus cycle operation. There are two unlock write cycles, fol-
lowed by writing the erase set-up command. Two more unlock write cycles are followed by the
chip erase command. Chip erase does not erase protected sectors.
The chip erase operation initiates the Embedded Erase algorithm, which automatically prepro-
grams and verifies the entire memory to an all zero pattern prior to electrical erase. The system
is not required to provide any controls or timings during these operations. Note that a hardware
reset immediately terminates the programming operation. The command sequence should be
reinitiated once that bank returns to reading array data, to ensure data integrity.
The Embedded Erase algorithm erase begins on the rising edge of the last WE# or CE# pulse
(whichever occurs first) in the command sequence. The status of the erase operation is deter-
mined three ways:
Data# polling of the DQ7 pin (See DQ7: Data# Polling on page 56)
Checking the status of the toggle bit DQ6 (See DQ6: Toggle Bit I on page 58)
Checking the status of the RY/BY# pin (See RY/BY#: Ready/Busy# on page 56)
Once erasure begins, only the Erase Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device returns to reading array data, and
addresses are no longer latched. Note that an address change is required to begin read valid array
data.
Figure 5 on page 48 illustrates the Embedded Erase Algorithm. See the Erase/Program
Operations on page 73 for parameters, and Figure 21 and Figure 22 for timing diagrams.
Sector Erase Command
The Sector Erase command is used to erase individual sectors or the entire flash memory con-
tents. Sector erase is a six-bus cycle operation. There are two unlock write cycles, followed by
writing the erase set-up command. Two more unlock write cycles are then followed by the erase
command (30h). The sector address (any address location within the desired sector) is latched
46
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
on the falling edge of WE# or CE# (whichever occurs last) while the command (30h) is latched
on the rising edge of WE# or CE# (whichever occurs first).
Specifying multiple sectors for erase is accomplished by writing the six bus cycle operation, as
described above, and then following it by additional writes of only the last cycle of the Sector
Erase command to addresses or other sectors to be erased. The time between Sector Erase com-
mand writes must be less than 80 µs, otherwise the command is rejected. It is recommended that
processor interrupts be disabled during this time to guarantee this critical timing condition. The
interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 80 µs
from the rising edge of the last WE# (or CE#) initiates the execution of the Sector Erase com-
mand(s). If another falling edge of the WE# (or CE#) occurs within the 80 µs time-out window,
the timer is reset. Once the 80 µs window times out and erasure begins, only the Erase Suspend
command is recognized (See Sector Erase and Program Suspend Command on page 47 and
Sector Erase and Program Resume Command on page 49). If that occurs, the sector erase com-
mand sequence should be reinitiated once that bank returns to reading array data, to ensure data
integrity. Loading the sector erase registers may be done in any sequence and with any number
of sectors.
Sector erase does not require the user to program the device prior to erase. The device automat-
ically preprograms all memory locations, within sectors to be erased, prior to electrical erase.
When erasing a sector or sectors, the remaining unselected sectors or the write protected sectors
are unaffected. The system is not required to provide any controls or timings during sector erase
operations. The Erase Suspend and Erase Resume commands may be written as often as required
during a sector erase operation.
Automatic sector erase operations begin on the rising edge of the WE# or CE# pulse of the last
sector erase command issued, and once the 80 µs time-out window expires. The status of the
sector erase operation is determined three ways:
Data# polling of the DQ7 pin
Checking the status of the toggle bit DQ6
Checking the status of the RY/BY# pin
Further status of device activity during the sector erase operation is determined using toggle bit
DQ2 (See DQ2: Toggle Bit II on page 58).
When the Embedded Erase algorithm is complete, the device returns to reading array data, and
addresses are no longer latched. Note that an address change is required to begin read valid array
data.
Figure 5 on page 48 illustrates the Embedded™ Erase Algorithm, using a typical command se-
quence and bus operation. See the Erase/Program Operations on page 73 for parameters, and
to Figure 21 and Figure 22 for timing diagrams.
Sector Erase and Program Suspend Command
The Sector Erase and Program Suspend command allows the user to interrupt a Sector Erase or
Program operation and perform data read or programs in a sector that is not being erased or to
the sector where a programming operation was initiated. This command is applicable only during
the Sector Erase and Programming operation, which includes the time-out period for Sector
Erase.
Sector Erase and Program Suspend Operation Mechanics
The Sector Erase and Program Suspend command is ignored if written during the execution of the
Chip Erase operation or Embedded Program Algorithm (but resets the chip if written improperly
during the command sequences). Writing the Sector Erase and Program command during the
Sector Erase time-out results in immediate termination of the time-out period and suspension of
the erase operation. Once in Erase Suspend, the device is available for reading (note that in the
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
47
P r e l i m i n a r y
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1.See Table 41 and Table 42 for erase command sequence.
2.See DQ3: Sector Erase Timer for more information.
Figure 5. Erase Operation
Erase Suspend mode, the Reset command is not required for read operations and is ignored) or
program operations in sectors not being erased. Any other command written during the Erase
Suspend mode is ignored, except for the Sector Erase and Program Resume command. Writing
the Erase and Program Resume command resumes the sector erase operation. The bank address
of the erase suspended bank is required when writing this command
If the Sector Erase and Program Suspend command is written during a programming operation,
the device suspends programming operations and allows only read operations in sectors not se-
lected for programming. Further nesting of either erase or programming operations is not
permitted. Table 40 summarizes permissible operations during Erase and Program Suspend. (A
busy sector is one that is selected for programming or erasure.):
Table 40. Allowed Operations During Erase/Program Suspend
Sector
Program Suspend
Program Resume
Read Only
Erase Suspend
Erase Resume
Busy Sector
Non-busy sectors
Read or Program
When the Sector Erase and Program Suspend command is written during a Sector Erase opera-
tion, the chip takes between 0.1 µs and 20 µs to actually suspend the operation and go into the
erase suspended read mode (pseudo-read mode), at which time the user can read or program
from a sector that is not erase suspended. Reading data in this mode is the same as reading from
the standard read mode, except that the data must be read from sectors that were not erase
suspended.
Polling DQ6 on two immediately consecutive reads from a given address provides the system with
the ability to determine if the device is in Erase or Program Suspend. Before the device enters
Erase or Program Suspend, the DQ6 pin toggles between two immediately consecutive reads from
the same address. After the device enters Erase suspend, DQ6 stops toggling between two im-
48
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
mediately consecutive reads to the same address. During the Sector Erase operation and also in
Erase suspend mode, two immediately consecutive readings from the erase-suspended sector
causes DQ2 to toggle. DQ2 does not toggle if reading from a non-busy (non-erasing) sector
(stored data is read). No bits are toggled during program suspend mode. Software must keep
track of the fact that the device is in a suspended mode.
After entering the erase-suspend-read mode, the system may read or program within any non-
suspended sector:
A read operation from the erase-suspended bank returns polling data during the first 8 µs
after the erase suspend command is issued; read operations thereafter return array data.
Read operations from the other bank return array data with no latency.
A program operation while in the erase suspend mode is the same as programming in the
regular program mode, except that the data must be programmed to a sector that is not
erase suspended. Write operation status is obtained in the same manner as a normal pro-
gram operation.
Sector Erase and Program Resume Command
The Sector Erase and Program Resume command (30h) resumes a Sector Erase or Program op-
eration that was suspended. Any further writes of the Sector Erase and Program Resume
command ignored. However, another Sector Erase and Program Suspend command can be writ-
ten after the device resumes sector erase operations. Note that until a suspended program or
erase operation resumes, the contents of that sector are unknown.
The Sector Erase and Program Resume Command is ignored if the Secured Silicon sector is
enabled.
Configuration Register Read Command
The Configuration Register Read command is used to verify the contents of the Configuration Reg-
ister. Execution of this command is only allowed while in user mode and is not available during
Unlock Bypass mode or during Security mode. The Configuration Register Read command is pre-
ceded by the standard two-cycle unlock sequence, followed by the Configuration Register Read
command (C6h), and finally followed by performing a read operation to the bank address speci-
fied when the C6h command was written. Reading the other bank results in reading the flash
memory contents. The contents of the Configuration Register are place on DQ15–DQ0. Contents
of DQ31–DQ16 are XXXXh and should be ignored. The user should execute the Read/Reset com-
mand to place the device back in standard user operation after executing the Configuration
Register Read command.
The Configuration Register Read Command is fully operational if the Secured Silicon sector is
enabled.
Configuration Register Write Command
The Configuration Register Write command is used to modify the contents of the Configuration
Register. Execution of this command is only allowed while in user mode and is not available during
Unlock Bypass mode or during Security mode. The Configuration Register Write command is pre-
ceded by the standard two-cycle unlock sequence, followed by the Configuration Register Write
command (D0h), and finally followed by writing the contents of the Configuration Register to any
address. The contents of the Configuration Register are placed on DQ31–DQ0. The contents of
DQ31–DQ16 are XXXXh and are ignored. Writing the Configuration Register while an Embedded
Algorithm™ or Erase Suspend modes are executing results in the contents of the Configuration
Register not being updated.
The Configuration Register Read Command is fully operational if the Secured Silicon sector is
enabled.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
49
P r e l i m i n a r y
Common Flash Interface (CFI) Command
The Common Flash Interface (CFI) command provides device size, geometry, and capability in-
formation directly to the users system. Flash devices that support CFI, have a Query Command
that returns information about the device to the system. The Query structure contents are read
at the specific address locations following a single system write cycle where:
A 98h query command code is written to 55h address location within the device’s address
space
The device is initially in any valid read state, such as Read Array or Read ID Data
Other device statistics may exist within a long sequence of commands or data input; such se-
quences must first be completed or terminated before writing of the 98H Query command,
otherwise invalid Query data structure output may result.
Note that for data bus bits greater than DQ7 (DQ31–DQ8), the valid Query access code contains
all zeroes (0s) in the upper DQ bus locations. Thus, the 16-bit Query command code is 0098h and
the 32-bit Query command code is 00000098h.
To terminate the CFI operation, it is necessary to execute the Read/Reset command.
The CFI command is not permitted if the Secured Silicon sector is enabled and Simultaneous
Read/Write operation is disabled once the command is entered.
See Common Flash Interface (CFI) Command on page 50 for the specific CFI command codes.
Password Program Command
The Password Program Command permits programming the password that is used as part of the
hardware protection scheme. The actual password is 64-bits long. Depending upon the state of
the WORD# pin, multiple Password Program Commands are required. For a x32 bit data bus, 2
Password Program commands are required. The user must enter the unlock cycle, password pro-
gram command (38h) and the program address/data for each portion of the password when
programming. There are no provisions for entering the 2-cycle unlock cycle, the password pro-
gram command, and all the password data. There is no special addressing order required for
programming the password. Also, when the password is undergoing programming, Simultaneous
Read/Write operation is disabled. Read operations to any memory location returns the program-
ming status. Once programming is complete, the user must issue a Read/Reset command to
return the device to normal operation. Once the Password is written and verified, the Password
Mode Locking Bit must be set in order to prevent verification. The Password Program Command
is only capable of programming 0s. Programming a 1 after a cell is programmed as a 0 results in
a time-out by the Embedded Program Algorithm™ with the cell remaining as a 0. The password
is all F’s when shipped from the factory. All 64-bit password combinations are valid as a password.
Password Programming is permitted if the Secured Silicon sector is enabled.
Password Verify Command
The Password Verify Command is used to verify the Password. The Password is verifiable only
when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is pro-
grammed and the user attempts to verify the Password, the device always drives all F’s onto the
DQ data bus.
The Password Verify command is permitted if the Secured Silicon sector is enabled. Also, Simul-
taneous Read/Write operation is disabled when the Password Verify command is executed. Only
the password is returned regardless of the bank address. The lower two address bits (A0:A-1) are
valid during the Password Verify. Writing the Read/Reset command returns the device back to nor-
mal operation.
50
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Password Protection Mode Locking Bit Program Command
The Password Protection Mode Locking Bit Program Command programs the Password Protection
Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed,
the Password Protection Mode Locking Bit cannot be erased! If the Password Protection Mode
Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Pro-
gram command can be executed to improve the program margin. Once the Password Protection
Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry
is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the
Mode Locking Bit Program command is accomplished by writing the Read/Reset command.
The Password Protection Mode Locking Bit Program command is permitted if the Secured Silicon
sector is enabled.
Persistent Sector Protection Mode Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent
Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever
being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as pro-
grammed without margin, the Persistent Sector Protection Mode Locking Bit Program Command
should be reissued to improve program margin. By disabling the program circuitry of the Pass-
word Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of
operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program com-
mand is accomplished by writing the Read/Reset command.
The Persistent Sector Protection Mode Locking Bit Program command is permitted if the Secured
Silicon sector is enabled.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if
the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear com-
mand. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a
power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the
PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status
is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is
accomplished by writing the Read/Reset command.
The PPB Lock Bit Set command is permitted if the Secured Silicon sector is enabled.
DYB Write Command
The DYB Write command is used to set or clear a DYB for a given sector. The high order address
bits (A19–A11) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ
data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, re-
gardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware
reset. Exiting the DYB Write command is accomplished by writing the Read/Reset command.
The DYB Write command is permitted if the Secured Silicon sector is enabled.
Password Unlock Command
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked
for modification, thereby allowing the PPBs to become accessible for modification. The exact pass-
word must be entered in order for the unlocking function to occur. This command cannot be issued
any faster than 2 µs at a time to prevent a hacker from running through the all 64-bit combina-
tions in an attempt to correctly match a password. If the command is issued before the 2 µs
execution window for each portion of the unlock, the command is ignored.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
51
P r e l i m i n a r y
The Password Unlock function is accomplished by writing Password Unlock command and data to
the device to perform the clearing of the PPB Lock Bit. The password is 64 bits long, so the user
must write the Password Unlock command 2 times for a x32 bit data bus. A0 is used to determine
whether the 32 bit data quantity is used to match the upper 32 bits or lower 32 bits. Writing the
Password Unlock command is address order specific. In other words, for the x32 data bus config-
uration, the lower 32 bits of the password are written first and then the upper 32 bits of the
password are written. Writing out of sequence results in the Password Unlock not returning a
match with the password and the PPB Lock Bit remains set.
Once the Password Unlock command is entered, the RY/BY# pin goes LOW indicating that the
device is busy. Also, reading the small bank (25% bank) results in the DQ6 pin toggling, indicating
that the Password Unlock function is in progress. Reading the large bank (75% bank) returns ac-
tual array data. Approximately 1uSec is required for each portion of the unlock. Once the first
portion of the password unlock completes (RY/BY# is not driven and DQ6 does not toggle when
read), the Password Unlock command is issued again, only this time with the next part of the
password. The second Password Unlock command is the final command before the PPB Lock Bit
is cleared (assuming a valid password). As with the first Password Unlock command, the RY/BY#
signal goes LOW and reading the device results in the DQ6 pin toggling on successive read oper-
ations until complete. It is the responsibility of the microprocessor to keep track of the number
of Password Unlock commands (2 for x32 bus), the order, and when to read the PPB Lock bit to
confirm successful password unlock
The Password Unlock command is permitted if the Secured Silicon sector is enabled.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB. Each PPB is individually pro-
grammed (but is bulk erased with the other PPBs). The specific sector address (A19–A11) are
written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set
and the corresponding PPB is set for the sector, the PPB Program command does not execute and
the command times-out without programming the PPB.
The host system must determine whether a PPB is fully programmed by noting the status of DQ0
in the sixth cycle of the PPB Program command. If DQ0 = 0, the entire six-cycle PPB Program
command sequence must be reissued until DQ0 = 1.
All PPB Erase Command
The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually
erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However,
when the PPB erase command is written (60h) and A6 = 1, all Sector PPBs are erased in parallel.
If the PPB Lock Bit is set the ALL PPB Erase command does not execute and the command times-
out without erasing the PPBs. The host system must determine whether all PPB was fully erased
by noting the status of DQ0 in the sixth cycle of the All PPB Erase command. If DQ0 = 1, the entire
six-cycle All PPB Erase command sequence must be reissued until DQ0 = 1.
It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase com-
mand. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to
program the PPB at a later time. Also note that the total number of PPB program/erase cycles is
limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed.
The All PPB Erase command is permitted if the Secured Silicon sector is enabled.
DYB Write
The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at reset.
There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of
the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases.
52
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Since this is a volatile bit, removing power or resetting the device clears the DYBs. The bank ad-
dress is latched when the command is written.
The DYB Write command is permitted if the Secured Silicon sector is enabled.
PPB Lock Bit Set
The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit that is cleared
at reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the
value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs
or erases. Since this is a volatile bit, removing power or resetting the device clears the DYBs. The
bank address is latched when the command is written.
The PPB Lock command is permitted if the Secured Silicon sector is enabled.
DYB Status
PPB Status
The programming of the DYB for a given sector can be verified by writing a DYB status verify com-
mand to the device.
The programming of the PPB for a given sector can be verified by writing a PPB status verify com-
mand to the device.
PPB Lock Bit Status
The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit
status verify command to the device.
Non-volatile Protection Bit Program And Erase Flow
The device uses a standard command sequence for programming or erasing the Secured Silicon
Sector Protection, Password Locking, Persistent Sector Protection Mode Locking, or Persistent Pro-
tection Bits. Unlike devices that have the Single High Voltage Sector Unprotect/Protect feature,
the device has the standard two-cycle unlock followed by 60h, which places the device into non-
volatile bit program or erase mode. Once the mode is entered, the specific non-volatile bit status
is read on DQ0. Figure 4 on page 45 shows a typical flow for programming the non-volatile bit
and Figure 5 on page 48 shows a typical flow for erasing the non-volatile bits. The Secured Silicon
Sector Protection, Password Locking, Persistent Sector Protection Mode Locking bits are not
erasable after they are programmed. However, the PPBs are both erasable and programmable
(depending upon device security).
Unlike Single High Voltage Sector Protect/Unprotect, the A6 pin no longer functions as the pro-
gram/erase selector nor the program/erase margin enable. Instead, this function is accomplished
by issuing the specific command for either program (68h) or erase (60h).
In asynchronous mode, the DQ6 toggle bit indicates whether the program or erase sequence is
active. (In synchronous mode, ADV# indicates the status.) If the DQ6 toggle bit toggles with ei-
ther OE# or CE#, the non-volatile bit program or erase operation is in progress. When DQ6 stops
toggling, the value of the non-volatile bit is available on DQ0.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
53
P r e l i m i n a r y
Table 41. Memory Array Command Definitions
Bus Cycles (Notes 1–4)
Command (Notes)
First
Second
Third
Addr
Fourth
Addr
Fifth
Addr
Sixth
Addr
Addr
Data
RD
Addr
Data
Data
Data
Data
Data
Read (5)
1
1
4
RA
Reset (6)
XXX
555
F0
Manufacturer ID
Device ID (11)
AA
2AA
2AA
55
55
555
555
90
90
BA+X00
BA+X01
01
7E
09 for
32 Mb
36 or
Autoselect
(7)
6
555
AA
BA+X0E
BA+X0F
00/01
08 for
16 Mb
Program
4
6
6
1
1
1
2
3
4
3
2
2
1
2
555
555
555
BA
AA
AA
AA
B0
30
98
A0
AA
AA
AA
A0
80
98
90
2AA
2AA
2AA
55
55
55
555
555
555
A0
80
80
PA
PD
AA
AA
Chip Erase
Sector Erase
555
555
2AA
2AA
55
55
555
SA
10
30
Program/Erase Suspend (12)
Program/Erase Resume (13)
CFI Query (14, 15)
BA
55
Accelerated Program (16)
Configuration Register Verify (15)
Configuration Register Write (17)
Unlock Bypass Entry (18)
Unlock Bypass Program (18)
Unlock Bypass Erase (18)
Unlock Bypass CFI (14, 18)
Unlock Bypass Reset (18)
XX
PA
2AA
2AA
2AA
PA
PD
55
55
55
PD
10
555
555
555
XX
BA+555
555
C6
D0
20
BA+XX
XX
RD
WD
555
XX
XX
XX
XX
XX
00
RA = Read Address (Amax–A0).
RD = Read Data. Data DQmax–DQ0 at address location RA.
Legend:
BA = Bank Address. The set of addresses that comprise a bank. The
system may write any address within a bank to identify that bank for a
command.
SA = Sector Address. The set of addresses that comprise a sector. The
system may write any address within a sector to identify that sector
for a command.
PA = Program Address (Amax–A0). Addresses latch on the falling
edge of the WE# or CE# pulse, whichever happens later.
WD = Write Data. See Configuration Register on page 31 definition for
specific write data. Data latched on rising edge of WE#.
PD = Program Data (DQmax–DQ0) written to location PA. Data
latches on the rising edge of WE# or CE# pulse, whichever happens
first.
X = Don’t care
Notes:
1. See Table 27 on page 23 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are
write operations.
4. During unlock cycles, (lower address bits are 555 or 2AAh as
shown in table) address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
5. No unlock or command cycles required when bank is reading
array data.
6. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high
(while the bank is providing status information).
7. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID or device ID information. See Autoselect
Command on page 43 for more information.
8. This command cannot be executed until The Unlock Bypass
command must be executed before writing this command
sequence. The Unlock Bypass Reset command must be executed
to return to normal operation.
9. This command is ignored during any embedded program, erase
or suspended operation.
10. Valid read operations include asynchronous and burst read mode
operations.
11. The device ID must be read across the fourth, fifth, and sixth
cycles. 00h in the sixth cycle indicates ordering option 00, 01h
indicates ordering option 01.
12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Program/Erase Suspend
mode. The Program/Erase Suspend command is valid only
during a sector erase operation, and requires the bank address.
13. The Program/Erase Resume command is valid only during the
Erase Suspend mode, and requires the bank address.
14. Command is valid when device is ready to read array data or
when device is in autoselect mode.
15. Asynchronous read operations.
16. ACC must be at V during the entire operation of this command.
ID
17. Command is ignored during any Embedded Program, Embedded
Erase, or Suspend operation.
18. The Unlock Bypass Entry command is required prior to any
Unlock Bypass operation. The Unlock Bypass Reset command is
required to return to the read mode.
54
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Table 42. Sector Protection Command Definitions
Bus Cycles (Notes 1 – 4)
Command (Notes)
First
Second
Third
Addr
Fourth
Fifth
Addr
Sixth
Addr
Addr
Data
F0
Addr
Data
Data
Addr
Data
Data
Data
Reset
1
3
4
6
4
4
5
6
6
4
3
4
4
4
4
6
6
6
6
XXX
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
Secured Silicon Sector Entry
Secured Silicon Sector Exit
Secured Silicon Protection Bit Status
Password Program (5, 7, 8)
Password Verify
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
555
555
88
90
60
38
C8
28
60
60
90
78
58
48
48
58
60
60
60
60
XX
00
RD(0)
555
OW
555
PWA[0-1]
PWA[0-1]
PWA[0-1]
SG+WP
WP
PWD[0-1]
PWD[0-1]
PWD[0-1]
68
555
Password Unlock (7, 8)
PPB Program (5, 6)
All PPB Erase (5, 9, 10)
PPB Status (11, 12)
PPB Lock Bit Set
555
555
SG+WP
WP
48
40
SG+WP
WP
RD(0)
RD(0)
555
60
BA+555
555
SA+X02
00/01
PPB Lock Bit Status
DYB Write (7)
BA+555
555
SA
SA
SA
SA
PL
PL
SL
SL
RD(1)
X1
DYB Erase (7)
555
X0
DYB Status (12)
BA+555
555
RD(0)
68
PPMLB Program (5, 6)
PPMLB Status (5)
PL
SL
48
48
PL
SL
RD(0)
RD(0)
555
RD(0)
68
SPMLB Program (5, 6)
SPMLB Status (5)
555
555
RD(0)
Legend:
DYB = Dynamic Protection Bit
SA = Sector Address. The set of addresses that comprise a sector. The
system may write any address within a sector to identify that sector
for a command.
OW = Address (A5–A0) is (011X10).
PPB = Persistent Protection Bit
SG = Sector Group Address
PWA = Password Address. A0 selects between the low and high 32-bit
portions of the 64-bit Password
BA = Bank Address. The set of addresses that comprise a bank. The
system may write any address within a bank to identify that bank for a
command.
PWD = Password Data. Must be written over two cycles.
PL = Password Protection Mode Lock Address (A5–A0) is (001X10)
SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10)
WP = PPB Address (A5–A0) is (111010)
X = Don’t care
RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0= 1,
if unprotected, DQ0 = 0.
RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 =
1, if unprotected, DQ1 = 0.
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
Notes:
1. See Table 27 on page 23 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are
write operations.
4. During unlock cycles, (lower address bits are 555 or 2AAh as
shown in table) address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
8. The entire four bus-cycle sequence must be entered for each
portion of the password.
9. The fourth cycle erases all PPBs. The fifth and sixth cycles are
used to validate whether the bits were fully erased. If DQ0 (in
the sixth cycle) reads 1, the erase command must be issued and
verified again.
10. Before issuing the erase command, all PPBs should be
programmed in order to prevent over-erasure of PPBs.
11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not
set.
12. The status of additional PPBs and DYBs may be read (following
the fourth cycle) without reissuing the entire command
sequence.
5. The reset command returns the device to reading the array.
6. The fourth cycle programs the addressed locking bit. The fifth
and sixth cycles are used to validate whether the bit is fully
programmed. If DQ0 (in the sixth cycle) reads 0, the program
command must be issued and verified again.
7. Data is latched on the rising edge of WE#.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
55
P r e l i m i n a r y
Write Operation Status
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5,
DQ6, DQ7, and RY/BY#. Table 43 and the following subsections describe the functions of these
bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are discussed first.
DQ7: Data# Polling
The device features a Data# polling flag as a method to indicate to the host system whether the
embedded algorithms are in progress or are complete. During the Embedded Program Algorithm,
an attempt to read the bank in which programming was initiated produces the complement of the
data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to
read the device produces the true last data written to DQ7. Note that DATA# polling returns in-
valid data for the address being programmed or erased.
For example, the data read for an address programmed as 0000 0000 1000 0000b, returns XXXX
XXXX 0XXX XXXXb during an Embedded Program operation. Once the Embedded Program Algo-
rithm is complete, the true data is read back on DQ7. Note that at the instant when DQ7 switches
to true data, the other bits may not yet be true. However, they are all true data on the next read
from the device. Please note that Data# polling may give misleading status when an attempt is
made to write to a protected sector.
For chip erase, the Data# polling flag is valid after the rising edge of the sixth WE# pulse in the
six write pulse sequence. For sector erase, the Data# polling is valid after the last rising edge of
the sector erase WE# pulse. Data# polling must be performed at sector addresses within any of
the sectors being erased and not a sector that is a protected sector. Otherwise, the status may
not be valid. DQ7 = 0 during an Embedded Erase Algorithm (chip erase or sector erase operation),
but returns a 1 after the operation completes because it drops back into read mode.
In asynchronous mode, just prior to the completion of the Embedded Algorithm operations, DQ7
may change asynchronously while OE# is asserted low. (In synchronous mode, ADV# exhibits
this behavior.) The status information may be invalid during the instance of transition from status
information to array (memory) data. An extra validity check is therefore specified in the data poll-
ing algorithm. The valid array data on DQ31–DQ0 is available for reading on the next successive
read attempt.
The Data# polling feature is only active during the Embedded Programming Algorithm, Embedded
Erase Algorithm, Erase Suspend, Erase Suspend-Program mode, or sector erase time-out.
If the user attempts to write to a protected sector, Data# polling is activated for about 1 µs: the
device then returns to read mode, with the data from the protected sector unchanged. If the user
attempts to erase a protected sector, Toggle Bit (DQ6) is activated for about 150 µs; the device
then returns to read mode, without having erased the protected sector.
Table 43 shows the outputs for Data# Polling on DQ7. Figure 6 on page 57 shows the Data# Poll-
ing algorithm. Figure 23 shows the timing diagram for synchronous status DQ7 data polling.
RY/BY#: Ready/Busy#
The device provides a RY/BY# open drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or completed. If the output is low, the device is
busy with either a program, erase, or reset operation. If the output is floating, the device is ready
to accept any read/write or erase operation. When the RY/BY# pin is low, the device does not
accept any additional program or erase commands with the exception of the Erase suspend com-
mand. If the device enters Erase Suspend mode, the RY/BY# output is floating. For programming,
the RY/BY# is valid (RY/BY# = 0) after the rising edge of the fourth WE# pulse in the four write
pulse sequence. For chip erase, the RY/BY# is valid after the rising edge of the sixth WE# pulse
56
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
in the six write pulse sequence. For sector erase, the RY/BY# is also valid after the rising edge of
the sixth WE# pulse.
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector
selected for erasure. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5
Figure 6. Data# Polling Algorithm
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy)
until the internal reset operation is complete, which requires a time of tREADY (during Embedded
Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is
complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin
is floating), the reset operation is completed in a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RESET# pin returns to VIH.
Since the RY/BY# pin is an open-drain output, several RY/BY# pins can be tied together in parallel
with a pull-up resistor to VCC. An external pull-up resistor is required to take RY/BY# to a VIH level
since the output is an open drain.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
57
P r e l i m i n a r y
Table 43 shows the outputs for RY/BY#. Figures 15, 19, and 21 show RY/BY# for read, reset, pro-
gram, and erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete, or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at
any address, and is valid after the rising edge of the final WE# pulse in the command sequence
(prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, two immediately consecutive read
cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.
For asynchronous mode, either OE# or CE# can be used to control the read cycles. For synchro-
nous mode, the rising edge of ADV# is used or the rising edge of clock while ADV# is Low.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors
are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-
gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (See DQ7: Data# Polling on page 56).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the
program command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-
ded Program algorithm is complete.
Table 43 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit algorithm in
flowchart form, and Reading Toggle Bits DQ6/DQ2 on page 59 explains the algorithm. Figure 24
shows the toggle bit timing diagrams. Figure 24 shows the differences between DQ2 and DQ6 in
graphical form. Also see DQ2: Toggle Bit II on page 58. Figure 24 shows the timing diagram for
synchronous toggle bit status.
DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-
suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command
sequence.
DQ2 toggles when the system performs two immediately consecutive reads at addresses within
those sectors that were selected for erasure. (For asynchronous mode, either OE# or CE# can be
used to control the read cycles. For synchronous mode, ADV# is used.) But DQ2 cannot distin-
guish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates
whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sec-
tors are selected for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 43 to compare outputs for DQ2 and DQ6.
Toggle bit algorithm in is shown in Figure 7 in flowchart form, and the algorithm is explained in
Reading Toggle Bits DQ6/DQ2 on page 59. Also see DQ6: Toggle Bit I on page 58. Figure 24
shows the toggle bit timing diagram. Figure 25 shows the differences between DQ2 and DQ6 in
graphical form. Figure 26 shows the timing diagram for synchronous DQ2 toggle bit status.
58
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Reading Toggle Bits DQ6/DQ2
Refer to Figure 24 for the following discussion. Whenever the system initially begins reading tog-
gle bit status, it must perform two immediately consecutive reads of DQ7–DQ0 to determine
whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle
bit after the first read. After the second read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling, the device completed the program or erase
operation. The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two immediately consecutive read cycles, the system determines that
the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (See
DQ5: Exceeded Timing Limits on page 60). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5
went high. If the toggle bit is no longer toggling, the device successfully completed the program
or erase operation. If it is still toggling, the device did not complete the operation successfully,
and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and
DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through suc-
cessive read cycles, determining the status as described in the previous paragraph. Alternatively,
it may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation (top of Figure 7).
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
59
P r e l i m i n a r y
START
Read Byte
(DQ0-DQ7)
Address = VA
Read Byte
(Note 1)
(DQ0-DQ7)
Address = VA
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ 0-DQ7)
Adrdess = VA
(Notes 1, 2)
No
DQ6 = Toggle?
Yes
FAIL
PASS
Notes:
1. Read toggle bit with two immediately consecutive reads to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1.
Figure 7. Toggle Bit Algorithm
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program
or erase cycle was not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a location that is pre-
viously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this
condition, the device halts the operation, and when the operation exceeds the timing limits, DQ5
produces a 1.
Under both these conditions, the system must issue the reset command to return the device to
reading array data.
60
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether
or not an erase operation started. (The sector erase timer does not apply to the chip erase com-
mand.) If additional sectors are selected for erasure, the entire time-out also applies after each
additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The
system may ignore DQ3 if the system can guarantee that the time between additional sector
erase commands is always less than 50 µs. Also see Sector Erase Command on page 46.
After the sector erase command sequence is written, the system should read the status on DQ7
(Data# Polling) or DQ6 (Toggle Bit I) to ensure the device accepted the command sequence, and
then read DQ3. If DQ3 is 1, the internally controlled erase cycle started; all further commands
(other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the
device accepts additional sector erase commands. To ensure the command is accepted, the sys-
tem software should check the status of DQ3 prior to and following each subsequent sector erase
command. If DQ3 is high on the second status check, the last command might not have been
accepted. Table 43 shows the outputs for DQ3.
Table 43. Write Operation Status
DQ7
(Note 2)
DQ5
(Note 1)
DQ2
(Note 2)
Operation
DQ6
DQ3
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
N/A
1
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend
Mode
Reading within Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See
DQ5: Exceeded Timing Limits for more information.
2. DQ7 and DQ2 require a valid address when reading status information. See DQ7: Data# Polling and DQ2: Toggle Bit II
for further details.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
61
P r e l i m i n a r y
Absolute Maximum Ratings
Storage Temperature, Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +145°C
VCC, VIO (Note 1, Note 5) . . . . . . . . . . . . . -0.5 V to + 3.0V (16Mb), -0.5V to + 2.75V (32Mb)
ACC, A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +13.0 V
Address, Data, Control Signals
Except CLK (Note 1, Note 6) . . . . . . . . . . . . -0.5V to 3.6V (16 Mb), –0.5 V to 2.75 V (32 Mb)
All other pins (Note 1, Note 6). . . . . . . . . . . . -0.5V to 3.6V (16 Mb),–0.5 V to 2.75 V (32 Mb)
Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input at I/O pins may overshoot V to
SS
-2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on output and I/O pins is 3.6V (16Mb), 2.75V
(32Mb). During voltage transitions output pins may overshoot to V + 2.0V for periods up to 20 ns. See Figure 9.
CC
2. Minimum DC input voltage on pins ACC, A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot V to -2.0V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on pin A9 and
SS
OE# is +13.0 V which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than
one second.
4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
5. Parameter describes V power supply.
IO
6. Parameter describes I/O pin voltage tolerances.
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 8. Maximum Negative Overshoot Waveform
20 ns
V
V
CC +2.0 V
CC +0.5 V
2.0 V
20 ns
20 ns
Figure 9. Maximum Positive Overshoot Waveform
62
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C
V
Supply Voltages
CC
VCC for 2.6 V regulated voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.50 V to 2.75 V
V
Supply Voltages
IO
VIO
. . . . . . . . . . . . . . . . . . . . . . . . . . 1.65 V to 3.6 V (16 Mb), 1.65 V to 2.75 V (32 Mb)
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
63
P r e l i m i n a r y
DC Characteristics
CMOS Compatible
Parameter
Description
Input Load Current
Test Conditions
Min
Typ
Max
±1.0
–25
35
Unit
I
V
V
V
V
= V to V , V = V
IN SS IO IO
LI
IO max
= V to V , V = V
IN SS IO IO IO max
I
WP# Input Load Current
A9, ACC Input Load Current
Output Leakage Current
LIWP
µA
I
= V
; A9 = 12.5 V
CCmax
LIT
CC
OUT
I
= V to V , V = V
±1.0
LO
SS
CC
CC
CC max
56 MHz
CE# = V
OE# = V
,
8 Double
Word
IL
IL
I
V
Active Burst Read Current (1)
Active Asynchronous
70
90
10
CCB
CC1
CC
66, 75 MHz
V
CC
I
CE# = V , OE# = V
1 MHz
mA
IL
IL
Read Current (1)
I
I
I
V
V
V
V
Active Program Current (2, 4) CE# = V , OE# = V , ACC = V
40
20
50
50
60
CC3
CC4
CC5
CC
CC
CC
CC
IL
IH
IH
IH
Active Erase Current (2, 4)
Standby Current (CMOS)
Active Current
CE# = V , OE# = V , ACC = V
IL
IH
V
= V
, CE# = V ± 0.3 V
µA
CC
CC max
CC
I
CE# = V , OE# = V
IL
30
90
mA
CC6
IL
(Read While Write)
I
I
I
V
Reset Current ()
RESET# = V
IL
60
60
µA
µA
CC7
CC8
ACC
CC
Automatic Sleep Mode Current
Acceleration Current
V
= V ± 0.3 V, V = V ± 0.3 V
IH CC IL SS
V
ACC = V
20
mA
ACC
HH
V
Input Low Voltage
–0.5
0.7 x V
–0.2
0.3 x V
IL
IO
V
Input High Voltage
V
CC
IH
IO
V
CLK Input Low Voltage
CLK Input High Voltage
Voltage for Autoselect
Output Low Voltage
0.3 x V
2.75
ILCLK
IHCLK
IO
V
V
0.7 x V
11.5
CC
V
V
= 2.5 V
12.5
ID
CC
V
I
= 4.0 mA, V = V
CC
0.45
OL
OL
CC min
I
RY/BY#, Output Low Current
Accelerated (ACC pin) High Voltage
Output High Voltage
V
= 0.4 V
8
mA
V
OLRB
OL
OH
OH
V
V
I
I
= –2.0 mA, V = V
0.85 x V
CC
HH
OH
CC
CC min
= –100 µA, V = V
V
–0.1
CC
CC min
IO
V
Low V Lock-Out Voltage (3)
1.6
2.0
LKO
CC
Notes:
1. The I current listed includes both the DC operating current and the frequency dependent component.
CC
2.
3. Not 100% tested.
4. Maximum I specifications are tested with V = V .
CCmax
I
active while Embedded Erase or Embedded Program is in progress.
CC
CC
CC
64
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
DC Characteristics
Zero Power Flash
4
3
2
1
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 10.
I
Current vs. Time (Showing Active and Automatic Sleep Currents)
CC1
5
2.7 V
4
3
2
1
0
1
2
3
4
5
Frequency in MHz
Figure 11. Typical I
vs. Frequency
CC1
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
65
P r e l i m i n a r y
Test Conditions
Device
Under
Test
C
L
Note: Diodes are IN3064 or equivalent
Figure 12. Te s t Se t up
Test Specifications
Table 44. Test Specifications
Test Condition
40 MHz, 56 MHz
66 MHz, 75MHz
1 TTL gate
Unit
Output Load
Output Load Capacitance, C (including jig capacitance)
L
30
100
pF
ns
Input Rise and Fall Times
5
Input Pulse Levels
0.0 V – V
IO
Input timing measurement reference levels
Output timing measurement reference levels
V
V
/2
V
IO
IO
/2
Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
Switching Waveforms
VIO
VIO/2 V
VIO/2 V
Input
Measurement Level
Output
VSS
Figure 13. Input Waveforms and Measurement Levels
66
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
AC Characteristics
VCC and VIO Power-up
Parameter
Description
Test Setup
Speed
Unit
t
V
Setup Time
Setup Time
IO
VCS
CC
t
V
Min
50
µs
VIOS
RSTH
t
RESET# Low Hold Time
tVCS
VCC
tVIOS
VIOP
tRSTH
RESET#
Figure 14.
V
and V Power-up Diagram
CC IO
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
67
P r e l i m i n a r y
AC Characteristics
Asynchronous Read Operations
Parameter
Speed Options
Description
JEDEC Std.
Test Setup
Unit
75 MHz, 66 MHz, 56 MHz, 40 MHz,
0R
0P
0M
OJ
t
t
Read Cycle Time (Note 1)
Address to Output Delay
Min
48
54
64
67
AVAV
AVQV
RC
CE# = V
IL
IL
t
t
Max
48
52
54
64
69
67
ACC
OE# = V
t
t
Chip Enable to Output Delay
Output Enable to Output Delay
OE# = V
Max
Max
58
20
71
28
ELQV
CE
IL
t
t
t
GLQV
OE
Chip Enable to Output High Z
Note 1
t
t
Max
10
EHQZ
DF
DF
ns
Min
Max
Min
Min
2
10
0
t
Output Enable to Output High Z Note 1
GHQZ
Read
t
Output Enable Hold Time Note 1
OEH
Toggle and Data# Polling
10
Output Hold Time From Addresses, CE# or OE#, Whichever
Occurs First Note 1
t
t
Min
2
AXQX
OH
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 44 for test specifications
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
High Z
High Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 15. Conventional Read Operations Timings
68
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
AC Characteristics
Burst Mode Read for 32 Mb & 16 Mb
Parameter
Speed Options
75 MHz,
0R
32 MHz
Description
JEDE
Unit
66 MHz,
0P
56 MHz,
0M
40 MHz,
OJ
Std.
C
9 FBGA
9.5 PQFP
10 FBGA
10 PQFP
t
Burst Access Time Valid Clock to Output Delay
Max 7.5 FBGA
17
BACC
t
ADV# Setup Time to Rising Edge of CLK
ADV# Hold Time from Rising Edge of CLK
ADV# Pulse Width (32Mb, 75MHz)
Min
Min
Min
Min
5.75
1.5
12
6
ADVCS
t
2
ADVCH
t
13
15
22
17
ADVP
t
Valid Data Hold from CLK (Note Note:)
2
2
3
3
DVCH
9 FBGA
9.5 PQFP
10 FBGA
10 PQFP
t
CLK to Valid IND/WAIT#
Max 7.5 FBGA
Min
DIND
INDH
t
IND/WAIT# Hold from CLK
t
CLK to Valid Data Out, Initial Burst Access
Max
Min
Max
Max
Max
Min
Min
Min
48
54
15
64
18
67
25
IACC
13.
t
CLK Period
CLK
60
3
t
CLK Rise Time
CLKR
t
CLK Fall Time
3
CLKF
ns
t
CLK Low Time
2
2
2.5
2.5
6
3
3
CKL
t
CLK to High Time
CE# Setup Time to Clock
CLKH
t
CES
16 Mb =3
32 Mb = 8
t
CE# Hold Time
Min
Min
Min
CH
t
Address Setup Time to CLK
6
5
ACS
ACH
Address Hold Time from ADV# Rising
Edge of CLK while ADV# is Low
t
t
Output Enable to Output Valid
Max
Min
Max
Max
Min
Min
20
28
3
OE
2
2
3
t
t
Output Enable to Output High Z (Note Note:)
DF
OEZ
7.5
7.5
10
10
15
15
17
17
t
t
Chip Enable to Output High Z (Note Note:)
WE hold time after ADV falling edge
EHQZ
CEZ
t
0
5
WADVH
t
WE rising edge setup time to clock rising edge
WCKS
Note: Not 100% tested.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
69
P r e l i m i n a r y
AC Characteristics
tCEZ
tCES
CE#
CLK
tADVCS
ADV#
tADVCH
tACS
Aa
Addresses
Data
tDVCH
tBACC
tACH
Da
Da + 1
tIACC
Da + 2
Da + 3
Da + 31
tOE
tOEZ
OE#*
IND#
Figure 16. Burst Mode Read
CLK
ADV#
CE#
tCS
tCH
Stable Address
tWC
Addresses
Data
Valid Data
tAH
tAS
tDH
tDS
WE#
OE#
tOEH
tWPH
IND/WAIT#
Figure 17. Asynchronous Command Write Timing
Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/
RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are burst
mode when the burst mode option is enabled in the Configuration Register.
70
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
AC Characteristics
CE#
tCES
CLK
tADVCS
tADVP
ADV#
tACS
tACH
tACH
Valid Address
tWC
t
ACS
Addresses
Valid Address
tEHQZ
tADVCH
Data In
tWADVH
Data Out
Data
tDF
tWCKS
tDH
tOE
OE#
WE#
tDS
tWP
10 ns
IND/WAIT#
Figure 18. Synchronous Command Write/Read Timing
Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/
RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are burst
mode when the burst mode option is enabled in the Configuration Register.
Hardware Reset (RESET#)
Parameter
JEDEC Std.
Test
Setup
All Speed
Options
Description
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note)
t
t
Max
Max
11
µs
ns
READY
READY
RESET# Pin Low (NOT During Embedded Algorithms)
to Read or Write (See Note)
500
t
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
RP
t
RESET# High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
RH
t
RPD
t
RB
Note: Not 100% tested.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
71
P r e l i m i n a r y
AC Characteristics
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timing to Bank NOT Executing Embedded Algorithm
Reset Timing to Bank Executing Embedded Algorithm
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 19. RESET# Timings
Program/Erase Command
Data
WE#
tDS
tDH
tWP
tWPWS
Valid WP#
WP#
tCH
tWPRH
RY/BY#
Figure 20. WP# Timing
72
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
AC Characteristics
Erase/Program Operations
Parameter
All Speed Options
Description
JEDEC
Std.
Unit
t
t
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
Min
Min
Min
60
0
AVAV
AVWL
WLAX
WC
t
t
t
AS
AH
DS
DH
t
t
Address Hold Time
25
18
2
t
t
Data Setup to WE# Rising Edge
Data Hold from WE# Rising Edge
DVWH
WHDX
t
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
Min
0
GHWL
GHWL
t
t
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Min
Min
Max
Min
Min
0
2
ELWL
WHEH
WLWH
WHWL
CS
CH
WP
t
t
CE# Hold Time
t
t
t
WE# Width
25
30
18
1.0
50
0
t
Write Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
WPH
t
t
t
t
Double-Word
µs
sec.
µs
WHWH1
WHWH2
WHWH1
WHWH2
t
V
Setup Time (Note 1)
CC
VCS
t
Recovery Time from RY/BY#
RB
t
RY/BY# Delay After WE# Rising Edge
WP# Setup to WE# Rising Edge with Command
WP# Hold after RY/BY# Rising Edge
90
20
2
BUSY
ns
t
WPWS
t
WPRH
Notes:
1. Not 100% tested.
2. See Command Definitions for more information.
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Statu
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, D
is the true data at the program address.
OUT
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
73
P r e l i m i n a r y
AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status).
Figure 21. Chip/Sector Erase Operation Timings
tWC
Valid PA
tWC
tRC
tWC
Valid PA
tAH
Valid RA
Valid PA
Addresses
tCPH
tACC
tCE
CE#
OE#
tCP
tOE
tOEH
tGHWL
tWP
tWPH
WE#
Data
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE# Controlled Write Cycles
Figure 22. Back-to-Back Cycle Timings
74
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
AC Characteristics
tWC
VA
tRC
VA
Addresses
VA
tACC
tCE
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Data
Valid Data
Complement
Complement
True
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 23. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last sta-
tus read cycle, and array data read cycle.
Figure 24. Toggle Bit Timings (During Embedded Algorithms)
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
75
P r e l i m i n a r y
AC Characteristics
Enter Embedded
Erasing
WE#
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase Suspend
Read
Erase Suspend Erase Suspend
Program Read
Erase
Erase
Complete
Erase
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 25. DQ2 vs. DQ6 for Erase/Erase Suspend Operations
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tOE
tOE
Data
Status Data
Status Data
RDY
Notes:
1. The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, the toggle bits stop toggling.
3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is
active one clock cycle before data.
4. Data polling requires burst access time delay.
Figure 26. Synchronous Data Polling Timing/Toggle Bit Timings
76
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
AC Characteristics
V
IH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Protect/Unprotect
Verify
Data
60h
60h/68h**
40h/48h***
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* Valid address for sector protect: A[7:0] = 3Ah. Valid address for sector unprotect: A[7:0] = 3Ah.
** Command for sector protect is 68h. Command for sector unprotect is 60h.
*** Command for sector protect verify is 48h. Command for sector unprotect verify is 40h.
Figure 27. Sector Protect/Unprotect Timing Diagram
Alternate CE# Controlled Erase/Program Operations
Parameter
Description
All Speed
Options
Unit
JEDEC
Std.
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
65
0
AVAV
WC
t
t
t
AVEL
ELAX
AS
AH
DS
DH
t
t
45
35
2
t
t
Data Setup Time
DVEH
EHDX
t
Data Hold Time
t
Output Enable Setup Time
Read Recovery Time Before Write (OE# High to WE# Low)
WE# Setup Time
OES
ns
t
t
t
GHEL
GHEL
0
t
WLEL
WS
WH
t
t
WE# Hold Time
EHWH
t
WE# Width
32
16
30
18
1
WP
t
t
CE# Pulse Width
ELEH
EHEL
CP
t
t
CE# Pulse Width High
CPH
t
t
t
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
Double-Word
µs
WHWsH1
WHWH1
WHWH2
t
sec.
WHWH2
Notes:
1. Not 100% tested.
2. See Command Definitions for more information.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
77
P r e l i m i n a r y
AC Characteristics
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
PA
Addresses
tWC
tAS
tAH
tWPH
tWH
tWP
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D
= data
OUT
written to the device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 28. Alternate CE# Controlled Write Operation Timings
78
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Erase and Programming Performance
Typ
(Note 1)
Max
(Note 2)
Parameter
Sector Erase Time
Unit
Comments
1.0
5
s
s
Excludes 00h programming prior to erasure (Note 4)
16 Mb = 46
32 Mb = 78
16 Mb = 230
32 Mb = 460
Chip Erase Time
Double Word Program Time
18
8
250
130
µs
µs
Accelerated Double Word Program Time
16 Mb = 5
32 Mb = 10
16 Mb = 50
32 Mb = 100
Excludes system level overhead (Note 5)
Accelerated Chip Program Time
Chip Program Time (Note 3)
Notes:
s
s
16 Mb = 12
32 Mb = 24
16 Mb = 120
32 Mb = 240
x32
1. Typical program and erase times assume the following conditions: 25°C, 2.5 V V , 100K cycles. Additionally,
CC
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 145°C, V = 2.5 V, 1M cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
See Table 41 and Table 42 for further information on command definitions.
6. PPBs have a program/erase cycle endurance of 100 cycles.
Latchup Characteristics
Description
Input voltage with respect to V on all pins except I/O pins (including A9, ACC, and WP#)
Min
Max
–1.0 V
–1.0 V
–100 mA
12.5 V
SS
Input voltage with respect to V on all I/O pins
V
+ 1.0 V
CC
SS
V
Current
+100 mA
CC
Note: Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.
CC
CC
PQFP and Fortified BGA Pin Capacitance
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
Typ
6
Max
Unit
pF
C
V
= 0
= 0
= 0
7.5
12
9
IN
IN
C
Output Capacitance
V
8.5
7.5
pF
OUT
OUT
C
Control Pin Capacitance
V
pF
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
79
P r e l i m i n a r y
Revision Summary
S29CD016G Revision History
Revision A1 (March 22, 2004)
Performance Characteristics
Burst Mode Read: changed to 66-MHz.
Ordering Information
Changed device number/description call out to show the two 16-Mbit
configurations.
Table 12 and Table 13
Corrected which sectors report to which bank.
Asynchronous Read Operations Table
Removed the OR Speed option.
Revision A2 (May 24, 2004)
“Spansion” logo
Replaces AMD in bullet seven, first column.
Fujitsu MBM29LV and MBM129F
Added to bullet ten, first column.
Ultra Low Power Consumption Bullet
“capable of...” deleted from first bullet, second column.
Block diagram
Reset# moved, RY/BY added.
Simultaneous Read/Write Circuit Block Diagram
RY/BY added; Bank 1 added; Bank 0 added.
Pin Configuration
“A pull-up resistor of 10k...” added to RY/BY#.
Ordering Information
Additional ordering options updated to “protects sectors 44 and 45”.
Device Number/Description
Bit description altered.
Simultaneous Read/Write Operation With Zero Latency
Table 3 and 4 Bank # change.
Auto Select Mode
Table 5: Manufacturer ID Row updated (A3, A2).
Table 5: DQ7 to DQ0 Column updated.
80
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Linear Burst Read Operations
Table 6: “(x16)” removed from header row.
IND/Wait# Operation in Linear Mode
Figure 2 - “Address 2” removed.
Initial Burst Access Delay Control
Figure 3 - Valid Address line changed.
Notes - Clock cycles updated.
Configuration Register
Table 9: CR14 reserve bit assigned ASD.
Table 9: Speed options changed.
Table 10: CR14 reserve changed to ASD.
Table12. Sector Addresses for Ordering Option 00
Bank changed to 0.
Bank changed to 1.
Table 13. Sector Addresses for Ordering Option 01
Bank changed to 0.
Bank changed to 1.
Table 16. Device Geometry Definition
0005 = supports x16 and x32 via WORD#...” Removed.
Unlock Bypass Command Sequence
Table “18” replaced with “19” in text.
Table 19. Memory Array Command Definitions (x32 Mode)
Autoselect (7) - Device ID (11); Fifth/Data changed to “36”.
Table 20. Sector Protection Command Definitions (x32 Mode)
PBB Status (11,12) Third/Addr changed to “SG”. PPB Lock Bit Status; Third/Addr
“BA” removed. DYB Status; Third/Addr changed to “SA”.
Absolute Maximum Ratings
Address, Data... changed to 3.6v.
Table 22 CMOS Compatible
Input High Voltage Max changed to 3.6. RY/BY#, OUtput Low Current Min re-
moved, Max added (8).
Table 23. Test Specifications
Test conditions changed to OJ,OM,OP.
AC Characteristics
Figure 14 updated RESET#.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
81
P r e l i m i n a r y
Table number 24. Asynchronous Read Operations
OM speed options; Output Enable to Output Delay “20” added.
Table 26. Hardware Reset
Last row deleted.
Erase/Program Operations
TWADVH row added. TWCKS row added.
Table 27. Alternate CE# Controlled Erase/Program Operations
TWPH row added, TWADVH row added, TWCKS row added.
Physical Dimensions
Latchup characteristics deleted.
Pin Description
“WAIT# Provides data valid feedback only when the burst length is set to
continuous.” Removed from document.
Revision A3 (May 26, 2004)
Block Diagram on page 6
Moved RESET# to point to the State Control/Command Register.
Figure 2, on page 22
Updated note added “Double-Word” to figure title.
Table 9, “Configuration Register Definitions,” on page 24
Added “CR14 = Automatic Sleep Mode...” configurations.
Table 1, “Sector Addresses for Ordering Option 00,” on page 33
Re-inserted previously missing data.
Removed “Note 1” from Sector SA1.
Added “Note 3” to Sector SA44 and SA45.
Moved Sectors SA15 - SA30 to Bank 1.
Table on page 35
Added “Note 3” to Sector SA45.
Revision A4 (November 5, 2004)
Global
Added reference links
Added Colophon
Updated Trademark
Product Selector Guide
Removed note from Product Selector Guide table
82
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Block Diagram
Changed text on Input/Output buffers to show DQ0 to DQ31
Pin Configuration
Changed text in ACC description
Accelerated Program and Erase Operations
Changed text in this paragraph
Table 5
Change Address text column.
SecSi Sector Entry Command
Changed address text in this paragraph
Figure 18
t
Changed time spec call out from 10 ns to WADVH2
Table 27
t
Added new row for WADVH2
Rev History Family Data sheet Rev A (July 18, 2005)
Global
Merged S29CD016G and S29CD032G datasheets into one family CD-G datasheet
Changed datasheet status to "Preliminary Information"
Added in 75MHz parameters
Ordering Information
Model numbers (character 15th & 16th) changed to reflect mask revision, autoselect code and
top/bottom boot
Added GT Grade under Temperature Range and Quality Grade
Added note to "Refer to the KGD Datasheet supplement for die/wafer sales"
Product Selector Guide
Changed Min. Initial clock Delay values
Memory Map and Sector Protect Groups
Modified Notes 1 & 3
Add in Note 4
Simultaneous Read/Write Operation
Removed Table 2: Bank Assignment for Boot Bank Sector Deivice
Removed Table 3: Ordering Option 00
Removed Table 4: Ordering Option 01
Secured Silicon Sector
Added in Electronic Marking
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
83
P r e l i m i n a r y
Common Flash Memory Interface
Updated website to reflect Spansion.com
Changed address 28h from 0003h to 0005h
Command Definitions
Remove Secured Silicon Protection Bit Program command
Absolute Maximum Ratings
Changed Overshoot/Undershoot to be ± 0.7V from ± 2.0V
Changed Address, Data, Control Signals to -0.5V to 3V for 16Mb
Operating Ranges
Changed VIO to 1.65V to 3.6V
Burst Mode Read for 32Mb & 16 Mb
Changed tADVCS = 5.75ns for 75MHz
Changed tADVCH to be 2ns for 66MHz, 56MHz, 40 MHz
Changed tIACC values
Rounded tCLK values
Changed tCR to tCLKR
Changed tCF to tCLKF
Changed tCL to tCLKL
Changed tCH to tCLKH and changed values
Removed tDS, tDH, tAS, tAH, tCS
Added tWADVH, tWCKS
Erase/Program Operations
Removed tWCKS
Alternative CE# Controlled Erase/Program Operations
Added tWADVH
Added tWCKS
Rev History Family Datasheet Rev B0 (November 14, 2005)
Absolute Maximum Ratings
Changed under/overshoot to ± 2.0V
Changed Vcc, VIO values
Changed Address, Data, Control Signal values
Note 5 & 6
Revision History
Added in previous revision histories.
Erase/Program Operations
Added Note 1 to tWC and tVCS
84
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Global
Changed SecSi to Secured Silicon.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-
tioned uses of the products. Any semiconductor device has an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and
product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
November 14, 2005 S29CD-G_00_B0
S29CD-G Flash Family
85
相关型号：
S29CD032G0JQAM112
32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
SPANSION
S29CD032G0JQAM200
32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
SPANSION
S29CD032G0JQAM202
32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
SPANSION
S29CD032G0JQAM210
32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
SPANSION
S29CD032G0JQAM212
32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
SPANSION
S29CD032G0JQAN000
CMOS 2.5 VOLT ONLY BURST MODE DUAL BOOT, SIMULTANEOUS READ /WRITE FLASH MEMORY
SPANSION
S29CD032G0JQAN002
CMOS 2.5 VOLT ONLY BURST MODE DUAL BOOT, SIMULTANEOUS READ /WRITE FLASH MEMORY
SPANSION
S29CD032G0JQAN003
CMOS 2.5 VOLT ONLY BURST MODE DUAL BOOT, SIMULTANEOUS READ /WRITE FLASH MEMORY
SPANSION
S29CD032G0JQAN010
CMOS 2.5 VOLT ONLY BURST MODE DUAL BOOT, SIMULTANEOUS READ /WRITE FLASH MEMORY
SPANSION
S29CD032G0JQAN012
CMOS 2.5 VOLT ONLY BURST MODE DUAL BOOT, SIMULTANEOUS READ /WRITE FLASH MEMORY
SPANSION
S29CD032G0JQAN013
CMOS 2.5 VOLT ONLY BURST MODE DUAL BOOT, SIMULTANEOUS READ /WRITE FLASH MEMORY
SPANSION
©2020 ICPDF网 联系我们和版权申明