S29GL032A11FAIR13 [SPANSION]
64 MEGABIT 32MEGABIT 3.0 BOLT ONLY PAGE MODE FLASH MEMORY; 64兆位32MEGABIT 3.0 BOLT单页面模式闪存型号: | S29GL032A11FAIR13 |
厂家: | SPANSION |
描述: | 64 MEGABIT 32MEGABIT 3.0 BOLT ONLY PAGE MODE FLASH MEMORY |
文件: | 总88页 (文件大小:1198K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADVANCE
INFORMATION
S29GLxxxA MirrorBit™ Flash Family
S29GL064A, S29GL032A
64 Megabit, 32 Megabit 3.0, Volt-only Page Mode Flash
Memory Featuring 200 nm MirrorBit Process Technology
Data Sheet
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S29GLxxxA_00 Revision A Amendment 2 Issue Date January 28, 2005
This page intentionally left blank.
S29GLxxxA MirrorBit™ Flash Family
S29GL064A, S29GL032A
64 Megabit, 32 Megabit 3.0, Volt-only Page Mode Flash
Memory Featuring 200 nm MirrorBit Process Technology
ADVANCE
INFORMATION
Data Sheet
Distinctive Characteristics
Package options
— 48-pin TSOP
— 56-pin TSOP
— 64-ball Fortified BGA
— 48-ball fine-pitch BGA
Architectural Advantages
Single power supply operation
— 3 volt read, erase, and program operations
Manufactured on 200 nm MirrorBit process
technology
Secured Silicon Sector region
Software & Hardware Features
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
Flexible sector architecture
— 64Mb (uniform sector models): 128 32 Kword (64 KB)
sectors
— 64Mb (boot sector models): 127 32 Kword (64 KB)
sectors + 8 4Kword (8KB) boot sectors
— Unlock Bypass Program command reduces overall
multiple-word programming time
— 32Mb (uniform sector models): 64 32Kword (64KB)
sectors
Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of
charging code in locked sectors
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings on uniform
sector models
— 32Mb (boot sector models): 63 32Kword (64KB)
sectors + 8 4Kword (8KB) boot sectors
Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
100,000 erase cycles typical per sector
20-year data retention typical
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
Performance Characteristics
High performance
— 90 ns access time
— 4-word/8-byte page read buffer
— 25 ns page read times
— 16-word/32-byte write buffer which reduces overall
programming time for multiple-word updates
Low power consumption (typical values at 3.0 V, 5
MHz)
— 18 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
Publication Number S29GLxxxA_00 Revision A Amendment 2 Issue Date January 28, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e I n f o r m a t i o n
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, in-
cluding development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to high-
light their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more spe-
cific products, but has not committed any design to production. Information presented in a doc-
ument with this designation is likely to change, and in some cases, development on the product
may discontinue. Spansion LLC therefore places the following conditions upon Advance Informa-
tion content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the prod-
uct life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these as-
pects of production under consideration. Spansion places the following conditions upon Prelimi-
nary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-
tions due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance In-
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or V range. Changes
IO
may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
2
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
General Description
The S29GLxxxA family of devices are 3.0 V single power Flash memory manufac-
tured using 200 nm MirrorBit technology. The S29GL064A is a 64 Mb, organized
as 4,194,304 words or 8,388,608 bytes. The S29GL032A is a 32 Mb, organized
as 2,097,152 words or 4,194,304 bytes. Depending on the model number, the
devices have an 8-bit wide data bus only, 16-bit wide data bus only, or a 16-bit
wide data bus that can also function as an 8-bit wide data bus by using the BYTE#
input. The devices can be programmed either in the host system or in standard
EPROM programmers.
Access times as fast as 90 ns are available. Note that each access time has a spe-
cific operating voltage range (VCC) as specified in the Product Selector Guide and
the Ordering Information sections. Package offerings include 48-pin TSOP, 56-pin
TSOP, 48-ball fine-pitch BGA and 64-ball Fortified BGA, depending on model num-
ber. Each device has separate chip enable (CE#), write enable (WE#) and output
enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and
write functions. In addition to a VCC input, a high-voltage accelerated program
(ACC) feature provides shorter programming times through increased current on
the WP#/ACC input. This feature is intended to facilitate factory throughput dur-
ing system production, but may also be used in the field if desired.
The device is entirely command set compatible with the JEDEC single-power-
supply Flash standard. Commands are written to the device using standard mi-
croprocessor write timing. Write cycles also internally latch addresses and data
needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#
(RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead
by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low VCC detector that automat-
ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause an
erase operation in a given sector to read or program any other sector and then
complete the erase operation. The Program Suspend/Program Resume fea-
ture enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would thus also reset the device,
enabling the host system to read boot-up firmware from the Flash memory
device.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
3
A d v a n c e I n f o r m a t i o n
The device reduces power consumption in the standby mode when it detects
specific voltage levels on CE# and RESET#, or when addresses have been stable
for a specified period of time.
The Write Protect (WP#) feature protects the first or last sector by asserting
a logic low on the WP#/ACC pin or WP# pin, depending on model number. The
protected sector will still be protected even during accelerated programming.
The Secured Silicon Sector provides a 128-word/256-byte area for code or
data that can be permanently protected. Once this sector is protected, no further
changes within the sector can occur.
Spansion MirrorBit flash technology combines years of Flash memory manufac-
turing experience to produce the highest levels of quality, reliability and cost
effectiveness. The device electrically erases all bits within a sector simultaneously
via hot-hole assisted erase. The data is programmed using hot electron injection.
4
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Table of Contents
Write Pulse “Glitch” Protection ...............................................................38
Logical Inhibit ...................................................................................................38
Power-Up Write Inhibit ...............................................................................38
General Description . . . . . . . . . . . . . . . . . . . . . . . . .3
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .7
S29GL064A, S29GL032A ....................................................................................7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic Symbol-S29GL064A (Model R6, R7) .................................................. 14
Common Flash Memory Interface (CFI) . . . . . . . 39
Table 21. CFI Query Identification String ...............................39
Table 22. System Interface String........................................ 40
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 43
Ordering Information-S29GL032A . . . . . . . . . . . . 15
S29GL032A Standard Products .......................................................................15
Table 1. S29GL032A Ordering Options ................................. 16
Ordering Information-S29GL064A . . . . . . . . . . . . 17
S29GL064A Standard Products .......................................................................17
Table 2. S29GL064A Valid Combinations .............................. 18
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. Device Bus Operations ........................................... 19
Word/Byte Configuration ................................................................................20
Requirements for Reading Array Data ........................................................ 20
Page Mode Read ............................................................................................. 20
Writing Commands/Command Sequences ................................................ 20
Write Buffer ..................................................................................................... 21
Accelerated Program Operation ............................................................... 21
Autoselect Functions ..................................................................................... 21
Standby Mode ....................................................................................................... 21
Reading Array Data ........................................................................................... 43
Reset Command ................................................................................................. 43
Autoselect Command Sequence ...................................................................44
Enter Secured Silicon Sector/Exit Secured Silicon
Sector Command Sequence ............................................................................44
Word Program Command Sequence ......................................................44
Unlock Bypass Command Sequence ........................................................ 45
Write Buffer Programming ......................................................................... 45
Accelerated Program .................................................................................... 47
Figure 3. Write Buffer Programming Operation....................... 48
Figure 4. Program Operation ............................................... 49
Program Suspend/Program Resume Command Sequence ....................49
Figure 5. Program Suspend/Program Resume........................ 50
Chip Erase Command Sequence ...................................................................50
Sector Erase Command Sequence . . . . . . . . . . . 52
Figure 6. Erase Operation ................................................... 53
Erase Suspend/Erase Resume Commands ...................................................53
Command Definitions ........................................................................................55
Automatic Sleep Mode ..................................................................................... 22
RESET#: Hardware Reset Pin ........................................................................ 22
Output Disable Mode ....................................................................................... 22
Table 4. S29GL032M (Models R1, R2) Sector Addresses ......... 23
Table 5. S29GL032M (Models R3) Top Boot Sector Addresses . 24
Table 6. S29GL032M (Models R4) Bottom Boot
Table 25. Command Definitions (x16 Mode, BYTE# = VIH
) ......55
Table 26. Command Definitions (x8 Mode, BYTE# = VIL) .........56
Write Operation Status ....................................................................................57
DQ7: Data# Polling ........................................................................................... 57
Figure 7. Data# Polling Algorithm ........................................ 58
RY/BY#: Ready/Busy# .......................................................................................58
DQ6: Toggle Bit I ................................................................................................59
Figure 8. Toggle Bit Algorithm ............................................. 60
DQ2: Toggle Bit II ................................................................................................61
Reading Toggle Bits DQ6/DQ2 ......................................................................61
DQ5: Exceeded Timing Limits .........................................................................61
DQ3: Sector Erase Timer ................................................................................62
DQ1: Write-to-Buffer Abort ...........................................................................62
Table 27. Write Operation Status .........................................63
Absolute Maximum Ratings ..............................................................................64
Figure 9. Maximum Negative Overshoot Waveform................. 64
Figure 10. Maximum Positive
Overshoot Waveform.......................................................... 64
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 64
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 65
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 11. Test Setup......................................................... 66
Table 28. Test Specifications ...............................................66
Key to Switching Waveforms . . . . . . . . . . . . . . . . 66
Figure 12. Input Waveforms and Measurement Levels ............ 66
Read-Only Operations-S29GL064A only ................................................... 67
Read-Only Operations-S29GL032A only .................................................... 67
Figure 13. Read Operation Timings....................................... 68
Figure 14. Page Read Timings.............................................. 68
Hardware Reset (RESET#) ..............................................................................69
Figure 15. Reset Timings .................................................... 69
Erase and Program Operations-S29GL064A Only ..................................70
Erase and Program Operations-S29GL032A Only ....................................71
Figure 16. Program Operation Timings.................................. 72
Figure 17. Accelerated Program Timing Diagram.................... 72
Sector Addresses .............................................................. 24
Table 7. S29GL064A (Models R1, R2, R8, R9) Sector Addresses 25
Table 8. S29GL064A (Model R3) Top Boot Sector Addresses ... 26
Table 9. S29GL064A (Model R4) Bottom Boot Sector Addresses 27
Table 10. S29GL064A (Model R5) Sector Addresses ............... 28
Table 11. S29GL064A (Models R6, R7) Sector Addresses ........ 29
Autoselect Mode ................................................................................................ 30
Table 12. Autoselect Codes, (High Voltage Method) .............. 31
Sector Group Protection and Unprotection ...............................................31
Table 13. S29GL032A (Models R1, R2) Sector Group Protection/Un-
protection Addresses ......................................................... 32
Table 14. S29GL032A (Models R3) Sector Group Protection/Unpro-
tection Address Table ......................................................... 32
Table 15. S29GL032A (Models R4) Sector Group Protection/Unpro-
tection Address Table ......................................................... 32
Table 16. S29GL064A (Models R1, R2, R8, R9) Sector Group Protec-
tion/Unprotection Addresses ............................................... 32
Table 17. S29GL064A (Model R3) Top Boot Sector Protection/Unpro-
tection Addresses .............................................................. 33
Table 18. S29GL064A (Model R4) Bottom Boot Sector Protection/
Unprotection Addresses ...................................................... 33
Table 19. S29GL064A (Model R5) Sector Group Protection/Unpro-
tection Addresses .............................................................. 33
Table 20. S29GL064A (Models R6, R7) Sector Group Protection/Un-
protection Addresses ......................................................... 33
Temporary Sector Group Unprotect ...........................................................34
Figure 1. Temporary Sector Group Unprotect Operation .......... 34
Figure 2. In-System Sector Group Protect/Unprotect Algorithms 35
Secured Silicon Sector Flash Memory Region ............................................36
Write Protect (WP#) ........................................................................................37
Hardware Data Protection ..............................................................................37
Low VCC Write Inhibit ................................................................................37
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
5
A d v a n c e I n f o r m a t i o n
Figure 18. Chip/Sector Erase Operation Timings..................... 73
Figure 19. Data# Polling Timings
Program Operations-S29GL032A ..................................................................78
Figure 24. Alternate CE# Controlled Write
(During Embedded Algorithms)............................................ 73
Figure 20. Toggle Bit Timings (During Embedded Algorithms) .. 74
Figure 21. DQ2 vs. DQ6 ...................................................... 74
Temporary Sector Unprotect .........................................................................75
Figure 22. Temporary Sector Group Unprotect Timing Diagram 75
Figure 23. Sector Group Protect and Unprotect Timing Diagram 76
Alternate CE# Controlled Erase and
(Erase/Program) Operation Timings ..................................... 79
Erase And Programming Performance . . . . . . . . 80
TSOP Pin and BGA Package Capacitance . . . . . 81
TS048—48-Pin Standard Thin Small Outline Package (TSOP) ............82
TS056—56-Pin Standard Thin Small Outline Package (TSOP) .............83
LAA064—64-Ball Fortified Ball Grid Array (BGA) ..................................84
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 86
Program Operations-S29GL064A ..................................................................77
Alternate CE# Controlled Erase and
6
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Product Selector Guide
S29GL064A, S29GL032A
Part Number
S29GL064A
S29GL032A
Speed Option
90
90
90
25
25
10
100
100
30
11
110
110
30
90
90
90
25
25
10
100
100
30
11
110
110
30
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page Access Time (ns)
Max. OE# Access Time (ns)
30
30
30
30
Block Diagram
DQ15–DQ0 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
WP#/ACC
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
AMax**–A0
Note:
**A
**A
GL064A = A21.
MAX
GL032A = A20.
MAX
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
7
A d v a n c e I n f o r m a t i o n
Connection Diagrams
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
1
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
A8
48-Pin Standard TSOP
1
A19
9
A20
WE#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
RESET#
1,2
A21
1
1
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
Notes:
1. Pin 9 is A21, Pin 13 is ACC, Pin 14 is WP#, Pin 15 is A19, and Pin 47 is V on S29GL064A (models R6, R7).
IO
2. Pin 13 is NC on S29GL032A.
NC
NC
1
2
3
4
5
6
7
8
9
56 NC
55 NC
A15
A14
A13
A12
A11
A10
A9
54 A16
53 BYTE#
52 VSS
51 DQ15/A-1
50 DQ7
49 DQ14
48 DQ6
47 DQ13
46 DQ5
45 DQ12
44 DQ4
43 VCC
56-Pin Standard TSOP
A8 10
A19 11
A20 12
WE# 13
RESET# 14
A211 15
WP#/ACC 16
RY/BY# 17
A18 18
A17 19
A7 20
42 DQ11
41 DQ3
40 DQ10
39 DQ2
38 DQ9
37 DQ1
36 DQ8
35 DQ0
34 OE#
33 VSS
A6 21
A5 22
A4 23
A3 24
A2 25
32 CE#
31 A0
A1 26
NC 27
30 NC
NC 28
29 VIO
Notes:
1. Pin 15 is NC on S29GL032A.
8
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
64-ball Fortified BGA
Top View, Balls Facing Down
A8
B8
C8
D8
E8
F8
G8
NC
H8
1
NC
NC
NC
NC
VIO
VSS
NC
A7
B7
C7
D7
E7
F7
G7
H7
BYTE#2 DQ15/A-1
VSS
A13
A12
A14
A15
A16
A6
A9
B6
A8
C6
D6
E6
F6
G6
H6
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
3
VCC
WE# RESET# A21
A19
DQ5
DQ12
DQ4
A4
B4
C4
D4
E4
F4
G4
H4
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
A3
A7
B3
C3
A6
D3
A5
E3
F3
G3
H3
A17
DQ0
DQ8
DQ9
DQ1
A2
A3
B2
A4
C2
A2
D2
A1
E2
A0
F2
G2
H2
VSS
CE#
OE#
A1
B1
C1
D1
E1
F1
G1
NC
H1
4
NC
NC
NC
NC
NC
NC
VIO
Notes:
1. Ball D8 and Ball F1 are NC on S29GL064A (models R3, R4).
2. Ball F7 is NC on S29GL064A (model R5).
3. Ball C5 is NC on S29GL032A.
Special Package Handling Instructions
Special handling is required for Flash Memory products in moulded packages
(TSOP and BGA). The package and/or data integrity may be compromised if the
package body is exposed to temperatures above 150°C for prolonged periods of
time.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
9
A d v a n c e I n f o r m a t i o n
48-ball Fine-pitch BGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
BYTE#1 DQ15/A-1
VSS
A13
A12
A14
A15
A16
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
2
VCC
WE# RESET# A21
A19
DQ5
DQ12
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
VSS
CE#
OE#
Notes:
1. Ball F6 is V on S29GL064A (models R5).
IO
2. Ball C4 is NC on S29GL032A.
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(TSOP and BGA). The package and/or data integrity may be compromised if the
package body is exposed to temperatures above 150°C for prolonged periods of
time.
10
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Pin Descriptions
A21–A0
A20–A0
DQ7–DQ0
DQ14–DQ0
DQ15/A-1
=
=
=
=
=
22 Address inputs
21 Address inputs
8 Data inputs/outputs
15 Data inputs/outputs
DQ15 (Data input/output, word mode), A-1 (LSB
Address input, byte mode)
Chip Enable input
Output Enable input
Write Enable input
CE#
OE#
WE#
WP#/ACC
=
=
=
=
Hardware Write Protect input/Programming
Acceleration input
ACC
WP#
RESET#
RY/BY#
BYTE#
VCC
=
=
=
=
=
=
Acceleration input
Hardware Write Protect input
Hardware Reset Pin input
Ready/Busy output
Selects 8-bit or 16-bit mode
3.0 volt-only single power supply
(see Product Selector Guide for speed options and
voltage supply tolerances)
Device Ground
VSS
NC
VIO
=
=
=
Pin Not Connected Internally
Output Buffer Power
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
11
A d v a n c e I n f o r m a t i o n
Logic Symbol-S29GL032A (Models R1, R2)
21
A20–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
V
IO
Logic Symbol-S29GL032A (Models R3, R4)
21
A20–A0
16 or 8
DQ15–DQ0
CE#
OE#
WE#
(A-1)
WP#/ACC
RESET#
RY/BY#
BYTE#
12
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Logic Symbol-S29GL064A (Models R1, R2, R8, R9)
22
A21–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
V
IO
Logic Symbol-S29GL064A (Models R3, R4)
22
A21–A0
16 or 8
DQ15–DQ0
CE#
(A-1)
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
13
A d v a n c e I n f o r m a t i o n
Logic Symbol-S29GL064A (Model R5)
22
A21–A0
16
DQ15–DQ0
CE#
OE#
WE#
ACC
RESET#
V
RY/BY#
IO
Logic Symbol-S29GL064A (Model R6, R7)
22
A21–A0
16
DQ15–DQ0
CE#
OE#
WE#
WP#
ACC
RESET#
V
IO
14
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Ordering Information-S29GL032A
S29GL032A Standard Products
Standard products are available in several packages and operating ranges. The
order number (Valid Combination) is formed by a combination of the following:
S29GL032A
90
T
A
I
R1
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER
R1
R2
R3
R4
=
=
=
=
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address sector
protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Top boot sector device, top two address sectors
protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Bottom boot sector device, bottom two
address sectors protected when WP#/ACC=VIL
TEMPERATURE RANGE
I
= Industrial (–40°C to +85°C)
PACKAGE MATERIAL SET
A
F
=
=
Standard
Pb-Free
PACKAGE TYPE
T
B
F
=
=
=
Thin Small Outline Package (TSOP) Standard Pinout
Fine-pitch Ball-Grid Array Package
Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29GL032A
32 Megabit Page-Mode Flash Memory Manufactured using 200 nm MirrorBit™
Process Technology, 3.0 Volt-only Read, Program, and Erase
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
15
A d v a n c e I n f o r m a t i o n
Table 1. S29GL032A Ordering Options
S29GL032A Valid Combinations
Package Description
(Notes)
Device
Number
Speed
Option
Package, Material,
Model
Number
Packing
Type
& Temperature Range
TAI,TFI
TS056 (2)
TSOP
R1,R2
R3,R4
FAI,FFI
LAA064 (3)
TS048 (2)
FBC048 (3)
LAA064 (3)
Fortified BGA
TSOP
0,2,3
(Note 1)
S29GL032A
90, 10, 11
TAI,TFI
BAI,BFI
Fine-Pitch BGA
Fortified BGA
FAI,FFI
Notes:
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can
be packed in Types 0, 2, or 3.
2. TSOP package marking omits packing type designator from the ordering part number.
3. BGA package marking omits leading “S29” and packing type designator from the ordering part
number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult
your local sales office to confirm availability of specific valid combinations and to check on newly
released combinations.
16
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Ordering Information-S29GL064A
S29GL064A Standard Products
Standard products are available in several packages and operating ranges. The
order number (Valid Combination) is formed by a combination of the following:
S29GL064A
90
T
A
I
R1
2
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER
R1
R2
R3
R4
=
=
=
=
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Top boot sector device, top two address
sectors protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Bottom boot sector device, bottom two
address sectors protected when WP#/ACC=VIL
x16, VCC=3.0-3.6V, Uniform sector device
R5
R6
=
=
x16, VCC=3.0-3.6V, Uniform sector device, highest address sector
protected when WP#=VIL
R7
R8
R9
=
=
=
x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#=VIL
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#=VIL, TSO48 only
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#=VIL, TSO48 only
TEMPERATURE RANGE
I
= Industrial (–40°C to +85°C)
PACKAGE MATERIAL SET
A
F
=
=
Standard
Pb-Free
PACKAGE TYPE
T
B
F
=
=
=
Thin Small Outline Package (TSOP) Standard Pinout
Fine-pitch Ball-Grid Array Package
Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29GL064A
64 Megabit Page-Mode Flash Memory Manufactured using 200 nm MirrorBitTM
Process Technology, 3.0 Volt-only Read, Program, and Erase
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
17
A d v a n c e I n f o r m a t i o n
Table 2. S29GL064A Valid Combinations
S29GL064A Valid Combinations
Package, Material
& Temperature
Range
Package Description
Device
Number
Speed
Option
Packing
Type
Model Number
R3, R4, R6, R7, R8, R9
R1, R2
TS048 (note 2)
TSOP
TSOP
TAI, TFI
TS056 (note 2)
VBN048 (note 3)
LAA064 (note 3)
0, 2, 3
(Note 1)
S29GL064A
90, 10, 11
BAI, BFI
FAI, FFI
R3, R4, R5
Fine-pitch BGA
Fortified BGA
R1, R2, R3, R4, R5
Notes:
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types
0, 2, or 3.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading “S29” and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device.
Consult your local sales office to confirm availability of specific valid combinations and to
check on newly released combinations.
18
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 3 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 3. Device Bus Operations
DQ8–DQ15
BYTE# BYTE#
Addresses
(Note 1)
DQ0–
DQ7
Operation
CE# OE# WE# RESET#
WP#
ACC
= V = V
IH
IL
Read
L
L
L
H
L
H
H
X
X
AIN
AIN
DOUT
DOUT
(Note
4)
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
Accelerated Program
Standby
H
(Note 3)
X
(Note 4)
(Note
4)
L
H
X
L
H
(Note 3) VHH
AIN
X
(Note 4)
High-Z
VCC
0.3 V
±
VCC ±
0.3 V
X
X
H
High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
SA, A6 =L,
A3=L, A2=L, (Note 4)
A1=H, A0=L
Sector Group Protect
(Note 2)
L
H
L
VID
H
X
X
X
X
Sector Group
Unprotect
(Note 2)
SA, A6=H,
A3=L, A2=L, (Note 4)
A1=H, A0=L
L
H
X
L
VID
VID
H
H
X
X
X
Temporary Sector
Group Unprotect
(Note
4)
X
X
AIN
(Note 4)
High-Z
Legend: L = Logic Low = V , H = Logic High = V , V = 11.5–12.5V, V = 11.5–12.5V, X = Don’t Care, SA = Sector
IL
IH
ID
HH
Address, A = Address In, D = Data In, D = Data Out
IN
IN
OUT
Notes:
1. Addresses are Amax:A0 in word mode; Amax:A-1 in byte mode. Sector addresses are Amax:A15 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector Group Protection and Unprotection” section.
3. If WP# = V , the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors
IL
are protected (for boot sector devices). If WP# = V , the first or last sector, or the two outer boot sectors will be
IH
protected or unprotected as determined by the method described in “Sector Group Protection and Unprotection”.
All sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected
depending on version ordered.)
4. D or D
as required by command sequence, data polling, or sector protect algorithm (see Figure 7).
OUT
IN
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
19
A d v a n c e I n f o r m a t i o n
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only
data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/
O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE#
pins to VIL. CE# is the power control and selects the device. OE# is the output
control and gates array data to the output pins. WE# should remain at VIH
.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read-Only Op-
erations table for timing specifications and the timing diagram. Refer to the DC
Characteristics table for the active current specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. The page size of the device is 4 words/8 bytes.
The appropriate page is selected by the higher address bits A(max)–A2. Address
bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word
within a page. This is an asynchronous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page
read accesses (as long as the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is deasserted and reasserted
for a subsequent access, the access time is tACC or tCE. Fast page mode accesses
are obtained by keeping the “read-page addresses” constant and changing the
“intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH
.
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four. The “Word Program Command
Sequence” section has details on programming data to the device using both
standard and Unlock Bypass command sequences.
20
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 4-Table 20 indicates the address space that each sector occupies.
Refer to the DC Characteristics table for the active current specification for the
write mode. The AC Characteristics section contains timing specification tables
and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32
bytes in one programming operation. This results in faster effective programming
time than the standard programming algorithms. See “Write Buffer” for more
information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
is one of two functions provided by the WP#/ACC or ACC pin, depending on model
number. This function is primarily intended to allow faster manufacturing
throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the afore-
mentioned Unlock Bypass mode, temporarily unprotects any protected sector
groups, and uses the higher voltage on the pin to reduce the time required for
program operations. The system would use a two-cycle program command se-
quence as required by the Unlock Bypass mode. Removing VHH from the WP#/
ACC or ACC pin, depending on model number, returns the device to normal op-
eration. Note that the WP#/ACC or ACC pin must not be at VHH for operations
other than accelerated programming, or device damage may result. WP# has an
internal pullup; when unconnected, WP# is at VIH
.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7–DQ0. Standard read
cycle timings apply in this mode. Refer to the “Autoselect Mode” section on page
30 and “Autoselect Command Sequence” section on page 44 sections for more
information.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device
will be in the standby mode, but the standby current will be greater. The device
requires standard access time (tCE) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
Refer to the “DC Characteristics” section on page 65 for the standby current
specification.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
21
A d v a n c e I n f o r m a t i o n
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for tACC
+
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. Refer to the “DC Characteristics” section on page 65 for the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VSS±0.3 V, the device draws CMOS standby current (ICC5). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 15
for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins
are placed in the high impedance state.
22
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Table 4. S29GL032M (Models R1, R2) Sector Addresses
Sector
Size
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A20-A15
A20-A15
(KB/
Kwords)
Kwords)
SA0 0 0 0 0 0 0
SA1 0 0 0 0 0 1
SA2 0 0 0 0 1 0
SA3 0 0 0 0 1 1
SA4 0 0 0 1 0 0
SA5 0 0 0 1 0 1
SA6 0 0 0 1 1 0
SA7 0 0 0 1 1 1
SA8 0 0 1 0 0 0
SA9 0 0 1 0 0 1
SA10 0 0 1 0 1 0
SA11 0 0 1 0 1 1
SA12 0 0 1 1 0 0
SA13 0 0 1 1 0 1
SA14 0 0 1 1 1 0
SA15 0 0 1 1 1 1
SA16 0 1 0 0 0 0
SA17 0 1 0 0 0 1
SA18 0 1 0 0 1 0
SA19 0 1 0 0 1 1
SA20 0 1 0 1 0 0
SA21 0 1 0 1 0 1
SA22 0 1 0 1 1 0
SA23 0 1 0 1 1 1
SA24 0 1 1 0 0 0
SA25 0 1 1 0 0 1
SA26 0 1 1 0 1 0
SA27 0 1 1 0 1 1
SA28 0 1 1 1 0 0
SA29 0 1 1 1 0 1
SA30 0 1 1 1 1 0
SA31 0 1 1 1 1 1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
SA32 1 0 0 0 0 0
SA33 1 0 0 0 0 1
SA34 1 0 0 0 1 0
SA35 1 0 0 0 1 1
SA36 1 0 0 1 0 0
SA37 1 0 0 1 0 1
SA38 1 0 0 1 1 0
SA39 1 0 0 1 1 1
SA40 1 0 1 0 0 0
SA41 1 0 1 0 0 1
SA42 1 0 1 0 1 0
SA43 1 0 1 0 1 1
SA44 1 0 1 1 0 0
SA45 1 0 1 1 0 1
SA46 1 0 1 1 1 0
SA47 1 0 1 1 1 1
SA48 1 1 0 0 0 0
SA49 1 1 0 0 0 1
SA50 1 1 0 0 1 0
SA51 1 1 0 0 1 1
SA52 1 1 0 1 0 0
SA53 1 1 0 1 0 1
SA54 1 1 0 1 1 0
SA55 1 1 0 1 1 1
SA56 1 1 1 0 0 0
SA57 1 1 1 0 0 1
SA58 1 1 1 0 1 0
SA59 1 1 1 0 1 1
SA60 1 1 1 1 0 0
SA61 1 1 1 1 0 1
SA62 1 1 1 1 1 0
SA63 1 1 1 1 1 1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
23
A d v a n c e I n f o r m a t i o n
Table 5. S29GL032M (Models R3) Top Boot Sector Addresses
Sector
Size
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A20–A12
A20–A12
(KB/
Kwords)
Kwords)
SA0 000000xxx
SA1 000001xxx
SA2 000010xxx
SA3 000011xxx
SA4 000100xxx
SA5 000101xxx
SA6 000110xxx
SA7 000111xxx
SA8 001000xxx
SA9 001001xxx
SA10 001010xxx
SA11 001011xxx
SA12 001100xxx
SA13 001101xxx
SA14 001101xxx
SA15 001111xxx
SA16 010000xxx
SA17 010001xxx
SA18 010010xxx
SA19 010011xxx
SA20 010100xxx
SA21 010101xxx
SA22 010110xxx
SA23 010111xxx
SA24 011000xxx
SA25 011001xxx
SA26 011010xxx
SA27 011011xxx
SA28 011000xxx
SA29 011101xxx
SA30 011110xxx
SA31 011111xxx
SA32 100000xxx
SA33 100001xxx
SA34 100010xxx
SA35 101011xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
SA36 100100xxx
SA37 100101xxx
SA38 100110xxx
SA39 100111xxx
SA40 101000xxx
SA41 101001xxx
SA42 101010xxx
SA43 101011xxx
SA44 101100xxx
SA45 101101xxx
SA46 101110xxx
SA47 101111xxx
SA48 110000xxx
SA49 110001xxx
SA50 110010xxx
SA51 110011xxx
SA52 100100xxx
SA53 110101xxx
SA54 110110xxx
SA55 110111xxx
SA56 111000xxx
SA57 111001xxx
SA58 111010xxx
SA59 111011xxx
SA60 111100xxx
SA61 111101xxx
SA62 111110xxx
SA63 111111000
SA64 111111001
SA65 111111010
SA66 111111011
SA67 111111100
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
240000h–24FFFFh 120000h–127FFFh
250000h–25FFFFh 128000h–12FFFFh
260000h–26FFFFh 130000h–137FFFh
270000h–27FFFFh 138000h–13FFFFh
280000h–28FFFFh 140000h–147FFFh
290000h–29FFFFh 148000h–14FFFFh
2A0000h–2AFFFFh 150000h–157FFFh
2B0000h–2BFFFFh 158000h–15FFFFh
2C0000h–2CFFFFh 160000h–167FFFh
2D0000h–2DFFFFh 168000h–16FFFFh
2E0000h–2EFFFFh 170000h–177FFFh
2F0000h–2FFFFFh 178000h–17FFFFh
300000h–30FFFFh 180000h–187FFFh
310000h–31FFFFh 188000h–18FFFFh
320000h–32FFFFh 190000h–197FFFh
330000h–33FFFFh 198000h–19FFFFh
340000h–34FFFFh 1A0000h–1A7FFFh
350000h–35FFFFh 1A8000h–1AFFFFh
360000h–36FFFFh 1B0000h–1B7FFFh
370000h–37FFFFh 1B8000h–1BFFFFh
380000h–38FFFFh 1C0000h–1C7FFFh
390000h–39FFFFh 1C8000h–1CFFFFh
3A0000h–3AFFFFh 1D0000h–1D7FFFh
3B0000h–3BFFFFh 1D8000h–1DFFFFh
3C0000h–3CFFFFh 1E0000h–1E7FFFh
3D0000h–3DFFFFh 1E8000h–1EFFFFh
3E0000h–3EFFFFh 1F0000h–1F7FFFh
3F0000h–3F1FFFh 1F8000h–1F8FFFh
3F2000h–3F3FFFh 1F9000h–1F9FFFh
3F4000h–3F5FFFh 1FA000h–1FAFFFh
3F6000h–3F7FFFh 1FB000h–1FBFFFh
3F8000h–3F9FFFh 1FC000h–1FCFFFh
3FA000h–3FBFFFh 1FD000h–1FDFFFh
3FC000h–3FDFFFh 1FE000h–1FEFFFh
3FE000h–3FFFFFh 1FF000h–1FFFFFh
1A0000h–1AFFFFh D0000h–D7FFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh F9000h–107FFFh SA68 111111101
210000h–21FFFFh 108000h–10FFFFh SA69 111111110
220000h–22FFFFh 110000h–117FFFh SA70 111111111
230000h–23FFFFh 118000h–11FFFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Table 6. S29GL032M (Models R4) Bottom Boot Sector Addresses (Sheet 1 of 2)
Sector
Size
Sector
Size
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A20–A12
A20–A12
(KB/
(KB/
Kwords)
Kwords)
SA0 000000000
SA1 000000001
SA2 000000010
SA3 000000011
SA4 000000100
SA5 000000101
SA6 000000110
SA7 000000111
SA8 000001xxx
SA9 000010xxx
SA10 000011xxx
SA11 000100xxx
SA12 000101xxx
SA13 000110xxx
SA14 000111xxx
SA15 001000xxx
SA16 001001xxx
SA17 001010xxx
SA18 001011xxx
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
SA19 001100xxx 64/32
SA20 001101xxx 64/32
SA21 001101xxx 64/32
SA22 001111xxx 64/32
SA23 010000xxx 64/32
SA24 010001xxx 64/32
SA25 010010xxx 64/32
SA26 010011xxx 64/32
SA27 010100xxx 64/32
SA28 010101xxx 64/32
SA29 010110xxx 64/32
SA30 010111xxx 64/32
SA31 011000xxx 64/32
SA32 011001xxx 64/32
SA33 011010xxx 64/32
SA34 011011xxx 64/32
SA35 011000xxx 64/32
SA36 011101xxx 64/32
SA37 011110xxx 64/32
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
24
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Table 6. S29GL032M (Models R4) Bottom Boot Sector Addresses (Sheet 2 of 2)
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A20–A12
A20–A12
Kwords)
Kwords)
SA38 011111xxx
SA39 100000xxx
SA40 100001xxx
SA41 100010xxx
SA42 101011xxx
SA43 100100xxx
SA44 100101xxx
SA45 100110xxx
SA46 100111xxx
SA47 101000xxx
SA48 101001xxx
SA49 101010xxx
SA50 101011xxx
SA51 101100xxx
SA52 101101xxx
SA53 101110xxx
SA54 101111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
1F0000h–1FFFFFh
200000h–20FFFFh
F8000h–FFFFFh
F9000h–107FFFh SA56 110001xxx 64/32
SA55 110000xxx 64/32
300000h–30FFFFh 180000h–187FFFh
310000h–31FFFFh 188000h–18FFFFh
320000h–32FFFFh 190000h–197FFFh
330000h–33FFFFh 198000h–19FFFFh
340000h–34FFFFh 1A0000h–1A7FFFh
350000h–35FFFFh 1A8000h–1AFFFFh
360000h–36FFFFh 1B0000h–1B7FFFh
370000h–37FFFFh 1B8000h–1BFFFFh
380000h–38FFFFh 1C0000h–1C7FFFh
390000h–39FFFFh 1C8000h–1CFFFFh
3A0000h–3AFFFFh 1D0000h–1D7FFFh
3B0000h–3BFFFFh 1D8000h–1DFFFFh
3C0000h–3CFFFFh 1E0000h–1E7FFFh
3D0000h–3DFFFFh 1E8000h–1EFFFFh
3E0000h–3EFFFFh 1F0000h–1F7FFFh
3F0000h–3FFFFFh 1F8000h–1FFFFFh
210000h–21FFFFh 108000h–10FFFFh SA57 110010xxx 64/32
220000h–22FFFFh 110000h–117FFFh SA58 110011xxx 64/32
230000h–23FFFFh 118000h–11FFFFh SA59 100100xxx 64/32
240000h–24FFFFh 120000h–127FFFh SA60 110101xxx 64/32
250000h–25FFFFh 128000h–12FFFFh SA61 110110xxx 64/32
260000h–26FFFFh 130000h–137FFFh SA62 110111xxx 64/32
270000h–27FFFFh 138000h–13FFFFh SA63 111000xxx 64/32
280000h–28FFFFh 140000h–147FFFh SA64 111001xxx 64/32
290000h–29FFFFh 148000h–14FFFFh SA65 111010xxx 64/32
2A0000h–2AFFFFh 150000h–157FFFh SA66 111011xxx 64/32
2B0000h–2BFFFFh 158000h–15FFFFh SA67 111100xxx 64/32
2C0000h–2CFFFFh 160000h–167FFFh SA68 111101xxx 64/32
2D0000h–2DFFFFh 168000h–16FFFFh SA69 111110xxx 64/32
2E0000h–2EFFFFh 170000h–177FFFh SA70 111111xxx 64/32
2F0000h–2FFFFFh 178000h–17FFFFh
Table 7. S29GL064A (Models R1, R2, R8, R9) Sector Addresses (Sheet 1 of 2)
Sector
Size
Sector
Size
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A21–A15
A21–A15
(KB/
(KB/
Kwords)
Kwords)
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
400000–40FFFF
410000–41FFFF
420000–42FFFF
430000–43FFFF
440000–44FFFF
450000–45FFFF
460000–46FFFF
470000–47FFFF
480000–48FFFF
490000–49FFFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
SA10 0001010
SA11 0001011
SA12 0001100
SA13 0001101
SA14 0001110
SA15 0001111
SA16 0010000
SA17 0010001
SA18 0010010
SA19 0010011
SA20 0010100
SA21 0010101
SA22 0010110
SA23 0010111
SA24 0011000
SA25 0011001
SA26 0011010
SA27 0011011
SA28 0011100
SA29 0011101
SA30 0011110
SA31 0011111
SA32 0100000
SA33 0100001
SA34 0100010
SA35 0100011
SA36 0100100
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
25
A d v a n c e I n f o r m a t i o n
Table 7. S29GL064A (Models R1, R2, R8, R9) Sector Addresses (Sheet 2 of 2)
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A21–A15
A21–A15
Kwords)
Kwords)
SA74 1001010
SA75 1001011
SA76 1001100
SA77 1001101
SA78 1001110
SA79 1001111
SA80 1010000
SA81 1010001
SA82 1010010
SA83 1010011
SA84 1010100
SA85 1010101
SA86 1010110
SA87 1010111
SA88 1011000
SA89 1011001
SA90 1011010
SA91 1011011
SA92 1011100
SA93 1011101
SA94 1011110
SA95 1011111
SA96 1100000
SA97 1100001
SA98 1100010
SA99 1100011
SA100 1100100
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
4A0000–4AFFFF
4B0000–4BFFFF
4C0000–4CFFFF
4D0000–4DFFFF
4E0000–4EFFFF
4F0000–4FFFFF
500000–50FFFF
510000–51FFFF
520000–52FFFF
530000–53FFFF
540000–54FFFF
550000–55FFFF
560000–56FFFF
570000–57FFFF
580000–58FFFF
590000–59FFFF
5A0000–5AFFFF
5B0000–5BFFFF
5C0000–5CFFFF
5D0000–5DFFFF
5E0000–5EFFFF
5F0000–5FFFFF
600000–60FFFF
610000–61FFFF
620000–62FFFF
630000–63FFFF
640000–64FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
SA101 1100101
SA102 1100110
SA103 1100111
SA104 1101000
SA105 1101001
SA106 1101010
SA107 1101011
SA108 1101100
SA109 1101101
SA110 1101110
SA111 1101111
SA112 1110000
SA113 1110001
SA114 1110010
SA115 1110011
SA116 1110100
SA117 1110101
SA118 1110110
SA119 1110111
SA120 1111000
SA121 1111001
SA122 1111010
SA123 1111011
SA124 1111100
SA125 1111101
SA126 1111110
SA127 1111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
650000–65FFFF
660000–66FFFF
670000–67FFFF
680000–68FFFF
690000–69FFFF
6A0000–6AFFFF
6B0000–6BFFFF
6C0000–6CFFFF
6D0000–6DFFFF
6E0000–6EFFFF
6F0000–6FFFFF
700000–70FFFF
710000–71FFFF
720000–72FFFF
730000–73FFFF
740000–74FFFF
750000–75FFFF
760000–76FFFF
770000–77FFFF
780000–78FFFF
790000–79FFFF
7A0000–7AFFFF
7B0000–7BFFFF
7C0000–7CFFFF
7D0000–7DFFFF
7E0000–7EFFFF
7F0000–7FFFFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
Table 8. S29GL064A (Model R3) Top Boot Sector Addresses (Sheet 1 of 2)
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A21–A15
A21–A15
Kwords)
Kwords)
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
0000000xxx
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
SA34 0100010xxx
SA35 0101011xxx
SA36 0100100xxx
SA37 0100101xxx
SA38 0100110xxx
SA39 0100111xxx
SA40 0101000xxx
SA41 0101001xxx
SA42 0101010xxx
SA43 0101011xxx
SA44 0101100xxx
SA45 0101101xxx
SA46 0101110xxx
SA47 0101111xxx
SA48 0110000xxx
SA49 0110001xxx
SA50 0110010xxx
SA51 0110011xxx
SA52 0100100xxx
SA53 0110101xxx
SA54 0110110xxx
SA55 0110111xxx
SA56 0111000xxx
SA57 0111001xxx
SA58 0111010xxx
SA59 0111011xxx
SA60 0111100xxx
SA61 0111101xxx
SA62 0111110xxx
SA63 0111111xxx
SA64 1000000xxx
SA65 1000001xxx
SA66 1000010xxx
SA67 1000011xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
220000h–22FFFFh 110000h–117FFFh
230000h–23FFFFh 118000h–11FFFFh
240000h–24FFFFh 120000h–127FFFh
250000h–25FFFFh 128000h–12FFFFh
260000h–26FFFFh 130000h–137FFFh
270000h–27FFFFh 138000h–13FFFFh
280000h–28FFFFh 140000h–147FFFh
290000h–29FFFFh 148000h–14FFFFh
2A0000h–2AFFFFh 150000h–157FFFh
2B0000h–2BFFFFh 158000h–15FFFFh
2C0000h–2CFFFFh 160000h–167FFFh
2D0000h–2DFFFFh 168000h–16FFFFh
2E0000h–2EFFFFh 170000h–177FFFh
2F0000h–2FFFFFh 178000h–17FFFFh
300000h–30FFFFh 180000h–187FFFh
310000h–31FFFFh 188000h–18FFFFh
320000h–32FFFFh 190000h–197FFFh
330000h–33FFFFh 198000h–19FFFFh
340000h–34FFFFh 1A0000h–1A7FFFh
350000h–35FFFFh 1A8000h–1AFFFFh
360000h–36FFFFh 1B0000h–1B7FFFh
370000h–37FFFFh 1B8000h–1BFFFFh
380000h–38FFFFh 1C0000h–1C7FFFh
390000h–39FFFFh 1C8000h–1CFFFFh
3A0000h–3AFFFFh 1D0000h–1D7FFFh
3B0000h–3BFFFFh 1D8000h–1DFFFFh
3C0000h–3CFFFFh 1E0000h–1E7FFFh
3D0000h–3DFFFFh 1E8000h–1EFFFFh
3E0000h–3EFFFFh 1F0000h–1F7FFFh
3F0000h–3FFFFFh 1F8000h–1FFFFFh
400000h–40FFFFh 200000h–207FFFh
410000h–41FFFFh 208000h–20FFFFh
420000h–42FFFFh 210000h–217FFFh
430000h–43FFFFh 218000h–21FFFFh
SA10 0001010xxx
SA11 0001011xxx
SA12 0001100xxx
SA13 0001101xxx
SA14 0001101xxx
SA15 0001111xxx
SA16 0010000xxx
SA17 0010001xxx
SA18 0010010xxx
SA19 0010011xxx
SA20 0010100xxx
SA21 0010101xxx
SA22 0010110xxx
SA23 0010111xxx
SA24 0011000xxx
SA25 0011001xxx
SA26 0011010xxx
SA27 0011011xxx
SA28 0011000xxx
SA29 0011101xxx
SA30 0011110xxx
SA31 0011111xxx
SA32 0100000xxx
SA33 0100001xxx
210000h–21FFFFh 108000h–10FFFFh
26
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Table 8. S29GL064A (Model R3) Top Boot Sector Addresses (Sheet 2 of 2)
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A21–A15
A21–A15
Kwords)
Kwords)
SA68 1000100xxx
SA69 1000101xxx
SA70 1000110xxx
SA71 1000111xxx
SA72 1001000xxx
SA73 1001001xxx
SA74 1001010xxx
SA75 1001011xxx
SA76 1001100xxx
SA77 1001101xxx
SA78 1001110xxx
SA79 1001111xxx
SA80 1010000xxx
SA81 1010001xxx
SA82 1010010xxx
SA83 1010011xxx
SA84 1010100xxx
SA85 1010101xxx
SA86 1010110xxx
SA87 1010111xxx
SA88 1011000xxx
SA89 1011001xxx
SA90 1011010xxx
SA91 1011011xxx
SA92 1011100xxx
SA93 1011101xxx
SA94 1011110xxx
SA95 1011111xxx
SA96 1100000xxx
SA97 1100001xxx
SA98 1100010xxx
SA99 1100011xxx
SA100 1100100xxx
SA101 1100101xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
440000h–44FFFFh 220000h–227FFFh SA102 1100110xxx
450000h–45FFFFh 228000h–22FFFFh SA103 1100111xxx
460000h–46FFFFh 230000h–237FFFh SA104 1101000xxx
470000h–47FFFFh 238000h–23FFFFh SA105 1101001xxx
480000h–48FFFFh 240000h–247FFFh SA106 1101010xxx
490000h–49FFFFh 248000h–24FFFFh SA107 1101011xxx
4A0000h–4AFFFFh 250000h–257FFFh SA108 1101100xxx
4B0000h–4BFFFFh 258000h–25FFFFh SA109 1101101xxx
4C0000h–4CFFFFh 260000h–267FFFh SA110 1101110xxx
4D0000h–4DFFFFh 268000h–26FFFFh SA111 1101111xxx
4E0000h–4EFFFFh 270000h–277FFFh SA112 1110000xxx
4F0000h–4FFFFFh 278000h–27FFFFh SA113 1110001xxx
500000h–50FFFFh 280000h–28FFFFh SA114 1110010xxx
510000h–51FFFFh 288000h–28FFFFh SA115 1110011xxx
520000h–52FFFFh 290000h–297FFFh SA116 1110100xxx
530000h–53FFFFh 298000h–29FFFFh SA117 1110101xxx
540000h–54FFFFh 2A0000h–2A7FFFh SA118 1110110xxx
550000h–55FFFFh 2A8000h–2AFFFFh SA119 1110111xxx
560000h–56FFFFh 2B0000h–2B7FFFh SA120 1111000xxx
570000h–57FFFFh 2B8000h–2BFFFFh SA121 1111001xxx
580000h–58FFFFh 2C0000h–2C7FFFh SA122 1111010xxx
590000h–59FFFFh 2C8000h–2CFFFFh SA123 1111011xxx
5A0000h–5AFFFFh 2D0000h–2D7FFFh SA124 1111100xxx
5B0000h–5BFFFFh 2D8000h–2DFFFFh SA125 1111101xxx
5C0000h–5CFFFFh 2E0000h–2E7FFFh SA126 1111110xxx
5D0000h–5DFFFFh 2E8000h–2EFFFFh SA127 1111111000
5E0000h–5EFFFFh 2F0000h–2FFFFFh SA128 1111111001
5F0000h–5FFFFFh 2F8000h–2FFFFFh SA129 1111111010
600000h–60FFFFh 300000h–307FFFh SA130 1111111011
610000h–61FFFFh 308000h–30FFFFh SA131 1111111100
620000h–62FFFFh 310000h–317FFFh SA132 1111111101
630000h–63FFFFh 318000h–31FFFFh SA133 1111111110
640000h–64FFFFh 320000h–327FFFh SA134 1111111111
650000h–65FFFFh 328000h–32FFFFh
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
660000h–66FFFFh 330000h–337FFFh
670000h–67FFFFh 338000h–33FFFFh
680000h–68FFFFh 340000h–347FFFh
690000h–69FFFFh 348000h–34FFFFh
6A0000h–6AFFFFh 350000h–357FFFh
6B0000h–6BFFFFh 358000h–35FFFFh
6C0000h–6CFFFFh 360000h–367FFFh
6D0000h–6DFFFFh 368000h–36FFFFh
6E0000h–6EFFFFh 370000h–377FFFh
6F0000h–6FFFFFh 378000h–37FFFFh
700000h–70FFFFh 380000h–387FFFh
710000h–71FFFFh 388000h–38FFFFh
720000h–72FFFFh 390000h–397FFFh
730000h–73FFFFh 398000h–39FFFFh
740000h–74FFFFh 3A0000h–3A7FFFh
750000h–75FFFFh 3A8000h–3AFFFFh
760000h–76FFFFh 3B0000h–3B7FFFh
770000h–77FFFFh 3B8000h–3BFFFFh
780000h–78FFFFh 3C0000h–3C7FFFh
790000h–79FFFFh 3C8000h–3CFFFFh
7A0000h–7AFFFFh 3D0000h–3D7FFFh
7B0000h–7BFFFFh 3D8000h–3DFFFFh
7C0000h–7CFFFFh 3E0000h–3E7FFFh
7D0000h–7DFFFFh 3E8000h–3EFFFFh
7E0000h–7EFFFFh 3F0000h–3F7FFFh
7F0000h–7F1FFFh 3F8000h–3F8FFFh
7F2000h–7F3FFFh 3F9000h–3F9FFFh
7F4000h–7F5FFFh 3FA000h–3FAFFFh
7F6000h–7F7FFFh 3FB000h–3FBFFFh
7F8000h–7F9FFFh 3FC000h–3FCFFFh
7FA000h–7FBFFFh 3FD000h–3FDFFFh
7FC000h–7FDFFFh 3FE000h–3FEFFFh
7FE000h–7FFFFFh 3FF000h–3FFFFFh
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Table 9. S29GL064A (Model R4) Bottom Boot Sector Addresses (Sheet 1 of 2)
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A21–A15
A21–A15
Kwords)
Kwords)
SA0 0000000000
SA1 0000000001
SA2 0000000010
SA3 0000000011
SA4 0000000100
SA5 0000000101
SA6 0000000110
SA7 0000000111
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
SA27 0010100xxx
SA28 0010101xxx
SA29 0010110xxx
SA30 0010111xxx
SA31 0011000xxx
SA32 0011001xxx
SA33 0011010xxx
SA34 0011011xxx
SA35 0011000xxx
SA36 0011101xxx
SA37 0011110xxx
SA38 0011111xxx
SA39 0100000xxx
SA40 0100001xxx
SA41 0100010xxx
SA42 0101011xxx
SA43 0100100xxx
SA44 0100101xxx
SA45 0100110xxx
SA46 0100111xxx
SA47 0101000xxx
SA48 0101001xxx
SA49 0101010xxx
SA50 0101011xxx
SA51 0101100xxx
SA52 0101101xxx
SA53 0101110xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh 108000h–10FFFFh
220000h–22FFFFh 110000h–117FFFh
230000h–23FFFFh 118000h–11FFFFh
240000h–24FFFFh 120000h–127FFFh
250000h–25FFFFh 128000h–12FFFFh
260000h–26FFFFh 130000h–137FFFh
270000h–27FFFFh 138000h–13FFFFh
280000h–28FFFFh 140000h–147FFFh
290000h–29FFFFh 148000h–14FFFFh
2A0000h–2AFFFFh 150000h–157FFFh
2B0000h–2BFFFFh 158000h–15FFFFh
2C0000h–2CFFFFh 160000h–167FFFh
2D0000h–2DFFFFh 168000h–16FFFFh
2E0000h–2EFFFFh 170000h–177FFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
SA8
SA9
0000001xxx
0000010xxx
SA10 0000011xxx
SA11 0000100xxx
SA12 0000101xxx
SA13 0000110xxx
SA14 0000111xxx
SA15 0001000xxx
SA16 0001001xxx
SA17 0001010xxx
SA18 0001011xxx
SA19 0001100xxx
SA20 0001101xxx
SA21 0001101xxx
SA22 0001111xxx
SA23 0010000xxx
SA24 0010001xxx
SA25 0010010xxx
SA26 0010011xxx
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
27
A d v a n c e I n f o r m a t i o n
Table 9. S29GL064A (Model R4) Bottom Boot Sector Addresses (Sheet 2 of 2)
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A21–A15
A21–A15
Kwords)
Kwords)
SA54 0101111xxx
SA55 0110000xxx
SA56 0110001xxx
SA57 0110010xxx
SA58 0110011xxx
SA59 0100100xxx
SA60 0110101xxx
SA61 0110110xxx
SA62 0110111xxx
SA63 0111000xxx
SA64 0111001xxx
SA65 0111010xxx
SA66 0111011xxx
SA67 0111100xxx
SA68 0111101xxx
SA69 0111110xxx
SA70 0111111xxx
SA71 1000000xxx
SA72 1000001xxx
SA73 1000010xxx
SA74 1000011xxx
SA75 1000100xxx
SA76 1000101xxx
SA77 1000110xxx
SA78 1000111xxx
SA79 1001000xxx
SA80 1001001xxx
SA81 1001010xxx
SA82 1001011xxx
SA83 1001100xxx
SA84 1001101xxx
SA85 1001110xxx
SA86 1001111xxx
SA87 1010000xxx
SA88 1010001xxx
SA89 1010010xxx
SA90 1010011xxx
SA91 1010100xxx
SA92 1010101xxx
SA93 1010110xxx
SA94 1010111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
2F0000h–2FFFFFh 178000h–17FFFFh
300000h–30FFFFh 180000h–187FFFh
310000h–31FFFFh 188000h–18FFFFh
320000h–32FFFFh 190000h–197FFFh
330000h–33FFFFh 198000h–19FFFFh
SA95 1011000xxx
SA96 1011001xxx
SA97 1011010xxx
SA98 1011011xxx
SA99 1011100xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
580000h–58FFFFh 2C0000h–2C7FFFh
590000h–59FFFFh 2C8000h–2CFFFFh
5A0000h–5AFFFFh 2D0000h–2D7FFFh
5B0000h–5BFFFFh 2D8000h–2DFFFFh
5C0000h–5CFFFFh 2E0000h–2E7FFFh
5D0000h–5DFFFFh 2E8000h–2EFFFFh
5E0000h–5EFFFFh 2F0000h–2FFFFFh
5F0000h–5FFFFFh 2F8000h–2FFFFFh
600000h–60FFFFh 300000h–307FFFh
610000h–61FFFFh 308000h–30FFFFh
620000h–62FFFFh 310000h–317FFFh
630000h–63FFFFh 318000h–31FFFFh
640000h–64FFFFh 320000h–327FFFh
650000h–65FFFFh 328000h–32FFFFh
660000h–66FFFFh 330000h–337FFFh
670000h–67FFFFh 338000h–33FFFFh
680000h–68FFFFh 340000h–347FFFh
690000h–69FFFFh 348000h–34FFFFh
6A0000h–6AFFFFh 350000h–357FFFh
6B0000h–6BFFFFh 358000h–35FFFFh
6C0000h–6CFFFFh 360000h–367FFFh
6D0000h–6DFFFFh 368000h–36FFFFh
6E0000h–6EFFFFh 370000h–377FFFh
6F0000h–6FFFFFh 378000h–37FFFFh
700000h–70FFFFh 380000h–387FFFh
710000h–71FFFFh 388000h–38FFFFh
720000h–72FFFFh 390000h–397FFFh
730000h–73FFFFh 398000h–39FFFFh
740000h–74FFFFh 3A0000h–3A7FFFh
750000h–75FFFFh 3A8000h–3AFFFFh
760000h–76FFFFh 3B0000h–3B7FFFh
770000h–77FFFFh 3B8000h–3BFFFFh
780000h–78FFFFh 3C0000h–3C7FFFh
790000h–79FFFFh 3C8000h–3CFFFFh
7A0000h–7AFFFFh 3D0000h–3D7FFFh
7B0000h–7BFFFFh 3D8000h–3DFFFFh
7C0000h–7CFFFFh 3E0000h–3E7FFFh
7D0000h–7DFFFFh 3E8000h–3EFFFFh
7E0000h–7EFFFFh 3F0000h–3F7FFFh
7F0000h–7FFFFFh 3F8000h–3FFFFFh
340000h–34FFFFh 1A0000h–1A7FFFh SA100 1011101xxx
350000h–35FFFFh 1A8000h–1AFFFFh SA101 1011110xxx
360000h–36FFFFh 1B0000h–1B7FFFh SA102 1011111xxx
370000h–37FFFFh 1B8000h–1BFFFFh SA103 1100000xxx
380000h–38FFFFh 1C0000h–1C7FFFh SA104 1100001xxx
390000h–39FFFFh 1C8000h–1CFFFFh SA105 1100010xxx
3A0000h–3AFFFFh 1D0000h–1D7FFFh SA106 1100011xxx
3B0000h–3BFFFFh 1D8000h–1DFFFFh SA107 1100100xxx
3C0000h–3CFFFFh 1E0000h–1E7FFFh SA108 1100101xxx
3D0000h–3DFFFFh 1E8000h–1EFFFFh SA109 1100110xxx
3E0000h–3EFFFFh 1F0000h–1F7FFFh SA110 1100111xxx
3F0000h–3FFFFFh 1F8000h–1FFFFFh SA111 1101000xxx
400000h–40FFFFh 200000h–207FFFh SA112 1101001xxx
410000h–41FFFFh 208000h–20FFFFh SA113 1101010xxx
420000h–42FFFFh 210000h–217FFFh SA114 1101011xxx
430000h–43FFFFh 218000h–21FFFFh SA115 1101100xxx
440000h–44FFFFh 220000h–227FFFh SA116 1101101xxx
450000h–45FFFFh 228000h–22FFFFh SA117 1101110xxx
460000h–46FFFFh 230000h–237FFFh SA118 1101111xxx
470000h–47FFFFh 238000h–23FFFFh SA119 1110000xxx
480000h–48FFFFh 240000h–247FFFh SA120 1110001xxx
490000h–49FFFFh 248000h–24FFFFh SA121 1110010xxx
4A0000h–4AFFFFh 250000h–257FFFh SA122 1110011xxx
4B0000h–4BFFFFh 258000h–25FFFFh SA123 1110100xxx
4C0000h–4CFFFFh 260000h–267FFFh SA124 1110101xxx
4D0000h–4DFFFFh 268000h–26FFFFh SA125 1110110xxx
4E0000h–4EFFFFh 270000h–277FFFh SA126 1110111xxx
4F0000h–4FFFFFh 278000h–27FFFFh SA127 1111000xxx
500000h–50FFFFh 280000h–28FFFFh SA128 1111001xxx
510000h–51FFFFh 288000h–28FFFFh SA129 1111010xxx
520000h–52FFFFh 290000h–297FFFh SA130 1111011xxx
530000h–53FFFFh 298000h–29FFFFh SA131 1111100xxx
540000h–54FFFFh 2A0000h–2A7FFFh SA132 1111101xxx
550000h–55FFFFh 2A8000h–2AFFFFh SA133 1111110xxx
560000h–56FFFFh 2B0000h–2B7FFFh SA134 1111111000
570000h–57FFFFh 2B8000h–2BFFFFh
Table 10. S29GL064A (Model R5) Sector Addresses (Sheet 1 of 2)
16-bit
Address
Range
16-bit
Address
Range
A21–A15
A21–A15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
28
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Table 10. S29GL064A (Model R5) Sector Addresses (Sheet 2 of 2)
16-bit
Address
Range
16-bit
Address
Range
A21–A15
A21–A15
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
Table 11. S29GL064A (Models R6, R7) Sector Addresses (Sheet 1 of 2)
16-bit
Address
Range
16-bit
Address
Range
A21–A15
A21–A15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
29
A d v a n c e I n f o r m a t i o n
Table 11. S29GL064A (Models R6, R7) Sector Addresses (Sheet 2 of 2)
16-bit
Address
Range
16-bit
Address
Range
A21–A15
A21–A15
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
group protection verification, through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment to automatically match a
device to be programmed with its corresponding programming algorithm. How-
ever, the autoselect codes can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode requires VID on ad-
dress pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 12.
In addition, when verifying sector protection, the sector address must appear on
the appropriate highest order address bits (see Table 4-Table 20). Table 12 shows
the remaining address bits that are don’t care. When all necessary bits have been
set as required, the programming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autose-
lect command via the command register, as shown in Table 25 and Table 26. This
30
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
method does not require VID. Refer to the Autoselect Command Sequence section
for more information.
Table 12. Autoselect Codes, (High Voltage Method)
DQ7 to DQ0
DQ8 to DQ15
BYTE# = BYTE# =
Model Number
A22 A14
to to
A8
to
A5 A3
to to
Description
Manufacturer
ID: Spansion
Products
CE# OE# WE# A15 A10 A9 A7 A6 A4 A2 A1 A0
V
V
R1, R2, R8, R9
R3, R4
R5, R6, R7
IH
IL
L
L
H
X
X
V
X
L
X
L
L
L
00
X
01h
01h
01h
ID
Cycle 1
Cycle 2
L
H
L
H
H
L
22
22
X
X
7Eh
0Ch
7Eh
10h
7Eh
13h
00h (-R4,
bottom boot)
01h (-R3, top
boot)
L
L
H
X
X
V
X
L
X
ID
Cycle 3
H
H
H
22
X
01h
01h
Cycle 1
Cycle 2
L
H
L
H
H
L
22
22
X
X
7Eh
1Dh
7Eh
1Ah
00h (-R4,
bottom boot)
01h (-R3,
top boot)
L
L
H
X
X
V
X
L
X
ID
Cycle 3
H
L
H
H
H
L
22
X
X
X
00h
Sector Group
Protection
Verification
01h (protected),
00h (unprotected)
L
L
L
L
H
H
SA
X
X
X
V
V
X
X
L
L
X
X
ID
ID
Secured Silicon
Sector Indicator
Bit (DQ7), WP#
protects highest
address sector
Secured Silicon
Sector Indicator
Bit (DQ7), WP#
protects lowest
address sector
98h (factory locked),
18h (not factory locked)
L
L
H
H
H
H
X
X
X
X
88h (factory locked),
08h (not factory locked)
L
L
H
X
X
V
X
L
X
ID
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Group Protection and Unprotection
The hardware sector group protection feature disables both program and erase
operations in any sector group (see Table 11-Table 20). The hardware sector
group unprotection feature re-enables both program and erase operations in pre-
viously protected sector groups. Sector group protection/unprotection can be
implemented via two methods.
Sector protection/unprotection requires VID on the RESET# pin only, and can be
implemented either in-system or via programming equipment. Figure 2 shows
the algorithms and Figure 24 shows the timing diagram. This method uses stan-
dard microprocessor bus cycle timing. For sector group unprotect, all unprotected
sector groups must first be protected prior to the first sector group unprotect
write cycle.
The device is shipped with all sector groups unprotected. Spansion offers the op-
tion of programming and protecting sector groups at its factory prior to shipping
the device through Spansion Programming Service. Contact a Spansion represen-
tative for details.
It is possible to determine whether a sector group is protected or unprotected.
See the Autoselect Mode section for details.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
31
A d v a n c e I n f o r m a t i o n
Table 13. S29GL032A (Models R1, R2) Sector Group Protection/Unprotection Addresses
Sector Group
SA0
A20–A15
000000
000001
000010
000011
0001xx
0010xx
Sector Group
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
A20–A15
0011xx
0100xx
0101xx
0110xx
0111xx
1000xx
Sector Group
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
A20–A15
1001xx
1010xx
1011xx
1100xx
1101xx
Sector Group
SA56–SA59
SA60
A20–A15
1110xx
111100
111101
111110
111111
SA1
SA2
SA3
SA61
SA62
SA63
SA4–SA7
SA8–SA11
Table 14. S29GL032A (Models R3) Sector Group Protection/Unprotection Address Table
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector
A20–A12
Sector
A20–A12
Sector
A20–A12
SA0-SA3
SA4-SA7
SA8-SA11
SA12-SA15 0011XXXXXh
SA16-SA19 0100XXXXXh
SA20-SA23 0101XXXXXh
SA24-SA27 0110XXXXXh
SA28-SA31 0111XXXXXh
SA32–SA35 1000XXXXXh
0000XXXXXh
0001XXXXXh
0010XXXXXh
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA36–SA39 1001XXXXXh
SA40–SA43 1010XXXXXh
SA44–SA47 1011XXXXXh
SA48–SA51 1100XXXXXh
SA52-SA55 1101XXXXXh
SA56-SA59 1110XXXXXh
111100XXXh
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
111111000h
111111001h
111111010h
111111011h
111111100h
111111101h
111111110h
111111111h
8
8
8
8
8
8
8
8
SA60-SA62 111101XXXh
111110XXXh
192 (3x64)
Table 15. S29GL032A (Models R4) Sector Group Protection/Unprotection Address Table
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector
A20–A12
Sector
A20–A12
Sector
A20–A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
000000000h
000000001h
000000010h
000000011h
000000100h
000000101h
000000110h
000000111h
8
8
8
8
8
8
8
8
000001XXXh
000010XXXh
000011XXXh
SA35-SA38 0111XXXXXh
SA39-SA42 1000XXXXXh
SA43-SA46 1001XXXXXh
SA47-SA50 1010XXXXXh
SA51-SA54 1011XXXXXh
SA55–SA58 1100XXXXXh
SA59–SA62 1101XXXXXh
SA63–SA66 1110XXXXXh
SA67–SA70 1111XXXXXh
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA8–SA10
192 (3x64)
SA11–SA14 0001XXXXXh
SA15–SA18 0010XXXXXh
SA19–SA22 0011XXXXXh
SA23–SA26 0100XXXXXh
SA27-SA30 0101XXXXXh
SA31-SA34 0110XXXXXh
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Table 16. S29GL064A (Models R1, R2, R8, R9) Sector Group Protection/Unprotection Addresses
Sector Group
A21–A15
0000000
0000001
0000010
0000011
00001xx
00010xx
00011xx
00100xx
00101xx
00110xx
Sector Group
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
A21–A15
00111xx
01000xx
01001xx
01010xx
01011xx
01100xx
01101xx
01110xx
01111xx
10000xx
Sector Group
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
A21–A15
10001xx
10010xx
10011xx
10100xx
10101xx
10110xx
10111xx
11000xx
11001xx
11010xx
Sector Group
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124
A21–A15
11011xx
11100xx
11101xx
11110xx
1111100
1111101
1111110
1111111
SA0
SA1
SA2
SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA125
SA126
SA127
32
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Table 17. S29GL064A (Model R3) Top Boot Sector Protection/Unprotection Addresses
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector
A21–A12
Sector
A20–A12
Sector
A20–A12
SA0-SA3
SA4-SA7
SA8-SA11 00010XXXXX
00000XXXXX
00001XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
SA56-SA59
SA60-SA63
SA64-SA67
01110XXXXX
01111XXXXX
10000XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
SA112-SA115 11100XXXXX
SA116-SA119 11101XXXXX
SA120-SA123 11110XXXXX
1111100XXX
256 (4x64)
256 (4x64)
256 (4x64)
SA12-SA15 00011XXXXX
256 (4x64)
SA68-SA71
10001XXXXX
256 (4x64)
SA124-SA126 1111101XXX
1111110XXX
192 (3x64)
SA16-SA19 00100XXXXX
SA20-SA23 00101XXXXX
SA24-SA27 00110XXXXX
SA28-SA31 00111XXXXX
SA32-SA35 01000XXXXX
SA36-SA39 01001XXXXX
SA40-SA43 01010XXXXX
SA44-SA47 01011XXXXX
SA48-SA51 01100XXXXX
SA52-SA55 01101XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA72-SA75
SA76-SA79
SA80-SA83
SA84-SA87
SA88-SA91
SA92-SA95
SA96-SA99
SA100-SA103 11001XXXXX
SA104-SA107 11010XXXXX
SA108-SA111 11011XXXXX
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
8
8
8
8
8
8
8
8
Table 18. S29GL064A (Model R4) Bottom Boot Sector Protection/Unprotection Addresses
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector
A21–A12
Sector
A20–A12
Sector
A20–A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001XXX,
8
8
8
8
8
8
8
8
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55–SA58
SA59–SA62
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA87–SA90
SA91–SA94
SA95–SA98
SA99–SA102 10111XXXXX
SA103–SA106 11000XXXXX
SA107–SA110 11001XXXXX
SA111–SA114 11010XXXXX
SA115–SA118 11011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA8–SA10 0000010XXX,
192 (3x64)
SA63–SA66
01110XXXXX
256 (4x64)
SA119–SA122 11100XXXXX
256 (4x64)
0000011XXX,
SA11–SA14 00001XXXXX
SA15–SA18 00010XXXXX
SA19–SA22 00011XXXXX
SA23–SA26 00100XXXXX
SA27-SA30 00101XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
SA83–SA86
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA123–SA126 11101XXXXX
SA127–SA130 11110XXXXX
SA131–SA134 11111XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
Table 19. S29GL064A (Model R5) Sector Group Protection/Unprotection Addresses
Sector Group
SA0–SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
A21–A15
00000
00001
00010
00011
00100
00101
00110
00111
Sector Group
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
A21–A15
01000
01001
01010
01011
01100
01101
01110
01111
Sector Group
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
A21–A15
10000
10001
10010
10011
10100
10101
10110
10111
Sector Group
SA96–SA99
A21–A15
11000
11001
11010
11011
11100
11101
11110
11111
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
Note: All sector groups are 128 Kwords in size.
Table 20. S29GL064A (Models R6, R7) Sector Group Protection/Unprotection Addresses
Sector Group
SA0–SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
A21–A15
00000
00001
00010
00011
00100
00101
00110
00111
Sector Group
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
A21–A15
01000
01001
01010
01011
01100
01101
01110
01111
Sector Group
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
A21–A15
10000
10001
10010
10011
10100
10101
10110
10111
Sector Group
SA96–SA99
A21–A15
11000
11001
11010
11011
11100
11101
11110
11111
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
Note: All sector groups are 128 Kwords in size.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
33
A d v a n c e I n f o r m a t i o n
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector groups
to change data in-system. The Sector Group Unprotect mode is activated by set-
ting the RESET# pin to VID. During this mode, formerly protected sector groups
can be programmed or erased by selecting the sector group addresses. Once VID
is removed from the RESET# pin, all the previously protected sector groups are
protected again. Figure 1 shows the algorithm, and Figure 22 shows the timing
diagrams, for this feature.
START
RESET# = V
(Note 1)
ID
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Group Unprotect Completed
(Note 2)
Notes:
1. All protected sector groups unprotected (If WP# = V , the highest or lowest address sector will remain protected for
IL
uniform sector devices; the top or bottom two address sectors will remain protected for boot sector devices).
2. All previously protected sector groups are protected once again.
Figure 1. Temporary Sector Group Unprotect Operation
34
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
START
START
PLSCNT = 1
PLSCNT = 1
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
RESET# = VID
Wait 1 µs
Wait 1 µs
Temporary Sector
Group Unprotect
Mode
Temporary Sector
Group Unprotect
Mode
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Yes
Yes
Set up sector
group address
All sector
groups
No
protected?
Yes
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up first sector
group address
Sector Group
Unprotect:
Wait 150 µs
Write 60h to sector
group address with
A6–A0 = 1xx0010
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
Read from
sector group address
with A6–A0
= 0xx0010
Increment
PLSCNT
A6–A0 = 1xx0010
No
No
PLSCNT
= 25?
Read from
sector group
address with
Data = 01h?
Yes
A6–A0 = 1xx0010
No
Yes
Set up
next sector group
address
Protect
another
sector group?
Yes
No
PLSCNT
= 1000?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
Last sector
group
verified?
No
Device failed
Write reset
command
Yes
Remove VID
from RESET#
Sector Group
Unprotect
Sector Group
Protect
Sector Group
Protect complete
Write reset
command
Algorithm
Algorithm
Sector Group
Unprotect complete
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
35
A d v a n c e I n f o r m a t i o n
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables
permanent part identification through an Electronic Serial Number (ESN). The
Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector
Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked
when shipped from the factory. This bit is permanently set at the factory and can-
not be changed, which prevents cloning of a factory locked part. This ensures the
security of the ESN once the product is shipped to the field.
The factory offers the device with the Secured Silicon Sector either customer
lockable (standard shipping option) or factory locked (contact a Spansion sales
representative for ordering information). The customer-lockable version is
shipped with the Secured Silicon Sector unprotected, allowing customers to pro-
gram the sector after receiving the device. The customer-lockable version also
has the Secured Silicon Sector Indicator Bit permanently set to a “0.” The factory-
locked version is always protected when shipped from the factory, and has the
Secured Silicon Sector Indicator Bit permanently set to a “1.” Thus, the Secured
Silicon Sector Indicator Bit prevents customer-lockable devices from being used
to replace devices that are factory locked. Note that the ACC function and unlock
bypass modes are not available when the Secured Silicon Sector is enabled.
The Secured Silicon sector address space in this device is allocated as follows:
Secured Silicon Sector Address Range
Standard Factory
Locked
ExpressFlash Factory
Locked
x16
x8
Customer Lockable
ESN or determined by
customer
000000h–000007h
000008h–00007Fh
000000h-00000Fh
000010h-0000FFh
ESN
Determined by customer
Unavailable
Determined by customer
The system accesses the Secured Silicon Sector through a command sequence
(see “Write Protect (WP#)”). After the system has written the Enter Secured Sil-
icon Sector command sequence, it may read the Secured Silicon Sector by using
the addresses normally occupied by the first sector (SA0). This mode of operation
continues until the system issues the Exit Secured Silicon Sector command se-
quence, or until power is removed from the device. On power-up, or following a
hardware reset, the device reverts to sending commands to sector SA0.
Customer Lockable: Secured Silicon Sector NOT Programmed or
Protected At the Factory
Unless otherwise specified, the device is shipped such that the customer may
program and protect the 256-byte Secured Silicon sector.
The system may program the Secured Silicon Sector using the write-buffer, ac-
celerated and/or unlock bypass methods, in addition to the standard
programming command sequence. See “Command Definitions” .
Programming and protecting the Secured Silicon Sector must be used with cau-
tion since, once protected, there is no procedure available for unprotecting the
Secured Silicon Sector area and none of the bits in the Secured Silicon Sector
memory space can be modified in any way.
The Secured Silicon Sector area can be protected using one of the following
procedures:
Write the three-cycle Enter Secured Silicon Sector Region command se-
quence, and then follow the in-system sector protect algorithm as shown in
36
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Figure 2, except that RESET# may be at either VIH or VID. This allows in-sys-
tem protection of the Secured Silicon Sector without raising any device pin to
a high voltage. Note that this method is only applicable to the Secured Silicon
Sector.
Write the three-cycle Enter Secured Silicon Sector Region command se-
quence, and then use the alternate method of sector protection described in
the “Sector Group Protection and Unprotection” section.
Once the Secured Silicon Sector is programmed, locked and verified, the system
must write the Exit Secured Silicon Sector Region command sequence to return
to reading and writing within the remainder of the array.
Factory Locked: Secured Silicon Sector Programmed and
Protected At the Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device
is shipped from the factory. The Secured Silicon Sector cannot be modified in any
way. An ESN Factory Locked device has an 16-byte random ESN at addresses
000000h–000007h. Please contact your sales representative for details on order-
ing ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the
Spansion programming service (Customer Factory Locked). The devices are then
shipped from the factory with the Secured Silicon Sector permanently locked.
Contact your sales representative for details on using the Spansion programming
service.
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or
last sector group without using VID. Write Protect is one of two functions provided
by the WP#/ACC input.
If the system asserts VIL on the WP#/ACC pin, the device disables program and
erase functions in the first or last sector group independently of whether those
sector groups were protected or unprotected. Note that if WP#/ACC is at VIL
when the device is in the standby mode, the maximum input load current is in-
creased. See the table in “DC Characteristics” section on page 65.
If the system asserts VIH on the WP#/ACC pin, the device reverts to
whether the first or last sector was previously set to be protected or un-
protected using the method described in “Sector Group Protection and
Unprotection”. Note that WP# has an internal pullup; when uncon-
nected, WP# is at VIH
.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Table 25 and Table
26 for command definitions). In addition, the following hardware data protection
measures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during VCC power-up and power-down
transitions, or from system noise.
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This pro-
tects data during VCC power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
37
A d v a n c e I n f o r m a t i o n
mode. Subsequent writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# =
VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
38
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h, any time the device is ready to read array data.
The system can read CFI information at the addresses given in Table 21-Table 24.
To terminate reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Table 21-Table 24. The system must write the
reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication
100. Alternatively, contact your sales representative for copies of these
documents.
Table 21. CFI Query Identification String
Addresses
(x16)
Addresses
(x8)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
39
A d v a n c e I n f o r m a t i o n
Table 22. System Interface String
Addresses
(x16)
Addresses
(x8)
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
1Ch
36h
38h
0027h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0007h
0007h
000Ah
0000h
0001h
0005h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Reserved for future use
Typical timeout for Min. size buffer write 2N
µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Reserved for future use
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Note: CFI data related to V and time-outs may differ from actual V and time-outs of the product. Please consult the Ordering
CC
CC
Information tables to obtain the V range for particular part numbers. Please consult the Erase and Programming Performance table
CC
for typical timeout specifications.
40
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Table 23. Device Geometry Definition
Addresses
(x16)
Addresses
(x8)
Data
Description
Device Size = 2N byte
27h
4Eh
00xxh
0017h = 64 Mb, 0016h = 32Mb
Flash Device Interface description (refer to CFI publication 100)
28h
29h
50h
52h
000xh
0000h
0000h = x8-only bus devices
0001h = x16-only bus devices
0002h = x8/x16 bus devices
2Ah
2Bh
54h
56h
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device (01h = uniform device,
02h = boot device)
2Ch
58h
00xxh
Erase Block Region 1 Information
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
000xh
00x0h
000xh
(refer to the CFI specification or CFI publication 100)
007Fh, 0000h, 0020h, 0000h = 32 Mb (-R1, -R2)
003Fh, 0000h, 0001h = 32 Mb (-R3, R4)
007Fh, 0000h, 0020h, 0000h = 64 Mb (-R1, -R2, -R8, -R9)
007Fh, 0000h, 0000h, 0001h = 64 Mb (-R3, -R4, -R5, -R6, -R7)
31h
32h
33h
34h
60h
64h
66h
68h
00xxh
0000h
0000h
000xh
Erase Block Region 2 Information (refer to CFI publication 100)
003Eh, 0000h, 0000h, 0001h = 32 Mb (-R1, -R2)
007Eh, 0000h, 0000h, 0001h = 64 Mb (-R1, -R2, -R8, -R9)
0000h, 0000h, 0000h, 0000h = all others
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
January 28, 2005 S29GLxxxA_00_A2
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A d v a n c e I n f o r m a t i o n
Table 24. Primary Vendor-Specific Extended Query
Addresses
(x16)
Addresses
(x8)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
000xh
Process Technology (Bits 7-2) 0010b = 200 nm MirrorBit
0009h = x8-only bus devices
0008h = all other devices
Erase Suspend
46h
47h
48h
49h
4Ah
4Bh
4Ch
8Ch
8Eh
90h
92h
94h
96h
98h
0002h
0001h
0001h
0004h
0000h
0000h
0001h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
0004h = Standard Mode (Refer to Text)
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
9Ah
9Ch
00B5h
00C5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
4Fh
50h
9Eh
A0h
00xxh
0001h
02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform
sectors bottom WP# protect, 05h = Uniform sectors top WP# protect
Program Suspend
00h = Not Supported, 01h = Supported
42
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 25 and Table 26 define the valid register
command sequences. Writing incorrect address and data values or writing them
in the improper sequence may place the device in an unknown state. A reset com-
mand is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the
erase-suspend-read mode, after which the system can read data from any non-
erase-suspended sector. After completing a programming operation in the Erase
Suspend mode, the system may once again read array data with the same ex-
ception. See the Erase Suspend/Erase Resume Commands section for more
information.
The system must issue the reset command to return the device to the read (or
erase-suspend-read) mode if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode. See the next section, Reset
Command, for more information.
See also Requirements for Reading Array Data in the Device Bus Operations sec-
tion for more information. The Read-Only Operations–“AC Characteristics”
section on page 67 provides the read parameters, and Figure 13 shows the timing
diagram.
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ignores reset commands until
the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the device to the
read mode. If the program command sequence is written while the device is in
the Erase Suspend mode, writing the reset command returns the device to the
erase-suspend-read mode. Once programming begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If the device entered the autoselect mode
while in the Erase Suspend mode, writing the reset command returns the device
to the erase-suspend-read mode.
January 28, 2005 S29GLxxxA_00_A2
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A d v a n c e I n f o r m a t i o n
If DQ5 goes high during a program or erase operation, writing the reset command
returns the device to the read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Programming operation, the sys-
tem must write the Write-to-Buffer-Abort Reset command sequence to reset the
device for the next operation.
Autoselect Command Sequence
The autoselect command sequence allows the host system to read several iden-
tifier codes at specific addresses:
A7:A0
(x16)
A6:A-1
(x8)
Identifier Code
Manufacturer ID
Device ID, Cycle 1
00h
01h
00h
02h
Device ID, Cycle 2
0Eh
1Ch
Device ID, Cycle 3
0Fh
1Eh
Secured Silicon Sector Factory Protect
Sector Protect Verify
03h
06h
(SA)02h
(SA)04h
Note: The device ID is read over three cycles. SA = Sector Address
The autoselect command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system may read at any address any
number of times without initiating another autoselect command sequence:
The system must write the reset command to return to the read mode (or erase-
suspend-read mode if the device was previously in Erase Suspend).
Enter Secured Silicon Sector/Exit Secured Silicon
Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing an 8-
word/16-byte random Electronic Serial Number (ESN). The system can access
the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon
Sector command sequence. The device continues to access the Secured Silicon
Sector region until the system issues the four-cycle Exit Secured Silicon Sector
command sequence. The Exit Secured Silicon Sector command sequence returns
the device to normal operation. Table 25 and Table 26 show the address and data
requirements for both command sequences. See also “Secured Silicon Sector
Flash Memory Region” for further information. Note that the ACC function and un-
lock bypass modes are not available when the Secured Silicon Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up com-
mand. The program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to provide further con-
trols or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin. Table 25 and Table 26 show the
address and data requirements for the word program command sequence,
respectively.
44
S29GLxxxA MirrorBit™ Flash Family
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A d v a n c e I n f o r m a t i o n
When the Embedded Program algorithm is complete, the device then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by using DQ7 or DQ6. Refer to the Write Op-
eration Status section for information on these status bits. Any commands
written to the device during the Embedded Program Algorithm are ignored. Note
that the Secured Silicon Sector, autoselect, and CFI functions are unavailable
when a program operation is in progress. Note that a hardware reset immedi-
ately terminates the program operation. The program command sequence should
be reinitiated once the device has returned to the read mode, to ensure data
integrity.
Programming is allowed in any sequence of address locations and across sector
boundaries. Programming to the same word address multiple times without in-
tervening erases (incremental bit programming) requires a modified
programming method. For such application requirements, please contact your
local Spansion representative. Word programming is supported for backward
compatibility with existing Flash driver software and for occasional writing of in-
dividual words. Use of write buffer programming (see below) is strongly
recommended for general programming use when more than a few words are to
be programmed. The effective word programming time using write buffer pro-
gramming is approximately four times shorter than the single word programming
time.
Any bit in a word cannot be programmed from “0” back to a “1.” Attempt-
ing to do so may cause the device to set DQ5=1, or cause DQ7 and DQ6 status
bits to indicate the operation was successful. However, a succeeding read will
show that the data is still “0.” Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass mode command
sequence is all that is required to program in this mode. The first cycle in this se-
quence contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two unlock cycles required in
the standard program command sequence, resulting in faster total programming
time.Table 25 and Table 26 show the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle
must contain the data 90h. The second cycle must contain the data 00h. The de-
vice then returns to the read mode.
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32
bytes in one programming operation. This results in faster effective programming
time than the standard programming algorithms. The Write Buffer Programming
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load command written at the
Sector Address in which programming will occur. The fourth cycle writes the sec-
tor address and the number of word locations, minus one, to be programmed. For
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
45
A d v a n c e I n f o r m a t i o n
example, if the system will program 6 unique address locations, then 05h should
be written to the device. This tells the device how many write buffer addresses
will be loaded with data and therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot exceed the size of the
write buffer or the operation will abort.
The fifth cycle writes the first address location and data to be programmed. The
write-buffer-page is selected by address bits AMAX–A4. All subsequent address/
data pairs must fall within the selected-write-buffer-page. The system then
writes the remaining address/data pairs into the write buffer. Write buffer loca-
tions may be loaded in any order.
The write-buffer-page address must be the same for all address/data pairs loaded
into the write buffer. (This means Write Buffer Programming cannot be performed
across multiple write-buffer pages.) This also means that Write Buffer Program-
ming cannot be performed across multiple sectors. If the system attempts to load
programming data outside of the selected write-buffer page, the operation will
abort.
Note that if a Write Buffer address location is loaded multiple times, the address/
data pair counter will be decremented for every data load operation. The host
system must therefore account for loading a write-buffer location more than
once. The counter decrements for each data load operation, not for each unique
write-buffer-address location. Note also that if an address location is loaded more
than once into the buffer, the final data loaded for that address will be
programmed.
Once the specified number of write buffer locations have been loaded, the system
must then write the Program Buffer to Flash command at the sector address. Any
other address and data combination aborts the Write Buffer Programming oper-
ation. The device then begins programming. Data polling should be used while
monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5,
and DQ1 should be monitored to determine the device status during Write Buffer
Programming.
The write-buffer programming operation can be suspended using the standard
program suspend/resume commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to execute the next command.
The Write Buffer Programming Sequence can be aborted in the following ways:
Load a value that is greater than the page buffer size during the Number of
Locations to Program step.
Write to an address in a sector different than the one specified during the
Write-Buffer-Load command.
Write an Address/Data pair to a different write-buffer-page than the one se-
lected by the Starting Address during the write buffer data loading stage of
the operation.
Write data other than the Confirm Command after the specified number of
data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address
location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset com-
mand sequence must be written to reset the device for the next operation.
Note that the Secured Silicon Sector, autoselect, and CFI functions are unavail-
able when a program operation is in progress.This flash device is capable of
handling multiple write buffer programming operations on the same write buffer
address range without intervening erases. For applications requiring incremental
46
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
bit programming, a modified programming method is required; please contact
your local Spansion representative. Any bit in a write buffer address range
cannot be programmed from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5=1, of cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeeding read will show that the data
is still “0.” Only erase operations can convert a “0” to a “1.”
Accelerated Program
The device offers accelerated program operations through the WP#/ACC or ACC
pin depending on the particular product. When the system asserts VHH on the
WP#/ACC or ACC pin. The device uses the higher voltage on the WP#/ACC or ACC
pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH
for operations other than accelerated programming, or device damage may re-
sult. WP# has an internal pullup; when unconnected, WP# is at VIH
.
Figure 3 illustrates the algorithm for the program operation. Refer to the Erase
and Program Operations–“AC Characteristics” section on page 67 section for pa-
rameters, and Figure 14 for timing diagrams.
January 28, 2005 S29GLxxxA_00_A2
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A d v a n c e I n f o r m a t i o n
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Buffer Operation?
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
Write next address/data pair
(Note 1)
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Read DQ7 - DQ0 at
Last Loaded Address
Yes
DQ7 = Data?
No
No
No
DQ1 = 1?
DQ5 = 1?
Yes
Yes
Read DQ7 - DQ0 with
address = Last Loaded
Address
Yes
(Note 2)
DQ7 = Data?
No
FAIL or ABORT
PASS
(Note 3)
Notes:
1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer
address locations with data, all addresses must fall within the selected Write-Buffer Page.
2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified.
3. If this flowchart location was reached because DQ5= “1”, then the device FAILED. If this flowchart location was reached
because DQ1= “1”, then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be
written before the device can begin another operation. If DQ1=1, write the Write-Buffer-Programming-Abort-Reset
command. if DQ5=1, write the Reset command.
4. See Table 25 and Table 26 for command sequences required for write buffer programming.
Figure 3. Write Buffer Programming Operation
48
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
Programming
Completed
Note:See Table 25 and Table 26 for program command sequence
.
Figure 4. Program Operation
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming
operation or a Write to Buffer programming operation so that data can be read
from any non-suspended sector. When the Program Suspend command is written
during a programming process, the device halts the program operation within 15
µs maximum (5µs typical) and updates the status bits. Addresses are not re-
quired when writing the Program Suspend command.
After the programming operation has been suspended, the system can read array
data from any non-suspended sector. The Program Suspend command may also
be issued during a programming operation while an erase is suspended. In this
case, data may be read from any addresses not in Erase Suspend or Program
Suspend. If a read is needed from the Secured Silicon Sector area (One-time Pro-
gram area), then user must use the proper command sequences to enter and exit
this region. Note that the Secured Silicon Sector, autoselect, and CFI functions
are unavailable when a program operation is in progress.
The system may also write the autoselect command sequence when the device
is in the Program Suspend mode. The system can read as many autoselect codes
as required. When the device exits the autoselect mode, the device reverts to the
Program Suspend mode, and is ready for another valid operation. See Autoselect
Command Sequence for more information.
January 28, 2005 S29GLxxxA_00_A2
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A d v a n c e I n f o r m a t i o n
After the Program Resume command is written, the device reverts to program-
ming. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See Write Op-
eration Status for more information.
The system must write the Program Resume command (address bits are don’t
care) to exit the Program Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ignored. Another Program
Suspend command can be written after the device has resumed programming.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Write address/data
XXXh/B0h
Command is also valid for
Erase-suspended-program
operations
Wait 15 µs
Autoselect and SecSi Sector
read operations are also allowed
Read data as
required
Data cannot be read from erase- or
program-suspended sectors
Done
No
reading?
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Figure 5. Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Table 25 and Table 26 show the address and data
requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation
Status section for information on these status bits.
50
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Any commands written during the chip erase operation are ignored. However,
note that a hardware reset immediately terminates the erase operation. If that
occurs, the chip erase command sequence should be reinitiated once the device
has returned to reading array data, to ensure data integrity.
Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and
Program Operations table in the AC Characteristics section for parameters, and
Figure 18 section for timing diagrams.
January 28, 2005 S29GLxxxA_00_A2
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A d v a n c e I n f o r m a t i o n
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table 25 and Table 26 shows
the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 µs, otherwise erasure
may begin. Any sector erase address and command following the exceeded time-
out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written. Any com-
mand other than Sector Erase or Erase Suspend during the time-out
period resets the device to the read mode. Note that the Secured Silicon
Sector, autoselect, and CFI functions are unavailable when an erase op-
eration is in progress. The system must rewrite the command sequence and
any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector.
Refer to the Write Operation Status section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and
Program Operations table in the AC Characteristics section for parameters, and
Figure 18 section for timing diagrams.
52
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A d v a n c e I n f o r m a t i o n
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 25 and Table 26 for program command sequence.
2. See the section on DQ3 for information on the sector erase timer.
Figure 6. Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase
operation and then read data from, or program data to, any sector not selected
for erasure. This command is valid only during the sector erase operation, includ-
ing the 50 µs time-out period during the sector erase command sequence. The
Erase Suspend command is ignored if written during the chip erase operation or
Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation,
the device requires a typical of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend command is written during the sec-
tor erase time-out, the device immediately terminates the time-out period and
suspends the erase operation.
After the erase operation has been suspended, the device enters the erase-sus-
pend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for
erasure.) Reading at any address within erase-suspended sectors produces sta-
tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer
to the Write Operation Status section for information on these status bits.
After an erase-suspended program operation is complete, the device returns to
the erase-suspend-read mode. The system can determine the status of the pro-
gram operation using the DQ7 or DQ6 status bits, just as in the standard word
January 28, 2005 S29GLxxxA_00_A2
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A d v a n c e I n f o r m a t i o n
program operation. Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also issue the autoselect com-
mand sequence. Refer to the “Autoselect Mode” section on page 30 and
“Autoselect Command Sequence” section on page 44 sections for details.
To resume the sector erase operation, the system must write the Erase Resume
command. Further writes of the Resume command are ignored. Another Erase
Suspend command can be written after the chip has resumed erasing.
Note:During an erase operation, this flash device performs multiple internal operations which are invisible to the system. When an
erase operation is suspended, any of the internal operations that were not fully completed must be restarted. As such, if this flash
device is continually issued suspend/resume commands in rapid succession, erase progress will be impeded as a function of the
number of suspends. The result will be a longer cumulative erase time than without suspends. Note that the additional suspends do
not affect device reliability or future performance. In most systems rapid erase/suspend activity occurs only briefly. In such cases,
erase performance will not be significantly impacted
.
54
S29GLxxxA MirrorBit™ Flash Family
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A d v a n c e I n f o r m a t i o n
Command Definitions
Table 25. Command Definitions (x16 Mode, BYTE# = V
)
IH
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
4
RA
XXX
555
RD
F0
Manufacturer ID
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
(Note
18)
(Note
18)
Device ID (Note 9)
4
4
555
555
AA
AA
X0E
X0F
Secured SiliconSector Factory
Protect (Note 10)
2AA
2AA
55
55
555
555
90
90
X03
(Note 10)
00/01
Sector Group Protect Verify (Note
12)
4
555
AA
(SA)X02
Enter Secured Silicon Sector Region
Exit Secured Silicon Sector Region
Program
3
4
4
3
1
3
3
2
2
6
6
1
1
1
555
555
555
555
SA
AA
AA
AA
AA
29
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
00
PD
WC
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 13)
Unlock Bypass
SA
PA
PD
WBL
PD
555
555
XXX
XXX
555
555
XXX
XXX
55
AA
AA
A0
90
2AA
2AA
PA
55
55
PD
00
55
55
555
555
F0
20
Unlock Bypass Program (Note 14)
Unlock Bypass Reset (Note 15)
Chip Erase
XXX
2AA
2AA
AA
AA
B0
30
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend (Note 16)
Program/Erase Resume (Note 17)
CFI Query (Note 18)
98
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 3 for description of bus operations.
2. All values are in hexadecimal.
10. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
11. Total number of cycles in command sequence is determined by
number of words written to write buffer. Maximum number of
cycles in command sequence is 21, including “Program Buffer to
Flash” command.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
13. Unlock Bypass command is required prior to Unlock Bypass
Program command.
14. Unlock Bypass Reset command is required to return to read
mode when device is in unlock bypass mode.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are
555 or 2AA as shown in table, address bits above A11 and data
bits above DQ7 are don’t care.
5. No unlock or command cycles required when device is in read
mode.
6. Reset command is required to return to read mode (or to erase-
suspend-read mode if previously in Erase Suspend) when device
is in autoselect mode, or if DQ5 goes high while device is
providing status information.
15. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
16. Erase Resume command is valid only during Erase Suspend
mode.
7. Fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD
and WC. See Autoselect Command Sequence section for more
information.
8. Device ID must be read in three cycles.
17. Command is valid when device is ready to read array data or
when device is in autoselect mode.
18. Refer to Table 12, AutoSelect Codes for individual Device IDs
per device density and model number.
9. If WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. If WP# protects lowest
address sector, data is 88h for factory locked and 08h for not
factor locked.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
55
A d v a n c e I n f o r m a t i o n
Table 26. Command Definitions (x8 Mode, BYTE# = V )
IL
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Addr Data
Sixth
Addr Data
Addr Data Addr Data Addr Data
Addr
Data
Read (Note 6)
Reset (Note 7)
Manufacturer ID
1
1
4
4
RA
RD
F0
XXX
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
90
90
X00
X02
01
7E
Device ID (Note 9)
X1C (Note 17) X1E (Note 17)
Secured Silicon Sector Factory
Protect (Note 10)
4
AAA
AA
555
55
AAA
90
X06
(Note 10)
Sector Group Protect Verify (Note
12)
4
AAA
AA
555
55
AAA
90
(SA)X04
00/01
Enter Secured Silicon Sector Region
Exit Secured Silicon Sector Region
Write to Buffer (Note 11)
3
4
3
1
3
6
6
1
1
1
AAA
AAA
AAA
SA
AA
AA
AA
29
555
555
555
55
55
55
AAA
AAA
SA
88
90
25
XXX
SA
00
BC
PA
PD
WBL
PD
Program Buffer to Flash
Write to Buffer Abort Reset (Note 13)
Chip Erase
AAA
AAA
AAA
XXX
XXX
AA
AA
AA
AA
B0
30
555
555
555
55
55
55
AAA
AAA
AAA
F0
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Program/Erase Suspend (Note 14)
Program/Erase Resume (Note 15)
CFI Query (Note 16)
98
Legend:
X = Don’t care
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
RA = Read Address of memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
BC = Byte Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 3 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are
555 or AAA as shown in table, address bits above A11 are don’t
care.
10. If WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. If WP# protects lowest
address sector, data is 88h for factory locked and 08h for not
factor locked.
11. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
12. Total number of cycles in command sequence is determined by
number of bytes written to write buffer. Maximum number of
cycles in command sequence is 37, including “Program Buffer to
Flash” command.
13. Command sequence resets device for next command after
aborted write-to-buffer operation.
14. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
15. Erase Resume command is valid only during Erase Suspend
mode.
5. Unless otherwise noted, address bits A21–A11 are don’t cares.
6. No unlock or command cycles required when device is in read
mode.
7. Reset command is required to return to read mode (or to erase-
suspend-read mode if previously in Erase Suspend) when device
is in autoselect mode, or if DQ5 goes high while device is
providing status information.
8. Fourth cycle of autoselect command sequence is a read cycle.
Data bits DQ15–DQ8 are don’t care. See Autoselect Command
Sequence section or more information.
9. Device ID must be read in three cycles.
16. Command is valid when device is ready to read array data or
when device is in autoselect mode.
17. Refer to Table 12, AutoSelect Codes for individual Device IDs
per device density and model number.
56
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Write Operation Status
The device provides several bits to determine the status of a program or erase
operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 27 and the following subsec-
tions describe the function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress.
The device also provides a hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is in progress or has been
completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Program or Erase algorithm is in progress or completed, or whether the device is
in Erase Suspend. Data# Polling is valid after the rising edge of the final WE#
pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must
provide an address within any of the sectors selected for erasure to read valid
status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7
may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is as-
serted low. That is, the device may change from providing status information to
valid data on DQ7. Depending on when the system samples the DQ7 output, it
may read the status or valid data. Even if the device has completed the program
or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may
be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.
Table 27 shows the outputs for Data# Polling on DQ7. Figure 7 shows the Data#
Polling algorithm. Figure 19 in the AC Characteristics section shows the Data#
Polling timing diagram.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
57
A d v a n c e I n f o r m a t i o n
START
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector
being erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 7. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an
Embedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel with
a pull-up resistor to VCC
.
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is in the read mode, the standby mode, or in the erase-suspend-read
mode. Table 27 shows the outputs for RY/BY#.
58
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table 27 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit
algorithm. Figure 20 in the “AC Characteristics” section shows the toggle bit tim-
ing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical
form. See also the subsection on DQ2: Toggle Bit II.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
59
A d v a n c e I n f o r m a t i o n
START
Read DQ7–DQ0
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes
to “1.” See the subsections on DQ6 and DQ2 for more information.
Figure 8. Toggle Bit Algorithm
60
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 27 to compare outputs for DQ2 and DQ6.
Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2:
Toggle Bit II” explains the algorithm. See also the RY/BY#: Ready/Busy# subsec-
tion. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the
differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8 for the following discussion. Whenever the system initially be-
gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of Figure 8).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time has ex-
ceeded a specified internal pulse count limit. Under these conditions DQ5
produces a “1,” indicating that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a
location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the device halts the opera-
tion, and when the timing limit has been exceeded, DQ5 produces a “1.”
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
61
A d v a n c e I n f o r m a t i o n
In all these cases, the system must write the reset command to return the device
to the reading the array (or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase commands from the system can be as-
sumed to be less than 50 µs, the system need not monitor DQ3. See also the
Sector Erase Command Sequence section.
After the sector erase command is written, the system should read the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device will accept addi-
tional sector erase commands. To ensure the command has been accepted, the
system software should check the status of DQ3 prior to and following each sub-
sequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 27 shows the status of DQ3 relative to the other status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these
conditions DQ1 produces a “1”. The system must issue the Write-to-Buffer-Abort-
Reset command sequence to return the device to reading array data. See Write
Buffer section for more details.
62
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Table 27. Write Operation Status
DQ7
(Note 2)
DQ5
(Note 1) DQ3
DQ2
(Note 2)
RY/
BY#
Status
DQ6
Toggle
Toggle
DQ1
0
Embedded Program Algorithm
Embedded Erase Algorithm
Program-Suspended
DQ7#
0
0
0
N/A
1
No toggle
Toggle
0
0
Standard
Mode
N/A
Invalid (not allowed)
Data
1
1
1
1
0
Program
Suspend
Mode
Program-
Suspend
Read
Sector
Non-Program
Suspended Sector
Erase-Suspended
Sector
1
No toggle
Toggle
0
N/A
Toggle
N/A
N/A
N/A
Erase-
Suspend
Read
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Erase-Suspend-Program
(Embedded Program)
DQ7#
0
N/A
Busy (Note 3)
Abort (Note 4)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Write-to-
Buffer
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for
further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
63
A d v a n c e I n f o r m a t i o n
Absolute Maximum Ratings
Storage Temperature, Plastic Packages. . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground:
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, ACC and RESET# (Note 2) . . . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1). . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs
or I/Os may overshoot V to –2.0 V for periods of up to 20 ns. See Figure 9.
SS
Maximum DC voltage on input or I/Os is V + 0.5 V. During voltage transitions,
CC
input or I/O pins may overshoot to V + 2.0 V for periods up to 20 ns. See Figure
CC
10.
2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During
voltage transitions, A9, OE#, ACC, and RESET# may overshoot V to –2.0 V for
SS
periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pin A9, OE#,
ACC, and RESET# is +12.5 V which may overshoot to +14.0V for periods up to
20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods may affect device
reliability.
20 ns
20 ns
20 ns
V
+0.8 V
CC
+2.0 V
V
–0.5 V
–2.0 V
CC
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 9. Maximum Negative
Overshoot Waveform
Figure 10. Maximum Positive
Overshoot Waveform
Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC for full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V
VCC for regulated voltage range. . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V
VIO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC
Note:Operating ranges define those limits between which the functionality of the device is guaranteed
.
64
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
DC Characteristics
CMOS Compatible
Parameter
Parameter Description (Notes)
Test Conditions
= V to V
Min
Typ
Max
Unit
Symbol
V
V
,
CC
IN
CC
SS
= V
I
Input Load Current (Note 1)
A9, ACC Input Load Current
±1.0
µA
LI
CC max
-40°C to 0°C
0°C to 85°C
250
35
V
= V
12.5 V
; A9 =
CC
CC max
I
I
µA
LIT
I
Reset Leakage Current
Output Leakage Current
V
= V
; RESET# = 12.5 V
35
µA
µA
LR
CC
CC max
V
V
= V to V
SS
CC max
,
CC
OUT
±1.0
LO
= V
CC
1 MHz
5
20
25
50
20
40
60
CE# = V OE# =
IH
IL,
I
V
Initial Read Current (Notes 2, 3)
5 MHz
18
35
5
mA
mA
CC1
CC2
CC
V
,
10 MHz
10 MHz
40 MHz
I
V
Intra-Page Read Current (Notes 2, 3) CE# = V OE# = V
CC
IL,
IH
10
50
I
I
I
I
V
V
V
Active Write Current (Note 3)
Standby Current (Note 3)
Reset Current (Note 3)
CE# = V OE# = V
IH
mA
µA
µA
µA
CC3
CC4
CC5
CC6
CC
CC
CC
IL,
CE#, RESET# = V ± 0.3 V,
CC
1
1
1
5
5
WP# = V
IH
RESET# = V ± 0.3 V, WP# = V
SS
IH
V
= V ± 0.3 V;
CC
IH
Automatic Sleep Mode (Notes 3, 5)
5
-0.1< V ≤ 0.3 V, WP# = V
IL
IH
V
Input Low Voltage 1 (Note 6)
Input High Voltage 1 (Note 6)
–0.5
0.8
V
V
IL
V
0.7 V
V
+ 0.5
IH
CC
CC
Voltage for ACC Program
Acceleration
V
V
V
= 2.7 –3.6 V
= 2.7 –3.6 V
11.5
11.5
12.0
12.0
12.5
V
V
HH
CC
CC
Voltage for Autoselect and Temporary
Sector Unprotect
V
12.5
0.45
ID
V
Output Low Voltage (Note 6)
Output High Voltage
I
I
I
= 4.0 mA, V = V
CC min
V
V
V
V
OL
OL
OH
OH
CC
V
= –2.0 mA, V = V
0.85 V
CC
OH1
OH2
CC
CC min
CC min
V
= –100 µA, V = V
V
–0.4
CC
CC
V
Low V Lock-Out Voltage (Note 7)
2.3
2.5
LKO
CC
Notes:
1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA.
2. The ICC current listed is typically less than 3.5 mA/MHz, with OE# at VIH
.
3. Maximum ICC specifications are tested with VCC = VCCmax.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
6. VCC voltage requirements.
7. Not 100% tested.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
65
A d v a n c e I n f o r m a t i o n
Test Conditions
Table 28. Test Specifications
3.3 V
Test Condition
Output Load
All Speeds
1 TTL gate
Unit
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 k
Ω
0.0 or VCC
Input timing measurement
reference levels (See Note)
0.5 VCC
0.5 VCC
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent.
Figure 11. Test Setup
Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
V
CC
0.5 V
Input
0.5 V
Measurement Level
Output
CC
CC
0.0 V
Figure 12. Input Waveforms and Measurement Levels
66
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
AC Characteristics
Read-Only Operations-S29GL064A only
Parameter
Speed Options
JEDEC
Std.
Description
Test Setup
90
10
100
100
100
30
11
110
110
110
30
Unit
ns
t
t
Read Cycle Time (Note 1)
Address to Output Delay
Min
Max
Max
Max
Max
Max
Max
90
90
90
25
25
AVAV
RC
t
t
CE#, OE# = V
IL
ns
AVQV
ACC
t
t
OE# = V
IL
Chip Enable to Output Delay
Page Access Time
ns
ELQV
CE
t
ns
PACC
t
t
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
30
ns
GLQV
OE
t
t
16
ns
EHQZ
DF
t
t
16
0
ns
GHQZ
DF
Output Hold Time From Addresses, CE# or OE#, Whichever Occurs
First
t
t
Min
Min
Min
ns
ns
ns
AXQX
OH
Read
0
Output Enable Hold Time
t
OEH
Toggle and
(Note 1)
10
Data# Polling
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 28 for test specifications.
Read-Only Operations-S29GL032A only
Parameter
Speed Options
JEDEC
Std.
Description
Test Setup
90
10
100
100
100
30
11
Unit
ns
t
t
Read Cycle Time (Note 1)
Address to Output Delay
Chip Enable to Output Delay
Page Access Time
Min
Max
Max
Max
Max
Max
Max
90
90
90
25
25
110
110
110
30
AVAV
RC
t
t
CE#, OE# = V
IL
ns
AVQV
ACC
t
t
OE# = V
IL
ns
ELQV
CE
t
ns
PACC
t
t
Output Enable to Output Delay
30
30
ns
GLQV
OE
t
t
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
16
ns
EHQZ
DF
t
t
16
ns
GHQZ
DF
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
t
t
Min
Min
Min
0
0
ns
ns
ns
AXQX
OH
Read
t
Output Enable Hold Time (Note 1)
OEH
Toggle and
Data# Polling
10
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 28 for test specifications.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
67
A d v a n c e I n f o r m a t i o n
tRC
Addresses Stable
tACC
Addresses
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operation Timings
Same Page
A23-A2
A1-A0*
Ad
Aa
Ab
Ac
tPACC
tPACC
tPACC
tACC
Data Bus
Qa
Qb
Qc
Qd
CE#
OE#
Note: * Figure shows device in word mode. Addresses are A1–A-1 for byte mode
.
Figure 14. Page Read Timings
68
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Hardware Reset (RESET#)
Parameter
JEDEC Std.
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Input Low to Standby Mode (See Note)
RY/BY# Output High to CE#, OE# pin Low
Note:Not 100% tested
.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRH
tRP
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
Figure 15. Reset Timings
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
69
A d v a n c e I n f o r m a t i o n
Erase and Program Operations-S29GL064A Only
Parameter
JEDEC
Speed Options
Std.
Description
90
10
11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
90
100
110
AVAV
WC
t
t
0
15
45
0
AVWL
AS
t
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
ASO
t
t
WLAX
DVWH
AH
t
Address Hold Time From CE# or OE# high during toggle bit polling
Data Setup Time
AHT
t
t
t
35
0
DS
t
Data Hold Time
WHDX
DH
t
t
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
20
20
0
CEPH
OEPH
GHWL
t
t
GHWL
t
t
0
ELWL
WHEH
WLWH
CS
t
t
t
CE# Hold Time
0
CH
t
Write Pulse Width
35
WP
t
t
Write Pulse Width High
Min
Typ
Typ
Typ
Typ
30
240
60
WHDL
WPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
t
t
t
t
µs
WHWH1
WHWH1
54
0.5
sec
ns
µs
ns
µs
WHWH2
WHWH2
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
Min
Min
Min
Max
250
50
VHH
HH
CC
t
VCS
t
WE# High to RY/BY# Low
90
100
4
110
BUSY
t
Program Valid before Status Polling
POLL
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once
programming has resumed (that is, the program resume command has been written). If the suspend command was issued
after tPOLL, status data is available immediately after programming has resumed. See Figure 16.
70
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Erase and Program Operations-S29GL032A Only
Parameter
Speed Options
JEDEC
Std.
Description
90
10
100
0
11
110
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
90
AVAV
WC
t
t
AVWL
AS
t
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
45
0
ASO
t
t
WLAX
AH
t
Address Hold Time From CE# or OE# high during toggle bit polling
Data Setup Time
AHT
t
t
35
0
DVWH
DS
t
t
Data Hold Time
WHDX
DH
t
t
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
20
20
0
CEPH
OEPH
GHWL
t
t
GHWL
t
t
0
ELWL
CS
t
t
CE# Hold Time
0
WHEH
CH
t
t
Write Pulse Width
35
WLWH
WP
t
t
Write Pulse Width High
Min
Typ
Typ
Typ
Typ
30
240
60
WHDL
WPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
t
t
t
µs
WHWH1
WHWH1
54
t
0.5
sec
ns
µs
ns
µs
WHWH2
WHWH2
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
Min
Min
Min
Max
250
50
VHH
HH
CC
t
VCS
t
WE# High to RY/BY# Low
90
100
4
110
BUSY
t
Program Valid before Status Polling
POLL
Notes:
1. Not 100% tested.
2. See “Erase And Programming Performance” for more information
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once
programming resumes (that is, the program resume command has been written). If the suspend command was issued after
tPOLL, status data is available immediately after programming resumes. See Figure 16.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
71
A d v a n c e I n f o r m a t i o n
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tPOLL
tWP
WE#
Data
tWPH
tCS
tWHWH1
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode.
Figure 16. Program Operation Timings
V
HH
V
or V
IL IH
V
or V
IL IH
ACC
t
t
VHH
VHH
Figure 17. Accelerated Program Timing Diagram
72
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.)
2. Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
tPOLL
tCH
tOE
OE#
WE#
tDF
tOH
tOEH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
73
A d v a n c e I n f o r m a t i o n
tAHT
tAS
Addresses
CE#
tAHT
tASO
tCEPH
tOEH
WE#
OE#
tOEPH
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6 / DQ2
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
Enter
Erase
Suspend
Enter Erase
Suspend Program
Embedded
Erasing
Erase
Resume
Erase
Erase Suspend
Read
Erase
Erase
WE#
Erase
Erase Suspend
Read
Suspend
Program
Complete
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 21. DQ2 vs. DQ6
74
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
Temporary Sector Unprotect
Parameter
JEDEC
Std
tVIDR
Description
VID Rise and Fall Time (See Note)
All Speed Options
Unit
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Notes:
1. Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 22. Temporary Sector Group Unprotect Timing Diagram
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
75
A d v a n c e I n f o r m a t i o n
VID
VIH
RESET#
SA, A6,
A3, A2,
A1, A0
Valid*
Sector Group Protect or Unprotect
60h 60h
Valid*
Valid*
Status
Verify
40h
Data
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note: For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.
Figure 23. Sector Group Protect and Unprotect Timing Diagram
76
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
AC Characteristics
Alternate CE# Controlled Erase and Program Operations-S29GL064A
Parameter
JEDEC Std.
Speed Options
Unit
Description
Write Cycle Time (Note 1)
90
10
100
0
11
t
t
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Max
90
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVWL
WC
t
t
Address Setup Time
AS
AH
DS
DH
t
t
Address Hold Time
45
35
0
ELAX
DVEH
EHDX
t
t
t
Data Setup Time
t
Data Hold Time
t
t
t
Read Recovery Time Before Write (OE# High to WE# Low)
WE# Setup Time
0
GHEL
GHEL
t
0
WLEL
WS
t
t
WE# Hold Time
0
EHWH
WH
t
t
CE# Pulse Width
35
25
240
60
54
0.5
50
4
ELEH
EHEL
CP
t
t
CE# Pulse Width High
CPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
Program Valid before Status Polling (Note 5)
t
t
t
t
µs
WHWH1
WHWH2
WHWH1
sec
ns
WHWH2
t
RH
t
µs
POLL
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once
programming has resumed (that is, the program resume command has been written). If the suspend command was issued
after tPOLL, status data is available immediately after programming has resumed. See Figure 24.
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
77
A d v a n c e I n f o r m a t i o n
Alternate CE# Controlled Erase and Program Operations-S29GL032A
Parameter
JEDEC
Speed Options
Std.
Description
90
10
100
0
11
Unit
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
90
110
AVAV
WC
t
t
ns
AVWL
AS
t
t
45
ns
ELAX
AH
t
t
t
35
0
ns
DVEH
DS
t
Data Hold Time
ns
EHDX
DH
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
GHEL
Min
0
ns
GHEL
WLEL
t
t
WE# Setup Time
WE# Hold Time
Min
Min
Min
0
0
ns
ns
ns
ns
WS
t
t
EHWH
WH
t
t
CE# Pulse Width
CE# Pulse Width High
35
ELEH
EHEL
CP
t
t
CPH
Min
Typ
Typ
Typ
Typ
25
240
60
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
t
t
t
t
µs
WHWH1
WHWH1
WHWH2
54
0.5
sec
ns
WHWH2
t
RESET# High Time Before Write
Min
50
4
RH
t
Program Valid before Status Polling (Note 4)
Max
µs
POLL
Notes:
1. Not 100% tested.
2. See “Erase And Programming Performance” for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once
programming resumes (that is, the program resume command has been written). If the suspend command was issued after
tPOLL, status data is available immediately after programming resumes. See Figure 24.
78
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
PBA for program
2AA for erase
SA for program buffer to flash
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tPOLL
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
PBD for program 29 for program buffer to flash
55 for erase
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D
4. Illustration shows device in word mode.
is the data written to the device.
OUT
Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
79
A d v a n c e I n f o r m a t i o n
Erase And Programming Performance
Max
Parameter
Typ (Note 1)
(Note 2)
Unit
Comments
Sector Erase Time
0.5
32
3.5
64
Excludes 00h
programming
prior to erasure
(Note 6)
S29GL032A
S29GL064A
sec
Chip Erase Time
64
128
Total Write Buffer Program Time (Notes 3, 5)
240
µs
µs
Total Accelerated Effective Write Buffer Program Time
(Notes 4, 5)
Excludes system
level overhead
(Note 7)
200
S29GL032A
S29GL064A
31.5
63
Chip Program Time
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, V = 3.0V, 10,000 cycles; checkerboard
CC
data pattern.
2. Under worst case conditions of 90°C; Worst case V , 100,000 cycles.
CC
3. Effective programming time (typ) is 15 µs (per word), 7.5 µs (per byte).
4. Effective accelerated programming time (typ) is 12.5 µs (per word), 6.3 µs (per byte).
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer
operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program command. See
Tables 25 and 26 for further information on command definitions.
80
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
TSOP Pin and BGA Package Capacitance
Parameter Symbol
Parameter Description
Test Setup
Typ
6
Max
7.5
5.0
12
Unit
pF
TSOP
BGA
CIN
Input Capacitance
VIN = 0
4.2
8.5
5.4
7.5
3.9
pF
TSOP
BGA
pF
COUT
Output Capacitance
VOUT = 0
VIN = 0
6.5
9
pF
TSOP
BGA
pF
CIN2
Control Pin Capacitance
4.7
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
81
A d v a n c e I n f o r m a t i o n
Physical Dimensions
TS048—48-Pin Standard Thin Small Outline Package (TSOP)
STANDARD PIN OUT (TOP VIEW)
A2
2
0.10 C
1
N
SEE DETAIL B
-A-
-B-
5
E
e
9
N
2
N
2
+1
5
A1
D1
4
C
D
SEATING
PLANE
B
A
0.08MM (0.0031")
M
C
A-B
6
S
B
b
7
SEE DETAIL A
WITH PLATING
c1
(c)
7
b1
BASE METAL
R
SECTION B-B
e/2
c
GAGE LINE
0.25MM (0.0098") BSC
0˚
-X-
X = A OR B
PARALLEL TO
SEATING PLANE
L
DETAIL A
DETAIL B
NOTES:
Package
TS 048
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
MO-142 (B) EC
Jedec
1
2
3
4
MIN
NOM MAX
1.20
Symbol
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
NOT APPLICABLE.
A
A1
A2
b1
b
c1
c
D
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
1.05
0.23
0.27
0.16
0.21
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
0.22
5
6
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15MM (.0059") PER SIDE.
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
D1
E
e
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.60
3˚
0.70
5˚
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
0.20
48
3325 \ 16-038 10a
82
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
TS056—56-Pin Standard Thin Small Outline Package (TSOP)
2X
0.10
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
2X
0.10
2
0.10
A2
1
N
REVERSE PIN OUT (TOP VIEW)
3
SEE DETAIL B
A
B
1
N
5
E
N
2
N
2
+1
e
9
5
D1
A1
N
+1
N
2
4
2
D
0.25
2X (N/2 TIPS)
C
B
SEATING
PLANE
A
B
SEE DETAIL A
0.08MM (0.0031")
M
C
A - B S
b
6
7
WITH PLATING
c1
(c)
7
b1
BASE METAL
SECTION B-B
R
(c)
e/2
GAUGE PLANE
0.25MM (0.0098") BSC
θ°
PARALLEL TO
SEATING PLANE
X
C
L
X = A OR B
DETAIL A
DETAIL B
NOTES:
Package
Jedec
TS 056
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
MO-142 (D) EC
1
2
3
4
MIN
NOM MAX
1.20
Symbol
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
A
A1
A2
b1
b
c1
c
D
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
1.05
0.23
0.27
0.16
0.21
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
0.22
5
6
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
19.80 20.00 20.20
18.30 18.40 18.50
13.90 14.00 14.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
D1
E
e
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.08
0.60
0.70
8˚
0.20
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
56
3356 \ 16-038.10c
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
83
A d v a n c e I n f o r m a t i o n
LAA064—64-Ball Fortified Ball Grid Array (BGA)
84
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
A d v a n c e I n f o r m a t i o n
VBN048—48-Ball Fine-pitch Ball Grid Array (BGA) 10x 6 mm Package
D1
A
D
e
6
5
4
3
2
1
e
7
SE
E1
E
Ø0.50
H
G
F
E
D
C
B
A
B
A1 CORNER
+0.20
-0.50
7
6
SD
1.00
A1 ID.
Øb
Ø0.08
Ø0.15
M
C
M
C A B
0.10
0.08
C
A2
A
SEATING PLANE
C
C
A1
NOTES:
PACKAGE
JEDEC
VBN 048
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
10.00 mm x 6.00 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
---
NOM
MAX
1.00
---
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
---
---
OVERALL THICKNESS
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.17
0.62
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
---
0.73
BODY THICKNESS
BODY SIZE
10.00 BSC.
6.00 BSC.
5.60 BSC.
4.00 BSC.
8
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
MD
ME
N
BALL FOOTPRINT
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
6
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
48
φb
0.35
---
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
e
0.80 BSC.
0.40 BSC.
NONE
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3425\ 16-038.25
January 28, 2005 S29GLxxxA_00_A2
S29GLxxxA MirrorBit™ Flash Family
85
A d v a n c e I n f o r m a t i o n
Revision Summary
Revision A (October 13, 2004)
Initial Release.
Revision A1 (December 17, 2004)
Secured Silicon Sector Flash Memory Region
Updated Secured Silicon Sector address table with addresses in x8-mode.
DC Characteristics (CMOS Compatible)
ILIT re-specified over temperature.
Corrected WP#/ACC input load current footnote.
Revision A2 (January 28, 2005)
Global
Added S29GL032A information.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-
tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright © 2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks
of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective
companies.
86
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005
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