S29GL256N11FFIIH2_技术文档

S29GL-N

MirrorBit^™Flash Family with Alternative BGA Layout

S29GL256N, S29GL128N

256 Megabit and 128 Megabit

3.0 Volt-only Page Mode Flash Memory featuring

110 nm MirrorBit™ Process Technology

S29GL-N Cover Sheet

Data Sheet

Notice to Readers: This document states the current technical specifications regarding the Spansion

product(s) described herein. Each product described herein may be designated as Advance Information,

Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.

Publication Number S29GL-N_01

Revision A

Amendment 0

Issue Date May 1, 2006

D a t a S h e e t

Notice On Data Sheet Designations

Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of

product information or intended specifications throughout the product life cycle, including development,

qualification, initial production, and full production. In all cases, however, readers are encouraged to verify

that they have the latest information before finalizing their design. The following descriptions of Spansion data

sheet designations are presented here to highlight their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion Inc. is developing one or more specific

products, but has not committed any design to production. Information presented in a document with this

designation is likely to change, and in some cases, development on the product may discontinue. Spansion

Inc. therefore places the following conditions upon Advance Information content:

“This document contains information on one or more products under development at Spansion Inc.

The information is intended to help you evaluate this product. Do not design in this product without

contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed

product without notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a commitment

to production has taken place. This designation covers several aspects of the product life cycle, including

product qualification, initial production, and the subsequent phases in the manufacturing process that occur

before full production is achieved. Changes to the technical specifications presented in a Preliminary

document should be expected while keeping these aspects of production under consideration. Spansion

places the following conditions upon Preliminary content:

“This document states the current technical specifications regarding the Spansion product(s)

described herein. The Preliminary status of this document indicates that product qualification has been

completed, and that initial production has begun. Due to the phases of the manufacturing process that

require maintaining efficiency and quality, this document may be revised by subsequent versions or

modifications due to changes in technical specifications.”

Combination

Some data sheets contain a combination of products with different designations (Advance Information,

Preliminary, or Full Production). This type of document distinguishes these products and their designations

wherever necessary, typically on the first page, the ordering information page, and pages with the DC

Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first

page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal changes

are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include

those affecting the number of ordering part numbers available, such as the addition or deletion of a speed

option, temperature range, package type, or V_IOrange. Changes may also include those needed to clarify a

description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following

conditions to documents in this category:

“This document states the current technical specifications regarding the Spansion product(s)

described herein. Spansion Inc. deems the products to have been in sufficient production volume such

that subsequent versions of this document are not expected to change. However, typographical or

specification corrections, or modifications to the valid combinations offered may occur.”

Questions regarding these document designations may be directed to your local sales office.

ii

S29GL-N

S29GL-N_01_A0 May 1, 2006

S29GL-N

MirrorBit^™Flash Family with Alternative BGA Layout

S29GL256N, S29GL128N

256 Megabit and 128 Megabit

3.0 Volt-only Page Mode Flash Memory featuring

110 nm MirrorBit™ Process Technology

Data Sheet

Distinctive Characteristics

Note

Devices are available in both x16 only and x8/x16 bus width configurations, which should be considered when reading statements containing “byte” or “word”.

– 16-word/32-byte write buffer reduces overall programming time for

multiple-word updates

Architectural Advantages

Single Power Supply Operation

Low Power Consumption (typical values at 3.0 V, 5 MHz)

– 3 volt read, erase, and program operations

– 25 mA typical active read current;

Enhanced VersatileI/O™ Control

– 50 mA typical erase/program current

– All input levels (address, control, and DQ input levels) and outputs

– 1 µA typical standby mode current

are determined by voltage on V input. V range is 1.65 to V

CC

IO

Package options

Manufactured on 110 nm MirrorBit process technology

Secured Silicon Sector Region

– 64-ball Fortified BGA (10 x13 mm)

– 128-word/256-byte sector for permanent, secure identification

through an 8-word/16-byte random Electronic Serial Number,

accessible through a command sequence

Software & Hardware Features

Software Features

– Program Suspend and Resume: read other sectors before

programming operation is completed

– Erase Suspend and Resume: read/program other sectors before an

erase operation is completed

– Data# polling and toggle bits provide status

– Unlock Bypass Program command reduces overall multiple-word

programming time

– CFI (Common Flash Interface) compliant: allows host system to

identify and accommodate multiple flash devices

– May be programmed and locked at the factory or by the customer

Flexible Sector Architecture

– S29GL256N: Two hundred fifty-six 64 Kword (128 Kbyte) sectors

– S29GL128N: One hundred twenty-eight 64 Kword (128 Kbyte)

sectors

Compatibility with JEDEC Standards

– Provides pinout and software compatibility for single-power supply

flash, and superior inadvertent write protection

100,000 Erase Cycles per Sector Typical

20-year Data Retention typical

Hardware Features

– Advanced Sector Protection

– WP#/ACC input accelerates programming time (when high voltage

is applied) for greater throughput during system production.

Protects first or last sector regardless of sector protection settings

– Hardware reset input (RESET#) resets device

– Ready/Busy# output (RY/BY#) detects program or erase cycle

completion

Performance Characteristics

High Performance

– 110 ns access time

– 8-word/16-byte page read buffer

– 25 ns page read times

Publication Number S29GL-N_01

Revision A

Amendment 0

Issue Date May 1, 2006

D a t a S h e e t

Table of Contents

Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.

2.

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1

S29GL256N, S29GL128N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.

4.

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1

Special Package Handling Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.

6.

7.

8.

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

VersatileIO^TM(V_IO) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Requirements for Reading Array Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

RESET#: Hardware Reset Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.10 Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.11 Advanced Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.12 Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.13 Persistent Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.14 Persistent Protection Mode Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.15 Password Sector Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.16 Password and Password Protection Mode Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.17 64-bit Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.18 Persistent Protection Bit Lock (PPB Lock Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.19 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.20 Write Protect (WP#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.21 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9.

Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10. Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.1 Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.2 Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.3 Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

10.4 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence . . . . . . . . . 35

10.5 Word Program Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

10.6 Program Suspend/Program Resume Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 39

10.7 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

10.8 Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10.9 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10.10 Lock Register Command Set Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10.11 Password Protection Command Set Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

10.12 Non-Volatile Sector Protection Command Set Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.13 Global Volatile Sector Protection Freeze Command Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.14 Volatile Sector Protection Command Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.15 Secured Silicon Sector Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2

S29GL-N

S29GL-N_01_A0 May 1, 2006

D a t a S h e e t

10.16 Secured Silicon Sector Exit Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11. Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

12. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

12.1 DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

12.2 RY/BY#: Ready/Busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.3 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

12.4 DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.5 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.6 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.7 DQ3: Sector Erase Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

12.8 DQ1: Write-to-Buffer Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

13. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

14. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

15. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

15.1 CMOS Compatible. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

16. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

17. Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

18. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

18.1 Read-Only Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

18.2 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

18.3 Erase and Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

18.4 Alternate CE# Controlled Erase and Program Operations—S29GL128N, S29GL256N . . . . 66

19. Erase And Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

20. BGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

21. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

21.1 FAA064—64-Ball Fortified Ball Grid Array (FBGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

22. Advance Information on S29GL-P Hardware Reset (RESET#) and Power-up Sequence. . . . . . . 70

23. Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

23.1 Revision A (May 1, 2006). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

List of Tables

Table 8.1

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Sector Address Table–S29GL256N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Sector Address Table–S29GL128N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Autoselect Codes (High Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Memory Array Commands (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Sector Protection Commands (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Memory Array Commands (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Sector Protection Commands (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Power-Up Sequence Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 8.2

Table 8.3

Table 8.4

Table 8.5

Table 8.6

Table 9.1

Table 9.2

Table 9.3

Table 9.4

Table 11.1

Table 11.2

Table 11.3

Table 11.4

Table 12.1

Table 16.1

Table 22.1

Table 22.2

May 1, 2006 S29GL-N_01_A0

S29GL-N

3

D a t a S h e e t

List of Figures

Figure 6.1

Figure 6.2

S29GL256N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

S29GL128N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 10.1 Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 10.2 Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 10.3 Program Suspend/Program Resume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 10.4 Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 12.1 Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 12.2 Toggle Bit Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 13.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 13.2 Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 16.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 17.1 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 18.1 Read Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 18.2 Page Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 18.3 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 18.4 Program Operation Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 18.5 Accelerated Program Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 18.6 Chip/Sector Erase Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 18.7 Data# Polling Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 18.8 Toggle Bit Timings (During Embedded Algorithms). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 18.9 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 18.10 Alternate CE# Controlled Write (Erase/Program) Operation Timings . . . . . . . . . . . . . . . . . . 67

Figure 22.1 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 22.2 Power-On Reset Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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1. General Description

The S29GL256/128N family of devices are 3.0V single power flash memory manufactured using 110 nm

MirrorBit technology. The S29GL256N is a 256 Mbit device, organized as 16,777,216 words or 33,554,432

bytes (x8/x16 option only). The S29GL128N is a 128 Mbit device, organized as 8,388,608 words or

16,777,216 bytes (x8/x16 option only). The devices have a 16-bit wide data bus that can also function as an

8-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system or in

standard EPROM programmers.

Access times as fast as 110 ns are available. Note that each access time has a specific operating voltage

range (V_CC) and an I/O voltage range (V_IO), as specified in the Product Selector Guide on page 6 and the

Ordering Information on page 10. The devices are offered in a 64-ball Fortified BGA package. Each device

has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a

V_CCinput, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times

through increased current. This feature is intended to facilitate factory throughput during system production,

but may also be used in the field if desired.

The devices are entirely command set compatible with the JEDEC single-power-supply Flash standard.

Commands are written to the device using standard microprocessor write timing. Write cycles also internally

latch addresses and data needed for the programming and erase operations.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully erased when shipped from the factory.

Device programming and erasure are initiated through command sequences. Once a program or erase

operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or

monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate

programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write

cycles to program data instead of four.

The Enhanced VersatileI/O™ (V_IO) control allows the host system to set the voltage levels that the device

generates and tolerates on all input levels (address, chip control, and DQ input levels) to the same voltage

level that is asserted on the V_IOpin. This allows the device to operate in a 1.8 V or 3 V system environment as

required.

Hardware data protection measures include a low V_CCdetector that automatically inhibits write operations

during power transitions. Persistent Sector Protection provides in-system, command-enabled protection of

any combination of sectors using a single power supply at V_CC. Password Sector Protection prevents

unauthorized write and erase operations in any combination of sectors through a user-defined 64-bit

password.

The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given

sector to read or program any other sector and then complete the erase operation. The Program Suspend/

Program Resume feature enables the host system to pause a program operation in a given sector to read

any other sector and then complete the program operation.

The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then

ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would

thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.

The device reduces power consumption in the standby mode when it detects specific voltage levels on CE#

and RESET#, or when addresses have been stable for a specified period of time.

The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently

protected. Once this sector is protected, no further changes within the sector can occur.

The Write Protect (WP#/ACC) feature protects the first or last sector by asserting a logic low on the WP# pin.

MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector

simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.

May 1, 2006 S29GL-N_01_A0

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2. Product Selector Guide

2.1

S29GL256N, S29GL128N

Part Number

S29GL256N, S29GL128N

V

= 2.7–3.6 V

11

IO

V

= 2.7–3.6 V

CC

Speed Option

= 1.65–1.95 V

11

V

= Regulated (3.0–3.6 V)

Max. Access Time (ns)

110

25

110

30

Max. CE# Access Time (ns)

Max. Page access time (ns)

Max. OE# Access Time (ns)

35

3. Block Diagram

DQ15–DQ0 (A-1)

RY/BY#

V_CC

Sector Switches

V_SS

V_IO

Erase Voltage

Generator

Input/Output

Buffers

RESET#

WE#

State

WP#/ACC

Control

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

X-Decoder

A_Max–A0

(Note 1)

Note

1.

A

GL256N = A23, A

GL128N = A22

Max

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S29GL-N_01_A0 May 1, 2006

D a t a S h e e t

4. Connection Diagrams

64-ball Fortified BGA (model number VH only)

Top View, Balls Facing Down

A8

B8

C8

D8

E8

F8

G8

H8

A23*

A21

RFU

A20

A16

RY/BY#

OE#

WE#

A7

B7

C7

D7

E7

F7

G7

H7

DQ7

A17

A18

A19

A15 DQ15/A-1* RFU

DQ14

A6

B6

C6

D6

E6

F6

G6

H6

V_CC

RFU

DQ6

V_SS

A5

B5

C5

D5

E5

F5

G5

H5

DQ5

A12

A13

A14

RFU

DQ4

DQ12

DQ13

A4

B4

C4

D4

E4

F4

G4

H4

WP#/ACC CE#

A11

RESET#

DQ3

DQ11

V_IO

V_SS

A3

A7

B3

A8

C3

A9

D3

E3

F3

G3

H3

A10

DQ9

DQ10

DQ2

V_CC

A2

A5

B2

C2

A6

D2

A4

E2

F2

G2

H2

RFU

V_SS

DQ1

DQ0

A-1

A1

A0

B1

A1

C1

A2

D1

A3

E1

F1

G1

H1

RFU

DQ8

BYTE#

A22

Note

* Ball H8 is NC on S29GL128. Ball E7 is A-1 in byte mode on model number VH.

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64-ball Fortified BGA (model number IH only)

Top View, Balls Facing Down

A8

B8

C8

D8

E8

F8

G8

H8

A23*

A21

RFU

A20

A16

RY/BY#

OE#

WE#

A7

B7

C7

D7

E7

F7

G7

H7

DQ7

A17

A18

A19

A15

DQ15

RFU

DQ14

A6

B6

C6

D6

E6

F6

G6

H6

V_CC

RFU

DQ6

V_SS

A5

B5

C5

D5

E5

F5

G5

H5

DQ5

A12

A13

A14

RFU

DQ4

DQ12

DQ13

A4

B4

C4

D4

E4

F4

G4

H4

WP#/ACC CE#

A11

RESET#

DQ3

DQ11

V_CC

V_SS

A3

A7

B3

A8

C3

A9

D3

E3

F3

G3

H3

A10

DQ9

DQ10

DQ2

V_CC

A2

A5

B2

C2

A6

D2

A4

E2

F2

G2

H2

RFU

V_SS

DQ1

DQ0

RFU

A1

A0

B1

A1

C1

A2

D1

A3

E1

F1

G1

H1

RFU

DQ8

RFU

A22

Note

* Ball H8 is NC on S29GL128N.

4.1

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages (TSOP, BGA). The package

and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for

prolonged periods of time.

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5. Pin Description

A23–A0

A22–A0

DQ14–DQ0

DQ15/A-1

CE#

24 Address inputs (256 Mb)

23 Address inputs (128 Mb)

15 Data inputs/outputs

DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode)

Chip Enable input

OE#

Output Enable input

WE#

Write Enable input

WP#/ACC

RESET#

BYTE#

Hardware Write Protect input; Acceleration input

Hardware Reset Pin input

Selects 8-bit or 16-bit mode

Ready/Busy output

RY/BY#

3.0 volt-only single power supply

(see Product Selector Guide on page 6 for speed options and voltage supply tolerances)

V_CC

V_IO

V_SS

NC

Output Buffer power

Device Ground

Pin Not Connected Internally

6. Logic Symbol

Figure 6.1 S29GL256N

Figure 6.2 S29GL128N

24

23

A23–A0

16 or 8

A22–A0

16 or 8

DQ15–DQ0

(A-1)

DQ15–DQ0

CE#

(A-1)

OE#

WE#

WP#/ACC

RESET#

V_IO

WP#/ACC

RESET#

V_IO

RY/BY#

BYTE#

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7. Ordering Information

The ordering part number is formed by a valid combination of the following:

S29GL256N

11

F

I

IH

0

Packing Type

0

2

3

= Tray (standard) (Note 1)

= 7” Tape and Reel

= 13” Tape and Reel

Model Number (V range, protection when WP# =V bus width)

IO

IL,

IH = V = V = 2.7 to 3.6 V,

IO

CC

highest address sector protected, x16 data bus

VH= V = 1.65 to 3.6 V, V = 2.7 to 3.6 V,

IO

CC

highest address sector protected, x8/x16 data bus

Temperature Range

^{= Industrial (–40}°C to +85°C)

Package Materials Set

I

A

= SnPb

F

= Pb-free (Recommended)

Package Type

= Fortified Ball Grid Array, 1.0 mm pitch package (FAA064)

F

Speed Option

11 = 110 ns

Device Number/description

S29GL128N, S29GL256N

3.0 Volt-only, 128 Megabit (16 M x 16-Bit/32 M x 8-Bit) or 256 Megabit (32 M x 16-Bit/64 M x 8-Bit)

Page-Mode Flash Memory, Manufactured on 110 nm MirrorBit^®process technology

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult your local

sales office to confirm availability of specific valid combinations and to check on newly released

combinations.

S29GL-N Valid Combinations

Base Part

Number

Speed (ns)

Package

Temperature

Model Number

Packing Type

S29GL128N,

S29GL256N

11

FA, FF (Note 2)

I

IH, VH

0, 2, 3 (Note 1)

Notes

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading “S29” and packing type designator from ordering part number.

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8. Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the

internal command register. The command register itself does not occupy any addressable memory location.

The register is a latch used to store the commands, along with the address and data information needed to

execute the command. The contents of the register serve as inputs to the internal state machine. The state

machine outputs dictate the function of the device. Table 8.1 lists the device bus operations, the inputs and

control levels they require, and the resulting output. The following subsections describe each of these

operations in further detail.

Table 8.1 Device Bus Operations

DQ8–DQ15

Addresses

(Note 1)

DQ0–

DQ7

BYTE#

= V

Operation

CE#

OE# WE# RESET#

WP#/ACC

X

= V

IH

IL

Read

L

H

L

H

A

D

OUT

IN

OUT

DQ8–DQ14

= High-Z,

DQ15 = A-1

Write (Program/Erase)

Accelerated Program

(Note 2)

(Note 3) (Note 3)

V

HH

V

0.3 V

V

CC

0.3 V

CC

Standby

X

H

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z

X

Legend

L = Logic Low = V

IL

H = Logic High = V

IH

V

= 11.5–12.5 V

ID

= 11.5–12.5V

HH

X = Don’t Care

SA = Sector Address

A

= Address In

= Data In

IN

D

IN

= Data Out

OUT

Notes

1. Addresses are AMax:A0 in word mode; A

:A-1 in byte mode. Sector addresses are A

:A16 in both modes.

Max

2. If WP# = V , the first or last sector group remains protected. If WP# = V , the first or last sector is protected or unprotected as

IL

IH

determined by the method described in “Write Protect (WP#)”. All sectors are unprotected when shipped from the factory (The Secured

Silicon Sector may be factory protected depending on version ordered.)

3.

D

or D

as required by command sequence, data polling, or sector protect algorithm (see Figure 10.2 on page 39, Figure 10.4

OUT

IN

on page 41, and Figure 12.1 on page 51).

8.1

8.2

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the

BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are active and controlled by CE#

and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used

as an input for the LSB (A-1) address function.

VersatileIO^TM(V ) Control

IO

The VersatileIO^TM(V_IO) control allows the host system to set the voltage levels that the device generates and

tolerates on CE# and DQ I/Os to the same voltage level that is asserted on V_IO. See Ordering Information

on page 10 for V_IOoptions on this device.

For example, a V_I/Oof 1.65–3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to

and from other 1.8 or 3 V devices on the same data bus.

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8.3

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output control and gates array data to the output pins. WE# should

remain at V_IH.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory content occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses

on the device address inputs produce valid data on the device data outputs. The device remains enabled for

read access until the command register contents are altered.

See Reading Array Data on page 34 for more information. Refer to Read-Only Operations on page 59 for

timing specifications and to Figure 18.1 on page 59 for the timing diagram. Refer to DC Characteristics

on page 57 for the active current specification on reading array data.

8.3.1

Page Mode Read

The device is capable of fast page mode read and is compatible with the page mode Mask ROM read

operation. This mode provides faster read access speed for random locations within a page. The page size of

the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits A(max)–A3.

Address bits A2–A0 in word mode (A2–A-1 in byte mode) determine the specific word within a page. This is

an asynchronous operation; the microprocessor supplies the specific word location.

The random or initial page access is equal to t_ACCor t_CEand subsequent page read accesses (as long as the

locations specified by the microprocessor falls within that page) is equivalent to t_PACC. When CE# is de-

asserted and reasserted for a subsequent access, the access time is t_ACCor t_CE. Fast page mode accesses

are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses.

8.4

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing

sectors of memory), the system must drive WE# and CE# to V_IL, and OE# to V_IH.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The

“Word Program Command Sequence” section has details on programming data to the device using both

standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Table 8.3 on page 20 and

Table 8.4 on page 23 indicate the address space that each sector occupies.

Refer to DC Characteristics on page 57 table for the active current specification for the write mode.

AC Characteristics on page 59 contains timing specification tables and timing diagrams for write operations.

8.4.1

Write Buffer

Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming

operation. This results in faster effective programming time than the standard programming algorithms. See

Write Buffer on page 12 for more information.

8.4.2

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at

the factory.

If the system asserts V_HHon this pin, the device automatically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce

the time required for program operations. The system would use a two-cycle program command sequence as

required by the Unlock Bypass mode. Removing V_HHfrom the WP#/ACC pin returns the device to normal

operation. Note that the WP#/ACC pin must not be at V_HHfor operations other than accelerated

programming, or device damage may result. WP# has an internal pull-up; when unconnected, WP# is at V_IH.

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8.4.3

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system

can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–

DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 23 and Autoselect

Command Sequence on page 35, for more information.

8.5

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,

independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V_IO0.3 V.

(Note that this is a more restricted voltage range than V_IH.) If CE# and RESET# are held at V_IH, but not within

V_IO0.3 V, the device is in the standby mode, but the standby current is greater. The device requires

standard access time (t_CE) for read access when the device is in either of these standby modes, before it is

ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation

is completed.

Refer to DC Characteristics on page 57 for the standby current specification.

8.6

8.7

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables

this mode when addresses remain stable for t_ACC+ 30 ns. The automatic sleep mode is independent of the

CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are

changed. While in sleep mode, output data is latched and always available to the system. Refer to DC

Characteristics on page 57 for the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the

RESET# pin is driven low for at least a period of t_RP, the device immediately terminates any operation in

progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to reading array data. The operation that was interrupted

should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V_SS0.3 V, the device

draws CMOS standby current (I_CC5). If RESET# is held at V_ILbut not within V_SS0.3 V, the standby current is

greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firmware from the Flash memory.

Refer to AC Characteristics on page 59 for RESET# parameters and to Figure 18.3 on page 61 for the

timing diagram.

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8.8

Output Disable Mode

When the OE# input is at V_IH, output from the device is disabled. The output pins are placed in the high

impedance state.

Table 8.2 Sector Address Table–S29GL256N (Sheet 1 of 6)

8-bit

16-bit

Sector Size

(Kbytes/Kwords)

Address Range

(in hexadecimal)

Address Range

(in hexadecimal)

Sector

SA0

A23–A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

128/64

0000000–001FFFF

0020000–003FFFF

0040000–005FFFF

0060000–007FFFF

0080000–009FFFF

00A0000–00BFFFF

00C0000–00DFFFF

00E0000–00FFFFF

0100000–011FFFF

0120000–013FFFF

0140000–015FFFF

0160000–017FFFF

0180000–019FFFF

01A0000–01BFFFF

01C0000–01DFFFF

01E0000–01FFFFF

0200000–021FFFF

0220000–023FFFF

0240000–025FFFF

0260000–027FFFF

0280000–029FFFF

02A0000–02BFFFF

02C0000–02DFFFF

02E0000–02FFFFF

0300000–031FFFF

0320000–033FFFF

0340000–035FFFF

0360000–037FFFF

0380000–039FFFF

03A0000–03BFFFF

03C0000–03DFFFF

03E0000–03FFFFF

0400000–041FFFF

0420000–043FFFF

0440000–045FFFF

0460000–047FFFF

0480000–049FFFF

04A0000–04BFFFF

04C0000–04DFFFF

04E0000–04FFFFF

0500000–051FFFF

0520000–053FFFF

0540000–055FFFF

0560000–057FFFF

0000000–000FFFF

0010000–001FFFF

0020000–002FFFF

0030000–003FFFF

0040000–004FFFF

0050000–005FFFF

0060000–006FFFF

0070000–007FFFF

0080000–008FFFF

0090000–009FFFF

00A0000–00AFFFF

00B0000–00BFFFF

00C0000–00CFFFF

00D0000–00DFFFF

00E0000–00EFFFF

00F0000–00FFFFF

0100000–010FFFF

0110000–011FFFF

0120000–012FFFF

0130000–013FFFF

0140000–014FFFF

0150000–015FFFF

0160000–016FFFF

0170000–017FFFF

0180000–018FFFF

0190000–019FFFF

01A0000–01AFFFF

01B0000–01BFFFF

01C0000–01CFFFF

01D0000–01DFFFF

01E0000–01EFFFF

01F0000–01FFFFF

0200000–020FFFF

0210000–021FFFF

0220000–022FFFF

0230000–023FFFF

0240000–024FFFF

0250000–025FFFF

0260000–026FFFF

0270000–027FFFF

0280000–028FFFF

0290000–029FFFF

02A0000–02AFFFF

02B0000–02BFFFF

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

14

S29GL-N

S29GL-N_01_A0 May 1, 2006

D a t a S h e e t

Table 8.2 Sector Address Table–S29GL256N (Sheet 2 of 6)

8-bit

16-bit

Sector Size

(Kbytes/Kwords)

Address Range

(in hexadecimal)

Address Range

(in hexadecimal)

Sector

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

A23–A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

128/64

0580000–059FFFF

05A0000–05BFFFF

05C0000–05DFFFF

05E0000–05FFFFF

0600000–061FFFF

0620000–063FFFF

0640000–065FFFF

0660000–067FFFF

0680000–069FFFF

06A0000–06BFFFF

06C0000–06DFFFF

06E0000–06FFFFF

0700000–071FFFF

0720000–073FFFF

0740000–075FFFF

0760000–077FFFF

0780000–079FFFF

07A0000–7BFFFF

07C0000–07DFFFF

07E0000–07FFFFF0

0800000–081FFFF

0820000–083FFFF

0840000–085FFFF

0860000–087FFFF

0880000–089FFFF

08A0000–08BFFFF

08C0000–08DFFFF

08E0000–08FFFFF

0900000–091FFFF

0920000–093FFFF

0940000–095FFFF

0960000–097FFFF

0980000–099FFFF

09A0000–09BFFFF

09C0000–09DFFFF

09E0000–09FFFFF

0A00000–0A1FFFF

0A20000–0A3FFFF

0A40000–045FFFF

0A60000–0A7FFFF

0A80000–0A9FFFF

0AA0000–0ABFFFF

0AC0000–0ADFFFF

0AE0000–AEFFFFF

0B00000–0B1FFFF

0B20000–0B3FFFF

0B40000–0B5FFFF

02C0000–02CFFFF

02D0000–02DFFFF

02E0000–02EFFFF

02F0000–02FFFFF

0300000–030FFFF

0310000–031FFFF

0320000–032FFFF

0330000–033FFFF

0340000–034FFFF

0350000–035FFFF

0360000–036FFFF

0370000–037FFFF

0380000–038FFFF

0390000–039FFFF

03A0000–03AFFFF

03B0000–03BFFFF

03C0000–03CFFFF

03D0000–03DFFFF

03E0000–03EFFFF

03F0000–03FFFFF

0400000–040FFFF

0410000–041FFFF

0420000–042FFFF

0430000–043FFFF

0440000–044FFFF

0450000–045FFFF

0460000–046FFFF

0470000–047FFFF

0480000–048FFFF

0490000–049FFFF

04A0000–04AFFFF

04B0000–04BFFFF

04C0000–04CFFFF

04D0000–04DFFFF

04E0000–04EFFFF

04F0000–04FFFFF

0500000–050FFFF

0510000–051FFFF

0520000–052FFFF

0530000–053FFFF

0540000–054FFFF

0550000–055FFFF

0560000–056FFFF

0570000–057FFFF

0580000–058FFFF

0590000–059FFFF

05A0000–05AFFFF

May 1, 2006 S29GL-N_01_A0

S29GL-N

15

D a t a S h e e t

Table 8.2 Sector Address Table–S29GL256N (Sheet 3 of 6)

8-bit

16-bit

Sector Size

(Kbytes/Kwords)

Address Range

(in hexadecimal)

Address Range

(in hexadecimal)

Sector

SA91

A23–A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

128/64

0B60000–0B7FFFF

0B80000–0B9FFFF

0BA0000–0BBFFFF

0BC0000–0BDFFFF

0BE0000–0BFFFFF

0C00000–0C1FFFF

0C20000–0C3FFFF

0C40000–0C5FFFF

0C60000–0C7FFFF

0C80000–0C9FFFF

0CA0000–0CBFFFF

0CC0000–0CDFFFF

0CE0000–0CFFFFF

0D00000–0D1FFFF

0D20000–0D3FFFF

0D40000–0D5FFFF

0D60000–0D7FFFF

0D80000–0D9FFFF

0DA0000–0DBFFFF

0DC0000–0DDFFFF

0DE0000–0DFFFFF

0E00000–0E1FFFF

0E20000–0E3FFFF

0E40000–0E5FFFF

0E60000–0E7FFFF

0E80000–0E9FFFF

0EA0000–0EBFFFF

0EC0000–0EDFFFF

0EE0000–0EFFFFF

0F00000–0F1FFFF

0F20000–0F3FFFF

0F40000–0F5FFFF

0F60000–0F7FFFF

0F80000–0F9FFFF

0FA0000–0FBFFFF

0FC0000–0FDFFFF

0FE0000–0FFFFFF

1000000–101FFFF

1020000–103FFFF

1040000–105FFFF

1060000–107FFFF

1080000–109FFFF

10A0000–10BFFFF

10C0000–10DFFFF

10E0000–10FFFFF

1100000–111FFFF

1120000–113FFFF

05B0000–05BFFFF

05C0000–05CFFFF

05D0000–05DFFFF

05E0000–05EFFFF

05F0000–05FFFFF

0600000–060FFFF

0610000–061FFFF

0620000–062FFFF

0630000–063FFFF

0640000–064FFFF

0650000–065FFFF

0660000–066FFFF

0670000–067FFFF

0680000–068FFFF

0690000–069FFFF

06A0000–06AFFFF

06B0000–06BFFFF

06C0000–06CFFFF

06D0000–06DFFFF

06E0000–06EFFFF

06F0000–06FFFFF

0700000–070FFFF

0710000–071FFFF

0720000–072FFFF

0730000–073FFFF

0740000–074FFFF

0750000–075FFFF

0760000–076FFFF

0770000–077FFFF

0780000–078FFFF

0790000–079FFFF

07A0000–07AFFFF

07B0000–07BFFFF

07C0000–07CFFFF

07D0000–07DFFFF

07E0000–07EFFFF

07F0000–07FFFFF

0800000–080FFFF

0810000–081FFFF

0820000–082FFFF

0830000–083FFFF

0840000–084FFFF

0850000–085FFFF

0860000–086FFFF

0870000–087FFFF

0880000–088FFFF

0890000–089FFFF

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

16

S29GL-N

S29GL-N_01_A0 May 1, 2006

D a t a S h e e t

Table 8.2 Sector Address Table–S29GL256N (Sheet 4 of 6)

8-bit

16-bit

Sector Size

(Kbytes/Kwords)

Address Range

(in hexadecimal)

Address Range

(in hexadecimal)

Sector

SA138

SA139

SA140

SA141

SA142

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

SA159

SA160

SA161

SA162

SA163

SA164

SA165

SA166

SA167

SA168

SA169

SA170

SA171

SA172

SA173

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

A23–A16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

128/64

1140000–115FFFF

1160000–117FFFF

1180000–119FFFF

11A0000–11BFFFF

11C0000–11DFFFF

11E0000–11FFFFF

1200000–121FFFF

1220000–123FFFF

1240000–125FFFF

1260000–127FFFF

1280000–129FFFF

12A0000–12BFFFF

12C0000–12DFFFF

12E0000–12FFFFF

1300000–131FFFF

1320000–133FFFF

1340000–135FFFF

1360000–137FFFF

1380000–139FFFF

13A0000–13BFFFF

13C0000–13DFFFF

13E0000–13FFFFF

1400000–141FFFF

1420000–143FFFF

1440000–145FFFF

1460000–147FFFF

1480000–149FFFF

14A0000–14BFFFF

14C0000–14DFFFF

14E0000–14FFFFF

1500000–151FFFF

1520000–153FFFF

1540000–155FFFF

1560000–157FFFF

1580000–159FFFF

15A0000–15BFFFF

15C0000–15DFFFF

15E0000–15FFFFF

1600000–161FFFF

1620000–163FFFF

1640000–165FFFFF

1660000–167FFFF

1680000–169FFFF

16A0000–16BFFFF

16C0000–16DFFFF

16E0000–16FFFFF

1700000–171FFFF

08A0000–08AFFFF

08B0000–08BFFFF

08C0000–08CFFFF

08D0000–08DFFFF

08E0000–08EFFFF

08F0000–08FFFFF

0900000–090FFFF

0910000–091FFFF

0920000–092FFFF

0930000–093FFFF

0940000–094FFFF

0950000–095FFFF

0960000–096FFFF

0970000–097FFFF

0980000–098FFFF

0990000–099FFFF

09A0000–09AFFFF

09B0000–09BFFFF

09C0000–09CFFFF

09D0000–09DFFFF

09E0000–09EFFFF

09F0000–09FFFFF

0A00000–0A0FFFF

0A10000–0A1FFFF

0A20000–0A2FFFF

0A30000–0A3FFFF

0A40000–0A4FFFF

0A50000–0A5FFFF

0A60000–0A6FFFF

0A70000–0A7FFFF

0A80000–0A8FFFF

0A90000–0A9FFFF

0AA0000–0AAFFFF

0AB0000–0ABFFFF

0AC0000–0ACFFFF

0AD0000–0ADFFFF

0AE0000–0AEFFFF

0AF0000–0AFFFFF

0B00000–0B0FFFF

0B10000–0B1FFFF

0B20000–0B2FFFF

0B30000–0B3FFFF

0B40000–0B4FFFF

0B50000–0B5FFFF

0B60000–0B6FFFF

0B70000–0B7FFFF

0B80000–0B8FFFF

May 1, 2006 S29GL-N_01_A0

S29GL-N

17

D a t a S h e e t

Table 8.2 Sector Address Table–S29GL256N (Sheet 5 of 6)

8-bit

16-bit

Sector Size

(Kbytes/Kwords)

Address Range

(in hexadecimal)

Address Range

(in hexadecimal)

Sector

SA185

SA186

SA187

SA188

SA189

SA190

SA191

SA192

SA193

SA194

SA195

SA196

SA197

SA198

SA199

SA200

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

SA224

SA225

SA226

SA227

SA228

SA229

SA230

SA231

A23–A16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

128/64

1720000–173FFFF

1740000–175FFFF

1760000–177FFFF

1780000–179FFFF

17A0000–17BFFFF

17C0000–17DFFFF

17E0000–17FFFFF

1800000–181FFFF

1820000–183FFFF

1840000–185FFFF

1860000–187FFFF

1880000–189FFFF

18A0000–18BFFFF

18C0000–18DFFFF

18E0000–18FFFFF

1900000–191FFFF

1920000–193FFFF

1940000–195FFFF

1960000–197FFFF

1980000–199FFFF

19A0000–19BFFFF

19C0000–19DFFFF

19E0000–19FFFF

1A00000–1A1FFFF

1A20000–1A3FFFF

1A40000–1A5FFFF

1A60000–1A7FFFF

1A80000–1A9FFFF

1AA0000–1ABFFFF

1AC0000–1ADFFFF

1AE0000–1AFFFFF

1B00000–1B1FFFF

1B20000–1B3FFFF

1B40000–1B5FFFF

1B60000–1B7FFFF

1B80000–1B9FFFF

1BA0000–1BBFFFF

1BC0000–1BDFFFF

1BE0000–1BFFFFF

1C00000–1C1FFFF

1C20000–1C3FFFF

1C40000–1C5FFFF

1C60000–1C7FFFF

1C80000–1C9FFFF

1CA0000–1CBFFFF

1CC0000–1CDFFFF

1CE0000–1CFFFFF

0B90000–0B9FFFF

0BA0000–0BAFFFF

0BB0000–0BBFFFF

0BC0000–0BCFFFF

0BD0000–0BDFFFF

0BE0000–0BEFFFF

0BF0000–0BFFFFF

0C00000–0C0FFFF

0C10000–0C1FFFF

0C20000–0C2FFFF

0C30000–0C3FFFF

0C40000–0C4FFFF

0C50000–0C5FFFF

0C60000–0C6FFFF

0C70000–0C7FFFF

0C80000–0C8FFFF

0C90000–0C9FFFF

0CA0000–0CAFFFF

0CB0000–0CBFFFF

0CC0000–0CCFFFF

0CD0000–0CDFFFF

0CE0000–0CEFFFF

0CF0000–0CFFFFF

0D00000–0D0FFFF

0D10000–0D1FFFF

0D20000–0D2FFFF

0D30000–0D3FFFF

0D40000–0D4FFFF

0D50000–0D5FFFF

0D60000–0D6FFFF

0D70000–0D7FFFF

0D80000–0D8FFFF

0D90000–0D9FFFF

0DA0000–0DAFFFF

0DB0000–0DBFFFF

0DC0000–0DCFFFF

0DD0000–0DDFFFF

0DE0000–0DEFFFF

0DF0000–0DFFFFF

0E00000–0E0FFFF

0E10000–0E1FFFF

0E20000–0E2FFFF

0E30000–0E3FFFF

0E40000–0E4FFFF

0E50000–0E5FFFF

0E60000–0E6FFFF

0E70000–0E7FFFF

18

S29GL-N

S29GL-N_01_A0 May 1, 2006

D a t a S h e e t

Table 8.2 Sector Address Table–S29GL256N (Sheet 6 of 6)

8-bit

16-bit

Sector Size

(Kbytes/Kwords)

Address Range

(in hexadecimal)

Address Range

(in hexadecimal)

Sector

SA232

SA233

SA234

SA235

SA236

SA237

SA238

SA239

SA240

SA241

SA242

SA243

SA244

SA245

SA246

SA247

SA248

SA249

SA250

SA251

SA252

SA253

SA254

SA255

A23–A16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

128/64

1D00000–1D1FFFF

1D20000–1D3FFFF

1D40000–1D5FFFF

1D60000–1D7FFFF

1D80000–1D9FFFF

1DA0000–1DBFFFF

1DC0000–1DDFFFF

1DE0000–1DFFFFF

1E00000–1E1FFFF

1E20000–1E3FFFF

1E40000–1E5FFFF

1E60000–137FFFF

1E80000–1E9FFFF

1EA0000–1EBFFFF

1EC0000–1EDFFFF

1EE0000–1EFFFFF

1F00000–1F1FFFF

1F20000–1F3FFFF

1F40000–1F5FFFF

1F60000–1F7FFFF

1F80000–1F9FFFF

1FA0000–1FBFFFF

1FC0000–1FDFFFF

1FE0000–1FFFFFF

0E80000–0E8FFFF

0E90000–0E9FFFF

0EA0000–0EAFFFF

0EB0000–0EBFFFF

0EC0000–0ECFFFF

0ED0000–0EDFFFF

0EE0000–0EEFFFF

0EF0000–0EFFFFF

0F00000–0F0FFFF

0F10000–0F1FFFF

0F20000–0F2FFFF

0F30000–0F3FFFF

0F40000–0F4FFFF

0F50000–0F5FFFF

0F60000–0F6FFFF

0F70000–0F7FFFF

0F80000–0F8FFFF

0F90000–0F9FFFF

0FA0000–0FAFFFF

0FB0000–0FBFFFF

0FC0000–0FCFFFF

0FD0000–0FDFFFF

0FE0000–0FEFFFF

0FF0000–0FFFFFF

May 1, 2006 S29GL-N_01_A0

S29GL-N

19

D a t a S h e e t

Table 8.3 Sector Address Table–S29GL128N (Sheet 1 of 3)

Sector Size

(Kbytes/

Kwords)

8-Bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector

SA0

A22–A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

128/64

0000000–001FFFF

0020000–003FFFF

0040000–005FFFF

0060000–007FFFF

0080000–009FFFF

00A0000–00BFFFF

00C0000–00DFFFF

00E0000–00FFFFF

0100000–011FFFF

0120000–013FFFF

0140000–015FFFF

0160000–017FFFF

0180000–019FFFF

01A0000–01BFFFF

01C0000–01DFFFF

01E0000–01FFFFF

0200000–021FFFF

0220000–023FFFF

0240000–025FFFF

0260000–027FFFF

0280000–029FFFF

02A0000–02BFFFF

02C0000–02DFFFF

02E0000–02FFFFF

0300000–031FFFF

0320000–033FFFF

0340000–035FFFF

0360000–037FFFF

0380000–039FFFF

03A0000–03BFFFF

03C0000–03DFFFF

03E0000–03FFFFF

0400000–041FFFF

0420000–043FFFF

0440000–045FFFF

0460000–047FFFF

0480000–049FFFF

04A0000–04BFFFF

04C0000–04DFFFF

04E0000–04FFFFF

0500000–051FFFF

0520000–053FFFF

0540000–055FFFF

0560000–057FFFF

0580000–059FFFF

05A0000–05BFFFF

0000000–000FFFF

0010000–001FFFF

0020000–002FFFF

0030000–003FFFF

0040000–004FFFF

0050000–005FFFF

0060000–006FFFF

0070000–007FFFF

0080000–008FFFF

0090000–009FFFF

00A0000–00AFFFF

00B0000–00BFFFF

00C0000–00CFFFF

00D0000–00DFFFF

00E0000–00EFFFF

00F0000–00FFFFF

0100000–010FFFF

0110000–011FFFF

0120000–012FFFF

0130000–013FFFF

0140000–014FFFF

0150000–015FFFF

0160000–016FFFF

0170000–017FFFF

0180000–018FFFF

0190000–019FFFF

01A0000–01AFFFF

01B0000–01BFFFF

01C0000–01CFFFF

01D0000–01DFFFF

01E0000–01EFFFF

01F0000–01FFFFF

0200000–020FFFF

0210000–021FFFF

0220000–022FFFF

0230000–023FFFF

0240000–024FFFF

0250000–025FFFF

0260000–026FFFF

0270000–027FFFF

0280000–028FFFF

0290000–029FFFF

02A0000–02AFFFF

02B0000–02BFFFF

02C0000–02CFFFF

02D0000–02DFFFF

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

20

S29GL-N

S29GL-N_01_A0 May 1, 2006

D a t a S h e e t

Table 8.3 Sector Address Table–S29GL128N (Sheet 2 of 3)

Sector Size

(Kbytes/

Kwords)

8-Bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

A22–A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

128/64

05C0000–05DFFFF

05E0000–05FFFFF

0600000–061FFFF

0620000–063FFFF

0640000–065FFFF

0660000–067FFFF

0680000–069FFFF

06A0000–06BFFFF

06C0000–06DFFFF

06E0000–06FFFFF

0700000–071FFFF

0720000–073FFFF

0740000–075FFFF

0760000–077FFFF

0780000–079FFFF

07A0000–07BFFFF

07C0000–07DFFFF

07E0000–07FFFFF

0800000–081FFFF

0820000–083FFFF

0840000–085FFFF

0860000–087FFFF

0880000–089FFFF

08A0000–08BFFFF

08C0000–08DFFFF

08E0000–08FFFFF

0900000–091FFFF

0920000–093FFFF

0940000–095FFFF

0960000–097FFFF

0980000–099FFFF

09A0000–09BFFFF

09C0000–09DFFFF

09E0000–09FFFFF

0A00000–0A1FFFF

0A20000–0A3FFFF

0A40000–0A5FFFF

0A60000–0A7FFFF

0A80000–0A9FFFF

0AA0000–0ABFFFF

0AC0000–0ADFFFF

0AE0000–0AFFFFF

0B00000–0B1FFFF

0B20000–0B3FFFF

0B40000–0B5FFFF

0B60000–0B7FFFF

0B80000–0B9FFFF

02E0000–02EFFFF

02F0000–02FFFFF

0300000–030FFFF

0310000–031FFFF

0320000–032FFFF

0330000–033FFFF

0340000–034FFFF

0350000–035FFFF

0360000–036FFFF

0370000–037FFFF

0380000–038FFFF

0390000–039FFFF

03A0000–03AFFFF

03B0000–03BFFFF

03C0000–03CFFFF

03D0000–03DFFFF

03E0000–03EFFFF

03F0000–03FFFFF

0400000–040FFFF

0410000–041FFFF

0420000–042FFFF

0430000–043FFFF

0440000–044FFFF

0450000–045FFFF

0460000–046FFFF

0470000–047FFFF

0480000–048FFFF

0490000–049FFFF

04A0000–04AFFFF

04B0000–04BFFFF

04C0000–04CFFFF

04D0000–04DFFFF

04E0000–04EFFFF

04F0000–04FFFFF

0500000–050FFFF

0510000–051FFFF

0520000–052FFFF

0530000–053FFFF

0540000–054FFFF

0550000–055FFFF

0560000–056FFFF

0570000–057FFFF

0580000–058FFFF

0590000–059FFFF

05A0000–05AFFFF

05B0000–05BFFFF

05C0000–05CFFFF

May 1, 2006 S29GL-N_01_A0

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21

D a t a S h e e t

Table 8.3 Sector Address Table–S29GL128N (Sheet 3 of 3)

Sector Size

(Kbytes/

Kwords)

8-Bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector

SA93

A22–A16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

128/64

0BA0000–0BBFFFF

0BC0000–0BDFFFF

0BE0000–0BFFFFF

0C00000–0C1FFFF

0C20000–0C3FFFF

0C40000–0C5FFFF

0C60000–0C7FFFF

0C80000–0C9FFFF

0CA0000–0CBFFFF

0CC0000–0CDFFFF

0CE0000–0CFFFFF

0D00000–0D1FFFF

0D20000–0D3FFFF

0D40000–0D5FFFF

0D60000–0D7FFFF

0D80000–0D9FFFF

0DA0000–0DBFFFF

0DC0000–0DDFFFF

0DE0000–0DFFFFF

0E00000–0E1FFFF

0E20000–0E3FFFF

0E40000–0E5FFFF

0E60000–0E7FFFF

0E80000–0E9FFFF

0EA0000–0EBFFFF

0EC0000–0EDFFFF

0EE0000–0EFFFFF

0F00000–0F1FFFF

0F20000–0F3FFFF

0F40000–0F5FFFF

0F60000–0F7FFFF

0F80000–0F9FFFF

0FA0000–0FBFFFF

0FC0000–0FDFFFF

0FE0000–0FFFFFF

05D0000–05DFFFF

05E0000–05EFFFF

05F0000–05FFFFF

0600000–060FFFF

0610000–061FFFF

0620000–062FFFF

0630000–063FFFF

0640000–064FFFF

0650000–065FFFF

0660000–066FFFF

0670000–067FFFF

0680000–068FFFF

0690000–069FFFF

06A0000–06AFFFF

06B0000–06BFFFF

06C0000–06CFFFF

06D0000–06DFFFF

06E0000–06EFFFF

06F0000–06FFFFF

0700000–070FFFF

0710000–071FFFF

0720000–072FFFF

0730000–073FFFF

0740000–074FFFF

0750000–075FFFF

0760000–076FFFF

0770000–077FFFF

0780000–078FFFF

0790000–079FFFF

07A0000–07AFFFF

07B0000–07BFFFF

07C0000–07CFFFF

07D0000–07DFFFF

07E0000–07EFFFF

07F0000–07FFFFF

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

22

S29GL-N

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D a t a S h e e t

8.9

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector group protection

verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming

equipment to automatically match a device to be programmed with its corresponding programming algorithm.

However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6,

A3, A2, A1, and A0 must be as shown in Table 8.4. In addition, when verifying sector protection, the sector

address must appear on the appropriate highest order address bits (see Table 8.2 and Table 8.3). Table 8.4

shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the

programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the

command register, as shown in Table 11.1 on page 46 and Table 11.3 on page 48. This method does not

require V_ID. Refer to Autoselect Command Sequence on page 35 for more information.

Table 8.4 Autoselect Codes (High Voltage Method)

DQ8 to DQ15

A14

to

A22

to

A8

to

A5 A3

to to

BYTE# BYTE#

Description

CE# OE# WE# A15 A10 A9 A7 A6 A4 A2 A1 A0

= V

DQ7 to DQ0

IH

IL

Manufacturer ID:

Spansion Product

L

H

X

V

X

L

X

L

00

X

01h

ID

Cycle 1

Cycle 2

L

H

L

22

X

7Eh

22h

H

L

H

V

L

ID

Cycle 3

H

22

X

01h

Cycle 1

Cycle 2

L

H

L

22

X

7Eh

21h

H

L

H

X

SA

X

V

X

L

X

ID

Cycle 3

H

L

H

L

22

X

01h

Sector Group

Protection Verification

01h (protected),

00h (unprotected)

ID

Secured Silicon

Sector Indicator Bit

(DQ7), WP# protects

highest address

sector

98h (factory

locked),

18h (not factory

locked)

L

H

X

ID

Secured Silicon

88h (factory

locked),

08h (not factory

locked)

Sector Indicator Bit

(DQ7), WP# protects

lowest address sector

L

H

X

V

X

L

X

ID

Legend

L = Logic Low = V

IL

H = Logic High = V

IH

SA = Sector Address

X = Don’t care.

May 1, 2006 S29GL-N_01_A0

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23

D a t a S h e e t

8.10 Sector Protection

The device features several levels of sector protection, which can disable both the program and erase

operations in certain sectors or sector groups:

8.10.1

8.10.2

Persistent Sector Protection

A command sector protection method that replaces the old 12 V controlled protection method.

Password Sector Protection

A highly sophisticated protection method that requires a password before changes to certain sectors or sector

groups are permitted

8.10.3

8.10.4

WP# Hardware Protection

A write protect pin that can prevent program or erase operations in the outermost sectors.

The WP# Hardware Protection feature is always available, independent of the software managed protection

method chosen.

Selecting a Sector Protection Mode

All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the

Persistent or Password Protection method is most desirable. There are two one-time programmable non-

volatile bits that define which sector protection method is used. If the customer decides to continue using the

Persistent Sector Protection method, they must set the Persistent Sector Protection Mode Locking Bit.

This permanently sets the part to operate only using Persistent Sector Protection. If the customer decides to

use the password method, they must set the Password Mode Locking Bit. This permanently sets the part to

operate only using password sector protection.

It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the

Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between

the two methods once a locking bit is set. It is important that one mode is explicitly selected when the

device is first programmed, rather than relying on the default mode alone. This is so that it is not

possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an

unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode.

The device is shipped with all sectors unprotected. The factory offers the option of programming and

protecting sectors at the factory prior to shipping the device through the ExpressFlash™ Service. Contact

your sales representative for details.

It is possible to determine whether a sector is protected or unprotected. See Autoselect Command Sequence

on page 35 for details.

8.11 Advanced Sector Protection

Advanced Sector Protection features several levels of sector protection, which can disable both the program

and erase operations in certain sectors.

Persistent Sector Protection is a method that replaces the old 12V controlled protection method.

Password Sector Protection is a highly sophisticated protection method that requires a password before

changes to certain sectors are permitted.

24

S29GL-N

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D a t a S h e e t

8.12 Lock Register

The Lock Register consists of 3 bits (DQ2, DQ1, and DQ0). These DQ2, DQ1, DQ0 bits of the Lock Register

are programmable by the user. Users are not allowed to program both DQ2 and DQ1 bits of the Lock Register

to the 00 state. If the user tries to program DQ2 and DQ1 bits of the Lock Register to the 00 state, the device

aborts the Lock Register back to the default 11 state. The programming time of the Lock Register is same as

the typical word programming time without utilizing the Write Buffer of the device. During a Lock Register

programming sequence execution, the DQ6 Toggle Bit I toggles until the programming of the Lock Register

has completed to indicate programming status. All Lock Register bits are readable to allow users to verify

Lock Register statuses.

The Customer Secured Silicon Sector Protection Bit is DQ0, Persistent Protection Mode Lock Bit is DQ1, and

Password Protection Mode Lock Bit is DQ2 are accessible by all users. Each of these bits are non-volatile.

DQ15-DQ3 are reserved and must be 1's when the user tries to program the DQ2, DQ1, and DQ0 bits of the

Lock Register. The user is not required to program DQ2, DQ1 and DQ0 bits of the Lock Register at the same

time. This allows users to lock the Secured Silicon Sector and then set the device either permanently into

Password Protection Mode or Persistent Protection Mode and then lock the Secured Silicon Sector at

separate instances and time frames.

Secured Silicon Sector Protection allows the user to lock the Secured Silicon Sector area

Persistent Protection Mode Lock Bit allows the user to set the device permanently to operate in the

Persistent Protection Mode

Password Protection Mode Lock Bit allows the user to set the device permanently to operate in the

Password Protection Mode

Table 8.5 Lock Register

DQ15-3

DQ2

DQ1

DQ0

Password Protection Mode Lock

Bit

Persistent Protection Mode Lock

Bit

Secured Silicon Sector

Protection Bit

Don’t Care

8.13 Persistent Sector Protection

The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the

same time enhancing flexibility by providing three different sector protection states:

Dynamically Locked -The sector is protected and can be changed by a simple command

Persistently Locked -A sector is protected and cannot be changed

Unlocked -The sector is unprotected and can be changed by a simple command

In order to achieve these states, three types of “bits” are going to be used:

8.13.1

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYB

bits are in the “unprotected state”. Each DYB is individually modifiable through the DYB Set Command and

DYB Clear Command. When the parts are first shipped, all of the Persistent Protect Bits (PPB) are cleared

into the unprotected state. The DYB bits and PPB Lock bit are defaulted to power up in the cleared state or

unprotected state - meaning the all PPB bits are changeable.

The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that

sector. For the sectors that have the PPB bits cleared, the DYB bits control whether or not the sector is

protected or unprotected. By issuing the DYB Set and DYB Clear command sequences, the DYB bits is

protected or unprotected, thus placing each sector in the protected or unprotected state. These are the so-

called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch

back and forth between the protected and un-protected conditions. This allows software to easily protect

sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are

needed.

The DYB bits maybe set or cleared as often as needed. The PPB bits allow for a more static, and difficult to

change, level of protection. The PPB bits retain their state across power cycles because they are Non-

May 1, 2006 S29GL-N_01_A0

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D a t a S h e e t

Volatile. Individual PPB bits are set with a program command but must all be cleared as a group through an

erase command.

The PPB Lock Bit adds an additional level of protection. Once all PPB bits are programmed to the desired

settings, the PPB Lock Bit may be set to the “freeze state”. Setting the PPB Lock Bit to the “freeze state”

disables all program and erase commands to the Non-Volatile PPB bits. In effect, the PPB Lock Bit locks the

PPB bits into their current state. The only way to clear the PPB Lock Bit to the “unfreeze state” is to go

through a power cycle, or hardware reset. The Software Reset command does not clear the PPB Lock Bit to

the “unfreeze state”. System boot code can determine if any changes to the PPB bits are needed e.g. to allow

new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock Bit

to disable any further changes to the PPB bits during system operation.

The WP# write protect pin adds a final level of hardware protection. When this pin is low it is not possible to

change the contents of the WP# protected sectors. These sectors generally hold system boot code. So, the

WP# pin can prevent any changes to the boot code that could override the choices made while setting up

sector protection during system initialization.

It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state.

The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB

Set command sequence is all that is necessary. The DYB Set and DYB Clear commands for the dynamic

sectors switch the DYB bits to signify protected and unprotected, respectively. If there is a need to change the

status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be

disabled to the “unfreeze state” by either putting the device through a power-cycle, or hardware reset. The

PPB bits can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again to the

“freeze state” locks the PPB bits, and the device operates normally again.

To achieve the best protection, execute the PPB Lock Bit Set command early in the boot code, and protect

the boot code by holding WP# = V_IL.

8.13.2

Persistent Protection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is assigned to each sector. If a PPB is programmed to the

protected state through the “PPB Program” command, that sector is protected from program or erase

operations is read-only. If a PPB requires erasure, all of the sector PPB bits must first be erased in parallel

through the “All PPB Erase” command. The “All PPB Erase” command preprograms all PPB bits prior to PPB

erasing. All PPB bits erase in parallel, unlike programming where individual PPB bits are programmable. The

PPB bits have the same endurance as the flash memory.

Programming the PPB bit requires the typical word programming time without utilizing the Write Buffer.

During a PPB bit programming and all PPB bit erasing sequence executions, the DQ6 Toggle Bit I toggles

until the programming of the PPB bit or erasing of all PPB bits has completed to indicate programming and

erasing status. Erasing all of the PPB bits at once requires typical sector erase time. During the erasing of all

PPB bits, the DQ3 Sector Erase Timer bit outputs a 1 to indicate the erasure of all PPB bits are in progress.

When the erasure of all PPB bits has completed, the DQ3 Sector Erase Timer bit outputs a 0 to indicate that

all PPB bits have been erased. Reading the PPB Status bit requires the initial access time of the device.

8.13.3

Persistent Protection Bit Lock (PPB Lock Bit)

A global volatile bit. When set to the “freeze state”, the PPB bits cannot be changed. When cleared to the

“unfreeze state”, the PPB bits are changeable. There is only one PPB Lock Bit per device. The PPB Lock Bit

is cleared to the “unfreeze state” after power-up or hardware reset. There is no command sequence to unlock

or “unfreeze” the PPB Lock Bit.

Configuring the PPB Lock Bit to the freeze state requires approximately 100ns. Reading the PPB Lock Status

bit requires the initial access time of the device.

26

S29GL-N

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D a t a S h e e t

Table 8.6 Sector Protection Schemes

Protection States

DYB Bit

Unprotect

Protect

PPB Bit

Unprotect

Protect

PPB Lock Bit

Unfreeze

Freeze

Sector State

Unprotected – PPB and DYB are changeable

Unprotected – PPB not changeable, DYB is changeable

Protected – PPB and DYB are changeable

Unfreeze

Freeze

Protect

Protected – PPB not changeable, DYB is changeable

Protected – PPB and DYB are changeable

Unprotect

Protect

Unfreeze

Freeze

Protect

Protected – PPB not changeable, DYB is changeable

Protected – PPB and DYB are changeable

Protect

Unfreeze

Freeze

Protect

Protected – PPB not changeable, DYB is changeable

Table 8.6 contains all possible combinations of the DYB bit, PPB bit, and PPB Lock Bit relating to the status

of the sector. In summary, if the PPB bit is set, and the PPB Lock Bit is set, the sector is protected and the

protection cannot be removed until the next power cycle or hardware reset clears the PPB Lock Bit to

“unfreeze state”. If the PPB bit is cleared, the sector can be dynamically locked or unlocked. The DYB bit then

controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a

protected sector, the device ignores the command and returns to read mode. A program command to a

protected sector enables status polling for approximately 1 µs before the device returns to read mode without

having modified the contents of the protected sector. An erase command to a protected sector enables status

polling for approximately 50 µs after which the device returns to read mode without having erased the

protected sector. The programming of the DYB bit, PPB bit, and PPB Lock Bit for a given sector can be

verified by writing a DYB Status Read, PPB Status Read, and PPB Lock Status Read commands to the

device.

The Autoselect Sector Protection Verification outputs the OR function of the DYB bit and PPB bit per sector

basis. When the OR function of the DYB bit and PPB bit is a 1, the sector is either protected by DYB or PPB

or both. When the OR function of the DYB bit and PPB bit is a 0, the sector is unprotected through both the

DYB and PPB.

8.14 Persistent Protection Mode Lock Bit

Like the Password Protection Mode Lock Bit, a Persistent Protection Mode Lock Bit exists to guarantee that

the device remain in software sector protection. Once programmed, the Persistent Protection Mode Lock Bit

prevents programming of the Password Protection Mode Lock Bit. This guarantees that a hacker could not

place the device in Password Protection Mode. The Password Protection Mode Lock Bit resides in the “Lock

Register”.

8.15 Password Sector Protection

The Password Sector Protection method allows an even higher level of security than the Persistent Sector

Protection method. There are two main differences between the Persistent Sector Protection and the

Password Sector Protection methods:

When the device is first powered on, or comes out of a reset cycle, the PPB Lock Bit is set to the locked

state, or the freeze state, rather than cleared to the unlocked state, or the unfreeze state.

The only means to clear and unfreeze the PPB Lock Bit is by writing a unique 64-bit Password to the

device.

The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method.

A 64-bit password is the only additional tool utilized in this method.

The password is stored in a one-time programmable (OTP) region outside of the flash memory. Once the

Password Protection Mode Lock Bit is set, the password is permanently set with no means to read, program,

or erase it. The password is used to clear and unfreeze the PPB Lock Bit. The Password Unlock command

must be written to the flash, along with a password. The flash device internally compares the given password

with the pre-programmed password. If they match, the PPB Lock Bit is cleared to the unfreezed state, and the

PPB bits can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for

May 1, 2006 S29GL-N_01_A0

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D a t a S h e e t

each password check after the valid 64-bit password is entered for the PPB Lock Bit to be cleared to the

unfreezed state. This delay is intended to thwart any efforts to run a program that tries all possible

combinations in order to crack the password.

8.16 Password and Password Protection Mode Lock Bit

In order to select the Password Sector Protection method, the customer must first program the password.

The factory recommends that the password be somehow correlated to the unique Electronic Serial Number

(ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password

should be different for every flash device. While programming in the password region, the customer may

perform Password Read operations. Once the desired password is programmed in, the customer must then

set the Password Protection Mode Lock Bit. This operation achieves two objectives:

1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to

reverse this function.

2. It also disables all further commands to the password region. All program, and read operations are

ignored.

Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The

user must be sure that the Password Sector Protection method is desired when programming the Password

Protection Mode Lock Bit. More importantly, the user must be sure that the password is correct when the

Password Protection Mode Lock Bit is programmed. Due to the fact that read operations are disabled, there is

no means to read what the password is afterwards. If the password is lost after programming the Password

Protection Mode Lock Bit, there is no way to clear and unfreeze the PPB Lock Bit. The Password Protection

Mode Lock Bit, once programmed, prevents reading the 64-bit password on the DQ bus and further password

programming. The Password Protection Mode Lock Bit is not erasable. Once Password Protection Mode

Lock Bit is programmed, the Persistent Protection Mode Lock Bit is disabled from programming, guaranteeing

that no changes to the protection scheme are allowed.

8.17 64-bit Password

The 64-bit Password is located in its own memory space and is accessible through the use of the Password

Program and Password Read commands. The password function works in conjunction with the Password

Protection Mode Lock Bit, which when programmed, prevents the Password Read command from reading

the contents of the password on the pins of the device.

8.18 Persistent Protection Bit Lock (PPB Lock Bit)

A global volatile bit. The PPB Lock Bit is a volatile bit that reflects the state of the Password Protection Mode

Lock Bit after power-up reset. If the Password Protection Mode Lock Bit is also programmed after

programming the Password, the Password Unlock command must be issued to clear and unfreeze the PPB

Lock Bit after a hardware reset (RESET# asserted) or a power-up reset. Successful execution of the

Password Unlock command clears and unfreezes the PPB Lock Bit, allowing for sector PPB bits to be

modified. Without issuing the Password Unlock command, while asserting RESET#, taking the device

through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a the “freeze

state”.

If the Password Protection Mode Lock Bit is not programmed, the device defaults to Persistent Protection

Mode. In the Persistent Protection Mode, the PPB Lock Bit is cleared to the unfreeze state after power-up or

hardware reset. The PPB Lock Bit is set to the freeze state by issuing the PPB Lock Bit Set command. Once

set to the freeze state the only means for clearing the PPB Lock Bit to the “unfreeze state” is by issuing a

hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode.

Reading the PPB Lock Bit requires a 200ns access time.

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8.19 Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector feature provides a Flash memory region that enables permanent part

identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length,

and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is

locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed,

which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is

shipped to the field.

The factory offers the device with the Secured Silicon Sector either customer lockable (standard shipping

option) or factory locked (contact an AMD sales representative for ordering information). The customer-

lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to program the

sector after receiving the device. The customer-lockable version also has the Secured Silicon Sector

Indicator Bit permanently set to a 0. The factory-locked version is always protected when shipped from the

factory, and has the Secured Silicon Sector Indicator Bit permanently set to a 1. Thus, the Secured Silicon

Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory

locked.

The Secured Silicon sector address space in this device is allocated as follows:

Secured Silicon Sector

Address Range

ExpressFlash

Factory Locked

Customer Lockable

ESN Factory Locked

ESN

000000h–000007h

000008h–00007Fh

ESN or determined by customer

Determined by customer

Unavailable

The system accesses the Secured Silicon Sector through a command sequence (see Write Protect (WP#)

on page 30). After the system has written the Enter Secured Silicon Sector command sequence, it may read

the Secured Silicon Sector by using the addresses normally occupied by the first sector (SA0). This mode of

operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until

power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending

commands to sector SA0.

8.19.1

Customer Lockable: Secured Silicon Sector NOT Programmed or Protected

At the Factory

Unless otherwise specified, the device is shipped such that the customer may program and protect the 256-

byte Secured Silicon sector.

The system may program the Secured Silicon Sector using the write-buffer, accelerated and/or unlock

bypass methods, in addition to the standard programming command sequence. See Command Definitions

on page 34.

Programming and protecting the Secured Silicon Sector must be used with caution since, once protected,

there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the

Secured Silicon Sector memory space can be modified in any way.

The Secured Silicon Sector area can be protected using one of the following procedures:

Write the three-cycle Enter Secured Silicon Sector Region command.

To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm.

Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured

Silicon Sector Region command sequence to return to reading and writing within the remainder of the array.

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8.19.2

Factory Locked: Secured Silicon Sector Programmed and Protected At the

Factory

In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory.

The Secured Silicon Sector cannot be modified in any way. An ESN Factory Locked device has an 16-byte

random ESN at addresses 000000h–000007h. Please contact your sales representative for details on

ordering ESN Factory Locked devices.

Customers may opt to have their code programmed by the factory through the ExpressFlash service (Express

Flash Factory Locked). The devices are then shipped from the factory with the Secured Silicon Sector

permanently locked. Contact your sales representative for details on using the ExpressFlash service.

8.20 Write Protect (WP#)

The Write Protect function provides a hardware method of protecting the first or last sector group without

using V_ID. Write Protect is one of two functions provided by the WP#/ACC input.

If the system asserts V_ILon the WP#/ACC pin, the device disables program and erase functions in the first or

last sector group independently of whether those sector groups were protected or unprotected using the

method described in Advanced Sector Protection on page 24. Note that if WP#/ACC is at V_ILwhen the

device is in the standby mode, the maximum input load current is increased. See the table in DC

Characteristics on page 57.

If the system asserts V_IHon the WP#/ACC pin, the device reverts to whether the first or last sector

was previously set to be protected or unprotected. Note that WP# has an internal pull-up; when

unconnected, WP# is at V_IH.

8.21 Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection

against inadvertent writes (refer to Table 11.1 on page 46 and Table 11.3 on page 48 for command

definitions). In addition, the following hardware data protection measures prevent accidental erasure or

programming, which might otherwise be caused by spurious system level signals during V_CCpower-up and

power-down transitions, or from system noise.

8.21.1

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not accept any write cycles. This protects data during V_CC

power-up and power-down. The command register and all internal program/erase circuits are disabled, and

the device resets to the read mode. Subsequent writes are ignored until V_CCis greater than V_LKO. The

system must provide the proper signals to the control pins to prevent unintentional writes when V_CCis greater

than V_LKO

.

8.21.2

8.21.3

Write Pulse Glitch Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a logical one.

8.21.4

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up, the device does not accept commands on the rising

edge of WE#. The internal state machine is automatically reset to the read mode on power-up.

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9. Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software interrogation

handshake, which allows specific vendor-specified software algorithms to be used for entire families of

devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address

55h, any time the device is ready to read array data. The system can read CFI information at the addresses

given in Table 9.1 to Table 9.3 on page 32. To terminate reading CFI data, the system must write the reset

command.

The system can also write the CFI query command when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read CFI data at the addresses given in Table 9.1 to

Table 9.4 on page 33. The system must write the reset command to return the device to reading array data.

For further information, please refer to the CFI Specification and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact your sales representative for copies of

these documents.

Table 9.1 CFI Query Identification String

Addresses (x16) Addresses (x8)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

Table 9.2 System Interface String

Addresses (x16) Addresses (x8)

Data

Description

V

Min. (write/erase)

CC

1Bh

1Ch

36h

38h

0027h

0036h

D7–D4: volt, D3–D0: 100 millivolt

V

Max. (write/erase)

CC

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0007h

000Ah

0000h

0003h

0005h

0004h

0000h

V

Min. voltage (00h = no V pin present)

PP

Max. voltage (00h = no V pin present)

PP

Typical timeout per single byte/word write 2^Nµs

^{Typical timeout for Min. size buffer write 2}^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

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Table 9.3 Device Geometry Definition

Addresses (x16) Addresses (x8)

Data

Description

Device Size = 2^Nbyte

1A = 512 Mb

001Ah

0019h

0018h

27h

4Eh

19 = 256 Mb

18 = 128 Mb

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0005h

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

Number of Erase Block Regions within device

01h = uniform device

2Ch

58h

0001h

02h = boot device)

Erase Block Region 1 Information

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

00xxh

000xh

0000h

000xh

(refer to the CFI specification or CFI publication 100)

00FFh, 001h, 0000h, 0002h = 512 Mb

00FFh, 0000h, 0000h, 0002h = 256 Mb

007Fh, 0000h, 0000h, 0002h = 128 Mb

31h

32h

33h

34h

62h

64h

66h

68h

0000h

Erase Block Region 2 Information (refer to CFI publication 100)

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

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Table 9.4 Primary Vendor-Specific Extended Query

Addresses (x16) Addresses (x8)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required

45h

8Ah

0010h

1 = Not Required

Process Technology (Bits 7-2) 0100b = 110 nm MirrorBit

Erase Suspend

0 = Not Supported

1 = To Read Only

2 = To Read & Write

46h

47h

8Ch

8Eh

0002h

0001h

Sector Protect

0 = Not Supported

X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported

01 = Supported

48h

49h

4Ah

90h

92h

94h

0000h

0008h

0000h

Sector Protect/Unprotect scheme

0008h = Advanced Sector Protection

Simultaneous Operation

00 = Not Supported

X = Number of Sectors in Bank

Burst Mode Type

00 = Not Supported

01 = Supported

4Bh

4Ch

96h

98h

0000h

0002h

Page Mode Type

00 = Not Supported

01 = 4 Word Page

02 = 8 Word Page

ACC (Acceleration) Supply Minimum

00h = Not Supported

D7-D4: Volt

4Dh

4Eh

9Ah

9Ch

00B5h

00C5h

D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported

D7-D4: Volt

D3-D0: 100 mV

WP# Protection

4Fh

50h

9Eh

A0h

00xxh

0001h

04h = Uniform sectors bottom WP# protect

05h = Uniform sectors top WP# protect

Program Suspend

00h = Not Supported

01h = Supported

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10. Command Definitions

Writing specific address and data commands or sequences into the command register initiates device

operations. Table 11.1 on page 46 and Table 11.3 on page 48 define the valid register command sequences.

Writing incorrect address and data values or writing them in the improper sequence may place the device in

an unknown state. A reset command is then required to return the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens first. Refer to AC Characteristics on page 59 for timing

diagrams.

10.1 Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to

retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded

Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after

which the system can read data from any non-erase-suspended sector. After completing a programming

operation in the Erase Suspend mode, the system may once again read array data with the same exception.

See Erase Suspend/Erase Resume Commands on page 42 for more information.

The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if

DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See

Reset Command on page 34 for more information.

See also Requirements for Reading Array Data on page 12 for more information. Read-Only Operations

on page 59 provides the read parameters, and Figure 18.1 on page 59 shows the timing diagram.

10.2 Reset Command

Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t

cares for this command.

The reset command may be written between the sequence cycles in an erase command sequence before

erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores

reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before

programming begins. This resets the device to the read mode. If the program command sequence is written

while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-

suspend-read mode. Once programming begins, however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must be written to return to the read mode. If the device

entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device

to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the

read mode (or erase-suspend-read mode if the device was in Erase Suspend).

Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-to-

Buffer-Abort Reset command sequence to reset the device for the next operation.

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10.3 Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and device codes,

and determine whether or not a sector is protected. Table 11.1 on page 46 and Table 11.3 on page 48 show

the address and data requirements. This method is an alternative to that shown in Table 8.4 on page 23,

which is intended for PROM programmers and requires V_IDon address pin A9. The autoselect command

sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect

command may not be written while the device is actively programming or erasing.

The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third

write cycle that contains the autoselect command. The device then enters the autoselect mode. The system

may read at any address any number of times without initiating another autoselect command sequence:

A read cycle at address XX00h returns the manufacturer code.

Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code.

A read cycle to an address containing a sector address (SA), and the address 02h on A7–A0 in word mode

returns 01h if the sector is protected, or 00h if it is unprotected.

The system must write the reset command to return to the read mode (or erase-suspend-read mode if the

device was previously in Erase Suspend).

10.4 Enter Secured Silicon Sector/Exit Secured Silicon

Sector Command Sequence

The Secured Silicon Sector region provides a secured data area containing an 8-word/16-byte random

Electronic Serial Number (ESN). The system can access the Secured Silicon Sector region by issuing the

three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured

Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence.

The Exit Secured Silicon Sector command sequence returns the device to normal operation. Table 11.1

on page 46 shows the address and data requirements for both command sequences. See also Secured Silicon

Sector Flash Memory Region on page 29 for further information. Note that the ACC function and unlock

bypass modes are not available when the Secured Silicon Sector is enabled.

10.5 Word Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two

unlock write cycles, followed by the program set-up command. The program address and data are written

next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further

controls or timings. The device automatically provides internally generated program pulses and verifies the

programmed cell margin. Table 11.1 on page 46 and Table 11.3 on page 48 show the address and data

requirements for the word program command sequence.

When the Embedded Program algorithm is complete, the device then returns to the read mode and

addresses are no longer latched. The system can determine the status of the program operation by using

DQ7 or DQ6. Refer to Write Operation Status on page 50 for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored. Note that the

Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program operation is in

progress. Note that a hardware reset immediately terminates the program operation. The program

command sequence should be reinitiated once the device has returned to the read mode, to ensure data

integrity.

Programming is allowed in any sequence of address locations and across sector boundaries. Programming

to the same word address multiple times without intervening erases (incremental bit programming) is

permitted. Word programming is supported for backward compatibility with existing Flash driver software and

for occasional writing of individual words. Use of Write Buffer Programming is strongly recommended for

general programming use when more than a few words are to be programmed. The effective word

programming time using Write Buffer Programming is much shorter than the single word programming time.

Any bit cannot be programmed from 0 back to a 1. Attempting to do so may cause the device to set DQ5

= 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding

read shows that the data is still 0. Only erase operations can convert a 0 to a 1.

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10.5.1

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program words to the device faster than using the standard

program command sequence. The unlock bypass command sequence is initiated by first writing two unlock

cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then

enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is

required to program in this mode. The first cycle in this sequence contains the unlock bypass program

command, A0h; the second cycle contains the program address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial two unlock cycles required in the standard program

command sequence, resulting in faster total programming time. Table 11.1 on page 46 and Table 11.3

on page 48 show the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are

valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command

sequence. (See Table 11.1 on page 46 and Table 11.3 on page 48).

10.5.2

Write Buffer Programming

Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming

operation. This results in faster effective programming time than the standard programming algorithms. The

Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed

by a third write cycle containing the Write Buffer Load command written at the Sector Address in which

programming occurs. The fourth cycle writes the sector address and the number of word locations, minus

one, to be programmed. For example, if the system programs six unique address locations, then 05h should

be written to the device. This tells the device how many write buffer addresses are loaded with data and

therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot

exceed the size of the write buffer or the operation aborts.

The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected

by address bits A_MAX–A₄. All subsequent address/data pairs must fall within the selected-write-buffer-page.

The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be

loaded in any order.

The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This

means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also means

that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load

programming data outside of the selected write-buffer page, the operation aborts.)

Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter is

decremented for every data load operation. The host system must therefore account for loading a write-buffer

location more than once. The counter decrements for each data load operation, not for each unique write-

buffer-address location. Note also that if an address location is loaded more than once into the buffer, the

final data loaded for that address is programmed.

Once the specified number of write buffer locations have been loaded, the system must then write the

Program Buffer to Flash command at the sector address. Any other address and data combination aborts the

Write Buffer Programming operation. The device then begins programming. Data polling should be used

while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be

monitored to determine the device status during Write Buffer Programming.

The write-buffer programming operation can be suspended using the standard program suspend/resume

commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to

execute the next command.

The Write Buffer Programming Sequence can be aborted in the following ways:

Load a value that is greater than the page buffer size during the Number of Locations to Program step.

Write to an address in a sector different than the one specified during the Write-Buffer-Load command.

Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address

during the write buffer data loading stage of the operation.

Write data other than the Confirm Command after the specified number of data load cycles.

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The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 =

toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for

the next operation.

Write buffer programming is allowed in any sequence. Note that the Secured Silicon sector, autoselect, and

CFI functions are unavailable when a program operation is in progress. This flash device is capable of

handling multiple write buffer programming operations on the same write buffer address range without

intervening erases. For applications requiring incremental bit programming, a modified programming method

is required, please contact your local Spansion representative. Any bit in a write buffer address range

cannot be programmed from 0 back to a 1. Attempting to do so may cause the device to set DQ5 = 1, or

cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read

shows that the data is still 0. Only erase operations can convert a 0 to a 1.

10.5.3

Accelerated Program

The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V_HH

on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write

the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/

ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V_HHfor operations other than

accelerated programming, or device damage may result. WP# has an internal pull-up; when unconnected,

WP# is at V_IH.

Figure 10.2 on page 39 illustrates the algorithm for the program operation. Refer to Erase and Program

Operations on page 62 for parameters, and Figure 18.4 on page 63 for timing diagrams.

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Figure 10.1 Write Buffer Programming Operation

Write “Write to Buffer”

command and

Sector Address

Part of “Write to Buffer”

Command Sequence

Write number of addresses

to program minus 1(WC)

and Sector Address

Write first address/data

Yes

WC = 0 ?

No

Write to a different

sector address

Abort Write to

Buffer Operation?

Yes

Write to buffer ABORTED.

Must write “Write-to-buffer

Abort Reset” command

sequence to return

No

(Note 1)

Write next address/data pair

to read mode.

WC = WC - 1

Write program buffer to

flash sector address

Read DQ15 - DQ0 at

Last Loaded Address

Yes

DQ7 = Data?

No

DQ1 = 1?

Yes

DQ5 = 1?

Yes

Read DQ15 - DQ0 with

address = Last Loaded

Address

Yes

(Note 2)

DQ7 = Data?

No

(Note 3)

FAIL or ABORT

PASS

Notes

1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address

locations with data, all addresses must fall within the selected Write-Buffer Page.

2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified.

3. If this flowchart location was reached because DQ5= 1, then the device FAILED. If this flowchart location was reached because DQ1= 1,

then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin

another operation. If DQ1=1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5=1, write the Reset command.

4. See Table 11.1 on page 46 and Table 11.3 on page 48 for command sequences required for write buffer programming.

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Figure 10.2 Program Operation

START

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note

See Table 11.1 on page 46 and Table 11.3 on page 48 for program command sequence.

10.6 Program Suspend/Program Resume Command Sequence

The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer

programming operation so that data can be read from any non-suspended sector. When the Program

Suspend command is written during a programming process, the device halts the program operation within

15 µs maximum (5 µs typical) and updates the status bits. Addresses are not required when writing the

Program Suspend command.

After the programming operation is suspended, the system can read array data from any non-suspended

sector. The Program Suspend command may also be issued during a programming operation while an erase

is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend.

If a read is needed from the Secured Silicon Sector area (One-time Program area), then user must use the

proper command sequences to enter and exit this region. Note that the Secured Silicon Sector autoselect,

and CFI functions are unavailable when program operation is in progress.

The system may also write the autoselect command sequence when the device is in the Program Suspend

mode. The system can read as many autoselect codes as required. When the device exits the autoselect

mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See

Autoselect Command Sequence on page 35 for more information.

After the Program Resume command is written, the device reverts to programming. The system can

determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard

program operation. See Write Operation Status on page 50 for more information.

The system must write the Program Resume command (address bits are don’t care) to exit the Program

Suspend mode and continue the programming operation. Further writes of the Resume command are

ignored. Another Program Suspend command can be written after the device has resume programming.

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Figure 10.3 Program Suspend/Program Resume

Program Operation

or Write-to-Buffer

Sequence in Progress

Write Program Suspend

Command Sequence

Write address/data

XXXh/B0h

Command is also valid for

Erase-suspended-program

operations

Wait 15 μs

Autoselect and SecSi Sector

read operations are also allowed

Read data as

required

Data cannot be read from erase- or

program-suspended sectors

Done

No

reading?

Yes

Write Program Resume

Command Sequence

Write address/data

XXXh/30h

Device reverts to

operation prior to

Program Suspend

10.7 Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical erase. The system is not required to provide any

controls or timings during these operations. Table 11.1 on page 46 and Table 11.3 on page 48 show the

address and data requirements for the chip erase command sequence.

When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no

longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2.

Refer to Write Operation Status on page 50 for information on these status bits.

Any commands written during the chip erase operation are ignored, including erase suspend commands.

However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip

erase command sequence should be reinitiated once the device has returned to reading array data, to ensure

data integrity.

Figure 10.4 on page 41 illustrates the algorithm for the erase operation. Note that the Secured Silicon

Sector, autoselect, and CFI functions are unavailable when an erase operation in is progress. Refer to

Erase and Program Operations on page 62 for parameters, and Figure 18.6 on page 64 for timing diagrams.

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10.8 Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed

by the address of the sector to be erased, and the sector erase command. Table 11.1 on page 46 and

Table 11.3 on page 48 shows the address and data requirements for the sector erase command sequence.

The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm

automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase.

The system is not required to provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may

be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between

these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and

command following the exceeded time-out may or may not be accepted. It is recommended that processor

interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be

re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets the device to the read mode. Note that the Secured

Silicon Sector, autoselect, and CFI functions are unavailable when an erase operation in is progress.

The system must rewrite the command sequence and any additional addresses and commands.

The system can monitor DQ3 to determine if the sector erase timer has timed out (See DQ3: Sector Erase

Timer on page 55.). The time-out begins from the rising edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses

are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or

DQ2 in the erasing sector. Refer to Write Operation Status on page 50 for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands

are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs,

the sector erase command sequence should be reinitiated once the device has returned to reading array

data, to ensure data integrity.

Figure 10.4 on page 41 illustrates the algorithm for the erase operation. Refer to Erase and Program

Operations on page 62 for parameters, and Figure 18.6 on page 64 for timing diagrams.

Figure 10.4 Erase Operation

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes

1. See Table 11.1 on page 46 and Table 11.3 on page 48 for program command sequence.

2. See DQ3: Sector Erase Timer on page 55 for information on the sector erase timer.

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10.9 Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected for erasure. This command is valid only during the

sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The

Erase Suspend command is ignored if written during the chip erase operation or Embedded Program

algorithm.

When the Erase Suspend command is written during the sector erase operation, the device requires a typical

of 5 μs (maximum of 20 μs) to suspend the erase operation. However, when the Erase Suspend command is

written during the sector erase time-out, the device immediately terminates the time-out period and suspends

the erase operation.

After the erase operation is suspended, the device enters the erase-suspend-read mode. The system can

read data from or program data to any sector not selected for erasure. (The device erase suspends all

sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status

information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is

actively erasing or is erase-suspended. Refer to Write Operation Status on page 50 for information on these

status bits.

After an erase-suspended program operation is complete, the device returns to the erase-suspend-read

mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just

as in the standard word program operation. Refer to Write Operation Status on page 50 for more information.

In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to

Autoselect Mode on page 23 and Autoselect Command Sequence on page 35 for details.

To resume the sector erase operation, the system must write the Erase Resume command. The address of

the erase-suspended sector is required when writing this command. Further writes of the Resume command

are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. It is

important to allow an interval of at least 5 ms between Erase Resume and Erase Suspend.

10.10 Lock Register Command Set Definitions

The Lock Register Command Set permits the user to one-time program the Secured Silicon Sector Protection

Bit, Persistent Protection Mode Lock Bit, and Password Protection Mode Lock Bit. The Lock Register bits are

all readable after an initial access delay.

The Lock Register Command Set Entry command sequence must be issued prior to any of the following

commands listed, to enable proper command execution.

Note that issuing the Lock Register Command Set Entry command disables reads and writes for the

flash memory.

Lock Register Program Command

Lock Register Read Command

The Lock Register Command Set Exit command must be issued after the execution of the commands to

reset the device to read mode. Otherwise the device hangs. If this happens, the flash device must be reset.

Please refer to Reset Command on page 34 for more information. It is important to note that the device is in

either Persistent Protection mode or Password Protection mode depending on the mode selected prior to the

device hang.

For either the Secured Silicon Sector to be locked, or the device to be permanently set to the Persistent

Protection Mode or the Password Protection Mode, the associated Lock Register bits must be programmed.

Note that only the Persistent Protection Mode Lock Bit or the Password Protection Mode Lock Bit can be

programmed. The Lock Register Program operation aborts if there is an attempt to program both the

Persistent Protection Mode and the Password Protection Mode Lock bits.

The Lock Register Command Set Exit command must be initiated to re-enable reads and writes to the main

memory.

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10.11 Password Protection Command Set Definitions

The Password Protection Command Set permits the user to program the 64-bit password, verify the

programming of the 64-bit password, and then later unlock the device by issuing the valid 64-bit password.

The Password Protection Command Set Entry command sequence must be issued prior to any of the

commands listed following to enable proper command execution.

Note that issuing the Password Protection Command Set Entry command disabled reads and writes the

main memory.

Password Program Command

Password Read Command

Password Unlock Command

The Password Program command permits programming the password that is used as part of the hardware

protection scheme. The actual password is 64-bits long. There is no special addressing order required for

programming the password. The password is programmed in 8-bit or 16-bit portions. Each portion

requires a Password Program Command.

Once the Password is written and verified, the Password Protection Mode Lock Bit in the Lock Register must

be programmed in order to prevent verification. The Password Program command is only capable of

programming 0s. Programming a 1 after a cell is programmed as a 0 results in a time-out by the Embedded

Program Algorithm^TMwith the cell remaining as a 0. The password is all F’s when shipped from the factory. All

64-bit password combinations are valid as a password.

The Password Read command is used to verify the Password. The Password is verifiable only when the

Password Protection Mode Lock Bit in the Lock Register is not programmed. If the Password Protection

Mode Lock Bit in the Lock Register is programmed and the user attempts to read the Password, the device

always drives all F’s onto the DQ data bus.

The lower two address bits (A1–A0) for word mode and (A1–A-1) for by byte mode are valid during the

Password Read, Password Program, and Password Unlock commands. Writing a 1 to any other address

bits (A_MAX-A2) aborts the Password Read and Password Program commands.

The Password Unlock command is used to clear the PPB Lock Bit to the unfreeze state so that the PPB bits

can be modified. The exact password must be entered in order for the unlocking function to occur. This 64-bit

Password Unlock command sequence takes at least 2 µs to process each time to prevent a hacker from

running through the all 64-bit combinations in an attempt to correctly match the password. If another

password unlock is issued before the 64-bit password check execution window is completed, the command is

ignored. If the wrong address or data is given during password unlock command cycle, the device may enter

the write-to-buffer abort state. In order to exit the write-to-abort state, the write-to-buffer-abort-reset command

must be given. Otherwise the device hangs.

The Password Unlock function is accomplished by writing Password Unlock command and data to the device

to perform the clearing of the PPB Lock Bit to the unfreeze state. The password is 64 bits long. A1 and A0 are

used for matching in word mode and A1, A0, A-1 in byte mode. Writing the Password Unlock command does

not need to be address order specific. An example sequence is starting with the lower address A1-A0=00,

followed by A1-A0=01, A1-A0=10, and A1-A0=11 if the device is configured to operate in word mode.

Approximately 2 µs is required for unlocking the device after the valid 64-bit password is given to the device.

It is the responsibility of the microprocessor to keep track of the entering the portions of the 64-bit password

with the Password Unlock command, the order, and when to read the PPB Lock bit to confirm successful

password unlock. In order to re-lock the device into the Password Protection Mode, the PPB Lock Bit Set

command can be re-issued.

Note: The Password Protection Command Set Exit command must be issued after the execution of the

commands listed previously to reset the device to read mode. Otherwise the device hangs.

Note: Issuing the Password Protection Command Set Exit command re-enables reads and writes for the

main memory.

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10.12 Non-Volatile Sector Protection Command Set Definitions

The Non-Volatile Sector Protection Command Set permits the user to program the Persistent Protection Bits

(PPB bits), erase all of the Persistent Protection Bits (PPB bits), and read the logic state of the Persistent

Protection Bits (PPB bits).

The Non-Volatile Sector Protection Command Set Entry command sequence must be issued prior to any

of the commands listed following to enable proper command execution.

Note that issuing the Non-Volatile Sector Protection Command Set Entry command disables reads and

writes for the main memory.

PPB Program Command

The PPB Program command is used to program, or set, a given PPB bit. Each PPB bit is individually

programmed (but is bulk erased with the other PPB bits). The specific sector address (A23-A16 for

S29GL256N, A22-A16 for S29GL128N) is written at the same time as the program command. If the PPB

Lock Bit is set to the freeze state, the PPB Program command does not execute and the command times-

out without programming the PPB bit.

All PPB Erase Command

The All PPB Erase command is used to erase all PPB bits in bulk. There is no means for individually

erasing a specific PPB bit. Unlike the PPB program, no specific sector address is required. However, when

the All PPB Erase command is issued, all Sector PPB bits are erased in parallel. If the PPB Lock Bit is set

to freeze state, the ALL PPB Erase command does not execute and the command times-out without

erasing the PPB bits.

The device preprograms all PPB bits prior to erasing when issuing the All PPB Erase command. Also note

that the total number of PPB program/erase cycles has the same endurance as the flash memory array.

PPB Status Read Command

The programming state of the PPB for a given sector can be verified by writing a PPB Status Read

Command to the device. This requires an initial access time latency.

The Non-Volatile Sector Protection Command Set Exit command must be issued after the execution of

the commands listed previously to reset the device to read mode.

Note that issuing the Non-Volatile Sector Protection Command Set Exit command re-enables reads and

writes for the main memory.

10.13 Global Volatile Sector Protection Freeze Command Set

The Global Volatile Sector Protection Freeze Command Set permits the user to set the PPB Lock Bit and

reading the logic state of the PPB Lock Bit.

The Global Volatile Sector Protection Freeze Command Set Entry command sequence must be issued

prior to any of the commands listed following to enable proper command execution.

Reads and writes from the main memory are not allowed.

PPB Lock Bit Set Command

The PPB Lock Bit Set command is used to set the PPB Lock Bit to the freeze state if it is cleared either at

reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear

command. Once the PPB Lock Bit is set to the freeze state, it cannot be cleared unless the device is taken

through a power-on clear (for Persistent Protection Mode) or the Password Unlock command is executed

(for Password Protection Mode). If the Password Protection Mode Lock Bit is programmed, the PPB Lock

Bit status is reflected as set to the freeze state, even after a power-on reset cycle.

PPB Lock Bit Status Read Command

The programming state of the PPB Lock Bit can be verified by executing a PPB Lock Bit Status Read

command to the device.

The Global Volatile Sector Protection Freeze Command Set Exit command must be issued after the

execution of the commands listed previously to reset the device to read mode.

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10.14 Volatile Sector Protection Command Set

The Volatile Sector Protection Command Set permits the user to set the Dynamic Protection Bit (DYB) to the

protected state, clear the Dynamic Protection Bit (DYB) to the unprotected state, and read the logic state of

the Dynamic Protection Bit (DYB).

The Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the

commands listed following to enable proper command execution.

Note that issuing the Volatile Sector Protection Command Set Entry command disables reads and

writes from main memory.

DYB Set Command

DYB Clear Command

The DYB Set and DYB Clear commands are used to protect or unprotect a given sector. The high order

address bits are issued at the same time as the code 00h or 01h on DQ7-DQ0. All other DQ data bus pins

are ignored during the data write cycle. The DYB bits are modifiable at any time, regardless of the state of

the PPB bit or PPB Lock Bit. The DYB bits are cleared to the unprotected state at power-up or hardware

reset.

DYB Status Read Command

The programming state of the DYB bit for a given sector can be verified by writing a DYB Status Read

command to the device. This requires an initial access delay.

The Volatile Sector Protection Command Set Exit command must be issued after the execution of the

commands listed previously to reset the device to read mode.

Note that issuing the Volatile Sector Protection Command Set Exit command re-enables reads and

writes to the main memory.

10.15 Secured Silicon Sector Entry Command

The Secured Silicon Sector Entry command allows the following commands to be executed

Read from Secured Silicon Sector

Program to Secured Silicon Sector

Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command has to

be issued to exit Secured Silicon Sector Mode.

10.16 Secured Silicon Sector Exit Command

The Secured Silicon Sector Exit command may be issued to exit the Secured Silicon Sector Mode.

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11. Command Definitions

Table 11.1 Memory Array Commands (x16)

Bus Cycles (Notes 1–5)

Third Fourth

Addr Addr

First

Addr

Second

Fifth

Addr

Sixth

Addr

Command Sequence

(Notes)

Data

RD

F0

Addr

Data

Asynchronous Read (6)

Reset (7)

1

4

6

4

1

4

6

1

3

2

6

1

3

4

1

4

RA

XXX

555

55

Manufacturer ID

AA

98

2AA

55

555

90

X00

X01

01

Device ID (8)

227E

Data

X0E

PA

Data

X0F

Data

Sector Protect Verify (9)

Secure Device Verify (10)

[SA]X02

X03

CFI Query (11)

Program

555

SA

AA

29

2AA

55

555

PA

A0

25

PA

SA

PD

Write to Buffer (12)

Program Buffer to Flash

Write to Buffer Abort Reset (13)

Entry

WC

PD

WBL

PD

555

XXX

555

XXX

555

00

AA

A0

80

2AA

PA

55

PD

30

10

00

55

555

F0

20

Program (14)

Sector Erase (14)

Chip Erase (14)

Reset

SA

80

SA

90

XXX

2AA

Chip Erase

AA

B0

30

555

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Erase/Program Suspend (15)

Erase/Program Resume (16)

Entry

AA

Data

AA

2AA

55

555

88

A0

Program (17)

PA

PD

00

Read (17)

Exit (17)

555

2AA

55

555

90

XXX

Legend

X = Don’t care.

RA = Read Address.

RD = Read Data.

PA = Program Address. Addresses latch on the falling edge of WE# or CE# pulse, whichever occurs later.

PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first.

SA = Sector Address. Any address that falls within a specified sector. See Table 8.2 on page 14 and Table 8.3 on page 20 for sector address ranges.

WBL = Write Buffer Location. Address must be within the same write buffer page as PA.

WC = Word Count. Number of write buffer locations to load minus 1.

Notes

1. See Table 8.1 on page 11 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells indicate read cycles.

4. Address and data bits not specified in table, legend, or notes are don’t cares (each hex digit implies 4 bits of data).

5. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset

command to return reading array data.

6. No unlock or command cycles required when bank is reading array data.

7. Reset command is required to return to reading array data in certain cases. See Reset Command on page 34 section for details.

8. Data in cycles 5 and 6 are listed in Table 8.4 on page 23.

9. The data is 00h for an unprotected sector and 01h for a protected sector. PPB Status Read provides the same data but in inverted form.

10. If DQ7 = 1, region is factory serialized and protected. If DQ7 = 0, region is unserialized and unprotected when shipped from factory. See Secured Silicon Sector

Flash Memory Region on page 29 for more information.

11. Command is valid when device is ready to read array data or when device is in autoselect mode.

12. Total number of cycles in the command sequence is determined by the number of words written to the write buffer.

13. Command sequence resets device for next command after write-to-buffer operation.

14. Requires Entry command sequence prior to execution. Unlock Bypass Reset command is required to return to reading array data.

15. System may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid

only during a sector erase operation.

16. Erase Resume command is valid only during the Erase Suspend mode.

17. Requires Entry command sequence prior to execution. Secured Silicon Sector Exit Reset command is required to exit this mode; device may otherwise be

placed in an unknown state.

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Table 11.2 Sector Protection Commands (x16)

Bus Cycles (Notes 1–4)

Third Fourth

First

Second

Fifth

Sixth

Seventh

Command Sequence

(Notes)

Addr Data Addr

Data

55

Addr

Data Addr Data Addr Data Addr Data Addr Data

Command Set Entry (5)

3

2

1

2

3

2

555

XX

00

AA

A0

2AA

XXX

555

40

Lock

Register

Bits

Program (6)

Data

Read (6)

Data

90

Command Set Exit (7)

Command Set Entry (5)

Program (8)

XX

555

XX

00

55

AA

A0

2AA

555

60

PWAx PWDx

PWD

0

PWD

2

PWD

3

Password

Protection

Read (9)

4

7

XXX

00

01

00

PWD1

03

02

00

03

01

PWD

0

PWD

1

PWD

2

PWD

3

Unlock (10)

25

02

03

00

29

Command Set Exit (7)

Command Set Entry (5)

PPB Program (11)

All PPB Erase (11, 12)

PPB Status Read

2

3

2

1

2

3

2

1

2

3

2

1

2

XX

555

XX

SA

XX

555

XX

90

AA

XX

2AA

SA

00

55

00

30

555

C0

A0

Non-Volatile

Sector

Protection

(PPB)

80

00

RD(0)

90

Command Set Exit (7)

Command Set Entry (5)

PPB Lock Bit Set

XX

2AA

XX

00

55

00

AA

555

50

E0

Global

Volatile Sector

Protection

Freeze

A0

PPB Lock Bit Status Read

Command Set Exit (7)

Command Set Entry (5)

DYB Set

XXX RD(0)

(PPB Lock)

XX

555

XX

SA

XX

90

AA

XX

2AA

SA

00

55

00

01

A0

Volatile Sector

Protection

(DYB)

DYB Clear

A0

SA

DYB Status Read

RD(0)

90

Command Set Exit (7)

XX

00

Legend

X = Don’t care.

RA = Address of the memory location to be read.

SA = Sector Address. Any address that falls within a specified sector. See Table 8.2 on page 14 and Table 8.3 on page 20 for sector address ranges.

PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity.

PWD = Password Data.

RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0. If unprotected, DQ0 = 1.

Notes

1. All values are in hexadecimal.

2. Shaded cells indicate read cycles.

3. Address and data bits not specified in table, legend, or notes are don’t cares (each hex digit implies 4 bits of data).

4. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset

command to return the device to reading array data.

5. Entry commands are required to enter a specific mode to enable instructions only available within that mode.

6. No unlock or command cycles required when bank is reading array data.

7. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state.

8. Entire two bus-cycle sequence must be entered for each portion of the password.

9. Full address range is required for reading password.

10. Password may be unlocked or read in any order. Unlocking requires the full password (all seven cycles).

11. ACC must be at V when setting PPB or DYB.

IH

12. “All PPB Erase” command pre-programs all PPBs before erasure to prevent over-erasure.

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Table 11.3 Memory Array Commands (x8)

Bus Cycles (Notes 1–5)

Third Fourth

Addr Addr

First

Addr

Second

Fifth

Addr

Sixth

Addr

Command Sequence

(Notes)

Data

RD

F0

Addr

Data

Asynchronous Read (6)

Reset (7)

1

4

6

4

1

4

6

1

3

2

6

1

3

4

1

4

RA

XXX

AAA

AA

Manufacturer ID

AA

98

555

55

AAA

90

X00

X02

01

Device ID (8)

XX7E

Data

X1C

Data

X1E

Data

Sector Protect Verify (9)

Secure Device Verify (10)

[SA]X04

X06

CFI Query (11)

Program

AAA

SA

AA

29

555

55

AAA

PA

A0

25

PA

SA

PD

Write to Buffer (12)

Program Buffer to Flash

Write to Buffer Abort Reset (13)

Entry

WC

PA

PD

WBL

PD

AAA

XXX

AAA

XXX

AAA

00

AA

A0

80

PA

555

PA

55

PD

30

10

00

55

555

F0

20

AAA

Program (14)

Sector Erase (14)

Chip Erase (14)

Reset

SA

80

SA

90

XXX

555

Chip Erase

AA

B0

30

AAA

80

AAA

AA

555

55

AAA

SA

10

30

Sector Erase

Erase/Program Suspend (15)

Erase/Program Resume (16)

Entry

AA

Data

AA

555

55

AAA

88

A0

Program (17)

PA

PD

00

Read (17)

Exit (17)

AAA

555

55

AAA

90

XXX

Legend

X = Don’t care.

RA = Read Address.

RD = Read Data.

PA = Program Address. Addresses latch on the falling edge of WE# or CE# pulse, whichever occurs later.

PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first.

SA = Sector Address. Any address that falls within a specified sector. See Table 8.2 on page 14 and Table 8.3 on page 20 for sector address ranges.

WBL = Write Buffer Location. Address must be within the same write buffer page as PA.

WC = Word Count. Number of write buffer locations to load minus 1.

Notes

1. See Table 8.1 on page 11 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells indicate read cycles.

4. Address and data bits not specified in table, legend, or notes are don’t cares (each hex digit implies 4 bits of data).

5. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset

command to return reading array data.

6. No unlock or command cycles required when bank is reading array data.

7. Reset command is required to return to reading array data in certain cases. See Reset Command on page 34 for details.

8. Data in cycles 5 and 6 are listed in Table 8.4 on page 23.

9. The data is 00h for an unprotected sector and 01h for a protected sector. PPB Status Read provides the same data but in inverted form.

10. If DQ7 = 1, region is factory serialized and protected. If DQ7 = 0, region is unserialized and unprotected when shipped from factory. See Secured Silicon Sector

Flash Memory Region on page 29 for more information.

11. Command is valid when device is ready to read array data or when device is in autoselect mode.

12. Total number of cycles in the command sequence is determined by the number of words written to the write buffer.

13. Command sequence resets device for next command after write-to-buffer operation.

14. Requires Entry command sequence prior to execution. Unlock Bypass Reset command is required to return to reading array data.

15. System may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid

only during a sector erase operation.

16. Erase Resume command is valid only during the Erase Suspend mode.

17. Requires Entry command sequence prior to execution. Secured Silicon Sector Exit Reset command is required to exit this mode; device may otherwise be

placed in an unknown state.

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Table 11.4 Sector Protection Commands (x8)

Bus Cycles (Notes 1–4)

3rd/10th 4th/11th

1st/8th

2nd/9th

5th

6th

7th

Command Sequence

(Notes)

Addr Data Addr

Data

55

Addr

Data Addr Data Addr Data Addr Data Addr Data

Command Set Entry (5)

3

2

1

2

3

2

AAA

XXX

00

AA

A0

555

AAA

40

Lock

Register

Bits

Program (6)

XXX

Data

Read (6)

Data

90

Command Set Exit (7)

Command Set Entry (5)

Program (8)

XXX

AAA

XXX

555

00

55

AA

A0

AAA

02

60

PWAx PWDx

PWD

0

PWD

2

PWD

3

PWD

4

PWD

5

PWD

6

00

07

00

05

01

PWD1

03

04

02

05

03

06

04

Read (9)

8

PWD

7

Password

Protection

PWD

0

PWD

1

PWD

2

PWD

3

PWD

4

25

00

06

03

00

07

01

00

1

Unlock (10)

PWD

5

PWD

7

PWD6

29

Command Set Exit (7)

Command Set Entry (5)

PPB Program (11)

2

3

2

1

2

3

2

XX

90

AA

XX

555

SA

00

55

00

30

AAA

XXX

SA

AAA

C0

A0

Non-Volatile

Sector

Protection

(PPB)

All PPB Erase (11, 12)

PPB Status Read

80

RD(0)

90

Command Set Exit (7)

Command Set Entry (5)

PPB Lock Bit Set

XXX

AAA

XXX

555

00

55

00

AA

AAA

50

E0

Global

Volatile

Sector

Protection

Freeze

(PPB Lock)

A0

XXX

PPB Lock Bit Status

Read

1

XXX RD(0)

Command Set Exit (7)

Command Set Entry (5)

DYB Set

2

3

2

1

2

XXX

AAA

XXX

SA

90

AA

XX

555

SA

00

55

00

01

A0

Volatile

Sector

Protection

(DYB)

DYB Clear

A0

DYB Status Read

Command Set Exit (7)

RD(0)

90

XXX

00

Legend

X = Don’t care.

RA = Address of the memory location to be read.

SA = Sector Address. Any address that falls within a specified sector. See Table 8.2 on page 14 and Table 8.3 on page 20 for sector address ranges.

PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity.

PWD = Password Data.

RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0. If unprotected, DQ0 = 1.

Notes

1. All values are in hexadecimal.

2. Shaded cells indicate read cycles.

3. Address and data bits not specified in table, legend, or notes are don’t cares (each hex digit implies 4 bits of data).

4. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset

command to return the device to reading array data.

5. Entry commands are required to enter a specific mode to enable instructions only available within that mode.

6. No unlock or command cycles required when bank is reading array data.

7. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state.

8. Entire two bus-cycle sequence must be entered for each portion of the password.

9. Full address range is required for reading password.

10. Password may be unlocked or read in any order. Unlocking requires the full password (all seven cycles).

11. ACC must be at V when setting PPB or DYB.

IH

12. “All PPB Erase” command pre-programs all PPBs before erasure to prevent over-erasure.

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D a t a S h e e t

12. Write Operation Status

The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5,

DQ6, and DQ7. Table 12.1 on page 55 and the following subsections describe the function of these bits. DQ7

and DQ6 each offer a method for determining whether a program or erase operation is complete or in

progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an

Embedded Program or Erase operation is in progress or is completed.

12.1 DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm

is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising

edge of the final WE# pulse in the command sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum

programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the

Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system

must provide the program address to read valid status information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the read

mode.

During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7.

The system must provide an address within any of the sectors selected for erasure to read valid status

information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the

selected sectors that are protected. However, if the system reads DQ7 at an address within a protected

sector, the status may not be valid.

Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing

status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid

data, the data outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 appears on successive read

cycles.

Table 12.1 on page 55 shows the outputs for Data# Polling on DQ7. Figure 12.1 on page 51 shows the

Data# Polling algorithm. Figure 18.4 on page 63 shows the Data# Polling timing diagram.

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Figure 12.1 Data# Polling Algorithm

START

Read DQ15–DQ0

Addr = VA

Yes

DQ7 = Data?

No

DQ5 = 1

Yes

Read DQ15–DQ0

Addr = VA

Yes

DQ7 = Data?

No

PASS

FAIL

Notes

1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being

erased. During chip erase, a valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.

12.2 RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in

the erase-suspend-read mode. Table 12.1 on page 55 shows the outputs for RY/BY#.

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12.3 DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase

operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for

approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are

protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use

DQ7 (see DQ7: Data# Polling on page 50).

If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program

algorithm is complete.

Table 12.1 on page 55 shows the outputs for Toggle Bit I on DQ6. Figure 12.2 on page 53 shows the toggle

bit algorithm. Figure 18.8 on page 65 shows the toggle bit timing diagrams. Figure 18.9 on page 65 shows

the differences between DQ2 and DQ6 in graphical form. See also DQ2: Toggle Bit II on page 54.

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Figure 12.2 Toggle Bit Algorithm

START

Read DQ7–DQ0

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Program/Erase

Operation Complete

Complete, Write

Reset Command

Note

The system should recheck the toggle bit even if DQ5 = 1 because the toggle bit may stop toggling as DQ5 changes to 1. See DQ6: Toggle

Bit I on page 52 and DQ2: Toggle Bit II on page 54 for more information.

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D a t a S h e e t

12.4 DQ2: Toggle Bit II

The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that

is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is

valid after the rising edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure.

(The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the

sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is

actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,

both status bits are required for sector and mode information. Refer to Table 12.1 on page 55 to compare

outputs for DQ2 and DQ6.

Figure 12.2 on page 53 shows the toggle bit algorithm in flowchart form, and the section DQ2: Toggle Bit II

explains the algorithm. See also RY/BY#: Ready/Busy# on page 51. Figure 18.8 on page 65 shows the

toggle bit timing diagram. Figure 18.9 on page 65 shows the differences between DQ2 and DQ6 in graphical

form.

12.5 Reading Toggle Bits DQ6/DQ2

Refer to Figure 12.2 on page 53 and Figure 18.9 on page 65 for the following discussion. Whenever the

system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine

whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the

first read. After the second read, the system would compare the new value of the toggle bit with the first. If the

toggle bit is not toggling, the device has completed the program or erase operation. The system can read

array data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is high (see DQ5: Exceeded Timing Limits on page 54). If

it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have

stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully

completed the program or erase operation. If it is still toggling, the device did not completed the operation

successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous paragraph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the beginning of the algorithm when it returns to

determine the status of the operation (top of Figure 12.2 on page 53).

12.6 DQ5: Exceeded Timing Limits

DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse

count limit. Under these conditions DQ5 produces a 1, indicating that the program or erase cycle was not

successfully completed.

The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously

programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device

halts the operation, and when the timing limit is exceeded, DQ5 produces a 1.

In all these cases, the system must write the reset command to return the device to the reading the array (or

to erase-suspend-read if the device was previously in the erase-suspend-program mode).

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12.7 DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors

are selected for erasure, the entire time-out also applies after each additional sector erase command. When

the time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase

commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See

also Sector Erase Command Sequence on page 41.

After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is

1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until

the erase operation is complete. If DQ3 is 0, the device accepts additional sector erase commands. To

ensure the command is accepted, the system software should check the status of DQ3 prior to and following

each subsequent sector erase command. If DQ3 is high on the second status check, the last command might

not have been accepted.

Table 12.1 on page 55 shows the status of DQ3 relative to the other status bits.

12.8 DQ1: Write-to-Buffer Abort

DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a 1.

The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading

array data. See Write Buffer on page 12 for more details.

Table 12.1 Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

DQ1

0

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Program-Suspended

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

N/A

Invalid (not allowed)

Data

1

0

Program

Suspend

Mode

Program-

Suspend

Read

Sector

Non-Program

Suspended Sector

Erase-Suspended

Sector

1

No toggle

Toggle

0

N/A

Toggle

N/A

Erase-

Suspend

Read

Erase

Suspend

Mode

Non-Erase Suspended

Sector

Data

Erase-Suspend-Program

(Embedded Program)

DQ7#

0

N/A

Busy (Note 3)

Abort (Note 4)

DQ7#

Toggle

0

N/A

0

1

0

Write-to-

Buffer

Notes

1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing

limits. Refer to DQ5: Exceeded Timing Limits on page 54 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate section for further details.

3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.

4. DQ1 switches to 1 when the device has aborted the write-to-buffer operation

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13. Absolute Maximum Ratings

Storage Temperature, Plastic Packages

Ambient Temperature with Power Applied

Voltage with Respect to Ground:

–65°C to +150°C

–65°C to +125°C

V

(Note 1)

–0.5 V to +4.0 V

–0.5 V to +12.5 V

CC

IO

A9, OE#, and ACC (Note 2)

All other pins (Note 1)

–0.5 V to V + 0.5V

CC

Output Short Circuit Current (Note 3)

200 mA

Notes

1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may overshoot V to –2.0 V for periods of up to

SS

20 ns. See Figure 13.1 on page 56. Maximum DC voltage on input or I/Os is V + 0.5 V. During voltage transitions, input or I/O pins may

CC

overshoot to V + 2.0 V for periods up to 20 ns. See Figure 13.2 on page 56.

CC

2. Minimum DC input voltage on pins A9, OE#, and ACC is –0.5 V. During voltage transitions, A9, OE#, and ACC may overshoot V to –

SS

2.0 V for periods of up to 20 ns. See Figure 13.1 on page 56. Maximum DC input voltage on pin A9, OE#, and ACC is +12.5 V which may

overshoot to +14.0V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not

implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 13.1 Maximum Negative Overshoot Waveform

20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

Figure 13.2 Maximum Positive Overshoot Waveform

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

2.0 V

20 ns

14. Operating Ranges

Industrial (I) Devices

Ambient Temperature (T_A)

–40°C to +85°C

Supply Voltages

V_CC

V_IO(Note 2)

+2.7 V to +3.6 V or +3.0 V to 3.6 V

+1.65 V to 1.95 V or V_CC

Notes

1. Operating ranges define those limits between which the functionality of the device is guaranteed.

2. See Product Selector Guide on page 6.

56

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15. DC Characteristics

15.1 CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

= V to V

Min

Typ

Max

WP/ACC: 2.0

Others: 1.0

35

Unit

V

,

CC

IN

SS

I

Input Load Current (Note 1)

µA

LI

= V

CC

CC max

I

A9 Input Load Current

Output Leakage Current

V

= V

; A9 = 12.5 V

µA

LIT

CC

CC max

V

= V to V

,

CC

OUT

SS

I

1.0

20

LO

= V

CC

CC max

CE# = V ; OE# = V , V = V

;

IL

IH

CC

CCmax

6

f = 1 MHz, Byte Mode

CE# = V ; OE# = V , V = V

IL

IH

CC

CCmax

30

50

I

V

Active Read Current (Note 1)

mA

CC1

CC

f = 5 MHz, Word Mode

CE# = V ; OE# = V , V = V

;

IL

IH

CC

CCmax

60

90

f = 10 MHz

CE# = V ; OE# = V

IL

V

= V

;

CCmax

IH, CC

1

5

10

20

90

f = 10 MHz

I

V

Intra-Page Read Current (Note 1)

Active Erase/Program Current

CC2

CC

CE# = V , OE# = V , V = V

;

IL

IH

CC

CCmax

f=33 MHz

CC

I

CE# = V OE# = V V = V

IH, CC

50

mA

µA

CC3

IL,

CCmax

(Note 2, 3)

V

= V

; V = V ; OE# = V

CCmax IO CC IH

;

CC

V

Standby Current

Reset Current

= V + 0.3 V / –0.1 V;

1

5

CC4

CC

IL

SS

CE#, RESET# = V

0.3 V

CC

V

= V

; V = V

;

CC

CCmax

IO

I

V

= V + 0.3 V / –0.1 V;

µA

CC5

CC6

ACC

IL

SS

RESET# = V

0.3 V

; V = V

SS

V

= V

;

CC

CCmax IO

V

= V

0.3 V;

IH

IL

CC

SS

Automatic Sleep Mode (Note 4)

1

5

= V + 0.3 V / –0.1 V;

WP#/A = V

CC

IH

WP#/

ACC pin

10

50

20

90

CE# = V OE# = V

V

= V

IL,

IH, CC CCmax,

I

ACC Accelerated Program Current

mA

WP#/ACC = V

IH

V

CC

V

Input Low Voltage (Note 5)

Input High Voltage (Note 5)

–0.1

0.3 x V

V

IL

IO

V

0.7 x V

11.5

V

+ 0.3

IO

IH

IO

Voltage for ACC Erase/Program

Acceleration

V

= 2.7–3.6 V

12.5

V

HH

CC

Voltage for Autoselect and Temporary

Sector Unprotect

V

= 2.7–3.6 V

11.5

V

ID

OL

OH

CC

Output Low Voltage (Note 5)

Output High Voltage (Note 5)

I

= 100 µA

= -100 µA

0.15 x V

OL

IO

0.85 x

V

OH

V

IO

V

Low V Lock-Out Voltage (Note 3)

2.3

2.5

LKO

CC

Notes

1. The I current listed is typically less than 2 mA/MHz, with OE# at V

.

IH

CC

2.

I

active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.

CC

3. Not 100% tested.

4. Automatic sleep mode enables the lower power mode when addresses remain stable tor t

+ 30 ns.

ACC

5.

6.

V

= 1.65–1.95 V or 2.7–3.6 V

IO

= 3 V and V = 3V or 1.8V. When V is at 1.8V, I/O pins cannot operate at 3V.

CC

IO

May 1, 2006 S29GL-N_01_A0

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16. Test Conditions

Table 16.1 Test Specifications

Test Condition

All Speeds

1 TTL gate

Unit

Output Load

Output Load Capacitance, C

(including jig capacitance)

L

30

pF

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

0.0–V

IO

Input timing measurement reference levels (See Note)

Output timing measurement reference levels

Note

0.5V

V

IO

0.5 V

V

IO

If V < V , the reference level is 0.5 V

.

IO

CC

IO

Figure 16.1 Test Setup

3.3 V

2.7 kΩ

Device

Under

Test

C

6.2 kΩ

L

Note

Diodes are IN3064 or equivalent

17. Key to Switching Waveforms

Waveform

Inputs

Outputs

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

Figure 17.1 Input Waveforms and Measurement Levels

0.5 V_IO

V_IO

0.0 V

0.5 V_IO

V

Input

Measurement Level

Output

Note

If V < V , the input measurement reference level is 0.5 V .

IO

CC

IO

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18. AC Characteristics

18.1 Read-Only Operations

Speed

Parameter

Options

JEDEC

Std.

Description

Test Setup

= V = 3 V

110

Unit

V

110

IO

CC

t

Read Cycle Time

Min

Max

ns

AVAV

RC

V

= 1.8 V, V = 3 V

CC

IO

V

= V = 3 V

CC

IO

t

Address to Output Delay (Note 2)

ns

AVQV

ELQV

ACC

= 1.8 V, V = 3 V

CC

V

= V = 3 V

CC

IO

t

Chip Enable to Output Delay (Note 3)

CE

= 1.8 V, V = 3 V

110

30

CC

t

Page Access Time

Max

25

35

ns

PACC

t

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

35

GLQV

EHQZ

GHQZ

OE

t

20

DF

t

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First

t

Min

0

ns

AXQX

OH

Read

Output Enable Hold Time

t

OEH

Toggle and Data#

(Note 1)

10

35

Polling

t

Chip Enable Hold Time

Read

CEH

Notes

1. Not 100% tested.

2. CE#, OE# = V

IL

3. OE# = V

IL

4. See Figure 16.1 on page 58 and Table 16.1 on page 58 for test specifications.

5. Unless otherwise indicated, AC specifications for 110 ns speed options are tested with V = V = 3 V or V = 1.8 V and V = 3.0 V.

IO

CC

IO

CC

Figure 18.1 Read Operation Timings

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_CEH

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

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D a t a S h e e t

Figure 18.2 Page Read Timings

Same Page

Amax-A2

A2-A0*

Ad

Aa

t_ACC

Ab

t_PACC

Ac

t_PACC

Data Bus

Qa

Qb

Qc

Qd

CE#

OE#

Note

* Figure shows word mode. Addresses are A2–A-1 for byte mode.

18.2 Hardware Reset (RESET#)

Parameter

JEDEC Std.

Description

Speed (Note 2)

Unit

RESET# Pin Low (During Embedded Algorithms) to Read Mode

(Note 1, 2)

t

Max

20

ns

Ready

RESET# Pin Low (NOT During Embedded Algorithms) to Read

Mode (Note 1, 2)

t

500

ns

t

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

RP

t

Reset High Time Before Read ((Note 1, 2)

RESET# Low to Standby Mode

RY/BY# Recovery Time

RH

t

RPD

t

RB

Notes

1. Not 100% tested. If ramp rate is equal to or faster than 1V/100µs with a falling edge of the RESET# pin initiated, the RESET# pin needs

to be held low only for 100µs for power-up.

2. Next generation devices may have different reset speeds. To increase system design considerations, please refer to Advance Information

on S29GL-P Hardware Reset (RESET#) and Power-up Sequence on page 70 for advance reset speeds on S29GL---P devices.

60

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Figure 18.3 Reset Timings

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

t_RH

May 1, 2006 S29GL-N_01_A0

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D a t a S h e e t

18.3 Erase and Program Operations

Parameter

Speed Option

JEDEC

Std.

Description

110

0

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Min

Typ

AVAV

WC

t

ns

AVWL

AS

t

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

45

0

ns

ASO

t

ns

WLAX

AH

t

Address Hold Time From CE# or OE# high during toggle bit polling

Data Setup Time

ns

AHT

t

45

0

ns

DVWH

DS

t

Data Hold Time

ns

WHDX

DH

t

CE# High during toggle bit polling

Output Enable High during toggle bit polling

Read Recovery Time Before Write (OE# High to WE# Low)

CE# Setup Time

20

0

CEPH

OEPH

GHWL

t

ns

µs

t

GHWL

t

0

ELWL

WHEH

WLWH

CS

CH

WP

t

CE# Hold Time

0

t

Write Pulse Width

35

30

240

15

t

Write Pulse Width High

WHDL

WPH

Write Buffer Program Operation (Notes 2, 3)

Effective Write Buffer Program Operation (Notes 2, 4) Per Word

Accelerated Effective Write Buffer Program Operation

(Notes 2, 4)

t

Per Word

Typ

13.5

µs

WHWH1

WHWH2

WHWH1

Program Operation (Note 2)

Word

Typ

Min

Max

60

54

µs

Accelerated Programming Operation (Note 2)

Sector Erase Operation (Note 2)

0.5

250

50

sec

ns

WHWH2

t

V

Rise and Fall Time (Note 1)

Setup Time (Note 1)

VHH

HH

CC

t

µs

VCS

t

Erase/Program Valid to RY/BY# Delay

90

ns

BUSY

Notes

1. Not 100% tested.

2. See the Erase And Programming Performance on page 68 for more information.

3. For 1–16 words/1–32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

5. Unless otherwise indicated, AC specifications for 110 ns speed option are tested with V = V = 3 V or

IO

CC

with V = 1.8 V and V = 3.0 V.

IO

CC

62

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Figure 18.4 Program Operation Timings

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes

1. PA = program address, PD = program data, D

is the true data at the program address.

OUT

2. Illustration shows device in word mode.

Figure 18.5 Accelerated Program Timing Diagram

V_HH

V_ILor V_IH

ACC

t_VHH

Notes

1. Not 100% tested.

2. CE#, OE# = V

IL

3. OE# = V

IL

4. See Figure 16.1 on page 58 and Table 16.1 on page 58 for test specifications.

May 1, 2006 S29GL-N_01_A0

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D a t a S h e e t

Figure 18.6 Chip/Sector Erase Operation Timings

Erase Command Sequence (last two cycles)

Read Status Data

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (seeWrite Operation Status on page 50.)

2. These waveforms are for the word mode.

Figure 18.7 Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

High Z

DQ6–DQ0

Status Data

True

Valid Data

Status Data

t_BUSY

RY/BY#

Notes

1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

2. for data polling is 45 ns when V = 1.65 to 2.7 V and is 35 ns when V = 2.7 to 3.6 V.

t

OE

IO

64

S29GL-N

S29GL-N_01_A0 May 1, 2006

D a t a S h e e t

Figure 18.8 Toggle Bit Timings (During Embedded Algorithms)

t_AHT

t_AS

Addresses

CE#

t_AHT

t_ASO

t_CEPH

t_OEH

WE#

OE#

t_OEPH

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ2 and DQ6

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note

A = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array

data read cycle.

Figure 18.9 DQ2 vs. DQ6

Enter

Erase

Suspend

Enter Erase

Suspend Program

Embedded

Erasing

Erase

Resume

Erase

Erase Suspend

Read

Erase

WE#

Erase

Erase Suspend

Suspend

Program

Complete

Read

DQ6

DQ2

Note

DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.

May 1, 2006 S29GL-N_01_A0

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D a t a S h e e t

18.4 Alternate CE# Controlled Erase and Program Operations—S29GL128N,

S29GL256N

Parameter

JEDEC Std.

Speed Option

Description

110

0

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Min

AVAV

WC

t

ns

AVWL

AS

T

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

ns

ASO

t

45

ns

ELAX

AH

Address Hold Time From CE# or OE# high during toggle bit

polling

t

Min

0

ns

AHT

t

Data Setup Time

Min

Typ

45

0

ns

µs

DVEH

EHDX

DS

t

Data Hold Time

DH

t

CE# High during toggle bit polling

OE# High during toggle bit polling

Read Recovery Time Before Write (OE# High to WE# Low)

WE# Setup Time

20

0

CEPH

OEPH

t

GHEL

t

0

WLEL

WS

WH

t

WE# Hold Time

0

EHWH

t

CE# Pulse Width

35

30

240

ELEH

CP

t

CE# Pulse Width High

EHEL

CPH

Write Buffer Program Operation (Notes 2, 3)

Effective Write Buffer Program Operation

(Notes 2, 4)

Per Word

Typ

15

µs

Effective Accelerated Write Buffer Program

Per Word

t

Typ

13.5

60

µs

WHWH1

WHWH2

Operation (Notes 2, 4)

Program Operation (Note 2)

Word

Accelerated Programming Operation

(Note 2)

54

µs

Sector Erase Operation (Note 2)

0.5

sec

WHWH2

Notes

1. Not 100% tested.

2. See AC Characteristics on page 59 for more information.

3. For 1–16 words/1–32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

5. Unless otherwise indicated, AC specifications for 110 ns speed option are tested with V = V = 3 V;

IO

CC

or with V = 1.8 V and V = 3.0 V.

IO

CC

66

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S29GL-N_01_A0 May 1, 2006

D a t a S h e e t

Figure 18.10 Alternate CE# Controlled Write (Erase/Program) Operation Timings

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D

4. Waveforms are for the word mode.

is the data written to the device.

OUT

May 1, 2006 S29GL-N_01_A0

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67

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19. Erase And Programming Performance

Typ

Max

Parameter

(Note 1)

(Note 2)

Unit

Comments

Sector Erase Time

Chip Erase Time

0.5

64

3.5

256

512

sec

Excludes 00h programming

prior to erasure (Note 5)

S29GL128N

sec

µs

S29GL256N

128

Total Write Buffer

Programming Time

(Note 3)

240

200

Total Accelerated Effective

Write Buffer Programming

Time (Note 3)

Excludes system level

overhead (Note 6)

µs

S29GL128N

S29GL256N

123

246

Chip Program Time

sec

Notes

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 10,000 cycles, checkerboard pattern.

CC

2. Under worst case conditions of 90°C, V = 3.0 V, 100,000 cycles.

CC

3. Effective write buffer specification is based upon a 16-word write buffer operation.

4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program

faster than the maximum program times listed.

5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.

6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 11.1

on page 46 and Table 11.3 on page 48 for further information on command definitions.

20. BGA Package Capacitance

Parameter Symbol

Parameter Description

Test Setup

Typ

4.2

5.4

3.9

Max

5.0

6.5

4.7

Unit

pF

C

Input Capacitance

Output Capacitance

Control Pin Capacitance

V

= 0

IN

BGA

IN

C

V

= 0

pF

OUT

C

V

= 0

IN

pF

IN2

Notes

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

68

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21. Physical Dimensions

21.1 FAA064—64-Ball Fortified Ball Grid Array (FBGA)

D1

A

D

H

G

F

E

D

C

B

A

8

7

6

5

4

e

SE

E1

E

3

2

1

φ0.50

+0.20

-0.50

B

1.00

A1 CORNER

A1 ID.

7

6

φb

SD

φ0.08

φ0.15

M

C

C A B

TOP VIEW

BOTTOM VIEW

0.20 C

0.08 C

A2

A

A1

C

SEATING PLANE

SIDE VIEW

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M-1994.

PACKAGE

JEDEC

FAA 064

N/A

10.00 mm x 13.00 mm

PACKAGE

2. ALL DIMENSIONS ARE IN MILLIMETERS.

NOTE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

4. REPRESENTS THE SOLDER BALL GRID PITCH.

SYMBOL

MIN.

NOM.

MAX.

e

A

A1

A2

D

---

1.20

---

OVERALL THICKNESS

BALL HEIGHT

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D"

DIRECTION.

0.30

0.64

---

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

0.78

BODY THICKNESS

BODY SIZE

13.00 BSC.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

10.00 BSC.

7.00 BSC.

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM Z.

D1

E1

MD

BALL FOOTPRINT

7.00 BSC.

8

BALL FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

ROW MATRIX SIZE D DIRECTION

ME

N

8

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

BALL DIAMETER

64

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

b

0.40

0.45

0.50

e

1.00 BSC

0.50 BSC

BALL PITCH

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

SOLDER BALL PLACEMENT

SD / SE

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

9

FOR PACKAGE THICKNESS, "A" IS THE CONTROLLING

DIMENSION.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, INK MARK,

METALLIZED MARKINGS INDENTION OR OTHER MEANS.

3174\38.9G

May 1, 2006 S29GL-N_01_A0

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69

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22. Advance Information on S29GL-P Hardware Reset (RESET#)

and Power-up Sequence

Table 22.1 Hardware Reset (RESET#)

Parameter

JEDEC

Std.

Description

Speed

Unit

RESET# Pin Low (During Embedded Algorithms) to

Read Mode or Write mode

t

Min

35

µs

Ready

RESET# Pin Low (NOT During Embedded Algorithms)

to Read Mode or Write mode

35

µs

Ready

t

RESET# Pulse Width

Min

35

200

10

0

µs

ns

µs

ns

RP

t

Reset High Time Before Read

RESET# Low to Standby Mode

RY/BY# Recovery Time

RH

t

RPD

t

RB

Note

CE#, OE# and WE# must be at logic high during Reset Time.

Figure 22.1 Reset Timings

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

t_RH

70

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Table 22.2 Power-Up Sequence Timings

Parameter

Description

Speed

Unit

Reset Low Time from Rising Edge of V (or last Reset pulse) to Rising

CC

Edge of RESET#

t

Min

35

µs

VCS

Reset Low Time from Rising Edge of V (or last Reset pulse) to Rising

IO

Edge of RESET#

t

Min

35

µs

ns

VIOS

t

Reset High Time Before Read

Max

200

RH

Notes

1.

V

< V + 200 mV.

CC

IO

2.

V

and V ramp must be in sync during power up. If RESET# is not stable for 35 µs, the following conditions may occur: the device

IO

CC

does not permit any read and write operations, valid read operations return FFh, and a hardware reset is required.

3. Maximum V power up current is 20 mA (RESET# =V ).

CC

IL

Figure 22.2 Power-On Reset Timings

Vcc_min

Vio_min

V_CC

V_IO

t_RH

CE#

t_VIOS

t_VCS

RESET#

May 1, 2006 S29GL-N_01_A0

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71

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23. Revision Summary

23.1 Revision A (May 1, 2006)

Initial Release.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as

contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to

you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal

operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under

the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,

the prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under

development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this

document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular

purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no

liability for any damages of any kind arising out of the use of the information in this document.

trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.

72

S29GL-N

S29GL-N_01_A0 May 1, 2006


型号：	S29GL256N11FFIIH2
厂家：	SPANSION
描述：	Flash, 32MX16, 110ns, PBGA64, 10 X 13 MM, 1 MM PITCH, LEAD FREE, FBGA-64
文件：	总74页 (文件大小：1593K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S29GL256N11FFIIH2 [SPANSION]

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