S29GL512N10FFI13 [SPANSION]
Flash, 32MX16, 100ns, PBGA64, 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-64;
| 型号： | S29GL512N10FFI13 |
| 厂家： | 
SPANSION |
| 描述： | Flash, 32MX16, 100ns, PBGA64, 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-64 |
| 文件： | 总103页 (文件大小：2751K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S29GLxxxN MirrorBitTM Flash Family
S29GL512N, S29GL256N, S29GL128N
512 Megabit, 256 Megabit, and 128 Megabit,
3.0 Volt-only Page Mode Flash Memory featuring
110 nm MirrorBit process technology
ADVANCE
INFORMATION
Datasheet
Distinctive Characteristics
Architectural Advantages
Software & Hardware Features
Single power supply operation
— 3 volt read, erase, and program operations
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
Enhanced VersatileI/O™ control
— All input levels (address, control, and DQ input levels)
and outputs are determined by voltage on V input.
IO
V
range is 1.65 to V
CC
IO
Manufactured on 110 nm MirrorBit process
technology
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
SecSi™ (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
Hardware features
— Advanced Sector Protection
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
— May be programmed and locked at the factory or by
the customer
Flexible sector architecture
— S29GL512N: Five hundred twelve 64 Kword (128
Kbyte) sectors
— S29GL256N: Two hundred fifty-six 64 Kword (128
Kbyte) sectors
— S29GL128N: One hundred twenty-eight 64 Kword
(128 Kbyte) sectors
Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
100,000 erase cycles per sector typical
20-year data retention typical
Performance Characteristics
High performance
— 90 ns access time (S29GL128N, S29GL256N,
S29GL512N)
— 8-word/16-byte page read buffer
— 25 ns page read times
— 16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
Low power consumption (typical values at 3.0 V, 5
MHz)
— 25 mA typical active read current;
— 50 mA typical erase/program current
— 1 µA typical standby mode current
Package options
— 56-pin TSOP
— 64-ball Fortified BGA
Publication Number 27631 Revision A Amendment 5 Issue Date September 29, 2004
This document contains information on a product under development at Spansion LLC. The information is intended to help you evaluate this product. Spansion LLC
reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e I n f o r m a t i o n
General Description
The S29GL512/256/128N family of devices are 3.0V single power flash memory
manufactured using 110 nm MirrorBit technology. The S29GL512N is a 512 Mbit,
organized as 33,554,432 words or 67,108,864 bytes. The S29GL256N is a 256
Mbit, organized as 16,777,216 words or 33,554,432 bytes. The S29GL128N is a
128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The devices have
a 16-bit wide data bus that can also function as an 8-bit wide data bus by using
the BYTE# input. The device can be programmed either in the host system or in
standard EPROM programmers.
Access times as fast as 90 ns (S29GL128N, S29GL256N, S29GL512N) are avail-
able. Note that each access time has a specific operating voltage range (V ) and
CC
an I/O voltage range (V ), as specified in the “Product Selector Guide” and the
IO
“Ordering Information” sections. The devices are offered in a 56-pin TSOP or 64-
ball Fortified BGA package. Each device has separate chip enable (CE#), write en-
able (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and
write functions. In addition to a V input, a high-voltage accelerated program
CC
(WP#/ACC) input provides shorter programming times through increased cur-
rent. This feature is intended to facilitate factory throughput during system
production, but may also be used in the field if desired.
The devices are entirely command set compatible with the JEDEC single-
power-supply Flash standard. Commands are written to the device using
standard microprocessor write timing. Write cycles also internally latch addresses
and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#
(RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead
by requiring only two write cycles to program data instead of four.
The Enhanced VersatileI/O™ (V ) control allows the host system to set the
IO
voltage levels that the device generates and tolerates on all input levels (address,
chip control, and DQ input levels) to the same voltage level that is asserted on
the V pin. This allows the device to operate in a 1.8 V or 3 V system environ-
IO
ment as required.
Hardware data protection measures include a low V detector that automat-
CC
ically inhibits write operations during power transitions. Persistent Sector
Protection provides in-system, command-enabled protection of any combina-
tion of sectors using a single power supply at V . Password Sector Protection
CC
prevents unauthorized write and erase operations in any combination of sectors
through a user-defined 64-bit password.
The Erase Suspend/Erase Resume feature allows the host system to pause an
erase operation in a given sector to read or program any other sector and then
complete the erase operation. The Program Suspend/Program Resume fea-
ture enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program operation.
2
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
The hardware RESET# pin terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would thus also reset the device,
enabling the host system to read boot-up firmware from the Flash memory
device.
The device reduces power consumption in the standby mode when it detects
specific voltage levels on CE# and RESET#, or when addresses have been stable
for a specified period of time.
The SecSi™ (Secured Silicon) Sector provides a 128-word/256-byte area for
code or data that can be permanently protected. Once this sector is protected,
no further changes within the sector can occur.
The Write Protect (WP#/ACC) feature protects the first or last sector by as-
serting a logic low on the WP# pin.
MirrorBit flash technology combines years of Flash memory manufacturing expe-
rience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via hot-hole
assisted erase. The data is programmed using hot electron injection.
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
3
A d v a n c e I n f o r m a t i o n
Table of Contents
Table 9. System Interface String.......................................... 53
Table 10. Device Geometry Definition................................... 54
Table 11. Primary Vendor-Specific Extended Query ................ 55
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6
S29GL512N ..............................................................................................................6
S29GL256N .............................................................................................................6
S29GL128N ..............................................................................................................6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .8
Special Package Handling Instructions ............................................................9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
S29GL512N ......................................................................................................... 11
S29GL256N ........................................................................................................ 11
S29GL128N ........................................................................................................ 11
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 12
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 13
Table 1. Device Bus Operations ........................................... 13
Word/Byte Configuration .................................................................................13
VersatileIOTM (VIO) Control ..............................................................................13
Requirements for Reading Array Data ......................................................... 14
Page Mode Read .............................................................................................. 14
Writing Commands/Command Sequences ................................................. 14
Write Buffer ......................................................................................................15
Accelerated Program Operation ................................................................15
Autoselect Functions ......................................................................................15
Standby Mode ........................................................................................................15
Automatic Sleep Mode .......................................................................................15
RESET#: Hardware Reset Pin ......................................................................... 16
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 55
Reading Array Data ........................................................................................... 56
Reset Command ................................................................................................. 56
Autoselect Command Sequence ................................................................... 56
Enter SecSi Sector/Exit SecSi Sector Command Sequence ................... 57
Word Program Command Sequence .......................................................... 57
Unlock Bypass Command Sequence ........................................................58
Write Buffer Programming .........................................................................58
Accelerated Program .................................................................................... 59
Figure 1. Write Buffer Programming Operation....................... 60
Figure 2. Program Operation ............................................... 61
Program Suspend/Program Resume Command Sequence .....................61
Figure 3. Program Suspend/Program Resume........................ 62
Chip Erase Command Sequence ...................................................................62
Sector Erase Command Sequence ................................................................ 63
Figure 4. Erase Operation ................................................... 64
Erase Suspend/Erase Resume Commands ..................................................64
Lock Register Command Set Definitions .................................................... 65
Password Protection Command Set Definitions ...................................... 65
Non-Volatile Sector Protection Command Set Definitions .................. 67
Global Volatile Sector Protection Freeze Command Set ...................... 67
Volatile Sector Protection Command Set ..................................................68
SecSi Sector Entry Command .........................................................................68
SecSi Sector Exit Command ...........................................................................69
Command Definitions ........................................................................................70
Table 12. S29GL512N, S29GL256N, S29GL128N Command Defini-
tions, x16 .........................................................................70
Table 13. S29GL512N, S29GL256N, S29GL128N Command Defini-
tions, x8 ...........................................................................73
Write Operation Status ................................................................................... 76
Output Disable Mode ........................................................................................ 16
Table 2. Sector Address Table–S29GL512N ........................... 16
Table 3. Sector Address Table–S29GL256N ........................... 31
Table 4. Sector Address Table–S29GL128N ........................... 38
Autoselect Mode ................................................................................................ 42
Table 5. Autoselect Codes, (High Voltage Method) ................ 43
Sector Protection ................................................................................................43
Persistent Sector Protection .......................................................................43
Password Sector Protection ........................................................................43
WP# Hardware Protection .........................................................................43
Selecting a Sector Protection Mode .........................................................43
Advanced Sector Protection .......................................................................... 44
Lock Register ....................................................................................................... 44
Table 6. Lock Register ........................................................ 45
Persistent Sector Protection ...........................................................................45
Dynamic Protection Bit (DYB) ...................................................................45
Persistent Protection Bit (PPB) ................................................................. 46
Persistent Protection Bit Lock (PPB Lock Bit) ..................................... 46
Table 7. Sector Protection Schemes ..................................... 47
Persistent Protection Mode Lock Bit ...........................................................47
Password Sector Protection ........................................................................... 48
Password and Password Protection Mode Lock Bit ............................... 48
64-bit Password .................................................................................................. 49
Persistent Protection Bit Lock (PPB Lock Bit) .......................................... 49
SecSi (Secured Silicon) Sector Flash Memory Region ............................. 49
Write Protect (WP#) .........................................................................................51
Hardware Data Protection ...............................................................................51
Low VCC Write Inhibit .................................................................................51
Write Pulse “Glitch” Protection .................................................................51
Logical Inhibit ....................................................................................................51
Power-Up Write Inhibit .................................................................................51
DQ7: Data# Polling ........................................................................................... 76
Figure 5. Data# Polling Algorithm ........................................ 77
RY/BY#: Ready/Busy# ....................................................................................... 77
DQ6: Toggle Bit I ...............................................................................................78
Figure 6. Toggle Bit Algorithm ............................................. 79
DQ2: Toggle Bit II .............................................................................................. 79
Reading Toggle Bits DQ6/DQ2 .....................................................................80
DQ5: Exceeded Timing Limits ........................................................................80
DQ3: Sector Erase Timer ................................................................................80
DQ1: Write-to-Buffer Abort ............................................................................81
Table 14. Write Operation Status .........................................81
Figure 7. Maximum Negative Overshoot Waveform................. 82
Figure 8. Maximum Positive
Overshoot Waveform.......................................................... 82
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 82
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 83
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 9. Test Setup........................................................... 84
Table 15. Test Specifications ...............................................84
Key to Switching Waveforms . . . . . . . . . . . . . . . 84
Figure 10. Input Waveforms and
Measurement Levels........................................................... 84
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 85
Read-Only Operations–S29GL128N, S29GL256N, S29GL512N ...........85
Figure 11. Read Operation Timings....................................... 86
Figure 12. Page Read Timings.............................................. 86
Hardware Reset (RESET#) ..............................................................................87
Common Flash Memory Interface (CFI) . . . . . . 51
Table 8. CFI Query Identification String................................. 52
4
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Figure 13. Reset Timings..................................................... 87
Operation Timings.............................................................. 94
Erase And Programming Performance . . . . . . . . 95
TSOP Pin and BGA Package Capacitance . . . . . 95
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 96
TS056—56-Pin Standard Thin Small Outline Package (TSOP) .............96
LAA064—64-Ball Fortified Ball Grid Array (FBGA) ............................... 97
Advance Information on S29GLxxxP AC Character-
istics
Erase and Program Operations–S29GL128N,
S29GL256N, S29GL512N ..................................................................................88
Figure 14. Program Operation Timings .................................. 89
Figure 15. Accelerated Program Timing Diagram .................... 89
Figure 16. Chip/Sector Erase Operation Timings..................... 90
Figure 17. Data# Polling Timings
(During Embedded Algorithms)............................................ 91
Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 92
Figure 19. DQ2 vs. DQ6 ...................................................... 92
Alternate CE# Controlled Erase and Program Operations-
Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . 98
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 99
S29GL128N, S29GL256N, S29GL512N ..........................................................93
Figure 20. Alternate CE# Controlled Write (Erase/Program)
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
5
A d v a n c e I n f o r m a t i o n
Product Selector Guide
S29GL512N
Part Number
S29GL512N
V
V
V
= 2.7–3.6 V
= 1.65–1.95 V
= 3.0-3.6V
10
11
IO
IO
IO
V
V
= 2.7–3.6 V
CC
Speed Option
11
= 3.0-3.6V
90
90
90
25
25
CC
Max. Access Time (ns)
100
100
25
110
110
25
110
110
30
Max. CE# Access Time (ns)
Max. Page access time (ns)
Max. OE# Access Time (ns)
25
25
30
S29GL256N
Part Number
S29GL256N
V
V
V
= 2.7–3.6 V
10
11
IO
IO
IO
V
= 2.7–3.6 V
CC
Speed Option
= 1.65–1.95 V
11
V
= Regulated (3.0-3.6V)
= Regulated (3.0-3.6V)
90
90
90
25
25
CC
Max. Access Time (ns)
100
100
25
110
110
25
110
110
30
Max. CE# Access Time (ns)
Max. Page access time (ns)
Max. OE# Access Time (ns)
25
25
30
S29GL128N
Part Number
S29GL128N
V
V
V
= 2.7–3.6 V
10
11
IO
IO
IO
V
= 2.7–3.6 V
CC
Speed Option
= 1.65–1.95 V
11
V
= Regulated (3.0-3.6V)
= Regulated (3.0-3.6V)
90
90
90
25
25
CC
Max. Access Time (ns)
100
100
25
110
110
25
110
110
30
Max. CE# Access Time (ns)
Max. Page access time (ns)
Max. OE# Access Time (ns)
25
25
30
6
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Block Diagram
DQ15–DQ0 (A-1)
RY/BY#
V
V
CC
Sector Switches
SS
V
IO
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
WP#/ACC
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Data
Chip Enable
Output Enable
Logic
Latch
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
X-Decoder
A
**–A0
Max
** A
GL512N = A24, A
GL256N = A23, A GL128N = A22
Max
Max
Max
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
7
A d v a n c e I n f o r m a t i o n
Connection Diagrams
NC for S29GL128N
NC for S29GL256N
and S29GL128N
A23
A22
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
9
56 A24
55 NC
54 A16
53 BYTE#
52 VSS
51 DQ15/A-1
50 DQ7
49 DQ14
48 DQ6
47 DQ13
46 DQ5
45 DQ12
44 DQ4
43 VCC
42 DQ11
41 DQ3
40 DQ10
39 DQ2
38 DQ9
37 DQ1
36 DQ8
35 DQ0
34 OE#
33 VSS
56-Pin Standard TSOP
A8 10
A19 11
A20 12
WE# 13
RESET# 14
A21 15
WP#/ACC 16
RY/BY# 17
A18 18
A17 19
A7 20
A6 21
A5 22
A4 23
A3 24
A2 25
A1 26
32 CE#
31 A0
NC 27
30 NC
NC 28
29 VIO
8
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Connection Diagrams
64-ball Fortified BGA
Top View, Balls Facing Down
A8
NC
B8
C8
D8
E8
F8
G8
NC
H8
NC
A22
A231
VIO
VSS
A242
A7
B7
C7
D7
E7
F7
G7
H7
VSS
A13
A12
A14
A15
A16
BYTE# DQ15/A-1
A6
A9
B6
A8
C6
D6
E6
F6
G6
H6
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
VCC
WE# RESET#
A21
A19
DQ5
DQ12
DQ4
A4
B4
C4
D4
E4
F4
G4
H4
RY/BY# WP#/ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
A3
A7
B3
C3
A6
D3
A5
E3
F3
G3
H3
A17
DQ0
DQ8
DQ9
DQ1
A2
A3
B2
A4
C2
A2
D2
A1
E2
A0
F2
G2
H2
VSS
CE#
OE#
A1
NC
B1
NC
C1
NC
D1
NC
E1
F1
G1
NC
H1
NC
NC
VIO
Note:
1. Ball C8 is NC on S29GL128N
2. Ball F8 is NC on S29GL256N and S29GL128N
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(TSOP, BGA). The package and/or data integrity may be compromised if the pack-
age body is exposed to temperatures above 150°C for prolonged periods of time.
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
9
A d v a n c e I n f o r m a t i o n
PIN DESCRIPTION
A24–A0
=
=
=
=
=
25 Address inputs (512 Mb)
24 Address inputs (256 Mb)
23 Address inputs (128 Mb)
15 Data inputs/outputs
A23–A0
A22–A0
DQ14–DQ0
DQ15/A-1
DQ15 (Data input/output, word mode), A-1 (LSB
Address input, byte mode)
Chip Enable input
CE#
=
=
=
=
OE#
Output Enable input
WE#
Write Enable input
WP#/ACC
Hardware Write Protect input;
Acceleration input
RESET#
BYTE#
=
=
=
=
Hardware Reset Pin input
Selects 8-bit or 16-bit mode
Ready/Busy output
RY/BY#
V
CC
3.0 volt-only single power supply
(see Product Selector Guide for speed options and
voltage supply tolerances)
Output Buffer power
V
=
=
=
IO
V
Device Ground
SS
NC
Pin Not Connected Internally
10
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
LOGIC SYMBOL
S29GL512N
25
A24–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
V
IO
RY/BY#
BYTE#
S29GL256N
24
A23–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
V
IO
RY/BY#
BYTE#
S29GL128N
23
A22–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
V
IO
RY/BY#
BYTE#
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
11
A d v a n c e I n f o r m a t i o n
Ordering Information
The ordering part number is formed by a valid combination of the following:
S29GL512N
S29GL256N
S29GL128N
10
F
A
I
00
0
PACKING TYPE
0
2
3
=
=
=
Tray (standard; see note 1)
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER (V range, protection when WP# =V
)
IL
IO
= V = 2.7 to 3.6 V, highest address sector protected
CC
01
02
V1
=
=
=
V
V
V
IO
IO
IO
= V = 2.7 to 3.6 V, lowest address sector protected
CC
= 1.65 to 1.95 V, V = 2.7 to 3.6 V, highest address sector
CC
protected
= V = 1.65 to 1.95 V, V = 2.7 to 3.6 V, lowest address sector
IO
V2
CC
protected
R1
R2
=
=
V
= V = 3.0 to 3.6 V, highest address sector protected
CC
IO
IO
V
= V = 3.0 to 3.6 V, lowest address sector protected
CC
TEMPERATURE RANGE
I
=
Industrial (–40
°
C to +85°C)
PACKAGE MATERIALS SET
A
=
Standard
F
= Pb-free
PACKAGE TYPE
T
=
Thin Small Outline Package (TSOP) Standard Pinout
F
= Fortified Ball Grid Array, 1.0 mm pitch package
SPEED OPTION
90
10
11
=
=
=
90 ns (Note 4)
100 ns
110 ns
DEVICE NUMBER/DESCRIPTION
S29GL128N, S29GL256N, S29GL512N
3.0 Volt-only, 512 Megabit (32 M x 16-Bit/64 M x 8-Bit) Page-Mode Flash Memory
TM
Manufactured on 110 nm MirrorBit process technology
S29GL512N Valid Combinations
Package &
Package Description
128, 256, 512Mb
Speed (ns)
Model Number
Pack Type
Temperature
90
10, 11
11
R1, R2
01, 02
V1, V2
S29GL512N,
S29GL256N,
S29GL128N
TAI, TFI
FAI, FFI
TS056 (TSOP, Note 2);
0, 2, 3 (Note 1)
LAA064 (Fortified BGA, Note 3)
Notes:
1. Type 0 is standard. Specify other options as required.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading “S29” and packing type designator from ordering part number.
4. Contact the local sales representative for availability
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device.
Consult your local sales office to confirm availability of specific valid combinations and to
check on newly released combinations.
12
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
DQ8–DQ15
DQ0– BYTE# BYTE#
WE
#
WP#/
ACC
Addresses
(Note 1)
Operation
CE# OE#
RESET#
DQ7
= VIH
= VIL
Read
L
L
H
H
X
A
D
D
IN
OUT
OUT
(Note
3)
DQ8–DQ14
= High-Z,
Write (Program/Erase)
Accelerated Program
Standby
L
H
L
H
H
Note 2
A
(Note 3)
(Note 3)
IN
DQ15 = A-1
(Note
3)
L
H
X
L
V
A
HH
IN
V
V
CC
CC
X
H
X
High-Z High-Z
High-Z
0.3 V
0.3 V
Output Disable
Reset
L
H
X
H
X
H
L
X
X
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
Legend: L = Logic Low = V , H = Logic High = V , V = 11.5–12.5 V, V = 11.5–12.5V, X = Don’t Care, SA = Sector
IL
IH
ID
HH
Address, A = Address In, D = Data In, D = Data Out
IN
IN
OUT
Notes:
1. Addresses are AMax:A0 in word mode; A
:A-1 in byte mode. Sector addresses are A
:A16 in both modes.
Max
Max
2. If WP# = VIL, the first or last sector group remains protected. If WP# = VIH, the first or last sector will be
protected or unprotected as determined by the method described in “Write Protect (WP#)”. All sectors are
unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version
ordered.)
3. D or D
as required by command sequence, data polling, or sector protect algorithm (see Figure 2, Figure 4, and
OUT
IN
Figure 5).
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only
data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/
O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
VersatileIOTM (V ) Control
IO
TM
The VersatileIO (VIO) control allows the host system to set the voltage levels
that the device generates and tolerates on CE# and DQ I/Os to the same voltage
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
13
A d v a n c e I n f o r m a t i o n
level that is asserted on VIO. See Ordering Information for VIO options on this
device.
For example, a VI/O of 1.65–3.6 volts allows for I/O at the 1.8 or 3 volt levels,
driving and receiving signals to and from other 1.8 or 3 V devices on the same
data bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE#
pins to VIL. CE# is the power control and selects the device. OE# is the output
control and gates array data to the output pins. WE# should remain at VIH
.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read-Only Op-
erations table for timing specifications and to Figure 11 for the timing diagram.
Refer to the DC Characteristics table for the active current specification on read-
ing array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. The page size of the device is 8 words/16 bytes.
The appropriate page is selected by the higher address bits A(max)–A3. Address
bits A2–A0 in word mode (A2–A-1 in byte mode) determine the specific word
within a page. This is an asynchronous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page
read accesses (as long as the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is de-asserted and reasserted
for a subsequent access, the access time is tACC or tCE. Fast page mode accesses
are obtained by keeping the “read-page addresses” constant and changing the
“intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH
.
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The “Word Program Command
Sequence” section has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 2, Table 4, and Table 5 indicate the address space that each sector occupies.
14
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Refer to the DC Characteristics table for the active current specification for the
write mode. The AC Characteristics section contains timing specification tables
and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32
bytes in one programming operation. This results in faster effective programming
time than the standard programming algorithms. See “Write Buffer” for more
information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
is one of two functions provided by the WP#/ACC pin. This function is primarily
intended to allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the afore-
mentioned Unlock Bypass mode, temporarily unprotects any protected sector
groups, and uses the higher voltage on the pin to reduce the time required for
program operations. The system would use a two-cycle program command se-
quence as required by the Unlock Bypass mode. Removing VHH from the WP#/
ACC pin returns the device to normal operation. Note that the WP#/ACC pin must
not be at VHH for operations other than accelerated programming, or device dam-
age may result. WP# has an internal pullup; when unconnected, WP# is at VIH
.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7–DQ0. Standard read
cycle timings apply in this mode. Refer to the “Autoselect Mode” section on page
42 and “Autoselect Command Sequence” section on page 56 sections for more
information.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at VIO
0.3 V. (Note that this is a more restricted voltage range than
0.3 V, the device
VIH.) If CE# and RESET# are held at VIH, but not within VIO
will be in the standby mode, but the standby current will be greater. The device
requires standard access time (tCE) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
Refer to the “DC Characteristics” section on page 83 for the standby current
specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for tACC
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
+
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
15
A d v a n c e I n f o r m a t i o n
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. Refer to the “DC Characteristics” section on page 83 for the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VSS 0.3 V, the device draws CMOS standby current (ICC5). If RESET# is held
at VIL but not within VSS 0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 13
for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins
are placed in the high impedance state.
Table 2. Sector Address Table–S29GL512N
8-bit
16-bit
Sector Size
(Kbytes/
Kwords)
Address Range
Address Range
Sector
A24–A16
(in hexadecimal)
(in hexadecimal)
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
0000000–001FFFF
0020000–003FFFF
0040000–005FFFF
0060000–007FFFF
0080000–009FFFF
00A0000–00BFFFF
00C0000–00DFFFF
00E0000–00FFFFF
0100000–011FFFF
0120000–013FFFF
0140000–015FFFF
0160000–017FFFF
0180000–019FFFF
01A0000–01BFFFF
0000000–000FFFF
0010000–001FFFF
0020000–002FFFF
0030000–003FFFF
0040000–004FFFF
0050000–005FFFF
0060000–006FFFF
0070000–007FFFF
0080000–008FFFF
0090000–009FFFF
00A0000–00AFFFF
00B0000–00BFFFF
00C0000–00CFFFF
00D0000–00DFFFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
16
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
01C0000–01DFFFF
01E0000–01FFFFF
0200000–021FFFF
0220000–023FFFF
0240000–025FFFF
0260000–027FFFF
0280000–029FFFF
02A0000–02BFFFF
02C0000–02DFFFF
02E0000–02FFFFF
0300000–031FFFF
0320000–033FFFF
0340000–035FFFF
0360000–037FFFF
0380000–039FFFF
03A0000–03BFFFF
03C0000–03DFFFF
03E0000–0EFFFFF
0400000–041FFFF
0420000–043FFFF
0440000–045FFFF
0460000–047FFFF
0480000–049FFFF
04A0000–04BFFFF
04C0000–04DFFFF
04E0000–04FFFFF
0500000–051FFFF
0520000–053FFFF
0540000–055FFFF
0560000–057FFFF
0580000–059FFFF
05A0000–05BFFFF
05C0000–05DFFFF
05E0000–05FFFFF
0600000–061FFFF
00E0000–00EFFFF
00F0000–00FFFFF
0100000–010FFFF
0110000–011FFFF
0120000–012FFFF
0130000–013FFFF
0140000–014FFFF
0150000–015FFFF
0160000–016FFFF
0170000–017FFFF
0180000–018FFFF
0190000–019FFFF
01A0000–01AFFFF
01B0000–01BFFFF
01C0000–01CFFFF
01D0000–01DFFFF
01E0000–01EFFFF
01F0000–01FFFFF
0200000–020FFFF
0210000–021FFFF
0220000–022FFFF
0230000–023FFFF
0240000–024FFFF
0250000–025FFFF
0260000–026FFFF
0270000–027FFFF
0280000–028FFFF
0290000–029FFFF
02A0000–02AFFFF
02B0000–02BFFFF
02C0000–02CFFFF
02D0000–02DFFFF
02E0000–02EFFFF
02F0000–02FFFFF
0300000–030FFFF
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
17
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0620000–063FFFF
0640000–065FFFF
0660000–067FFFF
0680000–069FFFF
06A0000–06BFFFF
06C0000–06DFFFF
06E0000–06FFFFF
0700000–071FFFF
0720000–073FFFF
0740000–075FFFF
0760000–077FFFF
0780000–079FFFF
07A0000–07BFFFF
07C0000–07DFFFF
07E0000–07FFFFF
0800000–081FFFF
0820000–083FFFF
0840000–085FFFF
0860000–087FFFF
0880000–089FFFF
08A0000–08BFFFF
08C0000–08DFFFF
08E0000–08FFFFF
0900000–091FFFF
0920000–093FFFF
0940000–095FFFF
0960000–097FFFF
0980000–099FFFF
09A0000–09BFFFF
09C0000–09DFFFF
09E0000–09FFFFF
0A00000–0A1FFFF
0A20000–0A3FFFF
0A40000–0A5FFFF
0A60000–0A7FFFF
0310000–031FFFF
0320000–032FFFF
0330000–033FFFF
0340000–034FFFF
0350000–035FFFF
0360000–036FFFF
0370000–037FFFF
0380000–038FFFF
0390000–039FFFF
03A0000–03AFFFF
03B0000–03BFFFF
03C0000–03CFFFF
03D0000–03DFFFF
03E0000–03EFFFF
03F0000–03FFFFF
0400000–040FFFF
0410000–041FFFF
0420000–042FFFF
0430000–043FFFF
0440000–044FFFF
0450000–045FFFF
0460000–046FFFF
0470000–047FFFF
0480000–048FFFF
0490000–049FFFF
04A0000–04AFFFF
04B0000–04BFFFF
04C0000–04CFFFF
04D0000–04DFFFF
04E0000–04EFFFF
04F0000–04FFFFF
0500000–050FFFF
0510000–051FFFF
0520000–052FFFF
0530000–053FFFF
18
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA84
SA85
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0A80000–0A9FFFF
0AA0000–0ABFFFF
0AC0000–0ADFFFF
0AE0000–0AFFFFF
0B00000–0B1FFFF
0B20000–0B3FFFF
0B40000–0B5FFFF
0B60000–0B7FFFF
0B80000–0B9FFFF
0BA0000–0BBFFFF
0BC0000–0BDFFFF
0BE0000–0BFFFFF
0C00000–0C1FFFF
0C20000–0C3FFFF
0C40000–0C5FFFF
0C60000–0C7FFFF
0C80000–0C9FFFF
0CA0000–0CBFFFF
0CC0000–0CDFFFF
0CE0000–0CFFFFF
0D00000–0D1FFFF
0D20000–0D3FFFF
0D40000–0D5FFFF
0D60000–0D7FFFF
0D80000–0D9FFFF
0DA0000–0DBFFFF
0DC0000–0DDFFFF
0DE0000–0DFFFFF
0E00000–0E1FFFF
0E20000–0E3FFFF
0E40000–0E5FFFF
0E60000–0E7FFFF
0E80000–0E9FFFF
0EA0000–0EBFFFF
0EC0000–0EDFFFF
0540000–054FFFF
0550000–055FFFF
0560000–056FFFF
0570000–057FFFF
0580000–058FFFF
0590000–059FFFF
05A0000–05AFFFF
05B0000–05BFFFF
05C0000–05CFFFF
05D0000–05DFFFF
05E0000–05EFFFF
05F0000–05FFFFF
0600000–060FFFF
0610000–061FFFF
0620000–062FFFF
0630000–063FFFF
0640000–064FFFF
0650000–065FFFF
0660000–066FFFF
0670000–067FFFF
0680000–068FFFF
0690000–069FFFF
06A0000–06AFFFF
06B0000–06BFFFF
06C0000–06CFFFF
06D0000–06DFFFF
06E0000–06EFFFF
06F0000–06FFFFF
0700000–070FFFF
0710000–071FFFF
0720000–072FFFF
0730000–073FFFF
0740000–074FFFF
0750000–075FFFF
0760000–076FFFF
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
19
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
SA142
SA143
SA144
SA145
SA146
SA147
SA148
SA149
SA150
SA151
SA152
SA153
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0EE0000–0EFFFFF
0F00000–0F1FFFF
0F20000–0F3FFFF
0F40000–0F5FFFF
0F60000–0F7FFFF
0F80000–0F9FFFF
0FA0000–0FBFFFF
0FC0000–0FDFFFF
0FE0000–0FFFFFF
1000000–101FFFF
1020000–103FFFF
1040000–105FFFF
1060000–017FFFF
1080000–109FFFF
10A0000–10BFFFF
10C0000–10DFFFF
10E0000–10FFFFF
1100000–111FFFF
1120000–113FFFF
1140000–115FFFF
1160000–117FFFF
1180000–119FFFF
11A0000–11BFFFF
11C0000–11DFFFF
11E0000–11FFFFF
1200000–121FFFF
1220000–123FFFF
1240000–125FFFF
1260000–127FFFF
1280000–129FFFF
12A0000–12BFFFF
12C0000–12DFFFF
12E0000–12FFFFF
1300000–131FFFF
1320000–133FFFF
0770000–077FFFF
0780000–078FFFF
0790000–079FFFF
07A0000–07AFFFF
07B0000–07BFFFF
07C0000–07CFFFF
07D0000–07DFFFF
07E0000–07EFFFF
07F0000–07FFFFF
0800000–080FFFF
0810000–081FFFF
0820000–082FFFF
0830000–083FFFF
0840000–084FFFF
0850000–085FFFF
0860000–086FFFF
0870000–087FFFF
0880000–088FFFF
0890000–089FFFF
08A0000–08AFFFF
08B0000–08BFFFF
08C0000–08CFFFF
08D0000–08DFFFF
08E0000–08EFFFF
08F0000–08FFFFF
0900000–090FFFF
0910000–091FFFF
0920000–092FFFF
0930000–093FFFF
0940000–094FFFF
0950000–095FFFF
0960000–096FFFF
0970000–097FFFF
0980000–098FFFF
0990000–099FFFF
20
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA154
SA155
SA156
SA157
SA158
SA159
SA160
SA161
SA162
SA163
SA164
SA165
SA166
SA167
SA168
SA169
SA170
SA171
SA172
SA173
SA174
SA175
SA176
SA177
SA178
SA179
SA180
SA181
SA182
SA183
SA184
SA185
SA186
SA187
SA188
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1340000–135FFFF
1360000–137FFFF
1380000–139FFFF
13A0000–13BFFFF
13C0000–13DFFFF
13E0000–13FFFFF
1400000–141FFFF
1420000–143FFFF
1440000–145FFFF
1460000–147FFFF
1480000–149FFFF
14A0000–14BFFFF
14C0000–14DFFFF
14E0000–14FFFFF
1500000–151FFFF
1520000–153FFFF
1540000–155FFFF
1560000–157FFFF
1580000–159FFFF
15A0000–15BFFFF
15C0000–15DFFFF
15E0000–15FFFFF
160000–161FFFF
1620000–163FFFF
1640000–165FFFF
1660000–167FFFF
1680000–169FFFF
16A0000–16BFFFF
16C0000–16DFFFF
16E0000–16FFFFF
1700000–171FFFF
1720000–173FFFF
1740000–175FFFF
1760000–177FFFF
1780000–179FFFF
09A0000–09AFFFF
09B0000–09BFFFF
09C0000–09CFFFF
09D0000–09DFFFF
09E0000–09EFFFF
09F0000–09FFFFF
0A00000–0A0FFFF
0A10000–0A1FFFF
0A20000–0A2FFFF
0A30000–0A3FFFF
0A40000–0A4FFFF
0A50000–0A5FFFF
0A60000–0A6FFFF
0A70000–0A7FFFF
0A80000–0A8FFFF
0A90000–0A9FFFF
0AA0000–0AAFFFF
0AB0000–0ABFFFF
0AC0000–0ACFFFF
0AD0000–0ADFFFF
0AE0000–0AEFFFF
0AF0000–0AFFFFF
0B00000–0B0FFFF
0B10000–0B1FFFF
0B20000–0B2FFFF
0B30000–0B3FFFF
0B40000–0B4FFFF
0B50000–0B5FFFF
0B60000–0B6FFFF
0B70000–0B7FFFF
0B80000–0B8FFFF
0B90000–0B9FFFF
0BA0000–0BAFFFF
0BB0000–0BBFFFF
0BC0000–0BCFFFF
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
21
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA189
SA190
SA191
SA192
SA193
SA194
SA195
SA196
SA197
SA198
SA199
SA200
SA201
SA202
SA203
SA204
SA205
SA206
SA207
SA208
SA209
SA210
SA211
SA212
SA213
SA214
SA215
SA216
SA217
SA218
SA219
SA220
SA221
SA222
SA223
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
17A0000–17BFFFF
17C0000–17DFFFF
17E0000–17FFFFF
1800000–181FFFF
1820000–183FFFF
1840000–185FFFF
1860000–187FFFF
1880000–189FFFF
18A0000–18BFFFF
18C0000–18DFFFF
18E0000–18FFFFF
1900000–191FFFF
1920000–193FFFF
1940000–195FFFF
1960000–197FFFF
1980000–199FFFF
19A0000–19BFFFF
19C0000–19DFFFF
19E0000–19FFFFF
1A00000–1A1FFFF
1A20000–1A3FFFF
1A40000–1A5FFFF
1A60000–1A7FFFF
1A80000–1A9FFFF
1AA0000–1ABFFFF
1AC0000–1ADFFFF
1AE0000–1AFFFFF
1B00000–1B1FFFF
1B20000–1B3FFFF
1B40000–1B5FFFF
1B60000–1B7FFFF
1B80000–1B9FFFF
1BA0000–1BBFFFF
1BC0000–1BDFFFF
1BE0000–1BFFFFF
0BD0000–0BDFFFF
0BE0000–0BEFFFF
0BF0000–0BFFFFF
0C00000–0C0FFFF
0C10000–0C1FFFF
0C20000–0C2FFFF
0C30000–0C3FFFF
0C40000–0C4FFFF
0C50000–0C5FFFF
0C60000–0C6FFFF
0C70000–0C7FFFF
0C80000–0C8FFFF
0C90000–0C9FFFF
0CA0000–0CAFFFF
0CB0000–0CBFFFF
0CC0000–0CCFFFF
0CD0000–0CDFFFF
0CE0000–0CEFFFF
0CF0000–0CFFFFF
0D00000–0D0FFFF
0D10000–0D1FFFF
0D20000–0D2FFFF
0D30000–0D3FFFF
0D40000–0D4FFFF
0D50000–0D5FFFF
0D60000–0D6FFFF
0D70000–0D7FFFF
0D80000–0D8FFFF
0D90000–0D9FFFF
0DA0000–0DAFFFF
0DB0000–0DBFFFF
0DC0000–0DCFFFF
0DD0000–0DDFFFF
0DE0000–0DEFFFF
0DF0000–0DFFFFF
22
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA224
SA225
SA226
SA227
SA228
SA229
SA230
SA231
SA232
SA233
SA234
SA235
SA236
SA237
SA238
SA239
SA240
SA241
SA242
SA243
SA244
SA245
SA246
SA247
SA248
SA249
SA250
SA251
SA252
SA253
SA254
SA255
SA256
SA257
SA258
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1C00000–1C1FFFF
1C20000–1C3FFFF
1C40000–1C5FFFF
1C60000–1C7FFFF
1C80000–1C9FFFF
1CA0000–1CBFFFF
1CC0000–1CDFFFF
1CE0000–1CFFFFF
1D00000–1D1FFFF
1D20000–1D3FFFF
1D40000–1D5FFFF
1D60000–1D7FFFF
1D80000–1D9FFFF
1DA0000–1DBFFFF
1DC0000–1DDFFFF
1DE0000–1DFFFFF
1E00000–1E1FFFF
1E20000–1E3FFFF
1E40000–1E5FFFF
1E60000–1E7FFFF
1E80000–1E9FFFF
1EA0000–1EBFFFF
1EC0000–1EDFFFF
1EE0000–1EFFFFF
1F00000–1F1FFFF
1F20000–1F3FFFF
1F40000–1F5FFFF
1F60000–1F7FFFF
1F80000–1F9FFFF
1FA0000–1FBFFFF
1FC0000–1FDFFFF
1FE0000–1FFFFFF
2000000–201FFFF
2020000–203FFFF
2040000–205FFFF
0E00000–0E0FFFF
0E10000–0E1FFFF
0E20000–0E2FFFF
0E30000–0E3FFFF
0E40000–0E4FFFF
0E50000–0E5FFFF
0E60000–0E6FFFF
0E70000–0E7FFFF
0E80000–0E8FFFF
0E90000–0E9FFFF
0EA0000–0EAFFFF
0EB0000–0EBFFFF
0EC0000–0ECFFFF
0ED0000–0EDFFFF
0EE0000–0EEFFFF
0EF0000–0EFFFFF
0F00000–0F0FFFF
0F10000–0F1FFFF
0F20000–0F2FFFF
0F30000–0F3FFFF
0F40000–0F4FFFF
0F50000–0F5FFFF
0F60000–0F6FFFF
0F70000–0F7FFFF
0F80000–0F8FFFF
0F90000–0F9FFFF
0FA0000–0FAFFFF
0FB0000–0FBFFFF
0FC0000–0FCFFFF
0FD0000–0FDFFFF
0FE0000–0FEFFFF
0FF0000–0FFFFFF
1000000–100FFFF
1010000–101FFFF
1020000–102FFFF
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
23
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA259
SA260
SA261
SA262
SA263
SA264
SA265
SA266
SA267
SA268
SA269
SA270
SA271
SA272
SA273
SA274
SA275
SA276
SA277
SA278
SA279
SA280
SA281
SA282
SA283
SA284
SA285
SA286
SA287
SA288
SA289
SA290
SA291
SA292
SA293
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2060000–207FFFF
2080000–209FFFF
20A0000–20BFFFF
20C0000–20DFFFF
20E0000–20FFFFF
2100000–211FFFF
2120000–213FFFF
2140000–215FFFF
2160000–217FFFF
2180000–219FFFF
21A0000–21BFFFF
21C0000–21DFFFF
21E0000–21FFFFF
2200000–221FFFF
2220000–223FFFF
2240000–225FFFF
2260000–227FFFF
2280000–229FFFF
22A0000–22BFFFF
22C0000–22DFFFF
22E0000–22FFFFF
2300000–231FFFF
2320000–233FFFF
2340000–235FFFF
2360000–237FFFF
2380000–239FFFF
23A0000–23BFFFF
23C0000–23DFFFF
23E0000–23FFFFF
2400000–241FFFF
2420000–243FFFF
2440000–245FFFF
2460000–247FFFF
2480000–249FFFF
24A0000–24BFFFF
1030000–103FFFF
1040000–104FFFF
1050000–105FFFF
1060000–106FFFF
1070000–107FFFF
1080000–108FFFF
1090000–109FFFF
10A0000–10AFFFF
10B0000–10BFFFF
10C0000–10CFFFF
10D0000–10DFFFF
10E0000–10EFFFF
10F0000–10FFFFF
1100000–110FFFF
1110000–111FFFF
1120000–112FFFF
1130000–113FFFF
1140000–114FFFF
1150000–115FFFF
1160000–116FFFF
1170000–117FFFF
1180000–118FFFF
1190000–119FFFF
11A0000–11AFFFF
11B0000–11BFFFF
11C0000–11CFFFF
11D0000–11DFFFF
11E0000–11EFFFF
11F0000–11FFFFF
1200000–120FFFF
1210000–121FFFF
1220000–122FFFF
1230000–123FFFF
1240000–124FFFF
1250000–125FFFF
24
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA294
SA295
SA296
SA297
SA298
SA299
SA300
SA301
SA302
SA303
SA304
SA305
SA306
SA307
SA308
SA309
SA310
SA311
SA312
SA313
SA314
SA315
SA316
SA317
SA318
SA319
SA320
SA321
SA322
SA323
SA324
SA325
SA326
SA327
SA328
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
24C0000–24DFFFF
24E0000–24FFFFF
2500000–251FFFF
2520000–253FFFF
2540000–255FFFF
2560000–257FFFF
2580000–259FFFF
25A0000–25BFFFF
25C0000–25DFFFF
25E0000–25FFFFF
2600000–261FFFF
2620000–263FFFF
2640000–265FFFF
2660000–267FFFF
2680000–269FFFF
26A0000–26BFFFF
26C0000–26DFFFF
26E0000–26FFFFF
2700000–271FFFF
2720000–273FFFF
2740000–275FFFF
2760000–277FFFF
2780000–279FFFF
27A0000–27BFFFF
27C0000–27DFFFF
27E0000–27FFFFF
2800000–281FFFF
2820000–283FFFF
2840000–285FFFF
2860000–287FFFF
2880000–289FFFF
28A0000–28BFFFF
28C0000–28DFFFF
28E0000–28FFFFF
2900000–291FFFF
1260000–126FFFF
1270000–127FFFF
1280000–128FFFF
1290000–129FFFF
12A0000–12AFFFF
12B0000–12BFFFF
12C0000–12CFFFF
12D0000–12DFFFF
12E0000–12EFFFF
12F0000–12FFFFF
1300000–130FFFF
1310000–131FFFF
1320000–132FFFF
1330000–133FFFF
1340000–134FFFF
1350000–135FFFF
1360000–136FFFF
1370000–137FFFF
1380000–138FFFF
1390000–139FFFF
13A0000–13AFFFF
13B0000–13BFFFF
13C0000–13CFFFF
13D0000–13DFFFF
13E0000–13EFFFF
13F0000–13FFFFF
1400000–140FFFF
1410000–141FFFF
1420000–142FFFF
1430000–143FFFF
1440000–144FFFF
1450000–145FFFF
1460000–146FFFF
1470000–147FFFF
1480000–148FFFF
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
25
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA329
SA330
SA331
SA332
SA333
SA334
SA335
SA336
SA337
SA338
SA339
SA340
SA341
SA342
SA343
SA344
SA345
SA346
SA347
SA348
SA349
SA350
SA351
SA352
SA353
SA354
SA355
SA356
SA357
SA358
SA359
SA360
SA361
SA362
SA363
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2920000–293FFFF
2940000–295FFFF
2960000–297FFFF
2980000–299FFFF
29A0000–29BFFFF
29C0000–29DFFFF
29E0000–29FFFFF
2A00000–2A1FFFF
2A20000–2A3FFFF
2A40000–2A5FFFF
2A60000–2A7FFFF
2A80000–2A9FFFF
2AA0000–2ABFFFF
2AC0000–2ADFFFF
2AE00000–2EFFFFF
2B00000–2B1FFFF
2B20000–2B3FFFF
2B40000–2B5FFFF
2B60000–2B7FFFF
2B80000–2B9FFFF
2BA0000–2BBFFFF
2BC0000–2DFFFFF
2BE0000–2BFFFFF
2C00000–2C1FFFF
2C20000–2C3FFFF
2C40000–2C5FFFF
2C60000–2C7FFFF
2C80000–2C9FFFF
2CA0000–2CBFFFF
2CC0000–2CDFFFF
2CE0000–2CFFFFF
2D00000–2D1FFFF
2D20000–2D3FFFF
2D40000–2D5FFFF
2D60000–2D7FFFF
1490000–149FFFF
14A0000–14AFFFF
14B0000–14BFFFF
14C0000–14CFFFF
14D0000–14DFFFF
14E0000–14EFFFF
14F0000–14FFFFF
1500000–150FFFF
1510000–151FFFF
1520000–152FFFF
1530000–153FFFF
1540000–154FFFF
1550000–155FFFF
1560000–156FFFF
1570000–157FFFF
1580000–158FFFF
1590000–159FFFF
15A0000–15AFFFF
15B0000–15BFFFF
15C0000–15CFFFF
15D0000–15DFFFF
15E0000–15EFFFF
15F0000–15FFFFF
1600000–160FFFF
1610000–161FFFF
1620000–162FFFF
1630000–163FFFF
1640000–164FFFF
1650000–165FFFF
1660000–166FFFF
1670000–167FFFF
1680000–168FFFF
1690000–169FFFF
16A0000–16AFFFF
16B0000–16BFFFF
26
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA364
SA365
SA366
SA367
SA368
SA369
SA370
SA371
SA372
SA373
SA374
SA375
SA376
SA377
SA378
SA379
SA380
SA381
SA382
SA383
SA384
SA385
SA386
SA387
SA388
SA389
SA390
SA391
SA392
SA393
SA394
SA395
SA396
SA397
SA398
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
2D80000–2D9FFFF
2DA0000–2DBFFFF
2DC0000–2DDFFFF
2DE0000–2DFFFFF
2E00000–2E1FFFF
2E20000–2E3FFFF
2E40000–2E5FFFF
2E60000–2E7FFFF
2E80000–2E9FFFF
2EA0000–2EBFFFF
2EC0000–2EDFFFF
2EE0000–2EFFFFF
2F00000–2F1FFFF
2F20000–2F3FFFF
2F40000–2F5FFFF
2F60000–2F7FFFF
2F80000–2F9FFFF
2FA0000–2FBFFFF
2FC0000–2FDFFFF
3FE0000–3FFFFFF
3000000–301FFFF
3020000–303FFFF
3040000–305FFFF
3060000–307FFFF
3080000–309FFFF
30A0000–30BFFFF
30C0000–30DFFFF
30E0000–30FFFFF
3100000–311FFFF
3120000–313FFFF
3140000–315FFFF
3160000–317FFFF
3180000–319FFFF
31A0000–31BFFFF
31C0000–31DFFFF
16C0000–16CFFFF
16D0000–16DFFFF
16E0000–16EFFFF
16F0000–16FFFFF
1700000–170FFFF
1710000–171FFFF
1720000–172FFFF
1730000–173FFFF
1740000–174FFFF
1750000–175FFFF
1760000–176FFFF
1770000–177FFFF
1780000–178FFFF
1790000–179FFFF
17A0000–17AFFFF
17B0000–17BFFFF
17C0000–17CFFFF
17D0000–17DFFFF
17E0000–17EFFFF
17F0000–17FFFFF
1800000–180FFFF
1810000–181FFFF
1820000–182FFFF
1830000–183FFFF
1840000–184FFFF
1850000–185FFFF
1860000–186FFFF
1870000–187FFFF
1880000–188FFFF
1890000–189FFFF
18A0000–18AFFFF
18B0000–18BFFFF
18C0000–18CFFFF
18D0000–18DFFFF
18E0000–18EFFFF
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
27
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA399
SA400
SA401
SA402
SA403
SA404
SA405
SA406
SA407
SA408
SA409
SA410
SA411
SA412
SA413
SA414
SA415
SA416
SA417
SA418
SA419
SA420
SA421
SA422
SA423
SA424
SA425
SA426
SA427
SA428
SA429
SA430
SA431
SA432
SA433
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
31E0000–31FFFFF
3200000–321FFFF
3220000–323FFFF
3240000–325FFFF
3260000–327FFFF
3280000–329FFFF
32A0000–32BFFFF
32C0000–32DFFFF
32E0000–32FFFFF
3300000–331FFFF
3320000–333FFFF
3340000–335FFFF
3360000–337FFFF
3380000–339FFFF
33A0000–33BFFFF
33C0000–33DFFFF
33E0000–33FFFFF
3400000–341FFFF
3420000–343FFFF
3440000–345FFFF
3460000–347FFFF
3480000–349FFFF
34A0000–34BFFFF
34C0000–34DFFFF
34E0000–34FFFFF
3500000–351FFFF
3520000–353FFFF
3540000–355FFFF
3560000–357FFFF
3580000–359FFFF
35A0000–35BFFFF
35C0000–35DFFFF
35E0000–35FFFFF
3600000–361FFFF
3620000–363FFFF
18F0000–18FFFFF
1900000–190FFFF
1910000–191FFFF
1920000–192FFFF
1930000–193FFFF
1940000–194FFFF
1950000–195FFFF
1960000–196FFFF
1970000–197FFFF
1980000–198FFFF
1990000–199FFFF
19A0000–19AFFFF
19B0000–19BFFFF
19C0000–19CFFFF
19D0000–19DFFFF
19E0000–19EFFFF
19F0000–19FFFFF
1A00000–1A0FFFF
1A10000–1A1FFFF
1A20000–1A2FFFF
1A30000–1A3FFFF
1A40000–1A4FFFF
1A50000–1A5FFFF
1A60000–1A6FFFF
1A70000–1A7FFFF
1A80000–1A8FFFF
1A90000–1A9FFFF
1AA0000–1AAFFFF
1AB0000–1ABFFFF
1AC0000–1ACFFFF
1AD0000–1ADFFFF
1AE0000–1AEFFFF
1AF0000–1AFFFFF
1B00000–1B0FFFF
1B10000–1B1FFFF
28
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA434
SA435
SA436
SA437
SA438
SA439
SA440
SA441
SA442
SA443
SA444
SA445
SA446
SA447
SA448
SA449
SA450
SA451
SA452
SA453
SA454
SA455
SA456
SA457
SA458
SA459
SA460
SA461
SA462
SA463
SA464
SA465
SA466
SA467
SA468
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
3640000–365FFFF
3660000–367FFFF
3680000–369FFFF
36A0000–36BFFFF
36C0000–36DFFFF
36E0000–36FFFFF
3700000–371FFFF
3720000–373FFFF
3740000–375FFFF
3760000–377FFFF
3780000–379FFFF
37A0000–37BFFFF
37C0000–37DFFFF
37E0000–37FFFFF
3800000–381FFFF
3820000–383FFFF
3840000–385FFFF
3860000–387FFFF
3880000–389FFFF
38A0000–38BFFFF
38C0000–38DFFFF
38E0000–38FFFFF
3900000–391FFFF
3920000–393FFFF
3940000–395FFFF
3960000–397FFFF
3980000–399FFFF
39A0000–39BFFFF
39C0000–39DFFFF
39E0000–39FFFFF
3A00000–3A1FFFF
3A20000–3A3FFFF
3A40000–3A5FFFF
3A60000–3A7FFFF
3A80000–3A9FFFF
1B20000–1B2FFFF
1B30000–1B3FFFF
1B40000–1B4FFFF
1B50000–1B5FFFF
1B60000–1B6FFFF
1B70000–1B7FFFF
1B80000–1B8FFFF
1B90000–1B9FFFF
1BA0000–1BAFFFF
1BB0000–1BBFFFF
1BC0000–1BCFFFF
1BD0000–1BDFFFF
1BE0000–1BEFFFF
1BF0000–1BFFFFF
1C00000–1C0FFFF
1C10000–1C1FFFF
1C20000–1C2FFFF
1C30000–1C3FFFF
1C40000–1C4FFFF
1C50000–1C5FFFF
1C60000–1C6FFFF
1C70000–1C7FFFF
1C80000–1C8FFFF
1C90000–1C9FFFF
1CA0000–1CAFFFF
1CB0000–1CBFFFF
1CC0000–1CCFFFF
1CD0000–1CDFFFF
1CE0000–1CEFFFF
1CF0000–1CFFFFF
1D00000–1D0FFFF
1D10000–1D1FFFF
1D20000–1D2FFFF
1D30000–1D3FFFF
1D40000–1D4FFFF
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
29
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA469
SA470
SA471
SA472
SA473
SA474
SA475
SA476
SA477
SA478
SA479
SA480
SA481
SA482
SA483
SA484
SA485
SA486
SA487
SA488
SA489
SA490
SA491
SA492
SA493
SA494
SA495
SA496
SA497
SA498
SA499
SA500
SA501
SA502
SA503
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3AA0000–3ABFFFF
3AC0000–3ADFFFF
3AE0000–3AFFFFF
3B00000–3B1FFFF
3B20000–3B3FFFF
3B40000–3B5FFFF
3B60000–3B7FFFF
3B80000–3B9FFFF
3BA0000–3BBFFFF
3BC0000–3BDFFFF
3BE0000–3BFFFFF
3C00000–3C1FFFF
3C20000–3C3FFFF
3C40000–3C5FFFF
3C60000–3C7FFFF
3C80000–3C9FFFF
3CA0000–3CBFFFF
3CC0000–3CDFFFF
3CE0000–3CFFFFF
3D00000–3D1FFFFF
3D20000–3D3FFFF
3D40000–3D5FFFF
3D60000–3D7FFFF
3D80000–3D9FFFF
3DA0000–3DBFFFF
3DC0000–3DDFFFF
3DE0000–3DFFFFF
3E00000–3E1FFFF
3E20000–3E3FFFF
3E40000–3E5FFFF
3E60000–3E7FFFF
3E80000–3E9FFFF
3EA0000–3EBFFFF
3EC00000–3EDFFFF
3EE0000–3EFFFFF
1D50000–1D5FFFF
1D60000–1D6FFFF
1D70000–1D7FFFF
1D80000–1D8FFFF
1D90000–1D9FFFF
1DA0000–1DAFFFF
1DB0000–1DBFFFF
1DC0000–1DCFFFF
1DD0000–1DDFFFF
1DE0000–1DEFFFF
1DF0000–1DFFFFF
1E00000–1E0FFFF
1E10000–1E1FFFF
1E20000–1E2FFFF
1E30000–1E3FFFF
1E40000–1E4FFFF
1E50000–1E5FFFF
1E60000–1E6FFFF
1E70000–1E7FFFF
1E80000–1E8FFFF
1E90000–1E9FFFF
1EA0000–1EAFFFF
1EB0000–1EBFFFF
1EC0000–1ECFFFF
1ED0000–1EDFFFF
1EE0000–1EEFFFF
1EF0000–1EFFFFF
1F00000–1F0FFFF
1F10000–1F1FFFF
1F20000–1F2FFFF
1F30000–1F3FFFF
1F40000–1F4FFFF
1F50000–1F5FFFF
1F60000–1F6FFFF
1F70000–1F7FFFF
30
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table–S29GL512N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A24–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA504
SA505
SA506
SA507
SA508
SA509
SA510
SA511
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3F00000–3F1FFFF
3F20000–3F3FFFF
3F40000–3F5FFFF
3F60000–3F7FFFF
3F80000–3F9FFFF
3FA0000–3FBFFFF
3FC0000–3FDFFFF
3FE0000–3FFFFFF
1F80000–1F8FFFF
1F90000–1F9FFFF
1FA0000–1FAFFFF
1FB0000–1FBFFFF
1FC0000–1FCFFFF
1FD0000–1FDFFFF
1FE0000–1FEFFFF
1FF0000–1FFFFFF
Table 3. Sector Address Table–S29GL256N
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector Size
(Kbytes/
Kwords)
Sector
A23–A16
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
0000000–001FFFF
0020000–003FFFF
0040000–005FFFF
0060000–007FFFF
0080000–009FFFF
00A0000–00BFFFF
00C0000–00DFFFF
00E0000–00FFFFF
0100000–011FFFF
0120000–013FFFF
0140000–015FFFF
0160000–017FFFF
0180000–019FFFF
01A0000–01BFFFF
01C0000–01DFFFF
01E0000–01FFFFF
0200000–021FFFF
0220000–023FFFF
0240000–025FFFF
0260000–027FFFF
0280000–029FFFF
02A0000–02BFFFF
0000000–000FFFF
0010000–001FFFF
0020000–002FFFF
0030000–003FFFF
0040000–004FFFF
0050000–005FFFF
0060000–006FFFF
0070000–007FFFF
0080000–008FFFF
0090000–009FFFF
00A0000–00AFFFF
00B0000–00BFFFF
00C0000–00CFFFF
00D0000–00DFFFF
00E0000–00EFFFF
00F0000–00FFFFF
0100000–010FFFF
0110000–011FFFF
0120000–012FFFF
0130000–013FFFF
0140000–014FFFF
0150000–015FFFF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
31
A d v a n c e I n f o r m a t i o n
Table 3. Sector Address Table–S29GL256N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A23–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
02C0000–02DFFFF
02E0000–02FFFFF
0300000–031FFFF
0320000–033FFFF
0340000–035FFFF
0360000–037FFFF
0380000–039FFFF
03A0000–03BFFFF
03C0000–03DFFFF
03E0000–03FFFFF
0400000–041FFFF
0420000–043FFFF
0440000–045FFFF
0460000–047FFFF
0480000–049FFFF
04A0000–04BFFFF
04C0000–04DFFFF
04E0000–04FFFFF
0500000–051FFFF
0520000–053FFFF
0540000–055FFFF
0560000–057FFFF
0580000–059FFFF
05A0000–05BFFFF
05C0000–05DFFFF
05E0000–05FFFFF
0600000–061FFFF
0620000–063FFFF
0640000–065FFFF
0660000–067FFFF
0680000–069FFFF
06A0000–06BFFFF
06C0000–06DFFFF
06E0000–06FFFFF
0700000–071FFFF
0160000–016FFFF
0170000–017FFFF
0180000–018FFFF
0190000–019FFFF
01A0000–01AFFFF
01B0000–01BFFFF
01C0000–01CFFFF
01D0000–01DFFFF
01E0000–01EFFFF
01F0000–01FFFFF
0200000–020FFFF
0210000–021FFFF
0220000–022FFFF
0230000–023FFFF
0240000–024FFFF
0250000–025FFFF
0260000–026FFFF
0270000–027FFFF
0280000–028FFFF
0290000–029FFFF
02A0000–02AFFFF
02B0000–02BFFFF
02C0000–02CFFFF
02D0000–02DFFFF
02E0000–02EFFFF
02F0000–02FFFFF
0300000–030FFFF
0310000–031FFFF
0320000–032FFFF
0330000–033FFFF
0340000–034FFFF
0350000–035FFFF
0360000–036FFFF
0370000–037FFFF
0380000–038FFFF
32
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 3. Sector Address Table–S29GL256N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A23–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0720000–073FFFF
0740000–075FFFF
0760000–077FFFF
0780000–079FFFF
07A0000–7BFFFF
07C0000–07DFFFF
07E0000–07FFFFF0
0800000–081FFFF
0820000–083FFFF
0840000–085FFFF
0860000–087FFFF
0880000–089FFFF
08A0000–08BFFFF
08C0000–08DFFFF
08E0000–08FFFFF
0900000–091FFFF
0920000–093FFFF
0940000–095FFFF
0960000–097FFFF
0980000–099FFFF
09A0000–09BFFFF
09C0000–09DFFFF
09E0000–09FFFFF
0A00000–0A1FFFF
0A20000–0A3FFFF
0A40000–045FFFF
0A60000–0A7FFFF
0A80000–0A9FFFF
0AA0000–0ABFFFF
0AC0000–0ADFFFF
0AE0000–AEFFFFF
0B00000–0B1FFFF
0B20000–0B3FFFF
0B40000–0B5FFFF
0B60000–0B7FFFF
0390000–039FFFF
03A0000–03AFFFF
03B0000–03BFFFF
03C0000–03CFFFF
03D0000–03DFFFF
03E0000–03EFFFF
03F0000–03FFFFF
0400000–040FFFF
0410000–041FFFF
0420000–042FFFF
0430000–043FFFF
0440000–044FFFF
0450000–045FFFF
0460000–046FFFF
0470000–047FFFF
0480000–048FFFF
0490000–049FFFF
04A0000–04AFFFF
04B0000–04BFFFF
04C0000–04CFFFF
04D0000–04DFFFF
04E0000–04EFFFF
04F0000–04FFFFF
0500000–050FFFF
0510000–051FFFF
0520000–052FFFF
0530000–053FFFF
0540000–054FFFF
0550000–055FFFF
0560000–056FFFF
0570000–057FFFF
0580000–058FFFF
0590000–059FFFF
05A0000–05AFFFF
05B0000–05BFFFF
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
33
A d v a n c e I n f o r m a t i o n
Table 3. Sector Address Table–S29GL256N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A23–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA92
SA93
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0B80000–0B9FFFF
0BA0000–0BBFFFF
0BC0000–0BDFFFF
0BE0000–0BFFFFF
0C00000–0C1FFFF
0C20000–0C3FFFF
0C40000–0C5FFFF
0C60000–0C7FFFF
0C80000–0C9FFFF
0CA0000–0CBFFFF
0CC0000–0CDFFFF
0CE0000–0CFFFFF
0D00000–0D1FFFF
0D20000–0D3FFFF
0D40000–0D5FFFF
0D60000–0D7FFFF
0D80000–0D9FFFF
0DA0000–0DBFFFF
0DC0000–0DDFFFF
0DE0000–0DFFFFF
0E00000–0E1FFFF
0E20000–0E3FFFF
0E40000–0E5FFFF
0E60000–0E7FFFF
0E80000–0E9FFFF
0EA0000–0EBFFFF
0EC0000–0EDFFFF
0EE0000–0EFFFFF
0F00000–0F1FFFF
0F20000–0F3FFFF
0F40000–0F5FFFF
0F60000–0F7FFFF
0F80000–0F9FFFF
0FA0000–0FBFFFF
0FC0000–0FDFFFF
05C0000–05CFFFF
05D0000–05DFFFF
05E0000–05EFFFF
05F0000–05FFFFF
0600000–060FFFF
0610000–061FFFF
0620000–062FFFF
0630000–063FFFF
0640000–064FFFF
0650000–065FFFF
0660000–066FFFF
0670000–067FFFF
0680000–068FFFF
0690000–069FFFF
06A0000–06AFFFF
06B0000–06BFFFF
06C0000–06CFFFF
06D0000–06DFFFF
06E0000–06EFFFF
06F0000–06FFFFF
0700000–070FFFF
0710000–071FFFF
0720000–072FFFF
0730000–073FFFF
0740000–074FFFF
0750000–075FFFF
0760000–076FFFF
0770000–077FFFF
0780000–078FFFF
0790000–079FFFF
07A0000–07AFFFF
07B0000–07BFFFF
07C0000–07CFFFF
07D0000–07DFFFF
07E0000–07EFFFF
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
34
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 3. Sector Address Table–S29GL256N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A23–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
SA142
SA143
SA144
SA145
SA146
SA147
SA148
SA149
SA150
SA151
SA152
SA153
SA154
SA155
SA156
SA157
SA158
SA159
SA160
SA161
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0FE0000–0FFFFFF
1000000–101FFFF
1020000–103FFFF
1040000–105FFFF
1060000–107FFFF
1080000–109FFFF
10A0000–10BFFFF
10C0000–10DFFFF
10E0000–10FFFFF
1100000–111FFFF
1120000–113FFFF
1140000–115FFFF
1160000–117FFFF
1180000–119FFFF
11A0000–11BFFFF
11C0000–11DFFFF
11E0000–11FFFFF
1200000–121FFFF
1220000–123FFFF
1240000–125FFFF
1260000–127FFFF
1280000–129FFFF
12A0000–12BFFFF
12C0000–12DFFFF
12E0000–12FFFFF
1300000–131FFFF
1320000–133FFFF
1340000–135FFFF
1360000–137FFFF
1380000–139FFFF
13A0000–13BFFFF
13C0000–13DFFFF
13E0000–13FFFFF
1400000–141FFFF
1420000–143FFFF
07F0000–07FFFFF
0800000–080FFFF
0810000–081FFFF
0820000–082FFFF
0830000–083FFFF
0840000–084FFFF
0850000–085FFFF
0860000–086FFFF
0870000–087FFFF
0880000–088FFFF
0890000–089FFFF
08A0000–08AFFFF
08B0000–08BFFFF
08C0000–08CFFFF
08D0000–08DFFFF
08E0000–08EFFFF
08F0000–08FFFFF
0900000–090FFFF
0910000–091FFFF
0920000–092FFFF
0930000–093FFFF
0940000–094FFFF
0950000–095FFFF
0960000–096FFFF
0970000–097FFFF
0980000–098FFFF
0990000–099FFFF
09A0000–09AFFFF
09B0000–09BFFFF
09C0000–09CFFFF
09D0000–09DFFFF
09E0000–09EFFFF
09F0000–09FFFFF
0A00000–0A0FFFF
0A10000–0A1FFFF
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
35
A d v a n c e I n f o r m a t i o n
Table 3. Sector Address Table–S29GL256N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A23–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA162
SA163
SA164
SA165
SA166
SA167
SA168
SA169
SA170
SA171
SA172
SA173
SA174
SA175
SA176
SA177
SA178
SA179
SA180
SA181
SA182
SA183
SA184
SA185
SA186
SA187
SA188
SA189
SA190
SA191
SA192
SA193
SA194
SA195
SA196
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1440000–145FFFF
1460000–147FFFF
1480000–149FFFF
14A0000–14BFFFF
14C0000–14DFFFF
14E0000–14FFFFF
1500000–151FFFF
1520000–153FFFF
1540000–155FFFF
1560000–157FFFF
1580000–159FFFF
15A0000–15BFFFF
15C0000–15DFFFF
15E0000–15FFFFF
1600000–161FFFF
1620000–163FFFF
1640000–165FFFFF
1660000–167FFFF
1680000–169FFFF
16A0000–16BFFFF
16C0000–16DFFFF
16E0000–16FFFFF
1700000–171FFFF
1720000–173FFFF
1740000–175FFFF
1760000–177FFFF
1780000–179FFFF
17A0000–17BFFFF
17C0000–17DFFFF
17E0000–17FFFFF
1800000–181FFFF
1820000–183FFFF
1840000–185FFFF
1860000–187FFFF
1880000–189FFFF
0A20000–0A2FFFF
0A30000–0A3FFFF
0A40000–0A4FFFF
0A50000–0A5FFFF
0A60000–0A6FFFF
0A70000–0A7FFFF
0A80000–0A8FFFF
0A90000–0A9FFFF
0AA0000–0AAFFFF
0AB0000–0ABFFFF
0AC0000–0ACFFFF
0AD0000–0ADFFFF
0AE0000–0AEFFFF
0AF0000–0AFFFFF
0B00000–0B0FFFF
0B10000–0B1FFFF
0B20000–0B2FFFF
0B30000–0B3FFFF
0B40000–0B4FFFF
0B50000–0B5FFFF
0B60000–0B6FFFF
0B70000–0B7FFFF
0B80000–0B8FFFF
0B90000–0B9FFFF
0BA0000–0BAFFFF
0BB0000–0BBFFFF
0BC0000–0BCFFFF
0BD0000–0BDFFFF
0BE0000–0BEFFFF
0BF0000–0BFFFFF
0C00000–0C0FFFF
0C10000–0C1FFFF
0C20000–0C2FFFF
0C30000–0C3FFFF
0C40000–0C4FFFF
36
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 3. Sector Address Table–S29GL256N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A23–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA197
SA198
SA199
SA200
SA201
SA202
SA203
SA204
SA205
SA206
SA207
SA208
SA209
SA210
SA211
SA212
SA213
SA214
SA215
SA216
SA217
SA218
SA219
SA220
SA221
SA222
SA223
SA224
SA225
SA226
SA227
SA228
SA229
SA230
SA231
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
18A0000–18BFFFF
18C0000–18DFFFF
18E0000–18FFFFF
1900000–191FFFF
1920000–193FFFF
1940000–195FFFF
1960000–197FFFF
1980000–199FFFF
19A0000–19BFFFF
19C0000–19DFFFF
19E0000–19FFFF
1A00000–1A1FFFF
1A20000–1A3FFFF
1A40000–1A5FFFF
1A60000–1A7FFFF
1A80000–1A9FFFF
1AA0000–1ABFFFF
1AC0000–1ADFFFF
1AE0000–1AFFFFF
1B00000–1B1FFFF
1B20000–1B3FFFF
1B40000–1B5FFFF
1B60000–1B7FFFF
1B80000–1B9FFFF
1BA0000–1BBFFFF
1BC0000–1BDFFFF
1BE0000–1BFFFFF
1C00000–1C1FFFF
1C20000–1C3FFFF
1C40000–1C5FFFF
1C60000–1C7FFFF
1C80000–1C9FFFF
1CA0000–1CBFFFF
1CC0000–1CDFFFF
1CE0000–1CFFFFF
0C50000–0C5FFFF
0C60000–0C6FFFF
0C70000–0C7FFFF
0C80000–0C8FFFF
0C90000–0C9FFFF
0CA0000–0CAFFFF
0CB0000–0CBFFFF
0CC0000–0CCFFFF
0CD0000–0CDFFFF
0CE0000–0CEFFFF
0CF0000–0CFFFFF
0D00000–0D0FFFF
0D10000–0D1FFFF
0D20000–0D2FFFF
0D30000–0D3FFFF
0D40000–0D4FFFF
0D50000–0D5FFFF
0D60000–0D6FFFF
0D70000–0D7FFFF
0D80000–0D8FFFF
0D90000–0D9FFFF
0DA0000–0DAFFFF
0DB0000–0DBFFFF
0DC0000–0DCFFFF
0DD0000–0DDFFFF
0DE0000–0DEFFFF
0DF0000–0DFFFFF
0E00000–0E0FFFF
0E10000–0E1FFFF
0E20000–0E2FFFF
0E30000–0E3FFFF
0E40000–0E4FFFF
0E50000–0E5FFFF
0E60000–0E6FFFF
0E70000–0E7FFFF
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
37
A d v a n c e I n f o r m a t i o n
Table 3. Sector Address Table–S29GL256N (Continued)
8-bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A23–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA232
SA233
SA234
SA235
SA236
SA237
SA238
SA239
SA240
SA241
SA242
SA243
SA244
SA245
SA246
SA247
SA248
SA249
SA250
SA251
SA252
SA253
SA254
SA255
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1D00000–1D1FFFF
1D20000–1D3FFFF
1D40000–1D5FFFF
1D60000–1D7FFFF
1D80000–1D9FFFF
1DA0000–1DBFFFF
1DC0000–1DDFFFF
1DE0000–1DFFFFF
1E00000–1E1FFFF
1E20000–1E3FFFF
1E40000–1E5FFFF
1E60000–137FFFF
1E80000–1E9FFFF
1EA0000–1EBFFFF
1EC0000–1EDFFFF
1EE0000–1EFFFFF
1F00000–1F1FFFF
1F20000–1F3FFFF
1F40000–1F5FFFF
1F60000–1F7FFFF
1F80000–1F9FFFF
1FA0000–1FBFFFF
1FC0000–1FDFFFF
1FE0000–1FFFFFF
0E80000–0E8FFFF
0E90000–0E9FFFF
0EA0000–0EAFFFF
0EB0000–0EBFFFF
0EC0000–0ECFFFF
0ED0000–0EDFFFF
0EE0000–0EEFFFF
0EF0000–0EFFFFF
0F00000–0F0FFFF
0F10000–0F1FFFF
0F20000–0F2FFFF
0F30000–0F3FFFF
0F40000–0F4FFFF
0F50000–0F5FFFF
0F60000–0F6FFFF
0F70000–0F7FFFF
0F80000–0F8FFFF
0F90000–0F9FFFF
0FA0000–0FAFFFF
0FB0000–0FBFFFF
0FC0000–0FCFFFF
0FD0000–0FDFFFF
0FE0000–0FEFFFF
0FF0000–0FFFFFF
Table 4. Sector Address Table–S29GL128N
8-Bit
16-bit
Address Range
(in hexadecimal)
Sector Size
(Kbytes/
Kwords)
Address Range
Sector
A22–A16
(in hexadecimal)
SA0
SA1
SA2
SA3
SA4
SA5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
128/64
128/64
128/64
128/64
128/64
128/64
0000000–001FFFF
0020000–003FFFF
0040000–005FFFF
0060000–007FFFF
0080000–009FFFF
00A0000–00BFFFF
0000000–000FFFF
0010000–001FFFF
0020000–002FFFF
0030000–003FFFF
0040000–004FFFF
0050000–005FFFF
38
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 4. Sector Address Table–S29GL128N (Continued)
8-Bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A22–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
00C0000–00DFFFF
00E0000–00FFFFF
0100000–011FFFF
0120000–013FFFF
0140000–015FFFF
0160000–017FFFF
0180000–019FFFF
01A0000–01BFFFF
01C0000–01DFFFF
01E0000–01FFFFF
0200000–021FFFF
0220000–023FFFF
0240000–025FFFF
0260000–027FFFF
0280000–029FFFF
02A0000–02BFFFF
02C0000–02DFFFF
02E0000–02FFFFF
0300000–031FFFF
0320000–033FFFF
0340000–035FFFF
0360000–037FFFF
0380000–039FFFF
03A0000–03BFFFF
03C0000–03DFFFF
03E0000–03FFFFF
0400000–041FFFF
0420000–043FFFF
0440000–045FFFF
0460000–047FFFF
0480000–049FFFF
04A0000–04BFFFF
04C0000–04DFFFF
04E0000–04FFFFF
0500000–051FFFF
0060000–006FFFF
0070000–007FFFF
0080000–008FFFF
0090000–009FFFF
00A0000–00AFFFF
00B0000–00BFFFF
00C0000–00CFFFF
00D0000–00DFFFF
00E0000–00EFFFF
00F0000–00FFFFF
0100000–010FFFF
0110000–011FFFF
0120000–012FFFF
0130000–013FFFF
0140000–014FFFF
0150000–015FFFF
0160000–016FFFF
0170000–017FFFF
0180000–018FFFF
0190000–019FFFF
01A0000–01AFFFF
01B0000–01BFFFF
01C0000–01CFFFF
01D0000–01DFFFF
01E0000–01EFFFF
01F0000–01FFFFF
0200000–020FFFF
0210000–021FFFF
0220000–022FFFF
0230000–023FFFF
0240000–024FFFF
0250000–025FFFF
0260000–026FFFF
0270000–027FFFF
0280000–028FFFF
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
39
A d v a n c e I n f o r m a t i o n
Table 4. Sector Address Table–S29GL128N (Continued)
8-Bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A22–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0520000–053FFFF
0540000–055FFFF
0560000–057FFFF
0580000–059FFFF
05A0000–05BFFFF
05C0000–05DFFFF
05E0000–05FFFFF
0600000–061FFFF
0620000–063FFFF
0640000–065FFFF
0660000–067FFFF
0680000–069FFFF
06A0000–06BFFFF
06C0000–06DFFFF
06E0000–06FFFFF
0700000–071FFFF
0720000–073FFFF
0740000–075FFFF
0760000–077FFFF
0780000–079FFFF
07A0000–07BFFFF
07C0000–07DFFFF
07E0000–07FFFFF
0800000–081FFFF
0820000–083FFFF
0840000–085FFFF
0860000–087FFFF
0880000–089FFFF
08A0000–08BFFFF
08C0000–08DFFFF
08E0000–08FFFFF
0900000–091FFFF
0920000–093FFFF
0940000–095FFFF
0960000–097FFFF
0290000–029FFFF
02A0000–02AFFFF
02B0000–02BFFFF
02C0000–02CFFFF
02D0000–02DFFFF
02E0000–02EFFFF
02F0000–02FFFFF
0300000–030FFFF
0310000–031FFFF
0320000–032FFFF
0330000–033FFFF
0340000–034FFFF
0350000–035FFFF
0360000–036FFFF
0370000–037FFFF
0380000–038FFFF
0390000–039FFFF
03A0000–03AFFFF
03B0000–03BFFFF
03C0000–03CFFFF
03D0000–03DFFFF
03E0000–03EFFFF
03F0000–03FFFFF
0400000–040FFFF
0410000–041FFFF
0420000–042FFFF
0430000–043FFFF
0440000–044FFFF
0450000–045FFFF
0460000–046FFFF
0470000–047FFFF
0480000–048FFFF
0490000–049FFFF
04A0000–04AFFFF
04B0000–04BFFFF
40
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 4. Sector Address Table–S29GL128N (Continued)
8-Bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A22–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0980000–099FFFF
09A0000–09BFFFF
09C0000–09DFFFF
09E0000–09FFFFF
0A00000–0A1FFFF
0A20000–0A3FFFF
0A40000–0A5FFFF
0A60000–0A7FFFF
0A80000–0A9FFFF
0AA0000–0ABFFFF
0AC0000–0ADFFFF
0AE0000–0AFFFFF
0B00000–0B1FFFF
0B20000–0B3FFFF
0B40000–0B5FFFF
0B60000–0B7FFFF
0B80000–0B9FFFF
0BA0000–0BBFFFF
0BC0000–0BDFFFF
0BE0000–0BFFFFF
0C00000–0C1FFFF
0C20000–0C3FFFF
0C40000–0C5FFFF
0C60000–0C7FFFF
0C80000–0C9FFFF
0CA0000–0CBFFFF
0CC0000–0CDFFFF
0CE0000–0CFFFFF
0D00000–0D1FFFF
0D20000–0D3FFFF
0D40000–0D5FFFF
0D60000–0D7FFFF
0D80000–0D9FFFF
0DA0000–0DBFFFF
0DC0000–0DDFFFF
04C0000–04CFFFF
04D0000–04DFFFF
04E0000–04EFFFF
04F0000–04FFFFF
0500000–050FFFF
0510000–051FFFF
0520000–052FFFF
0530000–053FFFF
0540000–054FFFF
0550000–055FFFF
0560000–056FFFF
0570000–057FFFF
0580000–058FFFF
0590000–059FFFF
05A0000–05AFFFF
05B0000–05BFFFF
05C0000–05CFFFF
05D0000–05DFFFF
05E0000–05EFFFF
05F0000–05FFFFF
0600000–060FFFF
0610000–061FFFF
0620000–062FFFF
0630000–063FFFF
0640000–064FFFF
0650000–065FFFF
0660000–066FFFF
0670000–067FFFF
0680000–068FFFF
0690000–069FFFF
06A0000–06AFFFF
06B0000–06BFFFF
06C0000–06CFFFF
06D0000–06DFFFF
06E0000–06EFFFF
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
41
A d v a n c e I n f o r m a t i o n
Table 4. Sector Address Table–S29GL128N (Continued)
8-Bit
Sector Size
16-bit
Address Range
(in hexadecimal)
Address Range
(Kbytes/
Sector
A22–A16
(in hexadecimal)
Kwords)
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
128/64
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0DE0000–0DFFFFF
0E00000–0E1FFFF
0E20000–0E3FFFF
0E40000–0E5FFFF
0E60000–0E7FFFF
0E80000–0E9FFFF
0EA0000–0EBFFFF
0EC0000–0EDFFFF
0EE0000–0EFFFFF
0F00000–0F1FFFF
0F20000–0F3FFFF
0F40000–0F5FFFF
0F60000–0F7FFFF
0F80000–0F9FFFF
0FA0000–0FBFFFF
0FC0000–0FDFFFF
0FE0000–0FFFFFF
06F0000–06FFFFF
0700000–070FFFF
0710000–071FFFF
0720000–072FFFF
0730000–073FFFF
0740000–074FFFF
0750000–075FFFF
0760000–076FFFF
0770000–077FFFF
0780000–078FFFF
0790000–079FFFF
07A0000–07AFFFF
07B0000–07BFFFF
07C0000–07CFFFF
07D0000–07DFFFF
07E0000–07EFFFF
07F0000–07FFFFF
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
group protection verification, through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment to automatically match a
device to be programmed with its corresponding programming algorithm. How-
ever, the autoselect codes can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode requires VID on ad-
dress pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 5.
In addition, when verifying sector protection, the sector address must appear on
the appropriate highest order address bits (see Table 2). Table 5 shows the re-
maining address bits that are don’t care. When all necessary bits have been set
as required, the programming equipment may then read the corresponding iden-
tifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autose-
lect command via the command register, as shown in Table 12 and Table 13. This
method does not require VID. Refer to the Autoselect Command Sequence section
for more information.
42
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Table 5. Autoselect Codes, (High Voltage Method)
DQ8 to DQ15
A22 A14
to to
A15 A10
A8
to A6
A7
A5
to
A4
A3
to
A2
WE
#
Description
CE# OE#
A9
A1
A0
DQ7 to DQ0
BYTE#= BYTE#
VIH
= VIL
Manufacturer ID:
Spansion Product
L
L
H
X
X
V
ID
X
L
X
L
L
L
00
X
01h
Cycle 1
Cycle 2
Cycle 3
Cycle 1
Cycle 2
Cycle 3
Cycle 1
Cycle 2
Cycle 3
L
H
H
L
L
H
H
L
H
L
22
22
22
22
22
22
22
22
22
X
X
X
X
X
X
X
X
X
7Eh
23h
01h
7Eh
22h
01h
7Eh
21h
01h
L
L
H
X
X
V
X
L
X
ID
H
H
L
L
L
H
X
X
V
ID
X
L
X
H
H
L
H
H
L
H
H
L
L
L
H
X
X
V
ID
X
L
X
H
H
H
H
H
Sector Group
01h (protected),
L
L
H
SA
X
V
ID
X
L
X
L
H
L
X
X
Protection Verification
00h (unprotected)
SecSi Sector Indicator
Bit (DQ7), WP#
protects highest
address sector
98h (factory locked),
L
L
H
X
X
V
X
L
X
L
H
H
X
X
ID
18h (not factory locked)
SecSi Sector Indicator
Bit (DQ7), WP#
protects lowest
88h (factory locked),
L
L
H
X
X
V
ID
X
L
X
L
H
H
X
X
08h (not factory locked)
address sector
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection
The device features several levels of sector protection, which can disable both the
program and erase operations in certain sectors or sector groups:
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled pro-
tection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before
changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in the outermost
sectors.
The WP# Hardware Protection feature is always available, independent of the
software managed protection method chosen.
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The cus-
tomer must then choose if the Persistent or Password Protection method is most
desirable. There are two one-time programmable non-volatile bits that define
which sector protection method will be used. If the customer decides to continue
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
43
A d v a n c e I n f o r m a t i o n
using the Persistent Sector Protection method, they must set the Persistent
Sector Protection Mode Locking Bit. This will permanently set the part to op-
erate only using Persistent Sector Protection. If the customer decides to use the
password method, they must set the Password Mode Locking Bit. This will
permanently set the part to operate only using password sector protection.
It is important to remember that setting either the Persistent Sector Protec-
tion Mode Locking Bit or the Password Mode Locking Bit permanently
selects the protection mode. It is not possible to switch between the two methods
once a locking bit has been set. It is important that one mode is explicitly
selected when the device is first programmed, rather than relying on the
default mode alone. This is so that it is not possible for a system program or
virus to later set the Password Mode Locking Bit, which would cause an unex-
pected shift from the default Persistent Sector Protection Mode into the Password
Protection Mode.
The device is shipped with all sectors unprotected. The factory offers the option
of programming and protecting sectors at the factory prior to shipping the device
through the ExpressFlash™ Service. Contact your sales representative for details.
It is possible to determine whether a sector is protected or unprotected. See “Au-
toselect Command Sequence” section on page 56 for details.
Advanced Sector Protection
Advanced Sector Protection features several levels of sector protection, which can
disable both the program and erase operations in certain sectors.
Persistent Sector Protection is a method that replaces the old 12V controlled
protection method.
Password Sector Protection is a highly sophisticated protection method that
requires a password before changes to certain sectors are permitted.
Lock Register
The Lock Register consists of 3 bits (DQ2, DQ1, and DQ0). These DQ2, DQ1, DQ0
bits of the Lock Register are programmable by the user. Users are not allowed to
program both DQ2 and DQ1 bits of the Lock Register to the 00 state. If the user
tries to program DQ2 and DQ1 bits of the Lock Register to the 00 state, the device
will abort the Lock Register back to the default 11 state. The programming time
of the Lock Register is same as the typical word programming time without uti-
lizing the Write Buffer of the device. During a Lock Register programming
sequence execution, the DQ6 Toggle Bit I will toggle until the programming of the
Lock Register has completed to indicate programming status. All Lock Register
bits are readable to allow users to verify Lock Register statuses.
The Customer SecSi Sector Protection Bit is DQ0, Persistent Protection Mode Lock
Bit is DQ1, and Password Protection Mode Lock Bit is DQ2 are accessible by all
users. Each of these bits are non-volatile. DQ15-DQ3 are reserved and must be
1's when the user tries to program the DQ2, DQ1, and DQ0 bits of the Lock Reg-
ister. The user is not required to program DQ2, DQ1 and DQ0 bits of the Lock
Register at the same time. This allows users to lock the SecSi Sector and then set
the device either permanently into Password Protection Mode or Persistent Pro-
tection Mode and then lock the SEcSi Sector at separate instances and time
frames.
SecSi Sector Protection allows the user to lock the SecSi Sector area
44
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Persistent Protection Mode Lock Bit allows the user to set the device perma-
nently to operate in the Persistent Protection Mode
Password Protection Mode Lock Bit allows the user to set the device perma-
nently to operate in the Password Protection Mode
Table 6. Lock Register
DQ15-3
DQ2
DQ1
DQ0
Password Protection Persistent Protection
SecSi Sector
Protection Bit
Don’t Care
Mode Lock Bit Mode Lock Bit
Persistent Sector Protection
The Persistent Sector Protection method replaces the old 12 V controlled protec-
tion method while at the same time enhancing flexibility by providing three
different sector protection states:
Dynamically Locked-The sector is protected and can be changed by a sim-
ple command
Persistently Locked-A sector is protected and cannot be changed
Unlocked-The sector is unprotected and can be changed by a simple com-
mand
In order to achieve these states, three types of “bits” are going to be used:
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware
reset, the contents of all DYB bits are in the “unprotected state”. Each DYB is in-
dividually modifiable through the DYB Set Command and DYB Clear Command.
When the parts are first shipped, all of the Persistent Protect Bits (PPB) are
cleared into the unprotected state. The DYB bits and PPB Lock bit are defaulted
to power up in the cleared state or unprotected state - meaning the all PPB bits
are changeable.
The Protection State for each sector is determined by the logical OR of the PPB
and the DYB related to that sector. For the sectors that have the PPB bits cleared,
the DYB bits control whether or not the sector is protected or unprotected. By is-
suing the DYB Set and DYB Clear command sequences, the DYB bits will be
protected or unprotected, thus placing each sector in the protected or unpro-
tected state. These are the so-called Dynamic Locked or Unlocked states. They
are called dynamic states because it is very easy to switch back and forth be-
tween the protected and un-protected conditions. This allows software to easily
protect sectors against inadvertent changes yet does not prevent the easy re-
moval of protection when changes are needed.
The DYB bits maybe set or cleared as often as needed. The PPB bits allow for a
more static, and difficult to change, level of protection. The PPB bits retain their
state across power cycles because they are Non-Volatile. Individual PPB bits are
set with a program command but must all be cleared as a group through an erase
command.
The PPB Lock Bit adds an additional level of protection. Once all PPB bits are pro-
grammed to the desired settings, the PPB Lock Bit may be set to the “freeze
state”. Setting the PPB Lock Bit to the “freeze state” disables all program and
erase commands to the Non-Volatile PPB bits. In effect, the PPB Lock Bit locks the
PPB bits into their current state. The only way to clear the PPB Lock Bit to the
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
45
A d v a n c e I n f o r m a t i o n
“unfreeze state” is to go through a power cycle, or hardware reset. The Software
Reset command will not clear the PPB Lock Bit to the “unfreeze state”. System
boot code can determine if any changes to the PPB bits are needed e.g. to allow
new system code to be downloaded. If no changes are needed then the boot code
can set the PPB Lock Bit to disable any further changes to the PPB bits during
system operation.
The WP# write protect pin adds a final level of hardware protection. When this
pin is low it is not possible to change the contents of the WP# protected sectors.
These sectors generally hold system boot code. So, the WP# pin can prevent any
changes to the boot code that could override the choices made while setting up
sector protection during system initialization.
It is possible to have sectors that have been persistently locked, and sectors that
are left in the dynamic state. The sectors in the dynamic state are all unprotected.
If there is a need to protect some of them, a simple DYB Set command sequence
is all that is necessary. The DYB Set and DYB Clear commands for the dynamic
sectors switch the DYB bits to signify protected and unprotected, respectively. If
there is a need to change the status of the persistently locked sectors, a few more
steps are required. First, the PPB Lock Bit must be disabled to the “unfreeze
state” by either putting the device through a power-cycle, or hardware reset. The
PPB bits can then be changed to reflect the desired settings. Setting the PPB Lock
Bit once again to the “freeze state” will lock the PPB bits, and the device operates
normally again.
Note: to achieve the best protection, it's recommended to execute the PPB Lock
Bit Set command early in the boot code, and protect the boot code by holding
WP# = V .
IL
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to each sector. If a PPB
is programmed to the protected state through the “PPB Program” command, that
sector will be protected from program or erase operations will be read-only. If a
PPB requires erasure, all of the sector PPB bits must first be erased in parallel
through the “All PPB Erase” command. The “All PPB Erase” command will prepro-
grammed all PPB bits prior to PPB erasing. All PPB bits erase in parallel, unlike
programming where individual PPB bits are programmable. The PPB bits have the
same endurance as the flash memory.
Programming the PPB bit requires the typical word programming time without uti-
lizing the Write Buffer. During a PPB bit programming and A11 PPB bit erasing
sequence execution, the DQ6 Toggle Bit I will toggle until the programming of the
PPB bit or erasing of all PPB bits has completed to indicate programming and
erasing status. Erasing all of the PPB bits at once requires typical sector erase
time. During the erasing of all PPB bits, the DQ3 Sector Erase Timer bit will output
a 1 to indicate the erasure of all PPB bits are in progress. When the erasure of all
PPB bits has completed, the DQ3 Sector Erase Timer bit will output a 0 to indicate
that all PPB bits have been erased. Reading the PPB Status bit requires the initial
access time of the device.
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. When set to the “freeze state”, the PPB bits cannot be
changed. When cleared to the “unfreeze state”, the PPB bits are changeable.
There is only one PPB Lock Bit per device. The PPB Lock Bit is cleared to the “un-
46
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
freeze state” after power-up or hardware reset. There is no command sequence
to unlock or “unfreeze” the PPB Lock Bit.
Configuring the PPB Lock Bit to the freeze state requires approximately 100ns.
Reading the PPB Lock Status bit requires the initial access time of the device.
Table 7. Sector Protection Schemes
Protection States
Sector State
DYB Bit
PPB Bit
PPB Lock Bit
Unprotect
Unprotect
Unfreeze
Unprotected – PPB and DYB are changeable
Unprotected – PPB not changeable, DYB is
changeable
Unprotect
Unprotect
Freeze
Unprotect
Unprotect
Protect
Protect
Protect
Unfreeze
Freeze
Protected – PPB and DYB are changeable
Protected – PPB not changeable, DYB is changeable
Protected – PPB and DYB are changeable
Unprotect
Unprotect
Protect
Unfreeze
Freeze
Protect
Protected – PPB not changeable, DYB is changeable
Protected – PPB and DYB are changeable
Protect
Unfreeze
Freeze
Protect
Protect
Protected – PPB not changeable, DYB is changeable
Table 7 contains all possible combinations of the DYB bit, PPB bit, and PPB Lock
Bit relating to the status of the sector. In summary, if the PPB bit is set, and the
PPB Lock Bit is set, the sector is protected and the protection cannot be removed
until the next power cycle or hardware reset clears the PPB Lock Bit to “unfreeze
state”. If the PPB bit is cleared, the sector can be dynamically locked or unlocked.
The DYB bit then controls whether or not the sector is protected or unprotected.
If the user attempts to program or erase a protected sector, the device ignores
the command and returns to read mode. A program command to a protected sec-
tor enables status polling for approximately 1 µs before the device returns to read
mode without having modified the contents of the protected sector. An erase
command to a protected sector enables status polling for approximately 50 µs
after which the device returns to read mode without having erased the protected
sector. The programming of the DYB bit, PPB bit, and PPB Lock Bit for a given sec-
tor can be verified by writing a DYB Status Read, PPB Status Read, and PPB Lock
Status Read commands to the device.
The Autoselect Sector Protection Verification outputs the OR function of the DYB
bit and PPB bit per sector basis. When the OR function of the DYB bit and PPB bit
is a 1, the sector is either protected by DYB or PPB or both. When the OR function
of the DYB bit and PPB bit is a 0, the sector is unprotected through both the DYB
and PPB.
Persistent Protection Mode Lock Bit
Like the Password Protection Mode Lock Bit, a Persistent Protection Mode Lock Bit
exists to guarantee that the device remain in software sector protection. Once
programmed, the Persistent Protection Mode Lock Bit prevents programming of
the Password Protection Mode Lock Bit. This guarantees that a hacker could not
place the device in Password Protection Mode. The Password Protection Mode
Lock Bit resides in the “Lock Register”.
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
47
A d v a n c e I n f o r m a t i o n
Password Sector Protection
The Password Sector Protection method allows an even higher level of security
than the Persistent Sector Protection method. There are two main differences be-
tween the Persistent Sector Protection and the Password Sector Protection
methods:
When the device is first powered on, or comes out of a reset cycle, the PPB
Lock Bit is set to the locked state, or the freeze state, rather than cleared to
the unlocked state, or the unfreeze state.
The only means to clear and unfreeze the PPB Lock Bit is by writing a unique
64-bit Password to the device.
The Password Sector Protection method is otherwise identical to the Persistent
Sector Protection method.
A 64-bit password is the only additional tool utilized in this method.
The password is stored in a one-time programmable (OTP) region outside of the
flash memory. Once the Password Protection Mode Lock Bit is set, the password
is permanently set with no means to read, program, or erase it. The password is
used to clear and unfreeze the PPB Lock Bit. The Password Unlock command must
be written to the flash, along with a password. The flash device internally com-
pares the given password with the pre-programmed password. If they match, the
PPB Lock Bit is cleared to the “unfreezed state”, and the PPB bits can be altered.
If they do not match, the flash device does nothing. There is a built-in 2 µs delay
for each “password check” after the valid 64-bit password has been entered for
the PPB Lock Bit to be cleared to the “unfreezed state”. This delay is intended to
thwart any efforts to run a program that tries all possible combinations in order
to crack the password.
Password and Password Protection Mode Lock Bit
In order to select the Password Sector Protection method, the customer must first
program the password. The factory recommends that the password be somehow
correlated to the unique Electronic Serial Number (ESN) of the particular flash de-
vice. Each ESN is different for every flash device; therefore each password should
be different for every flash device. While programming in the password region,
the customer may perform Password Read operations. Once the desired pass-
word is programmed in, the customer must then set the Password Protection
Mode Lock Bit. This operation achieves two objectives:
1. It permanently sets the device to operate using the Password Protection Mode.
It is not possible to reverse this function.
2. It also disables all further commands to the password region. All program, and
read operations are ignored.
Both of these objectives are important, and if not carefully considered, may lead
to unrecoverable errors. The user must be sure that the Password Sector Protec-
tion method is desired when programming the Password Protection Mode Lock
Bit. More importantly, the user must be sure that the password is correct when
the Password Protection Mode Lock Bit is programmed. Due to the fact that read
operations are disabled, there is no means to read what the password is after-
wards. If the password is lost after programming the Password Protection Mode
Lock Bit, there will be no way to clear and unfreeze the PPB Lock Bit. The Pass-
word Protection Mode Lock Bit, once programmed, prevents reading the 64-bit
password on the DQ bus and further password programming. The Password Pro-
tection Mode Lock Bit is not erasable. Once Password Protection Mode Lock Bit is
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programmed, the Persistent Protection Mode Lock Bit is disabled from program-
ming, guaranteeing that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through
the use of the Password Program and Password Read commands. The password
function works in conjunction with the Password Protection Mode Lock Bit, which
when programmed, prevents the Password Read command from reading the con-
tents of the password on the pins of the device.
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. The PPB Lock Bit is a volatile bit that reflects the state of the
Password Protection Mode Lock Bit after power-up reset. If the Password Protec-
tion Mode Lock Bit is also programmed after programming the Password, the
Password Unlock command must be issued to clear and unfreeze the PPB Lock Bit
after a hardware reset (RESET# asserted) or a power-up reset. Successful exe-
cution of the Password Unlock command clears and unfreezes the PPB Lock Bit,
allowing for sector PPB bits to be modified. Without issuing the Password Unlock
command, while asserting RESET#, taking the device through a power-on reset,
or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a the “freeze
state”.
If the Password Protection Mode Lock Bit is not programmed, the device defaults
to Persistent Protection Mode. In the Persistent Protection Mode, the PPB Lock Bit
is cleared to the “unfreeze state” after power-up or hardware reset. The PPB Lock
Bit is set to the “freeze state” by issuing the PPB Lock Bit Set command. Once set
to the “freeze state” the only means for clearing the PPB Lock Bit to the “unfreeze
state” is by issuing a hardware or power-up reset. The Password Unlock com-
mand is ignored in Persistent Protection Mode.
Reading the PPB Lock Bit requires a 200ns access time.
SecSi (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that
enables permanent part identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator
Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from
the factory. This bit is permanently set at the factory and cannot be changed,
which prevents cloning of a factory locked part. This ensures the security of the
ESN once the product is shipped to the field.
The factory offers the device with the SecSi Sector either customer lockable
(standard shipping option) or factory locked (contact an AMD sales representa-
tive for ordering information). The customer-lockable version is shipped with the
SecSi Sector unprotected, allowing customers to program the sector after receiv-
ing the device. The customer-lockable version also has the SecSi Sector Indicator
Bit permanently set to a “0.” The factory-locked version is always protected when
shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit
permanently set to a “1.” Thus, the SecSi Sector Indicator Bit prevents customer-
lockable devices from being used to replace devices that are factory locked. Note
that the ACC function and unlock bypass modes are not available when the SecSi
Sector is enabled.
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A d v a n c e I n f o r m a t i o n
The SecSi sector address space in this device is allocated as follows:
ExpressFlash
Factory Locked
SecSi Sector Address Range
000000h–000007h
Customer Lockable
ESN Factory Locked
ESN
ESN or determined by
customer
Determined by customer
000008h–00007Fh
Unavailable
Determined by customer
The system accesses the SecSi Sector through a command sequence (see “Write
Protect (WP#)”). After the system has written the Enter SecSi Sector command
sequence, it may read the SecSi Sector by using the addresses normally occupied
by the first sector (SA0). This mode of operation continues until the system issues
the Exit SecSi Sector command sequence, or until power is removed from the de-
vice. On power-up, or following a hardware reset, the device reverts to sending
commands to sector SA0.
Customer Lockable: SecSi Sector NOT Programmed or Protected
At the Factory
Unless otherwise specified, the device is shipped such that the customer may
program and protect the 256-byte SecSi sector.
The system may program the SecSi Sector using the write-buffer, accelerated
and/or unlock bypass methods, in addition to the standard programming com-
mand sequence. See “Command Definitions” .
Programming and protecting the SecSi Sector must be used with caution since,
once protected, there is no procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory space can be modified in
any way.
The SecSi Sector area can be protected using one of the following procedures:
Write the three-cycle Enter SecSi Sector Region command sequence, and
then follow the in-system sector protect algorithm, except that RESET# may
be at either VIH or VID. This allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage. Note that this method is only
applicable to the SecSi Sector.
To verify the protect/unprotect status of the SecSi Sector, follow the algo-
rithm.
Once the SecSi Sector is programmed, locked and verified, the system must write
the Exit SecSi Sector Region command sequence to return to reading and writing
within the remainder of the array.
Factory Locked: SecSi Sector Programmed and Protected At the
Factory
In devices with an ESN, the SecSi Sector is protected when the device is shipped
from the factory. The SecSi Sector cannot be modified in any way. An ESN Factory
Locked device has an 16-byte random ESN at addresses 000000h–000007h.
Please contact your sales representative for details on ordering ESN Factory
Locked devices.
Customers may opt to have their code programmed by the factory through the
ExpressFlash service (Express Flash Factory Locked). The devices are then
shipped from the factory with the SecSi Sector permanently locked. Contact your
sales representative for details on using the ExpressFlash service.
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Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or
last sector group without using V . Write Protect is one of two functions provided
ID
by the WP#/ACC input.
If the system asserts V on the WP#/ACC pin, the device disables program and
IL
erase functions in the first or last sector group independently of whether those
sector groups were protected or unprotected using the method described in“Ad-
vanced Sector Protection” section on page 44. Note that if WP#/ACC is at V
IL
when the device is in the standby mode, the maximum input load current is in-
creased. See the table in “DC Characteristics” section on page 83.
If the system asserts VIH on the WP#/ACC pin, the device reverts to
whether the first or last sector was previously set to be protected or un-
protected using the method described in “Sector Group Protection and
Unprotection”. Note that WP# has an internal pullup; when uncon-
nected, WP# is at VIH
.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Table 12 and Table
13 for command definitions). In addition, the following hardware data protection
measures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during V power-up and power-down
CC
transitions, or from system noise.
Low V Write Inhibit
CC
When V is less than V , the device does not accept any write cycles. This pro-
CC
LKO
tects data during V power-up and power-down. The command register and all
CC
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until V is greater than V . The system
CC
LKO
must provide the proper signals to the control pins to prevent unintentional writes
when V is greater than V
CC
.
LKO
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V , CE# = V or WE# =
IL IH
V . To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
IH
logical one.
Power-Up Write Inhibit
If WE# = CE# = V and OE# = V during power up, the device does not accept
IL IH
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
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ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h, any time the device is ready to read array data.
The system can read CFI information at the addresses given in Tables 8-11. To
terminate reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 8–11. The system must write the reset
command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication
100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alter-
natively, contact your sales representative for copies of these documents.
Table 8. CFI Query Identification String
Addresses
(x16)
Addresses
(x8)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
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Table 9. System Interface String
Addresses
(x16)
Addresses
(x8)
Data
Description
V
Min. (write/erase)
CC
1Bh
1Ch
36h
0027h
D7–D4: volt, D3–D0: 100 millivolt
V
Max. (write/erase)
CC
38h
0036h
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0007h
0007h
000Ah
0000h
0001h
0005h
0004h
0000h
V
V
Min. voltage (00h = no V pin present)
PP
PP
PP
Max. voltage (00h = no V pin present)
PP
N
Typical timeout per single byte/word write 2 µs
N
Typical timeout for Min. size buffer write 2
µs (00h = not supported)
N
Typical timeout per individual block erase 2 ms
N
Typical timeout for full chip erase 2 ms (00h = not supported)
N
Max. timeout for byte/word write 2 times typical
N
Max. timeout for buffer write 2 times typical
N
Max. timeout per individual block erase 2 times typical
N
Max. timeout for full chip erase 2 times typical (00h = not supported)
September 29, 2004 27631A5
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A d v a n c e I n f o r m a t i o n
Table 10. Device Geometry Definition
Addresses
(x16)
Addresses
(x8)
Data
Description
001Ah
0019h
0018h
N
Device Size = 2 byte
27h
4Eh
1A = 512 Mb, 19 = 256 Mb, 18 = 128 Mb
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
N
2Ah
2Bh
54h
56h
0005h
0000h
Max. number of byte in multi-byte write = 2
(00h = not supported)
Number of Erase Block Regions within device (01h = uniform device,
02h = boot device)
2Ch
58h
0001h
Erase Block Region 1 Information
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
000xh
0000h
000xh
(refer to the CFI specification or CFI publication 100)
00FFh, 001h, 0000h, 0002h = 512 Mb
00FFh, 0000h, 0000h, 0002h = 256 Mb
007Fh, 0000h, 0000h, 0002h = 128 Mb
31h
32h
33h
34h
60h
64h
66h
68h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
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A d v a n c e I n f o r m a t i o n
Table 11. Primary Vendor-Specific Extended Query
Addresses
(x16)
Addresses
(x8)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
0010h
Process Technology (Bits 7-2) 0100b = 110 nm MirrorBit
Erase Suspend
46h
47h
48h
49h
4Ah
4Bh
4Ch
8Ch
8Eh
90h
92h
94h
96h
98h
0002h
0001h
0000h
0008h
0000h
0000h
0002h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
0008h = Advanced Sector Protection
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
9Ah
9Ch
00B5h
00C5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
WP# Protection
4Fh
50h
9Eh
A0h
00xxh
0001h
04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors
top WP# protect
Program Suspend
00h = Not Supported, 01h = Supported
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 12 and Table 13 define the valid register
command sequences. Writing incorrect address and data values or writing them
in the improper sequence may place the device in an unknown state. A reset com-
mand is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing diagrams.
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Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the
erase-suspend-read mode, after which the system can read data from any non-
erase-suspended sector. After completing a programming operation in the Erase
Suspend mode, the system may once again read array data with the same ex-
ception. See the Erase Suspend/Erase Resume Commands section for more
information.
The system must issue the reset command to return the device to the read (or
erase-suspend-read) mode if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode. See the next section, Reset
Command, for more information.
See also Requirements for Reading Array Data in the Device Bus Operations sec-
tion for more information. The Read-Only Operations–“AC Characteristics”
section provides the read parameters, and Figure 11 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ignores reset commands until
the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the device to the
read mode. If the program command sequence is written while the device is in
the Erase Suspend mode, writing the reset command returns the device to the
erase-suspend-read mode. Once programming begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If the device entered the autoselect mode
while in the Erase Suspend mode, writing the reset command returns the device
to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command
returns the device to the read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Programming operation, the sys-
tem must write the Write-to-Buffer-Abort Reset command sequence to reset the
device for the next operation.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manu-
facturer and device codes, and determine whether or not a sector is protected.
Table 12 and Table 13 show the address and data requirements. This method is
an alternative to that shown in Table 5, which is intended for PROM programmers
and requires V on address pin A9. The autoselect command sequence may be
ID
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A d v a n c e I n f o r m a t i o n
written to an address that is either in the read or erase-suspend-read mode. The
autoselect command may not be written while the device is actively programming
or erasing.
The autoselect command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system may read at any address any
number of times without initiating another autoselect command sequence:
A read cycle at address XX00h returns the manufacturer code.
Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code.
A read cycle to an address containing a sector address (SA), and the address
02h on A7–A0 in word mode returns 01h if the sector is protected, or 00h if
it is unprotected.
The system must write the reset command to return to the read mode (or erase-
suspend-read mode if the device was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing an 8-word/16-
byte random Electronic Serial Number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi Sector command sequence.
The device continues to access the SecSi Sector region until the system issues
the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector com-
mand sequence returns the device to normal operation. Table 12 shows the
address and data requirements for both command sequences. See also “SecSi
(Secured Silicon) Sector Flash Memory Region” for further information. Note that
the ACC function and unlock bypass modes are not available when the SecSi Sec-
tor is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up com-
mand. The program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to provide further con-
trols or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin. Table 12 and Table 13 show the
address and data requirements for the word program command sequence.
When the Embedded Program algorithm is complete, the device then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by using DQ7 or DQ6. Refer to the Write Op-
eration Status section for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that the SecSi Sector, autoselect, and CFI functions are
unavailable when a program operation is in progress. Note that a hard-
ware reset immediately terminates the program operation. The program
command sequence should be reinitiated once the device has returned to the
read mode, to ensure data integrity.
Programming is allowed in any sequence of address locations and across sector
boundaries. Programming to the same word address multiple times without in-
tervening erases (incremental bit programming) requires a modified
programming method. For such application requirements, please contact your
local Spansion representative. Word programming is supported for backward
compatibility with existing Flash driver software and for occasional writing of in-
September 29, 2004 27631A5
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A d v a n c e I n f o r m a t i o n
dividual words. Use of Write Buffer Programming is strongly recommended for
general programming use when more than a few words are to be programmed.
The effective word programming time using Write Buffer Programming is much
shorter than the single word programming time. Any word cannot be pro-
grammed from “0” back to a “1.” Attempting to do so may cause the device
to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation
was successful. However, a succeeding read will show that the data is still “0.”
Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program com-
mand sequence is all that is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program command, A0h; the second
cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required
in the standard program command sequence, resulting in faster total program-
ming time. Table 12 and Table 13 show the requirements for the command
sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. (See Table 12
and Table 13).
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32
bytes in one programming operation. This results in faster effective programming
time than the standard programming algorithms. The Write Buffer Programming
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load command written at the
Sector Address in which programming will occur. The fourth cycle writes the sec-
tor address and the number of word locations, minus one, to be programmed. For
example, if the system will program 6 unique address locations, then 05h should
be written to the device. This tells the device how many write buffer addresses
will be loaded with data and therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot exceed the size of the
write buffer or the operation will abort.
The fifth cycle writes the first address location and data to be programmed. The
write-buffer-page is selected by address bits A
–A . All subsequent address/
4
MAX
data pairs must fall within the selected-write-buffer-page. The system then
writes the remaining address/data pairs into the write buffer. Write buffer loca-
tions may be loaded in any order.
The write-buffer-page address must be the same for all address/data pairs loaded
into the write buffer. (This means Write Buffer Programming cannot be performed
across multiple write-buffer pages. This also means that Write Buffer Program-
ming cannot be performed across multiple sectors. If the system attempts to load
programming data outside of the selected write-buffer page, the operation will
abort.)
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A d v a n c e I n f o r m a t i o n
Note that if a Write Buffer address location is loaded multiple times, the address/
data pair counter will be decremented for every data load operation. The host
system must therefore account for loading a write-buffer location more than
once. The counter decrements for each data load operation, not for each unique
write-buffer-address location. Note also that if an address location is loaded more
than once into the buffer, the final data loaded for that address will be
programmed.
Once the specified number of write buffer locations have been loaded, the system
must then write the Program Buffer to Flash command at the sector address. Any
other address and data combination aborts the Write Buffer Programming oper-
ation. The device then begins programming. Data polling should be used while
monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5,
and DQ1 should be monitored to determine the device status during Write Buffer
Programming.
The write-buffer programming operation can be suspended using the standard
program suspend/resume commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to execute the next command.
The Write Buffer Programming Sequence can be aborted in the following ways:
Load a value that is greater than the page buffer size during the Number of
Locations to Program step.
Write to an address in a sector different than the one specified during the
Write-Buffer-Load command.
Write an Address/Data pair to a different write-buffer-page than the one se-
lected by the Starting Address during the write buffer data loading stage of
the operation.
Write data other than the Confirm Command after the specified number of
data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address
location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset com-
mand sequence must be written to reset the device for the next operation. Note
that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required
when using Write-Buffer-Programming features in Unlock Bypass mode.
Write buffer programming is allowed in any sequence. Note that the SecSi sector,
autoselect, and CFI functions are unavailable when a program operation is in
progress. This flash device is capable of handling multiple write buffer program-
ming operations on the same write buffer address range without intervening
erases. For applications requiring incremental bit programming, a modified pro-
gramming method is required, please contact your local Spansion representative.
Any bit in a write buffer address range cannot be programmed from “0”
back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or
cause the DQ7 and DQ6 status bits to indicate the operation was successful. How-
ever, a succeeding read will show that the data is still “0.” Only erase operations
can convert a “0” to a “1.”
Accelerated Program
The device offers accelerated program operations through the WP#/ACC pin.
When the system asserts V
on the WP#/ACC pin, the device automatically en-
HH
ters the Unlock Bypass mode. The system may then write the two-cycle Unlock
Bypass program command sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not
September 29, 2004 27631A5
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A d v a n c e I n f o r m a t i o n
be at VHH for operations other than accelerated programming, or device damage
may result. WP# has an internal pullup; when unconnected, WP# is at VIH
.
Figure 2 illustrates the algorithm for the program operation. Refer to the Erase
and Program Operations–“AC Characteristics” section for parameters, and Figure
14 for timing diagrams.
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Buffer Operation?
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
(Note 1)
Write next address/data pair
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Notes:
1. When Sector Address is specified, any
address in the selected sector is acceptable.
However, when loading Write-Buffer
address locations with data, all addresses
must fall within the selected Write-Buffer
Page.
Read DQ15 - DQ0 at
Last Loaded Address
2. DQ7 may change simultaneously with DQ5.
Therefore, DQ7 should be verified.
Yes
DQ7 = Data?
No
3. If this flowchart location was reached
because DQ5= “1”, then the device FAILED.
If this flowchart location was reached
because DQ1= “1”, then the Write to Buffer
operation was ABORTED. In either case, the
proper reset command must be written
before the device can begin another
operation. If DQ1=1, write the Write-
Buffer-Programming-Abort-Reset
No
No
DQ1 = 1?
Yes
DQ5 = 1?
Yes
Read DQ15 - DQ0 with
address = Last Loaded
Address
command. if DQ5=1, write the Reset
command.
4. See Table 12 and Table 13 for command
sequences required for write buffer
programming.
Yes
(Note 2)
DQ7 = Data?
No
(Note 3)
FAIL or ABORT
PASS
Figure 1. Write Buffer Programming Operation
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A d v a n c e I n f o r m a t i o n
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Table 12 and Table 13 for program com-
mand sequence.
Figure 2. Program Operation
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming
operation or a Write to Buffer programming operation so that data can be read
from any non-suspended sector. When the Program Suspend command is written
during a programming process, the device halts the program operation within 15
µs maximum (5µs typical) and updates the status bits. Addresses are not re-
quired when writing the Program Suspend command.
After the programming operation has been suspended, the system can read array
data from any non-suspended sector. The Program Suspend command may also
be issued during a programming operation while an erase is suspended. In this
case, data may be read from any addresses not in Erase Suspend or Program
Suspend. If a read is needed from the SecSi Sector area (One-time Program
area), then user must use the proper command sequences to enter and exit this
region. Note that the SecSi Sector autoselect, and CFI functions are unavailable
when program operation is in progress.
The system may also write the autoselect command sequence when the device
is in the Program Suspend mode. The system can read as many autoselect codes
as required. When the device exits the autoselect mode, the device reverts to the
Program Suspend mode, and is ready for another valid operation. See Autoselect
Command Sequence for more information.
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A d v a n c e I n f o r m a t i o n
After the Program Resume command is written, the device reverts to program-
ming. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See Write Op-
eration Status for more information.
The system must write the Program Resume command (address bits are don’t
care) to exit the Program Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ignored. Another Program
Suspend command can be written after the device has resume programming.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Write address/data
XXXh/B0h
Command is also valid for
Erase-suspended-program
operations
Wait 15 µs
Autoselect and SecSi Sector
read operations are also allowed
Read data as
required
Data cannot be read from erase- or
program-suspended sectors
Done
No
reading?
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Figure 3. Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Table 12 and Table 13 show the address and data
requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation
Status section for information on these status bits.
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Any commands written during the chip erase operation are ignored, including
erase suspend commands. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the chip erase command sequence
should be reinitiated once the device has returned to reading array data, to en-
sure data integrity.
Figure 4 illustrates the algorithm for the erase operation. Note that the SecSi
Sector, autoselect, and CFI functions are unavailable when an erase op-
eration in is progress. Refer to the Erase and Program Operations table in the
AC Characteristics section for parameters, and Figure 16 section for timing
diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table 12 and Table 13 shows
the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 µs, otherwise erasure
may begin. Any sector erase address and command following the exceeded time-
out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written. Any com-
mand other than Sector Erase or Erase Suspend during the time-out
period resets the device to the read mode. Note that the SecSi Sector,
autoselect, and CFI functions are unavailable when an erase operation
in is progress. The system must rewrite the command sequence and any addi-
tional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector.
Refer to the Write Operation Status section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and
Program Operations table in the AC Characteristics section for parameters, and
Figure 16 section for timing diagrams.
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A d v a n c e I n f o r m a t i o n
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 12 and Table 13 for program command
sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 4. Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase
operation and then read data from, or program data to, any sector not selected
for erasure. This command is valid only during the sector erase operation, includ-
ing the 50 µs time-out period during the sector erase command sequence. The
Erase Suspend command is ignored if written during the chip erase operation or
Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation,
the device requires a typical of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend command is written during the sec-
tor erase time-out, the device immediately terminates the time-out period and
suspends the erase operation.
After the erase operation has been suspended, the device enters the erase-sus-
pend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for
erasure.) Reading at any address within erase-suspended sectors produces sta-
tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer
to the Write Operation Status section for information on these status bits.
After an erase-suspended program operation is complete, the device returns to
the erase-suspend-read mode. The system can determine the status of the pro-
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gram operation using the DQ7 or DQ6 status bits, just as in the standard word
program operation. Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also issue the autoselect com-
mand sequence. Refer to the “Autoselect Mode” section and “Autoselect
Command Sequence” section on page 56 sections for details.
To resume the sector erase operation, the system must write the Erase Resume
command. The address of the erase-suspended sector is required when writing
this command. Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip has resumed erasing. It is
important to allow an interval of at least 5 ms between Erase Resume and Erase
Suspend.
Lock Register Command Set Definitions
The Lock Register Command Set permits the user to one-time program the SecSi
Sector Protection Bit, Persistent Protection Mode Lock Bit, and Password Protec-
tion Mode Lock Bit. The Lock Register bits are all readable after an initial access
delay.
The Lock Register Command Set Entry command sequence must be issued
prior to any of the following commands listed, to enable proper command
execution.
Note that issuing the Lock Register Command Set Entry command disables
reads and writes for the flash memory.
Lock Register Program Command
Lock Register Read Command
The Lock Register Command Set Exit command must be issued after the ex-
ecution of the commands to reset the device to read mode. Otherwise the device
will hang. If this happens, the flash device must be reset. Please refer to RESET#
for more information. It is important to note that the device will be in either Per-
sistent Protection mode or Password Protection mode depending on the mode
selected prior to the device hang.
For either the SecSi Sector to be locked, or the device to be permanently set to
the Persistent Protection Mode or the Password Protection Mode, the associated
Lock Register bits must be programmed. Note that the Persistent Protection
Mode Lock Bit and Password Protection Mode Lock Bit can never be pro-
grammed together at the same time. If so, the Lock Register Program
operation will abort.
The Lock Register Command Set Exit command must be initiated to re-
enable reads and writes to the main memory.
Password Protection Command Set Definitions
The Password Protection Command Set permits the user to program the 64-bit
password, verify the programming of the 64-bit password, and then later unlock
the device by issuing the valid 64-bit password.
The Password Protection Command Set Entry command sequence must be
issued prior to any of the commands listed following to enable proper command
execution.
Note that issuing the Password Protection Command Set Entry command
disabled reads and writes the main memory.
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A d v a n c e I n f o r m a t i o n
Password Program Command
Password Read Command
Password Unlock Command
The Password Program command permits programming the password that is
used as part of the hardware protection scheme. The actual password is 64-bits
long. There is no special addressing order required for programming the pass-
word. The password is programmed in 8-bit or 16-bit portions. Each
portion requires a Password Program Command.
Once the Password is written and verified, the Password Protection Mode Lock Bit
in the “Lock Register” must be programmed in order to prevent verification. The
Password Program command is only capable of programming “0”s. Programming
a “1” after a cell is programmed as a “0” results in a time-out by the Embedded
TM
Program Algorithm with the cell remaining as a “0”. The password is all F’s when
shipped from the factory. All 64-bit password combinations are valid as a
password.
The Password Read command is used to verify the Password. The Password is
verifiable only when the Password Protection Mode Lock Bit in the “Lock Register”
is not programmed. If the Password Protection Mode Lock Bit in the “Lock Regis-
ter” is programmed and the user attempts to read the Password, the device will
always drive all F’s onto the DQ databus.
The lower two address bits (A1–A0) for word mode and (A1–A-1) for by byte
mode are valid during the Password Read, Password Program, and Password Un-
lock commands. Writing a “1” to any other address bits (AMAX-A2) will
abort the Password Read and Password Program commands.
The Password Unlock command is used to clear the PPB Lock Bit to the “unfreeze
state” so that the PPB bits can be modified. The exact password must be entered
in order for the unlocking function to occur. This 64-bit Password Unlock com-
mand sequence will take at least 2 µs to process each time to prevent a
hacker from running through the all 64-bit combinations in an attempt
to correctly match the password. If another password unlock is issued
before the 64-bit password check execution window is completed, the
command will be ignored. If the wrong address or data is given during
password unlock command cycle, the device may enter the write-to-
buffer abort state. In order to exit the write-to-abort state, the write-to-
buffer-abort-reset command must be given. Otherwise the device will
hang.
The Password Unlock function is accomplished by writing Password Unlock com-
mand and data to the device to perform the clearing of the PPB Lock Bit to the
“unfreeze state”. The password is 64 bits long. A1 and A0 are used for matching
in word mode and A1, A0, A-1 in byte mode. Writing the Password Unlock com-
mand does not need to be address order specific. An example sequence is
starting with the lower address A1-A0=00, followed by A1-A0=01, A1-A0=10,
and A1-A0=11 if the device is configured to operate in word mode.
Approximately 2 µs is required for unlocking the device after the valid
64-bit password is given to the device. It is the responsibility of the mi-
croprocessor to keep track of the entering the portions of the 64-bit
password with the Password Unlock command, the order, and when to
read the PPB Lock bit to confirm successful password unlock. In order to
re-lock the device into the Password Protection Mode, the PPB Lock Bit Set com-
mand can be re-issued.
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The Password Protection Command Set Exit command must be issued after
the execution of the commands listed previously to reset the device to read
mode. Otherwise the device will hang.
Note that issuing the Password Protection Command Set Exit command re-
enables reads and writes for the main memory.
Non-Volatile Sector Protection Command Set Definitions
The Non-Volatile Sector Protection Command Set permits the user to program the
Persistent Protection Bits (PPB bits), erase all of the Persistent Protection Bits
(PPB bits), and read the logic state of the Persistent Protection Bits (PPB bits).
The Non-Volatile Sector Protection Command Set Entry command se-
quence must be issued prior to any of the commands listed following to enable
proper command execution.
Note that issuing the Non-Volatile Sector Protection Command Set Entry
command disables reads and writes for the main memory.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB bit. Each PPB
bit is individually programmed (but is bulk erased with the other PPB bits). The
specific sector address (A24-A16 for S29GL512N, A23-A16 for S29GL256N, A22-
A16 for S29GL128N) is written at the same time as the program command. If the
PPB Lock Bit is set to the “freeze state”, the PPB Program command will not exe-
cute and the command will time-out without programming the PPB bit.
All PPB Erase Command
The All PPB Erase command is used to erase all PPB bits in bulk. There is no
means for individually erasing a specific PPB bit. Unlike the PPB program, no spe-
cific sector address is required. However, when the All PPB Erase command is
issued, all Sector PPB bits are erased in parallel. If the PPB Lock Bit is set to
“freeze state”, the ALL PPB Erase command will not execute and the command
will time-out without erasing the PPB bits.
The device will preprogram all PPB bits prior to erasing when issuing the All PPB
Erase command. Also note that the total number of PPB program/erase cycles has
the same endurance as the flash memory array.
PPB Status Read Command
The programming state of the PPB for a given sector can be verified by writing a
PPB Status Read Command to the device. This requires an initial access time
latency.
The Non-Volatile Sector Protection Command Set Exit command must be
issued after the execution of the commands listed previously to reset the device
to read mode.
Note that issuing the Non-Volatile Sector Protection Command Set Exit
command re-enables reads and writes for the main memory.
Global Volatile Sector Protection Freeze Command Set
The Global Volatile Sector Protection Freeze Command Set permits the user to set
the PPB Lock Bit and reading the logic state of the PPB Lock Bit.
The Global Volatile Sector Protection Freeze Command Set Entry com-
mand sequence must be issued prior to any of the commands listed following to
enable proper command execution.
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A d v a n c e I n f o r m a t i o n
Reads and writes from the main memory are not allowed.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock Bit to the “freeze state”
if it is cleared either at reset or if the Password Unlock command was successfully
executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set
to the “freeze state”, it cannot be cleared unless the device is taken through a
power-on clear (for Persistent Protection Mode) or the Password Unlock command
is executed (for Password Protection Mode). If the Password Protection Mode Lock
Bit is programmed, the PPB Lock Bit status is reflected as set to the “freeze state”,
even after a power-on reset cycle.
PPB Lock Bit Status Read Command
The programming state of the PPB Lock Bit can be verified by executing a PPB
Lock Bit Status Read command to the device.
The Global Volatile Sector Protection Freeze Command Set Exit command
must be issued after the execution of the commands listed previously to reset the
device to read mode.
Volatile Sector Protection Command Set
The Volatile Sector Protection Command Set permits the user to set the Dynamic
Protection Bit (DYB) to the “protected state”, clear the Dynamic Protection Bit
(DYB) to the “unprotected state”, and read the logic state of the Dynamic Protec-
tion Bit (DYB).
The Volatile Sector Protection Command Set Entry command sequence
must be issued prior to any of the commands listed following to enable proper
command execution.
Note that issuing the Volatile Sector Protection Command Set Entry com-
mand disables reads and writes from main memory.
DYB Set Command
DYB Clear Command
The DYB Set and DYB Clear commands are used to protect or unprotect a DYB for
a given sector. The high order address bits are issued at the same time as the
code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are ignored during the
data write cycle. The DYB bits are modifiable at any time, regardless of the state
of the PPB bit or PPB Lock Bit. The DYB bits are cleared to the “unprotected state”
at power-up or hardware reset.
—DYB Status Read Command
The programming state of the DYB bit for a given sector can be verified by writing
a DYB Status Read command to the device. This requires an initial access delay.
The Volatile Sector Protection Command Set Exit command must be issued
after the execution of the commands listed previously to reset the device to read
mode.
Note that issuing the Volatile Sector Protection Command Set Exit com-
mand re-enables reads and writes to the main memory.
SecSi Sector Entry Command
The SecSi Sector Entry command allows the following commands to be executed
Read from SecSi Sector
Program to SecSi Sector
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Once the SecSi Sector Entry Command is issued, the SecSi Sector Exit command
has to be issued to exit SecSi Sector Mode.
SecSi Sector Exit Command
The SecSi Sector Exit command may be issued to exit the SecSi Sector Mode.
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A d v a n c e I n f o r m a t i o n
Command Definitions
Table 12. S29GL512N, S29GL256N, S29GL128N Command Definitions, x16
Bus Cycles (Notes 2–5)
Command (Notes)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (6)
1
1
4
RA
RD
F0
Reset (7)
XXX
555
Manufacturer ID
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
01
Note
17
Note
17
Device ID
4
4
4
555
555
555
AA
AA
AA
227E
X0E
X0F
XX00
XX01
(SA)
X02
Sector Protect Verify
2AA
2AA
55
55
555
555
90
90
Note
10
Secure Device Verify (9)
X03
CFI Query (11)
1
4
3
1
3
3
2
2
2
2
6
6
1
1
55
98
AA
AA
29
AA
AA
A0
80
80
90
AA
AA
B0
30
Program
555
555
SA
2AA
2AA
55
55
555
SA
A0
25
PA
SA
PD
Write to Buffer
WC
PA
PD
WBL
PD
Program Buffer to Flash (confirm)
Write-to-Buffer-Abort Reset (16)
Unlock Bypass
555
555
XXX
XXX
XXX
XXX
555
555
XXX
XXX
2AA
2AA
PA
55
55
PD
30
10
00
55
55
555
555
F0
20
Unlock Bypass Program (12)
Unlock Bypass Sector Erase (12)
Unlock Bypass Chip Erase (12)
Unlock Bypass Reset (13)
Chip Erase
SA
XXX
XXX
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend/Program Suspend (14)
Erase Resume/Program Resume (15)
Sector Command Definitions
SecSi Sector Entry
3
555
AA
2AA
55
555
88
90
SecSi Sector Exit (18)
4
555
AA
2AA
55
555
XX
00
Lock Register Command Set Definitions
Lock Register Command Set Entry
Lock Register Bits Program (22)
Lock Register Bits Read (22)
3
2
1
2
555
XXX
00
AA
2AA
55
555
40
A0
XXX
Data
Data
90
Lock Register Command Set Exit (18, 23)
XXX
XXX
00
Password Protection Command Set Definitions
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A d v a n c e I n f o r m a t i o n
Bus Cycles (Notes 2–5)
Third Fourth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command (Notes)
First
Second
Fifth
Sixth
Password Protection Command Set Entry
3
2
555
AA
2AA
55
555
60
PWA
x
PWD
x
Password Program (20)
Password Read (19)
XXX
A0
PWD
0
PWD
1
PWD
2
PWD
3
4
7
2
XXX
01
00
02
00
03
01
PWD
0
PWD
1
PWD
PWD
00
00
25
29
90
03
02
03
2
3
Password Unlock (19)
Password Protection Command Set Exit (18,
23)
XXX
XXX
00
Non-Volatile Sector Protection Command Set Definitions
Nonvolatile Sector Protection Command Set
Entry
3
555
AA
2AA
55
555
C0
PPB Program (24, 25)
All PPB Erase
2
2
XXX
XXX
A0
80
SA
00
00
30
RD
(0)
PPB Status Read (25)
1
2
SA
Non-Volatile Sector Protection Command Set
Exit (18)
XXX
90
XXX
00
Global Non-Volatile Sector Protection Freeze Command Set Definitions
Global Non-Volatile Sector Protection Freeze
Command Set Entry
3
2
1
555
XXX
XXX
AA
A0
2AA
XXX
55
00
555
50
PPB Lock Bit Set (25)
RD
(0)
PPB Lock Status Read (25)
Global Non-Volatile Sector Protection Freeze
Command Set Exit (18)
2
XXX
90
XXX
00
Volatile Sector Protection Command Set Definitions
Volatile Sector Protection Command Set Entry
3
2
2
555
XXX
XXX
AA
A0
A0
2AA
55
00
01
555
E0
DYB Set (24, 25)
SA
DYB Clear (25)
SA
RD
(0)
DYB Status Read (25)
1
2
SA
Volatile Sector Protection Command Set Exit
(18)
XXX
90
XXX
00
Legend:
X = Don’t care
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A16 uniquely select any sector.
WBL = Write Buffer Location. The address must be within the same write buffer page as PA.
September 29, 2004 27631A5
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A d v a n c e I n f o r m a t i o n
WC = Word Count is the number of write buffer locations to load minus 1.
PWD = Password
PWDx = Password word0, word1, word2, and word3.
DATA = Lock Register Contents: PD(0) = SecSi Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2) =
Password Protection Mode Lock Bit.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write
cycles.
4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles.
5. Address bits AMAX:A16 are don't cares for unlock and command cycles, unless SA or PA required. (AMAX is the Highest
Address pin.).
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status data).
8. The fourth, fifth, and sixth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more
information. This is same as PPB Status Read except that the protect and unprotect statuses are inverted here.
10. The data value for DQ7 is “1” for a serialized and protected OTP region and “0” for an unserialized and unprotected
SecSi™Sector region. See “SecSi™ Sector Flash Memory Region” for more information. For S29GLxxxNH: XX18h/18h = Not
Factory Locked. XX98h/98h = Factory Locked. For S29GLxxxNL: XX08h/08h = Not Factory Locked. XX88h/88h = Factory
Locked.
11. Command is valid when device is ready to read array data or when device is in autoselect mode.
12. The Unlock-Bypass command is required prior to the Unlock-Bypass-Program command.
13. The Unlock-Bypass-Reset command is required to return to reading array data when the device is in the unlock bypass
mode.
14. The system may read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the
Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
15. The Erase Resume/Program Resume command is valid only during the Erase Suspend/Program Suspend modes.
16. Issue this command sequence to return to READ mode after detecting device is in a Write-to-Buffer-Abort state. NOTE: the
full command sequence is required if resetting out of ABORT while using Unlock Bypass Mode.
17. S29GL512NH/L = 2223h/23h, 2201h/01h; S29GL256NH/L = 2222h/22h, 2201h/01h; S29GL128NH/L = 2221h/21h, 2201h/
01h.
18. The Exit command returns the device to reading the array.
19. Note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
20. For PWDx, only one portion of the password can be programmed per each “A0” command.
21. The All PPB Erase command embeds programming of all PPB bits before erasure.
22. All Lock Register bits are one-time programmable. Note that the program state = “0” and the erase state = “1”. Also note
that of both the Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the
same time or the Lock Register Bits Program operation will abort and return the device to read mode. Lock Register bits that
are reserved for future use will default to “1's”. The Lock Register is shipped out as “FFFF's” before Lock Register Bit program
execution.
23. If any of the Entry command was initiated, an Exit command must be issued to reset the device into read mode. Otherwise
the device will hang.
24. If ACC = VHH, sector protection will match when ACC = VIH
25. Protected State = “00h”, Unprotected State = “01h”.
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Table 13. S29GL512N, S29GL256N, S29GL128N Command Definitions, x8
Bus Cycles (Notes 2–5)
Command (Notes)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (6)
1
1
4
RA
RD
F0
Reset (7)
XXX
AAA
Manufacturer ID
AA
555
555
55
55
AAA
AAA
90
90
X00
X02
01
Note
17
Note
17
Device ID
4
4
4
AAA
AAA
AAA
AA
AA
AA
XX7E
X1C
X1E
00
01
(SA)
X04
Sector Protect Verify
555
555
55
55
AAA
AAA
90
90
Note
10
Secure Device Verify (9)
X06
CFI Query (11)
1
3
1
3
6
6
1
1
AA
98
AA
29
AA
AA
AA
B0
30
Write to Buffer
AAA
SA
555
55
SA
25
SA
WC
PA
PD
WBL
PD
Program Buffer to Flash (confirm)
Write-to-Buffer-Abort Reset (16)
Chip Erase
AAA
AAA
AAA
XXX
XXX
PA
55
55
55
555
AAA
AAA
F0
80
80
555
555
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Erase Suspend/Program Suspend (14)
Erase Resume/Program Resume (15)
SecSi Sector Command Definitions
SecSi Sector Entry
3
AAA
AA
555
55
AAA
88
SecSi Sector Exit (18)
4
AAA
AA
555
55
AAA
90
XX
00
Lock Register Command Set Definitions
Lock Register Command Set Entry
Lock Register Bits Program (22)
Lock Register Bits Read (22)
3
2
1
2
AAA
XXX
00
AA
555
55
AAA
40
A0
XXX
Data
Data
90
Lock Register Command Set Exit (18, 23)
XXX
XXX
00
Password Protection Command Set Definitions
Password Protection Command Set Entry
3
AAA
AA
555
55
AAA
60
PWA PWD
Password Program (20)
2
XXX
A0
x
x
PWD
0
PWD
1
00
06
01
PWD
2
PWD
3
PWD
4
PWD
5
Password Read (19)
8
02
03
04
05
PWD
6
PWD
7
07
00
PWD
0
PWD
1
PWD
2
PWD
3
00
25
03
00
06
01
07
02
00
03
Password Unlock (19)
11
PWD
4
PWD
5
PWD
6
PWD
7
04
05
29
Password Protection Command Set Exit
(18, 23)
2
XXX
90
XXX
00
September 29, 2004 27631A5
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A d v a n c e I n f o r m a t i o n
Bus Cycles (Notes 2–5)
Command (Notes)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Non-Volatile Sector Protection Command Set Definitions
Nonvolatile Sector Protection Command
Set Entry
3
AAA
AA
55
55
AAA
C0
PPB Program (24, 25)
All PPB Erase
2
2
XXX
XXX
A0
80
SA
00
00
30
RD
(0)
PPB Status Read (25)
1
2
SA
Non-Volatile Sector Protection Command
Set Exit (18)
XXX
90
XXX
00
Global Non-Volatile Sector Protection Freeze Command Set Definitions
Global Non-Volatile Sector Protection
Freeze Command Set Entry
3
2
1
AAA
XXX
XXX
AA
A0
555
XXX
55
00
AAA
50
PPB Lock Bit Set (25)
RD
(0)
PPB Lock Status Read (25)
Global Non-Volatile Sector Protection
Freeze Command Set Exit (18)
2
XXX
90
XXX
00
Volatile Sector Protection Command Set Definitions
Volatile Sector Protection Command Set
Entry
3
AAA
AA
555
55
AAA
E0
DYB Set (24, 25)
DYB Clear (25)
2
2
XXX
XXX
A0
A0
SA
SA
00
01
RD
(0)
DYB Status Read (25)
1
2
SA
Volatile Sector Protection Command Set
Exit (18)
XXX
90
XXX
00
Legend:
X = Don’t care
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A16 uniquely select any sector.
WBL = Write Buffer Location. The address must be within the same write buffer page as PA.
WC = Word Count is the number of write buffer locations to load minus 1.
PWD = Password
PWDx = Password word0, word1, word2, word3. word 4, word 5, word 6, and word 7.
DATA = Lock Register Contents: PD(0) = SecSi Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2) =
Password Protection Mode Lock Bit.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write
cycles.
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4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles.
5. Address bits AMAX:A16 are don't cares for unlock and command cycles, unless SA or PA required. (AMAX is the Highest
Address pin.).
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status data).
8. The fourth, fifth, and sixth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more
information. This is same as PPB Status Read except that the protect and unprotect statuses are inverted here.
10. The data value for DQ7 is “1” for a serialized and protected OTP region and “0” for an unserialized and unprotected
SecSi™ Sector region. See “SecSi™ Sector Flash Memory Region” for more information. For S29GLxxxNH.: XX18h/18h = Not
Factory Locked. XX98h/98h = Factory Locked. For S29GLxxxNL: XX08h/08h = Not Factory Locked. XX88h/88h = Factory
Locked.
11. Command is valid when device is ready to read array data or when device is in autoselect mode.
12. The system may read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the
Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
13. The Erase Resume/Program Resume command is valid only during the Erase Suspend/Program Suspend modes.
14. Issue this command sequence to return to READ mode after detecting device is in a Write-to-Buffer-Abort state. NOTE: the
full command sequence is required if resetting out of ABORT while using Unlock Bypass Mode.
15. S29GL512NH/L = 2223h/23h, 2201h/01h; S29GL256NH/L = 2222h/22h, 2201h/01h; S29GL128NH/L = 2221h/21h, 2201h/
01h.
16. The Exit command returns the device to reading the array.
17. Note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
18. For PWDx, only one portion of the password can be programmed per each “A0” command.
19. The All PPB Erase command embeds programming of all PPB bits before erasure.
20. All Lock Register bits are one-time programmable. Note that the program state = “0” and the erase state = “1”. Also note
that of both the Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the
same time or the Lock Register Bits Program operation will abort and return the device to read mode. Lock Register bits that
are reserved for future use will default to “1's”. The Lock Register is shipped out as “FFFF's” before Lock Register Bit program
execution.
21. If any of the Entry command was initiated, an Exit command must be issued to reset the device into read mode. Otherwise
the device will hang.
22. If ACC = VHH, sector protection will match when ACC = VIH
Protected State = “00h”, Unprotected State = “01h”.
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A d v a n c e I n f o r m a t i o n
Write Operation Status
The device provides several bits to determine the status of a program or erase
operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 14 and the following subsec-
tions describe the function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress.
The device also provides a hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is in progress or has been
completed.
Note that all Write Operation Status DQ bits are valid only after 4 µs delay.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Program or Erase algorithm is in progress or completed, or whether the device is
in Erase Suspend. Data# Polling is valid after the rising edge of the final WE#
pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must
provide an address within any of the sectors selected for erasure to read valid
status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7
may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is as-
serted low. That is, the device may change from providing status information to
valid data on DQ7. Depending on when the system samples the DQ7 output, it
may read the status or valid data. Even if the device has completed the program
or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may
be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.
Table 14 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data#
Polling algorithm. Figure 17 in the AC Characteristics section shows the Data#
Polling timing diagram.
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S29GLxxxN MirrorBitTM Flash Family
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A d v a n c e I n f o r m a t i o n
START
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1
Yes
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 5. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an
Embedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel with
a pull-up resistor to V
.
CC
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is in the read mode, the standby mode, or in the erase-suspend-read
mode. Table 14 shows the outputs for RY/BY#.
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
77
A d v a n c e I n f o r m a t i o n
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table 14 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit
algorithm. Figure 18 in the “AC Characteristics” section shows the toggle bit tim-
ing diagrams. Figure 19 shows the differences between DQ2 and DQ6 in graphical
form. See also the subsection on DQ2: Toggle Bit II.
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A d v a n c e I n f o r m a t i o n
START
Read DQ7–DQ0
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Program/Erase
Operation Complete
Complete, Write
Reset Command
Note:
The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling
as DQ5 changes to “1.” See the subsections on DQ6
and DQ2 for more information.
Figure 6. Toggle Bit Algorithm
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# to control the
September 29, 2004 27631A5
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A d v a n c e I n f o r m a t i o n
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 14 to compare outputs for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart form, and the section “DQ2:
Toggle Bit II” explains the algorithm. See also the RY/BY#: Ready/Busy# subsec-
tion. Figure 18 shows the toggle bit timing diagram. Figure 19 shows the
differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 and Figure 19 for the following discussion. Whenever the system
initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in
a row to determine whether a toggle bit is toggling. Typically, the system would
note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If
the toggle bit is not toggling, the device has completed the program or erase op-
eration. The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time has ex-
ceeded a specified internal pulse count limit. Under these conditions DQ5
produces a “1,” indicating that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a
location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the device halts the opera-
tion, and when the timing limit has been exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset command to return the device
to the reading the array (or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors are selected for erasure,
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27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
the entire time-out also applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase commands from the system can be as-
sumed to be less than 50 µs, the system need not monitor DQ3. See also the
Sector Erase Command Sequence section.
After the sector erase command is written, the system should read the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device will accept addi-
tional sector erase commands. To ensure the command has been accepted, the
system software should check the status of DQ3 prior to and following each sub-
sequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 14 shows the status of DQ3 relative to the other status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these
conditions DQ1 produces a “1”. The system must issue the Write-to-Buffer-Abort-
Reset command sequence to return the device to reading array data. See Write
Buffer section for more details.
Table 14. Write Operation Status
DQ7
(Note 2)
DQ5
(Note 1) DQ3
DQ2
(Note 2)
RY/
BY#
Status
DQ6
DQ1
0
Embedded Program Algorithm
Embedded Erase Algorithm
Program-Suspended
DQ7#
0
Toggle
Toggle
0
0
N/A
1
No toggle
Toggle
0
0
Standard
Mode
N/A
Invalid (not allowed)
1
1
1
1
0
Program
Suspend
Mode
Program-
Sector
Suspend
Non-Program
Read
Data
Suspended Sector
Erase-Suspended
1
No toggle
0
N/A
Toggle
N/A
Erase-
Sector
Suspend
Erase
Suspend
Mode
Non-Erase
Read
Data
Suspended Sector
Erase-Suspend-Program
(Embedded Program)
DQ7#
Toggle
0
N/A
N/A
N/A
Busy (Note 3)
Abort (Note 4)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Write-to-
Buffer
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for
further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
81
A d v a n c e I n f o r m a t i o n
ABSOLUTE MAXIMUM RATINGS
Storage Temperature, Plastic Packages. . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground:
V
V
(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
CC
IO
A9, OE#, and ACC (Note 2) . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1). . . . . . . . . . . . . . . . . . . . .–0.5 V to V + 0.5V
CC
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs
or I/Os may overshoot V to –2.0 V for periods of up to 20 ns. See Figure 7.
SS
Maximum DC voltage on input or I/Os is V + 0.5 V. During voltage transitions,
CC
input or I/O pins may overshoot to V + 2.0 V for periods up to 20 ns. See Figure
CC
8.
2. Minimum DC input voltage on pins A9, OE#, and ACC is –0.5 V. During voltage
transitions, A9, OE#, and ACC may overshoot V to –2.0 V for periods of up to
SS
20 ns. See Figure 7. Maximum DC input voltage on pin A9, OE#, and ACC is +12.5
V which may overshoot to +14.0V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods may affect device
reliability.
20 ns
20 ns
20 ns
V
CC
+0.8 V
+2.0 V
V
–0.5 V
–2.0 V
CC
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 7. Maximum Negative
Overshoot Waveform
Figure 8. Maximum Positive
Overshoot Waveform
Operating Ranges
Industrial (I) Devices
Ambient Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
A
Supply Voltages
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V or +3.0V to 3.6V
V
(Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.65V to 1.95V or VCC
IO
Notes:
1. Operating ranges define those limits between which the functionality of the device is guaranteed.
2. See “Product Selector Guide” .
82
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
DC Characteristics
CMOS Compatible-S29GL128N, S29GL256N, S29GL512N
Parameter
Symbol
Parameter Description
(Notes)
Test Conditions
Min
Typ
Max
Unit
WP/ACC: 2.0
Others: 1.0
35
VIN = VSS to VCC
VCC = VCC max
,
ILI
Input Load Current (1)
µA
ILIT
A9 Input Load Current
Output Leakage Current
VCC = VCC max; A9 = 12.5 V
µA
µA
VOUT = VSS to VCC
VCC = VCC max
,
ILO
1.0
20
50
90
10
CE# = VIL, OE# = VIH, VCC = VCCmax
,
,
6
30
60
1
f = 1 MHz, Byte Mode
CE# = VIL, OE# = VIH, VCC = VCCmax
ICC1
VCC Active Read Current (1)
mA
f = 5 MHz, Word Mode
CE# = VIL, OE# = VIH, VCC = VCCmax
f = 10 MHz
,
CE# = VIL, OE# = VIH, VCC = VCCmax
f = 10 MHz
ICC2
VCC Intra-Page Read Current (1)
mA
CE# = VIL, OE# = VIH, VCC = VCCmax
f=33 MHz
,
5
20
80
ICC3
VCC Active Erase/Program Current (2, 3) CE# = VIL, OE# = VIH, VCC = VCCmax
50
mA
mA
CE#, RESET# = VSS
0.3 V, OE# =
ICC4
VCC Standby Current
V
IH, VCC = VCCmax VIL = VSS + 0.3 V/-
1
5
0.1V
VCC = VCCmax
;
ICC5
VCC Reset Current
VIL = VSS + 0.3 V/-0.1V,
RESET# = VSS 0.3 V
1
5
µA
VCC = VCCmax
VIH = VCC 0.3 V,
ICC6
Automatic Sleep Mode (4)
1
5
µA
VIL = VSS + 0.3 V/-0.1V,
WP#/ACC = VIH
WP#/ACC
pin
10
50
20
CE# = VIL, OE# = VIH, VCC = VCCmax,
WP#/ACC = VIH
IACC
ACC Accelerated Program Current
mA
VCC pin
–0.1
80
VIL
Input Low Voltage (5)
Input High Voltage (5)
0.3 x VIO
VIO + 0.3
V
V
VIH
0.7 x VIO
Voltage for ACC Erase/Program
Acceleration
VHH
VCC = 2.7 –3.6 V
11.5
11.5
12.5
V
Voltage for Autoselect and Temporary
Sector Unprotect
VID
VCC = 2.7 –3.6 V
12.5
V
V
VOL
Output Low Voltage (5)
IOL = 100 µA
IOH = -100 µA
0.15 x VIO
VOH
Output High Voltage (5)
0.85 x VIO
2.3
V
V
VLKO
Low VCC Lock-Out Voltage (3)
2.5
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH
.
2. ICC active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.
3. Not 100% tested.
4. Automatic sleep mode enables the lower power mode when addresses remain stable tor tACC + 30 ns.
5. VIO = 1.65–1.95 V or 2.7–3.6 V
6. VCC = 3 V and VIO = 3V or 1.8V. When VIO is at 1.8V, I/O pins cannot operate at 3V.
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
83
A d v a n c e I n f o r m a t i o n
Test Conditions
Note: Diodes are IN3064 or equivalent
3.3 V
Table 15. Test Specifications
Test Condition
Output Load
All Speeds
1 TTL gate
Unit
2.7 k
Ω
Device
Under
Test
Output Load Capacitance, C
(including jig capacitance)
L
30
pF
C
L
6.2 k
Ω
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0.0–V
IO
Input timing measurement
reference levels (See Note)
0.5V
V
V
IO
Note: Diodes are IN3064 or equivalent.
Output timing measurement
reference levels
0.5 V
IO
Figure 9. Test Setup
Note: If VIO < VCC, the reference level is 0.5 VIO
.
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
VIO
0.5 VIO
0.5 VIO V
Input
Measurement Level
Output
0.0 V
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO
.
Figure 10. Input Waveforms and
Measurement Levels
84
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Read-Only Operations–S29GL128N, S29GL256N, S29GL512N
Parameter
Speed Options
JEDEC Std. Description
Test Setup
VIO = VCC = 3 V
90 100 110 110 Unit
90 100 110
tAVAV
tAVQV
tELQV
tRC Read Cycle Time
Min
Max
Max
ns
VIO = 1.8 V, VCC = 3 V
VIO = VCC = 3 V
VIO = 1.8 V, VCC = 3 V
VIO = VCC = 3 V
110
90 100 110
Address to Output Delay
tACC
ns
(Note 2)
110
90 100 110
Chip Enable to Output Delay
(Note 3)
tCE
ns
VIO = 1.8 V, VCC = 3 V
110
tPACC Page Access Time
Max 25
Max 25
Max
25
25
25
35
30
35
ns
ns
ns
tGLQV
tEHQZ
tOE Output Enable to Output Delay
tDF Chip Enable to Output High Z (Note 1)
20
20
Output Enable to Output High Z
tGHQZ
tDF
Max
ns
(Note 1)
Output Hold Time From Addresses, CE#
tAXQX
tOH
Min
Min
Min
Min
0
0
ns
ns
ns
ns
or OE#, Whichever Occurs First
Read
Output Enable Hold
tOEH
Time (Note 1)
Toggle and
10
35
Data# Polling
tCEH
Chip Enable Hold Time Read
Notes:
1. Not 100% tested.
2. CE#, OE# = VIL
3. OE# = VIL
4. See Figure 9 and Table 15 for test specifications.
5. Unless otherwise indicated, AC specifications for 90 ns, 100 ns, and 110 ns speed options are tested with VIO = VCC = 3 V.
AC specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V.
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
85
A d v a n c e I n f o r m a t i o n
AC Characteristics
tRC
Addresses Stable
tACC
Addresses
CE#
tCEH
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 11. Read Operation Timings
Same Page
Amax-A2
A2-A0*
Ad
Aa
Ab
Ac
tPACC
tPACC
tPACC
tACC
Data Bus
Qa
Qb
Qc
Qd
CE#
OE#
* Figure shows word mode. Addresses are A2–A-1 for byte mode.
Figure 12. Page Read Timings
86
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
Speed (Note 2)
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
Max
20
ns
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Notes:
1. Not 100% tested. If ramp rate is equal to or faster than 1V/100µs with a falling edge of the RESET# pin initiated, the
RESET# pin needs to be held low only for 100µs for power-up.
2. Next generation devices may have different reset speeds. To increase system design considerations, please refer to the
“Advance Information on S29GLxxxP AC Characteristics Hardware Reset (RESET#)” section for advance reset speeds on
S29GLxxxP devices.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
tRH
Figure 13. Reset Timings
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
87
A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase and Program Operations–S29GL128N, S29GL256N, S29GL512N
Parameter
JEDEC Std. Description
Speed Options
90
100
110
110
Unit
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
90
100
110
110
AVAV
WC
t
t
0
15
45
0
ns
AVWL
AS
Address Setup Time to OE# low during toggle
bit polling
t
Min
Min
Min
ns
ns
ns
ASO
t
t
Address Hold Time
WLAX
AH
Address Hold Time From CE# or OE# high
during toggle bit polling
t
AHT
t
t
t
Data Setup Time
Min
Min
Min
Min
45
0
ns
ns
DVWH
DS
t
Data Hold Time
WHDX
DH
t
t
CE# High during toggle bit polling
Output Enable High during toggle bit polling
20
20
CEPH
ns
ns
OEPH
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
Min
0
GHWL
GHWL
t
t
CE# Setup Time
Min
Min
Min
Min
Typ
0
0
ns
ns
ns
ns
µs
ELWL
CS
t
t
CE# Hold Time
WHEH
WLWH
CH
t
t
Write Pulse Width
35
30
240
WP
t
t
Write Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
WHDL
WPH
Effective Write Buffer Program
Per Word
Operation (Notes 2, 4)
Typ
15
µs
Accelerated Effective Write Buffer
Per Word
Program Operation (Notes 2, 4)
t t
WHWH1 WHWH1
Typ
Typ
Typ
13.5
60
µs
µs
µs
Program Operation (Note 2)
Word
Word
Accelerated Programming
Operation (Note 2)
54
t
t
WHWH2 WHWH2
Sector Erase Operation (Note 2)
Typ
Min
Min
Min
0.5
250
50
sec
ns
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
VHH
HH
CC
t
µs
ns
VCS
t
Erase/Program Valid to RY/BY# Delay
90
BUSY
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 90 ns, 100 ns, and 110 ns speed options are tested with V = V
IO
CC
= 3 V. AC specifications for 110 ns speed options are tested with V = 1.8 V and V = 3.0 V.
IO
CC
88
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode.
Figure 14. Program Operation Timings
VHH
VIL or VIH
VIL or VIH
ACC
tVHH
tVHH
Figure 15. Accelerated Program Timing Diagram
Notes:
1. Not 100% tested.
2. CE#, OE# = V
IL
3. OE# = V
IL
4. See Figure 9 and Table 15 for test specifications.
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
89
A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
tAS
SA
tWC
2AAh
VA
VA
Addresses
CE#
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.
Figure 16. Chip/Sector Erase Operation Timings
90
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
tRC
Addresses
VA
tACC
tCE
VA
VA
CE#
tCH
tOE
OE#
tOEH
WE#
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ6–DQ0
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note:
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read
cycle.
2. tOE for data polling is 45 ns when VIO = 1.65 to 2.7 V and is 35 ns when VIO = 2.7 to 3.6 V
Figure 17. Data# Polling Timings
(During Embedded Algorithms)
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
91
A d v a n c e I n f o r m a t i o n
AC Characteristics
tAHT
tAS
Addresses
tAHT
tASO
CE#
tOEH
WE#
tCEPH
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ2 and DQ6
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command
sequence, last status read cycle, and array data read cycle
Figure 18. Toggle Bit Timings (During Embedded Algorithms)
Enter
Erase
Suspend
Enter Erase
Suspend Program
Embedded
Erasing
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE#
or CE# to toggle DQ2 and DQ6.
Figure 19. DQ2 vs. DQ6
92
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Alternate CE# Controlled Erase and Program Operations-
S29GL128N, S29GL256N, S29GL512N
Parameter
Speed Options
JEDEC
Std. Description
90
100
110
110
Unit
ns
t
t
Write Cycle Time (Note 1)
Min
Min
90
100
110
110
AVAV
WC
t
t
Address Setup Time
0
15
45
0
ns
AVWL
AS
Address Setup Time to OE# low during
toggle bit polling
T
Min
Min
Min
ns
ns
ns
ASO
t
t
Address Hold Time
ELAX
AH
Address Hold Time From CE# or OE# high
during toggle bit polling
t
AHT
t
t
Data Setup Time
Min
Min
Min
Min
45
0
ns
ns
ns
ns
DVEH
DS
t
t
Data Hold Time
EHDX
DH
t
t
CE# High during toggle bit polling
OE# High during toggle bit polling
20
20
CEPH
OEPH
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
Min
0
ns
GHEL
GHEL
t
t
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
0
0
ns
ns
ns
ns
WLEL
WS
t
t
EHWH
WH
t
t
CE# Pulse Width
CE# Pulse Width High
35
30
ELEH
CP
t
t
CPH
EHEL
Write Buffer Program Operation (Notes 2,
3)
Typ
Typ
240
µs
µs
Effective Write Buffer
Program Operation (Notes
2, 4)
Per Word
15
t t
WHWH1 WHWH1
Effective Accelerated Write
Buffer Program Operation
(Notes 2, 4)
Per Word
Typ
13.5
µs
Program Operation (Note 2)
Word
Word
Typ
Typ
Typ
60
54
µs
µs
Accelerated Programming
Operation (Note 2)
t t
WHWH2 WHWH2
Sector Erase Operation (Note 2)
0.5
sec
Notes:
1. Not 100% tested.
2. See the “AC Characteristics” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 90 ns, 100ns, and 110 ns speed options are tested with V = V
IO
CC
= 3 V. AC specifications for 110 ns speed options are tested with V = 1.8 V and V = 3.0 V.
IO
CC
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
93
A d v a n c e I n f o r m a t i o n
AC Characteristics
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D
4. Waveforms are for the word mode.
is the data written to the device.
OUT
Figure 20. Alternate CE# Controlled Write (Erase/Program)
Operation Timings
94
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Erase And Programming Performance
Typ
Max
Parameter
(Note 1)
(Note 2)
Unit
Comments
Sector Erase Time
0.5
64
3.5
256
sec
Excludes 00h
programming prior to
erasure (Note 5)
S29GL128N
S29GL256N
S29GL512N
Chip Erase Time
128
256
512
sec
1024
Total Write Buffer
Programming Time
(Note 3)
240
µs
Total Accelerated Effective
Write Buffer Programming
Time (Note 3)
200
µs
Excludes system level
overhead (Note 6)
S29GL128N
S29GL256N
S29GL512N
123
246
492
Chip Program Time
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 10,000 cycles, checkerboard
CC
pattern.
2. Under worst case conditions of 90°C, V = 3.0 V, 100,000 cycles.
CC
3. Effective write buffer specification is based upon a 16-word write buffer operation.
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
words program faster than the maximum program times listed.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 12 and Table 13 for further information on command definitions.
TSOP Pin and BGA Package Capacitance
Parameter Symbol
Parameter Description
Test Setup
Typ
6
Max
7.5
5.0
12
Unit
pF
TSOP
BGA
C
Input Capacitance
V
= 0
IN
IN
4.2
8.5
5.4
7.5
3.9
pF
TSOP
BGA
pF
C
Output Capacitance
V
= 0
OUT
OUT
6.5
9
pF
TSOP
BGA
pF
C
Control Pin Capacitance
V
= 0
IN2
IN
4.7
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
95
A d v a n c e I n f o r m a t i o n
Physical Dimensions
TS056—56-Pin Standard Thin Small Outline Package (TSOP)
NOTES:
PACKAGE
TS 56
JEDEC
MO-142 (B) EC
1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)
SYMBOL
MIN.
---
NOM.
---
MAX.
1.20
0.15
1.05
0.23
0.27
0.16
0.21
2
3
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
A
A1
A2
b1
b
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.05
0.95
0.17
0.17
0.10
0.10
---
1.00
0.20
0.22
---
4
5
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTUSION IS 0.15 mm PER SIDE.
c1
c
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE
DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b
DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN
PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.
---
D
19.80
18.30
20.00
18.40
20.20
18.50
D1
6
7
8
THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10 mm AND 0.25 mm FROM THE LEAD TIP.
E
e
13.90
14.00
14.10
0.50 BASIC
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
L
0.50
0˚
0.60
-
0.70
8˚
O
R
N
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
---
56
0.20
3160\38.10A
96
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Physical Dimensions
LAA064—64-Ball Fortified Ball Grid Array (FBGA)
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
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A d v a n c e I n f o r m a t i o n
Advance Information on S29GLxxxP AC Characteristics
Hardware Reset (RESET#)
Parameter
JDEC
Std.
Description
Speed
Unit
RESET# Pin Low (During Embedded Algorithms) to Read Mode
(See Note 1)
t
t
Max
Max
1
ms
READY
RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode
(See Note)
1
ms
READY
t
RESET# Pulse Width
Min
Min
Min
Min
1
50
20
0
ms
ns
µs
ns
RP
t
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
RH
t
RPD
t
RB
Notes:
1. Not 100% tested. If ramp rate is equal to or faster than 1V/100µs with a falling edge of the RESET# pin initiated, the
RESET# pin needs to be held low only for 100µs for power-up.
2. Advance Information are forecasted and can change without notice.
98
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27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Revision Summary
Revision A (September 2, 2003)
Initial Release.
Revision A+1 (October 16, 2003)
Global
Added LAA064 package.
Distinctive Characteristics, Performance Characteristics
Clarified fifth bullet information.
Added RTSOP to Package Options.
Distinctive Characteristics, Software and Hardware Features
Clarified “Password Sector Protection” to “Advanced Sector Protection”
Connection Diagrams
Removed Note.
Ordering Information
Modified Package codes
Device Bus Operations, Table 1
Modified Table, removed Note.
Sector Address Tables
All address ranges doubled in all sector address tables.
Sector Protection
Lock Register: Corrected text to reflect 3 bits instead of 4.
Table 6, Lock Register: Corrected address range from DQ15-5 to DQ15-3; re-
moved DQ4 and DQ3; Corrected DQ15-3 Lock Register to Don’t Care.
Table 7, Sector Protection Schemes: Corrected Sector States.
Command Definitions
Table 12, Command Definitions, x16
Nonvolatile Sector Protection Command Set Entry Second Cycle Address cor-
rected from 55 to 2AA.
Legend: Clarified PWDx, DATA
Notes: Clarified Note 19.
Table 13, Command Definitions, x8
Password Read and Unlock Addresses and Data corrected.
Legend: Clarified PWDx, DATA
Notes: Clarified Note 19.
Test Conditions
Table 15, Test Specifications and Figure 10, Input Waveforms and Measurement
Levels: Corrected Input Pulse Levels to 0.0–VIO; corrected Input timing mea-
surement reference levels to 0.5V
.
IO
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A d v a n c e I n f o r m a t i o n
Revision A+2 (January 22, 2004)
Lock Register
Corrected and added new text for SecSi Sector Protection Bit, Persistent Protec-
tion Mode Lock Bit, and Password Protection Mode Lock Bit.
Persistent Sector Protection
Persistent Protection Bit (PPB): Added the second paragraph text about program-
ming the PPB bit.
Persistent Protection Bit Lock (PPB Lock Bit): Added the second paragraph text
about configuring the PPB Lock Bit, and fourth paragraph on Autoselect Sector
Protection Verification.
Added PPB Lock Bit requirement of 200ns access time.
Password Sector Protection
Corrected 1 µs (built-in delay for each password check) to 2 µs.
Lock Register Command Set Definitions
Added new information for this section.
Password Protection Command Set Definitions
Added new information for this section.
Non-Volatile Sector Protection Command Set Definitions
Added new information for this section.
Global Volatile Sector Protection Freeze Command Set
Added new information for this section.
Volatile Sector Protection Command Set
Added new information for this section.
SecSi Sector Entry Command
Added new information for this section.
SecSi Sector Exit Command
Added new information for this section.
Revision A+3 (March 2, 2004)
Connection Diagrams
Removed 56-pin reverse TSOP diagram.
Ordering Information
Updated the Standard Products for the S29GL512/256/128N devices and modi-
fied the valid combinations tables.
Word Program Command Sequence
Added new information to this section.
Lock Register Command Set Definitions
Added new information to this section.
Table 13
Updated this table.
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27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Revision A+4 (May 13, 2004)
Global
Removed references to RTSOP.
Distinctive Characteristics
Removed 16-word/32-byte page read buffer from Performance Characteristics.
Changed Low power consumption to 25 mA typical active read current and re-
moved 10 mA typical intrapage active read current.
Ordering Information
Changed formatting of pages.
Changed model numbers from 00,01,02,03 to 01, 02, V1, V2.
Table 1, “Device Bus Operations”
Combined WP# and ACC columns.
Table 8, “CFI Query Identification String”, Table 9, “System Interface
String”, Table 10, “Device Geometry Definition”, and Table 11, “Primary
Vendor-Specific Extended Query
Added Address (x8) column.
Word Program Command Sequence
Added text to fourth paragraph.
Figure 1, “Write Buffer Programming Operation,”
Added note references and removed DQ15 and DQ13.
Figure 3, “Program Suspend/Program Resume,”
Changed field to read XXXh/B0h and XXXh/30h.
Password Protection Command Set Definitions
Replaced all text.
Table 12, “S29GL512N, S29GL256N, S29GL128N Command Definitions,
x16”
Changed the first cycle address of CFI Query to 55.
Table 13, “S29GL512N, S29GL256N, S29GL128N Command Definitions,
x8”
Changed the third cycle data Device ID to 90.
Removed Unlock Bypass Reset.
Removed Note 12 and 13.
Figure 5, “Data# Polling Algorithm,”
Removed DQ15 and DQ13.
Absolute Maximum Ratings
Removed VCC from “All other pins” with respect to Ground.
CMOS Compatible
Changed the Max of I
to 70 mA
CC4
Added V to the Test conditions of I
IL
, I , and I
CC5 CC6 CC7
Change the Min of V to - 0.1 V.
IL
Updated note 5.
Read-Only Operations–S29GL128N Only
Added t parameter to table.
CEH
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A d v a n c e I n f o r m a t i o n
Figure 11, “Read Operation Timings,”
Added t to figure.
CEH
Figure 12, “Page Read Timings,”
Change A1-A0 to A2-A0.
Erase and Program Operations
Updated t
and t
with values.
WHWH2
WHWH1
Figure 16, “Chip/Sector Erase Operation Timings,”
Changed 5555h to 55h and 3030h to 30h.
Figure 17, “Data# Polling Timings (During Embedded Algorithms),”
Removed DQ15 and DQ14-DQ8
Added Note 2
Figure 18, “Toggle Bit Timings (During Embedded Algorithms),”
Changed DQ6 & DQ14/DQ2 & DQ10 to DQ2 and DQ6.
Alternate CE# Controlled Erase and Program Operations
Updated t
and t
with values.
WHWH2
WHWH1
Latchup Characteristics
Removed Table.
Erase and Programming Performance
Updated TBD with values.
Updated Note 1 and 2.
Physical Dimensions
Removed the reverse pinout information and note 3.
Revision A+5 (September 29, 2004)
Performance Characteristics
Removed 80 ns.
Product Selector Guide
Updated values in tables.
Ordering Information
Created a family table.
Operating Ranges
Updated VIO.
CMOS Characteristics
Created a family table.
Read-Only Operations
Created a family table.
Hardware Reset (RESET#)
Created a family table.
Figure 13, “Reset Timings,”
Added tRH to waveform.
Erase and Program Operations
Created a family table.
102
S29GLxxxN MirrorBitTM Flash Family
27631A5 September 29, 2004
A d v a n c e I n f o r m a t i o n
Alternate CE# Controlled Erase and Program Operations
Created a family table.
Erase and Programming Performance
Created a family table.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-
tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a SpansionTM product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright © 2004 Spansion LLC. All rights reserved.
SpansionTM, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion LLC. Other company and product names used
in this publication are for identification purposes only and may be trademarks of their respective companies.
September 29, 2004 27631A5
S29GLxxxN MirrorBitTM Flash Family
103
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