S29NS016J0LBJW002_技术文档

S29NS-J

128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit),

32 Megabit (2 M x 16-Bit), and 16 Megabit (1 M x 16 Bit),

110 nm CMOS 1.8-Volt only Simultaneous Read/Write,

Burst Mode Flash Memories

S29NS-J Cover Sheet

Data Sheet

Notice to Readers: This document states the current technical specifications regarding the Spansion

product(s) described herein. Each product described herein may be designated as Advance Information,

Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.

Publication Number S29NS-J_00

Revision A

Amendment 11

Issue Date February 7, 2007

D a t a S h e e t

Notice On Data Sheet Designations

Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of

product information or intended specifications throughout the product life cycle, including development,

qualification, initial production, and full production. In all cases, however, readers are encouraged to verify

that they have the latest information before finalizing their design. The following descriptions of Spansion data

sheet designations are presented here to highlight their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion Inc. is developing one or more specific

products, but has not committed any design to production. Information presented in a document with this

designation is likely to change, and in some cases, development on the product may discontinue. Spansion

Inc. therefore places the following conditions upon Advance Information content:

“This document contains information on one or more products under development at Spansion Inc.

The information is intended to help you evaluate this product. Do not design in this product without

contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed

product without notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a commitment

to production has taken place. This designation covers several aspects of the product life cycle, including

product qualification, initial production, and the subsequent phases in the manufacturing process that occur

before full production is achieved. Changes to the technical specifications presented in a Preliminary

document should be expected while keeping these aspects of production under consideration. Spansion

places the following conditions upon Preliminary content:

“This document states the current technical specifications regarding the Spansion product(s)

described herein. The Preliminary status of this document indicates that product qualification has been

completed, and that initial production has begun. Due to the phases of the manufacturing process that

require maintaining efficiency and quality, this document may be revised by subsequent versions or

modifications due to changes in technical specifications.”

Combination

Some data sheets contain a combination of products with different designations (Advance Information,

Preliminary, or Full Production). This type of document distinguishes these products and their designations

wherever necessary, typically on the first page, the ordering information page, and pages with the DC

Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first

page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal changes

are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include

those affecting the number of ordering part numbers available, such as the addition or deletion of a speed

option, temperature range, package type, or V_IOrange. Changes may also include those needed to clarify a

description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following

conditions to documents in this category:

“This document states the current technical specifications regarding the Spansion product(s)

described herein. Spansion Inc. deems the products to have been in sufficient production volume such

that subsequent versions of this document are not expected to change. However, typographical or

specification corrections, or modifications to the valid combinations offered may occur.”

Questions regarding these document designations may be directed to your local sales office.

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S29NS-J

S29NS-J_00_A11 February 7, 2007

S29NS-J

128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit),

32 Megabit (2 M x 16-Bit), and 16 Megabit (1 M x 16 Bit),

110 nm CMOS 1.8-Volt only Simultaneous Read/Write,

Burst Mode Flash Memories

Data Sheet

Features

Single 1.8 volt read, program and erase (1.7 to 1.95 V)

Sector Protection

– Software command sector locking

– WP# protects the two highest sectors

– All sectors locked when A = V

Multiplexed Data and Address for reduced

I/O count

– A15–A0 multiplexed as DQ15–DQ0

– Addresses are latched by AVD# control input when CE# low

cc

IL

Handshaking feature

– Provides host system with minimum possible latency by monitoring

RDY

Simultaneous Read/Write operation

– Data can be continuously read from one bank while executing

erase/program functions in other bank

Supports Common Flash Memory Interface (CFI)

– Zero latency between read and write operations

Software command set compatible with JEDEC 42.4

standards

Read access times at 54 MHz (C_L=30 pF)

– Burst access times of 11/13.5 ns

at industrial temperature range

– Asynchronous random access times

of 65/70 ns

– Synchronous random access times

of 71/87.5 ns

– Backwards compatible with Am29F and Am29LV families

Manufactured on 110 nm process technology

Embedded Algorithms

– Embedded Erase algorithm automatically preprograms and erases

the entire chip or any combination of designated sectors

– Embedded Program algorithm automatically writes and verifies data

at specified addresses

Burst Modes

– Continuous linear burst

– 8/16/32 word linear burst with wrap around

– 8/16/32 word linear burst without wrap around

Data# Polling

– Provides a software method of detecting program and erase

operation completion

Power dissipation (typical values, 8 bits switching, C_L= 30

Erase Suspend/Resume

pF)

– Suspends an erase operation to read data from, or program data to,

a sector that is not being erased, then resumes the erase operation

– Burst Mode Read: 25 mA

– Simultaneous Operation: 40 mA

– Program/Erase: 15 mA

– Standby mode: 9 µA

Hardware reset input (RESET#)

– Hardware method to reset the device for reading array data

CMOS compatible inputs and outputs

Sector Architecture

Package

– Four 8 Kword sectors

– 48-ball Very Thin FBGA (S29NS128J)

– 44-ball Very Thin FBGA (S29NS064J, S29NS032J, S29NS016J)

– Two hundred fifty-five (S29NS128J), one hundred twenty-seven

(S29NS064J),sixty-three (S29NS032J), or thirty-one (S29NS016J)

32 Kword sectors

Cycling Endurance: 1 million cycles per sector typical

Data Retention: 20 years typical

– Four banks (see next page for sector count and size)

General Description

The S29NS128J, S29NS064J, S29NS032J and S29NS016J are 128 Mbit, 64 Mbit, 32 Mbit and 16 Mbit 1.8 Volt-only,

Simultaneous Read/Write, Burst Mode Flash memory devices, organized as 8,388,608, 4,194,304, 2,097,152 and 1,048,576.

words of 16 bits each. These devices use a single V_CCof 1.7 to 1.95 V to read, program, and erase the memory array. A 12.0-

volt A_ccmay be used for faster program performance if desired. These devices can also be programmed in standard

EPROM programmers.

The devices are offered at the following speeds:

Clock Speed

Burst Access (ns)

Synch. Initial Access (ns)

Asynchronous Initial Access (ns)

Output Loading

54 MHz

13.5

87.5

70

30 pF

Publication Number S29NS-J_00

Revision A

Amendment 11

Issue Date February 7, 2007

D a t a S h e e t

The devices operate within the temperature range of –25 °C to +85 °C, and are offered Very Thin FBGA

packages.

Simultaneous Read/Write Operations with Zero Latency

The Simultaneous Read/Write architecture divides the memory space into four banks. The device allows a

host system to program or erase in one bank, then immediately and simultaneously read from another bank,

with zero latency. This releases the system from waiting for the completion of program or erase operations.

The devices are structured as shown in the following tables:

S29NS128J

Bank A Sectors

Bank B, C & D Sectors

Quantity

Size

Quantity

Size

4

8 Kwords

32 Kwords

64

32 Kwords

63

32 Mbits total

96 Mbits total

S29NS064J

S29NS032J

S29NS016J

Bank A Sectors

Bank B, C & D Sectors

Quantity

Size

Quantity

Size

4

8 Kwords

32 Kwords

32

32 Kwords

31

16 Mbits total

48 Mbits total

Bank A Sectors

Bank B, C & D Sectors

Quantity

Size

Quantity

Size

4

8 Kwords

32 Kwords

16

32 Kwords

15

8 Mbits total

24 Mbits total

Bank A Sectors

Bank B, C & D Sectors

Quantity

Size

Quantity

Size

4

7

8 Kwords

32 Kwords

8

32 Kwords

4 Mbits total

12 Mbits total

The devices use Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to

control asynchronous read and write operations. For burst operations, the devices additionally require Ready

(RDY) and Clock (CLK). This implementation allows easy interface with minimal glue logic to

microprocessors/microcontrollers for high performance read operations.

The devices offer complete compatibility with the JEDEC 42.4 single-power-supply Flash command set

standard. Commands are written to the command register using standard microprocessor write timings.

Reading data out of the device are similar to reading from other Flash or EPROM devices.

The host system can detect whether a program or erase operation is complete by using the device status bit

DQ7 (Data# Polling). After a program or erase cycle has been completed, the device automatically returns to

reading array data.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the

data contents of other sectors. The devices are fully erased when shipped from the factory.

Hardware data protection measures include a low V_CCdetector that automatically inhibits write operations

during power transitions. The devices also offer three types of data protection at the sector level. The sector

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S29NS-J_00_A11 February 7, 2007

D a t a S h e e t

lock/unlock command sequence disables or re-enables both program and erase operations in any sector.

When at V_IL, WP# locks the highest two sectors. Finally, when A_ccis at V_IL, all sectors are locked.

The devices offer two power-saving features. When addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode. The system can also place the device into the standby

mode. Power consumption is greatly reduced in both modes.

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D a t a S h e e t

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.

2.

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

Block Diagram of Simultaneous Operation Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.

4.

5.

6.

7.

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

Requirements for Asynchronous Read Operation (Non-Burst) . . . . . . . . . . . . . . . . . . . . . . . 19

Requirements for Synchronous (Burst) Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Programmable Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Simultaneous Read/Write Operations with Zero Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

RESET#: Hardware Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.10 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.11 WP# Boot Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.

Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Set Configuration Register Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Sector Lock/Unlock Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.10 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.

Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.1

9.2

9.3

9.4

9.5

9.6

9.7

DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

RDY: Ready. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

DQ3: Sector Erase Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.1 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11.1 CMOS Compatible. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

13. Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

13.1 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

14. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

14.1

V_CCPower-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

14.2 CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

14.3 Synchronous/Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6

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D a t a S h e e t

14.4 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

14.5 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

14.6 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

15. Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

16. BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

17. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

17.1 S29NS128J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

17.2 S29NS064J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

17.3 S29NS032J and S29NS016J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

18. Appendix A: Daisy Chain Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

19. Appendix B: Daisy Chain Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

20. Appendix C: Daisy Chain Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

21. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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Figures

Figure 3.1

Figure 3.2

Figure 3.3

Figure 3.4

Figure 8.1

Figure 8.2

Figure 9.1

Figure 9.2

S29NS128J—48-Ball Very Thin FBGA (VDC048). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

S29NS064J—44-Ball Very Thin FBGA (VDD044). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

S29NS032J—44-Ball Very Thin FBGA (VDE044). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

S29NS016J—44-Ball Very Thin FBGA (VDE044). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Toggle Bit Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 10.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 10.2 Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 12.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 13.1 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 14.1

V_CCPower-up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 14.2 CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 14.3 Burst Mode Read (54 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 14.4 Burst Mode Read (40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 14.5 Asynchronous Mode Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 14.6 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 14.7 Program Operation Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 14.8 Chip/Sector Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 14.9 Accelerated Unlock Bypass Programming Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 14.10 Data# Polling Timings (During Embedded Algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 14.11 Toggle Bit Timings (During Embedded Algorithm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 14.12 8-, 16-, and 32-Word Linear Burst Address Wrap Around. . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 14.13 Latency with Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 14.14 Initial Access at 3Eh with Address Boundary Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 14.15 Example of Extended Valid Address Reducing Wait State Usage . . . . . . . . . . . . . . . . . . . . 61

Figure 14.16 Back-to-Back Read/Write Cycle Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 18.1 VDC048 Daisy Chain Layout (Top View, Balls Facing Down). . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 19.1 VDD044 Daisy Chain Layout (Top View, Balls Facing Down). . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 20.1 VDE044 Daisy Chain Layout(Top View, Balls Facing Down) . . . . . . . . . . . . . . . . . . . . . . . . 69

8

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Tables

Table 7.1

Table 7.2

Table 8.1

Table 8.2

Table 8.3

Table 8.4

Table 8.5

Table 8.6

Table 8.7

Table 8.8

Table 8.9

Table 8.10

Table 8.11

Table 8.12

Table 8.13

Table 8.14

Table 8.15

Table 8.16

Table 9.1

Table 9.2

Table 12.1

Table 18.1

Table 18.2

Table 18.3

Table 19.1

Table 19.2

Table 19.3

Table 20.1

Table 20.2

Table 20.3

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Sector Address Table, S29NS128J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Sector Address Table, S29NS064J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Sector Address Table, S29NS032J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Sector Address Table, S29NS016J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Burst Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Wait States for Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Autoselect Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Accelerated Sector Erase Groups, S29NS128J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Accelerated Sector Erase Groups, S29NS064J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Accelerated Sector Erase Groups, S29NS032J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Accelerated Sector Erase Groups, S29NS016J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Daisy Chain Part for 128Mbit 110 nm Flash Products (VDC048, 10 x 11 mm) . . . . . . . . . . .67

VDC048 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

VDC048 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Daisy Chain Part for 64Mbit 110 nm Flash Products (VDD044, 9.2 x 8 mm) . . . . . . . . . . . . .68

VDD044 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

VDD044 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Daisy Chain Part for 32 and 16 Mbit 110 nm Flash Products (VDE044, 7.7 x 6.2 mm) . . . . .69

VDE044 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

VDE044 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

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1. Product Selector Guide

Part Number

S29NS128J, S29NS064J, S29N032J, 29NS016J

Burst Frequency

54 MHz

0L

Speed Option

Max Initial Synchronous Access Time, ns (t

)

87.5

13.5

IACC

Max Burst Access Time, ns (t

)

BACC

Max Asynchronous Access Time, ns (t

)

ACC

70

Max CE# Access Time, ns (t

)

CE

Max OE# Access Time, ns (t

)

13.5

OE

2. Block Diagram

V_CC

V_SS

A/DQ15–A/DQ0

RDY

Buffer

RDY

Erase Voltage

Generator

Input/Output

Buffers

State

WE#

RESET#

A_cc

Control

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

CE#

OE#

Y-Decoder

Y-Gating

V_CC

Detector

Timer

Cell Matrix

X-Decoder

Burst

State

Control

Burst

Address

Counter

AVD#

CLK

A_max–A0

A/DQ15–A/DQ0

A_max–A16

Note:

1.

A

indicates the highest order address bit.

max

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2.1

Block Diagram of Simultaneous Operation Circuit

V

CC

V

SS

Acc

Bank A Address

DQ15–DQ0

Bank A

A

–A0

max

X-Decoder

OE#

Bank B Address

DQ15–DQ0

Bank B

X-Decoder

A

–A0

max

RESET#

WE#

OE#

STATE

CONTROL

&

COMMAND

REGISTER

DQ15–

DQ0

CE#

Status

AVD#

CLK

RDY

Control

DQ15–DQ0

A

–A0

max

X-Decoder

Bank C

DQ15–DQ0

Bank C Address

A

–A0

max

A

–A0

OE#

max

X-Decoder

Bank D

Bank D Address

DQ15–DQ0

Notes:

1. A15–A0 are multiplexed with DQ15–DQ0.

2. Amax indicates the highest order address bit.

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3. Connection Diagrams

Figure 3.1 S29NS128J—48-Ball Very Thin FBGA (VDC048)

Top View, Balls Facing Down

NC

A1

RDY A21 GND CLK V_CCWE# V_PPA19 A17 A22

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10

V_CCA16 A20 AVD# NC RESET# WP# A18 CE# GND

C1 C2 C3 C4 C5 C6? C7 C8 C9 C10

GND A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE#

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

A/DQ15 A/DQ14 GND A/DQ5 A/DQ4 A/DQ11A/DQ10 V_CCA/DQ1 A/DQ0

A2

A3

A4

A5

A6

A7

A8

A9

A10

NC

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D a t a S h e e t

Figure 3.2 S29NS064J—44-Ball Very Thin FBGA (VDD044)

Top View, Balls Facing Down

NC

A1

RDY A21 GND CLK V_CCWE# V_PPA19 A17

B1 B2 B3 B4 B5 B6 B7 B8 B9

A2

A3

A4

A5

A6

A7

A8

A9

A10

NC

B10

V_CCA16 A20 AVD# NC RESET# WP# A18 CE# GND

C1 C2 C3 C4 C5 C6? C7 C8 C9 C10

GND A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE#

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

A/DQ15 A/DQ14 GND A/DQ5 A/DQ4 A/DQ11A/DQ10 V_CCA/DQ1 A/DQ0

NC

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Figure 3.3 S29NS032J—44-Ball Very Thin FBGA (VDE044)

Top View, Balls Facing Down

NC

A1

RDY NC GND CLK V_CCWE# V_PPA19 A17

B1 B2 B3 B4 B5 B6 B7 B8 B9

A2

A3

A4

A5

A6

A7

A8

A9

A10

NC

B10

V_CCA16 A20 AVD# NC RESET# WP# A18 CE# GND

C1 C2 C3 C4 C5 C6? C7 C8 C9 C10

GND A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE#

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

A/DQ15 A/DQ14 GND A/DQ5 A/DQ4 A/DQ11A/DQ10 V_CCA/DQ1 A/DQ0

NC

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Figure 3.4 S29NS016J—44-Ball Very Thin FBGA (VDE044)

Top View, Balls Facing Down

NC

A1

RDY NC GND CLK V_CCWE# V_PPA19 A17

B1 B2 B3 B4 B5 B6 B7 B8 B9

V_CCA16

C1 C2

GND A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE#

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

A2

A3

A4

A5

A6

A7

A8

A9

A10

NC

B10

NC AVD# NC RESET# WP# A18 CE# GND

C3 C4 C5 C6? C7 C8 C9 C10

A/DQ15 A/DQ14 GND A/DQ5 A/DQ4 A/DQ11A/DQ10 V_CCA/DQ1 A/DQ0

NC

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4. Input/Output Descriptions

Signal

Description

A22–A16

A21–A16

A20–A16

A19–A16

A/DQ15–A/DQ0

CE#

Address Inputs, S29NS128J

Address Inputs, S29NS064J

Address Inputs, S29NS032J

Address Inputs, S29NS016J

Multiplexed Address/Data input/output

Chip Enable Input. Asynchronous relative to CLK for the Burst mode.

Output Enable Input. Asynchronous relative to CLK for the Burst mode.

Write Enable Input.

OE#

WE#

V

Device Power Supply (1.7 V–1.95 V).

Ground

CC

GND

NC

No Connect; not connected internally

RDY

Ready output; indicates the status of the Burst read. V = data invalid. V = data valid.

OL OH

The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst mode operation.

After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should

remain low during asynchronous access.

CLK

Address Valid input. Indicates to device that the valid address is present on the address inputs (address bits A15–

A0 are multiplexed, address bits A22–A16 are address only).

AVD#

V = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on

IL

rising edge of CLK.

= device ignores address inputs

V

IH

RESET#

WP#

Hardware reset input. V = device resets and returns to reading array data

IL

Hardware write protect input. V = disables writes to SA257–258 (S29NS128J), SA129–130 (S29NS064J), SA65–

IL

66 (S29NS032J), or SA33-34 (S29NS016J). Should be at V for all other conditions.

IH

At 12 V, accelerates programming; automatically places device in unlock bypass mode. At V , disables program

IL

A

cc

and erase functions. Should be at V for all other conditions.

IH

16

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5. Logic Symbol

A

–A16

max

16

A/DQ15–

A/DQ0

CLK

CE#

OE#

W’E#

RESET#

AVD#

WP#

RDY

A

cc

A

indicates the highest order address bit.

max

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6. Ordering Information

The ordering part number is formed by a valid combination of the following:

S29NS

128

J

0L

BA

W

00

3

Packing Type

0

2

3

= Tray

= 7-inch Tape and Reel

= 13-inch Tape and Reel

Additional Ordering Options)

00 = Standard Configuration

Temperature Range

W = Wireless (–25°C to +85°C)

Package Type & Material Set

BA = Very Thin Fine-Pitch BGA Lead (Pb)-Free Compliant Package

BF = Very Thin Fine-Pitch BGA Lead (Pb)-Free Package

BJ = Very Thin Fine-Pitch BGA Lead (Pb)-Free LF35 Package

Speed Option

0L = 54 MHz

Process Technology

J

= 110 nm Floating Gate Technology

Flash Density

128 = 128 Megabit (8 M x 16-Bit)

064 = 64 Megabit (4 M x 16-Bit)

032 = 32 Megabit (2 M x 16-Bit)

016 = 16 Megabit (1 M x 16-Bit)

Product Family

S29NS = Simultaneous Read/Write, Burst Mode Flash Memory with

Multiplexed I/O 1.8-Volt Operation

Valid Combinations

The following configurations are planned to be supported for this device. Contact your local Spansion sales

office to confirm availability of specific valid combinations and to check on newly released combinations.

Valid Combinations BGA Package

Order Number

Packing Type

0, 2 or 3

Package Marking

NS128J0LBAW00

NS128J0LBJW00

NS128J0LBFW00

NS064J0LBAW00

NS064J0LBJW00

NS064J0LBFW00

NS032J0LBJW00

NS032J0LBFW00

NS016J0LBJW00

NS016J0LBFW00

Package

Pb-Free Compliant

Pb-free, LF35

Pb-free

Density

Speed

S29NS128J0LBAW00

S29NS128J0LBJW00

S29NS128J0LBFW00

S29NS064J0LBAW00

S29NS064J0LBJW00

S29NS064J0LBFW00

S29NS032J0LBJW00

S29NS032J0LBFW00

S29NS016J0LBJW00

S29NS016J0LBFW00

128

Pb-Free Compliant

Pb-free, LF35

Pb-free

64

54 MHz

Pb-free, LF35

Pb-free

32

16

Pb-free, LF35

Pb-free

Note

For industrial temperature range, contact your local sales office.

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7. Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the

internal command register. The command register itself does not occupy any addressable memory location.

The register is composed of latches that store the commands, along with the address and data information

needed to execute the command. The contents of the register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the device. Table 7.1 lists the device bus operations, the

inputs and control levels they require, and the resulting output. The following subsections describe each of

these operations in further detail.

Table 7.1 Device Bus Operations

Operation

CE#

L

OE#

L

WE#

H

A

–16

A/DQ15–0

I/O

RESET#

CLK

L

AVD#

max

Asynchronous Read

Write

Addr In

H

L

H

L

Addr In

I/O

H/L

X

Standby (CE#)

Hardware Reset

H

X

HIGH Z

X

Burst Read Operations

Load Starting Burst Address

L

H

L

H

Addr In

X

Addr In

H

Advance Burst to next address with appropriate

Data presented on the Data Bus

Burst

Data Out

H

Terminate current Burst read cycle

H

X

H

X

HIGH Z

H

L

X

Terminate current Burst read cycle via RESET#

X

Terminate current Burst read cycle and start new

Burst read cycle

L

H

X

I/O

H

Legend

L = Logic 0, H = Logic 1, X = Don’t Care.

7.1

Requirements for Asynchronous Read Operation (Non-Burst)

To read data from the memory array, the system must assert a valid address on A/DQ15–A/DQ0 and A_max

A16, while AVD# and CE# are at V_IL. WE# should remain at V_IH. Note that CLK must remain at V_ILduring

asynchronous read operations. The rising edge of AVD# latches the address, after which the system can

drive OE# to V_IL. The data will appear on A/DQ15–A/DQ0. (See Figure 14.5.) Since the memory array is

–

divided into four banks, each bank remains enabled for read access until the command register contents are

altered.

Address access time (t_ACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (t_CE) is the delay from the stable addresses and stable CE# to valid data at the outputs. The

output enable access time (t_OE) is the delay from the falling edge of OE# to valid data at the output.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory content occurs during the power transition.

7.2

Requirements for Synchronous (Burst) Read Operation

The device is capable of seven different burst read modes (see Table 8.9): continuous burst read; 8-, 16-, and

32-word linear burst reads with wrap around; and 8-, 16-, and 32-word linear burst reads without wrap

around.

7.2.1

Continuous Burst

When the device first powers up, it is enabled for asynchronous read operation. The device will automatically

be enabled for burst mode and addresses will be latched on the first rising edge on the CLK input, while

AVD# is held low for one clock cycle. Prior to activating the clock signal, the system should determine how

many wait states are desired for the initial word (t_IACC) of each burst session. The system would then write the

Set Configuration Register command sequence.

The initial word is output t_IACCafter the rising edge of the first CLK cycle. Subsequent words are output t_BACC

after the rising edge of each successive clock cycle, which automatically increments the internal address

counter. Note that the device has a fixed internal address boundary that occurs every 64 words,

starting at address 00003Fh. The transition from the highest address to 000000h is also a boundary

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crossing. During a boundary crossing, there is a two-cycle latency between the valid read at address

00003Eh and the valid read at address 00003Fh (or between addresses offset from these values by the same

multiple of 64 words). RDY is deasserted during the two-cycle latency, and it is reasserted in the third cycle to

indicate that the data at address 00003Fh (or offset from 3Fh by a multiple of 64 words) is ready. See

Figure 14.13.

The device will continue to output continuous, sequential burst data, wrapping around to address 000000h

after it reaches the highest addressable memory location, until the system asserts CE# high, RESET# low, or

AVD# low in conjunction with a new address. See Table 7.1. The reset command does not terminate the

burst read operation.

If the host system crosses the bank boundary while reading in burst mode, and the device is not programming

or erasing, a two-cycle latency will occur as described above. If the host system crosses the bank boundary

while the device is programming or erasing, the device will provide asynchronous read status information.

The clock will be ignored. After the host has completed status reads, or the device has completed the

program or erase operation, the host can restart a burst operation using a new address and AVD# pulse.

If the clock frequency is less than 6 MHz during a burst mode operation, additional latencies will occur. RDY

indicates the length of the latency by pulsing low.

7.2.2

8-, 16-, and 32-Word Linear Burst with Wrap Around

These three modes are of the linear wrap around design, in which a fixed number of words are read from

consecutive addresses. In each of these modes, the burst addresses read are determined by the group within

which the starting address falls. The groups are sized according to the number of words read in a single burst

sequence for a given mode (see Table 7.2.)

Table 7.2 Burst Address Groups

Mode

8-word

16-word

32-word

Group Size

8 words

Group Address Ranges

0-7h, 8-Fh, 10-17h, 18-1Fh...

16 words

32 words

0-Fh, 10-1Fh, 20-2Fh, 30-3Fh...

00-1Fh, 20-3Fh, 40-5Fh, 60-7Fh...

As an example: if the starting address in the 8-word mode is 39h, the address range to be read would be 38-

3Fh, and the burst sequence would be 39-3A-3B-3C-3D-3E-3F-38h. The burst sequence begins with the

starting address written to the device, but wraps back to the first address in the selected group. In a similar

fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address

written to the device, and then wrap back to the first address in the selected address group. Note that in

these three burst read modes the address pointer does not cross the boundary that occurs every 64

words; thus, no wait states are inserted (except during the initial access).

7.2.3

8-, 16-, and 32-Word Linear Burst without Wrap Around

In these modes, a fixed number of words (predefined as 8,16,or 32 words) are read from consecutive

addresses starting with the initial word, which is written to the device. When the number of words has been

read completely, the burst read operation stops and the RDY output goes low. There is no group limitation

and is different from the Linear Burst with Wrap Around.

See Table 8.9 and Table 8.16 for the command of setting the 8-, 16-, and 32- Word Burst without Wrap

Around.

As an example, for 8-word length Burst Read, if the starting address written to the device is 39h, the burst

sequence would be 39-3A-3B-3C-3D-3E-3F-40h, and the read operation will be terminated at 40h. In a

similar fashion, the 16-word and 32-word modes begin their burst sequence on the starting address written to

the device, and Continuously Read to the predefined word length, 16 or 32 words.

The operation is similar to the Continuous Burst, but will stop the operation at fixed word length. It is possible

the device crosses the fixed internal address boundary that occurs every 64 words during burst read; a

latency occurs before data appears for the next address and RDY is pulsing low. If the host system crosses

the bank boundary, the device will react in the same manner as in the Continuous Burst.

If the clock frequency is less than 6 MHz during a burst mode operation, additional latencies will occur. RDY

indicates the length of the latency by pulsing low.

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7.3

Programmable Wait State

The programmable wait state feature indicates to the device the number of additional clock cycles that must

elapse after AVD# is driven active before data will be available. Upon power up, the device defaults to the

maximum of seven total cycles. The total number of wait states is programmable from two to seven cycles.

The wait state command sequence requires three cycles; after the two unlock cycles, the third cycle address

should be written according to the desired wait state as shown in Table 8.9. Address bits A11-A0 should be

set to 555h, while addresses bits A17-A12 set the wait state. For further details, see Section 8.3, Set

Configuration Register Command Sequence on page 36.

7.3.1

Handshaking Feature

The handshaking feature allows the host system to simply monitor the RDY signal from the device to

determine when the initial word of burst data is ready to be read. The host system should use the wait state

command sequence to set the number of wait states for optimal burst mode operation (03h for 54 MHz clock).

The initial word of burst data is indicated by the rising edge of RDY after OE# goes low.

7.4

7.5

Simultaneous Read/Write Operations with Zero Latency

This device is capable of reading data from one bank of memory while programming or erasing in one of the

other three banks of memory. An erase operation may also be suspended to read from or program to another

location within the same bank (except the sector being erased). Figure 14.16 shows how read and write

cycles may be initiated for simultaneous operation with zero latency. Refer to the Section 11., DC

Characteristics on page 51 table for read-while-program and read-while-erase current specifications.

Writing Commands/Command Sequences

The device has inputs/outputs that accept both address and data information. To write a command or

command sequence (which includes programming data to the device and erasing sectors of memory), the

system must drive AVD# and CE# to V_IL, and OE# to V_IHwhen providing an address to the device, and drive

WE# and CE# to V_IL, and OE# to V_IH. when writing commands or data.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are required to program a word, instead of four.

An erase operation can erase one sector, multiple sectors, or the entire device. Table 7 indicates the address

space that each sector occupies. The device address space is divided into four banks: Bank A contains both

8 Kword boot sectors in addition to 32 Kword sectors, while Banks B, C, and D contain only 32 Kword sectors.

A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the

address bits required to uniquely select a sector.

Refer to the DC Characteristics table for write mode current specifications. The AC Characteristics section

contains timing specification tables and timing diagrams for write operations.

7.5.1

Accelerated Program Operation

The device offers accelerated program operations through the A_ccinput. This function is primarily intended to

allow faster manufacturing throughput at the factory. If the system asserts V_IDon this input, the device

automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to

reduce the time required for program operations. The system would use a two-cycle program command

sequence as required by the Unlock Bypass mode. Removing V_IDfrom the A_ccinput returns the device to

normal operation.

7.5.2

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system

can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–

DQ0. Standard read cycle timings apply in this mode. See Section 7.5.2, Autoselect Functions on page 21

and Section 8.6, Autoselect Command Sequence on page 38 for more information.

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7.6

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,

independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at V_CC0.2 V.

The device requires standard access time (t_CE) for read access when the device is in either of these standby

modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation

is completed.

I

_CC3in DC Characteristics represents the standby current specification.

7.7

7.8

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enters this

mode when addresses remain stable for t_ACC+ 60 ns. The automatic sleep mode is independent of the CE#,

WE#, and OE# control signals. Standard address access timings provide new data when addresses are

changed. While in sleep mode, output data is latched and always available to the system. I_CC4in DC

Characteristics represents the automatic sleep mode current specification.

RESET#: Hardware Reset Input

The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#

is driven low for at least a period of t_RP, the device immediately terminates any operation in progress, tristates

all outputs, and ignores all read/write commands for the duration of the RESET# pulse. The device also

resets the internal state machine to reading array data. The operation that was interrupted should be

reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V_SS0.2 V, the device

draws CMOS standby current (I_CC4). If RESET# is held at V_ILbut not within V_SS0.2 V, the standby current

will be greater.

RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the device requires a time of t_READYW(during

Embedded Algorithms) before the device is ready to read data again. If RESET# is asserted when a program

or erase operation is not executing, the reset operation is completed within a time of t_READY(not during

Embedded Algorithms). The system can read data t_RHafter RESET# returns to V_IH.

Refer to the AC Characteristics tables for RESET# parameters and to Figure 14.6 for the timing diagram.

7.8.1

V

Power-up and Power-down Sequencing

CC

The device imposes no restrictions on V_CCpower-up or power-down sequencing. Asserting RESET# to V_ILis

required during the entire V_CCpower sequence until the respective supplies reach their operating voltages.

Once V_CCattains its operating voltage, de-assertion of RESET# to V_IHis permitted.

7.9

Output Disable Mode

When the OE# input is at V_IH, output from the device is disabled. The outputs are placed in the high

impedance state.

7.10 Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection

against inadvertent writes (refer to Table 8.16 for command definitions).

The device offers three types of data protection at the sector level:

The sector lock/unlock command sequence disables or re-enables both program and erase operations in

any sector.

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When WP# is at V_IL,

– SA257 and SA258 are locked (S29NS128J)

– SA129 and SA130 are locked (S29NS064J)

– SA65 and SA66 are locked (S29NS032J)

– SA33 and SA34 are locked (S29NS016J)

When A_ccis at V_IL, all sectors are locked.

7.11 WP# Boot Sector Protection

The WP# signal will be latched at a specific time in the embedded program or erase sequence. To prevent a

write to the top two sectors, WP# must be asserted (WP#=V_IL) on the last write cycle of the embedded

sequence (i.e., 4th write cycle in embedded program, 6th write cycle in embedded erase).

If using the Unlock Bypass feature: on the 2nd program cycle, after the Unlock Bypass command is written,

the WP# signal must be asserted on the 2nd cycle.

If selecting multiple sectors for erasure: The WP# protection status is latched only on the 6th write cycle of the

embedded sector erase command sequence when the first sector is selected. If additional sectors are

selected for erasure, they are subject to the WP# status that was latched on the 6th write cycle of the

command sequence.

The following hardware data protection measures prevent accidental erasure or programming, which might

otherwise be caused by spurious system level signals during V_CCpower-up and power-down transitions, or

from system noise.

7.11.1

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not accept any write cycles. This protects data during V_CC

power-up and power-down. The command register and all internal program/erase circuits are disabled, and

the device resets to reading array data. Subsequent writes are ignored until V_CCis greater than V_LKO. The

system must provide the proper signals to the control inputs to prevent unintentional writes when V_CCis

greater than V_LKO

.

7.11.2

7.11.3

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a logical one.

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D a t a S h e e t

8. Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software interrogation

handshake, which allows specific vendor-specified software algorithms to be used for entire families of

devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address

55h any time the device is ready to read array data. The system can read CFI information at the addresses

given in Tables 8.1–8.4. To terminate reading CFI data, the system must write the reset command.

The system can also write the CFI query command when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 8.1–8.4. The

system must write the reset command to return the device to the autoselect mode.

For further information, please refer to the CFI Specification and CFI Publication 100, available through the

World Wide Web at http://www.amd.com/flash/cfi. Alternatively, Contact your local Spansion sales office for

copies of these documents.

Table 8.1 CFI Query Identification String

Data

Addresses

Description

S29NS128J S29NS064J S29NS032J S29NS016J

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

17h

18h

0000h

19h

1Ah

0000h

Address for Alternate OEM

Extended Table (00h = none exists)

Table 8.2 System Interface String

Data

S29NS032J

Addresses

Description

S29NS128J S29NS064J

S29NS016J

V

Min. (write/erase)

CC

1Bh

1Ch

1Dh

0017h

0019h

0000h

D7–D4: volt, D3–D0: 100 millivolt

V

Max. (write/erase)

CC

D7–D4: volt, D3–D0: 100 millivolt

A

Min. voltage (00h = no A pin present)

cc

Refer to 4Dh

A

Max. voltage (00h = no A pin present)

cc

1Eh

1Fh

20h

21h

22h

0000h

0003h

0000h

0009h

0000h

Refer to 4Eh

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs

(00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms

(00h = not supported)

23h

24h

25h

0005h

0000h

0004h

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical

(00h = not supported)

26h

0000h

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Table 8.3 Device Geometry Definition

Data

S29NS064J S29NS032J S29NS016J

Addresses

Description

S29NS128J

27h

0018h

0017h

0016h

0015h

Device Size = 2^Nbyte

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication

100)

2Ah

2Bh

0000h

Max. number of bytes in multi-byte write = 2^N

(00h = not supported)

2Ch

0002h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

00FEh

0000h

0001h

007Eh

0000h

0001h

003Eh

0000h

0001h

001Eh

0000h

0001h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

0003h

0000h

0040h

0000h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

0000h

39h

3Ah

3Bh

3Ch

0000h

Table 8.4 Primary Vendor-Specific Extended Query (Sheet 1 of 2)

Data

Addresses

Description

S29NS128J S29NS064J S29NS032J S29NS016J

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

0000h

Silicon Revision Number (Bits 7-2)

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

0002h

0001h

0000h

0005h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

05 = 29BDS/N128 mode

Simultaneous Operation

Number of Sectors in all banks except boot bank

00C0h

0060h

0030h

0018h

Burst Mode Type

00 = Not Supported, 01 = Supported

0001h

0000h

00B5h

00C5h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

4Fh

0003h

0001h = Top/Middle Boot Device,

0002h = Bottom Boot Device, 03h = Top Boot Device

50h

57h

0000h

0004h

Program Suspend. 00h = not supported

Bank Organization: X = Number of banks

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D a t a S h e e t

Table 8.4 Primary Vendor-Specific Extended Query (Sheet 2 of 2)

Data

Addresses

Description

S29NS128J S29NS064J S29NS032J S29NS016J

58h

59h

5Ah

5Bh

0040h

0043h

0020h

0023h

0010h

0013h

0008h

Bank D Region Information. X = Number of sectors in bank

Bank C Region Information. X = Number of sectors in bank

Bank B Region Information. X = Number of sectors in bank

Bank A Region Information. X = Number of sectors in bank

Process Technology. 00h = 230 nm, 01h = 170 nm, 02h = 130

nm/110 nm

5Ch

0002h

Table 8.5 Sector Address Table, S29NS128J (Sheet 1 of 4)

Sector

Sector Size

32 Kwords

Address Range

000000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

Sector

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

Sector Size

32 Kwords

Address Range

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

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Table 8.5 Sector Address Table, S29NS128J (Sheet 2 of 4)

Sector

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

Sector Size

32 Kwords

Address Range

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

Sector

SA96

Sector Size

32 Kwords

Address Range

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3FFFFFh

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

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Table 8.5 Sector Address Table, S29NS128J (Sheet 3 of 4)

Sector

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

SA142

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

SA159

Sector Size

32 Kwords

Address Range

400000h–407FFFh

408000h–40FFFFh

410000h–417FFFh

418000h–41FFFFh

420000h–427FFFh

428000h–42FFFFh

420000h–427FFFh

438000h–43FFFFh

430000h–437FFFh

448000h–44FFFFh

450000h–457FFFh

458000h–45FFFFh

460000h–467FFFh

468000h–46FFFFh

470000h–477FFFh

478000h–47FFFFh

480000h–487FFFh

488000h–48FFFFh

490000h–497FFFh

498000h–49FFFFh

4A0000h–4A7FFFh

4A8000h–4AFFFFh

4B0000h–4B7FFFh

4B8000h–4BFFFFh

4C0000h–4C7FFFh

4C8000h–4CFFFFh

4D0000h–4D7FFFh

4D8000h–4DFFFFh

4E0000h–4E7FFFh

4E8000h–4EFFFFh

4F0000h–4F7FFFh

4F8000h–4FFFFFh

Sector

SA160

SA161

SA162

SA163

SA164

SA165

SA166

SA167

SA168

SA169

SA170

SA171

SA172

SA173

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

SA185

SA186

SA187

SA188

SA189

SA190

SA191

Sector Size

32 Kwords

Address Range

500000h–507FFFh

508000h–50FFFFh

510000h–517FFFh

518000h–51FFFFh

520000h–527FFFh

528000h–52FFFFh

530000h–537FFFh

538000h–53FFFFh

540000h–547FFFh

548000h–54FFFFh

550000h–557FFFh

558000h–55FFFFh

560000h–567FFFh

568000h–56FFFFh

570000h–577FFFh

578000h–57FFFFh

580000h–587FFFh

588000h–58FFFFh

590000h–597FFFh

598000h–59FFFFh

5A0000h–5A7FFFh

5A8000h–5AFFFFh

5B0000h–5B7FFFh

5B8000h–5BFFFFh

5C0000h–5C7FFFh

5C8000h–5CFFFFh

5D0000h–5D7FFFh

5D8000h–5DFFFFh

5E0000h–5E7FFFh

5E8000h–5EFFFFh

5F0000h–5F7FFFh

5F8000h–5FFFFFh

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Table 8.5 Sector Address Table, S29NS128J (Sheet 4 of 4)

Sector

SA192

SA193

SA194

SA195

SA196

SA197

SA198

SA199

SA200

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

Sector Size

32 Kwords

Address Range

600000h–607FFFh

608000h–60FFFFh

610000h–617FFFh

618000h–61FFFFh

620000h–627FFFh

628000h–62FFFFh

630000h–637FFFh

638000h–63FFFFh

640000h–647FFFh

648000h–64FFFFh

650000h–657FFFh

658000h–65FFFFh

660000h–667FFFh

668000h–66FFFFh

670000h–677FFFh

678000h–67FFFFh

680000h–687FFFh

688000h–68FFFFh

690000h–697FFFh

698000h–69FFFFh

6A0000h–6A7FFFh

6A8000h–6AFFFFh

6B0000h–6B7FFFh

6B8000h–6BFFFFh

6C0000h–6C7FFFh

6C8000h–6CFFFFh

6D0000h–6D7FFFh

6D8000h–6DFFFFh

6E0000h–6E7FFFh

6E8000h–6EFFFFh

6F0000h–6F7FFFh

6F8000h–6FFFFFh

Sector

SA224

SA225

SA226

SA227

SA228

SA229

SA230

SA231

SA232

SA233

SA234

SA235

SA236

SA237

SA238

SA239

SA240

SA241

SA242

SA243

SA244

SA245

SA246

SA247

SA248

SA249

SA250

SA251

SA252

SA253

SA254

SA255

SA256

SA257

SA258

Sector Size

32 Kwords

8 Kwords

Address Range

700000h–707FFFh

708000h–70FFFFh

710000h–717FFFh

718000h–71FFFFh

720000h–727FFFh

728000h–72FFFFh

730000h–737FFFh

738000h–73FFFFh

740000h–747FFFh

748000h–74FFFFh

750000h–757FFFh

758000h–75FFFFh

760000h–767FFFh

768000h–76FFFFh

770000h–777FFFh

778000h–77FFFFh

780000h–787FFFh

788000h–78FFFFh

790000h–797FFFh

798000h–79FFFFh

7A0000h–7A7FFFh

7A8000h–7AFFFFh

7B0000h–7B7FFFh

7B8000h–7BFFFFh

7C0000h–7C7FFFh

7C8000h–7CFFFFh

7D0000h–7D7FFFh

7D8000h–7DFFFFh

7E0000h–7E7FFFh

7E8000h–7EFFFFh

7F0000h–7F7FFFh

7F8000h–7F9FFFh

7FA000h–7FBFFFh

7FC000h–7FDFFFh

7FE000h–7FFFFFh

8 Kwords

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Table 8.6 Sector Address Table, S29NS064J (Sheet 1 of 4)

Sector

Sector Size

32 Kwords

Address Range

000000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

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Table 8.6 Sector Address Table, S29NS064J (Sheet 2 of 4)

Sector

Sector Size

32 Kwords

Address Range

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

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Table 8.6 Sector Address Table, S29NS064J (Sheet 3 of 4)

Sector

Sector Size

32 Kwords

Address Range

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

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Table 8.6 Sector Address Table, S29NS064J (Sheet 4 of 4)

Sector

Sector Size

32 Kwords

8 Kwords

Address Range

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3F9FFFh

3FA000h–3FBFFFh

3FC000h–3FDFFFh

3FE000h–3FFFFFh

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

8 Kwords

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Table 8.7 Sector Address Table, S29NS032J (Sheet 1 of 2)

Sector

Sector Size

32 Kwords

Address Range

000000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

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Table 8.7 Sector Address Table, S29NS032J (Sheet 2 of 2)

Sector

Sector Size

32 Kwords

8 Kwords

Address Range

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1F9FFFh

1FA000h–1FBFFFh

1FC000h–1FDFFFh

1FE000h–1FFFFFh

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

8 Kwords

Table 8.8 Sector Address Table, S29NS016J (Sheet 1 of 2)

Sector

SA0

Sector Size

32 Kwords

Address Range

000000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

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Table 8.8 Sector Address Table, S29NS016J (Sheet 2 of 2)

Sector

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

Sector Size

32 Kwords

8 Kwords

Address Range

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0F9FFFh

0FA000h–0FBFFFh

0FC000h–0FDFFFh

0FE000h–0FFFFFh

8 Kwords

8.1

8.2

Command Definitions

Writing specific address and data commands or sequences into the command register initiates device

operations. Table 8.16 defines the valid register command sequences. Writing incorrect address and data

values or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the rising edge of AVD#. All data is latched on the rising edge of WE#. Refer to

the AC Characteristics section for timing diagrams.

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to

retrieve data in asynchronous mode. Each bank is ready to read array data after completing an Embedded

Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-

read mode, after which the system can read data from any non-erase-suspended sector. After completing a

programming operation in the Erase Suspend mode, the system may once again read array data with the

same exception. See the Erase Suspend/Erase Resume Commands section for more information.

The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next

section, Reset Command, for more information.

See also Requirements for Asynchronous Read Operation (Non-Burst) and Requirements for Synchronous

(Burst) Read Operation in the Device Bus Operations section for more information. The Asynchronous Read

and Synchronous/Burst Read tables provide the read parameters, and Figures 14.3 and 14.5 show the

timings.

8.3

Set Configuration Register Command Sequence

The configuration register command sequence instructs the device to set a particular number of clock cycles

for the initial access in burst mode. The number of wait states that should be programmed into the device is

directly related to the clock frequency. The first two cycles of the command sequence are for unlock

purposes. On the third cycle, the system should write C0h to the address associated with the intended wait

state setting (see Table 8.9). Address bits A17–A12 determine the setting. Note that addresses A_max–A18

are shown as “0” but are actually don’t care.

Table 8.9 Burst Modes (Sheet 1 of 2)

Third Cycle Addresses for Wait States

Burst

Mode

Wait States

0

1

2

3

4

5

Clock Cycles

2

3

4

5

6

7

Continuous

00555h

08555h

01555h

09555h

02555h

0A555h

03555h

0B555h

04555h

0C555h

05555h

0D555h

8-word Linear (wrap around)

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Table 8.9 Burst Modes (Sheet 2 of 2)

Third Cycle Addresses for Wait States

Burst

Mode

Wait States

0

1

2

3

4

5

Clock Cycles

2

3

4

5

6

7

16-word Linear (wrap around)

32-word Linear (wrap around)

8-word Linear (no wrap around)

16-word Linear (no wrap around)

32-word Linear (no wrap around)

10555h

18555h

28555h

30555h

38555h

11555h

19555h

29555h

31555h

39555h

12555h

1A555h

2A555h

32555h

3A555h

13555h

1B555h

2B555h

33555h

3B555h

14555h

1C555h

2C555h

34555h

3C555h

15555h

1D555h

2D555h

35555h

3D555h

Note:

1. The burst mode is set in the third cycle of the Set Wait State command sequence.

Upon power up, the device defaults to the maximum seven cycle wait state setting. It is recommended that

the wait state command sequence be written, even if the default wait state value is desired, to ensure the

device is set as expected. A hardware reset will set the wait state to the default setting.

8.3.1

Handshaking Feature

The host system should set address bits A17–A12 to “000011” for a clock frequency of 54 MHz, assuming

continuous burst is desired in both cases, for optimal burst operation.

Table 8.10 describes the typical number of clock cycles (wait states) for various conditions.

Table 8.10 Wait States for Handshaking

Typical No. of Clock Cycles after AVD# Low

Conditions at Address

40 MHz

54 MHz

Initial address is even

4

5

6

7

5

6

7

8

Initial address is odd

Initial address is even, and is at boundary crossing (1)

Initial address is odd, and is at boundary crossing*

Note:

1. In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries when wrap around is enabled (at

address 3Fh, and at addresses offset from 3Fh by multiples of 64).

The autoselect function allows the host system to determine whether the flash device is enabled for

handshaking. See the Autoselect Command Sequence section for more information.

8.4

Sector Lock/Unlock Command Sequence

The sector lock/unlock command sequence allows the system to determine which sectors are protected from

accidental writes. When the device is first powered up, all sectors are locked. To unlock a sector, the system

must write the sector lock/unlock command sequence. Two cycles are first written: addresses are don’t care

and data is 60h. During the third cycle, the sector address (SLA) and unlock command (60h) is written, while

specifying with address A6 whether that sector should be locked (A6 = V_IL) or unlocked (A6 = V_IH). After the

third cycle, the system can continue to lock or unlock additional cycles, or exit the sequence by writing F0h

(reset command).

Note that the last two outermost boot sectors can be locked by taking the WP# signal to V_IL. Also, if A_ccis at

V_ILall sectors are locked; if the A_ccinput is at V_ID, all sectors are unlocked.

8.5

Reset Command

Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t

cares for this command.

The reset command may be written between the sequence cycles in an erase command sequence before

erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins,

however, the device ignores reset commands until the operation is complete.

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The reset command may be written between the sequence cycles in a program command sequence before

programming begins. This resets the bank to which the system was writing to the read mode. If the program

command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command

returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores

reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank

entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank

to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the

read mode (or erase-suspend-read mode if that bank was in Erase Suspend).

8.6

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and device codes,

and determine whether or not a sector is protected. Table 8.16 shows the address and data requirements.

The autoselect command sequence may be written to an address within a bank that is either in the read or

erase-suspend-read mode. The autoselect command may not be written while the device is actively

programming or erasing in the other bank.

The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect

mode. The system may read at any address within the same bank any number of times without initiating

another autoselect command sequence. The following table describes the address requirements for the

various autoselect functions, and the resulting data. BA represents the bank address, and SA represent the

sector address. The device ID is read in three cycles.

Table 8.11 Autoselect Device ID

Read Data

Description

Address

S29NS128J

S29NS064J

S29NS032J

S29NS016J

Manufacturer ID

Device ID, Word 1

Device ID, Word 2

Device ID, Word 3

(BA) + 00h

(BA) + 01h

(BA) + 0Eh

(BA) + 0Fh

0001h

007Eh

0016h

0000h

277Eh

2702h

2700h

2A7Eh

2A24h

2A00h

297Eh

2915h

2900h

0001h (locked),

0000h (unlocked)

Sector Block Lock/Unlock

Revision ID

(SA) + 02h

(BA) + 03h

TBD, Based on Nokia spec

The system must write the reset command to return to the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

8.7

Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two

unlock write cycles, followed by the program set-up command. The program address and data are written

next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further

controls or timings. The device automatically provides internally generated program pulses and verifies the

programmed cell margin. Table 8.16 shows the address and data requirements for the program command

sequence.

When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses

are no longer latched. The system can determine the status of the program operation by monitoring DQ7.

Refer to the Write Operation Status section for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program operation. The program command sequence should be

reinitiated once that bank has returned to the read mode, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from

“0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 status bit to

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indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only

erase operations can convert a “0” to a “1.”

Note: By default, upon every power up, the sectors will automatically be locked.

Therefore, everytime after power-up, users need to write unlock command to unlock the sectors before giving

program/erase command.

8.7.1

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program to a bank faster than using the standard program

command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles.

This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the

unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to

program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h;

the second cycle contains the program address and data. Additional data is programmed in the same

manner. This mode dispenses with the initial two unlock cycles required in the standard program command

sequence, resulting in faster total programming time. Table 8.16 shows the requirements for the unlock

bypass command sequences.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are

valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command

sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only

contain the data 00h. The bank then returns to the read mode.

The device offers accelerated program operations through the A_ccinput. When the system asserts A_ccon this

input, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle

Unlock Bypass program command sequence. The device uses the higher voltage on the A_ccinput to

accelerate the operation.

Figure 8.1 illustrates the algorithm for the program operation. Refer to the Erase/Program Operations table in

the AC Characteristics section for parameters, and Figure 14.7 for timing diagrams.

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Figure 8.1 Program Operation

START

Write Unlock Cycles:

Address XXX, Data 60

Address SLA, Data 60

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note

1. See Table 8.16 for program command sequence.

8.8

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical erase. The system is not required to provide any

controls or timings during these operations. Table 8.16 shows the address and data requirements for the chip

erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no

longer latched. The system can determine the status of the erase operation by using DQ7. Refer to the Write

Operation Status section for information on these status bits.

Any commands written during the chip erase operation are ignored. However, note that a hardware reset

immediately terminates the erase operation. If that occurs, the chip erase command sequence should be

reinitiated once that bank has returned to reading array data, to ensure data integrity.

Figure 8.2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in

the AC Characteristics section for parameters, and Figure 14.8 section for timing diagrams.

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8.9

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed

by the address of the sector to be erased, and the sector erase command. Table 8.16 shows the address and

data requirements for the sector erase command sequence.

The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm

automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase.

The system is not required to provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of no less than t_SEA(sector erase accept)

occurs. During the time-out period, additional sector addresses and sector erase commands may be written.

Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one

sector to all sectors. The time between these additional cycles must be less than t_SEA, otherwise erasure may

begin. Any sector erase address and command following the exceeded time-out may or may not be accepted.

It is recommended that processor interrupts be disabled during this time to ensure all commands are

accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command

other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read

mode. The system must rewrite the command sequence and any additional addresses and commands.

The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data

from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7in the

erasing bank. Refer to the Write Operation Status section for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands

are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs,

the sector erase command sequence should be reinitiated once that bank has returned to reading array data,

to ensure data integrity.

Figure 8.2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in

the AC Characteristics section for parameters, and Figure 14.8 section for timing diagrams.

8.9.1

Accelerated Sector Group Erase

Under certain conditions, the device can erase sectors in parallel. This method of erasing sectors is faster

than the standard sector erase command sequence. Table 8.12 lists the sector erase groups.

The accelerated sector group erase function must not be used more than 100 times per sector. In

addition, accelerated sector group erase should be performed at room temperature (30 +/- 10°C).

Table 8.12 Accelerated Sector Erase Groups, S29NS128J

SA0–SA7

SA8–SA15

SA128–SA135

SA136–SA143

SA144–SA151

SA152–SA159

SA160–SA167

SA168–SA175

SA176–SA183

SA184–SA191

SA192–SA199

SA200–SA207

SA208–SA215

SA216–SA223

SA224–SA231

SA232–SA239

SA240–SA247

SA248–SA254

SA16–SA23

SA24–SA31

SA32–SA39

SA40–SA47

SA48–SA55

SA56–SA63

SA64–SA71

SA72–SA79

SA80–SA87

SA88–SA95

SA96–SA103

SA104–SA111

SA112–SA119

SA120–SA127

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Table 8.13 Accelerated Sector Erase Groups, S29NS064J

SA0–SA7

SA8–SA15

SA16–SA23

SA24–SA31

SA32–SA39

SA40–SA47

SA48–SA55

SA56–SA63

SA64–SA71

SA72–SA79

SA80–SA87

SA88–SA95

SA96–SA103

SA104–SA111

SA112–SA119

SA120–SA126

Table 8.14 Accelerated Sector Erase Groups, S29NS032J

SA0–SA3

SA4–SA7

SA16-SA19

SA20-SA23

SA24-SA27

SA28-SA31

SA32-SA35

SA36-SA39

SA40-SA43

SA44-SA47

SA48-SA51

SA52-SA55

SA56–SA59

SA60–SA62

SA8–SA11

SA12-SA15

Table 8.15 Accelerated Sector Erase Groups, S29NS016J

SA0–SA1

SA2–SA3

SA4–SA5

SA6–SA7

SA8-SA9

SA10-SA11

SA12-SA13

SA14-SA15

SA16-SA17

SA18-SA19

SA20-SA21

SA24-SA25

SA26-SA27

SA28-SA29

SA30

Use the following procedure to perform accelerated sector group erase:

1. Unlock all sectors in a sector group to be erased using the sector lock/unlock command sequence.

All sectors that remain locked will not be erased.

2. Apply 12 V to the A_ccinput. This voltage must be applied at least 1 µs before executing Step 3.

3. Write 80h to any address within a sector group to be erased.

4. Write 10h to any address within a sector group to be erased.

5. Monitor status bits DQ2/DQ6 or DQ7 to determine when erasure is complete, just as in the

standard erase operation. See Write Operation Status for further details.

6. Lower A_ccfrom 12 V to V_CC

.

7. Relock sectors as required.

8.10 Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read

data from, program data to, any sector not selected for erasure. The system may also lock or unlock any

sector while the erase operation is suspended. The system must not write the sector lock/unlock

command to sectors selected for erasure. The bank address is required when writing this command. This

command is valid only during the sector erase operation, including the minimum t_SEAtime-out period during

the sector erase command sequence. The Erase Suspend command is ignored if written during the chip

erase operation or Embedded Program algorithm.

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When the Erase Suspend command is written during the sector erase operation, the device requires t_ESL

(erase suspend latency) to suspend the erase operation. However, when the Erase Suspend command is

written during the sector erase time-out, the device immediately terminates the time-out period and suspends

the erase operation.

After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system

can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all

sectors selected for erasure.) The system may also lock or unlock any sector while in the erase-suspend-read

mode. Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0.

The system can use DQ7 to determine if a sector is actively erasing or is erase-suspended. Refer to the Write

Operation Status section for information on these status bits.

After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode.

The system can determine the status of the program operation using DQ7 , just as in the standard program

operation. Refer to the Write Operation Status section for more information.

In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the

Autoselect Functions and Autoselect Command Sequence sections for details.

To resume the sector erase operation, the system must write the Erase Resume command. The bank

address of the erase-suspended bank is required when writing this command. Further writes of the Resume

command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

Figure 8.2 Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes

1. See Table 8.16 for erase command sequence.

2. See the section on DQ3 for information on the sector erase timer.

Table 8.16 Command Definitions

Bus Cycles (Notes 1–6)

Command Sequence

(Notes)

First

Second

Third

Addr

Fourth

Addr

Fifth

Addr

Sixth

Addr Data Addr Data

Data

Addr

Data

Asynchronous Read (7)

Reset (8)

1

RA

RD

F0

XXX

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Table 8.16 Command Definitions

Bus Cycles (Notes 1–6)

Fourth

Addr

Command Sequence

(Notes)

First

Second

Third

Addr

Fifth

Addr

Sixth

Addr Data Addr Data

Data

90

Data

0001

(10)

(13)

(14)

Data

Addr

Data

Manufacturer ID

Device ID

4

6

4

3

2

555

XXX

AA

A0

2AA

PA

55

PD

(BA)555

(SA)555

(BA)555

555

(BA)X00

(BA)X01

(SA)X02

(BA)X03

90

(BA)X0E

(11)

(BA) X0F

(12)

Sector Lock Verify (13)

Revision ID (14)

Mode Entry

90

20

Program (15)

Reset (16)

2

BA

90

XXX

00

Program

4

6

1

3

1

555

BA

AA

B0

30

2AA

55

555

A0

80

PA

PD

AA

Chip Erase

555

2AA

55

555

SA

10

30

Sector Erase

Erase Suspend (17)

Erase Resume (18)

Sector Lock/Unlock

Set Config. Register (19)

CFI Query (20)

BA

XXX

555

55

60

XXX

2AA

60

55

SLA

60

AA

98

(CR)555

C0

Legend

7. No unlock or command cycles required when bank is reading array data.

X = Don’t care

8. The Reset command is required to return to reading array data (or to the

erase-suspend-read mode if previously in Erase Suspend) when a bank is

in the autoselect mode, or if DQ5 goes high (while the bank is providing

status information).

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

9. The fourth cycle of the autoselect command sequence is a read cycle. Th

system must read device IDs across the 4th, 5th, and 6th cycles, The

system must provide the bank address. See the Autoselect Command

Sequence section for more information.

PA = Address of the memory location to be programmed. Addresses latch on

the falling edge of the WE# or CE# pulse, whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of

WE# or CE# pulse, whichever happens first.

10.For S29NS128J, the data is 007Eh. For S29NS064J, the data is 277Eh. Fo

S29NS032J, the data is 2A7Eh. For S29NS016J, the data is 297Eh.

11.For S29NS128J, the data is 0016h. For S29NS064J, the data is 2702h, fo

S29NS032J, the data is 2A24h, for S29NS016J, the data is 2915h.

SA = Address of the sector to be verified (in autoselect mode) or erased.

Address bits A

–A13 uniquely select any sector.

max

12.For S29NS128J, the data is 0000h, for S29NS064J, the data is 2700h, for

S29NS032J, the data is 2A00h for S29NS016J, the data is 2900h.

BA = Address of the bank (A22–A21 for S29NS128J, A21–A20 for S29NS064J,

A20–A19 for S29NS032J, A19–A18 for S29NS016J) that is being switched to

autoselect mode, is in bypass mode, or is being erased.

13.The data is 0000h for an unlocked sector and 0001h for a locked sector.

14.The data is TBD, based on Nokia spec.

15.The Unlock Bypass command sequence is required prior to this command

sequence.

SLA = Address of the sector to be locked. Set sector address (SA) and either

A6 = 1 for unlocked or A6 = 0 for locked.

16.The Unlock Bypass Reset command is required to return to reading array

data when the bank is in the unlock bypass mode.

CR = Configuration Register set by address bits A17–A12.

17.The system may read and program in non-erasing sectors, or enter the

autoselect mode, when in the Erase Suspend mode. The Erase Suspend

command is valid only during a sector erase operation, and requires the

bank address.

Notes

1. See Table 7.1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect command

sequence, all bus cycles are write cycles.

18.The Erase Resume command is valid only during the Erase Suspend

mode, and requires the bank address.

4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD

and PD.

19.The addresses in the third cycle must contain, on A17–A12, the additiona

wait counts to be set. See Set Configuration Register Command Sequenc

5. Unless otherwise noted, address bits A

–A12 are don’t cares.

20.Command is valid when device is ready to read array data or when device

in autoselect mode.

max

6. Writing incorrect address and data values or writing them in the improper

sequence may place the device in an unknown state. The system must

write the reset command to return the device to reading array data.

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9. Write Operation Status

The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5

and DQ7. Table 9.2 and the following subsections describe the function of these bits. DQ7 a method for

determining whether a program or erase operation is complete or in progress.

9.1

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm

is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising

edge of the final WE# pulse in the command sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum

programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the

Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system

must provide the program address to read valid status information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for approximately t_PSP, then that bank returns to the read

mode.

During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the sectors selected for erasure to read valid status

information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately t_ASP(all sectors protected toggle time), then the bank returns to the read

mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address

within a protected sector, the status may not be valid.

Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously

with DQ6–DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing

status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid

data, the data outputs on DQ6–DQ0 may be still invalid. Valid data on DQ7–DQ0 will appear on successive

read cycles.

Table 9.2 shows the outputs for Data# Polling on DQ7. Figure 9.1 shows the Data# Polling algorithm.

Figure 14.10 in the AC Characteristics section shows the Data# Polling timing diagram.

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D a t a S h e e t

Figure 9.1 Data# Polling Algorithm

START

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

PASS

FAIL

Notes

1. VA = Valid Address for programming. During a sector erase operation, a valid address is any sector address within the sector being

erased. During chip erase, a valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

9.2

RDY: Ready

The RDY pin is a dedicated status output that indicates valid output data on A/DQ15–A/DQ0 during burst

(synchronous) reads. When RDY is asserted (RDY = V_OH), the output data is valid and can be read. When

RDY is de-asserted (RDY = V_OL), the system should wait until RDY is re-asserted before expecting the next

word of data.

In synchronous (burst) mode with CE# = OE# = V_IL, RDY is de-asserted under the following conditions:

during the initial access; after crossing the internal boundary between addresses 3Eh and 3Fh (and

addresses offset from these by a multiple of 64); and when the clock frequency is less than 6 MHz (in which

case RDY is de-asserted every third clock cycle). The RDY pin will also switch during status reads when a

clock signal drives the CLK input. In addition, RDY = V_OHwhen CE# = V_ILand OE# = V_IH, and RDY is Hi-Z

when CE# = V_IH.

In asynchronous (non-burst) mode, the RDY pin does not indicate valid or invalid output data. Instead, RDY =

V_OHwhen CE# = V_IL, and RDY is Hi-Z when CE# = V_IH.

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9.3

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the

same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause

DQ6 to toggle. Note that OE# must be low during toggle bit status reads. When the operation is complete,

DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for

approximately t_ASP, then returns to reading array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are

protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approximately after t_PSPthe program

command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program

algorithm is complete.

See the following for additional information: (toggle bit flowchart), DQ6: Toggle Bit I (description),

Figure 14.11 (toggle bit timing diagram), and Table 9.1 (compares DQ2 and DQ6).

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Figure 9.2 Toggle Bit Algorithm

START

Read Byte

(DQ0-DQ7)

Address = VA

Read Byte

(DQ0-DQ7)

Address = VA

No

DQ6 = Toggle?

Yes

No

DQ5 = 1?

Yes

Read Byte Twice

(DQ?0-DQ7)

Adrdess = VA

No

DQ6 = Toggle?

Yes

FAIL

PASS

Note

1. The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the

subsections on DQ6 and DQ2 for more information.

9.4

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that

is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is

valid after the rising edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure.

Note that OE# must be low during toggle bit status reads. But DQ2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing,

or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits

are required for sector and mode information. Refer to Table 9.2 to compare outputs for DQ2 and DQ6.

See the following for additional information: (toggle bit flowchart), DQ6: Toggle Bit I (description),

Figure 14.11 (toggle bit timing diagram), and Table 9.1 (compares DQ2 and DQ6).

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Table 9.1 DQ6 and DQ2 Indications

If device is

and the system reads

then DQ6

and DQ2

programming,

at any address,

toggles,

does not toggle.

at an address within a sector selected

for erasure,

toggles,

also toggles.

does not toggle.

toggles.

actively erasing,

at an address within sectors not

selected for erasure,

at an address within a sector selected

for erasure,

does not toggle,

returns array data,

toggles,

erase suspended,

at an address within sectors not

returns array data. The system can read from

any sector not selected for erasure.

selected for erasure,

programming in

erase suspend

at any address,

is not applicable.

9.5

Reading Toggle Bits DQ6/DQ2

Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row

to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the

toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as

DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or

erase operation. If it is still toggling, the device did not completed the operation successfully, and the system

must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous paragraph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the beginning of the algorithm when it returns to

determine the status of the operation.

9.6

9.7

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully

completed.

The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously

programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write the reset command to return to the read mode (or to the

erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors

are selected for erasure, the entire time-out also applies after each additional sector erase command. When

the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase

commands from the system can be assumed to be less than t_SEA, the system need not monitor DQ3. See

also the Sector Erase Command Sequence section.

After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands.

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To ensure the command has been accepted, the system software should check the status of DQ3 prior to and

following each subsequent sector erase command. If DQ3 is high on the second status check, the last

command might not have been accepted.

Table 9.2 shows the status of DQ3 relative to the other status bits.

Table 9.2 Write Operation Status

Status

DQ7 (2)

DQ7#

0

DQ6

DQ5 (1)

DQ3

N/A

1

DQ2 (2)

No toggle

Toggle

Embedded Program Algorithm

Embedded Erase Algorithm

Toggle

0

Standard

Mode

Erase Suspended

Sector

1

No toggle

0

N/A

Toggle

Erase Suspend

Read (4)

Erase

Suspend

Mode

Non-Erase Suspended

Sector

Data

0

Data

N/A

Data

N/A

Erase Suspend Program

DQ7#

Toggle

Notes

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the

section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in

progress. The device outputs array data if the system addresses a non-busy bank.

4. The system may read either asynchronously or synchronously (burst) while in erase suspend. RDY will function exactly as in non-erase-

suspended mode.

10. Absolute Maximum Ratings

Storage Temperature

Ambient Temperature with Power Applied

Voltage with Respect to Ground, All Inputs and I/Os except A (Note 1)

–65°C to +150°C

–65°C to +125°C

–0.5 V to V + 0.5 V

CC

cc

V

A

(1)

–0.5 V to +2.5 V

–0.5 V to +12.5 V

100 mA

CC

(2)

cc

Output Short Circuit Current (3)

Notes

1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, input at I/Os may undershoot V to –2.0 V for periods of up to

SS

20 ns during voltage transitions inputs might overshooot to V +0.5 V for periods up to 20 ns. See Figure 10.1. Maximum DC voltage on

CC

output and I/Os is V + 0.5 V. During voltage transitions outputs may overshoot to V + 2.0 V for periods up to 20 ns. See Figure 10.2.

CC

2. Minimum DC input voltage on A is –0.5 V. During voltage transitions, A may undershoot V to –2.0 V for periods of up to 20 ns. See

cc

SS

Figure 10.1. Maximum DC input voltage on A is +12.5 V which may overshoot to +13.5 V for periods up to 20 ns.

cc

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not

implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 10.1 Maximum Negative Overshoot Waveform

20 ns

+0.9 V

–2.0 V

20 ns

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Figure 10.2 Maximum Positive Overshoot Waveform

20 ns

V

+2.0 V

2.0 V

CC

20 ns

10.1 Operating Ranges

Ambient Temperature (T )

–25°C to +85°C

A

V

Supply Voltages

CC

V

min

+1.7 V

CC

V

max

+1.95 V

CC

Note

1. Operating ranges define those limits between which the functionality of the device is guaranteed.

11. DC Characteristics

11.1 CMOS Compatible

Parameter

Description

Input Load Current

Output Leakage Current

Test Conditions (1)

= V to V , V = V

CC max

Min

Typ

Max

1

Unit

µA

I

V

IN

LI

SS

CC CC

I

V

= V to V , V = V

CC max

1

µA

LO

OUT

SS

CC CC

I

V

Active Burst Read Current (5)

CE# = V , OE# = V

25

12

3.5

15

9

30

16

5

mA

µA

CCB

CC

IL

5 MHz

1 MHz

I

V

Active Asynchronous Read Current (2)

CE# = V , OE# = V

IL

CC1

CC

IH

I

V

Active Write Current (3)

Standby Current (4)

Reset Current

CE# = V , OE# = V , A = V

40

CC2

CC3

CC4

CC

IL

IH

cc

IH

CE# = V , RESET# = V

IH

RESET# = V CLK = V

9

µA

IL,

IL

Active Current

I

CE# = V , OE# = V

IL

40

60

mA

CC5

IL

(Read While Write)

I

7

5

7

5

15

10

15

10

0.4

PPW

Accelerated Program Current (6)

A

= 12 V

cc

I

CCW

I

PPE

Accelerated Erase Current (6)

A

mA

I

CCE

V

Input Low Voltage

–0.5

V

IL

V

Input High Voltage

V

– 0.4

V

+ 0.2

CC

IH

CC

V

Output Low Voltage

I

= 100 µA, V = V

CC min

0.1

OL

OH

OL

CC

V

Output High Voltage

Voltage for Accelerated Program

= –100 µA, V = V

CC min

– 0.1

OH

CC

V

11.5

1.0

12.5

1.4

ID

V

Low V Lock-out Voltage

CC

LKO

Notes

1. Maximum I specifications are tested with V = V max.

CC

2. The I current listed is typically less than 2 mA/MHz, with OE# at V

.

CC

IH

3.

I

active while Embedded Erase or Embedded Program is in progress.

CC

4. Device enters automatic sleep mode when addresses are stable for t

5. Specifications assume 8 I/Os switching and continuous burst length.

+ 60 ns. Typical sleep mode current is equal to I

.

ACC

CC3

6. Not 100% tested. A is not a power supply pin.

cc

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12. Test Conditions

Figure 12.1 Test Setup

Device

Under

Test

^CL

Table 12.1 Test Specifications

Test Condition

All Speeds

Unit

pF

ns

V

Output Load Capacitance, C (including jig capacitance)

L

30

5

Input Rise and Fall Times

Input Pulse Levels

0.0–V

CC

Input timing measurement reference levels

Output timing measurement reference levels

V

/2

V

CC

/2

V

13. Key to Switching Waveforms

Waveform

Inputs

Outputs

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State

(High Z)

13.1 Switching Waveforms

Figure 13.1 Input Waveforms and Measurement Levels

V_CC

V_CC/2

Input

Measurement Level

Output

0.0 V

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14. AC Characteristics

14.1

V

Power-up

CC

Parameter

Description

Test Setup

Min

Speed

50

Unit

µs

t

V

Setup Time

CC

VCS

t

RESET# Low Hold Time

Min

50

µs

RSTH

Figure 14.1 V_CCPower-up Diagram

t_VCS

V_CC

t_RSTH

RESET#

14.2 CLK Characterization

Parameter

Description

0L (54 MHz)

Unit

f

CLK Frequency

CLK Period

Max

Min

54

MHz

ns

CLK

t

18.5

t

CLK High Time

CLK Low Time

CLK Rise Time

CLK Fall Time

CH

Min

4.5

3

ns

t

CL

t

CR

Max

t

CF

Figure 14.2 CLK Characterization

t

CLK

t

CL

t

CF

t

CH

t

CR

CLK

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14.3 Synchronous/Burst Read

Parameter

0L

(54 MHz)

Description

Unit

JEDEC

Standard

t

Initial Access Time

Max

Min

Max

Min

Max

87.5

13.5

5

ns

IACC

t

Burst Access Time Valid Clock to Output Delay

AVD# Setup Time to CLK

BACC

t

AVDS

AVDH

AVDO

t

AVD# Hold Time from CLK

7

t

AVD# High to OE# Low

0

t

Address Setup Time to CLK

Address Hold Time from CLK

Data Hold Time from Next Clock Cycle (1))

Output Enable to Data, PS, or RDY Valid

Chip Enable to High Z

5

ACS

ACH

BDH

t

7

t

3

t

13.5

10

5

OE

t

CEZ

OEZ

CES

t

Output Enable to High Z

CE# Setup Time to CLK

t

RDY Setup Time to CLK

5

RDYS

RACC

t

Ready access time from CLK

13.5

Note:

1. Not 100% tested

Figure 14.3 Burst Mode Read (54 MHz)

5 cycles for initial access shown.

Programmable wait state function is set to 03h.

t_CEZ

t_CES

18.5 ns typ. (54 MHz)

CE#

CLK

t_AVDS

AVD#

t_AVDH

t_AVDO

t_ACS

t_BDH

A

–

max

A16

Aa

t_BACC

t_ACH

Hi-Z

A/DQ15–

A/DQ0

Aa

Da

Da + 1

t_IACC

Da + 2

Da + n

t_OEZ

OE#

RDY

t_RACC

t_OE

Hi-Z

t_RYDS

Notes:

1. Figure shows total number of clock set to five.

2. If any burst address occurs at a 64-word boundary, two additional clock cycles are inserted and are indicated by RDY.

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Figure 14.4 Burst Mode Read (40 MHz)

4 cycles for initial access shown.

Programmable wait state function is set to 02h.

t_CEZ

t_CES

25 ns typ.

CE#

CLK

t_AVDS

AVD#

t_AVDH

t_AVDO

t_ACS

t_BDH

A

–A16

max

Aa

t_BACC

t_ACH

Hi-Z

A/DQ15–

A/DQ0

Aa

Da

Da + 1

t_IACC

Da + 2

Da + n

t_OEZ

OE#

RDY

t_RACC

t_OE

Hi-Z

t_RYDS

Notes

1. Figure shows total number of clock cycles set to four.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and are indicated by RDY.

14.4 Asynchronous Read

Parameter

JEDEC Standard

0L

(54 MHz)

Description

Unit

t

Access Time from CE# Low

Asynchronous Access Time

AVD# Low Time

Max

Min

Max

Min

Max

70

12

5

ns

CE

t

ACC

t

AVDP

AAVDS

AAVDH

t

Address Setup Time to Rising Edge of AVD

Address Hold Time from Rising Edge of AVD

Output Enable to Output Valid

t

3.7

13.5

0

t

OE

Read

t

Output Enable Hold Time

OEH

Data# Polling

10

t

Output Enable to High Z (1)

OEZ

Note

1. Not 100% tested.

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Figure 14.5 Asynchronous Mode Read

CE#

OE#

WE#

t_OE

t_OEH

t_CE

t_OEZ

A/DQ15–

A/DQ0

RA

t_ACC

Valid RD

RA

A

–A16

max

t_AAVDH

AVD#

t_AVDP

t_AAVDS

Note

1. RA = Read Address, RD = Read Data.

14.5 Hardware Reset (RESET#)

Parameter

Description

All Speed Options

Unit

JEDEC

Std

RESET# Pin Low (During Embedded Algorithms) to

Read Mode (1)

t

Max

35

µs

ns

Readyw

RESET# Pin Low (NOT During Embedded Algorithms)

to Read Mode (1)

t

500

Ready

t

RESET# Pulse Width

Min

500

200

20

ns

µs

RP

t

Reset High Time Before Read (1)

RESET# Low to Standby Mode

RH

t

RPD

Note

1. Not 100% tested.

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Figure 14.6 Reset Timings

CE#, OE#

RESET#

t

RH

t

RP

t

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

CE#, OE#

RESET#

t

Ready

t

RP

14.6 Erase/Program Operations

Parameter

0L

(54 MHz)

Description

Unit

JEDEC

Standard

t

Write Cycle Time (1)

Address Setup Time

Address Hold Time

AVD# Low Time

Min

Typ

Min

Max

Typ

80

5

ns

µs

AVAV

WC

t

AVWL

WLAX

AS

t

7

AH

t

12

45

0

AVDP

t

Data Setup Time

Data Hold Time

DVWH

DS

t

WHDX

DH

t

Read Recovery Time Before Write

CE# Setup Time

0

GHWL

t

0

ELWL

WHEH

WLWH

WHWL

CS

t

CE# Hold Time

0

CH

t

/t

Write Pulse Width

50

30

0

WP WRL

t

Write Pulse Width High

Latency Between Read and Write Operations

WPH

t

SR/W

t

A

V

Rise and Fall Time

500

1

Acc

cc

t

Setup Time (During Accelerated Programming)

VPS

VCS

cc

t

Setup Time

50

35

100

1

CC

t

Sector Erase Accept Time-out

SEA

t

Erase Suspend Latency

ESL

ASP

PSP

t

Toggle Time During Sector Protection

Toggle Time During Programming Within a Prot

Notes

1. Not 100% tested.

2. See the Erase and Programming Performance section for more information.

3. Does not include the preprogramming time.

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Figure 14.7 Program Operation Timings

Program Command Sequence (last two cycles)

Read Status Data

t_AS

AVD#

t_AH

t_AVDP

PA

VA

A

–A16

max

In

A/DQ15–

A/DQ0

555h

Complete

A0h

PD

t_DS

t_DH

VA

Progress

CE#

t_CH

OE#

WE#

t_WP

t_WHWH1

t_CS

t_WPH

t_WC

V

IH

CLK

V_CC

V

IL

t_VCS

Notes

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3.

A

–A16 are don’t care during command sequence unlock cycles.

max

Figure 14.8 Chip/Sector Erase Operations

Erase Command Sequence (last two cycles)

Read Status Data

t_AS

AVD#

t_AH

t_AVDP

SA

555h for

chip erase

VA

A

–A16

max

10h for

chip erase

In

A/DQ15–

A/DQ0

2AAh

Complete

55h

SA

30h

VA

Progress

t_DS

t_DH

CE#

t_CH

OE#

WE#

t_WP

t_WHWH2

t_CS

t_WPH

t_WC

V

IH

CLK

V_CC

V

IL

t_VCS

Notes

1. SA is the sector address for Sector Erase.

2. Address bits A

–A16 are don’t cares during unlock cycles in the command sequence.

max

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Figure 14.9 Accelerated Unlock Bypass Programming Timing

CE#

AVD#

WE#

A

–A16

PA

max

A/DQ15

A/DQ0

–

Don't Care

A0h

PA

PD

Don't Care

CE#

t_VPS

V

ID

V_PP

t_VPP

or V

IL

IH

Notes

1.

A

can be left high for subsequent programming pulses.

cc

2. Use setup and hold times from conventional program operation.

Figure 14.10 Data# Polling Timings (During Embedded Algorithm)

AVD#

CE#

t_CEZ

t_CE

t_OEZ

t_CH

t_OE

OE#

WE#

t_OEH

t_ACC

High Z

A

–A16

VA

max

High Z

A/DQ15–

A/DQ0

VA

Status Data

Notes

1. All status reads are asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is completeData# Polling

will output true data.

Figure 14.11 Toggle Bit Timings (During Embedded Algorithm)

AVD#

t_CEZ

t_CE

CE#

t_OEZ

t_CH

t_OE

OE#

WE#

t_OEH

t_ACC

High Z

A

–A16

VA

max

A/DQ15–

A/DQ0

VA

Status Data

Notes

1. All status reads are asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, .

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Figure 14.12 8-, 16-, and 32-Word Linear Burst Address Wrap Around

Address wraps back to beginning of address group.

Initial Access

39

CLK

39

3A

3B

3C

3D

3E

3F

38

Address (hex)

A/DQ15–

A/DQ0

D0

D1

D2

D3

D4

D5

D6

D7

V

IH

AVD#

OE#

V

IL

V

IH

IL

(stays low)

V

IL

CE#

Note

1. 8-word linear burst mode shown. 16- and 32-word linear burst read modes behave similarly. D0 represents the first word of the linear

burst.

Figure 14.13 Latency with Boundary Crossing

Address boundary occurs every 64 words, beginning at address

00003Fh: 00007Fh, 0000BFh, etc. Address 000000h is also a boundary crossing.

C60

C61

C62

C63

C64

C65

C66

C67

CLK

3C

(stays high)

3D

3E

3F

40

41

42

43

Address (hex)

V

IH

AVD#

RDY

V

IL

t_RACC

latency

A/DQ15–

A/DQ0

D60

D61

D62

D63

D64

D65

D66

D67

V

IH

OE#,

CE#

(stays low)

V

IL

Note

1. Cxx indicates the clock that triggers data Dxx on the outputs; for example, C60 triggers D60.

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Figure 14.14 Initial Access at 3Eh with Address Boundary Latency

AVD# low with clock

present enables

burst read mode

device is programmable from 2 to 7 total cycles

during initial access (here, programmable wait state

function is set to 04h; 6 cycles total)

2 additional

wait states if

address is

at boundary

CLK

AVD#

RDY

A/DQ15–

A/DQ0

High-Z

D0

D1

Address

D2

A

–A16

OE#

max

t_OE

Note

1. Devices should be programmed with wait states as discussed in Programmable Wait State on page 21.

Figure 14.15 Example of Extended Valid Address Reducing Wait State Usage

CE#

A/DQ

Addresses

D0

D1

D2

t_IACC

AVD#

CLK

OE#

RDY

t_AVDSM

Hi-Z

Note

1. If t

> 1 CLK cycle, wait state usage is reduced. Figure shows 40 MHz clock, handshaking enabled. Wait state usage is 4 clock

AVDSM

cycles instead of 5. Note that t

must be less than 76 µs for burst operation to begin.

AVDSM

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Figure 14.16 Back-to-Back Read/Write Cycle Timings

Last Cycle in

Program or

Sector Erase

Read status (at least two cycles) in same bank

and/or array data from other bank

Begin another

write or program

command sequence

Command Sequence

t_WC

t_RC

t_WC

CE#

OE#

t_OE

t_OEH

t_GHWL

WE#

t_WPH

t_OEZ

t_WP

t_DS

t_ACC

t_OEH

t_DH

RA

A/DQ15–

A/DQ0

RA

PA/SA

PD/30h

RD

555h

AAh

t_SR/W

RA

A

–A16

max

PA/SA

t_AS

AVD#

t_AH

Note

1. Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking the status of the

program or erase operation in the “busy” bank. The system should read status twice to ensure valid information.

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15. Erase and Programming Performance

Parameter

Typ (1)

Max (2)

Unit

Comments

32 Kword

8 Kword

0.4

0.2

108

54

27

13.5

9

5

Sector Erase Time

s

128 Mb

64 Mb

32 Mb

16 Mb

Excludes 00h programming

prior to erasure (4)

s

Chip Erase Time

Word Programming Time

210

120

288

144

72

µs

Excludes system level

overhead (5)

Accelerated Word Programming Time

4

128 Mb

64 Mb

32 Mb

16 Mb

128 Mb

64 Mb

32 Mb

16 Mb

128 Mb

64 Mb

32 Mb

16 Mb

96

48

24

12

32

16

8

s

Chip Programming Time (3)

36

96

s

48

Excludes system level

overhead (5)

Accelerated Chip Programming Time

24

4

12

50

25

12.5

6.25

Accelerated Chip Erase Time

Notes

^{1. Typical program and erase times assume the following conditions: 25}°C, 1.8 V V , 100,000 cycles. Additionally, programming typicals

CC

assume checkerboard pattern.

2. Under worst case conditions of 90°C, V = 1.7 V, 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed.

4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 8.16 for

further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles.

16. BGA Ball Capacitance

Parameter Symbol

Parameter Description

Input Capacitance

Test Setup

= 0

Typ

4.2

5.4

3.9

Max

5.0

6.5

4.7

Unit

pF

C

V

IN

C

Output Capacitance

Control Pin Capacitance

V

= 0

pF

OUT

C

V

= 0

IN

pF

IN2

Notes

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

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17. Physical Dimensions

17.1 S29NS128J

VDC048—48-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 10 x 11 mm Package

A

D

D1

A1 CORNER

INDEX MARK

A1 CORNER

10

9

8

7

6

5

4

3

2

1

NF2

NF1

NF3

NF4

A

B

C

D

e

E1

E

SE

1.00

7

NF5

NF6

1.00

NF7

NF8

B

SD

1.00 1.00

7

φb

6

0.10

0.08

C

A2

φ 0.15 M

φ 0.05 M

C

A B

A

A1

C

SEATING PLANE

NOTES:

PACKAGE

JEDEC

VDC 048

N/A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

9.95 mm x 10.95 mm NOM

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

0.86

0.20

0.66

9.85

10.85

NOM

---

MAX

1.00

---

NOTE

OVERALL THICKNESS

BALL HEIGHT

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

---

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

0.71

9.95

10.95

4.50

1.50

10

0.76

BODY THICKNESS

10.05 BODY SIZE

11.05 BODY SIZE

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

MD

ME

N

BALL FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

4

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

48

φb

0.25

0.30

0.50

0.25

0.35

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

e

BALL PITCH

SD / SE

SOLDER BALL PLACEMENT

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3241 \ 16-038.9h.aa01

Note

1. For reference only. BSC is an ANSI standard for Basic Space Centering.

64

S29NS-J

S29NS-J_00_A11 February 7, 2007

D a t a S h e e t

17.2 S29NS064J

VDD044—44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 9.2 x 8 mm Package

A

D

D1

A1 CORNER

INDEX MARK

A1 CORNER

10

9

8

7

6

5

4

3

2

1

NF2

NF1

A

B

C

D

e

E

E1

SE

1.00

7

NF4

NF3

1.00

SD

B

7

B

TOP VIEW

SIDE VIEW

φb

6

φ 0.15

φ 0.05

M

C A

C

M

0.10

0.08

C

A2

A

BOTTOM VIEW

A1

SEATING PLANE

C

NOTES:

PACKAGE

JEDEC

VDD 044

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

N/A

8.00 mm x 9.20 mm NOM

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

0.86

0.20

0.66

NOM

---

MAX

1.00

---

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

OVERALL THICKNESS

BALL HEIGHT

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

---

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

0.71

8.00

9.20

4.50

1.50

10

0.76

8.10

9.30

BODY THICKNESS

BODY SIZE

7.90

9.10

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

MD

ME

N

BALL FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

4

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

44

φb

0.25

0.30

0.50

0.25

0.35

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

e

BALL PITCH

SD / SE

SOLDER BALL PLACEMENT

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3239 \ 16-038.9h.aa01

Note

1. For reference only. BSC is an ANSI standard for Basic Space Centering.

February 7, 2007 S29NS-J_00_A11

S29NS-J

65

D a t a S h e e t

17.3 S29NS032J and S29NS016J

VDE044—44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 7.7 x 6.2 mm Package

D1

A

D

A1 CORNER

INDEX MARK

A1 CORNER

10

9

8

7

6

5

4

3

2

1

10

NF2

NF1

e

A

B

C

D

E

B

E1

SE

1.00

7

NF4

NF3

1.00

SD

B

7

TOP VIEW

φb

6

φ 0.05

φ 0.15

M

C

C A

0.10

C

A2

A

BOTTOM VIEW

0.08

C

A1

SEATING PLANE

C

SIDE VIEW

NOTES:

PACKAGE

JEDEC

VDE 044

N/A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

7.70 mm x 6.20 mm NOM

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

0.86

0.20

0.66

7.65

6.15

NOM

---

MAX

1.00

---

NOTE

OVERALL THICKNESS

BALL HEIGHT

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

---

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

0.71

7.7

0.76

7.75

6.25

BODY THICKNESS

BODY SIZE

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

6.2

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

MD

ME

N

4.50

1.50

10

BALL FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

4

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

44

φb

0.25

0.30

0.50 BSC.

0.25 BSC.

0.35

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

e

BALL PITCH

SD / SE

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3308.1 \ 16-038.9L

Note

1. For reference only. BSC is an ANSI standard for Basic Space Centering.

66

S29NS-J

S29NS-J_00_A11 February 7, 2007

D a t a S h e e t

18. Appendix A: Daisy Chain Information

Table 18.1 Daisy Chain Part for 128Mbit 110 nm Flash Products (VDC048, 10 x 11 mm)

Package

Marking

Daisy Chain

Connection

Spansion 128Mb Flash

Part Number

Daisy Chain Part Number

Flash Description

Lead (Pb) - Free Compliant:

AM29N128HVCD21CT

N128HD21C

Die Level

S29NS128J

128Mbit 110nm

Lead (Pb) - Free:

Am29N128HVCD21CFT

N128HD21CF

Table 18.2 VDC048 Package Information

Component Type/Name

VDC048

Solder resist opening

Daisy Chain Connection Level

Lead-Free Compliant

Quantity per Reel

0.25 + 0.05 mm

On die

Yes

550 (300 units per reel by special request to factory)

Table 18.3 VDC048 Connections

C1–D1

C2–D2

C3–D3

C4–D4

C5–D5

C6–D6

C7–D7

A10–B10

A9–B9

A8–B8

A7–B7

A6–B6

A5–B5

A4–B4

A3–B3

A2–B2

A1–B1

C8–D8

C9–D9

C10–D10

On substrate

NF1–NF4

NF16-NF19

NF2–NF5

NF17-NF20

Figure 18.1 VDC048 Daisy Chain Layout (Top View, Balls Facing Down)

NF2

NF1

NF4

NF5

1

2

3

4

5

6

7

8

9

10

A

B

C

D

NF16

NF17

NF19

NF20

February 7, 2007 S29NS-J_00_A11

S29NS-J

67

D a t a S h e e t

19. Appendix B: Daisy Chain Information

Table 19.1 Daisy Chain Part for 64Mbit 110 nm Flash Products (VDD044, 9.2 x 8 mm)

Daisy Chain

Connection

Spansion 64Mb Flash

Part Number

Daisy Chain Part Number

Package Marking

Description

Lead (Pb) - Free Compliant:

AM29N643GVAD21CT

N643GD21C

Die Level

S29NS064J

64Mbit 110nm

Lead (Pb)- Free:

AM29N643GVAD21CFT

N643GD21CF

Table 19.2 VDD044 Package Information

Component Type/Name

VDD044

Solder resist opening

Daisy Chain Connection Level

Lead-Free Compliant

Quantity per Reel

0.25 + 0.05 mm

On die

Yes

600 (300 units per reel by special request to factory)

Table 19.3 VDD044 Connections

C1–D1

C2–D2

C3–D3

C4–D4

C5–D5

C6–D6

C7–D7

A10–B10

A9–B9

A8–B8

A7–B7

A6–B6

A5–B5

A4–B4

A3–B3

A2–B2

A1–B1

C8–D8

C9–D9

C10–D10

On substrate

NF1–NF3

NF2–NF4

Figure 19.1 VDD044 Daisy Chain Layout (Top View, Balls Facing Down)

NF1

NF2

1

2

3

4

5

6

7

8

9

10

A

B

C

D

NF3

NF4

68

S29NS-J

S29NS-J_00_A11 February 7, 2007

D a t a S h e e t

20. Appendix C: Daisy Chain Information

Table 20.1 Daisy Chain Part for 32 and 16 Mbit 110 nm Flash Products (VDE044, 7.7 x 6.2 mm)

Daisy Chain

Connection

Spansion 64Mb Flash

Part Number

Daisy Chain Part Number

Package Marking

Description

Lead (Pb) - Free Compliant:

S99DCVDE044SDA002

99DCVDE044SDA00

S29NS032J

S29NS016J

64Mbit 110nm

32Mbit 110nm

Die Level

Lead (Pb)- Free:

S99DCVDE044SDF002

99DCVDE044SDF00

Table 20.2 VDE044 Package Information

Component Type/Name

VDE044

Solder resist opening

0.25 + 0.05 mm

On die

Daisy Chain Connection Level

Lead-Free Compliant

Yes

Quantity per 7-inch Reel

600 (300 units per reel by special request to factory)

Table 20.3 VDE044 Connections

C1–D1

C2–D2

C3–D3

C4–D4

C5–D5

C6–D6

C7–D7

A10–B10

A9–B9

A8–B8

A7–B7

A6–B6

A5–B5

A4–B4

A3–B3

A2–B2

A1–B1

C8–D8

C9–D9

C10–D10

On substrate

NF1–NF3

NF2–NF4

Figure 20.1 VDE044 Daisy Chain Layout(Top View, Balls Facing Down)

NF1

NF2

1

2

3

4

5

6

7

8

9

10

A

B

C

D

NF3

NF4

February 7, 2007 S29NS-J_00_A11

S29NS-J

69

D a t a S h e e t

21. Revision History

Section

Description

Revision A (May 16, 2003)

Initial release

Revision A1 (August 11, 2003)

Connection Diagram

Modified Connection Diagrams for Am29N129J and S29NS064J.

Changed VSS to GND, removed VCCQ and VSSQ.

Input/Output Descriptions

Requirements for Synchronous

(Burst) Read Operation, Continuous First paragraph, bold text, second sentence: the highest address changed to 000000h.

Burst

RESET#: Hardware Reset Input

Autoselect Command Sequence

Fourth paragraph: t_READYchanged to t_READYW

Added Table 11 title, Autoselect Device ID

WP# Boot Sector Protection, Low

VCC Write Inhibit, Table immediately

preceding Program Command

Sequence section

Modified Read Data for Device ID, Word 1, Device ID, Word 2 for S29NS064J only,

Device ID, Word 3

Added Notes 10 and 12; changed BA = Address of the bank from A22-A20 to A22-A21 for

S29NS128J, A21-A19 to A21-A20 for S29NS064J.

Table 14, Command Definitions

Added I_CCW, Typ and Max values for I_PPWand I_CCW; added I_CCE, Typ and Max values for I_PPEand

AC Characteristics CMOS

Compatible

I_CCE

.

AC Characteristics, Figure 15, 16, 18,

and 19

Changed AVD to AVD#

Revision A2 (August 19, 2003)

Requirements for Synchronous

(Burst) Read Operation

Modified bold text to indicate “highest address to 00000h”

Revision A3 (September 10, 2003)

DC Characteristics, CMOS

Compatible

Changed ICC3 and ICC4 Max values

Converted to Spansion format

Revision A4 (November 13, 2003)

Global

Revision A5 (February 5, 2004)

Added 0L Clock rate/asynchronous speed.

Updated Valid combinations to reflect addition

Ordering Information

Appendix C and D

Added these sections

Revision A6 (April 7, 2004)

Removed Pb-Free Compliant options from 32 Megabit and 16 Megabit combinations for both 66

MHz and 54 MHz

Ordering Information

Global

Corrected figure references

AC Characteristics

Modified the t

timing in Figure 14 in Hardware Reset (RESET#)

READY

Erase and Programming

Performance

Added density and typical values to Accelerated Chip Erase Time parameter.

Removed section

Data Retention

Revision A7 (August 4, 2004)

Changed all instances of “FASL” to “Spansion”.

Added Colophon text.

Global

Sector Erase Command Sequence

Replaced “” with “

70

S29NS-J

S29NS-J_00_A11 February 7, 2007

D a t a S h e e t

Section

Description

Replaced “SA0–SA7” with “SA0–SA3”.

Replaced “SA8–SA15” with “SA4–SA7”.

Replaced “SA16–SA23” with “SA8–SA11”.

Replaced “SA24–SA31” with “SA56–SA59”.

Deleted “SA40–SA47”.

Accelerated Sector Erase Groups,

S29NS032J

Deleted “SA48–SA55”.

Replaced “SA56–SA62” with “SA60–SA62”.

Replaced “SA0–SA7” with “SA0–SA1”.

Replaced “SA8–SA15” with

Replaced “SA16–SA23” with

Replaced “SA24–SA30” with

Accelerated Sector Erase Groups,

S29NS016J

Added the following: SA8-SA9; SA10-SA11; SA12-SA13; SA14-SA15; SA16-SA17; SA18-SA19;

SA20-SA21; SA22-SA23; SA24-SA25; SA26-SA27; SA28-SA29; SA30

Replaced “

Erase Suspend/Erase Resume

Commands

Replaced “

DQ7: Data# Polling

Replaced “

DQ6: Toggle Bit I

Replaced “µ

DQ3: Sector Erase Timer

Replaced “

Updated “Accelerated Chip Erase Time” as per the following:

Original

45

Updated

50

128Mb

64Mb

32Mb

16Mb

Erase and Programming

Performance

30

25

TBD

12.5

6.25

Deleted the following:

“Minimum 100,000 erase cycle guarantee per sector”.

“20-year data retention”.

Distinctive Characteristics

“Reliable operation for the life of the system”

Erase and Programming

Performance

In Note 2 changed “100,000” to “1,000,000”

Updated drawing.

8-, 16-, and 32-Word Linear Burst

Address Wrap Around

Removed “The host system may also initiate the chip erase and sector erase sequences in the

Unlock Bypass Command Sequence unlock bypass mode. The erase command sequences are four cycles in length instead of six

cycles.”

Command Definitions

Removed the Unlock Bypass “sector erase” and “chip erase” rows.

Removed Unlock Bypass Sector Erase section.

Removed Chip Erase section

Table 18, “Command Definitions”

Updated 2nd paragraph as follows: “If using the Unlock Bypass feature: on the 2nd program cycle,

after the Unlock Bypass command is written, the WP# signal must be asserted on the 2nd cycle.”

WP# Boot Sector Protection

Global

Replaced all “AMD” references with “contact your local Spansion sales office”

Removed “The host system may also initiate the chip erase command sequence while the device is

in the unlock bypass mode. The command sequence is two cycles in length instead of six cycles

Chip Erase Command Sequence

Replaced “50 µs” with “Removed the following “The host system may also initiate the sector erase

command sequence while the device is in the unlock bypass mode. The command sequence is four

cycles in length instead of six cycles.

Sector Erase Command Sequence

February 7, 2007 S29NS-J_00_A11

S29NS-J

71

D a t a S h e e t

Section

Description

Removed the following rows from table:

t_WHWH1t_WHWH1

t_WHWH2t_WHWH2

Programming Operation

Typ

9

4

µs

Erase/Program Operations

Accelerated Programming Operation

Sector Erase Operation

Typ 0.4 sec

Revision A8 (September 14, 2004)

Ordering Information

Added packing types 0 and 2.

Added Packing Type information

Valid Combinations

Revision A9 (November 11, 2005)

Ordering Information

Added LF35 package ordering option

Revision A10 (March 22, 2006)

Global

Changed V_PPto ACC.

AC Characteristics

Asynchronous Read table: updated the values of t_AAVDHfor both speed bins.

Revision A11 (February 7, 2007)

Updated document to new template.

Removed 66 MHz option

Global

72

S29NS-J

S29NS-J_00_A11 February 7, 2007

D a t a S h e e t

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as

contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to

you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal

operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under

the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,

the prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under

development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this

document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,

merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any

damages of any kind arising out of the use of the information in this document.

thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.

February 7, 2007 S29NS-J_00_A11

S29NS-J

73


型号：	S29NS016J0LBJW002
厂家：	SPANSION
描述：	Burst Mode Flash Memories 突发模式闪存产品闪存存储内存集成电路
文件：	总73页 (文件大小：2691K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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