S29PL256N80FAI002 [SPANSION]
256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory; 256/128/128 MB( 16/8/8的M× 16位)的CMOS , 3.0伏只同步读/写,页模式闪存![S29PL256N80FAI002](http://pdffile.icpdf.com/pdf1/p00114/img/icpdf/S29PL127N65FAI000_622817_icpdf.jpg)
型号: | S29PL256N80FAI002 |
厂家: | ![]() |
描述: | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
文件: | 总85页 (文件大小:1296K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
S29PL-N MirrorBit™ Flash Family
29PL256N, S29PL127N, S29PL129N,
256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only
Simultaneous Read/Write, Page-Mode Flash Memory
PRELIMINARY
Data Sheet
Notice to Readers: This document indicates states the current technical
specifications regarding the Spansion product(s) described herein. The
Preliminary status of this document indicates that a product qualification has
been completed, and that initial production has begun. Due to the phases of
the manufacturing process that require maintaining efficiency and quality, this
document may be revised by subsequent versions or modifications due to
changes in technical specifications.
Publication Number S29PL-N_00 Revision
A Amendment 4 Issue Date November 23, 2005
P r e l i m i n a r y
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, includ-
ing development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to
highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more spe-
cific products, but has not committed any design to production. Information presented in a
document with this designation is likely to change, and in some cases, development on the prod-
uct may discontinue. Spansion LLC therefore places the following conditions upon Advance
Information content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product
life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these as-
pects of production under consideration. Spansion places the following conditions upon
Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-
tions due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance In-
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or V range. Changes
IO
may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
ii
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
S29PL-N MirrorBit™ Flash Family
S29PL256N, S29PL127N, S29PL129N,
256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only
Simultaneous Read/Write, Page-Mode Flash Memory
Data Sheet
PRELIMINARY
General Description
The Spansion S29PL-N is the latest generation 3.0-Volt page mode read family fabricated using the 110 nm MirrorbitTM
Flash process technology. These 8-word page-mode Flash devices are capable of performing simultaneous read and write
operations with zero latency on two separate banks. These devices offer fast page access times of 25 to 30 ns, with
corresponding random access times of 65 ns, 70 ns, and 80 ns respectively, allowing high speed microprocessors to op-
erate without wait states. The S29PL129N device offers the additional feature of dual chip enable inputs (CE1# and
CE2#) that allow each half of the memory space to be controlled separately.
Distinctive Characteristics
Architectural Advantages
Hardware Features
32-Word Write Buffer
WP#/ACC (Write Protect/Acceleration) Input
— At VIL, hardware level protection for the first and last
two 32 Kword sectors.
— At VIH, allows the use of DYB/PPB sector protection
— At VHH, provides accelerated programming in a
factory setting
Dual Chip Enable Inputs (only for S29PL129N)
— Two CE# inputs control selection of each half of the
memory space
Single Power Supply Operation
— Full Voltage range of 2.7 – 3.6 V read, erase, and
program operations for battery-powered applications
— Voltage range of 2.7 – 3.1 V valid for PL-N MCP
products
Dual Boot and No Boot Options
Low VCC Write Inhibit
Security Features
Simultaneous Read/Write Operation
Persistent Sector Protection
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
— A command sector protection method to lock
combinations of individual sectors to prevent
program or erase operations within that sector
— Sectors can be locked and unlocked in-system at VCC
level
4-Bank Sector Architecture with Top and Bottom
Boot Blocks
256-Word Secured Silicon Sector Region
— Up to 128 factory-locked words
— Up to 128 customer-lockable words
Password Sector Protection
— A sophisticated sector protection method locks
combinations of individual sectors to prevent program
or erase operations within that sector using a user
defined 64-bit password
Manufactured on 0.11 µm Process Technology
Data Retention of 20 years Typical
Cycling Endurance of 100,000 Cycles per Sector
Typical
Performance Characteristics
Read Access Times (@ 30 pF, Industrial Temp.)
Typical Program & Erase Times (typical values) (See Note)
Typical Word
Typical Effective Word (32 words in buffer)
40 µs
9.4 µs
6 µs
Random Access Time, ns (tACC
Page Access Time, ns (tPACC
)
65
25
65
25
70
30
70
30
80
30
80
30
)
Accelerated Write Buffer Program
Max CE# Access Time, ns (tCE
)
Typical Sector Erase Time (32-Kword Sector)
Typical Sector Erase Time (128-Kword Sector)
300 ms
1.6 s
Max OE# Access Time, ns (tOE
)
Note: : Typical program and erase times assume the following
conditions: 25°C, 3.0 V VCC, 10,000 cycles; checkerboard data pattern.
Current Consumption (typical values)
Package Options
8-Word Page Read
6 mA
65 mA
25 mA
20 µA
VBH064
8.0 x 11.6 mm,
64-ball
VBH084
8.0 x 11.6 mm,
84-ball
LAA064
11 x 13 mm, 64-ball
Fortified BGA
Simultaneous Read/Write
Program/Erase
Standby
S29PL-N
256
129
127
Publication Number S29PL-N_00 Revision
A
Amendment 4 Issue Date November 23, 2005
P r e l i m i n a r y
Contents
1
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Input/Output Descriptions and Logic Symbols . . . . . . . . . . . . . . . . . . . . . . 7
3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Connection Diagrams/Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Special Handling Instructions for FBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2 VBH084, 8.0 x 11.6 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2.1 Connection Diagram – S29PL256N MCP Compatible Package. . . . . . . . . . . . . . . . . .9
4.2.2 Physical Dimensions – VBH084, 8.0 x 11.6 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 VBH064, 8 x 11.6 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.1 Connection Diagram – S29PL127N MCP Compatible Package . . . . . . . . . . . . . . . . . 11
4.3.2 Connection Diagram – S29PL129N MCP Compatible Package . . . . . . . . . . . . . . . . . 12
4.3.3 Physical Dimensions – VBH064, 8 x 11.6 mm – S29PL-N . . . . . . . . . . . . . . . . . . . . . . 13
4.3.4 Connection Diagram – S29PL-N Fortified Ball Grid Array Package . . . . . . . . . . . . . 14
4.3.5 Physical Dimensions – LAA064, 11 x 13 mm – S29PL-N . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 MCP Look-Ahead Connection Diagram/Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 16
4.4.1 For All Page Mode MCPs Comprised of Code Flash + (p)SRAM + Data Flash. . . . . . 16
5 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
6 Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
7.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1.1 Dual Chip Enable Device Description and Operation (PL129N Only) . . . . . . . . . . . 21
7.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7.2.1 Non-Page Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7.2.2 Page Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7.3 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7.4 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7.4.1 Single Word Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7.4.2 Write Buffer Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7.4.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7.4.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
7.4.5 Erase Suspend/Erase Resume Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
7.4.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
7.4.7 Accelerated Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.4.8 Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
7.4.9 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
7.5 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
7.6 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
7.7 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
7.8 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
8 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . 48
8.1 Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
8.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
8.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
8.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
8.5 Password Protection Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.7 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.7.1 WP# Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.7.2 Low VCC Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.7.3 Write Pulse Glitch Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.7.4 Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
9 Power Conservation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
9.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9.3 Hardware RESET# Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
10 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . 56
10.1 Factory Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
10.2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
10.3 Secured Silicon Sector Entry and Exit Command Sequences. . . . . . . . . . . . . . . . . . . . . . . .57
11 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
11.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.3 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.6 VCC Power Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.7 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
11.7.1 DC Characteristics (VCC = 2.7 V to 3.6 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
11.7.2 DC Characteristics (VCC = 2.7 V to 3.1 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
11.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
11.8.1 Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
11.8.2 Read Operation Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
11.8.3 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
11.8.4 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
11.8.5 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
11.8.6 BGA Ball Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
12.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
13 Commonly Used Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
14 Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
3
P r e l i m i n a r y
Tables
Table 2.1
Table 6.1
Table 6.2
Table 6.3
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
Table 7.8
Table 7.9
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
PL256N Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PL127N Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PL129N Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Dual Chip Enable Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Word Selection within a Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Autoselect Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Write Buffer Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Sector Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7.10 Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7.11 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7.12 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7.13 Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 7.14 Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 7.15 Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7.16 Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7.17 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7.18 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 7.19 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 8.1
Table 8.2
Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Sector Protection Schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 10.1 Secured Silicon Sector Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 10.2 Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 10.3 Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 10.4 Secured Silicon Sector Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 11.1 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 12.1 Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 12.2 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 12.3 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 12.4 System Interface String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 12.5 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 12.6 Primary Vendor-Specific Extended Query. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
Figures
Figure 2.1
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Figure 4.7
Figure 4.8
Logic Symbols – PL256N, PL129N, and PL127N .........................................................7
Connection Diagram – 84-ball Fine-Pitch Ball Grid Array (S29PL256N)..........................9
Physical Dimensions – 84-ball Fine-Pitch Ball Grid Array (S29PL256N)........................ 10
Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL127N) ....................... 11
Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL129N) ....................... 12
Physical Dimensions – 64-Ball Fine-Pitch Ball Grid Array (S29PL-N)...........................................13
Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL127N, S29PL256N) ............14
Physical Dimensions – 64-Ball Fortified Ball Grid Array (S29PL-N)..............................................15
MCP Look-Ahead Diagram .................................................................................... 16
Figure 7.1
Figure 7.2
Single Word Program Operation ............................................................................ 27
Write Buffer Programming Operation ..................................................................... 30
Figure 7.3
Figure 7.4
Figure 7.5
Figure 7.6
Sector Erase Operation ........................................................................................32
Write Operation Status Flowchart .......................................................................... 39
Simultaneous Operation Block Diagram for S29PL256N and S29PL127N ..................... 43
Simultaneous Operation Block Diagram for S29PL129N ............................................ 44
Figure 8.1
Figure 8.2
Advanced Sector Protection/Unprotection...............................................................48
Lock Register Program Algorithm........................................................................... 52
Figure 11.1
Figure 11.2
Figure 11.3
Figure 11.4
Figure 11.5
Figure 11.6
Figure 11.7
Figure 11.8
Figure 11.9
Maximum Negative Overshoot Waveform ...............................................................59
Maximum Positive Overshoot Waveform.................................................................59
Test Setup ......................................................................................................... 60
Input Waveforms and Measurement Levels............................................................. 61
VCC Power-Up Diagram ........................................................................................61
Read Operation Timings.......................................................................................64
Page Read Operation Timings ............................................................................... 65
Reset Timings..................................................................................................... 65
Program Operation Timings .................................................................................. 67
Figure 11.10 Accelerated Program Timing Diagram ....................................................................67
Figure 11.11 Chip/Sector Erase Operation Timings..................................................................... 68
Figure 11.12 Back-to-back Read/Write Cycle Timings .................................................................68
Figure 11.13 Data# Polling Timings (During Embedded Algorithms).............................................. 69
Figure 11.14 Toggle Bit Timings (During Embedded Algorithms)................................................... 69
Figure 11.15 DQ2 vs. DQ6...................................................................................................... 70
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
5
P r e l i m i n a r y
1 Ordering Information
The ordering part number is formed by a valid combination of the following:
S29PL 256
N
65 GA W W0 0
PACKING TYPE
0
2
3
=
=
=
Tray
7-inch Tape and Reel
13-inch Tape and Reel
MODEL NUMBER
(VCC Range)
W0
00
=
=
2.7 – 3.1 V
2.7 – 3.6 V
TEMPERATURE RANGE
W
I
=
=
Wireless (–25°C to +85°C)
Industrial (–40°C to +85°C)
PACKAGE TYPE AND MATERIAL
FA
FF
=
=
=
Fortified BGA, Lead (Pb)-free Compliant package
Fortified BGA, Lead (Pb)-free package
Very Thin Fine-Pitch MCP-compatible BGA,
Lead (Pb)-free Compliant Package
Very Thin Fine-Pitch MCP-compatible BGA,
Lead (Pb)-free Package
GA
GF
=
SPEED OPTION
65
70
80
=
=
=
65 ns
70 ns
80 ns
PROCESS TECHNOLOGY
110 nm MirrorBit™ Technology
N
=
FLASH DENSITY
256
129
127
=
=
=
256 Mb
128 Mb (Dual CE#)
128 Mb (Single CE#)
DEVICE FAMILY
S29PL
=
3.0 Volt-only Simultaneous Read/Write, Page Mode Flash Memory
Valid Combinations
Package Type
VIO Range
Base Ordering
Part Number
Speed
Option
Package Type, Material,
& Temperature Range Number
Model
Packing
Type
(Note 2)
VBH084 8.0 x 11.6 mm
S29PL256N
84-ball MCP-Compatible (FBGA)
0, 2, 3
65, 70
GAW, GFW
FAW, FFW
W0
00
2.7 – 3.1 V
2.7 – 3.6 V
(Note 1)
S29PL127N
S29PL129N
VBH064 8.0 x 11.6 mm
64-ball MCP-Compatible (FBGA)
S29PL256N,
S29PL127N
0, 2, 3
(Note 1)
LAA064 11x13 mm
64-Ball (Fortified BGA)
80
Notes:
1. Type 0 is standard. Specify other options as required.
Valid Combinations
2. BGA package marking omits leading S29 and packing
Valid Combinations list configurations planned to be
supported in volume for this device. Consult your local sales
office to confirm availability of specific valid combinations
and to check on newly released combinations.
type designator from ordering part number.
6
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
2 Input/Output Descriptions and Logic Symbols
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
Type
Description
Amax – A0
Input
Address bus
DQ15 – DQ0 I/O
16-bit data inputs/outputs/float
Chip Enable input
Output Enable input
Write Enable
CE#
OE#
WE#
VSS
Input
Input
Input
Supply
Device ground
NC
Not connected Pin Not Connected Internally
Ready/Busy output and open drain.
When RY/BY#= VIH, the device is ready to accept read operations and commands.
When RY/BY#= VOL, the device is either executing an embedded algorithm or the device
is executing a hardware reset operation.
RY/BY#
Output
VCC
Supply
Input
Device Power Supply
RESET#
Hardware reset pin
CE1#, CE2# Input
Chip Enable inputs for S29PL129 device
max +1
22
A21 – A0
Amax–A0
16
16
DQ15 – DQ0
DQ15 – DQ0
CE#
OE#
WE#
CE1#
CE2#
OE#
WP#/ACC
RESET#
VCC
WE#
RY/BY#
RY/BY#
WP#/ACC
RESET#
VCC
Notes:
1. Amax = 23 for the PL256N and 22 for the PL127N.
Logic Symbol – PL256N and PL127N
Logic Symbol – PL129N
Figure 2.1 Logic Symbols – PL256N, PL129N, and PL127N
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
7
P r e l i m i n a r y
3 Block Diagram
DQ15–DQ0
RY/BY# (See Note)
V
CC
V
SS
Sector
Switches
Input/Output
Buffers
RESET#
WE#
Erase Voltage
Generator
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
Data Latch
Y-Gating
Y-Decoder
X-Decoder
V
CC
Detector
Timer
Amax – A3
Cell Matrix
A2–A0
Notes:
1. RY/BY# is an open drain output.
2. Amax = A23 (PL256N), A22 (PL127N), A21 (PL129N).
3. PL129N has two CE# pins CE1# and CE2#.
8
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
4 Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S29PL256N.
4.1
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning meth-
ods. The package and/or data integrity may be compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of time.
4.2 VBH084, 8.0 x 11.6 mm
4.2.1 Connection Diagram – S29PL256N MCP Compatible Package
A10
NC
A1
NC
B2
B3
RFU
C3
B4
RFU
C4
B5
RFU
B6
RFU
C6
B7
RFU
C7
B8
RFU
C8
B9
RFU
C9
Legend
RFU
C5
C2
RFU
D2
Reserved for
Future Use
RFU
D9
A7
RFU
D4
WP#/ACC
D5
WE#
D6
A8
A11
D8
D3
A6
D7
A3
E2
A2
F2
A1
RFU
E4
RST#
E5
RFU
E6
A19
E7
A12
E8
A15
E9
E3
A5
F3
A4
A18
F4
RY/BY#
F5
A20
F6
A9
F7
A13
F8
A21
F9
A17
A10
A14
A22
RFU
A23
G2
A0
G3
G4
G7
G8
G9
G5
G6
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
J9
J2
J3
J4
DQ10
K4
J5
J6
J7
J8
RFU
DQ0
VCC
RFU
DQ12
DQ7
VSS
K2
K8
K3
K5
K7
K6
RFU
L6
K9
DQ14
DQ8
DQ2
DQ5
RFU
DQ11
RFU
L2
L3
L4
L5
L7
L8
L9
RFU
RFU
RFU
VCC
RFU
RFU
RFU
RFU
M10
NC
M1
NC
Notes:
1. Top view—balls facing down.
2. Recommended for wireless applications
Figure 4.1 Connection Diagram – 84-ball Fine-Pitch Ball Grid Array (S29PL256N)
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
9
P r e l i m i n a r y
4.2.2 Physical Dimensions – VBH084, 8.0 x 11.6 mm
0.05
(2X)
C
D1
D
A
e
10
9
8
7
6
5
4
3
2
1
e
7
SE
E1
E
M
L
K
J
H
G
F
E
D
C
B
A
A1 CORNER
A1 CORNER
INDEX MARK
B
SD
7
6
0.05
(2X)
C
10
NXφb
φ 0.08
φ 0.15
M
M
C
C
TOP VIEW
A
B
BOTTOM VIEW
0.10
C
A2
A
0.08
C
C
A1
SEATING PLANE
SIDE VIEW
NOTES:
PACKAGE
JEDEC
VBH 084
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
11.60 mm x 8.00 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
---
NOM
---
MAX
1.00
---
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
OVERALL THICKNESS
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.18
0.62
---
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
---
0.76
BODY THICKNESS
BODY SIZE
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
MD
ME
N
BALL FOOTPRINT
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
10
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
84
φb
0.33
---
0.43
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
e
0.80 BSC.
0.40 BSC.
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. NOT USED.
(A2-A9, B10-L10,
M2-M9, B1-L1)
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3339 \ 16-038.25b
Note: Recommended for wireless applications
Figure 4.2 Physical Dimensions – 84-ball Fine-Pitch Ball Grid Array (S29PL256N)
10
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
4.3 VBH064, 8 x 11.6 mm
4.3.1 Connection Diagram – S29PL127N MCP Compatible Package
A10
A1
NC
NC
Legend
B5
B7
RFU
RFU
Reserved for
Future Use
C4
C3
A7
C5
C6
C7
A8
C8
RFU
WP/ACC
WE#
A11
D4
D2
A3
D3
A6
D5
D7
D8
D9
D6
No Connection
RFU
RST#
RFU
A19
A12
A15
E2
A2
E3
A5
E4
E5
E6
E7
A9
E8
E9
A18
RY/BY#
A20
A13
A21
F2
A1
F3
A4
F4
F7
F8
F9
A17
A10
A14
A22
G2
A0
G3
G4
G7
G8
G9
VSS
DQ1
DQ6
RFU
A16
H4
H5
H6
H7
H8
H2
H2
H3
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
CE1#
OE#
J4
J6
J7
J8
J9
J2
J3
J5
DQ12
VSS
RFU
DQ0
DQ10
VCC
RFU
DQ7
K3
K4
K5
K6
K7
K8
DQ2
DQ11
RFU
DQ5
DQ14
DQ8
L5
L6
RFU
RFU
M1
M10
NC
NC
Notes:
1. Top view—balls facing down.
2. Recommended for wireless applications
Figure 4.3 Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL127N)
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
11
P r e l i m i n a r y
4.3.2 Connection Diagram – S29PL129N MCP Compatible Package
A10
A1
NC
NC
Legend
B5
B7
RFU
RFU
Reserved for
Future Use
C4
C3
A7
C5
C6
C7
A8
C8
RFU
WP/ACC
WE#
A11
D4
D2
A3
D3
A6
D5
D7
D8
D9
D6
No Connection
RFU
RST#
RFU
A19
A12
A15
E2
A2
E3
A5
E4
E5
E6
E7
A9
E8
E9
A18
RY/BY#
A20
A13
A21
F2
A1
F3
A4
F4
F7
F8
F9
A17
A10
A14
CE2#
G2
A0
G3
G4
G7
G8
G9
VSS
DQ1
DQ6
RFU
A16
H4
H5
H6
H7
H8
H2
H2
H3
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
CE1#
OE#
J4
J6
J7
J8
J9
J2
J3
J5
DQ12
VSS
RFU
DQ0
DQ10
VCC
RFU
DQ7
K3
K4
K5
K6
K7
K8
DQ2
DQ11
RFU
DQ5
DQ14
DQ8
L5
L6
RFU
RFU
M1
M10
NC
NC
Notes:
1. Top view—balls facing down.
2. Recommended for wireless applications
Figure 4.4 Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL129N)
12
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
4.3.3 Physical Dimensions – VBH064, 8 x 11.6 mm – S29PL-N
0.05
(2X)
C
D1
D
A
e
10
9
e
7
8
SE
7
6
E1
E
5
4
3
2
1
M
L
K
J
H
G
F
E
D
C
B
A
A1 CORNER
A1 CORNER
INDEX MARK
B
SD
7
6
0.05
(2X)
C
10
NXφb
φ 0.08
φ 0.15
M
M
C
C
TOP VIEW
A
B
BOTTOM VIEW
0.10
C
A2
A
0.08
C
C
A1
SEATING PLANE
SIDE VIEW
NOTES:
PACKAGE
JEDEC
VBH 064
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
11.60 mm x 8.00 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
---
NOM
---
MAX
1.00
---
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
OVERALL THICKNESS
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.18
0.62
---
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
---
0.76
BODY THICKNESS
BODY SIZE
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
MD
ME
N
BALL FOOTPRINT
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
10
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
64
φb
0.33
---
0.43
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
e
0.80 BSC.
0.40 BSC.
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. NOT USED.
(A2-9,B1-4,B7-10,C1-K1,
M2-9,C10-K10,L1-4,L7-10,
G5-6,F5-6)
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3330 \ 16-038.25b
Note: Recommended for wireless applications
Figure 4.5 Physical Dimensions – 64-Ball Fine-Pitch Ball Grid Array (S29PL-N)
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
13
P r e l i m i n a r y
4.3.4 Connection Diagram – S29PL-N Fortified Ball Grid Array Package
A8
NC
B8
C8
D8
E8
F8
G8
NC
H8
NC
A22
A23
VCC
VSS
NC
A7
B7
C7
D7
E7
F7
G7
H7
VSS
A13
A12
A14
A15
A16
RFU
DQ15
A6
A9
B6
A8
C6
D6
E6
F6
G6
H6
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
V
CC
WE#
RESET#
A21
A19
DQ5
DQ12
DQ4
A4
B4
C4
D4
E4
F4
G4
H4
RY/BY# WP#/ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
A3
A7
B3
C3
A6
D3
A5
E3
F3
G3
H3
A17
DQ0
DQ8
DQ9
DQ1
A2
A3
B2
A4
C2
A2
D2
A1
E2
A0
F2
G2
H2
VSS
CE#
OE#
A1
NC
B1
NC
C1
NC
D1
NC
E1
F1
G1
NC
H1
NC
NC
RFU
Notes:
1. Top view—balls facing down.
2. A23 is NC on PL127N.
Figure 4.6 Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL127N, S29PL256N)
14
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
4.3.5 Physical Dimensions – LAA064, 11 x 13 mm – S29PL-N
Note: Recommended for automotive applications
Figure 4.7 Physical Dimensions – 64-Ball Fortified Ball Grid Array (S29PL-N)
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
15
P r e l i m i n a r y
4.4 MCP Look-Ahead Connection Diagram/Physical Dimensions
4.4.1 For All Page Mode MCPs Comprised of Code Flash + (p)SRAM + Data Flash
A2
NC
A10
NC
A9
NC
A1
NC
Legend:
X
B1
NC
B9
NC
B2
NC
B10
NC
RFU
(Reserved for
Future Use)
C2
C3
C4
C5
C6
C7
C8
C9
X
F-VCC or
RFU
VSS
RFU
F2-CE#
N-PRE N-ALE# N-CLE
(N-VCC
)
Code Flash Only
D5
D2
D3
D4
D6
D7
D8
D9
RFU
A7
R-LB# WP#/ACC WE#
A8
A11
N1-CE#
X
MirrorBit Data
Only
E2
E3
E5
E7
E8
E9
E4
E6
A3
A6
R-UB# F-RST# R1-CE2
A19
A12
A15
X
F2
F3
F4
F6
F7
F8
F9
F5
Flash/Data
Shared
A2
A5
A18 F-RY/BY# A20
A9
A13
A21
G2
G3
G4
G5
G6
G7
G9
G8
X
R2-CE1# or
(N-WE#)
A1
A4
A17
A10
A22
A23
A14
Flash/xRAM
Shared
H2
H3
H4
H5
H6
H7
H8
H9
X
R2-VCC R2-CE2 or
(or N-VCC) (N-RE#)
A0
VSS
DQ1
DQ6
A24
A16
pSRAM Only
J2
J3
J4
J5
J6
J7
J8
J9
X
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
xRAM Shared
K4
K5
K2
K3
K6
K7
K8
K9
X
R1-CE1# DQ0
DQ10
F-VCC
R1-VCC
DQ12
DQ7
VSS
NAND or pSRAM
L2
L3
L4
L5
L6
L7
L8
L9
X
R1-VCC
DQ8
DQ2
DQ11
A25
DQ5
DQ14 N-WP#
NAND
M2
M3
M4
M7
M9
M5
M6
M8
A27
A26
VSS
F-VCC N2-CE# R-VCCQ
F-VIO
RFU
N1
NC
N2
NC
N10
NC
N9
NC
P1
P2
P10
NC
P9
NC
NC
NC
Notes:
1. F1 and F2 denote XIP/Code Flash, while F3 and F4 denote Data/Companion Flash.
2. In addition to being defined as F2-CE#, Ball C5 can also be assigned as F1-CE2# for code flash that has two chip enable
signals.
3. F-VIO is RFU on the PL-N product family.
Figure 4.8 MCP Look-Ahead Diagram
16
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
To provide customers with a migration path to higher densities, as well as the option to stack
more die in a package, Spansion has prepared a standard pinout that supports:
NOR Flash and SRAM densities up to 4 Gb
NOR Flash and PSRAM densities up to 4 Gb
NOR Flash and PSRAM and Data Storage densities up to 4 Gb
The signal locations of the resultant MCP device are shown above. Note that for different densi-
ties, the actual package outline can vary. However, any pinout in any MCP is a subset of the pinout
shown above.
In some cases, there may be outrigger balls in locations outside the grid shown above. In such
cases, the user is advised to treat these as RFUs, and not connect them to any other signal.
In case of any further inquiries about the above look-ahead pinout, please see the application
note, Design-in Scalable Wireless Solutions with Spansion Products, or contact a Spansion sales
office.
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
17
P r e l i m i n a r y
5 Additional Resources
Visit www.amd.com and www.fujitsu.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices
Simultaneous Read/Write vs. Erase Suspend/Resume
MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read
Design-In Scalable Wireless Solutions with Spansion Products
Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
Spansion Low-Level Drivers
Enhanced Flash Drivers
Flash File System
CAD Modeling Support
VHDL and Verilog
IBIS
ORCAD
Technical Support
Contact your local sales office or contact Spansion LLC directly for additional technical support:
Email
US and Canada: HW.support@amd.com
Asia Pacific: asia.support@amd.com
Europe, Middle East, and Africa
Japan: http://edevice.fujitsu.com/jp/support/tech/#b7
Frequently Asked Questions (FAQ)
http://ask.amd.com/
http://edevice.fujitsu.com/jp/support/tech/#b7
Phone
US: (408) 749-5703
Japan (03) 5322-3324
Spansion LLC Locations
915 DeGuigne Drive, P.O. Box 3453
Sunnyvale, CA 94088-3453, USA
Telephone: 408-962-2500 or
1-866-SPANSION
Spansion Japan Limited
4-33-4 Nishi Shinjuku, Shinjuku-ku
Tokyo, 160-0023
Telephone: +81-3-5302-2200
Facsimile: +81-3-5302-2674
http://www.spansion.com
18
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
6 Product Overview
The S29PLxxxN family consists of 256 and 128 Mb, 3.0 volts-only, simultaneous read/write
page-mode read Flash devices that are optimized for wireless designs of today that demand large
storage array and rich functionality, while requiring low power consumption. These products also
offer 32-word buffer for programming with program and erase suspend/resume functionality. Ad-
ditional features include:
Advanced Sector Protection methods for protecting an individual or group of sectors as re-
quired,
256-word of secured silicon area for storing customer and factory secured information
Simultaneous Read/Write operation
6.1
Memory Map
The S29PL-N devices consist of 4 banks organized as shown in Tables 6.1, 6.2, and 6.3.
Table 6.1 PL256N Sector and Memory Address Map
Bank
Size
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank
Address Range
Notes
64
64
SA00
SA01
SA02
SA03
SA04
000000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-03FFFFh
Sector Starting Address –
Sector Ending Address
4
64
A
4 MB
64
256
Sector Starting Address -
Sector Ending Address
(see note)
15
48
48
15
256
256
SA018
SA19
1E0000h-1FFFFFh
200000h-21FFFFh
First Sector, Sector Starting Address -
Last Sector, Sector Ending Address
(see note)
B
C
12 MB
12 MB
256
256
SA66
SA67
7E0000h-7FFFFFh
800000h-81FFFFh
First Sector, Sector Starting Address -
Last Sector, Sector Ending Address
(see note)
256
256
SA114
SA115
DE0000h-DFFFFFh
E00000h-E1FFFFh
Sector Starting Address -
Sector Ending Address
(see note)
256
64
64
SA129
SA130
SA131
SA132
SA133
FC0000h-FDFFFFh
FE0000h-FE7FFFh
FE8000h-FEFFFFh
FF0000h-FF7FFFh
FF8000h-FFFFFFh
D
4 MB
Sector Starting Address -
Sector Ending Address
4
64
64
Note: Ellipses indicate that other addresses in sector range follow the same pattern.
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
19
P r e l i m i n a r y
Table 6.2 PL127N Sector and Memory Address Map
Bank Sector
Sector Size
(KB)
Sector/
Sector Range
Bank
Address Range
Notes
Size
Count
64
64
SA00
SA01
SA02
SA03
SA04
000000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-03FFFFh
Sector Starting Address -
Sector Ending Address
4
64
A
2 MB
64
256
Sector Starting Address –
Sector Ending Address
(see note)
7
24
24
7
256
256
SA10
SA11
0E0000h-0FFFFFh
100000h-11FFFFh
First Sector, Sector Starting Address -
Last Sector, Sector Ending Address
(see note)
B
C
6 MB
6 MB
256
256
SA34
SA35
3E0000h-3FFFFFh
400000h-41FFFFh
First Sector, Sector Starting Address -
Last Sector, Sector Ending Address
(see note)
256
256
SA58
SA59
6E0000h-6FFFFFh
700000h-71FFFFh
Sector Starting Address -
Sector Ending Address
(see note)
256
64
SA65
SA66
SA67
SA68
SA69
7C0000h-7DFFFFh
7E0000h-7E7FFFh
7E80000h-7EFFFFh
7F0000h-7F7FFFh
7F8000h-7FFFFFh
D
2 MB
64
Sector Starting Address -
Sector Ending Address
4
64
64
Note: Ellipses indicate that other addresses in sector range follow the same pattern.
Table 6.3 PL129N Sector and Memory Address Map
Sector/
CE1# CE2# Sector
Range
Bank Sector Sector Size
Bank
Address Range
Notes
Size Count
(KB)
64
64
SA00
SA01
SA02
SA03
SA04
000000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-03FFFFh
Sector Starting Address -
Sector Ending Address
4
64
1A
2 MB
64
256
Sector Starting Address –
Sector Ending Address
(see note)
VIL
VIH
7
256
256
SA10
SA11
0E0000h-0FFFFFh
100000h-11FFFFh
First Sector, Sector Starting Address -
Last Sector, Sector Ending Address
(see note)
1B
2A
6 MB
6 MB
24
24
7
256
256
SA34
SA35
3E0000h-3FFFFFh
000000h-01FFFFh
First Sector, Sector Starting Address -
Last Sector, Sector Ending Address
(see note)
256
256
SA58
SA59
2E0000h - 2FFFFFh
300000h-31FFFFh
Sector Starting Address -
Sector Ending Address
(see note)
VIH
VIL
256
64
SA65
SA66
SA67
SA68
SA69
3C0000h-3DFFFFh
3E0000h-3E7FFFH
3E8000h-3EFFFFh
3F0000h-3F7FFFh
3F8000h-3FFFFFh
2B
2 MB
64
Sector Starting Address -
Sector Ending Address
4
64
64
20
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
7 Device Operations
This section describes the read, program, erase, simultaneous read/write operations, and reset
features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and
data patterns into the command registers (see Table 12.1 and Table 12.2). The command regis-
ter itself does not occupy any addressable memory location. Instead, the command register is
composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as input to the internal state
machine and the state machine outputs dictate the function of the device. Writing incorrect ad-
dress and data values or writing them in an improper sequence can place the device in an
unknown state, in which case the system must write the reset command to return the device to
the reading array data mode.
7.1
Device Operation Table
The device must be setup appropriately for each operation. Table 7.1 describes the required state
of each control pin for any particular operation.
Table 7.1 Device Operation
Addresses
Operation
Read
CE#
OE#
WE#
RESET#
WP#/ACC
(Amax – A0)
DQ15 – DQ0
L
L
H
H
X
A
D
OUT
IN
IN
X
Write
L
H
L
H
A
D
IN
(See Note)
Standby
H
L
X
H
X
X
H
X
H
H
L
X
X
X
A
A
A
High-Z
High-Z
High-Z
IN
IN
IN
Output Disable
Reset
X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VHH = 8.5 – 9.5 V, X = Don’t Care, SA = Sector Address, AIN = Address
In, DIN = Data In, DOUT = Data Out
Note: WP#/ACC must be high when writing to upper two and lower two sectors (PL256N: 0, 1,132, and 133; PL127/129N:
0, 1, 68, and 69)
7.1.1 Dual Chip Enable Device Description and Operation (PL129N Only)
The dual CE# product (PL129N) offers a reduced number of address pins to accommodate pro-
cessors with a limited addressable range. This product operates as two separate devices in a
single package and requires the processor to address half of the memory space with one chip en-
able and the remaining memory space with a second chip enable. For more details on the
addressing features of the Dual CE# device refer to Table 6.3 on page 20 for the PL129N Sector
and Memory Address Map.
Dual chip enable products must be setup appropriately for each operation. To place the device
into the active state either CE1# or CE2# must be set to V . To place the device in standby mode,
IL
both CE1# and CE2# must be set to V . Table 7.2 describes the required state of each control
IH
pin for any particular operation.
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
21
P r e l i m i n a r y
Table 7.2 Dual Chip Enable Device Operation
Addresses
CE1# CE2# OE# WE# RESET# WP#/ACC (A21 – A0) DQ15 – DQ0
Operation
L
H
L
H
L
AIN
DOUT
Read
L
H
L
H
H
X
H
L
X
AIN
DIN
Write
H
(Note 2)
H
H
L
Standby
H
L
X
H
X
X
H
X
H
H
L
X
X
X
X
X
X
High-Z
High-Z
High-Z
Output Disable
Reset
X
X
Temporary Sector Unprotect
(High Voltage)
AIN
DIN
X
X
X
X
V
X
ID
Legend: L = Logic Low = VIL, H = Logic High = VIH,VID = 11.5–12.5 V, VHH = 8.5 – 9.5 V,
X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. The sector and sector unprotect functions may also be implemented by programming equipment.
2. WP#/ACC must be high when writing to the upper two and lower two sectors.
7.2 Asynchronous Read
The internal state machine is set for reading array data upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the memory content occurs during the power
transition. No command is necessary in this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. Each bank remains enabled for read access until the command register con-
tents are altered.
7.2.1 Non-Page Random Read
Address access time (t
) is equal to the delay from stable addresses to valid output data. The
ACC
chip enable access time (t ) is the delay from the stable addresses and stable CE# to valid data
CE
at the output inputs. The output enable access time is the delay from the falling edge of the OE#
to valid data at the output (assuming the addresses have been stable for at least t
– t time).
OE
ACC
7.2.2 Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM
read operation. This mode provides faster read access speed for random locations within a page.
The random or initial page access is t
or t and subsequent page read accesses (as long as
CE
ACC
the locations specified by the microprocessor falls within that page) is equivalent to t
. When
PACC
CE# is deasserted (= V ), the reassertion of CE# for subsequent access has access time of t
IH
ACC
or t . Here again, CE# selects the device and OE# is the output control and should be used to
CE
gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by
keeping A
– A3 constant and changing A2 – A0 to select the specific word within that page.
max
Address bits A
– A3 select an 8-word page, and address bits A2 – A0 select a specific word
max
within that page. This is an asynchronous operation with the microprocessor supplying the specific
word location. See Table 7.3 for details on selecting specific words.
22
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
The device is automatically set to reading array data after device power-up. No commands are
required to retrieve data. Each bank is ready to read array data after completing an Embedded
Program or Embedded Erase algorithm. All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever
happens first.
Reads from the memory array may be performed in conjunction with the Erase Suspend and Pro-
gram Suspend features. After the device accepts an Erase Suspend command, the corresponding
bank enters the erase-suspend-read mode, after which the system can read data from any non-
erase-suspended sector within the same bank. The system can read array data using the standard
read timing, except that if it reads at an address within erase-suspended sectors, the device out-
puts status data. After completing a programming operation in the Erase Suspend mode, the
system may once again read array data with the same exception. After the device accepts a Pro-
gram Suspend command, the corresponding bank enters the program-suspend-read mode, after
which the system can read data from any non-program-suspended sector within the same bank.
Table 7.3 Word Selection within a Page
Word
A2
0
A1
0
0
1
1
0
0
1
1
A0
0
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
0
1
0
0
0
1
1
0
1
1
1
0
1
1
7.3
Autoselect
The Autoselect mode allows the host system to access manufacturer and device identification,
and verify sector protection, through identifier codes output from the internal register (separate
from the memory array) on DQ15-DQ0. This mode is primarily intended to allow equipment to
automatically match a device to be programmed with its corresponding programming algorithm.
When verifying sector protection, the sector address must appear on the appropriate highest
order address bits (see Table 7.5). The remaining address bits are don't care. When all necessary
bits have been set as required, the programming equipment can then read the corresponding
identifier code on DQ15-DQ0.
The Autoselect codes can also be accessed in-system through the command register. Note that if
a Bank Address (BA) on the four uppermost address bits is asserted during the third write cycle
of the Autoselect command, the host system can read Autoselect data from that bank and then
immediately read array data from the other bank, without exiting the Autoselect mode.
To access the Autoselect codes, the host system must issue the Autoselect command.
The Autoselect command sequence can be written to an address within a bank that is either
in the read or erase-suspend-read mode.
The Autoselect command cannot be written while the device is actively programming or eras-
ing in the other bank.
Autoselect does not support simultaneous operations or page modes.
The system must write the reset command to return to the read mode (or erase-suspend-
read mode if the bank was previously in Erase Suspend).
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
23
P r e l i m i n a r y
See Table 12.1 for command sequence details.
Table 7.4 Autoselect Codes
CE#
See Note
Amax
A12
–
A5 –
A4
Description
OE# WE#
A10 A9 A8 A7 A6
A3 A2 A1 A0
DQ15 to DQ0
Manufacturer ID
L
L
L
H
BA
X
X
X
L
L
X
L
L
L
L
L
L
L
0001h
227Eh
Read
Cycle 1
H
223Ch (PL256N)
2220h (PL127N)
2221h (PL129N)
Read
L
L
H
H
H
H
H
H
L
Cycle 2
L
H
BA
X
X
X
L
L
L
2200h (PL256N)
2200h (PL127N)
2200h (PL129N)
Read
Cycle 3
H
0000h
Unprotected
(Neither DYB nor PPB Locked),
0001h
Protected
(Either DYB or PPB Locked)
Sector
Protection
L
L
H
SA
X
X
X
L
L
L
L
L
H
L
Verification
- DQ15 - DQ8 = 0
- DQ7 - Factory Lock Bit
1 = Locked, 0 = Not Locked
- DQ6 -Customer Lock Bit
1 = Locked, 0 = Not Locked
- DQ5 - Handshake Bit
1 = Reserved,
Indicator Bit
L
L
H
BA
X
X
X
L
L
L
L
L
H
H
0 = Standard Handshake
- DQ4 & DQ3 -
WP# Protection Boot Code
00 = WP# Protects both Top Boot
and Bottom Boot Sectors,
11 = No WP# Protection
- DQ2 - DQ0 = 0
Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.
Note: For the PL129N Either CE1# or CE2# must be low to access Autoselect Codes
Software Functions and Sample Code
Table 7.5 Autoselect Entry
(LLD Function = lld_AutoselectEntryCmd)
Cycle
Operation
Write
Word Address
BAx555h
Data
Unlock Cycle 1
Unlock Cycle 2
Autoselect Command
0x00AAh
0x0055h
0x0090h
Write
BAx2AAh
Write
BAx555h
Table 7.6 Autoselect Exit
(LLD Function = lld_AutoselectExitCmd)
Cycle
Operation
Word Address
Data
Unlock Cycle 1
Write
base + xxxh
0x00F0h
Notes:
1. Any offset within the device works.
2. BA = Bank Address. The bank address is required.
3. base = base address.
The following is a C source code example of using the autoselect function to read the manufac-
turer ID. See the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
24
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*((UINT16 *)bank_addr + 0x555) = 0x00AA; /* write unlock cycle 1 */
*((UINT16 *)bank_addr + 0x2AA) = 0x0055; /* write unlock cycle 2 */
*((UINT16 *)bank_addr + 0x555) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
manuf_id = *((UINT16 *)bank_addr + 0x000); /* read manuf. id */
/* Autoselect exit */
*((UINT16 *)base_addr + 0x000) = 0x00F0; /* exit autoselect (write reset command) */
November 23, 2005 S29PL-N_00_A4
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7.4 Program/Erase Operations
These devices are capable of single word or write buffer programming operations which are de-
scribed in the following sections. The write buffer programming is recommended over single word
programming as it has clear benefits from greater programming efficiency. See Table 7.1 on
page 21 for the correct device settings required before initiation of a write command sequence.
Note the following details regarding the program/erase operations:
When the Embedded Program algorithm is complete, the device then returns to the read
mode.
The system can determine the status of the program operation by using DQ7 or DQ6. See
Write Operation Status for information on these status bits.
A 0 cannot be programmed back to a 1. Attempting to do so causes the device to set DQ5 =
1 (halting any further operation and requiring a reset command). A succeeding read shows
that the data is still 0.
Only erase operations can convert a 0 to a 1.
A hardware reset immediately terminates the program operation and the program command
sequence should be reinitiated once the device has returned to the read mode, to ensure data
integrity.
Any commands written to the device during the Embedded Program Algorithm are ignored
except the Program Suspend command.
Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program oper-
ation is in progress.
Programming is allowed in any sequence and across sector boundaries for single word pro-
gramming operation.
7.4.1 Single Word Programming
In single word programming mode, four Flash command write cycles are used to program an in-
dividual Flash address. While this method is supported by all Spansion devices, in general it is not
recommended for devices that support Write Buffer Programming. See Table 12.1 for the re-
quired bus cycles and Figure 7.1 for the flowchart.
When the Embedded Program algorithm is complete, the device then returns to the read mode
and addresses are no longer latched. The system can determine the status of the program oper-
ation by using DQ7 or DQ6. See Write Operation Status for information on these status bits.
Single word programming is supported for backward compatibility with existing Flash driver soft-
ware and use of write buffer programming is strongly recommended for general programming.
The effective word programming time using write buffer programming is approximately four times
faster than the single word programming time.
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Program Command:
Address 555h, Data A0h
Setup Command
Program Address (PA),
Program Data (PD)
Program Data to Address:
PA, PD
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Polling Status
= Busy?
No
Yes
Polling Status
= Done?
Error condition
No
(Exceeded Timing Limits)
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
Figure 7.1 Single Word Program Operation
Software Functions and Sample Code
Table 7.7 Single Word Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Write
Word Address
Data
00AAh
Unlock Cycle 1
Unlock Cycle 2
Program Setup
Base + 555h
Base + 2AAh
Base + 555h
Word Address
Write
0055h
Write
00A0h
Program
Write
Data Word
Note: Base = Base Address.
The following is a C source code example of using the single word program function. See the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program Command
*/
*((UINT16 *)base_addr + 0x555) = 0x00AA;
*((UINT16 *)base_addr + 0x2AA) = 0x0055;
*((UINT16 *)base_addr + 0x555) = 0x00A0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write program setup command
/* write data to be programmed
*/
*/
*/
*/
*((UINT16 *)pa)
= data;
/* Poll for program completion */
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7.4.2 Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one program-
ming operation. This results in a faster effective word programming time than the standard word
programming algorithms. The Write Buffer Programming command sequence is initiated by first
writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which programming occurs. At this point, the system
writes the number of word locations minus 1 that is loaded into the page buffer at the Sector Ad-
dress in which programming occurs. This tells the device how many write buffer addresses are
loaded with data and therefore when to expect the Program Buffer to Flash confirm command.
The number of locations to program cannot exceed the size of the write buffer or the operation
aborts. (Number loaded = the number of locations to program minus 1. For example, if the sys-
tem programs 6 address locations, then 05h should be written to the device.)
The system then writes the starting address/data combination. This starting address is the first
address/data pair to be programmed, and selects the write-buffer-page address. All subsequent
address/data pairs must fall within the elected-write-buffer-page.
The write-buffer-page is selected by using the addresses A
– A5.
max
The write-buffer-page addresses must be the same for all address/data pairs loaded into the write
buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer-
page. This also means that Write Buffer Programming cannot be performed across multiple sec-
tors. If the system attempts to load programming data outside of the selected write-buffer-page,
the operation ABORTS.)
After writing the Starting Address/Data pair, the system then writes the remaining address/data
pairs into the write buffer.
Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter
decrements for every data load operation. Also, the last data loaded at a location before the Pro-
gram Buffer to Flash confirm command is programmed into the device. The software takes care
of the ramifications of loading a write-buffer location more than once. The counter decrements
for each data load operation, NOT for each unique write-buffer-address location. Once the speci-
fied number of write buffer locations have been loaded, the system must then write the Program
Buffer to Flash command at the Sector Address. Any other address/data write combinations abort
the Write Buffer Programming operation. The device then goes busy. The Data Bar polling tech-
niques should be used while monitoring the last address location loaded into the write buffer. This
eliminates the need to store an address in memory because the system can load the last address
location, issue the program confirm command at the last loaded address location, and then data
bar poll at that same address.
The write-buffer embedded programming operation can be suspended using the standard sus-
pend/resume commands. Upon successful completion of the Write Buffer Programming operation,
the device returns to READ mode.
If the write buffer command sequence is entered incorrectly the device enters write buffer abort.
When an abort occurs the write-to buffer-abort reset command must be issued to return the de-
vice to read mode.
The Write Buffer Programming Sequence is ABORTED under any of the following conditions:
Load a value that is greater than the page buffer size during the Number of Locations to Pro-
gram step.
Write to an address in a sector different than the one specified during the Write-Buffer-Load
command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the
Starting Address during the write buffer data loading stage of the operation.
Write data other than the Confirm Command after the specified number of data load cycles.
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Use of the write buffer is strongly recommended for programming when multiple words are to be
programmed. Write buffer programming is approximately four times faster than programming
one word at a time. Note that the Secured Silicon, the CFI functions, and the Autoselect Codes
are not available for read when a write buffer programming operation is in progress.
Software Functions and Sample Code
Table 7.8 Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle
Description
Unlock
Operation
Write
Word Address
Base + 555h
Data
00AAh
1
2
3
4
Unlock
Write
Base + 2AAh
0055h
Write Buffer Load Command
Write Word Count
Write
Program Address
Program Address
0025h
Write
Word Count (N–1)h
Number of words (N) loaded into the write buffer can be from 1 to 32 words.
5 to 36
Last
Load Buffer Word N
Write Buffer to Flash
Write
Write
Program Address, Word N
Sector Address
Word N
0029h
Notes:
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles
can be from 6 to 37.
3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words)
possible.
The following is a C source code example of using the write buffer program function. See the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Write Buffer Programming Command
*/
/* NOTES: Write buffer programming limited to 16 words. */
/*
/*
/*
/*
All addresses to be written to the flash in
one operation must be within the same flash
page. A flash page begins at addresses
evenly divisible by 0x20.
*/
*/
*/
*/
UINT16 *src = source_of_data;
UINT16 *dst = destination_of_data;
UINT16 wc = words_to_program -1;
*((UINT16 *)base_addr + 0x555) = 0x00AA;
*((UINT16 *)base_addr + 0x2AA) = 0x0055;
/* address of source data
/* flash destination address
/* word count (minus 1)
/* write unlock cycle 1
/* write unlock cycle 2
*/
*/
*/
*/
*/
*((UINT16 *)sector_address)
*((UINT16 *)sector_address)
loop:
= 0x0025;
= wc;
/* write write buffer load command */
/* write word count (minus 1) */
*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */
dst++;
src++;
/* increment destination pointer
/* increment source pointer
*/
*/
if (wc == 0) goto confirm
/* done when word count equals zero */
wc--;
goto loop;
/* decrement word count
/* do it again
*/
*/
confirm:
*((UINT16 *)sector_address)
/* poll for completion */
= 0x0029;
/* write confirm command
*/
/* Example: Write Buffer Abort Reset */
*((UINT16 *)addr + 0x555) = 0x00AA;
*((UINT16 *)addr + 0x2AA) = 0x0055;
*((UINT16 *)addr + 0x555) = 0x00F0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write buffer abort reset
*/
*/
*/
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Issue
Write Buffer Load Command:
Address 555h, Data 25h
Load Word Count to Program
Program Data to Address:
SA = wc
wc = number of words – 1
Yes
Confirm command:
wc = 0?
No
SA 29h
Wait 4 µs
Write Next Word,
Decrement wc:
PA data , wc = wc – 1
No
Write Buffer
Abort Desired?
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Write to a Different
Sector Address to Cause
Write Buffer Abort
Yes
Polling Status
= Done?
No
Error?
Yes
No
Yes
Write Buffer
Abort?
No
RESET. Issue Write Buffer
Abort Reset Command
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
Figure 7.2 Write Buffer Programming Operation
7.4.3 Sector Erase
The sector erase function erases one or more sectors in the memory array. (See Table 12.1, and
Figure 7.3.) The device does not require the system to preprogram prior to erase. The Embedded
Erase algorithm automatically programs and verifies the entire memory for an all zero data pat-
tern prior to electrical erase. The system is not required to provide any controls or timings during
these operations.
After the command sequence is written, a sector erase time-out of no less than t
occurs. Dur-
SEA
ing the time-out period, additional sector addresses and sector erase commands can be written.
Loading the sector erase buffer can be done in any sequence, and the number of sectors can be
from one sector to all sectors. The time between these additional cycles must be less than t
.
SEA
Any sector erase address and command following the exceeded time-out (t
) may or may not
SEA
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be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period
resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase
timer has timed out (see DQ3: Sector Erase Timeout State Indicator). The time-out begins from
the rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and ad-
dresses are no longer latched. Note that while the Embedded Erase operation is in progress, the
system can read data from the non-erasing banks. The system can determine the status of the
erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. See Write Operation Status for
information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. However, note that a hardware reset immediately terminates the erase
operation. If that occurs, the sector erase command sequence should be reinitiated once that
bank has returned to reading array data, to ensure data integrity.
Figure 7.3 illustrates the algorithm for the erase operation. See AC Characteristics for the Erase/
Program Operations parameters and timing diagrams.
Software Functions and Sample Code
Table 7.9 Sector Erase
(LLD Function = lld_SectorEraseCmd)
Cycle
Description
Unlock
Operation
Write
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Sector Address
Data
1
2
3
4
5
6
00AAh
0055h
0080h
00AAh
0055h
0030h
Unlock
Write
Setup Command
Unlock
Write
Write
Unlock
Write
Sector Erase Command
Write
Unlimited additional sectors can be selected for erase; command(s) must be written within t
.
SEA
The following is a C source code example of using the sector erase function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Sector Erase Command */
*((UINT16 *)base_addr + 0x555) = 0x00AA;
*((UINT16 *)base_addr + 0x2AA) = 0x0055;
*((UINT16 *)base_addr + 0x555) = 0x0080;
*((UINT16 *)base_addr + 0x555) = 0x00AA;
*((UINT16 *)base_addr + 0x2AA) = 0x0055;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
*((UINT16 *)sector_address)
= 0x0030;
/* write sector erase command
*/
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Write Unlock Cycles:
Unlock Cycle 1
Unlock Cycle 2
Address 555h, Data AAh
Address 2AAh, Data 55h
Write Sector Erase Cycles:
Command Cycle 1
Address 555h, Data 80h
Command Cycle 2
Address 555h, Data AAh
Command Cycle 3
Specify first sector for erasure
Address 2AAh, Data 55h
Sector Address, Data 30h
Select
Additional
No
Sectors?
Yes
Write Additional
Sector Addresses
• Each additional cycle must be written within t
timeout
SEA
• Timeout resets after each additional cycle is written
• The host system may monitor DQ3 or wait t to ensure
SEA
acceptance of erase commands
Yes
Last Sector
Selected?
No
N
• No limit on number of sectors
Poll DQ3.
DQ3 = 1?
• Commands other than Erase Suspend or selecting
additional sectors for erasure during timeout reset device
to reading array data
No
Yes
Wait 4 µs
Perform Write Operation
Status Algorithm
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
Yes
Done?
No
No
DQ5 = 1?
Error condition (Exceeded Timing Limits)
Yes
PASS. Device returns
FAIL. Write reset command
to reading array.
to return to reading array.
Notes:
1. See Table 12.1 for erase command sequence.
2. See the section on DQ3 for information on the sector erase timeout.
Figure 7.3 Sector Erase Operation
7.4.4 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 12.1. These commands invoke the
Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all
zero data pattern prior to electrical erase. The system is not required to provide any controls or
timings during these operations. The Command Definition tables (Table 12.1 and Table 12.2)
show the address and data requirements for the chip erase command sequence.
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When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7 or DQ6/DQ2. See Write Operation Status for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.
Software Functions and Sample Code
Table 7.10 Chip Erase
(LLD Function = lld_ChipEraseCmd)
Cycle
Description
Unlock
Operation
Write
Word Address
Base + 555h
Base + 2AAh
Data
1
2
00AAh
0055h
Unlock
Write
Setup
Command
3
Write
Base + 555h
0080h
4
5
Unlock
Unlock
Write
Write
Base + 555h
Base + 2AAh
00AAh
0055h
Chip Erase
Command
6
Write
Base + 555h
0010h
The following is a C source code example of using the chip erase function. Refer to the Span-
sion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for
general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
*((UINT16 *)base_addr + 0x555) = 0x00AA;
*((UINT16 *)base_addr + 0x2AA) = 0x0055;
*((UINT16 *)base_addr + 0x555) = 0x0080;
*((UINT16 *)base_addr + 0x555) = 0x00AA;
*((UINT16 *)base_addr + 0x2AA) = 0x0055;
*((UINT16 *)base_addr + 0x000) = 0x0010;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
/* write chip erase command
*/
7.4.5 Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then
read data from, or program data to, any sector not selected for erasure. The bank address is re-
quired when writing this command. This command is valid only during the sector erase operation,
including the minimum t
time-out period during the sector erase command sequence. The
SEA
Erase Suspend command is ignored if written during the chip erase operation.
When the Erase Suspend command is written during the sector erase operation, the device re-
quires a maximum of t
(erase suspend latency) to suspend the erase operation. However,
ESL
when the Erase Suspend command is written during the sector erase time-out, the device imme-
diately terminates the time-out period and suspends the erase operation.
After the erase operation has been suspended, the bank enters the erase-suspend-read mode.
The system can read data from or program data to any sector not selected for erasure. (The de-
vice erase suspends all sectors selected for erasure.) Reading at any address within erase-
suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6,
and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to
Table 7.18 for information on these status bits.
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After an erase-suspended program operation is complete, the bank returns to the erase-suspend-
read mode. The system can determine the status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
In the erase-suspend-read mode, the system can also issue the Autoselect command sequence.
See Write Buffer Programming and Autoselect for details.
To resume the sector erase operation, the system must write the Erase Resume command. The
bank address of the erase-suspended bank is required when writing this command. Further writes
of the Resume command are ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Software Functions and Sample Code
Table 7.11 Erase Suspend
(LLD Function = lld_EraseSuspendCmd)
Cycle
Operation
Word Address
Data
1
Write
Bank Address
00B0h
The following is a C source code example of using the erase suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase suspend command */
*((UINT16 *)bank_addr + 0x000) = 0x00B0;
/* write suspend command
*/
Table 7.12 Erase Resume
(LLD Function = lld_EraseResumeCmd)
Word Address
Cycle
Operation
Data
1
Write
Bank Address
0030h
The following is a C source code example of using the erase resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase resume command */
*((UINT16 *)bank_addr + 0x000) = 0x0030;
/* write resume command
*/
/* The flash needs adequate time in the resume state */
7.4.6 Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming op-
eration or a Write to Buffer programming operation so that data can read from any non-
suspended sector. When the Program Suspend command is written during a programming pro-
cess, the device halts the programming operation within t
updates the status bits.
(program suspend latency) and
PSL
After the programming operation has been suspended, the system can read array data from any
non-suspended sector. The Program Suspend command can also be issued during a programming
operation while an erase is suspended. In this case, data can be read from any addresses not in
Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area,
then user must use the proper command sequences to enter and exit this region.
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The system can also write the Autoselect command sequence when the device is in Program Sus-
pend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes
are not stored in the memory array. When the device exits the Autoselect mode, the device re-
verts to Program Suspend mode, and is ready for another valid operation. See Autoselect for
more information.
After the Program Resume command is written, the device reverts to programming. The system
can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard program operation. See Write Operation Status for more information.
The system must write the Program Resume command (address bits are don't cares) to exit the
Program Suspend mode and continue the programming operation. Further writes of the Program
Resume command are ignored. Another Program Suspend command can be written after the de-
vice has resumed programming.
Software Functions and Sample Code
Table 7.13 Program Suspend
(LLD Function = lld_ProgramSuspendCmd)
Cycle
Operation
Word Address
Data
1
Write
Bank Address
00B0h
The following is a C source code example of using the program suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program suspend command */
*((UINT16 *)base_addr + 0x000) = 0x00B0;
/* write suspend command
*/
Table 7.14 Program Resume
(LLD Function = lld_ProgramResumeCmd)
Cycle
Operation
Write
Word Address
Data
1
Bank Address
0030h
The following is a C source code example of using the program resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program resume command */
*((UINT16 *)base_addr + 0x000) = 0x0030;
/* write resume command
*/
7.4.7 Accelerated Program
Accelerated single word programming, write buffer programming, sector erase, and chip erase
operations are enabled through the ACC function. This method is faster than the standard chip
program and erase command sequences.
The accelerated chip program and erase functions must not be used more than 10
times per sector. In addition, accelerated chip program and erase should be performed at room
temperature (25°C ±10°C).
This function is primarily intended to allow faster manufacturing throughput at the factory. If the
system asserts V on this input, the device automatically enters the aforementioned Unlock By-
HH
pass mode and uses the higher voltage on the input to reduce the time required for program and
erase operations. The system can then use the Write Buffer Load command sequence provided
by the Unlock Bypass mode. Note that if a Write-to-Buffer-Abort Reset is required while in Unlock
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Bypass mode, the full 3-cycle RESET command sequence must be used to reset the device. Re-
moving V
from the ACC input, upon completion of the embedded program or erase operation,
HH
returns the device to normal operation.
Sectors must be unlocked prior to raising WP#/ACC to V
.
HH
The WP#/ACC must not be at V
for operations other than accelerated programming and
HH
accelerated chip erase, or device damage can result.
Set the ACC pin at V when accelerated programming not in use.
CC
7.4.8 Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster word programming. Once the de-
vice enters the Unlock Bypass mode, only two write cycles are required to program data, instead
of the normal four cycles.
This mode dispenses with the initial two unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table 12.1, Memory Array Commands
shows the requirements for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the bank address and the data 90h.
The second cycle need only contain the data 00h. The bank then returns to the read mode.
Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit
functions. Refer to the Spansion Low Level Driver User’s Guide (available soon on www.amd.com
and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
Table 7.15 Unlock Bypass Entry
(LLD Function = lld_UnlockBypassEntryCmd)
Cycle
Description
Unlock
Operation
Write
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
1
2
3
00AAh
0055h
0020h
Unlock
Write
Entry Command
Write
/* Example: Unlock Bypass Entry Command
*((UINT16 *)bank_addr + 0x555) = 0x00AA;
*((UINT16 *)bank_addr + 0x2AA) = 0x0055;
*((UINT16 *)bank_addr + 0x555) = 0x0020;
*/
/* write unlock cycle 1
/* write unlock cycle 2
/* write unlock bypass command
*/
*/
*/
/* At this point, programming only takes two write cycles.
/* Once you enter Unlock Bypass Mode, do a series of like
/* operations (programming or sector erase) and then exit
/* Unlock Bypass Mode before beginning a different type of
/* operations.
*/
*/
*/
*/
*/
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Table 7.16 Unlock Bypass Program
(LLD Function = lld_UnlockBypassProgramCmd)
Cycle
Description
Operation
Write
Word Address
Data
00A0h
1
2
Program Setup Command
Program Command
Base +xxxh
Write
Program Address
Program Data
/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode!
*((UINT16 *)bank_addr + 0x555) = 0x00A0;
*/
/* write program setup command
/* write data to be programmed
*/
*/
*((UINT16 *)pa)
= data;
/* Poll until done or error.
*/
/* If done and more to program, */
/* do above two cycles again. */
Table 7.17 Unlock Bypass Reset
(LLD Function = lld_UnlockBypassResetCmd)
Cycle
Description
Reset Cycle 1
Reset Cycle 2
Operation
Write
Word Address
Base +xxxh
Base +xxxh
Data
1
2
0090h
0000h
Write
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
7.4.9 Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The
following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an Em-
bedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command se-
quence. Note that the Data# Polling is valid only for the last word being programmed in the write-
buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other
than the last word to be programmed in the write-buffer-page returns false status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# polling on DQ7 is active for approxi-
mately t , then that bank returns to the read mode.
PSP
During the Embedded Erase Algorithm, Data# polling produces a 0 on DQ7. When the Embedded
Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling pro-
duces a 1 on DQ7. The system must provide an address within any of the sectors selected for
erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately t , then the bank returns to the read mode.
ASP
If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7
at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 can change asyn-
chronously with DQ6 – DQ0 while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when the system
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samples the DQ7 output, it may read the status or valid data. Even if the device has completed
the program or erase operation and DQ7 has valid data, the data outputs on DQ6 – DQ0 may be
still invalid. Valid data on DQ7 – DQ0 appears on successive read cycles.
See the following for more information: Table 7.18, Write Operation Status, shows the outputs
for Data# Polling on DQ7. Figure 7.4, Write Operation Status Flowchart, shows the Data# Polling
algorithm. Figure 11.13, Data# Polling Timings (During Embedded Algorithms) shows the Data#
Polling timing diagram.
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START
Read 1
(Note 6)
YES
Erase
Operation
Complete
DQ7=valid
data?
NO
YES
YES
Read 2
Read 3
Read 1
DQ5=1?
Read3=
valid data?
NO
NO
Read 2
Read 3
Program
Operation
Failed
YES
Write Buffer
Programming?
YES
NO
Programming
Operation?
NO
Device BUSY,
Re-Poll
(Note 3)
(Note 5)
(Note 1)
YES
(Note 1)
YES
DQ6
toggling?
DQ6
toggling?
DEVICE
ERROR
TIMEOUT
NO
(Note 4)
NO
YES
Read3
DQ1=1?
(Note 2)
YES
NO
Device BUSY,
Re-Poll
DQ2
toggling?
NO
Read 2
Read 3
Device BUSY,
Re-Poll
Erase
Device in
Erase/Suspend
Mode
Operation
Complete
Notes:
1. DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2. DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3. May be due to an attempt to program a 0 to 1. Use the RESET
command to exit operation.
Read3
DQ1=1
AND DQ7 ≠
Valid Data?
YES
Write Buffer
Operation
Failed
4. Write buffer error if DQ1 of last read =1.
5. Invalid state, use RESET command to exit operation.
6. Valid data is the data that is intended to be programmed or all 1's for
an erase operation.
NO
7. Data polling algorithm valid for all operations except advanced sector
protection.
Device BUSY,
Re-Poll
Figure 7.4 Write Operation Status Flowchart
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DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algo-
rithm is in progress or complete, or whether the device has entered the Erase Suspend mode.
Toggle Bit I can be read at any address in the same bank, and is valid after the rising edge of the
final WE# pulse in the command sequence (prior to the program or erase operation), and during
the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately t
(all sectors protected toggle time), then returns to reading array
ASP
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-
gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7, see DQ7: Data# Polling.
If a program address falls within a protected sector, DQ6 toggles for approximately t
program command sequence is written, then returns to reading array data.
after the
PAP
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-
ded Program Algorithm is complete.
See the following for additional information: Figure 7.4, Write Operation Status Flowchart,
Figure 11.14, Toggle Bit Timings (During Embedded Algorithms), Table 7.18, Write Operation
Status, and Figure 11.15, DQ2 vs. DQ6.
Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the
change in state.
DQ2: Toggle Bit II . The Toggle Bit II on DQ2, when used with DQ6, indicates whether a partic-
ular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether
that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse
in the command sequence. DQ2 toggles when the system reads at addresses within those sectors
that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 7.18, Write Opera-
tion Status to compare outputs for DQ2 and DQ6. See the following for additional information:
Figure 7.4, Write Operation Status Flowchart and Figure 11.14, Toggle Bit Timings (During Em-
bedded Algorithms).
Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit status,
it must read DQ7 – DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typ-
ically, the system would note and store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erases operation. The system can
read array data on DQ7 – DQ0 on the following read cycle. However, if after the initial two read
cycles, the system determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then deter-
mine again whether the toggle bit is toggling, since the toggle bit might have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully com-
pleted the program or erases operation. If it is still toggling, the device did not complete the
operation successfully, and the system must write the reset command to return to reading array
data. The remaining scenario is that the system initially determines that the toggle bit is toggling
and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through
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successive read cycles, determining the status as described in the previous paragraph. Alterna-
tively, it can choose to perform other system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine the status of the operation. Refer to
Figure 7.4, Write Operation Status Flowchart for more details.
DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or erase time has exceeded
a specified internal pulse count limit. Under these conditions DQ5 produces a 1, indicating that
the program or erase cycle was not successfully completed. The device may output a 1 on DQ5 if
the system tries to program a 1 to a location that was previously programmed to 0. Only an erase
operation can change a 0 back to a 1, Under this condition, the device halts the operation, and
when the timing limit has been exceeded, DQ5 produces a 1. Under both these conditions, the
system must write the reset command to return to the read mode (or to the erase-suspend-read
mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator. After writing a sector erase command sequence,
the system may read DQ3 to determine whether or not erasure has begun. (The sector erase
timer does not apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command. When the time-out
period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase
commands from the system can be assumed to be less than t
DQ3. See Sector Erase Command Sequence for more details.
, the system need not monitor
SEA
After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and
then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (ex-
cept Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device
accepts additional sector erase commands. To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to and following each sub-sequent sector erase
command. If DQ3 is high on the second status check, the last command might not have been
accepted. Table 7.18 shows the status of DQ3 relative to the other status bits.
DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted.
Under these conditions DQ1 produces a 1. The system must issue the Write to Buffer Abort Reset
command sequence to return the device to reading array data. See Write Buffer Programming
Operation for more details.
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Table 7.18 Write Operation Status
DQ7
(Note 2)
DQ5
(Note 1)
DQ2
(Note 2)
DQ1
(Note 4)
Status
DQ6
DQ3
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
N/A
1
No toggle
Toggle
0
Standard
Mode
N/A
INVALID INVALID INVALID INVALID INVALID INVALID
(Not (Not (Not (Not (Not (Not
Allowed) Allowed) Allowed) Allowed) Allowed) Allowed)
Reading within Program
Suspended Sector
Program
Suspend
Mode
(Note 3)
Reading within Non-Program
Suspended Sector
Data
1
Data
Data
0
Data
N/A
Data
Data
N/A
Erase Suspended
No Toggle
Toggle
Sector
Erase
Suspend
Mode
Erase-Suspend-Read
Non-Erase
Suspended Sector
Data
DQ7#
1
Data
Toggle
Data
Data
N/A
N/A
Data
N/A
Data
N/A
N/A
Erase-Suspend-Program
0
0
Erase
No toggle
Toggle
Suspended Sector
Erase-Suspend-
Read
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
Data
Erase-Suspend-Program
BUSY State
DQ7#
DQ7#
DQ7#
DQ7#
Toggle
Toggle
Toggle
Toggle
0
0
1
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
Write to
Buffer
(Note 5)
Exceeded Timing Limits
ABORT State
0
1
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 a valid address when reading status information. Refer to the appropriate subsection for further details.
3. Data are invalid for addresses in a Program Suspended sector.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write
Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
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7.5 Simultaneous Read/Write
The simultaneous read/write feature allows the host system to read data from one bank of mem-
ory while programming or erasing another bank of memory. An erase operation may also be
suspended to read from or program another location within the same bank (except the sector
being erased). Figure 11.12, Back-to-back Read/Write Cycle Timings shows how read and write
cycles may be initiated for simultaneous operation with zero latency. See the table, DC Charac-
teristics for read-while-program and read-while-erase current specifications.
VCC
VSS
Mux
Bank A
Bank A Address
X-Decoder
Amax – A0
Bank B Address
Bank B
OE#
X-Decoder
Amax–A0
RESET#
State
Control
and
RY/BY#
Status
WE#
DQ15 – DQ0
CE#
WP#/ACC
Command
Register
Control
Mux
X-Decoder
Bank C
DQ0 – DQ15
Bank C Address
X-Decoder
Bank D
Amax – A0
Bank D Address
Mux
Note: Amax = A23 (PL256N), A22 (PL127N)
Figure 7.5 Simultaneous Operation Block Diagram for S29PL256N and S29PL127N
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CE1# = L
CE2# = H
VCC
VSS
Mux
Bank 1A
Bank 1A Address
A21 – A0
X-Decoder
Bank 1B Address
Bank 1B
X-Decoder
OE#
A21 – A0
RESET#
RY/BY#
State
Control
and
Status
WE#
CE1#
DQ15 – DQ0
CE2#
Command
Register
Control
Mux
WP#/ACC
CE1# = H
CE2# = L
X-Decoder
Bank 2A
DQ0 – DQ15
Bank 2A Address
X-Decoder
Bank 2B
A21 – A0
Bank 2B Address
Mux
Figure 7.6 Simultaneous Operation Block Diagram for S29PL129N
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7.6 Writing Commands/Command Sequences
During a write operation, the system must drive CE# and WE# to V and OE# to V when pro-
IL
IH
viding an address, command, and data. Addresses are latched on the last falling edge of WE# or
CE#, while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase
one sector, multiple sectors, or the entire device. Table 6.1 and Table 6.2 indicate the address
space that each sector occupies. The device address space is divided into four banks: Banks B
and C contain only 128 Kword sectors, while Banks A and D contain both 32 Kword boot sectors
in addition to 128 Kword sectors. A bank address is the set of address bits required to uniquely
select a bank. Similarly, a sector address is the address bits required to uniquely select a sector.
I
in DC Characteristics represents the active current specification for the write mode. see AC
CC2
Characteristics contains timing specification tables and timing diagrams for write operations.
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7.7
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of t , the device immediately terminates any
RP
operation in progress, tristates all outputs, and ignores all read/write commands for the duration
of the RESET# pulse. The device also resets the internal state machine to reading array data.
To ensure data integrity the operation that was interrupted should be reinitiated once the device
is ready to accept another command sequence.
When RESET# is held at V , the device draws CMOS standby current (I
). If RESET# is held
SS
CC4
at V , but not at V , the standby current is greater.
IL
SS
RESET# may be tied to the system reset circuitry which enables the system to read the boot-up
firmware from the Flash memory upon a system reset.
See Figure 11.5 and Figure 11.8 for timing diagrams.
7.8 Software Reset
Software reset is part of the command set (see Table 12.1) that also returns the device to array
read mode and must be used for the following conditions:
1. To exit Autoselect mode
2. To reset software when DQ5 goes high during write status operation that indicates program
or erase cycle was not successfully completed
3. To exit sector lock/unlock operation.
4. To return to erase-suspend-read mode if the device was previously in Erase Suspend mode.
5. To reset software after any aborted operations
Software Functions and Sample Code
Table 7.19 Reset
(LLD Function = lld_ResetCmd)
Cycle
Operation
Word Address
Data
Reset Command
Write
Base + xxxh
00F0h
Note: Base = Base Address.
The following is a C source code example of using the reset function. Refer to the Spansion
Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general
information on Spansion Flash memory software development guidelines.
/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
The following are additional points to consider when using the reset command:
This command resets the banks to the read and address bits are ignored.
Reset commands are ignored once erasure has begun until the operation is complete.
Once programming begins, the device ignores reset commands until the operation is com-
plete
The reset command may be written between the cycles in a program command sequence be-
fore programming begins (prior to the third cycle). This resets the bank to which the system
was writing to the read mode.
If the program command sequence is written to a bank that is in the Erase Suspend mode,
writing the reset command returns that bank to the erase-suspend-read mode.
The reset command may be also written during an Autoselect command sequence.
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If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode.
If DQ1 goes high during a Write Buffer Programming operation, the system must write the
Write to Buffer Abort Reset command sequence to RESET the device to reading array data.
The standard RESET command does not work during this condition.
To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset com-
mand sequence (see command tables for detail).
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8 Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase
operations in any or all sectors and can be implemented through software and/or hardware meth-
ods, which are independent of each other. This section describes the various methods of
protecting data stored in the memory array. An overview of these methods in shown in Figure 8.1.
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
Persistent Method
Password Method
(DQ1)
(DQ2)
WP# = VIL
(All boot
sectors locked)
64-bit Password
(One Time Protect)
PPB Lock Bit (Notes 1, 2, 3)
0 = PPBs Locked
1 = PPBs Unlocked
Persistent
Dynamic
Protection Bit (PPD)
Protection Bit (DYB)
Memory Array
(Notes 5, 6)
(Notes 7, 8, 9)
Sector 0
Sector 1
Sector 2
PPB 0
PPB 1
PPB 2
DYB 0
DYB 1
DYB 2
Sector N-2
Sector N-1
PPB N-2
PPB N-1
PPB N
DYB N-2
DYB N-1
DYB N
Sector N (Note 4)
Notes:
1. Bit is volatile, and defaults to 1 on reset.
2. Programming to 0 locks all PPBs to their current state.
3. Once programmed to 0, requires hardware reset to unlock.
4. N = Highest Address Sector.
5. 0 = Sector Protected,
1 = Sector Unprotected.
6. PPBs programmed individually, but cleared collectively.
7. 0 = Sector Protected,
1 = Sector Unprotected.
8. Protect effective only if PPB Lock Bit is unlocked and
corresponding PPB is 1 (unprotected).
9. Volatile Bits: defaults to user choice upon power-up
(see ordering options).
Figure 8.1 Advanced Sector Protection/Unprotection
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8.1
Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied, and
all sectors are unprotected, unless otherwise chosen through the DYB ordering option (see Or-
dering Information). The device programmer or host system must then choose which sector
protection method to use. Programming (setting to 0) any one of the following two one-time pro-
grammable, non-volatile bits locks the part permanently in that mode:
Lock Register Persistent Protection Mode Lock Bit (DQ1)
Lock Register Password Protection Mode Lock Bit (DQ2)
Table 8.1 Lock Register
Device
DQ15 – 05
DQ4
DQ3
DQ2
DQ1
DQ0
DYB Lock Boot Bit
0 = sectors
PPB One-Time
Programmable Bit
0 = All PPB erase
command disabled
1 = All PPB Erase
command enabled
power up
Password
Persistent
Secured
Silicon Sector
Protection Bit
S29PL256N
Undefined protected
1 = sectors
Protection
Protection
Mode Lock Bit
Mode Lock Bit
power up
unprotected
For programming lock register bits see Table 12.2.
Notes
1. If the password mode is chosen, the password must be programmed before setting the cor-
responding lock register bit.
2. After the Lock Register Bits Command Set Entry command sequence is written, reads and
writes for Bank A are disabled, while reads from other banks are allowed until exiting this
mode.
3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation
aborts.
4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is perma-
nently disabled, and no changes to the protection scheme are allowed. Similarly, if the
Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled.
After selecting a sector protection method, each sector can operate in any of the following three
states:
1. Constantly locked. The selected sectors are protected and cannot be reprogrammed unless
PPB lock bit is cleared via a password, hardware reset, or power cycle.
2. Dynamically locked. The selected sectors are protected and can be altered via software
commands.
3. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Sections 8.2 – 8.6.
8.2 Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same en-
durances as the Flash memory. Preprogramming and verification prior to erasure are handled by
the device, and therefore do not require system monitoring.
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Notes
1. Each PPB is individually programmed and all are erased in parallel.
2. Entry command disables reads and writes for the bank selected.
3. Reads within that bank return the PPB status for that sector.
4. Reads from other banks are allowed while writes are not allowed.
5. All Reads must be performed using the Asynchronous mode.
6. The specific sector addresses (A23 – A14 PL256N and A22 – A14 PL127N/PL129N) are writ-
ten at the same time as the program command.
7. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-
out without programming or erasing the PPB.
8. There are no means for individually erasing a specific PPB and no specific sector address is
required for this operation.
9. Exit command must be issued after the execution which resets the device to read mode and
re-enables reads and writes for Bank A.
10. The programming state of the PPB for a given sector can be verified by writing a PPB Status
Read Command to the device as described by the flow chart below.
8.3 Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified.
DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared
(erased to 1). By issuing the DYB Set or Clear command sequences, the DYBs are set (pro-
grammed to 0) or cleared (erased to 1), thus placing each sector in the protected or unprotected
state respectively. This feature allows software to easily protect sectors against inadvertent
changes yet does not prevent the easy removal of protection when changes are needed.
Notes
1. The DYBs can be set (programmed to 0) or cleared (erased to 1) as often as needed. When
the parts are first shipped, the PPBs are cleared (erased to 1) and upon power up or re-
set, the DYBs can be set or cleared depending upon the ordering option chosen.
2. If the option to clear the DYBs after power up is chosen, (erased to 1), then the sectorsmay
be modified depending upon the PPB state of that sector.
3. The sectors would be in the protected state If the option to set the DYBs after power up is
chosen (programmed to 0).
4. It is possible to have sectors that are persistently locked with sectors that are left in the
dynamic state.
5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected
state of the sectors respectively. However, if there is a need to change the status of the per-
sistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be
cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can
then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks
the PPBs, and the device operates normally again.
6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command
early in the boot code and protect the boot code by holding WP# = V . Note that the PPB
IL
and DYB bits have the same function when WP#/ACC = V
as they do when WP#/
HH
ACC = V
.
IH
8.4 Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed
to 0), this bit locks all PPB and when cleared (programmed to 1), unlocks each sector. There is
only one PPB Lock Bit per device.
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Notes
1. No software command sequence unlocks this bit unless the device is in the password pro-
tection mode; only a hardware reset or a power-up clears this bit.
2. The PPB Lock Bit must be set (programmed to 0) only after all PPBs are configured to the
desired settings.
8.5 Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector
Protection Mode by requiring a 64-bit password for unlocking the device PPB Lock Bit. In addition
to this password requirement, after power up and reset, the PPB Lock Bit is set 0 to maintain the
password mode of operation. Successful execution of the Password Unlock command by entering
the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.
Notes
1. There is no special addressing order required for programming the password. Once the
Password is written and verified, the Password Mode Locking Bit must be set to prevent ac-
cess.
2. The Password Program Command is only capable of programming 0s. Programming a 1
after a cell is programmed as a 0 results in a time-out with the cell as a 0.
3. The password is all 1s when shipped from the factory.
4. All 64-bit password combinations are valid as a password.
5. There is no means to verify what the password is after it is set.
6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data
bus and further password programming.
7. The Password Mode Lock Bit is not erasable.
8. The lower two address bits (A1 – A0) are valid during the Password Read, Password Pro-
gram, and Password Unlock.
9. The exact password must be entered in order for the unlocking function to occur.
10. The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent
a hacker from running through all the 64-bit combinations in an attempt to correctly match
a password.
11. Approximately 1 µs is required for unlocking the device after the valid 64-bit password is
given to the device.
12. Password verification is only allowed during the password programming operation.
13. All further commands to the password region are disabled and all operations are ignored.
14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the
PPB Lock Bit.
15. Entry command sequence must be issued prior to any of any operation and it disables reads
and writes for Bank A. Reads and writes for other banks excluding Bank A are allowed.
16. If the user attempts to program or erase a protected sector, the device ignores the com-
mand and returns to read mode.
17. A program or erase command to a protected sector enables status polling and returns to
read mode without having modified the contents of the protected sector.
18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing
individual status read commands DYB Status, PPB Status, and PPB Lock Status to the
device.
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write
Enter Lock Register Command:
Address 555h, Data 40h
XXXh = Address don’t care
* Not on future devices
Program Lock Register Data
Address XXXh, Data A0h
Address 77h*, Data PD
Program Data (PD): See text for Lock Register
definitions
Caution: Lock data may only be progammed once.
Wait 4 µs
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Done?
No
No
DQ5 = 1?
Yes
Error condition (Exceeded Timing Limits)
PASS. Write Lock Register
Exit Command:
FAIL. Write rest command
to return to reading array.
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
Figure 8.2 Lock Register Program Algorithm
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8.6 Advanced Sector Protection Software Examples
Table 8.2 Sector Protection Schemes
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
Unique Device PPB Lock Bit
0 = locked, 1 = unlocked
Sector Protection Status
Protected through PPB
Protected through PPB
Unprotected
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
0
0
0
1
1
0
0
1
1
x
x
1
0
x
x
0
1
0
0
0
1
1
1
1
Protected through DYB
Protected through PPB
Protected through PPB
Protected through DYB
Unprotected
Table 8.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the sta-
tus of the sector. In summary, if the PPB Lock Bit is locked (set to 0), no changes to the PPBs are
allowed. The PPB Lock Bit can only be unlocked (reset to 1) through a hardware reset or power
cycle. See also Figure 8.1 for an overview of the Advanced Sector Protection feature.
8.7 Hardware Data Protection Methods
The device offers data protection at the sector level via hardware control:
When WP#/ACC is at V , the four outermost sectors are locked (device specific).
IL
There are additional methods by which intended or accidental erasure of any sectors can be pre-
vented via hardware means. The following subsections describes these methods:
8.7.1 WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors.
This function is provided by the WP#/ACC pin and overrides the previously discussed Sector Pro-
tection/Unprotection method.
If the system asserts V on the WP#/ACC pin, the device disables program and erase functions
IL
in the outermost boot sectors. The outermost boot sectors are the sectors containing both the
lower and upper set of sectors in a dual-boot-configured device.
If the system asserts V on the WP#/ACC pin, the device reverts to whether the boot sectors
IH
were last set to be protected or unprotected. That is, sector protection or unprotection for these
sectors depends on whether they were last protected or unprotected.
Note that the WP#/ACC pin must not be left floating or unconnected as inconsistent behavior of
the device may result.
The WP#/ACC pin must be held stable during a command sequence execution
8.7.2 Low V
Write Inhibit
CC
When V is less than V
, the device does not accept any write cycles. This protects data during
LKO
CC
V
power-up and power-down.
CC
The command register and all internal program/erase circuits are disabled, and the device resets
to reading array data. Subsequent writes are ignored until V is greater than V . The system
CC
LKO
must provide the proper signals to the control inputs to prevent unintentional writes when V is
CC
greater than V
.
LKO
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8.7.3 Write Pulse Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.7.4 Power-Up Write Inhibit
If WE# = CE# = RESET# = V and OE# = V during power up, the device does not accept com-
IL
IH
mands on the rising edge of WE#. The internal state machine is automatically reset to the read
mode on powerup.
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9 Power Conservation Modes
9.1
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input. The device enters the CMOS standby mode
when the CE# and RESET# inputs are both held at V ±0.2 V. The device requires standard ac-
CC
cess time (t ) for read access, before it is ready to read data. If the device is deselected during
CE
erasure or programming, the device draws active current until the operation is completed. I
in DC Characteristics represents the standby current specification
CC3
9.2 Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous
mode. the device automatically enables this mode when addresses remain stable for t + 20 ns.
ACC
The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard
address access timings provide new data when addresses are changed. While in sleep mode, out-
put data is latched and always available to the system. I
automatic sleep mode current specification.
in DC Characteristics represents the
CC6
9.3 Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of t , the device immediately terminates any
RP
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once the
device is ready to accept another command sequence to ensure data integrity.
When RESET# is held at V ±0.2 V, the device draws CMOS standby current (I
). If RESET#
SS
CC4
is held at V but not within V ±0.2 V, the standby current is greater.
IL
SS
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
9.4 Output Disable (OE#)
When the OE# input is at V , output from the device is disabled. The outputs are placed in the
IH
high impedance state.
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10 Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part
identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words
in length that consists of 128 words for factory data and 128 words for customer-secured areas.
All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory
Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Se-
cured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6)
is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped
from the factory.
Note the following general conditions:
While the Secured Silicon Sector access is enabled, simultaneous operations are allowed ex-
cept for Bank A.
On power up, or following a hardware reset, the device reverts to sending commands to the
normal address space.
Reads outside of sector 0 return memory array data.
Sector 0 is remapped from the memory array to the Secured Silicon Sector array.
Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit
command must be issued to exit Secured Silicon Sector Mode.
The Secured Silicon Sector is not accessible when the device is executing an Embedded Pro-
gram or Embedded Erase algorithm.
Table 10.1 Secured Silicon Sector Addresses
Sector
Customer
Factory
Sector Size
128 words
128 words
Address Range
000080h-0000FFh
000000h-00007Fh
10.1 Factory Secured Silicon Sector
The Factory Secured Silicon Sector is always protected when shipped from the factory and has
the Factory Indicator Bit (DQ7) permanently set to a 1. This prevents cloning of a factory locked
part and ensures the security of the ESN and customer code once the product is shipped to the
field.
These devices are available pre programmed with one of the following:
A random, 8-word secure ESN only within the Factory Secured Silicon Sector
Customer code within the Customer Secured Silicon Sector through the SpansionTM program-
ming service.
Both a random, secure ESN and customer code through the Spansion programming service.
Customers may opt to have their code programmed through the Spansion programming services.
Spansion programs the customer's code, with or without the random ESN. The devices are then
shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured
Silicon Sector permanently locked. Contact your local representative for details on using Spansion
programming services.
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10.2 Customer Secured Silicon Sector
The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to 0), allowing
customers to utilize that sector in any manner they choose. If the security feature is not required,
the Customer Secured Silicon Sector can be treated as an additional Flash memory space.
Please note the following:
Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is
permanently set to 1.
The Customer Secured Silicon Sector can be read any number of times, but can be pro-
grammed and locked only once. The Customer Secured Silicon Sector lock must be used with
caution as once locked, there is no procedure available for unlocking the Customer Secured
Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space
can be modified in any way.
The accelerated programming (ACC) and unlock bypass functions are not available when pro-
gramming the Customer Secured Silicon Sector, but are available when reading in Banks B
through D.
Once the Customer Secured Silicon Sector is locked and verified, the system must write the
Exit Secured Silicon Sector Region command sequence which return the device to the mem-
ory array at sector 0.
10.3 Secured Silicon Sector Entry and Exit Command Sequences
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured
Silicon Sector command sequence. The device continues to access the Secured Silicon Sector re-
gion until the system issues the four-cycle Exit Secured Silicon Sector command sequence.
See the Command Definition Tables
Table 12.1, Memory Array Commands.
Table 12.2, Sector Protection Commands for address and data requirements for both command
sequences.
The Secured Silicon Sector Entry Command allows the following commands to be executed
Read customer and factory Secured Silicon areas
Program the customer Secured Silicon Sector
After the system has written the Enter Secured Silicon Sector command sequence, it may read
the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the
memory array. This mode of operation continues until the system issues the Exit Secured Silicon
Sector command sequence, or until power is removed from the device.
Software Functions and Sample Code
The following are C functions and source code examples of using the Secured Silicon Sector
Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User Guide
(available soon on www.amd.com and www.fujitsu.com) for general information on Spansion
Flash memory software development guidelines.
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Table 10.2 Secured Silicon Sector Entry
(LLD Function = lld_SecSiSectorEntryCmd)
Cycle
Operation
Write
Word Address
Data
Unlock Cycle 1
Unlock Cycle 2
Base + 555h
Base + 2AAh
Base + 555h
00AAh
0055h
0088h
Write
Entry Cycle
Write
Note: Base = Base Address.
/* Example: SecSi Sector Entry Command */
*((UINT16 *)base_addr + 0x555) = 0x00AA;
*((UINT16 *)base_addr + 0x2AA) = 0x0055;
*((UINT16 *)base_addr + 0x555) = 0x0088;
/* write unlock cycle 1
/* write unlock cycle 2
/* write Secsi Sector Entry Cmd
*/
*/
*/
Table 10.3 Secured Silicon Sector Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Write
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Word Address
Data
Unlock Cycle 1
Unlock Cycle 2
Program Setup
00AAh
0055h
Write
Write
00A0h
Program
Write
Data Word
Note: Base = Base Address.
/* Once in the SecSi Sector mode, you program */
/* words using the programming algorithm.
*/
Table 10.4 Secured Silicon Sector Exit
(LLD Function = lld_SecSiSectorExitCmd)
Cycle
Operation
Write
Word Address
Data
Unlock Cycle 1
Unlock Cycle 2
Exit Cycle
Base + 555h
Base + 2AAh
Base + 555h
00AAh
0055h
0090h
Write
Write
Note: Base = Base Address.
/* Example: SecSi Sector Exit Command */
*((UINT16 *)base_addr + 0x555) = 0x00AA;
*((UINT16 *)base_addr + 0x2AA) = 0x0055;
*((UINT16 *)base_addr + 0x555) = 0x0090;
*((UINT16 *)base_addr + 0x000) = 0x0000;
/* write unlock cycle 1
/* write unlock cycle 2
/* write SecSi Sector Exit cycle 3 */
/* write SecSi Sector Exit cycle 4 */
*/
*/
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11 Electrical Specifications
11.1 Absolute Maximum Ratings
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except as noted below (Note 1). . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VIO + 0.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VIO (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0V
ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 11.1. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage
transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 11.2.
2. Minimum DC input voltage on pin WP#⁄ACC is –0.5 V. During voltage transitions, WP#⁄ACC may overshoot VSS to 2.0 V
for periods of up to 20 ns. See Figure 11.1. Maximum DC voltage on pin WP#⁄ACC is +9.5 V, which may overshoot to
10.5 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than
one second.
4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 11.1 Maximum Negative Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
Figure 11.2 Maximum Positive Overshoot Waveform
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11.2 Operating Ranges
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.7 V to 3.1 V or
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V
(Note 3)
Notes:
1. Operating ranges define those limits between which the functionality of the device is guaranteed.
2. For all AC and DC specifications, VIO = VCC
.
3. Voltage range of 2.7 – 3.1 V valid for PL-N MCP products.
11.3 Test Conditions
Device
Under
Test
C
L
Figure 11.3 Test Setup
Table 11.1 Test Specifications
Test Condition
All Speeds
Unit
pF
ns
V
Output Load Capacitance, C (including jig capacitance)
30
5
L
Input Rise and Fall Times
Input Pulse Levels
V
V
= 3.0 V
= 3.0 V
CC
0.0 – 3.0
CC
Input timing measurement reference levels
Output timing measurement reference levels
V
V
/2
/2
V
CC
V
CC
11.4 Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State
(High Z)
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11.5 Switching Waveforms
VIO
All Inputs and Outputs
VCC/2
VCC/2
Input
Measurement Level
Output
0.0 V
Figure 11.4 Input Waveforms and Measurement Levels
11.6 VCC Power Up
Parameter
tVCS
Description
VCC Setup Time
Test Setup
Min
Speed
250
Unit
µs
ns
tREAD
Time between RESET# high and CE# low
Min
200
Notes:
1. VCC ramp rate must exceed 1 V/400 µs.
2. IO is internally connected to VCC
V
.
tVCS
VCC
VCC
min
VIH
RESET#
CE#
tRead
Figure 11.5
V
Power-Up Diagram
CC
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11.7 DC Characteristics
11.7.1 DC Characteristics (V
(CMOS Compatible)
= 2.7 V to 3.6 V)
CC
Parameter
Symbol
Parameter Description
Min
Typ
Test Conditions
Max
±2.0
±1.0
Unit
µA
(Notes)
(Note 2) (Note 2)
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC max (6)
V
OUT = VSS to VCC, OE# = VIH
VCC = VCC max (6)
ILO
Output Leakage Current
µA
OE# = VIH
,
ICC1
ICC2
ICC3
VCC Active Read Current (1, 3)
VCC Active Write Current (3)
VCC Standby Current
5 MHz
30
25
20
45
50
40
mA
mA
µA
VCC = VCC max (1, 6)
OE# = VIH, WE# = VIL
CE# (7), RESET#,
WP#/ACC = VCC ± 0.3 V
ICC4
ICC5
VCC Reset Current
RESET# = VSS ± 0.3 V
300
20
500
40
µA
µA
Automatic Sleep Mode (4)
VIH = VCC ±0.3 V; VIL = VSS ± 0.3 V
VCC Active Read-While-Write
Current (1)
ICC6
ICC7
ICC8
OE# = VIH
OE# = VIH
5 MHz
35
27
6
50
55
10
mA
mA
mA
VCC Active Program-While-Erase-
Suspended Current (5)
OE# = VIH, 8 word
Page Read
VCC Active Page Read Current
40 MHz
VIL
Input Low Voltage
Input High Voltage
VCC = 2.7 to 3.6 V
VCC = 2.7 to 3.6 V
–0.5
2.0
0.8
V
V
VIH
VCC + 0.3
Voltage for ACC Program
Acceleration
VHH
VCC = 3.0 V ±10% (6)
8.5
9.5
0.1
V
VOL
VOH
VLKO
Output Low Voltage
IOL = 100 µA, VCC = VCC min (6)
IOH = –100 µA (6)
V
V
V
Output High Voltage
VCC – 0.2
2.3
Low VCC Lock-Out Voltage (5)
2.5
Notes:
1. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH
.
2. Maximum ICC specifications are tested with VCC = VCC max, TA = TAmax. Typical ICC specifications are with typical
VCC=3.0 V, TA = +25°C.
3.
ICC is active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC +30 ns. Typical sleep mode
current is 1 µA.
5. Not 100% tested.
6. The data in the table is for VCC range 2.7 V to 3.6 V (recommended for standalone applications).
7. CE1# and CE2# for the PL129N.
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11.7.2 DC Characteristics (V
= 2.7 V to 3.1 V)
CC
(CMOS Compatible)
Parameter
Symbol
Parameter Description
(Notes)
Test Conditions
Min
Typ
Max
±2
Unit
µA
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC max (6)
VOUT = VSS to VCC, OE# = VIH
VCC = VCC max (6)
ILO
Output Leakage Current
±1
µA
OE# = VIH
,
ICC1
ICC2
ICC3
VCC Active Read Current (1, 2)
VCC Active Write Current (2, 3)
VCC Standby Current (2)
5 MHz
28
22
20
40
40
40
mA
mA
µA
V
CC = VCC max (1, 6)
OE# = VIH, WE# = VIL
CE# (7), RESET#, WP#/ACC
= VCC ± 0.3 V
ICC4
ICC5
VCC Reset Current (2)
RESET# = VSS ± 0.3 V
300
20
500
40
µA
µA
Automatic Sleep Mode (2, 4)
VIH = VCC ±0.3 V; VIL = VSS ± 0.1 V
VCC Active Read-While-Write
Current (1, 2)
ICC6
ICC7
ICC8
OE# = VIH
5 MHz
33
24
6
45
45
9
mA
mA
mA
VCC Active Program-While-Erase-
Suspended Current (2, 5)
OE# = VIH
OE# = VIH
8 word Page Read
VCC = 2.7 to 3.6 V
VCC = 2.7 to 3.6 V
,
VCC Active Page Read Current (2)
40 MHz
VIL
VIH
Input Low Voltage
Input High Voltage
–0.5
2.0
0.8
VCC + 0.3
9.5
V
V
V
V
V
V
VHH
VOL
VOH
VLKO
Voltage for ACC Program Acceleration VCC = 3.0 V ±10% (6)
8.5
Output Low Voltage
IOL = 100 µA, VCC = VCC min (6)
IOH = –100 µA (6)
0.1
Output High Voltage
VCC – 0.2
2.3
Low VCC Lock-Out Voltage (5)
2.5
Notes:
1. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH
.
2. Maximum ICC specifications are tested with VCC = VCC max, TA = TAmax. Typical ICC specifications are with typical
VCC=2.9 V, TA = +25°C.
3.
ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode
current is 1 µA.
5. Not 100% tested.
6. Data in table is for VCC range 2.7 V to 3.1 V (recommended for MCP applications)
7. CE1# and CE2# for the PL129N.
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11.8 AC Characteristics
11.8.1 Read Operations
Parameter
Speed Options
65 70 80 Unit
Description
(Notes)
Tes t Setup
JEDEC Std.
tAVAV
tRC Read Cycle Time (1)
Min 65 70 80
Max 65 70 80
Max 65 70 80
Max 25 30 30
Max 25 30 30
ns
ns
ns
ns
ns
ns
ns
tAVQV tACC Address to Output Delay
CE#, OE# = VIL
OE# = VIL
tELQV
tCE Chip Enable to Output Delay (5)
tPACC Page Access Time
tGLQV
tEHQZ
tGHQZ
tOE Output Enable to Output Delay
tDF Chip Enable to Output High Z (3)
tDF Output Enable to Output High Z (1, 3)
Max
Max
16
16
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (3)
tAXQX
tOH
Min
5
ns
Read
Min
Min
0
ns
ns
tOEH Output Enable Hold Time (1)
Toggle and Data# Polling
10
Notes:
1. Not 100% tested.
2. See Figure 11.3 and Table 11.1 for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE#
high to the data bus driven to VCC /2 is taken as tDF
.
4. For 70pf Output Load Capacitance, 2 ns is added to the above tACC ,tCE ,tPACC ,tOE values for all speed grades
5. CE1# and CE2# for the PL129N.
11.8.2 Read Operation Timing Diagrams
tRC
Addresses Stable
tACC
Addresses
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
Data
tCE
tOH
HIGH Z
HIGH Z
Valid Data
RESET#
RY/BY#
0 V
Figure 11.6 Read Operation Timings
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A
22 to A
3
Same page Addresses
A2 to A
0
Aa
Aa+1
Aa+2
Aa+3
Aa+4
Aa+5
Aa+6
Aa+7
t
ACC
tCE
CE#
OE#
tOEH
tOE
tDF
tPACC
tOH
tPACC
tOH
tPACC
tOH
tPACC
tOH
tPACC
tOH
tPACC
tPACC
tOH
WE#
tOH
tOH
Da+7
High-Z
Da
Da+1
Da+2
Da+3
Da+4
Da+5
Da+6
Output
Figure 11.7 Page Read Operation Timings
11.8.3 Hardware Reset (RESET#)
Parameter
All Speed Options
Description
Unit
JEDEC
Std.
t
RESET# Pulse Width
Reset High Time Before Read (See Note)
Min
Min
30
µs
ns
RP
t
200
RH
Note: Not 100% tested.
CE#, OE#
tRH
RESET#
tRP
Figure 11.8 Reset Timings
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11.8.4 Erase/Program Timing
Parameter
Speed Options
Description (Notes)
Unit
JEDEC
tAVAV
Std
tWC
tAS
65
70
80
Write Cycle Time (1)
Address Setup Time
Min 65 70 80
ns
ns
ns
ns
ns
ns
ns
ns
tAVWL
Min
Min
Min
Min
Min
Min
Min
0
15
35
0
tASO
tAH
tAHT
tDS
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
tWLAX
Address Hold Time From CE# or OE# high during toggle bit polling
Data Setup Time
tDVWH
tWHDX
30
0
tDH
Data Hold Time
tOEPH
Output Enable High during toggle bit polling
10
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
Max
Max
Max
Max
Max
Typ
Typ
0
0
ns
ns
ns
ns
ns
µs
µs
sec
ns
ns
ns
ns
µs
µs
µs
µs
µs
CE# Hold Time
tWP
Write Pulse Width
40
25
0
tWPH
tSR/W
Write Pulse Width High
Latency Between Read and Write Operations
tWHWH1
tWHWH1
tWHWH2
tWHWH1 Programming Operation
40
24
1.6
250
0
tWHWH1 Accelerated Programming Operation
tWHWH2 Sector Erase Operation
tVHH
tRB
VHH Rise and Fall Times
Write Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
Noise Pulse Margin on WE#
tBUSY
tWEP
tSEA
tESL
tPSL
tASP
tPSP
90
3
Sector Erase Accept Time-out
50
20
20
100
1
Erase Suspend Latency
Program Suspend Latency
Toggle Time During Sector Protection
Toggle Time During Programming Within a Protected Sector
Notes:
1. Not 100% tested.
2. In program operation timing, addresses are latched on the falling edge of WE#.
3. See Program/Erase Operations for more information.
4. Does not include the preprogramming time.
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Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, DOUT is the true data at the program address
Figure 11.9 Program Operation Timings
VHH
VIL or VIH
WP#/ACC
VIL or VIH
tVHH
tVHH
Figure 11.10 Accelerated Program Timing Diagram
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Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
Data
Status
D
OUT
55h
30h
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status)
Figure 11.11 Chip/Sector Erase Operation Timings
tWC
tWC
tRC
tWC
Valid PA
tAH
Valid RA
Valid PA
Valid PA
Addresses
tAS
tCPH
tAS
tAH
tACC
tCE
CE#
OE#
tCP
tOE
tOEH
tGHWL
tWP
WE#
Data
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE# Controlled Write Cycles
Figure 11.12 Back-to-back Read/Write Cycle Timings
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tRC
VA
Addresses
CE#
VA
VA
tACC
tCE
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ6–DQ0
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle
Figure 11.13 Data# Polling Timings (During Embedded Algorithms)
tAHT
tAS
Addresses
CE#
tAHT
tASO
tCEPH
tOEH
WE#
OE#
tOEPH
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
RY/BY#
Valid Data
(first read)
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle
Figure 11.14 Toggle Bit Timings (During Embedded Algorithms)
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Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to
toggle DQ2 and DQ6.
Figure 11.15 DQ2 vs. DQ6
11.8.5 Erase and Programming Performance
Parameter
(Notes)
Device
Condition
Typ
(Note 1)
Max
(Note 2)
Comments
(Notes)
Unit
VCC
ACC
VCC
ACC
1.6
1.6
0.3
0.3
7
7
4
4
128 Kword
32 Kword
Sector Erase Time
s
Excludes 00h programming
prior to erasure (4)
202 (PL256N)
100 (PL127N)
100(PL129N)
900 (PL256N)
450 (PL127N)
450 (PL129N)
VCC
Chip Erase Time
s
130 (PL256N)
65 (PL127N)
65 (PL129N)
512 (PL256N)
256 (PL127N)
256 (PL129N)
ACC
VCC
ACC
VCC
ACC
VCC
ACC
40
24
400
240
94
Excludes system level overhead
(5)
Word Programming Time
µs
µs
µs
9.4
6
Effective Word Programming Time
utilizing Program Write Buffer
60
300
192
3000
1920
Total 32-Word Buffer
Programming Time
157.3 (PL256N) 315 (PL256N)
78.6 (PL127N) 158 (PL127N)
78.6 (PL129N) 158 (PL129N)
VCC
Chip Programming Time
using 32-Word Buffer (3)
Excludes system level overhead
(5)
s
100 (PL256N)
50 (PL127N)
50 (PL129N)
200 (PL256N)
100 (PL127N)
100 (PL129N)
ACC
Erase Suspend/Erase Resume
<20
<20
µs
µs
Program Suspend/Program Resume
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 10,000 cycles. Additionally,
programming typicals assume checkerboard pattern. All values are subject to change.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 100,000 cycles. All values are subject to change.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
See Table 12.1 and Table 12.2 for further information on command definitions.
6. Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions.
7. See Application Note Erase Suspend/Resume Timing for more details.
8. Word programming specification is based upon a single word programming operation not utilizing the write buffer.
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11.8.6 BGA Ball Capacitance
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
COUT
CIN2
Input Capacitance
Output Capacitance
Control Pin Capacitance
VIN = 0
VOUT = 0
VIN = 0
7
8
8
10
12
11
pF
pF
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
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12 Appendix
This section contains information relating to software control or interfacing with the Flash device.
For additional information and assistance regarding software, see Additional Resources, or ex-
plore the Web at www.amd.com and www.fujitsu.com.
Table 12.1 Memory Array Commands
Bus Cycles (Notes 1 – 6)
Command Sequence
(Notes)
First
Addr
Second
Data Addr Data
Third
Addr Data
Fourth
Addr Data
Fifth
Addr
Sixth
Addr Data
Data
Read (7)
Reset (8)
1
1
4
RA
XXX
555
RD
F0
Manufacturer ID
Device ID (10)
AA 2AA 55 [BA]555 90 [BA]X00 0001
Auto-
select
(9)
(Note
10)
6
4
555
555
AA 2AA 55 [BA]555 90 [BA]X01 227E [BA]X0E
[BA]X0F 2200
(Note
AA 2AA 55 [BA]555 90 [BA]X03
11)
Indicator Bits
Program
4
6
1
3
6
6
1
1
555
555
SA
555
555
555
BA
AA 2AA 55
AA 2AA 55
29
AA 2AA 55
AA 2AA 55
AA 2AA 55
B0
555
SA
A0
25
PA
SA
Data
WC
Write to Buffer (17)
Program Buffer to Flash
Write to Buffer Abort Reset (17)
Chip Erase
PA
PD
WBL
PD
555
555
555
F0
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend (14)
Program/Erase Resume (15)
CFI Query (16)
BA
30
1 [BA]555 98
Unlock Bypass Entry
Unlock Bypass Program (12, 13)
Unlock Bypass Sector Erase (12, 13) 2
Unlock Bypass Erase (12, 13)
Unlock Bypass CFI (12, 13)
Unlock Bypass Reset
3
2
555
XX
XX
XX
BA
XX
AA 2AA 55
555
20
A0
80
PA
SA
PD
30
Unlock
Bypass
Mode
2
1
2
80 XXX 10
98
90 XXX 00
Secured Silicon Sector Command Definitions
Secured Silicon Sector Entry (18)
3
2
1
4
555
XX
RA
AA 2AA 55
555
555
88
90
Secured
Secured Silicon Sector Program
Secured Silicon Sector Read
A0
PA data
Silicon
Sector
data
AA 2AA 55
Secured Silicon Sector Exit (19)
555
XX
00
Legend:
X = Don’t care.
RA = Read Address.
RD = Read Data.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse whichever
happens later.
SA = Sector Address. PL127/129N = A22 – A15;
PL256N = A23 – A15.
BA = Bank Address. PL256N = A23 – A21; PL127N = A22 – A20;
PL127N = A21 – A20.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
Notes:
1. See (Table 7.1) for description of bus operations.
9. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address. See
Autoselect.
10. Device IDs: PL256N = 223Ch; PL127N = 2220h;
PL129N = 2221h.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read
cycle, fourth through sixth cycles of the Autoselect commands,
fourth cycle of the password verify command, and any cycle
reading at RD(0) and RD(1).
11. See Autoselect.
4. Data bits DQ15 – DQ8 are don’t care in command sequences,
except for RD, PD, WD, PWD, and PWD3 – PWD0.
12. The Unlock Bypass command sequence is required prior to this
command sequence.
5. Unless otherwise noted, these address bits are don’t cares:
13. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
PL127: A22 – A15; 129N: A21 – A15; PL256N: A23 – A14.
6. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
14. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
7. No unlock or command cycles required when bank is reading
array data.
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
8. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information) or
performing sector lock/unlock.
16. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer.
The maximum number of cycles in the command sequence is 37.
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17. Command sequence resets device for next command after write-
to-buffer operation.
18. Entry commands are needed to enter a specific mode to enable
instructions only available within that mode.
19. The Exit command must be issued to reset the device into read
mode. Otherwise the device hangs.
21. Command is valid when device is ready to read array data or
when device is in autoselect mode. Address equals 55h on all
future devices, but 555h for PL256N.
22. Requires Entry command sequence prior to execution. Secured
Silicon Sector Exit Reset command is required to exit this mode;
device may otherwise be placed in an unknown state.
20. The following mode cannot be performed at the same time.
Autoselect/CFI/Unlock Bypass/Secured Silicon. Command
sequence resets device for next command after write-to-buffer
operation.
Table 12.2 Sector Protection Commands
Bus Cycles (Notes 1 – 6)
Third Fourth
Addr Data Addr Data Addr Data Addr Data Addr Data
Command Sequence
First
Second
Fifth
Sixth
Seventh
(Notes)
Addr Data Addr Data
Lock Register Command Set Definitions
Lock Register Command Set Entry (25)
3
2
1
2
555
XX
00
AA
A0
data
90
2AA
00
55
data
555
40
Lock Register Bits Program (26)
Lock Register Bits Read
Lock
Register
Lock Register Command Set Exit (27)
XX
XX
00
Password Protection Command Set Definitions
Password Protection
3
2
555
XX
AA
A0
2AA
55
555
60
Command Set Entry (25)
PWD0/
00/01 PWD1/
02/03 PWD2/
PWD3
Password Program
Password
Password Read
Password Unlock
4
7
00
00
PWD0
25
01
00
PWD1
03
02
00
PWD2 03
PWD0 01
PWD3
PWD1 02 PWD2 03 PWD3 00
29
Password Protection
Command Set Exit (27)
2
XX
90
XX
00
Non-Volatile Sector Protection Command Set Definitions
Non-Volatile Sector Protection
3
555
AA
2AA
55
[BA]555
C0
Command Set Entry (25)
PPB Program
All PPB Erase (22)
PPB Status Read
2
2
1
XX
XX
A0
80
[BA]SA
00
00
30
PPB
[BA]SA RD(0)
Non-Volatile Sector Protection
Command Set Exit (27)
2
XX 90
XX
00
Global Non-Volatile Sector Protection Freeze Command Set Definitions
Global Volatile Sector Protection Freeze
3
555
AA
2AA
XX
55
00
555
50
E0
Command Set Entry (25)
PPB Lock Bit Set
PPB Lock Bit Status Read
2
1
XX
BA
A0
RD(0)
PPB Lock
Bit
Global Volatile Sector Protection Freeze
Command Set Exit (27)
2
XX
90
XX
00
Volatile Sector Protection Command Set Definitions
Volatile Sector Protection
Command Set Entry (25)
DYB Set
3
555
AA
2AA
55
[BA]555
2
2
1
XX
XX
A0
A0
[BA]SA
[BA]SA
00
01
DYB
DYB Clear
DYB Status Read
[BA]SA RD(0)
Volatile Sector Protection
Command Set Exit (27)
2
XX 90
XX
00
Legend:
X = Don’t care
RA = Read Address.
RD = Read Data.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse whichever
happens later.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
BA = Bank Address. PL256N = A23 – A21; PL127N = A22 – A20;
PL127N = A21 – A20.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
PWD3 – PWD0 = Password Data. PD3 – PD0 present four 16 bit
combinations that represent the 64-bit Password
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if
unprotected, DQ0 = 1.
SA = Sector Address. PL127/129N = A22 – A15; PL256N = A23 –
A15
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Notes:
1. See (Table 7.1) for description of bus operations.
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
2. All values are in hexadecimal.
16. Command is valid when device is ready to read array data or
when device is in autoselect mode.The total number of cycles in
the command sequence is determined by the number of words
written to the write buffer. The maximum number of cycles in
the command sequence is 37.
3. Except for the following, all bus cycles are write cycle: read
cycle, fourth through sixth cycles of the Autoselect commands,
and password verify commands, and any cycle reading at RD(0)
and RD(1).
4. Data bits DQ15 – DQ8 are don’t care in command sequences,
except for RD, PD, WD, PWD, and PWD3 – PWD0.
5. Unless otherwise noted, these address bits are don’t cares:
PL127: A22 – A15; 129N: A21 – A15; PL256N: A23 – A14.
6. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
7. No unlock or command cycles required when bank is reading
array data.
8. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information) or
performing sector lock/unlock.
9. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address. See
Autoselect.
10. The data is 0000h for an unlocked sector and 0001h for a locked
sector.
11. Device IDs: PL256N = 223Ch; PL127N = 2220h;
PL129N = 2221h.
12. See Autoselect.
17. The entire four bus-cycle sequence must be entered for which
portion of the password.
18. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass
mode.The system may read and program in non-erasing sectors,
or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
19. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
20. Command is valid when device is ready to read array data or
when device is in autoselect mode.The total number of cycles in
the command sequence is determined by the number of words
written to the write buffer. The maximum number of cycles in
the command sequence is 37.
21. The entire four bus-cycle sequence must be entered for which
portion of the password.
22. The ALL PPB ERASE command pre-programs all PPBs before
erasure to prevent over-erasure of PPBs.
23. WP#/ACC must be at VHH during the entire operation of this
command.
24. Command sequence resets device for next command after write-
to-buffer operation.
13. The Unlock Bypass command sequence is required prior to this
command sequence.
25. Entry commands are needed to enter a specific mode to enable
instructions only available within that mode.
26. If both the Persistent Protection Mode Locking Bit and the
password Protection Mode Locking Bit are set a the same time,
the command operation aborts and returns the device to the
default Persistent Sector Protection Mode.
14. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass
mode.The system may read and program in non-erasing sectors,
or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
27. The Exit command must be issued to reset the device into read
mode. Otherwise the device hangs.
12.1 Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software inter-
rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-
dent, and forward- and back-ward-compatible for the specified flash device families. Flash
vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address (BA)555h any time the device is ready to read array data. The system can read CFI in-
formation at the addresses given in Tables 12.3 – 12.6) within that bank. All reads outside of the
CFI address range, within the bank, return non-valid data. Reads from other banks are allowed,
writes are not. To terminate reading CFI data, the system must write the reset command.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to
the Spansion Low Level Driver User’s Guide (available at www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: CFI Entry command */
*((UINT16 *)bank_addr + 0x555) = 0x0098;
/* write CFI entry command
/* write cfi exit command
*/
*/
/* Example: CFI Exit command */
*((UINT16 *)bank_addr + 0x000) = 0x00F0;
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
75
P r e l i m i n a r y
For further information, please see the CFI Specification (see JEDEC publications JEP137-A and
JESD68.01and CFI Publication 100). Please contact your sales office for copies of these
documents.
Table 12.3 CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string QRY
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Table 12.4 System Interface String
Addresses
Data
Description
V
CC Min. (write/erase)
1Bh
0027h
D7 – D4: volt, D3 – D0: 100 millivolt
V
CC Max. (write/erase)
1Ch
0036h
D7 – D4: volt, D3 – D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0006h
0009h
000Bh
0000h
0003h
0003h
0002h
0000h
V
V
PP Min. voltage (00h = no VPP pin present)
PP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 12.5 Device Geometry Definition
Addresses
Data
Description
0019h (PL256N)
0018h (PL127N)
0018h (PL129N)
27h
Device Size = 2N byte
28h
29h
0001h
0000h
Flash Device Interface description (see CFI publication 100)
2Ah
2Bh
0006h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0003h
0000h
0000h
0001h
Erase Block Region 1 Information
(see the CFI specification or CFI publication 100)
007Dh (PL256N)
003Dh (PL127N)
003Dh (PL129N)
31h
Erase Block Region 2 Information
(see the CFI specification or CFI publication 100)
32h
33h
34h
0000h
0000h
0004h
35h
36h
37h
38h
0003h
0000h
0000h
0001h
Erase Block Region 3 Information
(see the CFI specification or CFI publication 100)
76
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
Table 12.6 Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string PRI
43h
44h
0031h
0034h
Major version number, ASCII (reflects modifications to the silicon)
Minor version number, ASCII (reflects modifications to the CFI table)
Address Sensitive Unlock (Bits 1 – 0)
0 = Required, 1 = Not Required
45h
0010h
Silicon Technology (Bits 5 – 2) 0100 = 0.11 µm
Erase Suspend
46h
47h
48h
0002h
0001h
0000h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode,
04 = 29LV800 mode 07 = New Sector Protect mode,
08 = Advanced Sector Protection
49h
4Ah
0008h (PL-N)
0073h (PL256N)
003Bh (PL127N)
003Bh (PL129N)
Simultaneous Operation
00 = Not Supported, X = Number of Sectors except Bank A
Burst Mode Type
4Bh
4Ch
4Dh
4Eh
0000h
0002h (PL-N)
0085h
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7 – D4: Volt, D3 – D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7 – D4: Volt, D3 – D0: 100 mV
0095h
Top/Bottom Boot Sector Flag
4Fh
50h
0001h
0001h
00h = No Boot, 01h = Dual Boot Device, 02h = Bottom Boot Device, 03h = Top
Boot Device
Program Suspend
0 = Not supported, 1 = Supported
Unlock Bypass
00 = Not Supported, 01=Supported
Secured Silicon Sector (Customer OTP Area) Size 2N bytes
51h
52h
53h
0001h
0007h
000Fh
Hardware Reset Low Time-out during an embedded algorithm to read mode
Maximum 2N ns
Hardware Reset Low Time-out not during an embedded algorithm to read mode
Maximum 2N ns
54h
000Eh
55h
56h
0005h
0005h
Erase Suspend Time-out Maximum 2N µs
Program Suspend Time-out Maximum 2N µs
Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
57h
0004h
0013h (PL256N)
000Bh (PL127N)
000Bh (PL129N)
58h
Bank A Region Information. X = Number of sectors in bank
Bank 1 Region Information. X = Number of sectors in bank
Bank 2 Region Information. X = Number of sectors in bank
Bank 3 Region Information. X = Number of sectors in bank
0030h (PL256N)
0018h (PL127N)
0018h (PL129N)
59h
5Ah
5Bh
0030h (PL256N)
0018h (PL127N)
0018h (PL129N)
0013h (PL256N)
000Bh (PL127N)
000Bh (PL129N)
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
77
P r e l i m i n a r y
13 Commonly Used Terms
Term
Definition
ACCelerate. A special purpose input signal which allows for faster programming or
ACC
erase operation when raised to a specified voltage above V . In some devices ACC
CC
may protect all sectors when at a low voltage.
Most significant bit of the address input [A23 for 256 Mbit, A22 for 128 Mbit, A21 for
64 Mbit]
A
A
max
Least significant bit of the address input signals (A0 for all devices in this document).
min
Operation where signal relationships are based only on propagation delays and are
unrelated to synchronous control (clock) signal.
Asynchronous
Autoselect
Read mode for obtaining manufacturer and device information as well as sector
protection status.
Section of the memory array consisting of multiple consecutive sectors. A read
operation in one bank, can be independent of a program or erase operation in a
different bank for devices that offer simultaneous read and write feature.
Bank
Smaller size sectors located at the top and or bottom of Flash device address space.
The smaller sector size allows for finer granularity control of erase and protection for
code or parameters used to initiate system operation after power on or reset.
Boot sector
Boundary
Burst Read
Byte
Location at the beginning or end of series of memory locations.
See synchronous read.
8 bits
Common Flash Interface. A Flash memory industry standard specification [JEDEC 137-
A and JESD68.01] designed to allow a system to interrogate the Flash to determine its
size, type and other performance parameters.
CFI
Clear
Zero (Logic Low Level)
Special purpose register which must be programmed to enable synchronous read
mode
Configuration Register
Synchronous method of burst read whereby the device reads continuously until it is
stopped by the host, or it has reached the highest address of the memory array, after
which the read address wraps around to the lowest memory array address
Continuous Read
Erase
Returns bits of a Flash memory array to their default state of a logical One (High Level).
Halts an erase operation to allow reading or programming in any sector that is not
selected for erasure
Erase Suspend/Erase Resume
Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array
and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram
for further details.
BGA
Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with
Linear Read
or without wraparound before requiring a new initial address
.
Multi-Chip Product. A method of combining integrated circuits in a single package by
stacking multiple die of the same or different devices.
MCP
Memory Array
MirrorBit™ Technology
The programmable area of the product available for data storage.
Spansion™ trademarked technology for storing multiple bits of data in the same
transistor.
Group of words that may be accessed more rapidly as a group than if the words were
accessed individually.
Page
78
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
Term
Definition
Asynchronous read operation of several words in which the first word of the group
takes a longer initial access time and subsequent words in the group take less page
access time to be read. Different words in the group are accessed by changing only the
least significant address lines.
Page Read
Sector protection method which uses a programmable password, in addition to the
Password Protection
Persistent Protection
Program
Persistent Protection method, for protection of sectors in the Flash memory device
.
Sector protection method that uses commands and only the standard core voltage
supply to control protection of sectors in the Flash memory device. This method
replaces a prior technique of requiring a 12V supply to control the protection method.
Stores data into a Flash memory by selectively clearing bits of the memory array to
leave a data pattern of ones and zeros.
Program Suspend/Program
Resume
Halts a programming operation to read data from any location that is not selected for
programming or erase.
Read
Host bus cycle that causes the Flash to output data onto the data bus.
Dynamic storage bits for holding device control information or tracking the status of
an operation.
Registers
An area consisting of 256 bytes in which any word may be programmed once, and the
entire area may be protected once from any future programming. Information in this
area may be programmed at the factory or by the user. Once programmed and
protected there is no way to change the secured information. This area is often used
to store a software readable identification such as a serial number.
Secured Silicon
Use of one or more control bits per sector to indicate whether each sector may be
programmed or erased. If the Protection bit for a sector is set the embedded
algorithms for program or erase ignore the program or erase commands related to that
sector.
Sector Protection
Sector
An Area of the memory array in which all bits must be erased together by an erase
operation.
Mode of operation in which a host system may issue a program or erase command to
one bank, that embedded algorithm operation may then proceed while the host
immediately follows the embedded algorithm command with reading from another
bank. Reading may continue concurrently in any bank other than the one executing
the embedded algorithm operation.
Simultaneous Operation
Synchronous Operation
Operation that progresses only when a timing signal, known as a clock, transitions
between logic levels (that is, at a clock edge).
Separate power supply or voltage reference signal that allows the host system to set
the voltage levels that the device generates at its data outputs and the voltages
tolerated at its data inputs.
VersatileIO™ (V )
IO
Mode that facilitates faster program times by reducing the number of command bus
cycles required to issue a write operation command. In this mode the initial two Unlock
write cycles, of the usual 4 cycle Program command, are not required – reducing all
Program commands to two bus cycles while in this mode.
Unlock Bypass
Word
Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two
contiguous words located on a two word boundary. A quad word is four contiguous
words located on a four word boundary.
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
79
P r e l i m i n a r y
Term
Definition
Special burst read mode where the read address wraps or returns back to the lowest
address boundary in the selected range of words, after reading the last Byte or Word
in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read
words in the sequence 2, 3, 0, 1.
Wraparound
Interchangeable term for a program/erase operation where the content of a register
and or memory location is being altered. The term write is often associated with writing
command cycles to enter or exit a particular mode of operation.
Write
Multi-word area in which multiple words may be programmed as a single operation. A
Write Buffer
Write Buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary
respectively.
Method of writing multiple words, up to the maximum size of the Write Buffer, in one
operation. Using Write Buffer Programming results in greater than eight times faster
programming time than by using single word at a time programming commands.
Write Buffer Programming
Write Operation Status
Allows the host system to determine the status of a program or erase operation by
reading several special purpose register bits
.
80
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
81
P r e l i m i n a r y
14 Revisions
Revision A0 (February 28, 2005)
Initial Release
Revision A1 (August 8, 2005)
Performance Characteristics
Updated Package Options
MCP Look-Ahead Connection Diagram
Corrected Pinout
Memory Map
Added Sector and Memory Address Map for S29PL127N
Device Operation Table
Added Dual Chip Enable Device Operation Table
V
Power Up
CC
Updated t
.
VCS
Added V ramp rate restriction
CC
DC Characteristics
Updated typical and maximum values.
Revision A2 (October 25, 2005)
Ordering Information
Updated table.
Connection Diagram and Package Dimensions - S29PL-N Fortified BGA
Added pinout and package dimensions.
Global
Changed data sheet status from Advance Information to Preliminary.
Removed Byte Address Information
Distinctive and Performance Characteristics
Removed Enhanced VersatileI/O, updated read access times, and Package options.
Logic Symbol and Block Diagram
Removed V from Logic Symbol and Block Diagram.
IO
Erase and Programming Performance
Updated table.
Write Buffer Programming
Updated Write Buffer Abort Description.
Operating Ranges
Updated V supply voltages.
IO
DC characteristics
Updated I
, I
, I
.
CC1 CC4 CC6
82
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
Revision A3 (November 14, 2005)
Ordering Information
Updated table
Valid Combinations Table
Updated table
Revision A4 (November 23, 2005)
Logic Symbols
Removed V from the illustrations
IO
Block Diagram
Removed V from the illustration
IO
Connection Diagrams
Modified Fortified BGA Pinout (LAA064)
PL129N Sector and Memory Address Map
Updated Address Ranges for Banks 2A and 2B
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-
mentioned uses of the products. Any semiconductor device has an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-
port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product
names used in this publication are for identification purposes only and may be trademarks of their respective companies.
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
83
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![](http://pdffile.icpdf.com/pdf1/p00114/img/page/S29PL127N65FAI000_622817_files/S29PL127N65FAI000_622817_2.jpg)
S29PL256N80FFI002
256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
SPANSION
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