S29WS064N0PBAI012 [SPANSION]
256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY; 256/128/64兆位CMOS 1.8伏只同时读/写突发模式闪存型号: | S29WS064N0PBAI012 |
厂家: | SPANSION |
描述: | 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
文件: | 总99页 (文件大小:921K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADVANCE
INFORMATION
S29WS-N MirrorBit™ Flash Family
S29WS256N, S29WS128N, S29WS064N
256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
Data Sheet
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S29WS-N_00 Revision G Amendment 0 Issue Date January 25, 2005
This page intentionally left blank.
S29WS-N MirrorBit™ Flash Family
S29WS256N, S29WS128N, S29WS064N
256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
ADVANCE
INFORMATION
Data Sheet
General Description
The Spansion S29WS256/128/064N are MirrorbitTM Flash products fabricated on 110 nm process technology. These burst
mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate
banks using separate data and address pins. These products can operate up to 80 MHz and use a single VCC of
1.7 V to 1.95 V that makes them ideal for today’s demanding wireless applications requiring higher density, better per-
formance and lowered power consumption.
Distinctive Characteristics
Single 1.8 V read/program/erase (1.70–1.95 V)
Command set compatible with JEDEC (42.4)
standard
110 nm MirrorBit™ Technology
Hardware (WP#) protection of top and bottom
sectors
Simultaneous Read/Write operation with zero
latency
32-word Write Buffer
Dual boot sector configuration (top and bottom)
Sixteen-bank architecture consisting of 16/8/4
Mwords for WS256N/128N/064N, respectively
Offered Packages
— WS064N: 80-ball FBGA (7 mm x 9 mm)
— WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)
Four 16 Kword sectors at both top and bottom of
memory array
Low VCC write inhibit
254/126/62 64 Kword sectors (WS256N/128N/
064N)
Persistent and Password methods of Advanced
Sector Protection
Programmable burst read modes
Write operation status bits indicate program and
erase operation completion
— Linear for 32, 16 or 8 words linear read with or
without wrap-around
Suspend and Resume commands for Program and
Erase operations
— Continuous sequential read mode
SecSi™ (Secured Silicon) Sector region consisting
of 128 words each for factory and customer
Unlock Bypass program command to reduce
programming time
20-year data retention (typical)
Synchronous or Asynchronous program operation,
independent of burst control register settings
Cycling Endurance: 100,000 cycles per sector
(typical)
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
RDY output indicates data available to system
Industrial Temperature range (contact factory)
Performance Characteristics
Read Access Times
Current Consumption (typical values)
Speed Option (MHz)
Max. Synch. Latency, ns (tIACC
Max. Synch. Burst Access, ns (tBACC
Max. Asynch. Access Time, ns (tACC
Max CE# Access Time, ns (tCE
Max OE# Access Time, ns (tOE
80
80
66
80
54
80
Continuous Burst Read @ 66 MHz
35 mA
50 mA
19 mA
19 mA
20 µA
)
Simultaneous Operation (asynchronous)
Program (asynchronous)
)
9
11.2
80
13.5
80
)
80
Erase (asynchronous)
)
80
80
80
Standby Mode (asynchronous)
)
13.5
13.5
13.5
Typical Program & Erase Times
Single Word Programming
40 µs
9.4 µs
6 µs
Effective Write Buffer Programming (VCC) Per Word
Effective Write Buffer Programming (VACC) Per Word
Sector Erase (16 Kword Sector)
150 ms
600 ms
Sector Erase (64 Kword Sector)
Publication Number S29WS-N_00 Revision G Amendment 0 Issue Date January 25, 2005
A d v a n c e I n f o r m a t i o n
Contents
1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2 Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4 Physical Dimensions/Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.1 Related Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Special Handling Instructions for FBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2.1 VBH084—84-ball Fine-Pitch Ball Grid Array, 8 x 11.6 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.2 TLC080—80-ball Fine-Pitch Ball Grid Array, 7 x 9 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 MCP Look-ahead Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
7 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.3 Synchronous (Burst) Read Mode &
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
7.3.3 Continuous Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3.4 8-, 16-, 32-Word Linear Burst Read with Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3.5 8-, 16-, 32-Word Linear Burst without Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3.6 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.5.1. Single Word Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.5.2 Write Buffer Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.5.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
7.5.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.5.5 Erase Suspend/Erase Resume Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.5.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5.7 Accelerated Program/Chip Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.5.8 Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.5.9 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
7.6 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.7 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.8 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.9 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.10 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
8.1 Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
8.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
8.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.5 Password Protection Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.7 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.7.1. WP# Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.7.2 ACC Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.7.3 Low VCC Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.7.4 Write Pulse “Glitch Protection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.7.5 Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9 Power Conservation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2
S29WS-N MirrorBit™ Flash Family
S29WS-N_00_G0 January25,2005
A d v a n c e I n f o r m a t i o n
9.3 Hardware RESET# Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
10.1 Factory Secured SiliconSector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
10.3 Secured Silicon Sector Entry and Secured Silicon Sector Exit Command Sequences. . . . . . . . . . . . . . . . . . . . . .61
11 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.3 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.6 VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.7 DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11.8.1. CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11.8.2 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.8.3 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11.8.4 AC Characteristics—Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.8.5 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.8.6 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
11.8.7 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.8.8 BGA Ball Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
12.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
13 Commonly Used Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
14 Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
January 25, 2005 S29WS-N_00_G0
S29WS-N MirrorBit™ Flash Family
3
A d v a n c e I n f o r m a t i o n
Figures
Figure 3.1.
Figure 4.1.
Figure 4.2.
Figure 4.3.
Figure 4.4.
Figure 4.5.
S29WS-N Block Diagram..................................................................................................................... 8
84-ball Fine-Pitch Ball Grid Array (S29WS256N, S29WS128N).................................................................10
VBH084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm MCP Compatible Package .........................11
80-ball Fine-Pitch Ball Grid Array (S29WS064N)....................................................................................12
TLC080—80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm MCP Compatible Package...............................13
MCP Look-ahead Diagram ..................................................................................................................15
Figure 7.1.
Figure 7.2.
Synchronous/Asynchronous State Diagram...........................................................................................21
Synchronous Read ............................................................................................................................23
Figure 7.3.
Figure 7.4.
Figure 7.5.
Figure 7.6.
Single Word Program.........................................................................................................................29
Write Buffer Programming Operation ...................................................................................................33
Sector Erase Operation ......................................................................................................................36
Write Operation Status Flowchart ........................................................................................................43
Figure 8.1.
Figure 8.2.
Advanced Sector Protection/Unprotection.............................................................................................50
PPB Program/Erase Algorithm.............................................................................................................53
Figure 8.3.
Lock Register Program Algorithm.........................................................................................................56
Figure 11.1. Maximum Negative Overshoot Waveform .............................................................................................64
Figure 11.2. Maximum Positive Overshoot Waveform...............................................................................................64
Figure 11.3. Test Setup .......................................................................................................................................64
Figure 11.4. Input Waveforms and Measurement Levels...........................................................................................66
Figure 11.5. VCC Power-up Diagram ......................................................................................................................66
Figure 11.6. CLK Characterization .........................................................................................................................68
Figure 11.7. CLK Synchronous Burst Mode Read......................................................................................................70
Figure 11.8. 8-word Linear Burst with Wrap Around.................................................................................................71
Figure 11.9. 8-word Linear Burst without Wrap Around ............................................................................................71
Figure 11.10. Linear Burst with RDY Set One Cycle Before Data..................................................................................72
Figure 11.11. Asynchronous Mode Read...................................................................................................................73
Figure 11.12. Reset Timings...................................................................................................................................74
Figure 11.13. Chip/Sector Erase Operation Timings...................................................................................................76
Figure 11.14. Asynchronous Program Operation Timings............................................................................................77
Figure 11.15. Synchronous Program Operation Timings .............................................................................................78
Figure 11.16. Accelerated Unlock Bypass Programming Timing ...................................................................................79
Figure 11.17. Data# Polling Timings (During Embedded Algorithm).............................................................................79
Figure 11.18. Toggle Bit Timings (During Embedded Algorithm)..................................................................................80
Figure 11.19. Synchronous Data Polling Timings/Toggle Bit Timings ............................................................................80
Figure 11.20. DQ2 vs. DQ6....................................................................................................................................81
Figure 11.21. Latency with Boundary Crossing when Frequency > 66 MHz....................................................................81
Figure 11.22. Latency with Boundary Crossing into Program/Erase Bank......................................................................82
Figure 11.23. Example of Wait States Insertion ........................................................................................................83
Figure 11.24. Back-to-Back Read/Write Cycle Timings ...............................................................................................84
4
S29WS-N MirrorBit™ Flash Family
S29WS-N_00_G0 January25,2005
A d v a n c e I n f o r m a t i o n
Tables
Table 2.1. Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 6.1. S29WS256N Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 6.2. S29WS128N Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 6.3. S29WS064N Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 7.1. Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 7.2. Address Latency (S29WS256N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7.3. Address Latency (S29WS128N/S29WS064N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7.4. Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7.5. Address/Boundary Crossing Latency (S29WS256N @ 54MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7.6. Address/Boundary Crossing Latency (S29WS128N/S29WS064N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 7.7. Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 7.8. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 7.9. Autoselect Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 7.10. Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 7.11. Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 7.12. Single Word Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 7.13. Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 7.14. Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 7.15. Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 7.16. Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 7.17. Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 7.18. Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 7.19. Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 7.20. Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 7.21. Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 7.22. Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 7.23. DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 7.24. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 7.25. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 8.1. Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 8.2. Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 10.1. Secured Silicon Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 10.2. Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 10.3. Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 10.4. Secured Silicon Sector Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 11.1. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 12.1. Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 12.2. Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 12.3. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 12.4. System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 12.5. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table 12.6. Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
January 25, 2005 S29WS-N_00_G0
S29WS-N MirrorBit™ Flash Family
5
A d v a n c e I n f o r m a t i o n
1 Ordering Information
The ordering part number is formed by a valid combination of the following:
S29WS
256
N
0S BA
W
01
0
PACKING TYPE
0
2
3
=
=
=
Tray (standard; see note 1)
7-inch Tape and Reel
13-inch Tape and Reel
MODEL NUMBER (Note 3)
(Package Ball Count, Package Dimensions, DYB Protect/Unprotect After
Power-up)
01
11
=
=
84-ball, 8 x 11.6 mm, DYB Unprotect
80-ball, 7 x 9 mm, DYB Protect
TEMPERATURE RANGE (Note 3)
W
I
=
=
Wireless (–25
°
C to +85
°
C)
Industrial (–40
°
C to +85
°C, contact factory for availability)
PACKAGE TYPE AND MATERIAL
BA
BF
=
=
Very Thin Fine-Pitch BGA, Lead (Pb)-free Compliant Package
Very Thin Fine-Pitch BGA, Lead (Pb)-free Package
SPEED OPTION (BURST FREQUENCY)
0S
0P
0L
=
=
=
80 MHz (contact factory for availability)
66 MHz
54 MHz
PROCESS TECHNOLOGY
110 nm MirrorBit™ Technology
N
=
FLASH DENSITY
256
128
064
=
=
=
256 Mb
128 Mb
64 Mb
DEVICE FAMILY
S29WS = 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
S29WS-N Valid Combinations (Notes 1, 2, 3)
DYB Power
Up State
Package Type
(Note 2)
Package Type,
VIO Range
Base Ordering
Part Number
Product
Status
Speed
Option
Model
Number
Packing
Type
Material, &
Temperature Range
01
11
01
11
01
Unprotect
Protect
S29WS256N
S29WS128N
Preliminary
Advance
8 mm x 11.6 mm
84-ball
BAW (Lead (Pb)-free
Compliant),
BFW (Lead (Pb)-free)
Unprotect
Protect
MCP-Compatible
0, 2, 3
(Note 1)
0S, 0P, 0L
1.70–1.95 V
Unprotect
7 mm x 9 mm
80-ball
MCP-Compatible
S29WS064N
Advance
11
Protect
Notes:
Valid Combinations
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S29” and packing type
designator from ordering part number.
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
3. For 1.5 VIO option, other boot options, or industrial temperature
range, contact your local sales office.
6
S29WS-N MirrorBit™ Flash Family
S29WS-N_00_G0 January25,2005
A d v a n c e I n f o r m a t i o n
2 Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
Table 2.1. Input/Output Descriptions
Symbol
A23–A0
DQ15–DQ0
CE#
Type
Input
Description
Address lines for WS256N (A22-A0 for WS128 and A21-A0 for WS064N).
Data input/output.
I/O
Input
Chip Enable. Asynchronous relative to CLK.
Output Enable. Asynchronous relative to CLK.
Write Enable.
OE#
Input
WE#
Input
VCC
Supply
Input
Device Power Supply.
VIO
VersatileIO Input. Should be tied to VCC
Ground.
.
VSS
I/O
NC
No Connect
Output
Not connected internally.
RDY
Ready. Indicates when valid burst data is ready to be read.
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK
increment the internal address counter. Should be at VIL or VIH while in asynchronous
mode.
CLK
Input
Input
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst
mode, causes starting address to be latched at the next active clock edge.
AVD#
When high, device ignores address inputs.
RESET#
WP#
Input
Input
Hardware Reset. Low = device resets and returns to reading array data.
Write Protect. At VIL, disables program and erase functions in the four outermost sectors.
Should be at VIH for all other conditions.
Acceleration Input. At VHH, accelerates programming; automatically places device in
unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for
all other conditions.
ACC
RFU
Input
Reserved
Reserved for future use (see MCP look-ahead pinout for use with MCP).
January 25, 2005 S29WS-N_00_G0
S29WS-N MirrorBit™ Flash Family
7
A d v a n c e I n f o r m a t i o n
3 Block Diagram
DQ15–DQ0
V
V
CC
SS
IO
RDY
Buffer
RDY
V
Input/Output
Buffers
Erase Voltage
Generator
WE#
RESET#
WP#
State
Control
ACC
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
CE#
OE#
Y-Decoder
Y-Gating
VCC
Detector
Timer
Cell Matrix
X-Decoder
Burst
State
Control
Burst
Address
Counter
AVD#
CLK
Amax–A0*
* WS256N: A23-A0
WS128N: A22-A0
WS064N: A21-A0
Figure 3.1. S29WS-N Block Diagram
8
S29WS-N MirrorBit™ Flash Family
S29WS-N_00_G0 January25,2005
A d v a n c e I n f o r m a t i o n
4 Physical Dimensions/Connection Diagrams
This section shows the I/O designations and package specifications for the S29WS-N.
4.1
Related Documents
The following documents contain information relating to the S29WS-N devices. Click on the title
or go to www.amd.com/flash (click on Technical Documentation) or www.fujitsu.com to download
the PDF file, or request a copy from your sales office.
Migration to the S29WS256N Family Application Note
Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits
4.2 Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning meth-
ods. The package and/or data integrity may be compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of time.
January 25, 2005 S29WS-N_00_G0
S29WS-N MirrorBit™ Flash Family
9
A d v a n c e I n f o r m a t i o n
84-Ball Fine-Pitch Ball Grid Array, 256 & 128 Mb
(Top View, Balls Facing Down,
MCP Compatible)
A10
NC
A1
NC
B2
B3
RFU
C3
B4
CLK
C4
B5
RFU
C5
B6
RFU
C6
B7
RFU
C7
B8
RFU
C8
B9
RFU
C9
AVD#
C2
WP#
D2
RFU
D9
A7
RFU
D4
ACC
D5
WE#
D6
A8
A11
D8
D3
A6
D7
A3
E2
A2
F2
A1
RFU
E4
RESET#
E5
RFU
E6
A19
E7
A12
E8
A15
E9
E3
Ball F6 is RFU on
128 Mb device.
A5
F3
A4
A18
F4
RDY
F5
A20
F6
A9
F7
A13
F8
A21
F9
A17
A10
A14
A22
RFU
A23
G2
A0
G3
G4
G7
G8
G9
G5
G6
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
CE#f1
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
J9
J2
J3
J4
DQ10
K4
J5
J6
J7
J8
RFU
DQ0
VCC
RFU
DQ12
DQ7
VSS
K2
K8
K3
K5
K7
K6
RFU
L6
K9
DQ14
DQ8
DQ2
DQ5
RFU
DQ11
RFU
L2
L3
L4
L5
L7
L8
L9
RFU
RFU
RFU
VCC
RFU
RFU
RFU
RFU
M10
NC
M1
NC
Figure 4.1. 84-ball Fine-Pitch Ball Grid Array (S29WS256N, S29WS128N)
10
S29WS-N MirrorBit™ Flash Family
S29WS-N_00_G0 January25,2005
A d v a n c e I n f o r m a t i o n
4.2.1 VBH084—84-ball Fine-Pitch Ball Grid Array, 8 x 11.6 mm
0.05
(2X)
C
D1
D
A
e
10
9
8
7
6
5
4
3
2
1
e
7
SE
E1
E
M
L
K
J
H
G
F
E
D
C
B
A
A1 CORNER
B
A1 CORNER
INDEX MARK
SD
7
6
0.05
(2X)
C
10
NXφb
φ 0.08
φ 0.15
M
M
C
TOP VIEW
C A
B
BOTTOM VIEW
0.10
C
A2
A
0.08
C
C
A1
SEATING PLANE
SIDE VIEW
NOTES:
PACKAGE
JEDEC
VBH 084
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
11.60 mm x 8.00 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
---
NOM
---
MAX
1.00
---
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
OVERALL THICKNESS
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.18
0.62
---
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
---
0.76
BODY THICKNESS
BODY SIZE
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
MD
ME
N
BALL FOOTPRINT
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
10
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
84
φb
0.33
---
0.43
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
e
0.80 BSC.
0.40 BSC.
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. NOT USED.
(A2-A9, B10-L10,
M2-M9, B1-L1)
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3339 \ 16-038.25b
Note: BSC is an ANSI standard for Basic Space Centering
Figure 4.2. VBH084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm MCP Compatible Package
January 25, 2005 S29WS-N_00_G0
S29WS-N MirrorBit™ Flash Family
11
A d v a n c e I n f o r m a t i o n
80-ball Fine-Pitch Ball Grid Array, 64 Mb
(Top View, Balls Facing Down,
MCP Compatible)
A1
A2
RFU
B2
A3
CLK
B3
A4
RFU
B4
A5
RFU
B5
A6
RFU
B6
A7
RFU
B7
A8
RFU
B8
AVD#
B1
WP#
C1
RFU
C8
A7
RFU
C3
ACC
C4
WE#
C5
A8
A11
C7
C2
C6
A3
D1
A2
E1
A1
A6
RFU
D3
RESET#
D4
RFU
D5
A19
D6
A12
D7
A15
D8
D2
A5
E2
A4
A18
E3
RDY
E4
A20
E5
A9
E6
A13
E7
A21
E8
A17
A10
A14
RFU
RFU
RFU
F1
A0
F2
F3
F6
F7
F8
F4
F5
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
G1
G2
G3
G4
G5
G6
G7
G8
CE#f1
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
H8
H1
H2
H3
DQ10
J3
H4
H5
H6
H7
RFU
DQ0
VCC
RFU
DQ12
DQ7
VSS
J1
J7
J2
J4
J6
J5
RFU
K5
J8
DQ14
DQ8
DQ2
DQ5
RFU
DQ11
RFU
K1
K2
K3
K4
K6
K7
K8
RFU
RFU
RFU
VCC
RFU
RFU
RFU
RFU
Figure 4.3. 80-ball Fine-Pitch Ball Grid Array (S29WS064N)
12
S29WS-N MirrorBit™ Flash Family
S29WS-N_00_G0 January25,2005
A d v a n c e I n f o r m a t i o n
4.2.2 TLC080—80-ball Fine-Pitch Ball Grid Array, 7 x 9 mm
D1
A
D
eD
0.15
(2X)
C
8
7
SE
7
6
5
4
3
2
E
B
E1
eE
1
K
J
H
G
F
E
D
C
B
A
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
A2
A
C
C
A1
SIDE VIEW
6
80X
b
0.15
0.08
M
M
C
C
A
B
NOTES:
PACKAGE
JEDEC
TLC 080
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
9.00 mm x 7.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
9.00 BSC.
7.00 BSC.
7.20 BSC.
5.60 BSC.
10
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
8
80
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3430 \ 16-038.22 \ 10.15.04
Note: BSC is an ANSI standard for Basic Space Centering
Figure 4.4. TLC080—80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm MCP Compatible Package
January 25, 2005 S29WS-N_00_G0
S29WS-N MirrorBit™ Flash Family
13
A d v a n c e I n f o r m a t i o n
4.3 MCP Look-ahead Connection Diagram
Figure 4.5 shows a migration path from the S29WS-N to higher densities and the option to include
additional die within a single package. Spansion LLC provides this standard look-ahead connection
diagram that supports
NOR Flash and SRAM densities up to 4 Gigabits
NOR Flash and pSRAM densities up to 4 Gigabits
NOR Flash and pSRAM and data storage densities up to 4 Gigabits
The following multi-chip package (MCP) data sheet(s) are based on the S29WS-N. Refer to these
documents for input/output descriptions for each product:
Publication Number S71WS256_512NC0.
The physical package outline may vary between connection diagrams and densities. The connec-
tion diagram for any MCP, however, is a subset of the pinout in Figure 4.5.
In some cases, outrigger balls may exist in locations outside the grid shown. These outrigger balls
are reserved; do not connect them to any other signal.
For further information about the MCP look-ahead pinout, refer to the Design-In Scalable Wireless
Solutions with Spansion Products application note, available on the web or through an AMD or
Fujitsu sales office.
14
S29WS-N MirrorBit™ Flash Family
S29WS-N_00_G0 January25,2005
A d v a n c e I n f o r m a t i o n
Legend:
A9
NC
A2
NC
A10
NC
A1
NC
Shared
or NC (not connected)
B9
NC
B1
NC
B2
NC
B10
NC
Data-storage Only
Flash Shared Only
1st Flash Only
2nd Flash Only
1st RAM Only
2nd RAM Only
RAM Shared Only
DoC Only
C4
C5
C6
C7
C8
C9
C2
C3
AVD#
VSSds
CLK
CE#f2
VCCds RESET#ds CLKds RY/BY#ds
D4
D2
D3
A7
D5
D6
D7
A8
D8
D9
WP#
LB#s
WP/ACC
WE#
A11
CE1#ds
E2
A3
E3
A6
E4
E5
E6
E7
E8
E9
UB#s RESET#f CE2s1
A19
A12
A15
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
A18
RDY
A20
A13
A21
G2
A1
G3
A4
G4
GG55
G6
G7
G8
G9
A17
CE1#s2
A23
A10
A14
A22
H2
A0
H3
H4
HH55
H6
H7
H8
H9
VSS
DQ1
VCCs2
CE2s2
DQ6
A24
A16
J2
J3
J4
J5
J6
J7
J8
J2
DQ9
DQ3
DQ4
DQ13
DQ15
CREs
CE#f1
OE#
K2
K3
K4
KK55
K6
K7
K8
K9
DQ12
VSS
CE1#s1
DQ0
DQ10
VCCf
VCCs1
DQ7
L4
L5
L6
L7
L8
L9
L2
L4
DQ2
DQ11
A25
DQ5
DQ14
LOCK
or WP#/ACCds
VCCnds
DQ8
M2
M3
M4
M5
M6
M7
M8
NC
M9
DNU
NC or ds
A27
A26
VSSnds
VCCf
CE2#ds VCCQs1
or VCCQds
N9
NC
N1
NC
N2
NC
N10
NC
P1
P9
P2
P10
NC
NC
NC
NC
Figure 4.5. MCP Look-ahead Diagram
January 25, 2005 S29WS-N_00_G0
S29WS-N MirrorBit™ Flash Family
15
A d v a n c e I n f o r m a t i o n
5 Additional Resources
Visit www.amd.com and www.fujitsu.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices
Understanding Burst Mode Flash Memory Devices
Simultaneous Read/Write vs. Erase Suspend/Resume
MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read
Design-In Scalable Wireless Solutions with Spansion Products
Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
Spansion low-level drivers
Enhanced Flash drivers
Flash file system
CAD Modeling Support
VHDL and Verilog
IBIS
ORCAD
Technical Support
Contact your local sales office or contact Spansion LLC directly for additional technical support:
Email
US and Canada: HW.support@amd.com
Asia Pacific: asia.support@amd.com
Europe, Middle East, and Africa
Japan: http://edevice.fujitsu.com/jp/support/tech/#b7
Frequently Asked Questions (FAQ)
http://ask.amd.com/
http://edevice.fujitsu.com/jp/support/tech/#b7
Phone
US: (408) 749-5703
Japan (03) 5322-3324
Spansion LLC Locations
915 DeGuigne Drive, P.O. Box 3453
Sunnyvale, CA 94088-3453, USA
Telephone: 408-962-2500 or
1-866-SPANSION
Spansion Japan Limited
4-33-4 Nishi Shinjuku, Shinjuku-ku
Tokyo, 160-0023
Telephone: +81-3-5302-2200
Facsimile: +81-3-5302-2674
http://www.spansion.com
16
S29WS-N_00_G0 January 25, 2005
A d v a n c e I n f o r m a t i o n
6 Product Overview
The S29WS-N family consists of 256, 128 and 64Mbit, 1.8 volts-only, simultaneous read/write
burst mode Flash device optimized for today’s wireless designs that demand a large storage array,
rich functionality, and low power consumption.
These devices are organized in 16, 8 or 4 Mwords of 16 bits each and are capable of continuous,
synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap
around. These products also offer single word programming or a 32-word buffer for programming
with program/erase and suspend functionality. Additional features include:
Advanced Sector Protection methods for protecting sectors as required
256 words of Secured Silicon area for storing customer and factory secured information.
The Secured Silicon Sector is One Time Programmable.
6.1
Memory Map
The S29WS256/128/064N Mbit devices consist of 16 banks organized as shown in Tables 6.1–6.3.
Table 6.1. S29WS256N Sector & Memory Address Map
Bank
Size
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank
Address Range
Notes
SA000
000000h–003FFFh
SA001
004000h–007FFFh
Contains four smaller sectors at
bottom of addressable memory.
4
32
2 MB
0
SA002
008000h–00BFFFh
SA003
00C000h–00FFFFh
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
15
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
SA004 to SA018
SA019 to SA034
SA035 to SA050
SA051 to SA066
SA067 to SA082
SA083 to SA098
SA099 to SA114
SA115 to SA130
SA131 to SA146
SA147 to SA162
SA163 to SA178
SA179 to SA194
SA195 to SA210
SA211 to SA226
SA227 to SA242
SA243 to SA257
SA258
010000h–01FFFFh to 0F0000h–0FFFFFh
100000h–10FFFFh to 1F0000h–1FFFFFh
200000h–20FFFFh to 2F0000h–2FFFFFh
300000h–30FFFFh to 3F0000h–3FFFFFh
400000h–40FFFFh to 4F0000h–4FFFFFh
500000h–50FFFFh to 5F0000h–5FFFFFh
600000h–60FFFFh to 6F0000h–6FFFFFh
700000h–70FFFFh to 7F0000h–7FFFFFh
800000h–80FFFFh to 8F0000h–8FFFFFh
900000h–90FFFFh to 9F0000h–9FFFFFh
A00000h–A0FFFFh to AF0000h–AFFFFFh
B00000h–B0FFFFh to BF0000h–BFFFFFh
C00000h–C0FFFFh to CF0000h–CFFFFFh
D00000h–D0FFFFh to DF0000h–DFFFFFh
E00000h–E0FFFFh to EF0000h–EFFFFFh
F00000h–F0FFFFh to FE0000h–FEFFFFh
FF0000h–FF3FFFh
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
1
2
3
4
5
6
All 128 KB sectors.
Pattern for sector address range
is xx0000h–xxFFFFh.
(see note)
7
8
9
10
11
12
13
14
2 MB
15
SA259
FF4000h–FF7FFFh
Contains four smaller sectors at
top of addressable memory.
4
32
SA260
FF8000h–FFBFFFh
SA261
FFC000h–FFFFFFh
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA005–SA017) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.
January 25, 2005 S29WS-N_00_G0
17
A d v a n c e I n f o r m a t i o n
Table 6.2. S29WS128N Sector & Memory Address Map
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank Size
Bank
Address Range
Notes
32
32
SA000
000000h–003FFFh
SA001
004000h–007FFFh
Contains four smaller sectors at
bottom of addressable memory.
4
1 MB
32
0
SA002
008000h–00BFFFh
32
SA003
00C000h–00FFFFh
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
7
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
32
SA004 to SA010
SA011 to SA018
SA019 to SA026
SA027 to SA034
SA035 to SA042
SA043 to SA050
SA051 to SA058
SA059 to SA066
SA067 to SA074
SA075 to SA082
SA083 to SA090
SA091 to SA098
SA099 to SA106
SA107 to SA114
SA115 to SA122
SA123 to SA129
SA130
010000h–01FFFFh to 070000h–07FFFFh
080000h–08FFFFh to 0F0000h–0FFFFFh
100000h–10FFFFh to 170000h–17FFFFh
180000h–18FFFFh to 1F0000h–1FFFFFh
200000h–20FFFFh to 270000h–27FFFFh
280000h–28FFFFh to 2F0000h–2FFFFFh
300000h–30FFFFh to 370000h–37FFFFh
380000h–38FFFFh to 3F0000h–3FFFFFh
400000h–40FFFFh to 470000h–47FFFFh
480000h–48FFFFh to 4F0000h–4FFFFFh
500000h–50FFFFh to 570000h–57FFFFh
580000h–58FFFFh to 5F0000h–5FFFFFh
600000h–60FFFFh to 670000h–67FFFFh
680000h–68FFFFh to 6F0000h–6FFFFFh
700000h–70FFFFh to 770000h–77FFFFh
780000h–78FFFFh to 7E0000h–7EFFFFh
7F0000h–7F3FFFh
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1
2
3
4
5
6
All 128 KB sectors.
Pattern for sector address range
is xx0000h–xxFFFFh.
(see note)
7
8
9
10
11
12
13
14
1 MB
32
15
SA131
7F4000h–7F7FFFh
Contains four smaller sectors at
top of addressable memory.
4
32
SA132
7F8000h–7FBFFFh
32
SA133
7FC000h–7FFFFFh
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA005–SA009) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.
18
S29WS-N_00_G0 January 25, 2005
A d v a n c e I n f o r m a t i o n
Table 6.3. S29WS064N Sector & Memory Address Map
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank Size
Bank
Address Range
000000h–003FFFh
Notes
SA000
SA001
004000h–007FFFh
Contains four smaller sectors at
bottom of addressable memory.
4
32
SA002
008000h–00BFFFh
0.5 MB
0
SA003
00C000h–00FFFFh
SA004
010000h–01FFFFh
3
128
SA005
020000h–02FFFFh
SA006
030000h–03FFFFh
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
4
4
4
4
4
4
4
4
4
4
4
4
4
4
128
128
128
128
128
128
128
128
128
128
128
128
128
128
1
2
SA007–SA010
SA011–SA014
SA015–SA018
SA019–SA022
SA023–SA026
SA027–SA030
SA031–SA034
SA035–SA038
SA039–SA042
SA043–SA046
SA047–SA050
SA051–SA054
SA055–SA058
SA059–SA062
SA063
040000h–04FFFFh to 070000h–07FFFFh
080000h–08FFFFh to 0B0000h–0BFFFFh
0C0000h–0CFFFFh to 0F0000h–0FFFFFh
100000h–10FFFFh to 130000h–13FFFFh
140000h–14FFFFh to 170000h–17FFFFh
180000h–18FFFFh to 1B0000h–1BFFFFh
1C0000h–1CFFFFh to 1F0000h–1FFFFFh
200000h–20FFFFh to 230000h–23FFFFh
240000h–24FFFFh to 270000h–27FFFFh
280000h–28FFFFh to 2B0000h–2BFFFFh
2C0000h–2CFFFFh to 2F0000h–2FFFFFh
300000h–30FFFFh to 330000h–33FFFFh
340000h–34FFFFh to 370000h–37FFFFh
380000h–38FFFFh to 3B0000h–3BFFFFh
3C0000h–3CFFFFh
3
4
5
6
All 128 KB sectors.
Pattern for sector address range is
xx0000h–xxFFFFh.
7
8
(see note)
9
10
11
12
13
14
3
128
SA064
3D0000h–3DFFFFh
SA065
3E0000h–3EFFFFh
0.5 MB
15
SA066
3F0000h–3F3FFFh
SA067
3F4000h–3F7FFFh
Contains four smaller sectors at top
of addressable memory.
4
32
SA068
3F8000h–3FBFFFh
SA069
3FC000h–3FFFFFh
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA008–SA009) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.
January 25, 2005 S29WS-N_00_G0
19
A d v a n c e I n f o r m a t i o n
7 Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshak-
ing, and reset features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and
data patterns into the command registers (see Tables 12.1 and 12.2). The command register itself
does not occupy any addressable memory location; rather, it is composed of latches that store
the commands, along with the address and data information needed to execute the command.
The contents of the register serve as input to the internal state machine and the state machine
outputs dictate the function of the device. Writing incorrect address and data values or writing
them in an improper sequence may place the device in an unknown state, in which case the sys-
tem must write the reset command to return the device to the reading array data mode.
7.1
Device Operation Table
The device must be setup appropriately for each operation. Table 7.1 describes the required state
of each control pin for any particular operation.
Table 7.1. Device Operations
Operation
CE#
L
OE#
L
WE#
Addresses
Addr In
Addr In
Addr In
Addr In
X
DQ15–0
Data Out
Data Out
I/O
RESET#
CLK
X
AVD#
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
H
H
L
H
H
H
H
H
L
L
L
X
L
L
L
H
X
Synchronous Write
L
H
L
I/O
Standby (CE#)
H
X
X
X
X
HIGH Z
HIGH Z
X
X
X
X
Hardware Reset
X
X
Burst Read Operations (Synchronous)
Load Starting Burst Address
L
L
X
L
H
H
Addr In
X
X
H
H
Advance Burst to next address with appropriate
Data presented on the Data Bus
Burst
Data Out
H
Terminate current Burst read cycle
H
X
X
X
H
H
X
X
HIGH Z
HIGH Z
H
L
X
X
Terminate current Burst read cycle via RESET#
X
Terminate current Burst read cycle and start new
Burst read cycle
L
X
H
Addr In
I/O
H
Legend: L = Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output.
7.2 Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data
is read from one memory location at a time. Addresses are presented to the device in random
order, and the propagation delay through the device causes the data on its outputs to arrive asyn-
chronously with the address on its inputs.
The device defaults to reading array data asynchronously after device power-up or hardware re-
set. Asynchronous read requires that the CLK signal remain at V during the entire memory read
IL
operation. To read data from the memory array, the system must first assert a valid address on
A
–A0, while driving AVD# and CE# to V . WE# must remain at V . The rising edge of AVD#
IL IH
max
latches the address. The OE# signal must be driven to V , once AVD# has been driven to V
.
IL
IH
20
S29WS-N_00_G0 January 25, 2005
A d v a n c e I n f o r m a t i o n
Data is output on A/DQ15-A/DQ0 pins after the access time (t ) has elapsed from the falling
OE
edge of OE#.
7.3
Synchronous (Burst) Read Mode &
Configuration Register
When a series of adjacent addresses needs to be read from the device (in order from lowest to
highest address), the synchronous (or burst read) mode can be used to significantly reduce the
overall time needed for the device to output array data. After an initial access time required for
the data from the first address location, subsequent data is output synchronized to a clock input
provided by the system.
The device offers both continuous and linear methods of burst read operation, which are dis-
cussed in subsections 7.3.3 and 7.3.4, and 7.3.5.
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the
configuration register must be set to enable the burst read mode. Other Configuration Register
settings include the number of wait states to insert before the initial word (t
) of each burst
IACC
access, the burst mode in which to operate, and when RDY indicates data is ready to be read.
Prior to entering the burst mode, the system should first determine the configuration register set-
tings (and read the current register settings if desired via the Read Configuration Register
command sequence), and then write the configuration register command sequence. See Section
7.3.6, Configuration Register, and Table 12.1, Memory Array Commands for further details.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(CR15 = 0)
Asynchronous Mode
(CR15 = 1)
Synchronous Read
Mode Only
Figure 7.1. Synchronous/Asynchronous State Diagram
The device outputs the initial word subject to the following operational conditions:
t
specification: the time from the rising edge of the first clock cycle after addresses
IACC
are latched to valid data on the device outputs.
configuration register setting CR13–CR11: the total number of clock cycles (wait states)
that occur before valid data appears on the device outputs. The effect is that t
lengthened.
is
IACC
January 25, 2005 S29WS-N_00_G0
21
A d v a n c e I n f o r m a t i o n
The device outputs subsequent words t
after the active edge of each successive clock cycle,
BACC
which also increments the internal address counter. The device outputs burst data at this rate sub-
ject to the following operational conditions:
starting address: whether the address is divisible by four (where A[1:0] is 00). A divisi-
ble-by-four address incurs the least number of additional wait states that occur after the
initial word. The number of additional wait states required increases for burst operations
in which the starting address is one, two, or three locations above the divisible-by-four
address (i.e., where A[1:0] is 01, 10, or 11).
boundary crossing: There is a boundary at every 128 words due to the internal architec-
ture of the device. One additional wait state must be inserted when crossing this boundary
if the memory bus is operating at a high clock frequency. Please refer to the tables below.
clock frequency: the speed at which the device is expected to burst data. Higher speeds
require additional wait states after the initial word for proper operation.
In all cases, with or without latency, the RDY output indicates when the next data is available to
be read.
Tables 7.2-7.6 reflect wait states required for S29WS256/128/064N devices. Refer to the “Con-
figuration Register” table (CR11 - CR14) and timing diagrams for more details.
Table 7.2. Address Latency (S29WS256N)
Word
Wait States
x ws
Cycle
D4
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
x ws
1 ws
1 ws
1 ws
D4
x ws
D3
1 ws
1 ws
D4
x ws
1 ws
D4
Table 7.3. Address Latency (S29WS128N/S29WS064N)
Word
Wait States
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
Cycle
D4
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
1 ws
1 ws
1 ws
D4
D3
1 ws
1 ws
D4
1 ws
D4
Table 7.4. Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz)
Word
Wait States
7, 6 ws
Cycle
1 ws
1 ws
1 ws
1 ws
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
7, 6 ws
1 ws
1 ws
1 ws
7, 6 ws
D3
1 ws
1 ws
7, 6 ws
1 ws
Table 7.5. Address/Boundary Crossing Latency (S29WS256N @ 54MHz)
Word
Wait States
5 ws
Cycle
D4
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
5 ws
1 ws
1 ws
1 ws
D4
5 ws
D3
1 ws
1 ws
D4
5 ws
1 ws
D4
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A d v a n c e I n f o r m a t i o n
Table 7.6. Address/Boundary Crossing Latency (S29WS128N/S29WS064N)
Word
Wait States
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
Cycle
1 ws
1 ws
1 ws
1 ws
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
1 ws
1 ws
1 ws
D3
1 ws
1 ws
1 ws
Note: Setup Configuration Register parameters
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Set Configuration Register
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
Command Cycle
CR = Configuration Register Bits CR15-CR0
Load Initial Address
Address = RA
RA = Read Address
Read Initial Data
RD = DQ[15:0]
RD = Read Data
Wait X Clocks:
Refer to the Latency tables.
Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
Read Next Data
RD = DQ[15:0]
No
Delay X Clocks
Crossing
Boundary?
No
End of Data?
Yes
Yes
Completed
Figure 7.2. Synchronous Read
7.3.3 Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting
address given and then wrap around to address 000000h when it reaches the highest addressable
memory location. The burst read mode continues until the system drives CE# high, or RESET=
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A d v a n c e I n f o r m a t i o n
V . Continuous burst mode can also be aborted by asserting AVD# low and providing a new ad-
IL
dress to the device.
If the address being read crosses a 128-word line boundary (as mentioned above) and the sub-
sequent word line is not being programmed or erased, additional latency cycles are required as
reflected by the configuration register table (Table 7.8).
If the address crosses a bank boundary while the subsequent bank is programming or erasing,
the device provides read status information and the clock is ignored. Upon completion of status
read or program or erase operation, the host can restart a burst read operation using a new ad-
dress and AVD# pulse.
7.3.4 8-, 16-, 32-Word Linear Burst Read with Wrap Around
In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from con-
secutive addresses that are determined by the group within which the starting address falls. The
groups are sized according to the number of words read in a single burst sequence for a given
mode (see Table 7.7).
For example, if the starting address in the 8-word mode is 3Ch, the address range to be read
would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device
outputs all words in that burst address group until all word are read, regardless of where the start-
ing address occurs in the address group, and then terminates the burst read.
In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on
the starting address provided to the device, then wrap back to the first address in the selected
address group.
Note that in this mode the address pointer does not cross the boundary that occurs every 128
words; thus, no additional wait states are inserted due to boundary crossing.
Table 7.7. Burst Address Groups
Mode
Group Size
8 words
Group Address Ranges
0-7h, 8-Fh, 10-17h,...
0-Fh, 10-1Fh, 20-2Fh,...
00-1Fh, 20-3Fh, 40-5Fh,...
8-word
16-word
32-word
16 words
32 words
7.3.5 8-, 16-, 32-Word Linear Burst without Wrap Around
If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word
burst executes up to the maximum memory address of the selected number of words. The burst
stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected
group.
For example, if the starting address in the 8- word mode is 3Ch, the address range to be read
would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around
is not enabled. The next address to be read requires a new address and AVD# pulse. Note that
in this burst read mode, the address pointer may cross the boundary that occurs every 128 words,
which will incur the additional boundary crossing wait state.
7.3.6 Configuration Register
The configuration register sets various operational parameters associated with burst mode. Upon
power-up or hardware reset, the device defaults to the asynchronous read mode, and the config-
uration register settings are in their default state. The host system should determine the proper
settings for the entire configuration register, and then execute the Set Configuration Register
command sequence, before attempting burst operations. The configuration register is not reset
after deasserting CE#. The Configuration Register can also be read using a command sequence
(see Table 12.1). The following list describes the register settings.
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A d v a n c e I n f o r m a t i o n
Table 7.8. Configuration Register
CR Bit
Function
Settings (Binary)
Set Device Read
Mode
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Read Mode (default) Enabled
CR15
54 MHz
66 Mhz
80 MHz
S29WS064N
S29WS128N
N/A
N/A
N/A
Default value is "0"
CR14
Boundary Crossing
0 = No extra boundary crossing latency
1 = With extra boundary crossing latency (default)
Must be set to “1” greater than 54 MHz.
S29WS256N
0
0
1
1
1
1
S29WS064N
S29WS128N
011 = Data valid on 5th active CLK edge after addresses
CR13
CR12
CR11
latched
100 = Data valid on 6th active CLK edge after addresses
latched
S29WS256N
S29WS064N
S29WS128N
101 = Data valid on 7th active CLK edge after addresses
latched (default)
Programmable
Wait State
1
1
0
0
0
1
110 = Reserved
111 = Reserved
S29WS256N
Inserts wait states before initial data is available. Setting
greater number of wait states before initial data reduces
latency after initial data.
S29WS064N
S29WS128N
(Notes 1, 2)
S29WS256N
0 = RDY signal active low
CR10
CR9
RDY Polarity
Reserved
1 = RDY signal active high (default)
1 = default
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
When CR13-CR11 are set to 000, RDY is active with data
regardless of CR8 setting.
CR8
RDY
CR7
CR6
CR5
CR4
Reserved
Reserved
Reserved
Reserved
1 = default
1 = default
0 = default
0 = default
0 = No Wrap Around Burst
1 = Wrap Around Burst (default)
CR3
Burst Wrap Around
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
CR2
CR1
CR0
Burst Length
Notes:
1. Refer to Tables 7.2 - 7.6 for wait states requirements.
2. Refer to Synchronous Burst Read timing diagrams
3. Configuration Register is in the default state upon power-up or hardware reset.
Reading the Configuration Table. The configuration register can be read with a four-cycle com-
mand sequence. See Table 12.1 for sequence details. Once the data has been read from the
configuration register, a software reset command is required to set the device into the correct
state.
7.4 Autoselect
The Autoselect is used for manufacturer ID, Device identification, and sector protection informa-
tion. This mode is primarily intended for programming equipment to automatically match a device
with its corresponding programming algorithm. The Autoselect codes can also be accessed in-sys-
tem. When verifying sector protection, the sector address must appear on the appropriate highest
order address bits (see Table 7.9). The remaining address bits are don't care. The most significant
four bits of the address during the third write cycle selects the bank from which the Autoselect
codes are read by the host. All other banks can be accessed normally for data read without exiting
the Autoselect mode.
To access the Autoselect codes, the host system must issue the Autoselect command.
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A d v a n c e I n f o r m a t i o n
The Autoselect command sequence may be written to an address within a bank that is
either in the read or erase-suspend-read mode.
The Autoselect command may not be written while the device is actively programming or
erasing. Autoselect does not support simultaneous operations or burst mode.
The system must write the reset command to return to the read mode (or erase-suspend-
read mode if the bank was previously in Erase Suspend).
See Table 12.1 for command sequence details.
Table 7.9. Autoselect Addresses
Description
Manufacturer ID
Device ID, Word 1
Address
Read Data
(BA) + 00h 0001h
(BA) + 01h 227Eh
2230 (WS256N)
Device ID, Word 2
Device ID, Word 3
(BA) + 0Eh 2231 (WS128N)
2232 (WS064N)
(BA) + 0Fh 2200
DQ15 - DQ8 = Reserved
DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked
DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked
DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake
DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and
Bottom Boot Sectors. 01, 10, 11 = Reserved
Indicator Bits
(See Note)
(BA) + 03h
DQ2 = Reserved
DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option),
0 = Locked (default)
DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed,
0 = Erase disabled
Sector Block Lock/
Unlock
(SA) + 02h 0001h = Locked, 0000h = Unlocked
Note: For WS128N and WS064, DQ1 and DQ0 are reserved.
Software Functions and Sample Code
Table 7.10. Autoselect Entry
(LLD Function = lld_AutoselectEntryCmd)
Cycle
Operation
Write
Byte Address
BAxAAAh
BAx555h
Word Address
BAx555h
Data
Unlock Cycle 1
Unlock Cycle 2
Autoselect Command
0x00AAh
0x0055h
0x0090h
Write
BAx2AAh
Write
BAxAAAh
BAx555h
Table 7.11. Autoselect Exit
(LLD Function = lld_AutoselectExitCmd)
Cycle
Operation
Write
Byte Address
Word Address
base + XXXh
Data
Unlock Cycle 1
base + XXXh
0x00F0h
Notes:
1. Any offset within the device works.
2. BA = Bank Address. The bank address is required.
3. base = base address.
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The following is a C source code example of using the autoselect function to read the manu-
facturer ID. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com
and www.fujitsu.com) for general information on Spansion Flash memory software develop-
ment guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */
/* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
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A d v a n c e I n f o r m a t i o n
7.5 Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are
described in detail in the following sections. However, prior to any programming and or erase op-
eration, devices must be setup appropriately as outlined in the configuration register (Table 7.8).
For any program and or erase operations, including writing command sequences, the system
must drive AVD# and CE# to V , and OE# to V when providing an address to the device, and
IL
IH
drive WE# and CE# to V , and OE# to V when writing commands or programming data.
IL
IH
Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st
rising edge of WE# or CE#.
Note the following:
When the Embedded Program algorithm is complete, the device returns to the read
mode.
The system can determine the status of the program operation by using DQ7 or DQ6.
Refer to the Write Operation Status section for information on these status bits.
A “0” cannot be programmed back to a “1.” Attempting to do so causes the device to set
DQ5 = 1 (halting any further operation and requiring a reset command). A succeeding
read shows that the data is still “0.” Only erase operations can convert a “0” to a “1.”
Any commands written to the device during the Embedded Program Algorithm are ig-
nored except the Program Suspend command.
Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program op-
eration is in progress.
A hardware reset immediately terminates the program operation and the program com-
mand sequence should be reinitiated once the device has returned to the read mode, to
ensure data integrity.
Programming is allowed in any sequence and across sector boundaries for single word
programming operation.
7.5.1. Single Word Programming
Single word programming mode is the simplest method of programming. In this mode, four Flash
command write cycles are used to program an individual Flash address. The data for this pro-
gramming operation could be 8-, 16- or 32-bits wide. While this method is supported by all
Spansion devices, in general it is not recommended for devices that support Write Buffer Pro-
gramming. See Table 12.1 for the required bus cycles and Figure 7.3 for the flowchart.
When the Embedded Program algorithm is complete, the device then returns to the read mode
and addresses are no longer latched. The system can determine the status of the program oper-
ation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these
status bits.
During programming, any command (except the Suspend Program command) is ignored.
The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program
operation is in progress.
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A d v a n c e I n f o r m a t i o n
A hardware reset immediately terminates the program operation. The program command
sequence should be reinitiated once the device has returned to the read mode, to ensure
data integrity.
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Program Command:
Address 555h, Data A0h
Setup Command
Program Address (PA),
Program Data (PD)
Program Data to Address:
PA, PD
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Polling Status
= Busy?
No
Yes
Polling Status
= Done?
Error condition
(Exceeded Timing Limits)
No
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
Figure 7.3. Single Word Program
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A d v a n c e I n f o r m a t i o n
Software Functions and Sample Code
Table 7.12. Single Word Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Word Address
Data
00AAh
Unlock Cycle 1
Unlock Cycle 2
Program Setup
Write
0055h
Write
00A0h
Program
Write
Data Word
Note: Base = Base Address.
The following is a C source code example of using the single word program function. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Program Command
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x00A0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write program setup command
/* write data to be programmed
*/
*/
*/
*/
*( (UINT16 *)pa )
= data;
/* Poll for program completion */
7.5.2 Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one program-
ming operation. This results in a faster effective word programming time than the standard
“word” programming algorithms. The Write Buffer Programming command sequence is initiated
by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer
Load command written at the Sector Address in which programming occurs. At this point, the sys-
tem writes the number of “word locations minus 1” that are loaded into the page buffer at the
Sector Address in which programming occurs. This tells the device how many write buffer ad-
dresses are loaded with data and therefore when to expect the “Program Buffer to Flash” confirm
command. The number of locations to program cannot exceed the size of the write buffer or the
operation aborts. (Number loaded = the number of locations to program minus 1. For example,
if the system programs 6 address locations, then 05h should be written to the device.)
The system then writes the starting address/data combination. This starting address is the first
address/data pair to be programmed, and selects the “write-buffer-page” address. All subsequent
address/data pairs must fall within the elected-write-buffer-page.
The “write-buffer-page” is selected by using the addresses A
- A5.
MAX
The “write-buffer-page” addresses must be the same for all address/data pairs loaded into the
write buffer. (This means Write Buffer Programming cannot be performed across multiple “write-
buffer-pages.” This also means that Write Buffer Programming cannot be performed across mul-
tiple sectors. If the system attempts to load programming data outside of the selected “write-
buffer-page”, the operation ABORTs.)
After writing the Starting Address/Data pair, the system then writes the remaining address/data
pairs into the write buffer.
Note that if a Write Buffer address location is loaded multiple times, the “address/data pair”
counter is decremented for every data load operation. Also, the last data loaded at a location be-
fore the “Program Buffer to Flash” confirm command is programmed into the device. It is the
software's responsibility to comprehend ramifications of loading a write-buffer location more than
30
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A d v a n c e I n f o r m a t i o n
once. The counter decrements for each data load operation, NOT for each unique write-buffer-
address location. Once the specified number of write buffer locations have been loaded, the sys-
tem must then write the “Program Buffer to Flash” command at the Sector Address. Any other
address/data write combinations abort the Write Buffer Programming operation. The device goes
“busy.” The Data Bar polling techniques should be used while monitoring the last address location
loaded into the write buffer. This eliminates the need to store an address in memory because the
system can load the last address location, issue the program confirm command at the last loaded
address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1
should be monitored to determine the device status during Write Buffer Programming.
The write-buffer “embedded” programming operation can be suspended using the standard sus-
pend/resume commands. Upon successful completion of the Write Buffer Programming operation,
the device returns to READ mode.
The Write Buffer Programming Sequence is ABORTED under any of the following conditions:
Load a value that is greater than the page buffer size during the “Number of Locations to
Program” step.
Write to an address in a sector different than the one specified during the Write-Buffer-
Load command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the
“Starting Address” during the “write buffer data loading” stage of the operation.
Write data other than the “Confirm Command” after the specified number of “data load”
cycles.
The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the “last address location
loaded”), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation
was ABORTED. A “Write-to-Buffer-Abort reset” command sequence is required when using the
write buffer Programming features in Unlock Bypass mode. Note that the Secured Silicon sector,
autoselect, and CFI functions are unavailable when a program operation is in progress.
Write buffer programming is allowed in any sequence of memory (or address) locations. These
flash devices are capable of handling multiple write buffer programming operations on the same
write buffer address range without intervening erases.
Use of the write buffer is strongly recommended for programming when multiple words are to be
programmed. Write buffer programming is approximately eight times faster than programming
one word at a time.
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A d v a n c e I n f o r m a t i o n
Software Functions and Sample Code
Table 7.13. Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Word Address
Base + 555h
Base + 2AAh
Data
00AAh
1
2
3
4
Unlock
Write
0055h
Write Buffer Load Command
Write Word Count
Write
Program Address
Program Address
0025h
Write
Word Count (N–1)h
Number of words (N) loaded into the write buffer can be from 1 to 32 words.
5 to 36
Last
Load Buffer Word N
Write Buffer to Flash
Write
Write
Program Address, Word N
Sector Address
Word N
0029h
Notes:
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of
words written, the total number of cycles may be from 6 to 37.
3. For maximum efficiency, it is recommended that the write buffer be loaded with
the highest number of words (N words) possible.
The following is a C source code example of using the write buffer program function. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Write Buffer Programming Command
*/
/* NOTES: Write buffer programming limited to 16 words. */
/*
/*
/*
/*
All addresses to be written to the flash in
one operation must be within the same flash
page. A flash page begins at addresses
evenly divisible by 0x20.
*/
*/
*/
*/
UINT16 *src = source_of_data;
UINT16 *dst = destination_of_data;
/* address of source data
/* flash destination address
/* word count (minus 1)
/* write unlock cycle 1
/* write unlock cycle 2
*/
*/
*/
*/
*/
UINT16 wc
= words_to_program -1;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)sector_address )
*( (UINT16 *)sector_address )
= 0x0025;
= wc;
/* write write buffer load command */
/* write word count (minus 1) */
loop:
*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */
dst++;
src++;
/* increment destination pointer
/* increment source pointer
*/
*/
if (wc == 0) goto confirm
wc--;
goto loop;
/* done when word count equals zero */
/* decrement word count
/* do it again
*/
*/
confirm:
*( (UINT16 *)sector_address )
/* poll for completion */
= 0x0029;
/* write confirm command
*/
/* Example: Write Buffer Abort Reset */
*( (UINT16 *)addr + 0x555 ) = 0x00AA;
*( (UINT16 *)addr + 0x2AA ) = 0x0055;
*( (UINT16 *)addr + 0x555 ) = 0x00F0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write buffer abort reset
*/
*/
*/
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A d v a n c e I n f o r m a t i o n
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Issue
Write Buffer Load Command:
Address 555h, Data 25h
Load Word Count to Program
Program Data to Address:
SA = wc
wc = number of words – 1
Yes
Confirm command:
wc = 0?
No
SA 29h
Wait 4 µs
Write Next Word,
Decrement wc:
PA data , wc = wc – 1
No
Write Buffer
Abort Desired?
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Write to a Different
Sector Address to Cause
Write Buffer Abort
Yes
Polling Status
= Done?
No
Error?
Yes
No
Yes
Write Buffer
Abort?
No
RESET. Issue Write Buffer
Abort Reset Command
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
Figure 7.4. Write Buffer Programming Operation
7.5.3 Sector Erase
The sector erase function erases one or more sectors in the memory array. (See Table 12.1,
Memory Array Commands; and Figure 7.5, Sector Erase Operation.) The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs
and verifies the entire memory for an all zero data pattern prior to electrical erase. After a suc-
cessful sector erase, all locations within the erased sector contain FFFFh. The system is not
required to provide any controls or timings during these operations.
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A d v a n c e I n f o r m a t i o n
After the command sequence is written, a sector erase time-out of no less than t
occurs. Dur-
SEA
ing the time-out period, additional sector addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any sequence, and the number of sectors may be
from one sector to all sectors. The time between these additional cycles must be less than t
.
SEA
Any sector erase address and command following the exceeded time-out (t
) may or may not
SEA
be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period
resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase
timer has timed out (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the
rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and ad-
dresses are no longer latched. Note that while the Embedded Erase operation is in progress, the
system can read data from the non-erasing banks. The system can determine the status of the
erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to “Write Operation Sta-
tus” for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. However, note that a hardware reset immediately terminates the erase
operation. If that occurs, the sector erase command sequence should be reinitiated once that
bank has returned to reading array data, to ensure data integrity.
Figure 7.5 illustrates the algorithm for the erase operation. Refer to the “Erase/Program Opera-
tions” section for parameters and timing diagrams.
34
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Software Functions and Sample Code
Table 7.14. Sector Erase
(LLD Function = lld_SectorEraseCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Base + AAAh
Base + 554h
Sector Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Sector Address
Data
1
2
3
4
5
6
00AAh
0055h
0080h
00AAh
0055h
0030h
Unlock
Write
Setup Command
Unlock
Write
Write
Unlock
Write
Sector Erase Command
Write
Unlimited additional sectors may be selected for erase; command(s) must be written within t
.
SEA
The following is a C source code example of using the sector erase function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Sector Erase Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
*( (UINT16 *)sector_address )
= 0x0030;
/* write sector erase command
*/
January 25, 2005 S29WS-N_00_G0
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A d v a n c e I n f o r m a t i o n
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Sector Erase Cycles:
Address 555h, Data 80h
Address 555h, Data AAh
Address 2AAh, Data 55h
Sector Address, Data 30h
Command Cycle 1
Command Cycle 2
Command Cycle 3
Specify first sector for erasure
Select
Additional
Sectors?
No
Yes
Write Additional
Sector Addresses
• Each additional cycle must be written within tSEA timeout
• Timeout resets after each additional cycle is written
• The host system may monitor DQ3 or wait tSEA to ensure
acceptance of erase commands
Yes
Last Sector
Selected?
No
• No limit on number of sectors
Poll DQ3.
DQ3 = 1?
• Commands other than Erase Suspend or selecting
additional sectors for erasure during timeout reset device
to reading array data
No
Yes
Wait 4 µs
Perform Write Operation
Status Algorithm
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
(see Figure 7.6)
Yes
Done?
No
No
Error condition (Exceeded Timing Limits)
DQ5 = 1?
Yes
PASS. Device returns
to reading array.
FAIL. Write reset command
to return to reading array.
Notes:
1. See Table 12.1 for erase command sequence.
2. See the section on DQ3 for information on the sector erase timeout.
Figure 7.5. Sector Erase Operation
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7.5.4 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 12.1. These commands invoke the
Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all
zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip
contain FFFFh. The system is not required to provide any controls or timings during these oper-
ations. The “Command Definition” section in the appendix shows the address and data
requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7 or DQ6/DQ2. Refer to “Write Operation Status” for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.
Software Functions and Sample Code
Table 7.15. Chip Erase
(LLD Function = lld_ChipEraseCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Base + 555h
Data
1
2
3
4
5
6
00AAh
0055h
0080h
00AAh
0055h
0010h
Unlock
Write
Setup Command
Unlock
Write
Write
Unlock
Write
Chip Erase Command
Write
The following is a C source code example of using the chip erase function. Refer to the Span-
sion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for
general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x000 ) = 0x0010;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
/* write chip erase command
*/
7.5.5 Erase Suspend/Erase Resume Commands
When the Erase Suspend command is written during the sector erase time-out, the device imme-
diately terminates the time-out period and suspends the erase operation. The Erase Suspend
command allows the system to interrupt a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. The bank address is required when writing
this command. This command is valid only during the sector erase operation, including the min-
imum t
time-out period during the sector erase command sequence. The Erase Suspend
SEA
command is ignored if written during the chip erase operation.
When the Erase Suspend command is written after the t time-out period has expired and dur-
SEA
ing the sector erase operation, the device requires a maximum of t
suspend the erase operation.
(erase suspend latency) to
ESL
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A d v a n c e I n f o r m a t i o n
After the erase operation has been suspended, the bank enters the erase-suspend-read mode.
The system can read data from or program data to any sector not selected for erasure. (The de-
vice “erase suspends” all sectors selected for erasure.) Reading at any address within erase-
suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6,
and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table
7.24 for information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-
read mode. The system can determine the status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
In the erase-suspend-read mode, the system can also issue the Autoselect command sequence.
Refer to the “Write Buffer Programming Operation” section and the “Autoselect Command Se-
quence” section for details.
To resume the sector erase operation, the system must write the Erase Resume command. The
bank address of the erase-suspended bank is required when writing this command. Further writes
of the Resume command are ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Software Functions and Sample Code
Table 7.16. Erase Suspend
(LLD Function = lld_EraseSuspendCmd)
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
00B0h
The following is a C source code example of using the erase suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase suspend command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Table 7.17. Erase Resume
(LLD Function = lld_EraseResumeCmd)
Cycle
Operation
Byte Address
Word Address
Bank Address
Data
1
Write
Bank Address
0030h
The following is a C source code example of using the erase resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase resume command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x0030;
/* write resume command
*/
/* The flash needs adequate time in the resume state */
7.5.6 Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming op-
eration or a “Write to Buffer” programming operation so that data can read from any non-
suspended sector. When the Program Suspend command is written during a programming pro-
cess, the device halts the programming operation within t
(program suspend latency) and
PSL
updates the status bits. Addresses are “don't-cares” when writing the Program Suspend
command.
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After the programming operation has been suspended, the system can read array data from any
non-suspended sector. The Program Suspend command may also be issued during a program-
ming operation while an erase is suspended. In this case, data may be read from any addresses
not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector
area, then user must use the proper command sequences to enter and exit this region.
The system may also write the Autoselect command sequence when the device is in Program Sus-
pend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes
are not stored in the memory array. When the device exits the Autoselect mode, the device re-
verts to Program Suspend mode, and is ready for another valid operation. See “Autoselect
Command Sequence” for more information.
After the Program Resume command is written, the device reverts to programming. The system
can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard program operation. See “Write Operation Status” for more information.
The system must write the Program Resume command (address bits are “don't care”) to exit the
Program Suspend mode and continue the programming operation. Further writes of the Program
Resume command are ignored. Another Program Suspend command can be written after the de-
vice has resumed programming.
Software Functions and Sample Code
Table 7.18. Program Suspend
(LLD Function = lld_ProgramSuspendCmd)
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
00B0h
The following is a C source code example of using the program suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program suspend command */
*( (UINT16 *)base_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Table 7.19. Program Resume
(LLD Function = lld_ProgramResumeCmd)
Cycle
Operation
Byte Address
Word Address
Bank Address
Data
1
Write
Bank Address
0030h
The following is a C source code example of using the program resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program resume command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0030;
/* write resume command
*/
7.5.7 Accelerated Program/Chip Erase
Accelerated single word programming, write buffer programming, sector erase, and chip erase
operations are enabled through the ACC function. This method is faster than the standard chip
program and erase command sequences.
The accelerated chip program and erase functions must not be used more than 10 times
per sector. In addition, accelerated chip program and erase should be performed at room tem-
perature (25°C ±10°C).
January 25, 2005 S29WS-N_00_G0
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A d v a n c e I n f o r m a t i o n
If the system asserts V
on this input, the device automatically enters the aforementioned Un-
HH
lock Bypass mode and uses the higher voltage on the input to reduce the time required for
program and erase operations. The system can then use the Write Buffer Load command se-
quence provided by the Unlock Bypass mode. Note that if a “Write-to-Buffer-Abort Reset” is
required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used
to reset the device. Removing V
from the ACC input, upon completion of the embedded pro-
HH
gram or erase operation, returns the device to normal operation.
Sectors must be unlocked prior to raising ACC to V
.
HH
The ACC pin must not be at V
for operations other than accelerated programming and
HH
accelerated chip erase, or device damage may result.
The ACC pin must not be left floating or unconnected; inconsistent behavior of the device
may result.
ACC locks all sector if set to V ; ACC should be set to V for all other conditions.
IL IH
7.5.8 Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster word programming. Once the de-
vice enters the Unlock Bypass mode, only two write cycles are required to program data, instead
of the normal four cycles.
This mode dispenses with the initial two unlock cycles required in the standard program command
sequence, resulting in faster total programming time. The “Command Definition Summary” sec-
tion shows the requirements for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the bank address and the data 90h.
The second cycle need only contain the data 00h. The bank then returns to the read mode.
Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit
functions. Refer to the Spansion Low Level Driver User’s Guide (available soon on www.amd.com
and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
Table 7.20. Unlock Bypass Entry
(LLD Function = lld_UnlockBypassEntryCmd)
Cycle
Description
Unlock
Operation
Write
Write
Write
*/
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
1
2
3
00AAh
0055h
0020h
Unlock
Entry Command
/* Example: Unlock Bypass Entry Command
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)bank_addr + 0x555 ) = 0x0020;
/* write unlock cycle 1
/* write unlock cycle 2
/* write unlock bypass command
*/
*/
*/
/* At this point, programming only takes two write cycles.
/* Once you enter Unlock Bypass Mode, do a series of like
/* operations (programming or sector erase) and then exit
/* Unlock Bypass Mode before beginning a different type of
/* operations.
*/
*/
*/
*/
*/
Table 7.21. Unlock Bypass Program
(LLD Function = lld_UnlockBypassProgramCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
1
Program Setup Command
Write
Base + xxxh
Base +xxxh
00A0h
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A d v a n c e I n f o r m a t i o n
Table 7.21. Unlock Bypass Program
(LLD Function = lld_UnlockBypassProgramCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
2
Program Command
Write
Program Address
Program Address
Program Data
/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode! */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0;
/* write program setup command
/* write data to be programmed
*/
*/
*( (UINT16 *)pa )
= data;
*/
/* Poll until done or error.
/* If done and more to program, */
/* do above two cycles again. */
Table 7.22. Unlock Bypass Reset
(LLD Function = lld_UnlockBypassResetCmd)
Cycle
Description
Reset Cycle 1
Reset Cycle 2
Operation
Write
Byte Address
Base + xxxh
Base + xxxh
Word Address
Base +xxxh
Base +xxxh
Data
1
2
0090h
0000h
Write
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
7.5.9 Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The
following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an Em-
bedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command se-
quence. Note that the Data# Polling is valid only for the last word being programmed in the write-
buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other
than the last word to be programmed in the write-buffer-page returns false status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# polling on DQ7 is active for approxi-
mately t , then that bank returns to the read mode.
PSP
During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Embed-
ded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling
produces a “1” on DQ7. The system must provide an address within any of the sectors selected
for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately t , then the bank returns to the read mode.
ASP
If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7
at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asyn-
chronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when the system
samples the DQ7 output, it may read the status or valid data. Even if the device has completed
January 25, 2005 S29WS-N_00_G0
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A d v a n c e I n f o r m a t i o n
the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be
still invalid. Valid data on DQ7-D00 appears on successive read cycles.
See the following for more information: Table 7.24, Write Operation Status, shows the outputs
for Data# Polling on DQ7. Figure 7.6, Write Operation Status Flowchart, shows the Data# Polling
algorithm; and Figure 11.17, Data# Polling Timings (During Embedded Algorithm), shows the
Data# Polling timing diagram.
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A d v a n c e I n f o r m a t i o n
START
Read 1
(Note 6)
YES
Erase
Operation
Complete
DQ7=valid
data?
NO
YES
YES
Read 2
Read 3
Read 1
DQ5=1?
Read3=
valid data?
NO
NO
Read 2
Program
Operation
Failed
YES
Write Buffer
Programming?
YES
NO
Programming
Operation?
Read 3
NO
Device BUSY,
Re-Poll
(Note 3)
(Note 5)
(Note 1)
YES
(Note 1)
YES
DQ6
toggling?
DQ6
toggling?
DEVICE
ERROR
TIMEOUT
NO
(Note 4)
NO
YES
Read3
DQ1=1?
(Note 2)
YES
NO
Device BUSY,
Re-Poll
DQ2
toggling?
NO
Read 2
Read 3
Device BUSY,
Re-Poll
Erase
Device in
Erase/Suspend
Mode
Operation
Complete
Read3
DQ1=1
YES
Write Buffer
AND DQ7 ≠
Valid Data?
Operation
Failed
NO
Notes:
1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3) May be due to an attempt to program a 0 to 1. Use the RESET
command to exit operation.
Device BUSY,
Re-Poll
4) Write buffer error if DQ1 of last read =1.
5) Invalid state, use RESET command to exit operation.
6) Valid data is the data that is intended to be programmed or all 1's for
an erase operation.
7) Data polling algorithm valid for all operations except advanced sector
protection.
Figure 7.6. Write Operation Status Flowchart
January 25, 2005 S29WS-N_00_G0
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A d v a n c e I n f o r m a t i o n
DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algo-
rithm is in progress or complete, or whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of
the final WE# pulse in the command sequence (prior to the program or erase operation), and dur-
ing the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately t
[all sectors protected toggle time], then returns to reading array
ASP
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-
gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately t
program command sequence is written, then returns to reading array data.
after the
PAP
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-
ded Program Algorithm is complete.
See the following for additional information: Figure 7.6, Write Operation Status Flowchart; Figure
11.18, Toggle Bit Timings (During Embedded Algorithm), and Tables 7.23 and 7.24.
Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the
change in state.
DQ2: Toggle Bit II . The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a par-
ticular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether
that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse
in the command sequence. DQ2 toggles when the system reads at addresses within those sectors
that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 7.23 to compare
outputs for DQ2 and DQ6. See the following for additional information: Figure 7.6, the “DQ6: Tog-
gle Bit I” section, and Figures 11.17–11.20.
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A d v a n c e I n f o r m a t i o n
Table 7.23. DQ6 and DQ2 Indications
If device is
and the system reads
then DQ6
and DQ2
programming,
at any address,
toggles,
does not toggle.
at an address within a sector
selected for erasure,
toggles,
toggles,
also toggles.
does not toggle.
toggles.
actively erasing,
erase suspended,
at an address within sectors not
selected for erasure,
at an address within a sector
selected for erasure,
does not toggle,
returns array data. The system can
read from any sector not selected for
erasure.
at an address within sectors not
returns array data,
toggles,
selected for erasure,
programming in
erase suspend
at any address,
is not applicable.
Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit status,
it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typ-
ically, the system would note and store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erases operation. The system can
read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read
cycles, the system determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then deter-
mine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just
as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed
the program or erases operation. If it is still toggling, the device did not complete the operation
successfully, and the system must write the reset command to return to reading array data. The
remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5
has not gone high. The system may continue to monitor the toggle bit and DQ5 through succes-
sive read cycles, determining the status as described in the previous paragraph. Alternatively, it
may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation. Refer to Figure 7.6 for
more details.
DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or erase time has exceeded
a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that
the program or erase cycle was not successfully completed. The device may output a “1” on DQ5
if the system tries to program a “1” to a location that was previously programmed to “0.” Only an
erase operation can change a “0” back to a “1.” Under this condition, the device halts the opera-
tion, and when the timing limit has been exceeded, DQ5 produces a “1.”Under both these
conditions, the system must write the reset command to return to the read mode (or to the erase-
suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator. After writing a sector erase command sequence,
the system may read DQ3 to determine whether or not erasure has begun. (The sector erase
timer does not apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command. When the time-out
period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase
commands from the system can be assumed to be less than t
DQ3. See Sector Erase Command Sequence for more details.
, the system need not monitor
SEA
After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and
January 25, 2005 S29WS-N_00_G0
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A d v a n c e I n f o r m a t i o n
then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands
(except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device
accepts additional sector erase commands. To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to and following each sub-sequent sector erase
command. If DQ3 is high on the second status check, the last command might not have been
accepted. Table 7.24 shows the status of DQ3 relative to the other status bits.
DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted.
Under these conditions DQ1 produces a “1”. The system must issue the Write to Buffer Abort
Reset command sequence to return the device to reading array data. See Write Buffer Program-
ming Operation for more details.
Table 7.24. Write Operation Status
DQ7
DQ5
DQ2
DQ1
Status
(Note 2)
DQ6
Toggle
Toggle
INVALID
(Note 1)
DQ3
N/A
(Note 2)
(Note 4)
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
0
0
No toggle
Toggle
0
Standard
Mode
1
N/A
INVALID
INVALID
INVALID
INVALID
INVALID
Program
Suspend
Mode
Reading within Program Suspended Sector
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
Reading within Non-Program Suspended
Sector
(Note 3)
Data
1
Data
No toggle
Data
Data
0
Data
N/A
Data
Toggle
Data
Data
N/A
Erase
Suspended Sector
Erase-Suspend-
Erase
Suspend
Mode
Read
Non-Erase Suspended
Data
Data
Data
Data
Sector
Erase-Suspend-Program
BUSY State
DQ7#
DQ7#
DQ7#
DQ7#
Toggle
Toggle
Toggle
Toggle
0
0
1
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
Write to
Buffer
(Note 5)
Exceeded Timing Limits
ABORT State
0
1
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the
section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. Data are invalid for addresses in a Program Suspended sector.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming
indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
46
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7.6 Simultaneous Read/Write
The simultaneous read/write feature allows the host system to read data from one bank of mem-
ory while programming or erasing another bank of memory. An erase operation may also be
suspended to read from or program another location within the same bank (except the sector
being erased). Figure 11.24, Back-to-Back Read/Write Cycle Timings, shows how read and write
cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Character-
istics (CMOS Compatible) table for read-while-program and read-while-erase current
specification.
7.7
Writing Commands/Command Sequences
When the device is configured for Asynchronous read, only Asynchronous write operations are
allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device is able
to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address
latches are supported in the Synchronous programming mode. During a synchronous write oper-
ation, to write a command or command sequence (which includes programming data to the
device and erasing sectors of memory), the system must drive AVD# and CE# to V , and OE#
IL
to V when providing an address to the device, and drive WE# and CE# to V , and OE# to V
IH
IH
IL
when writing commands or data. During an asynchronous write operation, the system must drive
CE# and WE# to V and OE# to V when providing an address, command, and data. Addresses
IL
IH
are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of
WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device.
Tables 6.1–6.3 indicate the address space that each sector occupies. The device address space is
divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and
15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A “bank address” is the
set of address bits required to uniquely select a bank. Similarly, a “sector address” is the address
bits required to uniquely select a sector. I
in “DC Characteristics” represents the active current
CC2
specification for the write mode. “AC Characteristics-Synchronous” and “AC Characteristics-Asyn-
chronous” contain timing specification tables and timing diagrams for write operations.
7.8 Handshaking
The handshaking feature allows the host system to detect when data is ready to be read by simply
monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#.
When the device is configured to operate in synchronous mode, and OE# is low (active), the initial
word of burst data becomes available after either the falling or rising edge of the RDY pin (de-
pending on the setting for bit 10 in the Configuration Register). It is recommended that the host
system set CR13–CR11 in the Configuration Register to the appropriate number of wait states to
ensure optimal burst mode operation (see Table 7.8, Configuration Register).
Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same
time that data is ready, or one cycle before data is ready.
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A d v a n c e I n f o r m a t i o n
7.9 Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of t , the device immediately terminates any
RP
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data.
To ensure data integrity the operation that was interrupted should be reinitiated once the device
is ready to accept another command sequence.
When RESET# is held at V , the device draws CMOS standby current (I
). If RESET# is held
SS
CC4
at V , but not at V , the standby current is greater.
IL
SS
RESET# may be tied to the system reset circuitry which enables the system to read the boot-up
firmware from the Flash memory upon a system reset.
See Figures 11.5 and 11.12 for timing diagrams.
7.10 Software Reset
Software reset is part of the command set (see Table 12.1) that also returns the device to array
read mode and must be used for the following conditions:
1. to exit Autoselect mode
2. when DQ5 goes high during write status operation that indicates program or erase cycle
was not successfully completed
3. exit sector lock/unlock operation.
4. to return to erase-suspend-read mode if the device was previously in Erase Suspend
mode.
5. after any aborted operations
Software Functions and Sample Code
Table 7.25. Reset
(LLD Function = lld_ResetCmd)
Cycle
Operation
Byte Address
Word Address
Data
Reset Command
Write
Base + xxxh
Base + xxxh
00F0h
Note: Base = Base Address.
The following is a C source code example of using the reset function. Refer to the Spansion
Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general
information on Spansion Flash memory software development guidelines.
/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
The following are additional points to consider when using the reset command:
This command resets the banks to the read and address bits are ignored.
Reset commands are ignored once erasure has begun until the operation is complete.
Once programming begins, the device ignores reset commands until the operation is
complete
The reset command may be written between the cycles in a program command sequence
before programming begins (prior to the third cycle). This resets the bank to which the
system was writing to the read mode.
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If the program command sequence is written to a bank that is in the Erase Suspend
mode, writing the reset command returns that bank to the erase-suspend-read mode.
The reset command may be also written during an Autoselect command sequence.
If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the
reset command returns that bank to the erase-suspend-read mode.
If DQ1 goes high during a Write Buffer Programming operation, the system must write
the "Write to Buffer Abort Reset" command sequence to RESET the device to reading
array data. The standard RESET command does not work during this condition.
To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset
command sequence [see command table for details].
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8 Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase
operations in any or all sectors and can be implemented through software and/or hardware meth-
ods, which are independent of each other. This section describes the various methods of
protecting data stored in the memory array. An overview of these methods in shown in Figure 8.1.
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
ACC = V
IL
All sectors locked)
Persistent Method
Password Method
(
(DQ1)
(DQ2)
WP# = V
IL
(All boot
sectors locked)
64-bit Password
(One Time Protect)
1. Bit is volatile, and defaults to “1” on
reset.
PPB Lock Bit1,2,3
2. Programming to “0” locks all PPBs to
their current state.
0 = PPBs Locked
1 = PPBs Unlocked
3. Once programmed to “0”, requires
hardware reset to unlock.
Persistent
Protection Bit
(PPB)4,5
Dynamic
Protection Bit
(PPB)6,7,8
Memory Array
Sector 0
PPB 0
PPB 1
PPB 2
DYB 0
DYB 1
DYB 2
Sector 1
Sector 2
Sector N-2
Sector N-1
Sector N3
PPB N-2
PPB N-1
PPB N
DYB N-2
DYB N-1
DYB N
3. N = Highest Address Sector.
4. 0 = Sector Protected,
1 = Sector Unprotected.
6. 0 = Sector Protected,
1 = Sector Unprotected.
5. PPBs programmed individually,
but cleared collectively
7. Protect effective only if PPB Lock Bit
is unlocked and corresponding PPB
is “1” (unprotected).
8. Volatile Bits: defaults to user choice
upon power-up (see ordering
options).
Figure 8.1. Advanced Sector Protection/Unprotection
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8.1
Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied, and
all sectors are unprotected, unless otherwise chosen through the DYB ordering option (see Or-
dering Information). The device programmer or host system must then choose which sector
protection method to use. Programming (setting to “0”) any one of the following two one-time
programmable, non-volatile bits locks the part permanently in that mode:
Lock Register Persistent Protection Mode Lock Bit (DQ1)
Lock Register Password Protection Mode Lock Bit (DQ2)
Table 8.1. Lock Register
Device
DQ15-05
DQ4
DQ3
DQ2
DQ1
DQ0
Password
Protection
Mode Lock Bit
Persistent
Protection
Mode Lock Bit
Customer
SecSi Sector
Protection Bit
S29WS256N
1
1
1
DYB Lock Boot Bit
PPB One-Time
0 = sectors
power up
protected
Programmable Bit
Password
Protection
Mode Lock Bit
Persistent
Protection
Mode Lock Bit
S29WS128N/
S29WS064N
0 = All PPB erase
command disabled
SecSi Sector
Protection Bit
Undefined
1 = sectors
power up
unprotected
1 = All PPB Erase
command enabled
For programming lock register bits refer to Table 12.2.
Notes
1. If the password mode is chosen, the password must be programmed before setting the cor-
responding lock register bit.
2. After the Lock Register Bits Command Set Entry command sequence is written, reads and
writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this
mode.
3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation
aborts.
4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently
disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent
Mode Lock Bit is programmed, the Password Mode is permanently disabled.
After selecting a sector protection method, each sector can operate in any of the following three
states:
1. Constantly locked. The selected sectors are protected and can not be reprogrammed
unless PPB lock bit is cleared via a password, hardware reset, or power cycle.
2. Dynamically locked. The selected sectors are protected and can be altered via software
commands.
3. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Sections 8.2–8.6.
8.2 Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same en-
durances as the Flash memory. Preprogramming and verification prior to erasure are handled by
the device, and therefore do not require system monitoring.
Notes
1. Each PPB is individually programmed and all are erased in parallel.
2. While programming PPB for a sector, array data can be read from any other bank, ex-
cept Bank 0 (used for Data# Polling) and the bank in which sector PPB is being
programmed.
January 25, 2005 S29WS-N_00_G0
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A d v a n c e I n f o r m a t i o n
3. Entry command disables reads and writes for the bank selected.
4. Reads within that bank return the PPB status for that sector.
5. Reads from other banks are allowed while writes are not allowed.
6. All Reads must be performed using the Asynchronous mode.
7. The specific sector address (A23-A14 WS256N, A22-A14 WS128N, A21-A14 WS064N)
are written at the same time as the program command.
8. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and
times-out without programming or erasing the PPB.
9. There are no means for individually erasing a specific PPB and no specific sector address
is required for this operation.
10. Exit command must be issued after the execution which resets the device to read mode
and re-enables reads and writes for Bank 0
11. The programming state of the PPB for a given sector can be verified by writing a PPB
Status Read Command to the device as described by the flow chart shown in Figure 8.2.
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Enter PPB
Command Set.
Addr = BA
Program PPB Bit.
Addr = SA
Read Byte Twice
Addr = SA0
No
DQ6 =
Toggle?
Yes
No
DQ5 = 1?
Yes
Wait 500 µs
Read Byte Twice
Addr = SA0
No
Read Byte.
Addr = SA
DQ6 =
Toggle?
Yes
DQ0 =
'1' (Erase)
'0' (Pgm.)?
No
FAIL
Yes
Issue Reset
Command
PASS
Exit PPB
Command Set
Figure 8.2. PPB Program/Erase Algorithm
8.3 Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified.
DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared
(erased to “1”). By issuing the DYB Set or Clear command sequences, the DYBs are set (pro-
grammed to “0”) or cleared (erased to “1”), thus placing each sector in the protected or
unprotected state respectively. This feature allows software to easily protect sectors against in-
advertent changes yet does not prevent the easy removal of protection when changes are
needed.
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A d v a n c e I n f o r m a t i o n
Notes
1. The DYBs can be set (programmed to “0”) or cleared (erased to “1”) as often as needed.
When the parts are first shipped, the PPBs are cleared (erased to “1”) and upon power up or reset,
the DYBs can be set or cleared depending upon the ordering option chosen.
2. If the option to clear the DYBs after power up is chosen, (erased to “1”), then the sectors
may be modified depending upon the PPB state of that sector (see Table 8.2).
3. The sectors would be in the protected state If the option to set the DYBs after power up
is chosen (programmed to “0”).
4. It is possible to have sectors that are persistently locked with sectors that are left in the
dynamic state.
5. The DYB Set or Clear commands for the dynamic sectors signify protected or unpro-
tectedstate of the sectors respectively. However, if there is a need to change the status
of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit
must be cleared by either putting the device through a power-cycle, or hardware reset.
The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit
once again locks the PPBs, and the device operates normally again.
6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set com-
mand early in the boot code and protect the boot code by holding WP# = V . Note that
IL
the PPB and DYB bits have the same function when ACC = V
as they do when ACC
HH
=V
.
IH
8.4 Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed
to “0”), it locks all PPBs and when cleared (programmed to “1”), allows the PPBs to be changed.
There is only one PPB Lock Bit per device.
Notes
1. No software command sequence unlocks this bit unless the device is in the password
protection mode; only a hardware reset or a power-up clears this bit.
2. The PPB Lock Bit must be set (programmed to “0”) only after all PPBs are configured to
the desired settings.
8.5 Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector
Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition
to this password requirement, after power up and reset, the PPB Lock Bit is set “0” to maintain
the password mode of operation. Successful execution of the Password Unlock command by en-
tering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.
Notes
1. There is no special addressing order required for programming the password. Once the
Password is written and verified, the Password Mode Locking Bit must be set in order to
prevent access.
2. The Password Program Command is only capable of programming “0”s. Programming a
“1” after a cell is programmed as a “0” results in a time-out with the cell as a “0”.
3. The password is all “1”s when shipped from the factory.
4. All 64-bit password combinations are valid as a password.
5. There is no means to verify what the password is after it is set.
6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the
data bus and further password programming.
7. The Password Mode Lock Bit is not erasable.
8. The lower two address bits (A1–A0) are valid during the Password Read, Password Pro-
gram, and Password Unlock.
9. The exact password must be entered in order for the unlocking function to occur.
54
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A d v a n c e I n f o r m a t i o n
10. The Password Unlock command cannot be issued any faster than 1 µs at a time to pre-
vent a hacker from running through all the 64-bit combinations in an attempt to
correctly match a password.
11. Approximately 1 µs is required for unlocking the device after the valid 64-bit password
is given to the device.
12. Password verification is only allowed during the password programming operation.
13. All further commands to the password region are disabled and all operations are
ignored.
14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear
the PPB Lock Bit.
15. Entry command sequence must be issued prior to any of any operation and it disables
reads and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are
allowed.
16. If the user attempts to program or erase a protected sector, the device ignores the com-
mand and returns to read mode.
17. A program or erase command to a protected sector enables status polling and returns
to read mode without having modified the contents of the protected sector.
18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by
writing individual status read commands DYB Status, PPB Status, and PPB Lock Status
to the device.
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A d v a n c e I n f o r m a t i o n
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write
Enter Lock Register Command:
Address 555h, Data 40h
XXXh = Address don’t care
* Not on future devices
Program Lock Register Data
Address XXXh, Data A0h
Address 77h*, Data PD
Program Data (PD): See text for Lock Register
definitions
Caution: Lock register can only be progammed
once.
Wait 4 µs
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Done?
No
No
DQ5 = 1?
Yes
Error condition (Exceeded Timing Limits)
PASS. Write Lock Register
Exit Command:
FAIL. Write rest command
to return to reading array.
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
Figure 8.3. Lock Register Program Algorithm
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8.6 Advanced Sector Protection Software Examples
Table 8.2. Sector Protection Schemes
Unique Device PPB Lock Bit
0 = locked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
1 = unlocked
Sector Protection Status
Protected through PPB
Protected through PPB
Unprotected
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
x
x
1
0
x
x
0
1
Protected through DYB
Protected through PPB
Protected through PPB
Protected through DYB
Unprotected
Table 8.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the sta-
tus of the sector. In summary, if the PPB Lock Bit is locked (set to “0”), no changes to the PPBs
are allowed. The PPB Lock Bit can only be unlocked (reset to “1”) through a hardware reset or
power cycle. See also Figure 8.1 for an overview of the Advanced Sector Protection feature.
8.7 Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control:
When WP# is at V , the four outermost sectors are locked (device specific).
IL
When ACC is at V , all sectors are locked.
IL
There are additional methods by which intended or accidental erasure of any sectors can be pre-
vented via hardware means. The following subsections describes these methods:
8.7.1. WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors.
This function is provided by the WP# pin and overrides the previously discussed Sector Protec-
tion/Unprotection method.
If the system asserts V on the WP# pin, the device disables program and erase functions in the
IL
“outermost” boot sectors. The outermost boot sectors are the sectors containing both the lower
and upper set of sectors in a dual-boot-configured device.
If the system asserts V on the WP# pin, the device reverts to whether the boot sectors were
IH
last set to be protected or unprotected. That is, sector protection or unprotection for these sectors
depends on whether they were last protected or unprotected.
Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the
device may result.
The WP# pin must be held stable during a command sequence execution
8.7.2 ACC Method
This method is similar to above, except it protects all sectors. Once ACC input is set to V , all
IL
program and erase functions are disabled and hence all sectors are protected.
8.7.3 Low V
Write Inhibit
CC
When V is less than V
, the device does not accept any write cycles. This protects data during
LKO
CC
V
power-up and power-down.
CC
January 25, 2005 S29WS-N_00_G0
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A d v a n c e I n f o r m a t i o n
The command register and all internal program/erase circuits are disabled, and the device resets
to reading array data. Subsequent writes are ignored until V is greater than V
. The system
CC
LKO
must provide the proper signals to the control inputs to prevent unintentional writes when V is
CC
greater than V
.
LKO
8.7.4 Write Pulse “Glitch Protection”
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.7.5 Power-Up Write Inhibit
If WE# = CE# = RESET# = V and OE# = V during power up, the device does not accept com-
IL
IH
mands on the rising edge of WE#. The internal state machine is automatically reset to the read
mode on power-up.
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A d v a n c e I n f o r m a t i o n
9 Power Conservation Modes
9.1
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input. The device enters the CMOS standby mode
when the CE# and RESET# inputs are both held at V ± 0.2 V. The device requires standard
CC
access time (t ) for read access, before it is ready to read data. If the device is deselected during
CE
erasure or programming, the device draws active current until the operation is completed. I
“DC Characteristics” represents the standby current specification
in
CC3
9.2 Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous
mode. the device automatically enables this mode when addresses remain stable for t + 20
ACC
ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Stan-
dard address access timings provide new data when addresses are changed. While in sleep mode,
output data is latched and always available to the system. While in synchronous mode, the auto-
matic sleep mode is disabled. Note that a new burst operation is required to provide new data.
I
in “DC Characteristics” represents the automatic sleep mode current specification.
CC6
9.3 Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of t , the device immediately terminates any
RP
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once the
device is ready to accept another command sequence to ensure data integrity.
When RESET# is held at V ± 0.2 V, the device draws CMOS standby current (I
). If RESET#
SS
CC4
is held at V but not within V ± 0.2 V, the standby current is greater.
IL
SS
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
9.4 Output Disable (OE#)
When the OE# input is at V , output from the device is disabled. The outputs are placed in the
IH
high impedance state.
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10 Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part
identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words
in length that consists of 128 words for factory data and 128 words for customer-secured areas.
All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory
Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Se-
cured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6)
is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped
from the factory.
Please note the following general conditions:
While Secured Silicon Sector access is enabled, simultaneous operations are allowed ex-
cept for Bank 0.
On power-up, or following a hardware reset, the device reverts to sending commands to
the normal address space.
Reads can be performed in the Asynchronous or Synchronous mode.
Burst mode reads within Secured Silicon Sector wrap from address FFh back to address
00h.
Reads outside of sector 0 return memory array data.
Continuous burst read past the maximum address is undefined.
Sector 0 is remapped from memory array to Secured Silicon Sector array.
Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit
command must be issued to exit Secured Silicon Sector Mode.
The Secured Silicon Sector is not accessible when the device is executing an Embedded
Program or Embedded Erase algorithm.
Table 10.1. Secured Silicon Sector Addresses
Sector
Customer
Factory
Sector Size
128 words
128 words
Address Range
000080h-0000FFh
000000h-00007Fh
10.1 Factory Secured SiliconSector
The Factory Secured Silicon Sector is always protected when shipped from the factory and has
the Factory Indicator Bit (DQ7) permanently set to a “1”. This prevents cloning of a factory locked
part and ensures the security of the ESN and customer code once the product is shipped to the
field.
These devices are available pre programmed with one of the following:
A random, 8 Word secure ESN only within the Factory Secured Silicon Sector
Customer code within the Customer Secured Silicon Sector through the SpansionTM pro-
gramming service.
Both a random, secure ESN and customer code through the Spansion programming ser-
vice.
Customers may opt to have their code programmed through the Spansion programming services.
Spansion programs the customer's code, with or without the random ESN. The devices are then
shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured
Silicon Sector permanently locked. Contact your local representative for details on using Spansion
programming services.
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10.2 Customer Secured Silicon Sector
The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to “0”), allowing
customers to utilize that sector in any manner they choose. If the security feature is not required,
the Customer Secured Silicon Sector can be treated as an additional Flash memory space.
Please note the following:
Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit
is permanently set to “1.”
The Customer Secured Silicon Sector can be read any number of times, but can be pro-
grammed and locked only once. The Customer Secured Silicon Sector lock must be used
with caution as once locked, there is no procedure available for unlocking the Customer
Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector
memory space can be modified in any way.
The accelerated programming (ACC) and unlock bypass functions are not available when
programming the Customer Secured Silicon Sector, but reading in Banks 1 through 15 is
available.
Once the Customer Secured Silicon Sector is locked and verified, the system must write
the Exit Secured Silicon Sector Region command sequence which return the device to the
memory array at sector 0.
10.3 Secured Silicon Sector Entry and Secured Silicon Sector
Exit Command Sequences
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured
Silicon Sector command sequence. The device continues to access the Secured Silicon Sector re-
gion until the system issues the four-cycle Exit Secured Silicon Sector command sequence.
See Command Definition Table [Secured Silicon Sector Command Table, Appendix
Table 12.1 for address and data requirements for both command sequences.
The Secured Silicon Sector Entry Command allows the following commands to be executed
Read customer and factory Secured Silicon areas
Program the customer Secured Silicon Sector
After the system has written the Enter Secured Silicon Sector command sequence, it may read
the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the
memory array. This mode of operation continues until the system issues the Exit Secured Silicon
Sector command sequence, or until power is removed from the device.
Software Functions and Sample Code
The following are C functions and source code examples of using the Secured Silicon Sector
Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User’s Guide
(available soon on www.amd.com and www.fujitsu.com) for general information on Spansion
Flash memory software development guidelines.
Table 10.2. Secured Silicon Sector Entry
(LLD Function = lld_SecSiSectorEntryCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
Unlock Cycle 1
Unlock Cycle 2
00AAh
0055h
0088h
Write
Entry Cycle
Write
Note: Base = Base Address.
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/* Example: SecSi Sector Entry Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0088;
/* write unlock cycle 1
/* write unlock cycle 2
/* write Secsi Sector Entry Cmd
*/
*/
*/
Table 10.3. Secured Silicon Sector Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Word Address
Data
00AAh
Unlock Cycle 1
Unlock Cycle 2
Program Setup
Write
0055h
Write
00A0h
Program
Write
Data Word
Note: Base = Base Address.
/* Once in the SecSi Sector mode, you program */
/* words using the programming algorithm. */
Table 10.4. Secured Silicon Sector Exit
(LLD Function = lld_SecSiSectorExitCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
Unlock Cycle 1
Unlock Cycle 2
00AAh
0055h
0090h
Write
Exit Cycle
Write
Note: Base = Base Address.
/* Example: SecSi Sector Exit Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
/* write unlock cycle 1
/* write unlock cycle 2
/* write SecSi Sector Exit cycle 3 */
*/
*/
/* write SecSi Sector Exit cycle 4 */
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11 Electrical Specifications
11.1 Absolute Maximum Ratings
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except
as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to VIO + 0.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V
VIO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V
ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +9.5 V
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or
I/Os may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 11.1.
Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions
outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 11.2.
2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may
overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 11.1. Maximum DC
voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
data sheet is not implied. Exposure of the device to absolute maximum rating conditions
for extended periods may affect device reliability.
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20 ns
20 ns
20 ns
VCC
+2.0 V
+0.8 V
VCC
–0.5 V
–2.0 V
+0.5 V
1.0 V
20 ns
20 ns
20 ns
Figure 11.1. Maximum Negative Overshoot
Waveform
Figure 11.2. Maximum Positive Overshoot
Waveform
Notes:
1. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the
S29W256N.
11.2 Operating Ranges
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V
VIO Supply Voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V
(Contact local sales office for VIO = 1.35 to +1.70 V.)
Notes: Operating ranges define those limits between which the functionality of the device
is guaranteed.
11.3 Test Conditions
Device
Under
Test
C
L
Figure 11.3. Test Setup
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Table 11.1. Test Specifications
Test Condition
All Speed Options
Unit
Output Load Capacitance, C
(including jig capacitance)
L
30
pF
3.0 @ 54, 66 MHz
2.5 @ 80 MHz
Input Rise and Fall Times
Input Pulse Levels
ns
0.0–V
V
V
IO
Input timing measurement
reference levels
V /2
IO
Output timing measurement
reference levels
V /2
V
IO
Notes:
1. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the
S29W256N.
11.4 Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
Notes:
1. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the
S29W256N.
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A d v a n c e I n f o r m a t i o n
11.5 Switching Waveforms
VIO
All Inputs and Outputs
VIO/2
VIO/2
Input
Measurement Level
Output
0.0 V
Figure 11.4. Input Waveforms and Measurement Levels
11.6 VCC Power-up
Parameter
Description
Setup Time
CC
Test Setup
Speed
Unit
ms
t
V
Min
1
VCS
Notes:
1. VCC >= VIO - 100mV and VCC ramp rate is > 1V / 100µs
2. VCC ramp rate <1V / 100µs, a Hardware Reset is required.
3. The content in this document is Advance information for the S29WS064N and
S29WS128N. Content in this document is Preliminary for the S29W256N.
tVCS
VCC
VIO
RESET#
Figure 11.5.
V
Power-up Diagram
CC
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11.7 DC Characteristics (CMOS Compatible)
Parameter
Description (Notes)
Input Load Current
Test Conditions (Notes 1, 2, 9)
VIN = VSS to VCC, VCC = VCCmax
VOUT = VSS to VCC, VCC = VCCmax
Min
Typ
Max
±1
±1
54
60
66
48
54
60
42
48
54
36
42
48
30
36
18
4
Unit
µA
ILI
ILO
Output Leakage Current (3)
VCC Active burst Read Current
VIO Non-active Output
µA
54 MHz
27
28
30
28
30
32
29
32
34
32
35
38
20
27
13
3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
CE# = VIL, OE# = VIH, WE#
= VIH, burst length = 8
66 MHz
80 MHz
54 MHz
66 MHz
80 MHz
54 MHz
66 MHz
80 MHz
54 MHz
66 MHz
80 MHz
CE# = VIL, OE# = VIH, WE#
= VIH, burst length = 16
ICCB
CE# = VIL, OE# = VIH, WE#
= VIH, burst length = 32
CE# = VIL, OE# = VIH, WE#
= VIH, burst length =
Continuous
IIO1
OE# = VIH
10 MHz
5 MHz
1 MHz
VACC
mA
mA
mA
µA
VCC Active Asynchronous
Read Current (4)
CE# = VIL, OE# = VIH, WE#
= VIH
ICC1
1
5
CE# = VIL, OE# = VIH, ACC
= VIH
ICC2
VCC Active Write Current (5)
VCC
19
1
52.5
5
mA
µA
VACC
CE# = RESET# =
VCC ± 0.2 V
ICC3
VCC Standby Current (6, 7)
VCC Reset Current (7)
VCC
20
70
40
150
µA
ICC4
ICC5
ICC6
RESET# = VIL, CLK = VIL
µA
VCC Active Current
(Read While Write) (7)
CE# = VIL, OE# = VIH, ACC = VIH
5 MHz
@
50
60
mA
VCC Sleep Current (7)
CE# = VIL, OE# = VIH
2
6
40
20
µA
mA
mA
V
VACC
VCC
CE# = VIL, OE# = VIH,
VACC = 9.5 V
IACC
Accelerated Program Current (8)
14
20
VIL
VIH
Input Low Voltage
VIO = 1.8 V
VIO = 1.8 V
–0.5
0.4
Input High Voltage
VIO – 0.4
VIO + 0.4
0.1
V
VOL
VOH
VHH
VLKO
Output Low Voltage
IOL = 100 µA, VCC = VCC min = VIO
IOH = –100 µA, VCC = VCC min = VIO
V
Output High Voltage
VIO – 0.1
8.5
V
Voltage for Accelerated Program
Low VCC Lock-out Voltage
9.5
1.4
V
1.0
V
Notes:
1. Maximum ICC specifications are tested with VCC = VCCmax.
2. VCC= VIO
3. CE# must be set high when measuring the RDY pin.
4. The ICC current listed is typically less than 3 mA/MHz, with OE# at VIH
5. ICC active while Embedded Erase or Embedded Program is in progress.
6. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns.
.
.
Typical sleep mode current is equal to ICC3
.
7. VIH = VCC ± 0.2 V and VIL > –0.1 V.
8. Total current during accelerated programming is the sum of VACC and VCC
currents.
9. VACC = VHH on ACC input.
10.The content in this document is Advance information for the S29WS064N and
S29WS128N. Content in this document is Preliminary for the S29W256N.
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A d v a n c e I n f o r m a t i o n
11.8 AC Characteristics
11.8.1. CLK Characterization
Parameter
Description
54 MHz
54
66 MHz
66
80 MHz
80
Unit
MHz
ns
fCLK
CLK Frequency
Max
Min
tCLK
tCH
CLK Period
18.5
15.1
12.5
CLK High Time
CLK Low Time
CLK Rise Time
CLK Fall Time
Min
7.4
3
6.1
3
5.0
2.5
ns
ns
tCL
tCR
Max
tCF
Notes:
1. The content in this document is Advance information for the S29WS064N and
S29WS128N. Content in this document is Preliminary for the S29W256N.
t
CLK
t
t
CL
CH
CLK
t
t
CF
CR
Figure 11.6. CLK Characterization
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11.8.2 Synchronous/Burst Read
Parameter
JEDEC
Standard
Description
54 MHz
66 MHz
80
80 MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIACC
tBACC
tACS
tACH
tBDH
tCR
Latency
Max
Burst Access Time Valid Clock to Output Delay Max
13.5
5
11.2
9
Address Setup Time to CLK (Note 1)
Address Hold Time from CLK (Note 1)
Data Hold Time from Next Clock Cycle
Chip Enable to RDY Valid
Min
Min
Min
Max
Max
Max
Max
Min
Min
Max
Min
Min
Min
Max
4
6
3
7
4
13.5
13.5
11.2
9
tOE
Output Enable to Output Valid
Chip Enable to High Z (Note 2)
Output Enable to High Z (Note 2)
CE# Setup Time to CLK
11.2
tCEZ
tOEZ
tCES
tRDYS
tRACC
tCAS
tAVC
tAVD
tAOE
10
10
4
RDY Setup Time to CLK
5
4
3.5
9
Ready Access Time from CLK
CE# Setup Time to AVD#
AVD# Low to CLK
13.5
11.2
0
4
AVD# Pulse
8
AVD Low to OE# Low
38.4
Notes:
1. Addresses are latched on the first rising edge of CLK.
2. Not 100% tested.
3. The content in this document is Advance information for the S29WS064N and
S29WS128N. Content in this document is Preliminary for the S29W256N.
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A d v a n c e I n f o r m a t i o n
11.8.3 Timing Diagrams
5 cycles for initial access shown.
18.5 ns typ. (54 MHz)
tCEZ
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tACS
Addresses
Data (n)
Aa
tBACC
tACH
Hi-Z
Hi-Z
tIACC
Da
Da + 1
Da + 2
Da + n
tOEZ
Da + 3
tAOE
tBDH
OE#
tRACC
tOE
Hi-Z
RDY (n)
tCR
tRDYS
Hi-Z
Hi-Z
Data (n + 1)
RDY (n + 1)
Da
Da + 1
Da + 2
Da + n
Da + 2
Hi-Z
Hi-Z
Hi-Z
Data (n + 2)
RDY (n + 2)
Da
Da + 1
Da + 1
Da + n
Da + 1
Hi-Z
Hi-Z
Hi-Z
Data (n + 3)
Da
Da
Da
Da + n
Da
Hi-Z
RDY (n + 3)
Notes:
1. Figure shows total number of wait states set to five cycles. The total number of
wait states can be programmed from two cycles to seven cycles.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”,
additional clock delay cycles are inserted, and are indicated by RDY.
3. The device is in synchronous mode.
Figure 11.7. CLK Synchronous Burst Mode Read
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7 cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
tAOE
OE#
RDY
tCR
tRACC
tRACC
tOE
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
3. The device is in synchronous mode with wrap around.
4. D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 4th address in range (0-F).
Figure 11.8. 8-word Linear Burst with Wrap Around
7 cycles for initial access shown.
tCES
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D10
D13
tAOE
tBDH
OE#
RDY
tCR
tRACC
tRACC
tOE
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles. Clock is set for active rising edge.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
3. The device is in asynchronous mode with out wrap around.
4. DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 1st address in range (c-13).
Figure 11.9. 8-word Linear Burst without Wrap Around
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tCEZ
6 wait cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
tAVC
AVD#
tAVD
tACS
Aa
Addresses
Data
tBACC
tACH
Hi-Z
Hi-Z
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tBDH
tAOE
tOEZ
tRACC
OE#
RDY
tCR
tOE
Hi-Z
tRDYS
Notes:
1. Figure assumes 6 wait states for initial access and synchronous read.
2. The Set Configuration Register command sequence has been written with CR8=0; device outputs RDY one
cycle before valid data.
Figure 11.10. Linear Burst with RDY Set One Cycle Before Data
11.8.4 AC Characteristics—Asynchronous Read
Parameter
80
MHz
JEDEC Standard
Description
Access Time from CE# Low
54 MHz
66 MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCE
tACC
Max
Max
Min
Min
Min
Max
Min
80
80
8
Asynchronous Access Time
tAVDP
tAAVDS
tAAVDH
tOE
AVD# Low Time
Address Setup Time to Rising Edge of AVD#
Address Hold Time from Rising Edge of AVD#
Output Enable to Output Valid
4
7
6
13.5
0
Read
tOEH
Output Enable Hold Time
Toggle and Data# Polling Min
10
10
0
tOEZ
tCAS
Output Enable to High Z (see Note)
CE# Setup Time to AVD#
Max
Min
Notes:
1. Not 100% tested.
2. The content in this document is Advance information for the S29WS064N and
S29WS128N. Content in this document is Preliminary for the S29W256N.
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A d v a n c e I n f o r m a t i o n
CE#
OE#
tOE
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
tAAVDH
tCAS
tAVDP
tAAVDS
Note: RA = Read Address, RD = Read Data.
Figure 11.11. Asynchronous Mode Read
January 25, 2005 S29WS-N_00_G0
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A d v a n c e I n f o r m a t i o n
11.8.5 Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
All Speed Options
Unit
µs
tRP
tRH
RESET# Pulse Width
Reset High Time Before Read (See Note)
Min
Min
30
200
ns
Notes:
1. Not 100% tested.
2. The content in this document is Advance information for the S29WS064N and
S29WS128N. Content in this document is Preliminary for the S29W256N.
CE#, OE#
tRH
RESET#
tRP
Figure 11.12. Reset Timings
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A d v a n c e I n f o r m a t i o n
11.8.6 Erase/Program Timing
Parameter
JEDEC
Standard
Description
54 MHz
66 MHz
80 MHz Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
Min
80
5
ns
ns
ns
Synchronous
Asynchronous
Synchronous
Asynchronous
tAVWL
tAS
Address Setup Time (Notes 2, 3)
Address Hold Time (Notes 2, 3)
0
9
tWLAX
tAH
Min
ns
20
8
tAVDP
tDS
AVD# Low Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Max
Max
Max
Typ
Typ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
tDVWH
tWHDX
tGHWL
Data Setup Time
45
20
tDH
Data Hold Time
0
0
tGHWL
tCAS
tCH
Read Recovery Time Before Write
CE# Setup Time to AVD#
CE# Hold Time
0
tWHEH
tWLWH
tWHWL
0
tWP
Write Pulse Width
30
20
0
tWPH
tSR/W
tVID
Write Pulse Width High
Latency Between Read and Write Operations
VACC Rise and Fall Time
500
1
tVIDS
tVCS
tCS
VACC Setup Time (During Accelerated Programming)
VCC Setup Time
50
5
tELWL
CE# Setup Time to WE#
tAVSW
tAVHW
tAVSC
tAVHC
tCSW
tWEP
tSEA
tESL
AVD# Setup Time to WE#
5
AVD# Hold Time to WE#
5
AVD# Setup Time to CLK
5
AVD# Hold Time to CLK
5
Clock Setup Time to WE#
5
Noise Pulse Margin on WE#
3
Sector Erase Accept Time-out
Erase Suspend Latency
50
20
20
100
1
tPSL
Program Suspend Latency
tASP
tPSP
Toggle Time During Sector Protection
Toggle Time During Programming Within a Protected Sector
Notes:
1. Not 100% tested.
2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and
Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing,
addresses are latched on the rising edge of CLK.
4. See the “Erase and Programming Performance” section for more information.
5. Does not include the preprogramming time.
6. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the
S29W256N.
January 25, 2005 S29WS-N_00_G0
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A d v a n c e I n f o r m a t i o n
Erase Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
SA
555h for
chip erase
VA
VA
Addresses
Data
2AAh
10h for
chip erase
In
Complete
55h
30h
Progress
tDS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH2
tCS
tWPH
tWC
tVCS
VCC
Figure 11.13. Chip/Sector Erase Operation Timings
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A d v a n c e I n f o r m a t i o n
Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVSW
tAVHW
tAVDP
AVD#
tAS
tAH
Addresses
Data
555h
PA
VA
VA
In
A0h
tDS
Complete
PD
Progress
tCAS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH1
tCS
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during
command sequence unlock cycles.
4. CLK can be either V or V
.
IL
IH
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the
Configuration Register.
Figure 11.14. Asynchronous Program Operation Timings
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A d v a n c e I n f o r m a t i o n
Program Command Sequence (last two cycles)
Read Status Data
tAVCH
CLK
tAS
tAH
tAVSC
AVD#
tAVDP
Addresses
Data
PA
VA
VA
555h
In
Complete
A0h
PD
tDS
tDH
Progress
tCAS
CE#
tCH
OE#
WE#
tCSW
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during
command sequence unlock cycles.
4. Addresses are latched on the first rising edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration
Register. The Configuration Register must be set to the Synchronous Read Mode.
Figure 11.15. Synchronous Program Operation Timings
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A d v a n c e I n f o r m a t i o n
CE#
AVD#
WE#
Addresses
Data
PA
Don't Care
Don't Care
A0h
PD
Don't Care
OE#
ACC
tVIDS
V
V
ID
tVID
or V
IL
IH
Note: Use setup and hold times from conventional program operation.
Figure 11.16. Accelerated Unlock Bypass Programming Timing
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
High Z
Addresses
VA
VA
High Z
Status Data
Status Data
Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data#
Polling outputs true data.
Figure 11.17. Data# Polling Timings (During Embedded Algorithm)
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A d v a n c e I n f o r m a t i o n
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
High Z
High Z
Addresses
Data
VA
Status Data
Status Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits
stop toggling.
Figure 11.18. Toggle Bit Timings (During Embedded Algorithm)
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tIACC
tIACC
Data
Status Data
Status Data
RDY
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits
stop toggling.
3. RDY is active with data (D8 = 1 in the Configuration Register). When D8 = 0 in the Configuration Register, RDY is active one clock cycle before
data.
Figure 11.19. Synchronous Data Polling Timings/Toggle Bit Timings
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A d v a n c e I n f o r m a t i o n
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Erase
WE#
Erase
Erase Suspend
Read
Suspend
Program
Complete
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 11.20. DQ2 vs. DQ6
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
C128
80
C129
81
C130
82
C131
83
CLK
7C
Address (hex)
(stays high)
AVD#
tRACC
tRACC
RDY(1)
latency
tRACC
tRACC
RDY(2)
Data
latency
D124
D125
D126
D127
D128
D129
D130
OE#,
CE#
(stays low)
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device not crossing a bank in the process of performing an erase or program.
5. RDY does not go low and no additional wait states are required if the Burst frequency is <=66 MHz and the Boundary Crossing bit (D14) in
the Configuration Register is set to 0
Figure 11.21. Latency with Boundary Crossing when Frequency > 66 MHz
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A d v a n c e I n f o r m a t i o n
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
CLK
7C
Address (hex)
(stays high)
AVD#
tRACC
tRACC
RDY(1)
latency
tRACC
tRACC
RDY(2)
Data
latency
D124
D125
D126
D127
Read Status
OE#,
CE#
(stays low)
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device crossing a bank in the process of performing an erase or program.
5. RDY does not go low and no additional wait states are required if the Burst frequency is < 66 MHz and the Boundary Crossing bit (D14) in
the Configuration Register is set to 0.
Figure 11.22. Latency with Boundary Crossing into Program/Erase Bank
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A d v a n c e I n f o r m a t i o n
Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
next burst data
AVD#
OE#
total number of clock cycles
following addresses being latched
1
2
0
3
1
4
5
6
4
7
5
CLK
2
3
number of clock cycles
programmed
Wait State Configuration Register Setup:
D13, D12, D11 = “111” ⇒ Reserved
D13, D12, D11 = “110” ⇒ Reserved
D13, D12, D11 = “101” ⇒ 5 programmed, 7 total
D13, D12, D11 = “100” ⇒ 4 programmed, 6 total
D13, D12, D11 = “011” ⇒ 3 programmed, 5 total
D13, D12, D11 = “010” ⇒ 2 programmed, 4 total
D13, D12, D11 = “001” ⇒ 1 programmed, 3 total
D13, D12, D11 = “000” ⇒ 0 programmed, 2 total
Note: Figure assumes address D0 is not at an address boundary, and wait state is set to “101”.
Figure 11.23. Example of Wait States Insertion
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A d v a n c e I n f o r m a t i o n
Last Cycle in
Program or
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
Sector Erase
Command Sequence
tWC
tRC
tRC
tWC
CE#
OE#
tOE
tOEH
tGHWL
WE#
Data
tWPH
tOEZ
tWP
tDS
tACC
tOEH
tDH
PD/30h
RD
RD
AAh
tSR/W
RA
Addresses
AVD#
PA/SA
tAS
RA
555h
tAH
Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while
checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure
valid information.
Figure 11.24. Back-to-Back Read/Write Cycle Timings
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A d v a n c e I n f o r m a t i o n
11.8.7 Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
64 Kword
16 Kword
VCC
VCC
0.6
3.5
2
Sector Erase Time
s
<0.15
153.6 (WS256N)
77.4 (WS128N)
39.3 (WS064N)
308 (WS256N)
154 (WS128N)
78 (WS064N)
Excludes 00h
programming prior
to erasure (Note 4)
VCC
Chip Erase Time
s
130.6 (WS256N)
65.8 (WS128N)
33.4 (WS064N)
262 (WS256N)
132 (WS128N)
66 (WS064N)
ACC
VCC
ACC
VCC
ACC
VCC
ACC
40
24
400
240
94
Single Word Programming Time
(Note 8)
µs
µs
µs
9.4
6
Effective Word Programming Time
utilizing Program Write Buffer
60
300
192
3000
1920
Total 32-Word Buffer Programming
Time
157.3 (WS256N)
78.6 (WS128N)
39.3 (WS064N)
314.6 (WS256N)
157.3 (WS128N)
78.6 (WS064N)
VCC
Excludes system
level overhead
(Note 5)
Chip Programming Time (Note 3)
s
100.7 (WS256N)
50.3 (WS128N)
25.2 (WS064N)
201.3 (WS256N)
100.7 (WS128N)
50.3 (WS064N)
ACC
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V V , 10,000
CC
cycles; checkerboard data pattern.
2. Under worst case conditions of 90°C, V = 1.70 V, 100,000 cycles.
CC
3. Typical chip programming time is considerably less than the maximum chip programming
time listed, and is based on utilizing the Write Buffer.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed
to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence
for the program command. See the Appendix for further information on command
definitions.
6. Contact the local sales office for minimum cycling endurance values in specific applications
and operating conditions.
7. Refer to Application Note “Erase Suspend/Resume Timing” for more details.
8. Word programming specification is based upon a single word programming operation not
utilizing the write buffer.
9. The content in this document is Advance information for the S29WS064N and S29WS128N.
Content in this document is Preliminary for the S29W256N.
January 25, 2005 S29WS-N_00_G0
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A d v a n c e I n f o r m a t i o n
11.8.8 BGA Ball Capacitance
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
Typ.
5.3
5.8
6.3
Max
6.3
6.8
7.3
Unit
pF
C
V
= 0
= 0
= 0
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
pF
OUT
OUT
C
V
pF
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C; f = 1.0 MHz.
3. The content in this document is Advance information for the S29WS064N and
S29WS128N. Content in this document is Preliminary for the S29W256N.
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A d v a n c e I n f o r m a t i o n
12 Appendix
This section contains information relating to software control or interfacing with the Flash device.
For additional information and assistance regarding software, see the Additional Resources sec-
tion on page 16, or explore the Web at www.amd.com and www.fujitsu.com.
January 25, 2005 S29WS-N_00_G0
87
A d v a n c e I n f o r m a t i o n
Table 12.1. Memory Array Commands
Bus Cycles (Notes 1–5)
First
Addr
RA
XXX
555
555
Second
Third
Addr
Fourth
Addr Data
Fifth
Addr
Sixth
Addr Data
Command Sequence
(Notes)
Asynchronous Read (6)
Reset (7)
Manufacturer ID
Data
RD
F0
Addr
Data
Data
Data
1
1
4
6
AA
AA
2AA
2AA
55
55
[BA]555
[BA]555
90
90
[BA]X00 0001
[BA]X01 227E
Device ID (9)
BA+X0E
PA
Data
PD
BA+X0F 2200
Indicator Bits (10)
4
555
AA
2AA
55
[BA]555
90
[BA]X03
Data
Program
4
6
1
3
6
6
1
1
4
4
1
3
2
1
555
555
SA
555
555
555
BA
AA
AA
29
AA
AA
AA
B0
30
AA
AA
98
AA
A0
98
2AA
2AA
55
55
555
PA
A0
25
PA
PA
PD
Write to Buffer (11)
Program Buffer to Flash
Write to Buffer Abort Reset (12)
Chip Erase
WC
WBL
PD
2AA
2AA
2AA
55
55
55
555
555
555
F0
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase/Program Suspend (13)
Erase/Program Resume (14)
Set Configuration Register (18)
Read Configuration Register
CFI Query (15)
BA
555
555
[BA]555
555
XXX
XXX
2AA
2AA
55
55
555
555
D0
C6
X00
X00
CR
CR
Entry
Program (16)
2AA
PA
55
PD
555
20
CFI (16)
Reset
2
XXX
90
XXX
00
Entry
3
4
1
555
555
00
AA
AA
Data
2AA
2AA
55
55
555
555
88
A0
Program (17)
Read (17)
PA
PD
00
Exit (17)
4
555
AA
2AA
55
555
90
XXX
Legend:
X = Don’t care.
RA = Read Address.
RD = Read Data.
PA = Program Address. Addresses latch on the rising edge of the
AVD# pulse or active edge of CLK, whichever occurs first.
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;
WS064N = A21–A14.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;
WS064N = A21–A18.
CR = Configuration Register data bits D15–D0.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
Notes:
1. See Table 7.1 for description of bus operations.
13. System may read and program in non-erasing sectors, or enter
the autoselect mode, when in the Erase Suspend mode. The
Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. Erase Resume command is valid only during the Erase Suspend
mode, and requires the bank address.
15. Command is valid when device is ready to read array data or
when device is in autoselect mode. Address equals 55h on all
future devices, but 555h for WS256N/128N/064N.
16. Requires Entry command sequence prior to execution. Unlock
Bypass Reset command is required to return to reading array
data.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles.
4. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
5. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
6. No unlock or command cycles required when bank is reading
array data.
7. Reset command is required to return to reading array data (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high
(while the bank is providing status information) or performing
sector lock/unlock.
17. Requires Entry command sequence prior to execution. SecSi
Sector Exit Reset command is required to exit this mode; device
may otherwise be placed in an unknown state.
18. Requires reset command to configure the Configuration Register.
8. The system must provide the bank address. See Autoselect
section for more information.
9. Data in cycle 5 is 2230 (WS256N), 2232 (WS064N), or 2231
(WS128N).
10. See Table 7.9 for indicator bit values.
11. Total number of cycles in the command sequence is determined
by the number of words written to the write buffer.
12. Command sequence resets device for next command after write-
to-buffer operation.
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A d v a n c e I n f o r m a t i o n
Table 12.2. Sector Protection Commands
Bus Cycles (Notes 1–4)
First
Second
Third
Fourth
Fifth
Sixth
Seventh
Command Sequence
(Notes)
Addr
Data
AA
Addr
Data
55
Addr
Data
Addr Data Addr Data Addr Data Addr Data
Command Set Entry (5)
Program (6, 12)
3
2
1
2
3
2
4
7
2
3
2
2
1
2
3
2
1
555
XX
2AA
555
40
Lock
Register
Bits
A0
77/00
data
Read (6)
77
data
90
Command Set Exit (7)
Command Set Entry (5)
Program [0-3] (8)
Read (9)
XX
XX
2AA
00
00
55
555
XX
AA
555
60
A0
PWD[0-3]
PWD1
03
Password
Protection
0...00 PWD0 0...01
0...02
00
PWD2 0...03 PWD3
PWD0
Unlock
00
XX
555
XX
XX
SA
XX
555
XX
BA
25
90
00
XX
01
PWD1
02
PWD2
03
PWD3
00
29
Command Set Exit (7)
Command Set Entry (5)
PPB Program (10)
All PPB Erase (10, 11)
PPB Status Read
00
AA
A0
2AA
SA
55
00
[BA]555
C0
Non-Volatile
Sector
Protection (PPB)
80
00
30
RD(0)
90
Command Set Exit (7)
Command Set Entry (5)
PPB Lock Bit Set
XX
2AA
XX
00
55
00
Global
Volatile Sector
Protection
Freeze
AA
[BA]555
[BA]555
50
E0
A0
PPB Lock Bit Status Read
RD(0)
Command Set Exit (7)
2
XX
90
XX
00
(PPB Lock)
Command Set Entry (5)
DYB Set
DYB Clear
3
2
2
1
2
555
XX
XX
SA
XX
AA
A0
A0
2AA
SA
55
00
01
Volatile Sector
Protection
(DYB)
SA
DYB Status Read
Command Set Exit (7)
RD(0)
90
XX
00
Legend:
X = Don’t care.
RA = Address of the memory location to be read.
PD(0) = SecSi Sector Lock Bit. PD(0), or bit[0].
PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must
be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’.
PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must
be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;
WS064N = A21–A18.
PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit
combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If
protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1,
DQ2 = 1.
PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;
WS064N = A21–A14.
Notes:
1. All values are in hexadecimal.
2. Shaded cells indicate read cycles.
6. If both the Persistent Protection Mode Locking Bit and the
Password Protection Mode Locking Bit are set at the same time,
the command operation aborts and returns the device to the
default Persistent Sector Protection Mode during 2nd bus cycle.
Note that on all future devices, addresses equal 00h, but is
currently 77h for the WS256N only. See Tables 8.1 and 8.2 for
explanation of lock bits.
3. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
4. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
7. Exit command must be issued to reset the device into read
mode; device may otherwise be placed in an unknown state.
5. Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
8. Entire two bus-cycle sequence must be entered for each portion
of the password.
9. Full address range is required for reading password.
10. See Figure 8.2 for details.
11. “All PPB Erase” command pre-programs all PPBs before erasure
to prevent over-erasure.
12. The second cycle address for the lock register program operation
is 77 for S29Ws256N; however, for WS128N and Ws064N this
address is 00.
January 25, 2005 S29WS-N_00_G0
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A d v a n c e I n f o r m a t i o n
12.1 Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software inter-
rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-
dent, and forward- and back-ward-compatible for the specified flash device families. Flash
vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address (BA)555h any time the device is ready to read array data. The system can read CFI in-
formation at the addresses given in Tables 12.3–12.6) within that bank. All reads outside of the
CFI address range, within the bank, returns non-valid data. Reads from other banks are allowed,
writes are not. To terminate reading CFI data, the system must write the reset command.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: CFI Entry command */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0098;
/* write CFI entry command
/* write cfi exit command
*/
*/
/* Example: CFI Exit command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0;
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A
and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these
documents.
Table 12.3. CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Table 12.4. System Interface String
Addresses
Data
Description
V
CC Min. (write/erase)
1Bh
1Ch
0017h
D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
0019h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0006h
0009h
000Ah
0000h
0004h
0004h
0003h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
90
S29WS-N_00_G0 January 25, 2005
A d v a n c e I n f o r m a t i o n
Table 12.5. Device Geometry Definition
Addresses
Data
Description
0019h (WS256N)
0018h (WS128N)
0017h (WS064N)
27h
Device Size = 2N byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ah
2Bh
0006h
0000h
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0003h
0000h
0080h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
00FDh (WS256N)
007Dh (WS128N)
003Dh (WS064N)
31h
Erase Block Region 2 Information
32h
33h
34h
0000h
0000h
0002h
35h
36h
37h
38h
0003h
0000h
0080h
0000h
Erase Block Region 3 Information
Erase Block Region 4 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
January 25, 2005 S29WS-N_00_G0
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A d v a n c e I n f o r m a t i o n
Table 12.6. Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0034h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
0100h
Silicon Technology (Bits 5-2) 0100 = 0.11 µm
Erase Suspend
46h
47h
48h
49h
0002h
0001h
0000h
0008h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
08 = Advanced Sector Protection
00F3h (WS256N)
007Bh (WS128N)
003Fh (WS064N)
Simultaneous Operation
Number of Sectors in all banks except boot bank
4Ah
4Bh
Burst Mode Type
00 = Not Supported, 01 = Supported
0001h
0000h
Page Mode Type
4Ch
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word
Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
0085h
0095h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
0001h = Dual Boot Device
4Fh
50h
51h
0001h
0001h
0001h
Program Suspend. 00h = not supported
Unlock Bypass
00 = Not Supported, 01=Supported
52h
53h
0007h
0014h
SecSi Sector (Customer OTP Area) Size 2N bytes
Hardware Reset Low Time-out during an embedded algorithm to read
mode Maximum 2N ns
Hardware Reset Low Time-out not during an embedded algorithm to read
mode Maximum 2N ns
54h
0014h
55h
56h
57h
0005h
0005h
0010h
Erase Suspend Time-out Maximum 2N ns
Program Suspend Time-out Maximum 2N ns
Bank Organization: X = Number of banks
0013h (WS256N)
000Bh (WS128N)
0007h (WS064N)
58h
Bank 0 Region Information. X = Number of sectors in bank
92
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A d v a n c e I n f o r m a t i o n
Table 12.6. Primary Vendor-Specific Extended Query (Continued)
Addresses
Data
Description
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
59h
Bank 1 Region Information. X = Number of sectors in bank
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
Bank 2 Region Information. X = Number of sectors in bank
Bank 3 Region Information. X = Number of sectors in bank
Bank 4 Region Information. X = Number of sectors in bank
Bank 5 Region Information. X = Number of sectors in bank
Bank 6 Region Information. X = Number of sectors in bank
Bank 7 Region Information. X = Number of sectors in bank
Bank 8 Region Information. X = Number of sectors in bank
Bank 9 Region Information. X = Number of sectors in bank
Bank 10 Region Information. X = Number of sectors in bank
Bank 11 Region Information. X = Number of sectors in bank
Bank 12 Region Information. X = Number of sectors in bank
Bank 13 Region Information. X = Number of sectors in bank
Bank 14 Region Information. X = Number of sectors in bank
Bank 15 Region Information. X = Number of sectors in bank
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0013h (WS256N)
000Bh (WS128N)
0007h (WS064N)
January 25, 2005 S29WS-N_00_G0
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A d v a n c e I n f o r m a t i o n
13 Commonly Used Terms
Term
Definition
ACCelerate. A special purpose input signal which allows for faster programming or
ACC
erase operation when raised to a specified voltage above V . In some devices ACC
CC
may protect all sectors when at a low voltage.
Most significant bit of the address input [A23 for 256Mbit, A22 for128Mbit, A21 for
64Mbit]
A
A
max
Least significant bit of the address input signals (A0 for all devices in this document).
min
Operation where signal relationships are based only on propagation delays and are
unrelated to synchronous control (clock) signal.
Asynchronous
Autoselect
Read mode for obtaining manufacturer and device information as well as sector
protection status.
Section of the memory array consisting of multiple consecutive sectors. A read
operation in one bank, can be independent of a program or erase operation in a
different bank for devices that offer simultaneous read and write feature.
Bank
Smaller size sectors located at the top and or bottom of Flash device address space.
The smaller sector size allows for finer granularity control of erase and protection for
code or parameters used to initiate system operation after power-on or reset.
Boot sector
Boundary
Burst Read
Byte
Location at the beginning or end of series of memory locations.
See synchronous read.
8 bits
Common Flash Interface. A Flash memory industry standard specification [JEDEC 137-
A and JESD68.01] designed to allow a system to interrogate the Flash to determine its
size, type and other performance parameters.
CFI
Clear
Zero (Logic Low Level)
Special purpose register which must be programmed to enable synchronous read
mode
Configuration Register
Synchronous method of burst read whereby the device reads continuously until it is
stopped by the host, or it has reached the highest address of the memory array, after
which the read address wraps around to the lowest memory array address
Continuous Read
Erase
Returns bits of a Flash memory array to their default state of a logical One (High Level).
Halts an erase operation to allow reading or programming in any sector that is not
selected for erasure
Erase Suspend/Erase Resume
Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array
and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram
for further details.
BGA
Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with
Linear Read
or without wraparound before requiring a new initial address
.
Multi-Chip Package. A method of combining integrated circuits in a single package by
“stacking” multiple die of the same or different devices.
MCP
Memory Array
MirrorBit™ Technology
The programmable area of the product available for data storage.
Spansion™ trademarked technology for storing multiple bits of data in the same
transistor.
94
S29WS-N_00_G0 January 25, 2005
A d v a n c e I n f o r m a t i o n
Term
Definition
Group of words that may be accessed more rapidly as a group than if the words were
accessed individually.
Page
Asynchronous read operation of several words in which the first word of the group
takes a longer initial access time and subsequent words in the group take less “page”
access time to be read. Different words in the group are accessed by changing only the
least significant address lines.
Page Read
Sector protection method which uses a programmable password, in addition to the
Password Protection
Persistent Protection
Program
Persistent Protection method, for protection of sectors in the Flash memory device
.
Sector protection method that uses commands and only the standard core voltage
supply to control protection of sectors in the Flash memory device. This method
replaces a prior technique of requiring a 12V supply to control the protection method.
Stores data into a Flash memory by selectively clearing bits of the memory array in
order to leave a data pattern of “ones” and “zeros”.
Program Suspend/Program
Resume
Halts a programming operation to read data from any location that is not selected for
programming or erase.
Read
Host bus cycle that causes the Flash to output data onto the data bus.
Dynamic storage bits for holding device control information or tracking the status of
an operation.
Registers
Secured Silicon. An area consisting of 256 bytes in which any word may be
programmed once, and the entire area may be protected once from any future
programming. Information in this area may be programmed at the factory or by the
user. Once programmed and protected there is no way to change the secured
information. This area is often used to store a software readable identification such as
a serial number.
Secured Silicon
Use of one or more control bits per sector to indicate whether each sector may be
programmed or erased. If the Protection bit for a sector is set the embedded
algorithms for program or erase ignores program or erase commands related to that
sector.
Sector Protection
Sector
An Area of the memory array in which all bits must be erased together by an erase
operation.
Mode of operation in which a host system may issue a program or erase command to
one bank, that embedded algorithm operation may then proceed while the host
immediately follows the embedded algorithm command with reading from another
bank. Reading may continue concurrently in any bank other than the one executing
the embedded algorithm operation.
Simultaneous Operation
Synchronous Operation
Operation that progresses only when a timing signal, known as a clock, transitions
between logic levels (that is, at a clock edge).
Separate power supply or voltage reference signal that allows the host system to set
the voltage levels that the device generates at its data outputs and the voltages
tolerated at its data inputs.
VersatileIO™ (V )
IO
Mode that facilitates faster program times by reducing the number of command bus
cycles required to issue a write operation command. In this mode the initial two
“Unlock” write cycles, of the usual 4 cycle Program command, are not required –
reducing all Program commands to two bus cycles while in this mode.
Unlock Bypass
Word
Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two
contiguous words located on a two word boundary. A quad word is four contiguous
words located on a four word boundary.
January 25, 2005 S29WS-N_00_G0
95
A d v a n c e I n f o r m a t i o n
Term
Definition
Special burst read mode where the read address “wraps” or returns back to the lowest
address boundary in the selected range of words, after reading the last Byte or Word
in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read
words in the sequence 2, 3, 0, 1.
Wraparound
Interchangeable term for a program/erase operation where the content of a register
and or memory location is being altered. The term write is often associated with
“writing command cycles” to enter or exit a particular mode of operation.
Write
Multi-word area in which multiple words may be programmed as a single operation. A
Write Buffer
Write Buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary
respectively.
Method of writing multiple words, up to the maximum size of the Write Buffer, in one
Write Buffer Programming
Write Operation Status
operation. Using Write Buffer Programming results in
time than by using single word at a time programming commands.
≥
8 times faster programming
Allows the host system to determine the status of a program or erase operation by
reading several special purpose register bits
.
96
S29WS-N_00_G0 January 25, 2005
A d v a n c e I n f o r m a t i o n
14 Revisions
Revision F (October 29, 2004)
Data sheet completely revised. Changed arrangement of sections; edited explanatory text, added
flowcharts. This document supersedes Revision E+1, issued August 9, 2004; only the changes
specified for Revision F in this section affect the document or device. All other device specifica-
tions remain the same as presented in Revision E+1.
Deleted product selector guide.
11.8.2, Synchronous/Burst Read
Deleted t
and t
from table. Modified Note 1.
AAS
AAH
Table 12.4, System Interface String
Changed data at address 23h from 0003h to 0004h.
Revision G (January 25, 2005)
Global
Updated t
, t
, t , CFI address 4Ah, and the Configuration Register.
IACC BACC OE
Added Figure 8.2, “PPB Program/Erase Algorithm” .
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-
tioned uses of the products. Any semiconductor device has an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and
product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
January 25, 2005 S29WS-N_00_G0
97
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