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S30MS01GR25TFW103 [SPANSION]

Flash, 128KX8, 25ns, PDSO48, LEAD FREE, MO-142DDD, TSOP-48;
S30MS01GR25TFW103
型号： S30MS01GR25TFW103
厂家： SPANSION    SPANSION
描述：

Flash, 128KX8, 25ns, PDSO48, LEAD FREE, MO-142DDD, TSOP-48

光电二极管
文件： 总48页 (文件大小：1990K)
中文：  中文翻译
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S30MS-R ORNANDTM Flash Family  
S30MS04GR, S30MS02GR, S30MS01GR, S30MS512R  
4 Gb/2 Gb/1 Gb/512 Mb, x8/x16, 1.8 Volt NAND Interface Memory  
Based on MirrorBit® Technology  
S30MS-R ORNANDTM Flash Family Cover Sheet  
Data Sheet  
Notice to Readers: This document states the current technical specifications regarding the Spansion  
product(s) described herein. Each product described herein may be designated as Advance Information,  
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.  
Publication Number S30MS-R_00  
Revision 06  
Issue Date March 30, 2009  
D a t a S h e e t  
Notice On Data Sheet Designations  
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of  
product information or intended specifications throughout the product life cycle, including development,  
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify  
that they have the latest information before finalizing their design. The following descriptions of Spansion data  
sheet designations are presented here to highlight their presence and definitions.  
Advance Information  
The Advance Information designation indicates that Spansion Inc. is developing one or more specific  
products, but has not committed any design to production. Information presented in a document with this  
designation is likely to change, and in some cases, development on the product may discontinue. Spansion  
Inc. therefore places the following conditions upon Advance Information content:  
“This document contains information on one or more products under development at Spansion Inc.  
The information is intended to help you evaluate this product. Do not design in this product without  
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed  
product without notice.”  
Preliminary  
The Preliminary designation indicates that the product development has progressed such that a commitment  
to production has taken place. This designation covers several aspects of the product life cycle, including  
product qualification, initial production, and the subsequent phases in the manufacturing process that occur  
before full production is achieved. Changes to the technical specifications presented in a Preliminary  
document should be expected while keeping these aspects of production under consideration. Spansion  
places the following conditions upon Preliminary content:  
“This document states the current technical specifications regarding the Spansion product(s)  
described herein. The Preliminary status of this document indicates that product qualification has been  
completed, and that initial production has begun. Due to the phases of the manufacturing process that  
require maintaining efficiency and quality, this document may be revised by subsequent versions or  
modifications due to changes in technical specifications.”  
Combination  
Some data sheets contain a combination of products with different designations (Advance Information,  
Preliminary, or Full Production). This type of document distinguishes these products and their designations  
wherever necessary, typically on the first page, the ordering information page, and pages with the DC  
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first  
page refers the reader to the notice on this page.  
Full Production (No Designation on Document)  
When a product has been in production for a period of time such that no changes or only nominal changes  
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include  
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed  
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a  
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following  
conditions to documents in this category:  
“This document states the current technical specifications regarding the Spansion product(s)  
described herein. Spansion Inc. deems the products to have been in sufficient production volume such  
that subsequent versions of this document are not expected to change. However, typographical or  
specification corrections, or modifications to the valid combinations offered may occur.”  
Questions regarding these document designations may be directed to your local sales office.  
2
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
S30MS-R ORNANDTM Flash Family  
S30MS04GR, S30MS02GR, S30MS01GR, S30MS512R  
4 Gb/2 Gb/1 Gb/512 Mb, x8/x16, 1.8 Volt NAND Interface Memory  
Based on MirrorBit® Technology  
Data Sheet  
Distinctive Characteristics  
„ Manufactured on 65 nm MirrorBit® Process Technology  
– Eight 2112 byte OTP pages that can be locked individually  
„ Erase Suspend and Resume  
„ Single Power Supply Operation  
– While Erase is suspended, a read or program operation may be  
– 1.8 volt read, erase, and program operations  
performed  
– V = 1.7 V – 1.95 V  
CC  
– An Erase command with any address resumes the last Erase  
operation  
„ Bus widths - x8 and x16  
„ Page Size  
„ 3 quality grades for different applications  
– No bad blocks  
– Full Page: 2K + 64 Byte  
– Partial Page: 512 + 16 Byte  
– Up to 2% initial bad blocks, no dynamic bad blocks  
– Up to 2% bad blocks including initial and dynamic bad blocks  
„ Block (erase unit) Architecture  
– Block Size: 128K + 4K Byte  
– Number of Blocks:  
4 Gb: 4K blocks 2 Gb: 2K blocks  
1 Gb: 1K blocks 512 Mb: 512 blocks  
„ Program/Erase Cycles  
– 100,000 Program/Erase Cycles per Block Typical  
– 10,000 Program/Erase Cycles per Block Minimum  
„ 10-Year Data Retention Typical  
„ Compatible with NAND Flash  
„ Operating Temperature Range  
– Signal and command set compatible with large page/block NAND  
flash  
– Wireless (–25°C to +85°C)  
– CE# Don’t Care  
„ Package Options  
„ Pipelined Read and Write  
– TSOP: 48-pin  
– A second page buffer is used to improve reading and programming  
throughput  
– FBGA: Multiple MCP Packages Available  
– PoP: Please contact a Spansion sales office for information about  
our Package on Package offerings.  
„ One Time Protect (OTP) Area  
Performance Characteristics  
Typical Program & Erase Times  
Read Access Times  
x8  
x16  
Full Page Random Access  
Partial Page Random Access  
Serial Read  
28 µs  
10 µs  
25ns  
Program  
2.4 MB/s  
2.6 MB/s  
26.3 MB/s  
38.4 MB/s  
22.0 MB/s  
2.5 MB/s  
2.6 MB/s  
39.7 MB/s  
75.9 MB/s  
31 MB/s  
Erase  
Full Page Read  
Pipeline Page Read  
Partial Page Read  
Current Consumption (typical values)  
Read Current  
40 mA  
60 mA  
60 mA  
10 uA  
Legend:  
b = bit, B = Byte  
Erase Current  
Program Current  
Standby Current  
Publication Number S30MS-R_00  
Revision 06  
Issue Date March 30, 2009  
D a t a S h e e t  
General Description  
The S30MS-R family is made up of single-voltage flash memory products manufactured using 65 nm  
MirrorBit® technology. The S30MS04GR is comprised of two 2 Gb devices and is organized as 256 M Words  
or 512 MB. The S30MS02GR is a 2 Gb device organized as 128 Mwords or 256MB. The S30MS01GR is a 1  
Gb device, organized as 64 Mwords or 128 MB. The S30MS512R is a 512 Mb device, organized as 32  
Mwords or 64 MB.  
The S30MS-R family of devices offer advantages such as:  
„ Fast read speed and reliability suitable for demanding code storage applications  
„ Fast write and sustained write speed suitable for data storage applications  
The devices are offered in a 48-pin TSOP and several FBGA MCP packages.  
The S30MS-R family is made up of byte/word serial-type memory devices that use the I/O pins for both  
address and data input/output, as well as for command input. The Erase and Program operations are  
automatically executed making the device suitable for applications such as solid-state disks, picture storage  
for still cameras, cellular phones, and other systems that require high-density non-volatile data storage.  
Typical application requirements are shown in the table below.  
Application  
2G Network  
Minimum Requirements  
14.4 Kbps (1.8 KB/sec)  
2 Mbps (250 KB/sec)  
14.4Mbps (1.8MB/sec)  
51 KB/sec up to 108 KB/sec  
up to 28 KB/sec  
Spansion ORNAND  
9
9
9
9
9
9
9
9
3G r99 Network  
3.5G Network (HSDPA)  
2.5G (GRPS)  
2.75 (EDGE)  
USB  
1.5 MB/sec  
MP3 Playback  
MPEG4 (H.264)  
320 Kbps (40 KB/sec)  
1 MB/sec  
The devices include the following features:  
„ Automatic boot read, allows access of the data in one page after power up, without command and address  
input of read command.  
„ Initiation of program and erase functions through command sequences.  
„ Chip Enable Don't Care support for direct connection with microcontrollers.  
„ The command set is compatible with the large page/block NAND Flash command set.  
„ Ready/Busy# pin allows the system to monitor the program/erase operation status.  
„ One Time Protect (OTP) Pages that store permanent information such as a serial number IMEI/ESN  
information, secure boot code, or SIM-Lock.  
„ Manufactured using MirrorBit flash technology resulting in the highest levels of quality, reliability, and cost  
effectiveness.  
4
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
Table of Contents  
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
1.  
2.  
3.  
4.  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Device Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
4.1  
4.2  
4.3  
CE# Don’t Care Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Stacked Die Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
WP# Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
5.  
6.  
7.  
8.  
9.  
Internal Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
5.1 Array Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
6.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
7.1 TSOP 48-Pin Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
8.1 48-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
9.1  
9.2  
9.3  
9.4  
9.5  
9.6  
9.7  
9.8  
9.9  
Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Power On and Power Off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
ID Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Pipeline Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Page Duplicate Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Block Erase and Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
9.10 OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
9.11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
10. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
10.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
10.2 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
10.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
10.4 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
10.5 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
10.6 Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
10.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
10.8 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
11. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
March 30, 2009 S30MS-R_00_06  
S30MS-R ORNANDTM Flash Family  
5
D a t a S h e e t  
Figures  
Figure 4.1  
Figure 5.1  
Figure 9.1  
Figure 9.2  
Figure 9.3  
Figure 9.4  
Figure 9.5  
Figure 9.6  
Figure 9.7  
Figure 9.8  
Figure 9.9  
WP# Signal—Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
Array Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Power-On/Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
ID Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Column Address Change Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Pipeline Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Pipeline Read Mode without RY/BY# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24  
Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Serial Input Command Sequence Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Cache Program with RY/BY# Only Monitored . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Figure 9.10 Cache Program Monitored by Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Figure 9.11 Page Duplicate Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Figure 9.12 Page Duplicate Program Operation with Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . 28  
Figure 9.13 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Figure 9.14 Erase Suspend Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29  
Figure 9.15 Multiple Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Figure 9.16 Status Read Timing Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Figure 9.17 RY/BY# During Program/Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Figure 9.18 Status Read During a Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Figure 9.19 RY/BY#: Termination for the Ready/Busy Pin (RY/BY#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Figure 9.20 OTP Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Figure 9.21 OTP Page Protect Command Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33  
Figure 9.22 OTP Command (Page Protection Status) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .33  
Figure 9.23 OTP Command (Overlay/Remove) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34  
Figure 9.24 OTP Command (Default as Overlay/Default as Removed) Timing Diagram . . . . . . . . . . . . .34  
Figure 9.25 Reset (FFh) Command Input During Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Figure 9.26 Reset (FFh) Command Input During Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Figure 9.27 Reset (FFh) Command Input During a Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Figure 9.28 Status Read Command (70h) Input After a Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Figure 9.29 Two or More Reset Commands Input in Succession. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Figure 10.1 Command Input Cycle Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Figure 10.2 Address Input Cycle Timing Diagram (512 Mbit/1 Gbit). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Figure 10.3 Address Input Cycle Timing Diagram (2 Gbit/4 Gbit). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Figure 10.4 Data Input Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Figure 10.5 Serial Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Figure 10.6 Status Read Cycle Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Figure 10.7 Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Figure 10.8 Column Address Change in Read Cycle Timing Diagram (1/2). . . . . . . . . . . . . . . . . . . . . . . 43  
Figure 10.9 Column Address Change in Read Cycle Timing Diagram (2/2). . . . . . . . . . . . . . . . . . . . . . . 43  
Figure 10.10 Program Operation Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Figure 10.11 Block Erase Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Figure 10.12 Cache Program Operation Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45  
Figure 10.13 Page Duplicate Program Operation with Random Data Input Timing Diagram . . . . . . . . . . .46  
Figure 10.14 ID Read Operation Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
6
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
Tables  
Table 4.1  
Table 5.1  
Table 5.2  
Table 5.3  
Table 5.4  
Table 5.5  
Table 5.6  
Table 5.7  
Table 6.1  
Table 9.1  
Table 9.2  
Table 9.3  
Table 9.4  
Table 9.5  
Table 9.6  
Table 9.7  
Table 10.1  
Table 10.2  
Table 10.3  
Table 10.4  
Table 10.5  
Table 10.6  
Table 10.7  
Table 10.8  
Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10  
Memory Addressing Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  
(2 Gb and 4 Gb) x 8 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  
(1 Gb) x 8 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  
(512 Mb) x8 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14  
(2 Gb and 4 Gb) x 16 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14  
(1 Gb) x 16 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14  
(512 Mb) x 16 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14  
Model Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15  
Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18  
ID Byte Settings Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20  
4th ID Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21  
5th ID Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21  
6th ID Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21  
Page Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25  
Status Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36  
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36  
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37  
Capacitance (Ta = 25°C, f = 1 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37  
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38  
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38  
Program and Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44  
March 30, 2009 S30MS-R_00_06  
S30MS-R ORNANDTM Flash Family  
7
D a t a S h e e t  
1. Definitions  
Term  
B
Definition  
Byte, 8 bits  
Word, 16 bits  
Bit  
W
b
ECC  
Memory  
Error Correction Code  
Flash array  
Portion of the memory array that is erased by a single erase operation. Generally 128 KB main area and 4 KB spare  
area.  
Block  
Portion of the memory array that may be made available via direct read and write operations of a RAM buffer. Typically  
a 2-KByte portion of the main area and a 64 Byte portion of the spare area.  
Page  
The smallest portion of the memory array that may be read or written. A 512 Byte portion of the main area or a 16 Byte  
portion of the spare area.  
Segment  
2. Signal Descriptions  
The device is a byte/word serial access memory that utilizes time-shared input of commands, address, and  
data information. The device signals are shown in Connection Diagrams on page 16.  
Signal  
Description  
Command Latch Enable: The CLE input signal is used to control loading of the operation mode command into the  
internal command register. The command is latched into the command register from the I/O signals on the rising edge of  
the WE# signal while CE# is low and CLE is High.  
CLE  
ALE  
Address Latch Enable: The ALE signal is used to control loading of either address information or input data into the  
internal address/data register. Address information is latched on the rising edge of WE# if CE# is low and ALE is High.  
Input data is latched if CE# is low and ALE is Low.  
Chip Enable: The CE# signal selects the device for data read and command write access. The device enters a low-  
power Standby mode when CE# is High and no Read, Program, or Erase operation is in progress.  
CE#  
WE#  
RE#  
Write Enable: The WE# signal is used to control the acquisition of data from the I/O port. Command, address, and data  
information on the I/O signals are latched on the rising edge of the WE pulse.  
Read Enable: The RE# signal controls serial data output. Data is available t  
after the falling edge of RE#. The  
REA  
internal column address counter is also incremented (Address = Address + 1) on this falling edge.  
I/O Port: The I/O0 to I/O7 signals are used as a port for transferring address, command, and input data to and output  
data from the device.  
I/O0 to I/O7  
I/O8 to I/O15  
WP#  
I/O Port: The I/O8 to I/O15 signals are used as a port for transferring input data to and output data from the device in  
x16 mode only. I/O8 to I/O15 pins must be low level during address and command input.  
Write Protect: The WP# signal is used to protect the device from accidental programming or erasing. This signal is  
usually used for protecting the data during the power-on/off sequence when input signals are invalid.  
Ready/Busy: The RY/BY# output signal is used to indicate the operating condition of the device. The RY/BY# signal is  
in the Busy state (RY/BY# = L) during the Program, Erase, and Read operations and returns to Ready state (RY/BY# =  
H) after completion of the operation. The output buffer for this signal is an open drain type, allowing the RY/BY# signals  
of multiple memories to be connected such that a single RY/BY# is provided to the system.  
RY/BY#  
V
V
Power: V is the power supply.  
CC  
CC  
SS  
Ground: V is the Ground.  
SS  
NC  
No Connection: Lead is not internally connected.  
DNU  
Do Not Use: Signal may be used for manufacturing purposes and must not be connected in system to any signal level.  
8
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
3. Block Diagram  
V
CC  
SS  
RY/BY#  
4Gb: (4096M + 128M) bit  
2Gb: (2048M + 64M) bit  
1Gb: (1024M + 32M) bit  
V
512 Mb: (512M + 16M) bit  
Flash Array  
Address  
Register  
& Decoders  
Data Register & S/A  
Cache Register  
Y-Decoder  
Command  
Command  
Register  
V
V
CC  
SS  
I/O Buffers & Latches  
Global Buffers  
CE#  
RE#  
WE#  
Control Logic  
& High Voltage  
Generator  
I/00  
Output  
Driver  
I/O7 or I/O15  
CLE ALE  
WP#  
March 30, 2009 S30MS-R_00_06  
S30MS-R ORNANDTM Flash Family  
9
D a t a S h e e t  
4. Device Bus Operation  
Address input, command input, and data input/output are controlled by the CLE, ALE, CE#, WE#, RE# and  
WP# signals, as shown in Table 4.1. The operation modes such as Program, Erase, Read, and Reset are  
controlled by the command operations shown in Table 4.1.  
Table 4.1 Operation Table  
CLE  
ALE  
L
CE#  
L
WE#  
RE#  
H
WP#  
X
Mode  
Command Input  
Address Input  
Sequential Read or Status Output  
H
Read Mode  
L
H
L
L
H
X
L
L
H
X
H
L
L
H
H
H
X
X
X
X
H
Command Input  
Address Input  
Program or Erase  
L
H
L
L
H
L
L
X
Data Input  
X
X
X
X
X
H
X
X
X
X
H
During Program (Busy)  
During Erase (Busy)  
Write Protect  
X
X
H
X
X
X
L
X
0 V or V (1) Stand-by  
CC  
Legend  
H: V , L: V , X: V or V  
IH  
IL  
IH  
IL  
Notes  
1. WP# should be biased to GND or V for lowest standby power.  
CC  
2. In Stand-by mode the device power consumption is lowered to the Stand-by power level only when internal Read, Program, or Erase  
operations are completed. Until all operations are complete the device still draws active level power.  
4.1  
4.2  
CE# Don’t Care Feature  
CE# does not need to be continuously asserted across command and address write operations or during  
busy periods as was required by some earlier generation NAND interface devices.  
Stacked Die Product  
A 4 Gb device is built from two stacked 2 Gb devices. The pinout of the stacked product has a single CE# pin  
and can be addressed as a single die solution.  
In the stacked die product, the most recently activated die accepts the command. The following commands  
do not require an address in order to execute. Before issuing these commands, the system should issue an  
address-carrying-command in order to select the correct die.  
„ ID Read  
„ Read Column Address Change  
„ Reset or Erase Suspend  
„ Status Read  
„ OTP Commands  
When the reset/erase suspend command is issued by the system, the most recently activated die receives  
the command. In the case where the device is erasing, the device suspends erase. In the case where the  
device is not erasing the die resets. Note that only one die will be reset. To reset both die in a stacked die  
product, the reset command should be entered to reset the most recently accessed die. Then an address  
carrying command should be entered to the non-active die. Once the second die has been activated another  
reset command can be entered to reset the second die.  
In addition, when one of two dies is performing some embedded operation, the input command of Program,  
Erase and Read is prohibited.  
10  
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
Amax + 1  
CE#  
Comments  
Device 0 Selected;  
Device 1 Standby  
0
0
Device 1 Selected;  
Device 0 Standby  
1
0
Note  
Amax +1 = A29 for x8 devices and A28 for x16 devices.  
4.3  
WP# Signal Timing  
The state of the WP# signal is checked only at the beginning of a program or erase operation. If WP# is low  
an operation cannot start. The user should keep the WP# pin either high or low during the complete  
command and program/erase operation. The level of the WP# pin may be changed after the erase and/or  
program is complete. The operations are enabled and disabled as shown in the following timing diagrams:  
Figure 4.1 WP# Signal—Low  
[Enable Programming]  
WE#  
[Enable Erasing]  
WE#  
80  
10  
60  
D0  
D
D
IN  
IN  
WP#  
WP#  
RY/BY#  
RY/BY#  
t
(100 ns min)  
t
(100 ns min)  
WW  
WW  
[Disable Programming]  
WE#  
[Disable Erasing]  
WE#  
80  
10  
60  
D0  
D
D
IN  
IN  
WP#  
WP#  
RY/BY#  
RY/BY#  
t
(100 ns min)  
t
(100 ns min)  
WW  
WW  
5. Internal Memory Array Organization  
The Program operation works on page units while the Erase operation works on block units.  
March 30, 2009 S30MS-R_00_06  
S30MS-R ORNANDTM Flash Family  
11  
D a t a S h e e t  
5.1  
Array Organization  
Figure 5.1 Array Organization  
I/O  
4 Gb device  
Page Buffer  
256K pages  
4096 blocks  
64  
2048  
I/O  
2 Gb device  
128K pages  
2048 blocks  
64 pages = 1 block  
Flash Memory  
Array  
1Gb device  
64K pages  
1024 blocks  
512 Mb device  
32K pages  
512 blocks  
8 I/O for x8  
16 I/O for x16  
2112 Bytes  
The memory array is divided into a main memory area and a related spare area. A page consists of 2112  
Bytes in which 2048 Bytes are used for main memory storage and 64 Bytes are used as a spare area for  
redundancy or other uses. Each page is divided into eight segments, four 512-Byte main-area segments and  
four 16-Byte spare-area segments.  
Segment  
Main Area  
512B  
or  
Spare Area  
16B  
Partial Page  
Main Area  
512B  
Spare Area  
16B  
Page  
Main Area  
Spare Area  
8th Segment  
(16B)  
1st Segment  
(512B)  
2nd Segment  
(512B)  
3rd Segment  
(512B)  
4th Segment  
(512B)  
5th Segment 6th Segment 7th Segment  
(16B)  
(16B)  
(16B)  
Block  
Main Area  
Spare Area  
64B Page 0  
2KB Page 0  
Page 0  
2KB Page 63  
64B Page 63  
Page 63  
12  
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
Array  
Density  
4 Gb  
# Blocks  
4096  
Block Size  
128 KB  
Pages per Block  
64  
64  
64  
64  
2 Gb  
2048  
128 KB  
1 Gb  
1024  
128 KB  
512 Mb  
512  
128 KB  
Table 5.1 shows a summary of the addressing for the memory array components.  
Table 5.1 Memory Addressing Key  
Row Address  
Page  
Column Address  
Main  
Spare  
Main  
Page  
Column  
Addres  
s
Spare  
Page  
Segment  
Column  
Addres  
s
Bus  
Block  
Address  
in Block  
Density Width Address  
Main/Spare Area  
Segment  
Blocks  
2 x 2048  
(See Note)  
4 Gb  
4 Gb  
x8  
A29:A18  
A28:A17  
A17:A12  
A16:A11  
A11 (0=Main, 1=Spare)  
A10:A9  
A9:A8  
A8:A0  
A7:A0  
A5:A4  
A4:A3  
A3:A0  
A2:A0  
2 x 2048  
(See Note)  
x16  
A10 (0=Main, 1=Spare)  
2 Gb  
2 Gb  
x8  
x16  
x8  
A28:A18  
A27:A17  
A27:A18  
A26:A17  
A26:A18  
A25:A17  
A17:A12  
A16:A11  
A17:A12  
A16:A11  
A17:A12  
A16:A11  
A11 (0=Main, 1=Spare)  
A10 (0=Main, 1=Spare)  
A11 (0=Main, 1=Spare)  
A10 (0=Main, 1=Spare)  
A11 (0=Main, 1=Spare)  
A10 (0=Main, 1=Spare)  
A10:A9  
A9:A8  
A8:A0  
A7:A0  
A8:A0  
A7:A0  
A8:A0  
A7:A0  
A5:A4  
A4:A3  
A5:A4  
A4:A3  
A5:A4  
A4:A3  
A3:A0  
A2:A0  
A3:A0  
A2:A0  
A3:A0  
A2:A0  
2048  
2048  
1024  
1024  
512  
1 Gb  
A10:A9  
A9:A8  
1 Gb  
x16  
x8  
512 Mb  
512 Mb  
A10:A9  
A9:A8  
x16  
512  
Note  
The 4 Gb device is a two-die stack of the 2 Gb device with each device having the same memory architecture as the 2 Gb.  
An address is loaded through the I/O port over four or five consecutive address write cycles, as shown in  
Tables 5.2 – 5.4. If a fifth address cycle is written to a device that needs only 4 cycles, the fifth address cycle  
is ignored. If a fifth address cycle is not written to a device that needs one the fifth address is treated as  
having a zero value. The Notes for Tables 5.2 – 5.4 and are listed below Table 5.4.  
Table 5.2 (2 Gb and 4 Gb) x 8 device  
2 Gb and 4 Gb I/O0  
I/O1  
A1  
I/O2  
A2  
I/O3  
A3  
I/O4  
A4  
I/O5  
A5  
I/O6  
A6  
I/O7  
A7  
1st Cycle  
2nd Cycle  
3rd Cycle  
4th Cycle  
5th Cycle  
A0  
A8  
A9  
A10  
A11  
L (Note 1)  
A16  
L (Note 1)  
A17  
L (Note 1)  
A18  
L (Note 1)  
A19  
A12  
A20  
A28  
A13  
A14  
A15  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A29 (Note 4)  
L (Note 1)  
L (Note 1)  
L (Note 1)  
L (Note 1)  
L (Note 1)  
L (Note 1)  
Table 5.3 (1 Gb) x 8 device  
1 Gb  
I/O0  
A0  
I/O1  
I/O2  
A2  
I/O3  
A3  
I/O4  
A4  
I/O5  
I/O6  
I/O7  
A7  
1st Cycle  
2nd Cycle  
3rd Cycle  
4th Cycle  
A1  
A9  
A5  
L (Note 1)  
A17  
A6  
L (Note 1)  
A18  
A8  
A10  
A14  
A22  
A11  
A15  
A23  
L (Note 1)  
A16  
L (Note 1)  
A19  
A12  
A20  
A13  
A21  
A24  
A25  
A26  
A27  
March 30, 2009 S30MS-R_00_06  
S30MS-R ORNANDTM Flash Family  
13  
D a t a S h e e t  
Table 5.4 (512 Mb) x8 Addressing  
512 Mb  
1st Cycle  
2nd Cycle  
3rd Cycle  
4th Cycle  
I/O0  
A0  
I/O1  
A1  
I/O2  
A2  
I/O3  
A3  
I/O4  
A4  
I/O5  
A5  
I/O6  
A6  
I/O7  
A7  
A8  
A9  
A10  
A14  
A22  
A11  
A15  
A23  
L (Note 1)  
A16  
L (Note 1)  
A17  
L (Note 1)  
A18  
L (Note 1)  
A19  
A12  
A20  
A13  
A21  
A24  
A25  
A26  
L (Note 1)  
Notes  
1. L = V  
IL.  
2. A0 to A11:Column address (12 bits for 2,112 Bytes).  
A12 to A28: Row address, consists of:  
A12 to A17: Page address in block (6 bits for 64 pages).  
3. A18 to A28: Block address (4 Gb and 2 Gb device: A18 to A28, 11 bits for 2048 blocks; 1 Gb device: A18 to A27, 10 bits for 1024 blocks;  
512 Mb device: A18 to A26, 9 bits for 512 blocks.)  
4. 4 Gb device is same die stack of 2 x 2 Gb devices. Therefore, 4 Gb devices have the same addressing as 2 Gb devices. 4 Gb has one  
single CE#, A29 is used to select any 2 Gb stacked devices to create 4 Gb device.  
The Notes for Tables 5.5 – 5.7 and are listed below Table 5.7.  
Table 5.5 (2 Gb and 4 Gb) x 16 Addressing  
2 Gb and 4  
Gb  
I/O0  
A0  
I/O1  
A1  
I/O2  
A2  
I/O3  
A3  
I/O4  
A4  
I/O5  
A5  
I/O6  
A6  
I/O7  
A7  
I/O8 – I/O15  
L (Note 1)  
L (Note 1)  
L (Note 1)  
L (Note 1)  
L (Note 1)  
1st Cycle  
2nd Cycle  
3rd Cycle  
4th Cycle  
5th Cycle  
A8  
A9  
A10  
L (Note 1)  
A14  
L (Note 1)  
A15  
L (Note 1)  
A16  
L (Note 1)  
A17  
L (Note 1)  
A18  
A11  
A19  
A27  
A12  
A13  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A28 (Note 4)  
L (Note 1)  
L (Note 1)  
L (Note 1)  
L (Note 1)  
L (Note 1)  
L (Note 1)  
Table 5.6 (1 Gb) x 16 Addressing  
I/O8 – I/  
O15  
1 Gb  
I/O0  
I/O1  
A1  
I/O2  
A2  
I/O3  
A3  
I/O4  
A4  
I/O5  
A5  
I/O6  
A6  
I/O7  
A7  
1st Cycle  
2nd Cycle  
3rd Cycle  
4th Cycle  
A0  
A8  
L (Note 1)  
L (Note 1)  
L (Note 1)  
L (Note 1)  
A9  
A10  
A13  
A21  
L (Note 1)  
A14  
L (Note 1)  
A15  
L (Note 1)  
A16  
L (Note 1)  
A17  
L (Note 1)  
A18  
A11  
A19  
A12  
A20  
A22  
A23  
A24  
A25  
A26  
Table 5.7 (512 Mb) x 16 Addressing  
512 Mb  
1st Cycle  
2nd Cycle  
3rd Cycle  
4th Cycle  
I/O0 I/O1 I/O2  
I/O3  
A3  
I/O4  
A4  
I/O5  
A5  
I/O6  
I/O7  
I/O8 – I/O15  
L (Note 1)  
L (Note 1)  
L (Note 1)  
L (Note 1)  
A0  
A8  
A1  
A9  
A2  
A6  
L (Note 1)  
A17  
A7  
A10  
L (Note 1)  
A14  
L (Note 1)  
A15  
L (Note 1)  
A16  
L (Note 1)  
A11 A12 A13  
A19 A20 A21  
A18  
A22  
A23  
A24  
A25  
L (Note 1)  
Notes  
1. L = V  
IL.  
2. A0 to A10:Column address (11 bits for 1,056 words)  
3. A11 to A27: Row address, consists of:  
A11 to A16: Page address in block (6 bits for 64 pages). A17 to A27: Block address (4 Gb and 2 Gb device: A17 to A27: 11 bits for 2048  
blocks; 1 Gb device: A17 to A26: 10 bits for 1024 blocks; 512 Mb device: A17 to A25: 9 bits for 512 blocks.)  
4. 4 Gb device is same die stack of 2 x 2 Gb devices. Therefore, 4 Gb devices have the same addressing as 2 Gb devices. 4 Gb has one  
single CE#, A28 is used to select any 2 Gb stacked devices to create 4 Gb device.  
14  
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
6. Ordering Information  
The ordering part number is formed by a valid combination of the following:  
S30MS  
04G  
R
25  
B
F
W
00  
2
PACKING TYPE  
0
2
3
= Tray  
= 7-inch Tape and Reel  
= 13-inch Tape and Reel  
MODEL NUMBER  
Refer to Table 6.1  
TEMPERATURE RANGE  
W
= Wireless (–25°C to +85°C)  
PACKAGE MATERIAL SET  
A
F
= Standard  
= Pb-Free  
PACKAGE TYPE  
T
= Thin Small Outline Package  
G
= Ball-Grid Array Package  
0.8 mm pitch, 1.0 mm height  
SPEED OPTION Serial Read Access Time  
25 = 25 ns  
PROCESS TECHNOLOGY  
R
= 65 nm MirrorBit® Technology  
FLASH DENSITY  
04G = 4 Gb  
02G = 2 Gb  
01G = 1 Gb  
512 = 512 Mb  
DEVICE FAMILY  
S30MS = 1.8 volt-only, NAND Interface Flash Memory  
Table 6.1 Model Numbers  
Bus Width  
2-bit Detect-1bit Fix ECC Required  
Bad Blocks  
Model Number  
x8  
No  
None  
00  
Up to 2% initial  
No bad blocks during life  
x8  
No  
10  
x8  
Yes  
No  
Maximum 2% over lifetime  
None  
20  
01  
x16  
Up to 2% initial  
No bad blocks during life  
x16  
x16  
No  
11  
21  
Yes  
Maximum 2% over lifetime  
Note  
The first block is guaranteed to be a valid block  
6.1  
Valid Combinations  
Consult your local sales office to confirm availability of specific valid combinations and to check on newly  
released combinations.  
Valid Combinations  
Base Ordering  
Part Number  
Speed  
Option  
Package Type, Material,  
and Temperature Range  
Model  
Number  
Packing  
Type  
S30MS04GR  
S30MS02GR  
0, 3  
(Note 1)  
00, 01,  
10,11,20,21  
25  
TFW  
S30MS01GR  
S30MS512R  
Note  
1. Type 0 is standard. Specify other options as required.  
March 30, 2009 S30MS-R_00_06  
S30MS-R ORNANDTM Flash Family  
15  
D a t a S h e e t  
7. Connection Diagrams  
7.1  
TSOP 48-Pin Pinout  
X16  
X8  
X8  
X16  
NC  
VSS  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
NC  
NC  
NC  
I/O7  
I/O6  
I/O5  
I/O4  
NC  
I/O15  
I/O7  
I/O14  
I/O6  
I/O13  
I/O5  
I/O12  
I/O4  
NC  
RY/BY# RY/BY#  
RE#  
CE#  
RE#  
CE#  
NC  
NC  
NC  
NC  
NC  
DNU  
VCC  
VSS  
NC  
NC  
NC  
DNU  
VCC  
NC  
VCC  
VSS  
NC  
VCC  
VSS  
NC  
NC  
NC  
NC  
NC  
I/O11  
I/O3  
I/O10  
I/O2  
I/O9  
I/O1  
I/O8  
I/O0  
CLE  
ALE  
WE#  
CLE  
ALE  
WE#  
I/O3  
I/O2  
I/O1  
I/O0  
NC  
WP#  
NC  
NC  
WP#  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
VSS  
16  
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
8. Physical Dimensions  
8.1  
48-Pin TSOP  
2X  
0.10  
STANDARD PIN OUT (TOP VIEW)  
2X (N/2 TIPS)  
0.10  
2X  
2
0.10  
5
A2  
1
N
REVERSE PIN OUT (TOP VIEW)  
3
SEE DETAIL B  
A
B
1
N
E
N
2
N
2
+1  
e
9
5
D1  
A1  
N
+1  
N
2
4
2
D
0.25  
2X (N/2 TIPS)  
C
B
SEATING  
PLANE  
A
B
SEE DETAIL A  
0.08MM (0.0031")  
M
C
6
A - B S  
b
7
WITH PLATING  
c1  
(c)  
7
b1  
BASE METAL  
SECTION B-B  
R
(c)  
e/2  
GAUGE PLANE  
0.25MM (0.0098") BSC  
θ°  
PARALLEL TO  
SEATING PLANE  
X
C
L
X = A OR B  
DETAIL A  
DETAIL B  
NOTES:  
Package  
Jedec  
TS/TSR 048  
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).  
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)  
MO-142 (D) DD  
1
2
3
4
MIN  
NOM MAX  
1.20  
Symbol  
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).  
A
A1  
A2  
b1  
b
c1  
c
D
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.  
0.15  
0.05  
0.95  
0.17  
0.17  
0.10  
0.10  
1.00  
0.20  
0.22  
1.05  
0.23  
0.27  
0.16  
0.21  
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF  
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT  
HORIZONTAL SURFACE.  
5
6
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS  
0.15mm (.0059") PER SIDE.  
19.80 20.00 20.20  
18.30 18.40 18.50  
11.90 12.00 12.10  
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE  
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE  
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").  
D1  
E
e
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND  
0.25MM (0.0098") FROM THE LEAD TIP.  
0.50 BASIC  
L
0
R
N
0.50  
0˚  
0.08  
0.60  
0.70  
8˚  
0.20  
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.  
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.  
48  
3355 \ 16-038.10c  
March 30, 2009 S30MS-R_00_06  
S30MS-R ORNANDTM Flash Family  
17  
D a t a S h e e t  
9. Device Operation  
9.1  
Commands  
Table 9.1 Command Table  
Command Accepted  
During Busy State  
Function  
1st Cycle  
00h  
2nd Cycle  
30h  
31h  
32h  
33h  
35h  
—
Page Read  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
Yes  
Yes  
No  
No  
No  
No  
No  
No  
Partial Page Read  
00h  
Pipeline Read - Full Page  
Pipeline Read - Full Page No Additional Requests  
Read for Page Duplicate  
ID Read  
00h  
00h  
00h  
90h  
Page Program  
80h  
10h  
15h  
10h  
—
Cache Program  
80h  
Page Duplicate Program  
Data Input for Column Address Change  
Read Column Address Change  
Block Erase/Erase Resume  
Reset or Erase Suspend  
Status Read  
85h  
85h  
05h  
E0h  
D0h  
—
60h  
FFh  
70h  
—
OTP Area Overlay  
B0h  
B0h  
B0h  
B0h  
B0h  
B0h  
00h  
01h  
02h  
03h  
04h  
05h  
OTP Area Remove  
OTP Page Protection Status  
OTP Area Default as Overlay  
OTP Area Default as Removed  
OTP Protect Page  
Notes  
1. Random Data Input/Output can be executed in a page or a partial 1/4 page.  
2. Input of a command (other than those specified above) is prohibited. If an unknown command is entered during the command cycle is  
undefined. A reset command may be required to return the device to a known idle state.  
3. During the Busy state, input commands are restricted to 70h and FFh.  
4. During Erase Suspend, the FFh command is restricted. All other commands are prohibited.  
18  
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
9.2  
Power On and Power Off  
During power transitions the control signals are don't care and data is protected while VCC is below 1.6 V.  
After VCC exceeds 1.6 V the device performs internal initialization operations. The maximum VCC ramp rate is  
1 V/400 µs. Exceeding 1 V/400 µs, will require power to be removed and the device to be powered up  
correctly.  
During the VCC ramp period, the VCC power supply current is IBOOT. Refer to DC Characteristics on page 37  
for the value of IBOOT  
.
Figure 9.1 Power-On/Off Sequence  
tWW  
1.7 V  
1.6 V  
1.7 V  
1.6 V  
V
CC  
0 V  
Don’t  
Care  
Don’t  
Care  
WE#, CE#,  
CLE, ALE  
Don’t  
Care  
Don’t  
Care  
RE#  
WP#  
t
PRE  
10 µs  
Operation  
Don’t  
Care  
Don’t  
Care  
RY/BY#  
During power transitions the control signals do not affect the device state while VCC is below 1.6 V. When  
VCC reaches 1.6 V, the device is above its lockout voltage and the control pins must follow the timing diagram  
in Figure 9.7. During this time CE# must remain high because the device cannot receive commands until the  
state machine is active.The RD/BY# pin will go low and indicate when the state machine is active. It is  
recommended that the WP# pin remain low during this time to protect the data during voltage stabilization.  
At power-off WP# should be utilized to protect the device during the power transition. It is recommended to  
assert WP# low tWW before VCC begins the ramp down.  
March 30, 2009 S30MS-R_00_06  
S30MS-R ORNANDTM Flash Family  
19  
D a t a S h e e t  
9.2.1  
Power-On Read  
During the power-on sequence the device will automatically load data into the output buffers. This feature  
enables the system to read boot code without issuing any commands, which is generally used for shadowing  
architectures that require automatic boot code download into buffer RAM.  
To use this feature the system must wait tPRE after VCC has sustained 1.6 V during the power ramp. The  
system can also determine that the data is loaded by monitoring the RD/BY# pin or by monitoring the status  
register. At power-on the state machine will become active 10 µs after ramp causing the RD/BY# pin to go  
low and the device status to show active. When the data is loaded into the register the device go to a standby  
state.  
The default state for the device is to load page 0 into the output buffers, but it is also possible to configure the  
device so that it will load OTP data into the buffers at power-on. Refer to Section 9.10 for more information on  
using default OTP overlay to read OTP data in the power-on sequence.  
9.3  
ID Read  
The ID Read command may be used to identify the manufacturer, type, density, and other features of the  
device. The 90h command is issued, followed by a single address cycle of value zero. Then a sequence of  
words or bytes may be read to identify the device. For devices with word (16-bit) wide data bus the ID  
information appears in the lower byte of the data bus on I/O0-I/O7, I/O8-I/O15 are undefined. Each toggle of  
the RE# signal delivers a new word or byte depending on the device data bus width. The meaning of the ID  
byte sequence is shown in Table 9.2 on page 20 through Table 9.5 on page 21. Data read beyond the fifth  
byte is undefined.  
Figure 9.2 ID Read Operation  
2nd  
byte  
3rd  
byte  
4th  
byte  
5th  
byte  
I/O  
00h  
01h  
90h  
Table 9.2 ID Byte Settings Summary  
Byte  
Description  
Hex Data  
1st Byte  
Maker Code  
01h  
81h  
91h  
A1h  
B1h  
AAh  
BAh  
CCh  
DCh  
11h  
00h  
22h  
00h  
512 Mb (x8)  
512 Mb (x16)  
1 Gb (x8)  
1 Gb (x16)  
2nd Byte  
Device Code 1st Byte  
2 Gb (x8)  
2 Gb (x16)  
4 Gb (x8)  
4 Gb (x16)  
ECC/ECC-Free  
3rd Byte  
4th Byte  
5th Byte  
6th Byte  
Device Code 2nd Byte  
Block Size, Simultaneous Programmed Pages, RFU  
Page Size, Spare Size, RFU  
RAM and Other MCP identifiers  
Note  
In x16, I/O 15 – I/O 8 = 00h  
20  
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
Table 9.3 4th ID Byte  
Description  
I/O 7  
X
I/O 6  
X
I/O 5  
X
I/O 4  
I/O 3  
I/O 2  
0
I/O 1  
0
I/O 0  
0
Block Size: 128 KBytes  
Block Size: 512 KBytes  
X
X
X
0
0
1
1
X
X
X
0
1
0
1
X
X
X
0
0
1
Block Size: 2048 KBytes  
X
X
X
0
1
0
1
2
4
8
X
X
X
X
X
X
X
X
X
X
X
X
Number of simultaneously programmed pages  
X
X
X
X
X
X
X
X
X
X
X
X
Table 9.4 5th ID Byte  
Description  
Page Size: 512 Bytes  
Page Size: 1024 Bytes  
Page Size: 2048 Bytes  
Page Size: 4096 Bytes  
Page Size: 8192 Bytes  
Spare Size: 0 Bytes  
Spare Size: 8 Bytes  
Spare Size: 16 Bytes  
Spare Size: 32 Bytes  
Spare Size: 64 Bytes  
I/O 7  
X
I/O 6  
X
I/O 5  
X
I/O 4  
X
I/O 3  
I/O 2  
0
I/O 1  
I/O 0  
X
X
X
X
X
0
0
0
0
1
X
X
X
X
0
X
X
X
X
0
1
0
X
X
X
X
0
1
1
X
X
X
X
1
0
0
X
X
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
X
X
X
0
1
0
X
X
X
0
1
1
X
X
X
1
0
0
X
Table 9.5 6th ID Byte  
Description  
I/O 7  
I/O 6  
I/O 5  
I/O 4  
I/O 3  
I/O 2  
I/O 1  
I/O 0  
RAM and Other MCP Identifiers:  
Reserved for Future Use  
X
X
X
X
X
X
X
X
March 30, 2009 S30MS-R_00_06  
S30MS-R ORNANDTM Flash Family  
21  
D a t a S h e e t  
9.3.1  
Read Mode  
During a read operation the device transfers one page of data from the memory array to a page buffer. After  
the data is transferred it is available for sequential byte/word access through a sequential read operation as  
shown in Table 4.1 on page 10.  
See Figure 9.3 on page 22 for timing details.  
The Read Column Address Change command allows the system to read from any location within a page, and  
may be issued multiple times by four or five address write cycles, depending on the device density, followed  
by a 31h command.  
A partial page read loads one main array area segment and its related spare area (512 + 16 Bytes) into the  
page buffer as shown in Table 9.6 on page 25. Because less data is loaded from the memory array a partial  
page read offers faster access time than a full page read.  
In a partial page read, if the address of the 1st segment is chosen, the 1st (Main) and 1st (Spare) segments  
data are loaded to the output buffer together. The 5th segment data is read out following the 1st segment  
data.  
Figure 9.3 Read Mode  
CLE  
CE#  
WE#  
ALE  
RE#  
Busy  
RY/BY#  
I/O  
Column Address A  
Page Address  
P
00h  
n
30h  
A
A+1  
A+2  
Page Address P  
Start-address input  
A data transfer operation from the cell array to the  
page buffer starts on the rising edge of WE# in the  
30h command input cycle (after the address  
information has been latched). The device is in  
Busy state during this transfer period.  
After the transfer period the device returns to  
Ready state. Serial data can be output  
A
Select  
page  
P
Cell array  
x8: n=2112 Bytes  
x16: n=1056 Words  
synchronously with the RE# clock from the start  
pointer designated in the address input cycle.  
Note  
1 Gb and 512 Mb devices require four cycles to load the addresses. An additional page address is needed for 2 Gb and 4 Gb devices.  
22  
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
Figure 9.4 Column Address Change Read  
CLE  
CE#  
WE#  
ALE  
RE#  
RY/BY#  
Busy  
Col. A  
E0h  
A’+4  
A
A+1 A+2 A+3  
A’+1  
A’+2 A’+3  
Page A  
30h  
05h  
00h  
A’  
I/O  
Col. A  
Page P  
Col. A’  
Page P  
Start from Col. A  
Start from Col. A'  
Start-address input  
A
During the serial data output from the register  
the column address can be changed by inputting  
a new column address using the 05h and E0  
commands. The data is read out in serial starting  
at the new column address. Random column  
address Change operation can be done multiple times  
within the same page.  
A’  
Select page  
P
Cell array  
Note  
1 Gb and 512 Mb devices require four cycles to load the addresses. An additional page address is needed for 2 Gb and 4 Gb devices.  
9.4  
Pipeline Read  
Pipeline read is a feature that caches sequential or random pages to achieve higher sustained read rates.To  
use pipeline read, the system should initiate a read command for page X. After RY/BY# goes high and prior to  
reading data from the device, the pipeline read command can be issued for a subsequent page X+1 to load  
into the cache. Once the Pipeline read command, 32h, has been entered the system can read page X from  
the output while the secondary buffer is loaded with page X+1. This command sequence can be repeated to  
sequentially read pages until the command entry for the final page.  
The address load command (00h) stops the prior read from page X and transfers the next page X+1 from the  
cache register to the output buffer. To continue with pipeline read the 32h input should be entered after the  
address input. If the system is on the final read cycle, a dummy address followed by 33h should be entered to  
indicate that the final page can be loaded to the buffer without a subsequent address load command.  
Pipeline Read is recommended for use with full pages. In the case where less than half of the page is read in  
a cycle, the system must wait 25us between entry of the Pipeline Read Command (32h) and the subsequent  
address load command (00h).  
Pipeline Read synchronization can be achieved by either monitoring RY/BY# or with the status read  
command. Please refer to Figure 9.5 when using RY/BY# and Figure 9.6 when using Status Read  
Command.  
March 30, 2009 S30MS-R_00_06  
S30MS-R ORNANDTM Flash Family  
23  
D a t a S h e e t  
Figure 9.5 Pipeline Read Mode  
tPT  
tR  
RY/BY#  
I/O  
Data  
Output  
Address  
Input  
Address  
Input  
00h  
00h  
30h  
32h  
Data from Page X  
Col Add & Row Add  
Page X  
Col Add & Row Add  
Page X+1  
Repeat as necessary  
tPT  
tPT  
RY/BY#  
I/O  
Data  
Output  
dummy  
addresses  
Data  
Output  
Address  
Input  
00h  
00h  
32h  
33h  
Data from Page X+n  
Col Add & Row Add  
Page X+n  
Data from Page X+n-1  
Figure 9.6 Pipeline Read Mode without RY/BY#  
Data  
Output  
Address  
Input  
Address  
Input  
I/O  
00h  
00h  
Status  
30h  
70h  
00h  
Status  
32h  
70h  
Data from Page X  
Col Add & Row Add  
Page X  
Col Add & Row Add  
Page X+2  
I/O 5 (True) = 0, Busy  
I/O 6 (Cache) = 0, Busy  
= 1, Ready  
= 1, Ready  
Data  
Output  
Dummy  
addresses  
Address  
Input  
Data  
Output  
I/O  
00h  
Status  
00h  
Status  
33h  
70h  
32h  
70h  
00h  
00h  
Data from Page X+n  
Col Add & Row Add  
Page X+n  
Data from Page X+n-1  
I/O 6 (Cache) = 0, Busy  
= 1, Ready  
I/O 6 (Cache) = 0, Busy  
= 1, Ready  
9.5  
Page Program  
The device conducts a Page Program operation when it receives a 10h Program confirm command after the  
address and data are input. The sequence of command and address and data input is shown below. (See  
Figure 9.7.)  
Partial page programming is allowed for this device. A page is divisible into eight segments and each  
segment may be programmed individually or in any combination of segments simultaneously. For example, in  
x8 devices the first data segment of 512 bytes and the first spare area segment of 16 bytes, are  
programmable at the same time. Table 9.6 describes the page segments:  
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Table 9.6 Page Segments  
x8  
x16  
Data Area (Segment)  
512 Bytes x 4 Segments/Page (Column Address)  
1st  
2nd  
3rd  
4th  
0 to 511  
0 to 255  
256 to 511  
512 to 767  
768 to 1023  
512 to 1023  
1024 to 1535  
1536 to 2047  
Spare Area  
(Segment)  
16 Bytes x 4 Segments/Page (Column Address)  
5th  
6th  
7th  
8th  
2048 to 2063  
2064 to 2079  
2080 to 2095  
2096 to 2111  
1024 to 1031  
1032 to 1039  
1040 to 1047  
1048 to 1055  
The maximum number of consecutive partial page program operations allowed in the same segment is one.  
Each of the eight segments may be programmed once before a block erase is required. Once a segment is  
programmed, any subsequent writes to the same segment without erase causes the initial data in the  
segment to become invalid. The data written during the second write will be valid.  
The device also supports random data programming within a page by using the random data input command  
(85h). Random data input requires the command to be entered between column addresses during the page  
program command cycle. Once the new column address is entered, the system can continue the page  
program command cycle by entering the page address and the data. The Page Program confirm command  
(10h) initiates the programming operation.  
Once the program operation starts, the Read Status Register command may be entered to read the status  
register. The system controller can detect the completion of a program cycle by monitoring the RY/BY#  
output, or the Status bit (I/O5) of the Status Register. When the Page Program is complete, the Status Bit  
(I/O0) may be verified. The internal write verify detects only errors for 1s that are not successfully  
programmed to 0s. The command register remains in Read Status command mode until another valid  
command is written to the command register.  
Only the Read Status command and Reset command are valid while programming is in progress. Entering  
any other command puts the device into an unknown state.  
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Figure 9.7 Page Program  
CLE  
CE#  
WE#  
ALE  
RE#  
RY/BY#  
I/O  
Din Din Din  
70h  
80h  
Din  
10h  
Col. A  
Data input  
Page P  
Data  
The data is transferred (programmed) from the page  
buffer to the selected page on the rising edge of WE#  
following input of the 10h command. After programming,  
the programmed data is transferred back to the register  
to be automatically verified by the device. If the  
programming does not succeed, the Program/Verify  
operation is repeated by the device until success is  
achieved or until the maximum loop number set in  
the device is reached.  
Program  
Read and verification  
Once the Serial Input command 80h is input, the only acceptable commands are the programming  
commands 10h, 85h or the Reset command FFh. If any other input command is used, the program operation  
is not performed and the device must be reset.  
Figure 9.8 Serial Input Command Sequence Error  
80  
XX  
10  
Command other than  
"10H","85H" or "FFH"  
9.6  
Cache Program  
Cache Program is a double buffer scheme for faster programming. The Cache buffer size is identical to the  
page buffer size (2112 B). Data may be written into the cache register while other data previously stored in  
the page buffer are programmed into the memory array.  
After writing the first set of data (up to 2112 B) into the cache register, the Cache program command (15h)  
must be entered instead of the standard Page Program command (10h) in order to free up the cache register  
and start the internal program operation. When data is transferred from the cache register to the data register,  
the device remains in the Busy state for a short period of time (tCBSY) then the cache register is ready for the  
next data-input. The Read Status command (70h) may be issued to verify that the cache register is ready by  
polling the Cache-Busy status bit (I/O6). Pass/Fail status of the previous page is available upon the return to  
the Ready state. When the next set of data is input with the Cache Program command, tCBSY is affected by  
the progress of pending internal programming. The programming of the cache register is initiated only when  
the pending program cycle is finished and the data register is available for the transfer of data from the cache  
register. The status bit (I/O5) for internal Ready/Busy may be polled to identify the completion of internal  
programming.  
If the system monitors the progress of programming with RY/BY# only, the last page of the target  
programming sequence must be programmed with Page Program command (10h). Alternatively, if the last  
page to be programmed is accomplished using the Cache Program command (15h), status bit (I/O5) must be  
polled to verify that the last program is actually finished before starting other operations.  
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Following the Cache Program Command (15h), the pass/fail status information is available as follows:  
1. I/O1 returns the status of the previous page (when ready or when the I/O6 bit is changing to a 1).  
2. I/O0 returns the status of the current page (upon true ready, or when the IO5 bit is changing to a 1).  
3. I/O0 and I/O1 may be read together.  
The WP# signal is either low during the entire cache program sequence to lock all the programs or it is high to  
allow programming. The WP# signal needs to be fixed before the first cache program command is input.  
Please refer to WP# Signal Timing on page 11.  
Figure 9.9 Cache Program with RY/BY# Only Monitored  
tPROGL  
tCBSY1  
tCBSY2  
tCBSY2  
RY/BY#  
I/O  
Address &  
Data Input  
Address &  
Data Input  
Address &  
Data Input*  
Address &  
Data Input  
80h  
70h  
10h  
80h  
15h  
80h  
80h  
15h  
15h  
Col Add1,2  
& Row Add1,2 or 3  
Data  
Col Add1,2  
& Row Add1,2 or 3  
Data  
Col Add1,2  
& Row Add1,2 or 3  
Data  
Col Add1,2  
& Row Add1,2 or 3  
Data  
Figure 9.10 Cache Program Monitored by Status Register  
tCBSY1  
tCBSY2  
tCBSY2  
RY/BY#  
Address &  
15h  
Status  
output  
Address &  
Data Input  
Status  
output  
Address &  
Data Input  
I/O  
80h  
80h  
80h  
70h  
15h  
70h  
15h  
Data Input  
Col Add1,2  
Col Add1,2  
Col Add1,2  
& Row Add1,2 or 3  
Data  
& Row Add1,2 or 3  
Data  
& Row Add1,2 or 3  
Data  
tCBSY2  
Address &  
Data Input  
Status  
70h  
Status  
output  
Status  
output  
80h  
70h  
15h  
output  
Col Add1,2  
& Row Add1,2 or 3  
Data  
Check I/O1 for pass/fail  
Check I/O5 for internal ready/busy  
Check I/O0,1 for pass/fail  
Note  
Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous  
program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous  
cycle, which can be expressed as the following formula: t  
command time + data loading time of last page).  
= Program time of last page + program time of the (last -1) page - (program  
PROG  
9.7  
Page Duplicate Program  
The Page Duplicate program is configured to quickly and efficiently rewrite data stored in one full page to  
another page location without utilizing external memory. Since the time-consuming serial access and re-  
loading cycles are removed, the system performance is improved. The benefit is especially obvious when a  
portion of a block is updated and the block also needs to be copied to the newly assigned free block. A Page  
Duplicate program operation is performed by first initiating a read operation with command 35h and the  
address of the source which then duplicates the whole 2112 Byte data into the internal data buffer. As soon  
as the device is ready, the Program Confirm command (10h) is required to actually begin the programming  
operation to the address of the destination page. Once the Page Duplicate Program is finished, any additional  
partial page programming into the copied pages is prohibited before erasure.  
The data input cycle for modifying a portion or multiple distant portions of the source page is allowed as  
shown in Figure 9.11 on page 28.  
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Figure 9.11 Page Duplicate Program Operation  
tR  
tPROG  
RY/BY#  
I/O  
Add.(4Cycles)  
Pass  
00h  
35h  
Add.(4Cycles)  
10h  
I/O0  
Fail  
85h  
70h  
Col. Add1,2 & Row Add1,2 or 3  
Destination Address  
Col. Add1,2 & Row Add1,2 or 3  
Source Address  
Figure 9.12 Page Duplicate Program Operation with Random Data Input  
tPROG  
tR  
RY/BY#  
I/O  
Add.(2Cycles)  
Col Add1,2  
Add.(4Cycles)  
35h  
Add.(4Cycles)  
70h  
00h  
85h  
Data  
85h  
Data  
10h  
Col. Add1,2 & Row Add1,2 or 3  
Source Address  
Col. Add1,2 & Row Add1,2 or 3  
Destination Address  
There is no limitation for the number of repetition.  
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9.8  
Block Erase and Erase Suspend  
The Block Erase command sequence starts with the block erase setup command 60h, followed by two or  
three cycles of row address, followed by the block erase execute command D0h. Note that the page address  
part of the row address is ignored.  
The Block Erase operation starts on the rising edge of WE# during the erase execute command. However,  
the Erase operation will not start if WP# is Low at this time or if the Erase command is addressing the OTP  
area after any OTP page has been protected.  
Once tPRESUS has elapsed, the Erase operation can be suspended by writing the Erase Suspend Command,  
FFh. RY/BY# or the status register may be monitored to determine when the erase is suspended, the device  
is ready, and it is safe to proceed with other commands. An Erase command with any address resumes the  
suspended Erase operation.  
During Erase suspend any command operation on the erase block, except erase, is ignored. The following  
command operations in any other block are allowed:  
„ Full or partial page read  
„ Full or partial page program  
„ Read for page duplicate  
„ Page duplicate program  
„ Program Address or Data Change  
„ Read Column Address Change  
„ Read Status  
„ ID Read  
Commands ignored during erase suspend:  
„ Pipeline Read  
„ Cache Program  
„ OTP Enter and Exit  
The Reset or Erase Suspend command is prohibited during erase supend.  
Figure 9.13 Block Erase  
Pass  
I/O  
60  
D0  
Erase Execute  
70  
Block Address  
input: 2 or 3 cycles  
Status Read  
command  
Fail  
command  
Busy  
RY/BY#  
Figure 9.14 Erase Suspend Operation  
tPRESUS  
tPRESUS  
Pass  
FF  
60  
D0  
I/O  
Command(a)  
I/O  
60  
Block Address P  
Input: 2 or 3 cycles  
D0  
70  
Block Address don't care  
Input: 2 or 3 cycles  
Fail  
Busy  
Busy  
RY/BY#  
Busy  
Internal  
Condition  
Block P Erase  
Block P Suspend  
Other command  
operation  
Block P Erase  
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9.9  
9.9.1  
Status  
Status Read  
The device contains a Status Register which may be read to find out whether a program or erase operation is  
completed, and whether the program or erase operation completed successfully. After writing a 70h  
command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on  
the falling edge of CE# or RE#, whichever occurs last. The control by two lines allows the system to poll the  
progress of each device in multiple device connection even if the RY/BY# pins are common wired. RE# or  
CE# does not have to be toggled for update status. Refer to Table 9.7 for specific Status Register definitions.  
The command register remains in Status Read mode until further commands are issued. Therefore, if the  
status register is read during a random read cycle, the read command (00h) should be given before starting  
read cycles. The Status Register clears after another valid command is entered, excluding a status read. An  
application example with multiple devices is shown in Figure 9.15.  
Table 9.7 Status Register Table  
During Program/  
I/O  
Erase  
Page Program  
Block Erase  
Cache Program  
Read  
Pipeline Read  
Definition  
0 = Pass;  
1 = Fail  
I/O 0  
Reserved  
Pass/Fail  
Pass/Fail  
Pass/Fail(N)  
Reserved  
Reserved  
Completed/  
Suspended  
(Note 3)  
0 = Pass, Completed;  
1 = Fail, Suspend  
I/O 1  
Reserved  
Reserved  
Pass/Fail(N-1)  
Reserved  
Reserved  
I/O 2  
I/O 3  
I/O 4  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
True Ready/  
Busy  
0 = Busy;  
1 = Ready  
I/O 5  
I/O 6  
Busy  
Busy  
True Ready/Busy  
Ready/Busy  
Ready/Busy  
Write Protect  
True Ready/Busy  
Ready/Busy  
Ready/Busy  
Write Protect  
Cache Ready/Busy  
(Note 1)  
Cache Ready/Busy  
(Note 1)  
Cache Ready/  
Busy (Note 4)  
0 = Busy;  
1 = Ready  
0 = Protected;  
1 = Unprotected  
I/O 7  
Reserved  
Write Protect  
Write Protect  
Write Protect  
Notes  
1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.  
2. I/Os defined as reserved are recommended to be masked out when Read Status in being executed.  
3. During an Erase suspended operation, I/O 1 will be able to hold the status which is in the Erase suspended condition, even if new a command is inputted.  
4. True Ready/Busy represents internal the read operation status which is being executed in pipeline read mode.  
Figure 9.15 Multiple Devices  
CE(1)#  
CE(2)#  
CE(N)#  
ALE  
CLE  
WE#  
RE#  
Device(1)  
Device(2)  
Device(N)  
n
I/On  
RY/BY#  
If the RY/BY# pin signals from multiple devices are wired together as shown in Figure 9.15, the Status Read  
function can be used to determine the status of each individual device.  
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Figure 9.16 Status Read Timing Application Example  
RY/BY#  
CLE  
Busy  
V
IL  
ALE  
WE#  
CE1#  
CEN#  
RE#  
I/O  
70H  
70H  
Status on Device 1  
Status on Device N  
9.9.2  
9.9.3  
Status After Power On or Reset  
After Reset or Device power up the device goes through a power-on sequence as described in Section 9.2.  
After tPRE has passed the status register will be in its cleared state. In the cleared state the status bits read  
60h if WP# is Low or they will read E0h if WP# is high. This state indicates that internal operations are  
complete and the device is ready to accept commands  
Status of Read, Program, or Erase  
„ Once a Read Program, or an Erase process starts, the Read Status Register command may be entered,  
followed by RE# and CE# Low, to read the status register.  
„ The system controller can detect the completion or failure of an operation by monitoring the RY/BY#  
output, or the Status bits (IO6 and IO5) of the Status Register.  
– RY/BY# is High during Ready and Low during Busy.  
– IO6 and IO5 are High during Ready and Low during Busy.  
– All other Status Bits are Reserved during Busy.  
„ Only the Read Status command and Reset command are valid while an operation is in progress.  
„ Successful completion, suspend, or failure of an operation results in a return to ready status.  
„ When the device is Ready (RY/BY#, IO6, and IO5 are High) the Write Status Bit (IO0) and Suspend Status  
Bit (IO1) may be checked  
– If Erase was the last operation before the device became ready, IO1 is Low if the Erase is completed  
and High if the Erase is suspended.  
– IO 0 is High if Program (or Erase) Error, or Low if Successful.  
„ The Status Register clears after another Execution command is entered.  
All 6 OTP commands will also clear the status registers because an embedded program occurs inside the  
device.  
Execution commands replace the status of the last operation with status of the operation initiated by the  
execution command. Execution commands are the commands that initiate a new operation. These are  
30h, 31h, 32h, 33h, 35h, 10h, D0h, and FFh. However, the cache program execution command 15h clears  
only the N–1 (I/O 1) status and shifts the N (I/O 0) status to the N–1 status position. The Page register  
Ready/Busy (I/O 5) and Cache Register Ready / Busy (I/O 6) status bits remain valid.  
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Figure 9.17 RY/BY# During Program/Erase  
tPROG  
RY/BY#  
Pass  
I07 – IO0  
I/O0  
Fail  
Address & Data Input  
70h  
2nd  
Command  
1st  
Command  
9.9.4  
Status Read During a Read Operation  
Figure 9.18 Status Read During a Read Operation  
00  
[A]  
30  
00  
70  
command  
CE#  
WE#  
BRYY#/  
RE#  
2nd Cycle of  
the Read Command  
Address N  
Status Read  
command input  
Status Read  
Data output  
The device status can be read by writing the Status Read command 70h in Read mode.  
Once the device is set to Status Read mode by a 70h command, the device does not return to Read mode.  
However, when the Read command 00h is written during [A], the Status mode is reset and the device returns  
to Read mode. In this case, data output starts automatically from address N and address input is  
unnecessary.  
When reading another page (example, address M), the following command patterns will be allowed;  
(1) 00h --- Address N --- 30h --- 70h --- FFh --- 00h --- Address M --- 30h --- RE# toggle  
(2) 00h --- Address N --- 30h --- 70h --- 00h --- 00h --- Address M --- 30h --- RE# toggle  
(3) 00h --- Address N --- 30h --- 70h --- 00h --- RE# toggle --- 00h --- Address M --- 30h --- RE# toggle  
(4) 00h --- Address N --- 30h --- 70h --- 00h --- Address M --- 30h --- RE# toggle  
In these cases, from the last 30h, the page data of Address M is read out by the RE# toggle.  
A pull-up resistor must be used for termination because the RY/BY# buffer consists of an open drain circuit.  
Figure 9.19 RY/BY#: Termination for the Ready/Busy Pin (RY/BY#)  
VCC  
VOL=0.1V, VOH= VCC - 0.1V  
Read y  
VCC  
VOH  
VCC  
R
VOL  
Busy  
VOL  
Device  
RY/BY#  
CL  
t
r
t
f
VSS  
VCC max - VOL  
R =  
=
IOL + IL  
1.85 V  
This data may vary from device to device.  
Use this data as a reference when selecting a  
resistor value.  
3 mA + IL  
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9.10 OTP  
The device includes a One Time Protection (OTP) area of memory separate from the normal memory array  
that may be permanently locked to secure data. The OTP area contains 8 pages, each of which can be  
individually locked to prevent program or erase. The commands for the OTP area are shown in Table 9.1.  
The system accesses the OTP pages by overlaying them into block 0 of the Main Array. The OTP default  
commands determine the OTP overlay status at power-on for the life of the device. Once one of the OTP  
default overlay commands is entered, the default cannot be changed. It is recommended that the OTP default  
be set during factory programming to prevent the default overlay from being changed after the device leaves  
the factory.  
If the system does not want the OTP overlayed at power-on, the “OTP Default as Removed” command should  
be issued during factory programming. To set the device so that the OTP area is overlayed at power-on, the  
system must issue the “OTP Area Default as Overlay” during factory programming. This is the configuration  
that should be used for systems that utilize the power-on read feature for boot. In this configuration, Pages 8  
through 63 of block 0 will not be accessible.  
Once the default is set, the OTP overlay can be adjusted using the “OTP Area Overlay” and “OTP Area  
Remove Commands”. These commands allow the system to determine whether the addresses for block 0 will  
map to the OTP pages or main array pages.  
The “OTP Page Protect” command is used to individually lock the pages and prevent further programming.  
After one of the OTP pages is protected, none of the remaining OTP pages are able to erase, since they are  
all part of the same block. The remaining unlocked pages can be programmed and they must be individually  
locked to secure the data from being overwritten. It is recommended that the pages be protected after they  
are programmed.  
Figure 9.20 OTP Commands  
First OTP  
command write  
Second OTP  
command write  
First OTP area related  
command write  
B0h  
XXh  
XXh  
Figure 9.21 OTP Page Protect Command Sequence Diagram  
Address  
05h  
80h  
10h  
B0h  
RY/BY#  
t
OTPD  
Figure 9.22 OTP Command (Page Protection Status) Timing Diagram  
tCLS tCLS  
tCLS  
CLE  
CE#  
tCLH  
tCH  
tCLH  
tCH  
tCLH  
tCH  
tCS  
tCS  
tCS  
tWP  
tWP  
tWP  
tWB  
tWC  
WE#  
ALE  
tALS  
tALS  
tALS  
tALH  
tALH  
tALH  
tDS  
tDS  
tDS  
tDH  
tDH  
tDH  
0#h  
Command  
I/O  
B0h  
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Note  
0#h is 2nd cycle command for OTP. # is 2.  
Figure 9.23 OTP Command (Overlay/Remove) Timing Diagram  
tCLS  
tCLS  
tCLS  
CLE  
CE#  
tCLH  
tCH  
tCLH  
tCH  
tCLH  
tCH  
tCS  
tCS  
tCS  
tWR  
tWP  
tWP  
tWP  
tWB  
tWC  
WE#  
ALE  
tALS  
tALS  
tALS  
tALH  
tALH  
tALH  
tDS  
tDS  
tDS  
tDH  
tDH  
tDH  
0#h  
Command  
I/O  
B0h  
tOTP  
RY/BY#  
Note  
0#h is 2nd cycle command for OTP. # is 0 or 1.  
Figure 9.24 OTP Command (Default as Overlay/Default as Removed) Timing Diagram  
tCLS  
tCLS tCLS  
CLE  
CE#  
tCLH  
tCH  
tCLH  
tCH  
tCLH  
tCH  
tCS  
tCS  
tCS  
tWR  
tWP  
tWP  
tWP  
tWB  
tWC  
WE#  
ALE  
tALS  
tALS  
tALS  
tALH  
tALH  
tALH  
tDS  
tDS  
tDS  
tDH  
tDH  
tDH  
0#h  
Command  
I/O  
B0h  
tOTPD  
RY/BY#  
Note  
0#h is 2nd cycle command for OTP. # is 3 or 4.  
34  
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D a t a S h e e t  
9.11 Reset  
The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally  
generated voltage is discharged to 0 V and the device enters standby.  
The response to an FFh Reset command input during the various device operations is shown in Figure 9.25  
to Figure 9.29.  
Figure 9.25 Reset (FFh) Command Input During Programming  
80  
10  
FF  
00  
00  
00  
Internal VPP  
RY/BY#  
tRST (Max 1 μs)  
Figure 9.26 Reset (FFh) Command Input During Erasing  
D0  
FF  
Internal  
erase  
voltage  
RY/BY#  
tSuspend (15 μs)  
Figure 9.27 Reset (FFh) Command Input During a Read Operation  
00  
FF  
RY/BY#  
tRST (Max 1 μs)  
Figure 9.28 Status Read Command (70h) Input After a Reset  
FF  
70  
I/O status:  
Pass/Fail  
Ready/Busy  
Pass  
Ready  
RY/BY#  
I/O status:  
Ready/Busy  
FF  
70  
Busy  
RY/BY#  
Figure 9.29 Two or More Reset Commands Input in Succession  
(1)  
FF  
(2)  
FF  
(3)  
FF  
RY/BY#  
FF  
The second  
command  
is accepted but may or may not  
extend the Busy status time.  
March 30, 2009 S30MS-R_00_06  
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35  
D a t a S h e e t  
10. Electrical Specifications  
10.1 Absolute Maximum Ratings  
Table 10.1 Absolute Maximum Ratings  
Parameter  
Symbol  
Rating  
Unit  
V
–0.5 to V + 0.5  
CC  
IN/OUT  
Voltage on any pin relative to V  
V
SS  
V
–0.5 to + 2.5  
–65 to +150  
–25 to +85 (Wireless)  
–65 to +125  
5
CC  
Storage Temperature  
Operating Temperature  
Temperature under bias  
Short circuit current  
1. Notes  
T
°C  
°C  
STG  
OPR  
BIAS  
T
T
°C  
I
mA  
OS  
2. Minimum DC voltage is –0.6 V on input/output pins. During transitions, this level may undershoot to –2.0 V for periods < 30 ns.  
3. Maximum DC voltage on input/output pins is V +0.3 V which, during transitions, may overshoot to V +2.0 V for periods < 20 ns.  
CC  
CC  
4. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the  
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended  
periods may affect reliability.  
10.2 Recommended DC Operating Conditions  
Table 10.2 Recommended DC Operating Conditions  
Parameter  
Symbol  
Parameter  
Description  
Min.  
1.7  
0
Typ.  
1.8  
0
Max.  
1.95  
0
Unit  
V
V
Power Supply Voltage  
Power Supply Voltage  
CC  
V
V
SS  
36  
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
10.3 DC Characteristics  
Table 10.3 DC Characteristics  
Parameter  
Symbol  
Parameter  
Description  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
V
active read current  
t
I
= 25 ns,  
CC  
RC  
I
—
40  
50  
mA  
CC1  
(average during read cycle)  
= 0 mA  
OUT  
I
I
Program current  
—
—
—
—
60  
60  
75  
75  
mA  
mA  
CC2  
Erase Current (standard mode)  
CC3  
CE# = V  
WP# = V  
,
IH  
I
Stand-by Current (TTL)  
—
—
—
—
1
60  
1
mA  
µA  
SB1  
SB2  
IL  
CE# = V –0.2 V,  
CC  
WP# = 0.2 V  
All other pins = –0.1 V  
I
Stand-by Current (CMOS)  
10  
V
V
= 0 to V  
,
CC  
IN  
I
Input Leakage Current  
Output Leakage Current  
—
—
µA  
µA  
LI  
= V max  
CC  
CC  
V
V
= 0 to V  
= V max  
CC  
,
CC  
OUT  
I
—
—
1
LO  
CC  
I
Boot Current  
—
—
—
—
100  
mA  
V
BOOT  
V
(note 1)  
Input High Voltage  
Input Low Voltage  
V
V
- 0.4  
V
+ 0.2  
CC  
IH  
CC  
V
(note 2)  
—
–0.3  
- 0.1  
0.4  
—
V
IL  
I
= –100 µA,  
OH  
V
Output High Voltage Level  
Output Low Voltage Level  
—
—
V
V
OH  
CC  
V
= V min  
CC  
CC  
I
= 100 µA,  
OL  
V
—
0.1  
—
OL  
V
= V min  
CC  
CC  
Output Low Current  
(RY/BY#)  
I
V
= 0.1 V  
1
1.4  
mA  
OL  
OL  
Notes  
1.  
V
can overshoot to V +0.4 V for durations of 20 ns or less.  
CC  
IH  
2.  
V
can undershoot to –0.4 V for durations of 20 ns or less.  
IL  
3. CE# is 15 pF, WP# = 18 pF, CLE = 18 pF  
10.4 Capacitance  
Table 10.4 Capacitance (Ta = 25°C, f = 1 MHz)  
Parameter  
Symbol  
Parameter  
Description  
Test  
Condition  
Density  
512 Mb  
1 Gb  
Typ.  
Max.  
10  
Unit  
—
—
—
—
—
—
—
—
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
10  
C
Input Capacitance  
Output Capacitance  
V
= 0  
IN  
IN  
2 Gb  
10  
4 Gb  
20  
512 Mb  
1 Gb  
10  
10  
C
V
= 0  
OUT  
OUT  
2 Gb  
10  
4 Gb  
20  
Notes  
1. Test conditions T = 25°C, f = 1.0 MHz  
a
2. Sampled, not 100% tested.  
3. CE is 15 pf.  
4. WP is 18 pf.  
5. CLE is 18 pf.  
March 30, 2009 S30MS-R_00_06  
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37  
D a t a S h e e t  
10.5 AC Test Conditions  
Table 10.5 AC Test Conditions  
Operating Range  
V
1.7 V to 1.95 V  
CC  
Input level  
0.0 to V  
CC  
Input comparison level  
Output data comparison level  
V
V
/2  
CC  
CC  
/2  
Load capacitance (C )  
30 pF  
5 ns  
L
Transition time (t ) (input rise and fall times)  
T
10.6 Valid Blocks  
Table 10.6 Valid Blocks  
Parameter  
Symbol  
Parameter  
Description  
Density  
512 Mb  
1 Gb  
Min.  
512  
Typ.  
—
Max.  
512  
Unit  
Blocks  
Blocks  
Blocks  
Blocks  
1024  
2048  
4096  
—
1024  
2048  
4096  
N
Number of Valid Blocks  
VB  
2 Gb  
—
4 Gb  
—
10.7 AC Characteristics  
Table 10.7 AC Characteristics (Sheet 1 of 2)  
Parameter  
Symbols  
Description  
Min.  
Max.  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
17  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
CLE Setup Time  
CLE Hold Time  
CE# Setup Time  
CE# Hold Time  
Write Pulse Width  
ALE Setup Time  
ALE Hold Time  
0
8
CLS  
CLH  
t
t
0
CS  
CH  
WP  
t
8
t
15  
0
t
ALS  
ALH  
t
8
t
Data Setup Time  
Data Hold Time  
Write Cycle Time  
WE# High Hold Time  
15  
8
DS  
DH  
t
t
t
25  
10  
100  
20  
20  
17  
25  
—
0
WC  
WH  
t
WP# High to WE# Low  
Ready to RE# Falling Edge  
Ready to WE# Falling Edge  
Read Pulse Width  
WW  
t
RR  
t
RW  
t
RP  
t
Read Cycle Time  
RC  
t
RE# Access Time  
REA  
t
CE# to RE# Time  
CR  
t
ALE to RE# Time  
10  
0
AR  
t
CLE to RE# Time  
CLR  
t
Data Output Hold Time  
RE# High to Output High Impedance  
CE# High to Output High Impedance  
RE# High Hold Time  
5
—
15  
15  
—
—
OH  
t
t
—
—
8
RHZ  
CHZ  
REH  
t
t
Output High Impedance to RE# Falling Edge  
0
IR  
38  
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
Table 10.7 AC Characteristics (Sheet 2 of 2)  
Parameter  
Symbols  
Description  
Min.  
30  
30  
60  
—
Max.  
—
Unit  
ns  
t
t
t
RE# High to WE# Low  
WE# High to CE# Low  
WE# High to RE# Low  
RHW  
WHC  
WHR  
—
ns  
—
ns  
Full Page Data Transfer from Memory Cell Array to Register  
Partial Page Data Transfer from Memory Cell Array to Register  
Pipeline Transfer  
28  
10  
28  
100  
6
t
µs  
R
—
t
0.4  
—
µs  
ns  
µs  
µs  
µs  
µs  
µs  
µs  
PT  
t
WE# High to Busy  
WB  
t
Device Resetting Time (Read/Program)  
Power on Reset and Full Page Read  
WE# High during Reset command to RY/BY# High  
Preamble time for suspended operation  
OTP Busy Time  
—
RST  
PRE  
t
—
250  
30  
10  
5
t
—
SUSPEND  
t
—
PRESUS  
t
—
OTP  
t
OTP Default Busy Time  
—
200  
OTPD  
10.8 Timing Diagrams  
Figure 10.1 Command Input Cycle Timing Diagram  
CLE  
tCLS  
tCS  
tCLH  
tCH  
CE#  
tWP  
WE#  
tALS  
tALH  
ALE  
I/O  
tDS  
tDH  
: VIL or VIH  
March 30, 2009 S30MS-R_00_06  
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39  
D a t a S h e e t  
Figure 10.2 Address Input Cycle Timing Diagram (512 Mbit/1 Gbit)  
tCLH  
tCLS  
CLE  
tWC  
tCH  
tCS  
CE#  
tWP  
tWH  
WE#  
ALE  
I/O  
tALH tALS  
tDS  
tDH  
Col. Add1  
Col. Add2  
Row Add1  
Row Add2  
: V or VIL  
IH  
Figure 10.3 Address Input Cycle Timing Diagram (2 Gbit/4 Gbit)  
tCLH  
tCLS  
CLE  
tWC  
tCH  
tCS  
CE#  
tWP  
tWH  
WE#  
ALE  
I/O  
tALH tALS  
tDS  
tDH  
Col. Add1  
Col. Add2  
Row Add1  
Row Add2  
Row Add3  
: V or VIL  
IH  
40  
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
Figure 10.4 Data Input Cycle Timing Diagram  
tCLS  
tCLH  
CLE  
tCH  
tCS  
CE#  
tWC  
tALH  
tALS  
ALE  
tWH  
tWP  
WE#  
tDH  
tDS  
DIN  
0
DIN  
1
DIN  
I/O  
2111 (x8)  
1055 (x16)  
: V or VIL  
IH  
Figure 10.5 Serial Read Cycle Timing Diagram  
CE# Don't Care  
tRC  
tCH  
tCR  
CE#  
tOH  
ALE#  
CLE#  
RE#  
tREH  
tRP  
tREA  
tOH  
tCHZ  
I/O  
DOUT0  
DOUT1  
DOUTN  
tRR  
tRHZ  
RY/BY#  
March 30, 2009 S30MS-R_00_06  
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41  
D a t a S h e e t  
Figure 10.6 Status Read Cycle Timing Diagram  
tCLR  
CLE  
tCLS  
tCS  
tCLH  
CE#  
tCH  
tWP  
tCR  
WE#  
tOH  
tWHC  
tWHR  
RE#  
I/O  
tOH  
tIR  
tDS  
tDH  
tCHZ  
tREA  
Status  
Output  
70H  
tRHZ  
RY/BY#  
: VIH or VIL  
Figure 10.7 Read Cycle Timing Diagram  
tCLR  
CLE  
tCLS  
tCS  
tCLH  
tCH  
CE#  
tWC  
tCR  
WE#  
ALE  
tALH tALS  
tALH tALS  
tAR  
tR  
tRC  
tWB  
RE#  
I/O  
tDS tDH  
tRR tREA  
Col.  
Col.  
Row  
Row  
Add2  
D
OUT  
A
D
OUT  
A+1  
00h  
30h  
Add1  
Add2  
Add1  
Data out from  
Col. Add. A  
Page Address P  
Column Address A  
RY/BY#  
Note  
In 2 Gbit/4 Gbit, Page Address is needed to input 3-cycles.  
42  
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
Figure 10.8 Column Address Change in Read Cycle Timing Diagram (1/2)  
tCLR  
CLE  
tCLS  
tCS  
tCLH  
tCH  
CE#  
tWC  
tCR  
WE#  
tALH  
tALS  
tALH  
tAR  
tALS  
ALE  
tRC  
tR  
RE#  
tWB  
tREA  
tDS tDH  
tRR  
Row  
Add1  
Row  
Add2  
Col.  
Add1  
Col.  
Add2  
D
D
OUT  
A+1  
D
OUT  
A+N  
OUT  
A
I/O  
00h  
30h  
Page address  
P
Column address  
A
Page address  
P
RY/BY#  
Column address  
A
Part A  
Part B  
A
Note  
In 2 Gbit/4 Gbit, Page Address is needed to input 3-cycles.  
Figure 10.9 Column Address Change in Read Cycle Timing Diagram (2/2)  
tCLR  
CLE  
tCLS  
tCS  
tCLH  
tCH  
CE#  
t
tCR  
RHW  
tWC  
WE#  
tALH tALS  
tALH tALS  
ALE  
tRC  
RE#  
I/O  
tDS tDH  
tREA  
tIR  
D
Col.  
Add1  
Col.  
Add2  
D
D
OUT  
B+1  
D
OUT  
B+N'  
OUT  
B
OUT  
05h  
E0h  
A+N  
Page address  
P
Column address  
B
RY/BY#  
Part A  
Part B  
Column address  
B
A
March 30, 2009 S30MS-R_00_06  
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43  
D a t a S h e e t  
10.8.1  
Program and Erase Characteristics  
Table 10.8 Program and Erase Characteristics  
Symbol  
Parameter  
Dummy Busy Time for Cache Programming (Note 2)  
Dummy Busy Time for Cache Programming (Note 3)  
Page Programming Time  
Min.  
—
Typ.  
0.4  
Max.  
0.8  
Unit  
µs  
t
CBSY1  
CBSY2  
t
—
(Note 4)  
800  
(Note 4)  
5000  
1400  
8
µs  
t
—
µs  
PROG  
t
Segment Programming Time  
—
260  
µs  
PPROG  
N
Number of Programming Cycles on Same Page (Note 1)  
Block Erasing Time  
—
—
t
—
50  
150  
ms  
BERASE  
P/E  
Number of Program/Erase Cycles (Notes 5, 6)  
10,000  
100,000  
—
cycles  
Notes  
1. One programming cycle per segment. Refer to Page Program on page 24 for more information.  
2. First cache programming of a sequence.  
3. Following cache programming of a sequence - second page and following pages.  
4. Calculation method for t  
is the following:  
CBSY2  
- t  
= t  
- (Command Cycles + t  
x Number of Data Input Cycles)  
WC  
CBSY2  
PROG  
5. Typical program and erase times assume the following conditions: 25°C, 1.8 V V , 10,000 cycles; checkerboard data pattern.  
CC  
6. Under worst case conditions of 90°C, V =1.70 V, 100,000 cycles.  
CC  
Figure 10.10 Program Operation Timing Diagram  
tCLS  
CLE  
tCLS tCLH  
tCS  
tCS  
CE#  
tCH  
WE#  
tALH  
tALH  
tALS  
tPROG  
tALS  
tWB  
tRW  
ALE  
RE#  
tDS  
tDH  
tDS tDH  
Col.  
Row  
Add2  
Col.  
Row  
Status  
output  
80h  
D
D
D
10h  
70h  
I/O  
IN0  
A
IN1  
IN  
Add1 Add2 Add1  
2111 (x8)  
1055 (x16)  
Column Address A  
Page Address P  
RY/BY#  
: V or VIL  
: Do not input data while data is being output.  
IH  
Note  
In 2 Gbit/4 Gbit, Page Address is needed to input 3-cycles.  
44  
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  
D a t a S h e e t  
Figure 10.11 Block Erase Timing Diagram  
CLE  
tCLS  
tCS  
tCLH  
tCLS  
CE#  
WE#  
tALH  
tALS  
tBERASE  
tWB  
ALE  
RE#  
tDS tDH  
Row  
Add1  
Row  
Add2  
Status  
output  
60h  
D0h  
70h  
I/O  
Note 2  
Note 1  
Busy  
Auto Block Erase Setup  
Command  
Erase Start  
Command  
Read Status  
command  
RY/BY#  
: V or VIL  
IH  
: Do not input data while data is being output.  
Notes  
1. If I/O 0 = 0, then the erase is successful. If I/O 0 = 1, then there is an error in the erase.  
2. Only the block address part of the Row Address bytes are used; page address is ignored.  
3. In 2 Gbit/4 Gbit, Page Address is needed to input 3-cycles.  
Figure 10.12 Cache Program Operation Timing Diagram  
CLE  
CE#  
tWC  
WE#  
ALE  
tWB tCBSY  
tPROG  
tWB  
RE#  
I/O  
Din  
N
Din  
M
Din  
N
Din  
M
Col Add2  
Row Add1 Row Add2  
80h  
Col Add1  
Col Add2  
Row Add1 Row Add2  
Col Add1  
15h  
80h  
10h  
70h  
I/O  
Program  
Command  
(Dummy)  
Program Confirm  
Command  
(T rue)  
Serial Data  
Page Address  
Page Address  
Column Address  
Input Command  
Serial Input  
Column Addre  
ss  
RY/BY#  
Note  
1. CE#, CLE, and ALE are Don’t care.  
2. In 2 Gbit/4 Gbit, Page Address is needed to input 3-cycles.  
March 30, 2009 S30MS-R_00_06  
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45  
D a t a S h e e t  
Figure 10.13 Page Duplicate Program Operation with Random Data Input Timing Diagram  
CLE  
CE#  
tWC  
WE#  
ALE  
tWB  
tWB  
tPROG  
tR  
RE#  
I/O  
Col Add2 Row Add1 RowAdd2  
ColAdd1  
85h  
00h  
Col Add2 RowAdd1 RowAdd2  
10h  
70h  
I/O0  
35h  
ColAdd1  
Data 1  
Data N  
Read Status  
Command  
Column Address  
Column Address  
Page Address  
Page Address  
RY/BY#  
Page Duplicate Date  
Input Command  
Busy  
Busy  
I/O 0=0 Successful Program  
I/O 0=1 Error in Program  
Notes  
1. CE#, CLE, and ALE are Don’t care.  
2. In 2 Gbit/4 Gbit, Page Address is needed to input 3-cycles.  
Figure 10.14 ID Read Operation Timing Diagram  
I
CLE  
tCLS  
tCH  
tCLS  
tCS  
CE#  
tALH  
tCS  
WE#  
tCR  
tALS  
tCH  
tALH  
tAR  
ALE  
tDS  
RE#  
tDH  
2nd  
byte  
3rd  
byte  
4th  
byte  
5th  
byte  
I/O  
00h  
01h  
90h  
tREA  
Address Input  
Maker Code  
Device Code  
: VIH or VIL  
Note  
CE#, CLE, and ALE are Don’t care.  
46  
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D a t a S h e e t  
11. Revision History  
Section  
Description  
Revision 01 (January 17, 2007)  
Initial Release  
Revision 02 (March 22, 2007)  
Block Erase  
Clarified command restrictions  
DC Characteristics  
Page Program  
Changed ICC1, ICC2, and ICC3 values and definitions  
Clarified command restrictions  
Changed tPRESUS value  
Changed tR value  
Changed tPRE value  
AC Characteristics  
Capacitance: Changed CE#, WP# and CLE capacitance values  
Clarified Erase Suspend Operation  
Status Bit: Clarified I/O 0 behavior during Erase Suspend  
Revision 03 (September 27, 2007)  
Global  
Deleted reference to 4 Gb ORNAND device  
DC Characteristics  
Changed Typical and Max specifications for ICC2 and ICC3  
Revision 04 (November 2, 2007)  
Changed tOTPD value  
Changed tSUSPEND value  
Changed tCHZ value  
Changed tRHZ value  
AC Characteristics  
Changed tRST value  
Changed tR Partial Page Data Transfer from Memory Cell Array to Register value  
Changed tCR value  
Changed tCLR value  
DC Characteristics  
Changed IOL value  
Program and Erase Characteristics  
Global  
Changed tPROG and tPPROG value  
Defined 3 quality grades  
Revision 05 (March 12, 2009)  
Changed bad block description on cover page.  
Added maximum slew rate (1V/400us) constraint.  
Added IBOOT description and specification.  
Updated data sheet designation.  
Global  
Revision 06 (March 30, 2009)  
Power On and Power Off  
Changed instructions for re-boot on ramp-rate violation.  
March 30, 2009 S30MS-R_00_06  
S30MS-R ORNANDTM Flash Family  
47  
D a t a S h e e t  
Colophon  
The products described in this document are designed, developed and manufactured as contemplated for general use, including without  
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as  
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the  
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,  
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for  
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to  
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor  
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design  
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal  
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under  
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,  
the prior authorization by the respective government entity will be required for export of those products.  
Trademarks and Notice  
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under  
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this  
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,  
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any  
damages of any kind arising out of the use of the information in this document.  
Copyright © 2007-2009 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,  
ORNAND2™, HD-SIM™, EcoRAM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names  
used are for informational purposes only and may be trademarks of their respective owners.  
48  
S30MS-R ORNANDTM Flash Family  
S30MS-R_00_06 March 30, 2009  

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