S71GL064A80BFI0K3 [SPANSION]
Memory Circuit, 4MX16, CMOS, PBGA56, 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56;型号: | S71GL064A80BFI0K3 |
厂家: | SPANSION |
描述: | Memory Circuit, 4MX16, CMOS, PBGA56, 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56 静态存储器 内存集成电路 |
文件: | 总134页 (文件大小:2383K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
S71GL064A Based MCPs
Stacked Multi-Chip Product (MCP) Flash Memory and RAM
64 Megabit (4 M x 16-bit) CMOS 3.0 Volt-only Page Mode Flash
Memory and 16/8 Megabit (1M/512K x 16-bit)
Pseudo Static RAM / Static RAM
ADVANCE
INFORMATION
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S71GL064A_00 Revision A Amendment 2 Issue Date February 8, 2005
This page intentionally left blank.
S71GL064A based MCPs
Stacked Multi-Chip Product (MCP) Flash Memory and
RAM 64 Megabit (4 M x 16-bit) CMOS 3.0 Volt-only Page
Mode Flash Memory and 16/8 Megabit (1M/512K x 16-bit)
Pseudo Static RAM / Static RAM
ADVANCE
INFORMATION
Data Sheet
Distinctive Characteristics
MCP Features
Power supply voltage of 2.7 to 3.1 volt
High performance
Packages
— 7 x 9 x 1.2 mm 56 ball FBGA (TLC056)
Operating Temperature
— 100 ns access time (100 ns Flash, 70 ns pSRAM/
SRAM)
— 25 ns page read times
— –25°C to +85°C
— –40°C to +85°C
General Description
The S71GL064A product series consists of S29GL064 Flash memory with pSRAM and SRAM
combinations defined as:
Flash Memory Density
64Mb
8Mb
S71GL064A80/S71GL064A08
S71GL064AA0/S71GL064A0A
pSRAM / SRAM
Density
16Mb
Publication Number S71GL064A_00 Revision A Amendment 2 Issue Date February 8, 2005
This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Ad-
vance Information, Preliminary, or Full Production. See the section “Notice on Data Sheet Designations” for definitions.
A d v a n c e I n f o r m a t i o n
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, in-
cluding development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to high-
light their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more spe-
cific products, but has not committed any design to production. Information presented in a doc-
ument with this designation is likely to change, and in some cases, development on the product
may discontinue. Spansion LLC therefore places the following conditions upon Advance Informa-
tion content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the prod-
uct life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these as-
pects of production under consideration. Spansion places the following conditions upon Prelimi-
nary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-
tions due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance In-
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or V range. Changes
IO
may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
2
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Product Selector Guide
64 Mb Flash Memory
Device-Model# (Note)
Flash Access time (ns) (p)SRAM density (p)SRAM Access time (ns)
(p)SRAM type
Package
S71GL064A80-0K
S71GL064A80-0P
S71GL064A08-0B
S71GL064A08-0F
S71GL064AA0-0K
S71GL064AA0-0P
S71GL064AA0-0U
S71GL064AA0-0Z
S71GL064A0A-0B
S71GL064A0A-0F
8 M pSRAM
8 M SRAM
pSRAM1
SRAM1
pSRAM1
pSRAM7
SRAM1
100
70
TLC056
16 M pSRAM
16 M SRAM
Note: Please see the valid combinations table for the model# description.
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
3
A d v a n c e I n f o r m a t i o n
Reset Command .................................................................................................40
Autoselect Command Sequence ....................................................................41
Enter Secured Silicon Sector/Exit Secured Silicon
S71GL064A based MCPs
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .3
64 Mb Flash Memory ............................................................................................3
Connection Diagram (S71GL064A) . . . . . . . . . . . . .8
Special Handling Instructions For FBGA Package ...................................8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 10
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 12
TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA)
Sector Command Sequence .............................................................................41
Word Program Command Sequence .......................................................41
Unlock Bypass Command Sequence ........................................................42
Write Buffer Programming .........................................................................42
Accelerated Program ....................................................................................44
Figure 3. Write Buffer Programming Operation....................... 45
Figure 4. Program Operation ............................................... 46
Program Suspend/Program Resume Command Sequence ....................46
Figure 5. Program Suspend/Program Resume........................ 48
Chip Erase Command Sequence ...................................................................48
Sector Erase Command Sequence . . . . . . . . . . . 49
Figure 6. Erase Operation ................................................... 50
Erase Suspend/Erase Resume Commands ..................................................50
9 x 7 mm Package ............................................................................................... 12
Table 10. Command Definitions (x16 Mode, BYTE# = V ) ......52
IH
S29GLxxxA MirrorBit™ Flash Family
DQ7: Data# Polling ............................................................................................53
Figure 7. Data# Polling Algorithm ........................................ 54
RY/BY#: Ready/Busy# ....................................................................................... 54
Figure 8. Toggle Bit Algorithm ............................................. 56
Reading Toggle Bits DQ6/DQ2 ..................................................................... 57
DQ5: Exceeded Timing Limits ........................................................................ 57
DQ3: Sector Erase Timer ................................................................................58
DQ1: Write-to-Buffer Abort ...........................................................................58
Table 11. Write Operation Status .........................................58
Figure 9. Maximum Negative Overshoot Waveform................. 59
Figure 10. Maximum Positive Overshoot Waveform ................ 59
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 59
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Figure 11. Test Setup......................................................... 61
Table 12. Test Specifications ...............................................61
Key to Switching Waveforms . . . . . . . . . . . . . . . . 62
Figure 12. Input Waveforms and Measurement Levels ............ 62
Read-Only Operations-S29GL064A only ................................................... 63
Figure 13. Read Operation Timings....................................... 63
Figure 14. Page Read Timings.............................................. 64
Hardware Reset (RESET#) ..............................................................................64
Figure 15. Reset Timings .................................................... 65
Erase and Program Operations-S29GL064A Only ..................................66
Figure 16. Program Operation Timings.................................. 67
Figure 17. Accelerated Program Timing Diagram.................... 67
Figure 18. Chip/Sector Erase Operation Timings..................... 68
Figure 19. Data# Polling Timings
(During Embedded Algorithms)............................................ 69
Figure 20. Toggle Bit Timings (During Embedded Algorithms).. 69
Figure 21. DQ2 vs. DQ6...................................................... 70
Temporary Sector Unprotect ........................................................................70
Figure 22. Temporary Sector Group Unprotect Timing Diagram 70
Figure 23. Sector Group Protect and Unprotect Timing Diagram 71
Alternate CE# Controlled Erase and
Distinctive Characteristics 13
General Description . . . . . . . . . . . . . . . . . . . . . . . . 14
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 15
S29GL064A ............................................................................................................15
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 19
Table 1. Device Bus Operations ........................................... 19
Requirements for Reading Array Data ......................................................... 19
Page Mode Read .............................................................................................20
Writing Commands/Command Sequences ................................................20
Write Buffer ....................................................................................................20
Accelerated Program Operation ..............................................................20
Autoselect Functions ..................................................................................... 21
Standby Mode ....................................................................................................... 21
Automatic Sleep Mode ...................................................................................... 21
RESET#: Hardware Reset Pin ......................................................................... 21
Output Disable Mode ........................................................................................ 21
Table 2. S29GL064A Top Boot Sector Architecture ................. 22
Table 3. S29GL064A Bottom Boot Sector Architecture ............ 25
Autoselect Mode ................................................................................................ 29
Table 4. Autoselect Codes, (High Voltage Method) ................ 30
Sector Group Protection and Unprotection ............................................. 30
Table 5. S29GL064A Sector Group
Protection/Unprotection Address ......................................... 31
Figure 1. Temporary Sector Group Unprotect Operation .......... 32
Figure 2. In-System Sector Group Protect/Unprotect Algorithms 33
Secured Silicon Sector Flash Memory Region ............................................34
Write Protect (WP#) ........................................................................................35
Hardware Data Protection ..............................................................................35
Low VCC Write Inhibit ................................................................................35
Write Pulse “Glitch” Protection ................................................................35
Logical Inhibit ...................................................................................................35
Power-Up Write Inhibit ................................................................................36
Program Operations-S29GL064A ................................................................. 72
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.............................................................. 73
Erase And Programming Performance . . . . . . . . 74
Common Flash Memory Interface (CFI) . . . . . . 36
Table 6. CFI Query Identification String ................................ 37
Table 7. System Interface String.......................................... 37
Table 8. Device Geometry Definition .................................... 38
Table 9. Primary Vendor-Specific Extended Query ................. 38
Command Definitions . . . . . . . . . . . . . . . . . . . . . .40
Reading Array Data ...........................................................................................40
pSRAM Type 1
Functional Description . . . . . . . . . . . . . . . . . . . . . 75
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 75
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 76
4
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Table 13. 4Mb pSRAM Asynchronous .................................... 76
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 105
Recommended Operating Conditions . . . . . . . . 105
Package Capacitance . . . . . . . . . . . . . . . . . . . . . 105
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 106
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .107
Table 14. 8Mb pSRAM Asynchronous .................................... 76
Table 15. 16Mb pSRAM Asynchronous .................................. 77
Table 16. 16Mb pSRAM Page Mode ...................................... 78
Table 17. 32Mb pSRAM Page Mode ...................................... 79
Table 18. 64Mb pSRAM Page Mode ...................................... 79
Read Operation .................................................................................................107
Write Operation .............................................................................................. 108
Power Down Parameters ...............................................................................109
Other Timing Parameters ...............................................................................109
AC Test Conditions ..........................................................................................110
AC Measurement Output Load Circuits ....................................................110
Figure 37. AC Output Load Circuit – 16 Mb.......................... 110
Figure 38. AC Output Load Circuit – 32 Mb and 64 Mb .......... 110
Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 80
Output Load Circuit .......................................................................................... 81
Figure 25. Output Load Circuit ............................................. 81
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 81
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 19. 4Mb pSRAM Page Mode ........................................ 82
Table 20. 8Mb pSRAM Asynchronous .................................... 84
Figure 26. 16Mb pSRAM Asynchronous.................................. 86
Table 21. 16Mb pSRAM Page Mode ...................................... 87
Table 22. 32Mb pSRAM Page Mode ...................................... 89
Table 23. 64Mb pSRAM Page Mode ...................................... 91
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Read Timings .........................................................................................................111
Figure 39. Read Timing #1 (Basic Timing)........................... 111
Figure 40. Read Timing #2 (OE# Address Access................. 111
Figure 41. Read Timing #3 (LB#/UB# Byte Access).............. 112
Figure 42. Read Timing #4 (Page Address Access after CE1# Control
Access for 32M and 64M Only)........................................... 112
Figure 43. Read Timing #5 (Random and Page Address Access for
32M and 64M Only).......................................................... 113
Write Timings .....................................................................................................113
Figure 44. Write Timing #1 (Basic Timing) .......................... 113
Figure 45. Write Timing #2 (WE# Control).......................... 114
Figure 46. Write Timing #3-1
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 92
Read Cycle ........................................................................................................... 92
Figure 27. Timing of Read Cycle
(CE# = OE# = V , WE# = ZZ# = V )................................. 92
IL
IH
Figure 28. Timing Waveform of Read Cycle (WE# = ZZ# = V ) 93
IH
Figure 29. Timing Waveform of Page Mode
Read Cycle (WE# = ZZ# = V )........................................... 94
IH
Write Cycle ..........................................................................................................95
Figure 30. Timing Waveform of Write Cycle
(WE# Control, ZZ# = V ) .................................................. 95
IH
(WE#/LB#/UB# Byte Write Control)................................... 114
Figure 47. Write Timing #3-3
Figure 31. Timing Waveform of Write Cycle
(CE# Control, ZZ# = V ) ................................................... 95
IH
(WE#/LB#/UB# Byte Write Control)................................... 115
Figure 48. Write Timing #3-4
Figure 32. Timing Waveform of Page Mode Write
Cycle (ZZ# = V ).............................................................. 96
IH
(WE#/LB#/UB# Byte Write Control)................................... 115
Read/Write Timings ..........................................................................................116
Figure 49. Read/Write Timing #1-1 (CE1# Control).............. 116
Figure 50. Read / Write Timing #1-2
(CE1#/WE#/OE# Control) ................................................ 116
Figure 51. Read / Write Timing #2 (OE#, WE# Control)........ 117
Figure 52. Read / Write Timing #3
(OE#, WE#, LB#, UB# Control)......................................... 117
Figure 53. Power-up Timing #1 ......................................... 118
Figure 54. Power-up Timing #2 ......................................... 118
Figure 55. Power Down Entry and Exit Timing...................... 118
Figure 56. Standby Entry Timing after Read or Write ............ 119
Figure 57. Power Down Program Timing (for 32M/64M Only) . 119
Power Savings Modes . . . . . . . . . . . . . . . . . . . . . . 96
Partial Array Self Refresh (PAR) .................................................................... 96
Temperature Compensated Refresh (for 64Mb) ......................................97
Deep Sleep Mode ................................................................................................97
Reduced Memory Size (for 32M and 16M) ...................................................97
Other Mode Register Settings (for 64M) .....................................................97
Figure 33. Mode Register..................................................... 98
Figure 34. Mode Register UpdateTimings (UB#, LB#, OE# are Don’t
Care)................................................................................ 98
Figure 35. Deep Sleep Mode - Entry/Exit Timings (for 64M) ..... 99
Figure 36. Deep Sleep Mode - Entry/Exit Timings
(for 32M and 16M) ............................................................. 99
Table 24. Mode Register Update and Deep Sleep Timings ....... 99
Table 25. Address Patterns for PASR (A4=1) (64M) ............... 99
ICC Characteristics ..........................................................................................100
Table 26. Deep ICC Characteristics (for 64Mb) .....................100
Table 27. Address Patterns for PAR (A3= 0, A4=1) (32M) ......100
Table 28. Address Patterns for RMS (A3 = 1, A4 = 1) (32M) ..100
Table 29. Low Power ICC Characteristics (32M) ....................101
Table 30. Address Patterns for PAR (A3= 0, A4=1) (16M) ......101
Table 31. Address Patterns for RMS (A3 = 1, A4 = 1) (16M) ..101
Table 32. Low Power ICC Characteristics (16M) ....................101
Type 1 SRAM
Common Features . . . . . . . . . . . . . . . . . . . . . . . 120
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Functional Description . . . . . . . . . . . . . . . . . . . . 121
4M Version F, 4M version G, 8M version C ..........................................121
Byte Mode ............................................................................................................121
8M Version D .................................................................................................122
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 122
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 123
Capacitance .........................................................................................................123
DC Operating Characteristics . . . . . . . . . . . . . . 123
pSRAM Type 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Functional Description . . . . . . . . . . . . . . . . . . . . . 103
Power Down (for 32M, 64M Only) . . . . . . . . . . . . 103
Power Down ......................................................................................................103
Power Down Program Sequence .................................................................104
Address Key .......................................................................................................104
AC Operating Conditions . . . . . . . . . . . . . . . . . . .126
Test Conditions .................................................................................................126
Figure 58. AC Output Load................................................ 126
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 126
Table 33. Read/Write Characteristics (V =2.7-3.3V) ........... 126
CC
Data Retention Characteristics . . . . . . . . . . . . . 127
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
5
A d v a n c e I n f o r m a t i o n
BYTE# is Low, Ignore UB#/LB# Timing) ............................. 130
Figure 63. Timing Waveform of Write Cycle(3) (UB#, LB#
controlled)...................................................................... 130
Figure 64. Data Retention Waveform.................................. 131
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 59. Timing Waveform of Read Cycle(1) (Address Controlled,
CS#1=OE#=V , CS2=WE#=V , UB# and/or LB#=V )....... 128
IL
IH
IL
Figure 60. Timing Waveform of Read Cycle(2) (WE#=V , if BYTE#
IH
is Low, Ignore UB#/LB# Timing)........................................ 129
Figure 61. Timing Waveform of Write Cycle(1) (WE# controlled, if
BYTE# is Low, Ignore UB#/LB# Timing).............................. 129
Figure 62. Timing Waveform of Write Cycle(2) (CS# controlled, if
Revision Summary
6
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
MCP Block Diagram
VCC
f
VCC
CE1#f
WP#/ACC
RESET#
Flash-only Address
Flash
Shared Address
OE#
WE#
RY/BY#
DQ15 to DQ0
VCCS
VCC
pSRAM/SRAM
IO15-IO0
CE1#s
UB#
CE#
UB#
LB#
LB#
CE2s
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
7
A d v a n c e I n f o r m a t i o n
Connection Diagram (S71GL064A)
56-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
Legend
A2
A7
A3
LB#
B3
A4
WP/ACC
B4
A5
WE#
B5
A6
A8
A7
A11
B7
B1
A3
B2
B6
B8
A15
C8
Shared
(Note 1)
A6
UB#
C3
RST#f
C4
CE2s
C5
A19
C6
A12
C7
C1
C2
A2
A5
A18
D3
RY/BY#
A20
A9
A13
D7
A21
D8
Flash only
RAM only
D1
D2
D6
A1
A4
A17
E3
A10
E6
A14
E7
RFU
E8
E1
E2
A0
VSS
F2
DQ1
F3
DQ6
F6
RFU
F7
A16
F8
F1
F4
DQ3
G4
F5
DQ4
G5
Reserved for
Future Use
CE1#f
G1
OE#
G2
DQ0
H2
DQ9
G3
DQ13
G6
DQ15
G7
RFU
G8
CE1#s
DQ10
H3
VCCf
H4
VCCs
H5
DQ12
H6
DQ7
H7
VSS
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
Notes:
1. May be shared depending on density.
—
—
A19 is shared for the 16M pSRAM and above configurations.
A18 is shared for the 8M (p)SRAM and above configurations.
MCP
S71GL064AA0
Flash-only Addresses
Shared Addresses
A19-A0
A21-A20
A21-A20
A21-A19
A21-A19
S71GL064A0A
S71GL064A80
S71GL064A08
A19-A0
A18-A0
A18-A0
Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning
methods. The package and/or data integrity may be compromised if the package body is ex-
posed to temperatures above 150°C for prolonged periods of time.
8
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Pin Description
A21–A0
DQ15–DQ0
CE1#f
CE1#s
CE2s
OE#
WE#
RY/BY#
UB#
LB#
=
=
=
=
=
=
=
=
=
=
=
=
=
22 Address Inputs (Common and Flash only)
16 Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable 1 (pSRAM/SRAM)
Chip Enable 2 (pSRAM/SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Output (Flash 1)
Upper Byte Control (pSRAM/SRAM)
Lower Byte Control (pSRAM/SRAM)
Hardware Reset Pin, Active Low (Flash)
Hardware Write Protect/Acceleration Pin (Flash)
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
RESET#
WP#/ACC
VCC
f
VCCS
VSS
NC
=
=
=
pSRAM/SRAM Power Supply
Device Ground (Common)
Pin Not Connected Internally
Logic Symbol
22
A21–A0
16
DQ15–DQ0
CE1#f
CE1#s
R Y/BY#
CE2s
OE#
WE#
WP#/ACC
RESET#
UB#
LB#
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
9
A d v a n c e I n f o r m a t i o n
Ordering Information
The order number is formed by a valid combinations of the following:
Table 1:
S71GL
064
A
A0 BA
W
9
Z
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER
See the Valid Combinations table.
PACKAGE MODIFIER
0
=
7 x 9 mm, 1.2 mm height, 56 balls (TLC056)
TEMPERATURE RANGE
W
I
=
=
Wireless (-25
Industrial (-40
°
C to +85
°
C)
°C to +85
°C)
PACKAGE TYPE
BA
BF
=
=
Fine-pitch BGA Lead (Pb)-free compliant package
Fine-pitch BGA Lead (Pb)-free package
pSRAM / SRAM DENSITY
0A
A0
80
08
=
=
=
=
16 Mb SRAM
16 Mb pSRAM
8 Mb pSRAM
8 Mb SRAM
PROCESS TECHNOLOGY
200 nm, MirrorBit Technology
A
=
FLASH DENSITY
064 64Mb
=
PRODUCT FAMILY
S71GL Multi-chip Product (MCP)
3.0-volt Page Mode Flash Memory and RAM
10
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
S71GL064A Valid Combinations
(p)SRAM Type/
Access Time
(ns)
Base Ordering
Part Number
Package &
Package Modifier/Model
Number
Speed Options (ns)/Boot
Sector Option
Package
Marking
Te mp e ratu re
Packing Type
S71GL064A80
S71GL064A80
S71GL064A08
S71GL064A08
S71GL064AA0
S71GL064AA0
S71GL064AA0
S71GL064AA0
S71GL064A0A
S71GL064A0A
S71GL064A80
S71GL064A80
S71GL064A08
S71GL064A08
S71GL064AA0
S71GL064AA0
S71GL064AA0
S71GL064AA0
S71GL064A0A
S71GL064A0A
S71GL064A80
S71GL064A80
S71GL064A08
S71GL064A08
S71GL064AA0
S71GL064AA0
S71GL064AA0
S71GL064AA0
S71GL064A0A
S71GL064A0A
S71GL064A80
S71GL064A80
S71GL064A08
S71GL064A08
S71GL064AA0
S71GL064AA0
S71GL064AA0
S71GL064AA0
S71GL064A0A
S71GL064A0A
0K
0P
0B
0F
0K
0P
0U
0Z
0B
0F
0K
0P
0B
0F
0K
0P
0U
0Z
0B
0F
0K
0P
0B
0F
0K
0P
0U
0Z
0B
0F
0K
0P
0B
0F
0K
0P
0U
0Z
0B
0F
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
100 / Bottom Boot Sector
100 / Top Boot Sector
pSRAM1/ 70
SRAM1 / 70
pSRAM1/ 70
pSRAM7 / 70
SRAM1 / 70
pSRAM1/ 70
SRAM1 / 70
pSRAM1/ 70
pSRAM7 / 70
SRAM1 / 70
pSRAM1/ 70
SRAM1 / 70
pSRAM1/ 70
pSRAM7 / 70
SRAM1 / 70
pSRAM1/ 70
SRAM1 / 70
pSRAM1/ 70
pSRAM7 / 70
SRAM1 / 70
BAW
0, 2, 3 (Note 1)
BFW
BAI
BFI
0, 2, 3 (Note 1)
0, 2, 3 (Note 1)
0, 2, 3 (Note 1)
TLC056
Notes:
1. Type 0 is standard. Specify other options as required.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this de-
vice. Consult your local sales office to confirm availability of specific valid combinations
and to check on newly released combinations.
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
11
A d v a n c e I n f o r m a t i o n
Physical Dimensions
TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA)
9 x 7 mm Package
A
D1
D
eD
0.15
(2X)
C
8
7
6
5
4
3
2
1
SE
7
E
B
E1
eE
H
G
F
E
D
C
B
A
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
56X
b
0.15
M
C
C
A
B
0.08
M
NOTES:
PACKAGE
JEDEC
TLC 056
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
9.00 mm x 7.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.20
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
9.00 BSC.
7.00 BSC.
5.60 BSC.
5.60 BSC.
8
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
8
56
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
A1,A8,D4,D5,E4,E5,H1,H8
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3348 \ 16-038.22a
12
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
S29GLxxxA MirrorBit™ Flash Family
Stacked Multi-Chip Product (MCP) Flash Memory and
RAM 64 Megabit (4 M x 16-bit) CMOS 3.0 Volt-only Page
Mode Flash Memory and 16/8 Megabit (1M/512K x 16-bit)
Pseudo Static RAM / Static RAM
ADVANCE
INFORMATION
Data Sheet
Distinctive Characteristics
Low power consumption (typical values at 3.0
Architectural Advantages
V, 5 MHz)
Single power supply operation
— 3 volt read, erase, and program operations
Manufactured on 200 nm MirrorBit process
technology
— 18 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
Secured Silicon Sector region
Software & Hardware Features
Software features
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
Flexible sector architecture
— 64Mb (uniform sector models): 128 32 Kword (64 KB)
sectors or 128 32 Kword sectors
— 64Mb (boot sector models): 127 32 Kword (64 KB)
sectors + 8 4Kword (8KB) boot sectors
— Unlock Bypass Program command reduces overall
multiple-word programming time
Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of
charging code in locked sectors
100,000 erase cycles typical per sector
20-year data retention typical
— WP#/ACC input accelerates programming time (when
high voltage is applied) for greater throughput during
system production. Protects first or last sector
regardless of sector protection settings on uniform
sector models
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or
erase cycle completionDistinctive Characteristics
Performance Characteristics
High performance
— 100 ns access time
— 4-word/8-byte page read buffer
— 25 ns page read times
— 16-word/32-byte write buffer, which reduces overall
programming time for multiple-word updates
Publication Number S71GL064A_00 Revision A Amendment 2 Issue Date February 8, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e I n f o r m a t i o n
General Description
The S29GL064A is a 64 Mb, organized as 4,194,304 words or 8,388,608 bytes.
Access times as fast as 90 ns are available. Note that each access time has a specific operat-
ing voltage range (VCC) as specified in the Product Selector Guide section. Each device has
separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and write functions.
In addition to a VCC input, a high-voltage accelerated program (ACC) feature provides
shorter programming times through increased current on the WP#/ACC input. This feature is
intended to facilitate factory throughput during system production, but may also be used in
the field if desired.
The device is entirely command set compatible with the JEDEC single-power-supply Flash
standard. Commands are written to the device using standard microprocessor write timing.
Write cycles also internally latch addresses and data needed for the programming and erase
operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed
without affecting the data contents of other sectors. The device is fully erased when shipped
from the factory.
Device programming and erasure are initiated through command sequences. Once a program
or erase operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6
(toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether
the operation is complete. To facilitate programming, an Unlock Bypass mode reduces com-
mand sequence overhead by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low VCC detector that automatically inhibits
write operations during power transitions. The hardware sector protection feature disables
both program and erase operations in any combination of sectors of memory. This can be
achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause an erase op-
eration in a given sector to read or program any other sector and then complete the erase
operation. The Program Suspend/Program Resume feature enables the host system to
pause a program operation in a given sector to read any other sector and then complete the
program operation.
The hardware RESET# pin terminates any operation in progress and resets the device, after
which it is then ready for a new operation. The RESET# pin may be tied to the system reset
circuitry. A system reset would thus also reset the device, enabling the host system to read
boot-up firmware from the Flash memory device.
The device reduces power consumption in the standby mode when it detects specific voltage
levels on CE# and RESET#, or when addresses have been stable for a specified period of time.
The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on
the WP#/ACC pin or WP# pin, depending on model number. The protected sector will still be
protected even during accelerated programming.
The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can
be permanently protected. Once this sector is protected, no further changes within the sector
can occur.
Spansion MirrorBit flash technology combines years of Flash memory manufacturing experi-
ence to produce the highest levels of quality, reliability and cost effectiveness. The device
electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data
is programmed using hot electron injection.
14
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Product Selector Guide
S29GL064A
Part Number
S29GL064A
Speed Option
100
100
100
25
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page Access Time (ns)
Max. OE# Access Time (ns)
25
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
15
A d v a n c e I n f o r m a t i o n
Block Diagram
DQ15–DQ0 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
WP#/ACC
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A21–A0
16
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Pin Descriptions
A21–A0
=
=
=
=
=
22 Address inputs
21 Address inputs
8 Data inputs/outputs
15 Data inputs/outputs
DQ15 (Data input/output, word mode), A-1 (LSB
Address input, byte mode)
A20–A0
DQ7–DQ0
DQ14–DQ0
DQ15/A-1
CE#
OE#
WE#
WP#/ACC
=
=
=
=
Chip Enable input
Output Enable input
Write Enable input
Hardware Write Protect input/Programming
Acceleration input
ACC
WP#
RESET#
RY/BY#
VCC
=
=
=
=
=
Acceleration input
Hardware Write Protect input
Hardware Reset Pin input
Ready/Busy output
3.0 volt-only single power supply
(see Product Selector Guide for speed options and
voltage supply tolerances)
VSS
NC
VIO
=
=
=
Device Ground
Pin Not Connected Internally
Output Buffer Power
Logic Symbols
S29GL064A (Models R1, R2)
22
A21–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
VIO
RY/BY#
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
17
A d v a n c e I n f o r m a t i o n
S29GL064A (Models R3, R4)
22
A21–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
S29GL064A (Model R5)
22
A21–A0
16
DQ15–DQ0
CE#
OE#
WE#
ACC
RESET#
VIO
RY/BY#
S29GL064A (Model R6, R7)
22
A21–A0
16
DQ15–DQ0
CE#
OE#
WE#
WP#
ACC
RESET#
VIO
18
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are ini-
tiated through the internal command register. The command register itself does not occupy
any addressable memory location. The register is a latch used to store the commands, along
with the address and data information needed to execute the command. The contents of the
register serve as inputs to the internal state machine. The state machine outputs dictate the
function of the device. Table 1 lists the device bus operations, the inputs and control levels
they require, and the resulting output. The following subsections describe each of these op-
erations in further detail.
Table 1. Device Bus Operations
Addresses
Operation
CE# OE# WE# RESET#
WP#
X
ACC
X
(Note 1)
DQ0–DQ15
DOUT
Read
L
L
L
H
H
H
L
H
H
AIN
Write (Program/Erase)
Accelerated Program
(Note 3)
X
AIN
(Note 4)
(Note 4)
L
L
H
(Note 3) VHH
AIN
VCC
0.3 V
±
VCC ±
0.3 V
Standby
X
X
X
H
X
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
X
X
X
X
High-Z
High-Z
X
SA, A6 =L,
A3=L, A2=L,
A1=H, A0=L
Sector Group Protect
(Note 2)
L
H
L
VID
H
X
(Note 4)
Sector Group
Unprotect
(Note 2)
SA, A6=H,
A3=L, A2=L,
A1=H, A0=L
L
H
X
L
VID
VID
H
H
X
X
(Note 4)
(Note 4)
Temporary Sector
Group Unprotect
X
X
AIN
Legend: L = Logic Low = V , H = Logic High = V , V = 11.5–12.5V, V = 11.5–12.5V, X = Don’t Care, SA = Sector
IL
IH
ID
HH
Address, A = Address In, D = Data In, D = Data Out
IN
IN
OUT
Notes:
1. Addresses are Amax:A0 in word mode; Amax:A-1 in byte mode. Sector addresses are Amax:A15 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group Protection
and Unprotection” section.
3. If WP# = VIL, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for boot
sector devices). If WP# = VIH, the first or last sector, or the two outer boot sectors will be protected or unprotected as determined by the
method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped from the factory (The Secured
Silicon Sector may be factory protected depending on version ordered.)
4.
DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL.
CE# is the power control and selects the device. OE# is the output control and gates array
data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hard-
ware reset. This ensures that no spurious alteration of the memory content occurs during the
power transition. No command is necessary in this mode to obtain array data. Standard mi-
croprocessor read cycles that assert valid addresses on the device address inputs produce
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
19
A d v a n c e I n f o r m a t i o n
valid data on the device data outputs. The device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table
for timing specifications and the timing diagram. Refer to the DC Characteristics table for the
active current specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask
ROM read operation. This mode provides faster read access speed for random locations within
a page. The page size of the device is 4 words/8 bytes. The appropriate page is selected by
the higher address bits A(max)–A2. Address bits A1–A0 in word mode (A1–A-1 in byte mode)
determine the specific word within a page. This is an asynchronous operation; the micropro-
cessor supplies the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page read accesses
(as long as the locations specified by the microprocessor falls within that page) is equivalent
to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is
tACC or tCE. Fast page mode accesses are obtained by keeping the “read-page addresses” con-
stant and changing the “intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device
and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the de-
vice enters the Unlock Bypass mode, only two write cycles are required to program a word,
instead of four. The “Word Program Command Sequence” section has details on programming
data to the device using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Refer to the DC Characteristics table for the active current specification for the write mode.
The AC Characteristics section contains timing specification tables and timing diagrams for
write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one
programming operation. This results in faster effective programming time than the standard
programming algorithms. See “Write Buffer” for more information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of
two functions provided by the WP#/ACC or ACC pin, depending on model number. This func-
tion is primarily intended to allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Un-
lock Bypass mode, temporarily unprotects any protected sector groups, and uses the higher
voltage on the pin to reduce the time required for program operations. The system would use
a two-cycle program command sequence as required by the Unlock Bypass mode. Removing
VHH from the WP#/ACC or ACC pin, depending on model number, returns the device to normal
operation. Note that the WP#/ACC or ACC pin must not be at VHH for operations other than
accelerated programming, or device damage may result. WP# has an internal pullup; when
unconnected, WP# is at VIH
.
20
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect
mode. The system can then read autoselect codes from the internal register (which is sepa-
rate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode.
Refer to the “Autoselect Mode” section on page 29 and “Autoselect Command Sequence” sec-
tion on page 41 sections for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at
VIO ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET#
are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the
standby current will be greater. The device requires standard access time (tCE) for read access
when the device is in either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current
until the operation is completed.
Refer to the “DC Characteristics” section on page 60 for the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automat-
ically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep
mode is independent of the CE#, WE#, and OE# control signals. Standard address access
timings provide new data when addresses are changed. While in sleep mode, output data is
latched and always available to the system. Refer to the “DC Characteristics” section on page
60 for the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data.
When the RESET# pin is driven low for at least a period of tRP, the device immediately termi-
nates any operation in progress, tristates all output pins, and ignores all read/write
commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V,
the device draws CMOS standby current (ICC5). If RESET# is held at VIL but not within
VSS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the Flash memory, enabling the system to read the boot-up firmware from the Flash
memory.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 15 for the timing
diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed
in the high impedance state.
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
21
A d v a n c e I n f o r m a t i o n
Table 2. S29GL064A Top Boot Sector Architecture
Sector Address
A21–A12
Sector Size
(KBs/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA0
0000000xxx
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
0011101xxx
0011110xxx
0011111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
0100000xxx
0100001xxx
0100010xxx
0101011xxx
22
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Table 2. S29GL064A Top Boot Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(KBs/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA36
SA37
SA38
SA39
SA40
SA41
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
0101111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
400000h–40FFFFh
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
470000h–47FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0100100xxx
0110101xxx
0110110xxx
0110111xxx
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
0111110xxx
0111111xxx
1000000xxx
1000001xxx
1000010xxx
1000011xxx
1000100xxx
1000101xxx
1000110xxx
1000111xxx
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
23
A d v a n c e I n f o r m a t i o n
Table 2. S29GL064A Top Boot Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(KBs/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
1010000xxx
1010001xxx
1010010xxx
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
1011101xxx
1011110xxx
1011111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
4B0000h–4BFFFFh
4C0000h–4CFFFFh
4D0000h–4DFFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
580000h–58FFFFh
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
650000h–65FFFFh
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
6B0000h–6BFFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
1100000xxx
1100001xxx
1100010xxx
1100011xxx
1100100xxx
1100101xxx
1100110xxx
1100111xxx
1101000xxx
1101001xxx
1101010xxx
1101011xxx
24
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Table 2. S29GL064A Top Boot Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(KBs/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA108
SA109
SA110
SA111
1101100xxx
1101101xxx
1101110xxx
1101111xxx
1110000xxx
1110001xxx
1110010xxx
1110011xxx
1110100xxx
1110101xxx
1110110xxx
1110111xxx
1111000xxx
1111001xxx
1111010xxx
1111011xxx
1111100xxx
1111101xxx
1111110xxx
1111111000
1111111001
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7F1FFFh
7F2000h–7F3FFFh
7F4000h–7F5FFFh
7F6000h–7F7FFFh
7F8000h–7F9FFFh
7FA000h–7FBFFFh
7FC000h–7FDFFFh
7FE000h–7FFFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3F8FFFh
3F9000h–3F9FFFh
3FA000h–3FAFFFh
3FB000h–3FBFFFh
3FC000h–3FCFFFh
3FD000h–3FDFFFh
3FE000h–3FEFFFh
3FF000h–3FFFFFh
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
8/4
1111111010
8/4
1111111011
8/4
1111111100
8/4
1111111101
8/4
1111111110
8/4
1111111111
8/4
Table 3. S29GL064A Bottom Boot Sector Architecture
Sector Address
A21–A12
Sector Size
(KBs/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA0
SA1
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
8/4
8/4
8/4
8/4
8/4
8/4
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
SA2
SA3
SA4
SA5
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
25
A d v a n c e I n f o r m a t i o n
Table 3. S29GL064A Bottom Boot Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(KBs/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA6
0000000110
0000000111
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
0011101xxx
0011110xxx
0011111xxx
8/4
00C000h–00DFFFh
00E000h–00FFFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
0100000xxx
0100001xxx
0100010xxx
26
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Table 3. S29GL064A Bottom Boot Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(KBs/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
0101111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
400000h–40FFFFh
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0100100xxx
0110101xxx
0110110xxx
0110111xxx
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
0111110xxx
0111111xxx
1000000xxx
1000001xxx
1000010xxx
1000011xxx
1000100xxx
1000101xxx
1000110xxx
SA72
SA73
SA74
SA75
SA76
SA77
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
27
A d v a n c e I n f o r m a t i o n
Table 3. S29GL064A Bottom Boot Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(KBs/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA78
SA79
SA80
SA81
1000111xxx
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
1010000xxx
1010001xxx
1010010xxx
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
1011101xxx
1011110xxx
1011111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
470000h–47FFFFh
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
4B0000h–4BFFFFh
4C0000h–4CFFFFh
4D0000h–4DFFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
580000h–58FFFFh
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
650000h–65FFFFh
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
1100000xxx
1100001xxx
1100010xxx
1100011xxx
1100100xxx
1100101xxx
1100110xxx
1100111xxx
1101000xxx
1101001xxx
1101010xxx
SA112
SA113
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S71GL064A based MCPs
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A d v a n c e I n f o r m a t i o n
Table 3. S29GL064A Bottom Boot Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(KBs/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
1101011xxx
1101100xxx
1101101xxx
1101110xxx
1101111xxx
1110000xxx
1110001xxx
1110010xxx
1110011xxx
1110100xxx
1110101xxx
1110110xxx
1110111xxx
1111000xxx
1111001xxx
1111010xxx
1111011xxx
1111100xxx
1111101xxx
1111110xxx
1111111000
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
6B0000h–6BFFFFh
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7FFFFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3FFFFFh
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector group pro-
tection verification, through identifier codes output on DQ7–DQ0. This mode is primarily
intended for programming equipment to automatically match a device to be programmed
with its corresponding programming algorithm. However, the autoselect codes can also be ac-
cessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9.
Address pins A6, A3, A2, A1, and A0 must be as shown in Table 4. In addition, when verifying
sector protection, the sector address must appear on the appropriate highest order address
bits. Table 4 shows the remaining address bits that are don’t care. When all necessary bits
have been set as required, the programming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command
via the command register, as shown in Table 10. This method does not require VID. Refer to
the Autoselect Command Sequence section for more information.
February 8, 2005 S71GL064A_00_A2
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A d v a n c e I n f o r m a t i o n
Table 4. Autoselect Codes, (High Voltage Method)
DQ8 to DQ15
A22 A14
A8
A5 A3
WE
#
Description
CE# OE#
to to A9 to A6 to to A1 A0
A15 A10
DQ7 to DQ0
BYTE# BYTE#=
A7
A4 A2
= VIH
VIL
Manufacturer
ID: Spansion
Products
L
L
L
L
L
L
H
H
H
X
X
X
X
X
VID
VID
VID
X
L
L
L
X
X
X
L
L
L
00
X
01h
Cycle 1
Cycle 2
L
H
L
H
H
L
22
22
X
X
7Eh
10h
X
X
00h (bottom boot)
01h (top boot)
Cycle 3
H
L
H
H
H
L
22
X
X
X
Sector Group
Protection
Verification
01h (protected),
00h (unprotected)
SA
Secured Silicon
Sector
98h (factory locked),
18h (not factory
locked)
Indicator Bit
(DQ7), WP#
protects
L
L
L
L
H
H
X
X
X
X
VID
X
X
L
L
X
X
L
L
H
H
H
H
X
X
X
X
highestaddress
sector
Secured Silicon
Sector
Indicator Bit
(DQ7), WP#
protects lowest
address sector
88h (factory locked),
08h (not factory
locked)
VID
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Group Protection and Unprotection
The hardware sector group protection feature disables both program and erase operations in
any sector group. In this device, a sector group consists of four adjacent sectors that are pro-
tected or unprotected at the same time (see Table 4). The hardware sector group
unprotection feature re-enables both program and erase operations in previously protected
sector groups. Sector group protection/unprotection can be implemented via two methods.
Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented
either in-system or via programming equipment. Figure 2 shows the algorithms and Figure
23 shows the timing diagram. This method uses standard microprocessor bus cycle timing.
For sector group unprotect, all unprotected sector groups must first be protected prior to the
first sector group unprotect write cycle.
The device is shipped with all sector groups unprotected. Spansion offers the option of pro-
gramming and protecting sector groups at its factory prior to shipping the device through
Spansion Programming Service. Contact a Spansion representative for details.
It is possible to determine whether a sector group is protected or unprotected. See the Au-
toselect Mode section for details.
30
S71GL064A based MCPs
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A d v a n c e I n f o r m a t i o n
Table 5. S29GL064A Sector Group Protection/Unprotection Address
Top Boot Sector
Sector Group
SA0
Bottom Boot Sector
A21–A15
0000000
0000001
0000010
0000011
00001xx
00010xx
00011xx
00100xx
00101xx
00110xx
00111xx
01000xx
01001xx
01010xx
01011xx
01100xx
01101xx
01110xx
01111xx
10000xx
10001xx
10010xx
10011xx
10100xx
10101xx
10110xx
10111xx
11000xx
11001xx
11010xx
11011xx
11100xx
11101xx
11110xx
1111100
1111101
1111110
1111111
SA1
SA2
SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124
SA125
SA126
SA127
February 8, 2005 S71GL064A_00_A2
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31
A d v a n c e I n f o r m a t i o n
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector groups to change
data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to
VID. During this mode, formerly protected sector groups can be programmed or erased by
selecting the sector group addresses. Once VID is removed from the RESET# pin, all the pre-
viously protected sector groups are protected again. Figure 1 shows the algorithm, and Figure
23 shows the timing diagrams, for this feature.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Group Unprotect Completed
(Note 2)
Notes:
1. All protected sector groups unprotected (If WP# = VIL, the first or last sector will remain protected).
2. All previously protected sector groups are protected once again.
Figure 1. Temporary Sector Group Unprotect Operation
32
S71GL064A based MCPs
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A d v a n c e I n f o r m a t i o n
START
START
PLSCNT = 1
PLSCNT = 1
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
RESET# = VID
Wait 1 µs
Wait 1 µs
Temporary Sector
Group Unprotect
Mode
Temporary Sector
Group Unprotect
Mode
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Yes
Yes
Set up sector
group address
All sector
groups
No
protected?
Yes
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up first sector
group address
Sector Group
Unprotect:
Wait 150 µs
Write 60h to sector
group address with
A6–A0 = 1xx0010
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
Read from
sector group address
with A6–A0
= 0xx0010
Increment
PLSCNT
A6–A0 = 1xx0010
No
No
PLSCNT
= 25?
Read from
sector group
address with
Data = 01h?
Yes
A6–A0 = 1xx0010
No
Yes
Set up
next sector group
address
Protect
another
sector group?
Yes
No
PLSCNT
= 1000?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
Last sector
group
verified?
No
Device failed
Write reset
command
Yes
Remove VID
from RESET#
Sector Group
Unprotect
Sector Group
Protect
Sector Group
Protect complete
Write reset
command
Algorithm
Algorithm
Sector Group
Unprotect complete
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
February 8, 2005 S71GL064A_00_A2
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33
A d v a n c e I n f o r m a t i o n
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables permanent
part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is
256 bytes in length, and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether
or not the Secured Silicon Sector is locked when shipped from the factory. This bit is perma-
nently set at the factory and cannot be changed, which prevents cloning of a factory locked
part. This ensures the security of the ESN once the product is shipped to the field.
The factory offers the device with the Secured Silicon Sector either customer lockable (stan-
dard shipping option) or factory locked (contact a Spansion sales representative for ordering
information). The customer-lockable version is shipped with the Secured Silicon Sector un-
protected, allowing customers to program the sector after receiving the device. The
customer-lockable version also has the Secured Silicon Sector Indicator Bit permanently set
to a “0.” The factory-locked version is always protected when shipped from the factory, and
has the Secured Silicon Sector Indicator Bit permanently set to a “1.” Thus, the Secured Sil-
icon Sector Indicator Bit prevents customer-lockable devices from being used to replace
devices that are factory locked. Note that the ACC function and unlock bypass modes are not
available when the Secured Silicon Sector is enabled.
The Secured Silicon sector address space in this device is allocated as follows:
Secured Silicon Sector
Address Range
ExpressFlash
Factory Locked
Customer Lockable ESN Factory Locked
ESN or determined by
customer
000000h–000007h
000008h–00007Fh
ESN
Determined by
customer
Determined by
customer
Unavailable
The system accesses the Secured Silicon Sector through a command sequence (see “Write
Protect (WP#)”). After the system has written the Enter Secured Silicon Sector command se-
quence, it may read the Secured Silicon Sector by using the addresses normally occupied by
the first sector (SA0). This mode of operation continues until the system issues the Exit Se-
cured Silicon Sector command sequence, or until power is removed from the device. On
power-up, or following a hardware reset, the device reverts to sending commands to sector
SA0.
Customer Lockable: Secured Silicon Sector NOT Programmed or
Protected At the Factory
Unless otherwise specified, the device is shipped such that the customer may program and
protect the 256-byte Secured Silicon sector.
The system may program the Secured Silicon Sector using the write-buffer, accelerated and/
or unlock bypass methods, in addition to the standard programming command sequence. See
Command Definitions.
Programming and protecting the Secured Silicon Sector must be used with caution since, once
protected, there is no procedure available for unprotecting the Secured Silicon Sector area
and none of the bits in the Secured Silicon Sector memory space can be modified in any way.
The Secured Silicon Sector area can be protected using one of the following procedures:
Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then
follow the in-system sector protect algorithm as shown in Figure 2, except that RESET#
may be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector
without raising any device pin to a high voltage. Note that this method is only applicable
to the Secured Silicon Sector.
To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm
shown in Figure 1.
34
S71GL064A based MCPs
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A d v a n c e I n f o r m a t i o n
Once the Secured Silicon Sector is programmed, locked and verified, the system must write
the Exit Secured Silicon Sector Region command sequence to return to reading and writing
within the remainder of the array.
Factory Locked: Secured Silicon Sector Programmed and Protected At
the Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped
from the factory. The Secured Silicon Sector cannot be modified in any way. An ESN Factory
Locked device has an 16-byte random ESN at addresses 000000h–000007h. Please contact
your sales representative for details on ordering ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the Spansion pro-
gramming service (Customer Factory Locked). The devices are then shipped from the factory
with the Secured Silicon Sector permanently locked. Contact your sales representative for de-
tails on using the Spansion programming service.
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or last sector
group without using VID. Write Protect is one of two functions provided by the WP#/ACC
input.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase func-
tions in the first or last sector group independently of whether those sector groups were
protected or unprotected. Note that if WP#/ACC is at VIL when the device is in the standby
mode, the maximum input load current is increased. See the table in “DC Characteristics” sec-
tion on page 60.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the
first or last sector was previously set to be protected or unprotected using the
method described in “Sector Group Protection and Unprotection”. Note that WP#
has an internal pullup; when unconnected, WP# is at VIH
.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides
data protection against inadvertent writes (refer to Tables 16 and 17 for command defini-
tions). In addition, the following hardware data protection measures prevent accidental
erasure or programming, which might otherwise be caused by spurious system level signals
during VCC power-up and power-down transitions, or from system noise.
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This protects data
during VCC power-up and power-down. The command register and all internal program/erase
circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored
until VCC is greater than VLKO. The system must provide the proper signals to the control pins
to prevent unintentional writes when VCC is greater than VLKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To ini-
tiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
February 8, 2005 S71GL064A_00_A2
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35
A d v a n c e I n f o r m a t i o n
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands
on the rising edge of WE#. The internal state machine is automatically reset to the read mode
on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software in-
terrogation handshake, which allows specific vendor-specified software algorithms to be used
for entire families of devices. Software support can then be device-independent, JEDEC ID-
independent, and forward- and backward-compatible for the specified flash device families.
Flash vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h,
to address 55h, any time the device is ready to read array data. The system can read CFI
information at the addresses given in Tables 27-30. To terminate reading CFI data, the system
must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode.
The device enters the CFI query mode, and the system can read CFI data at the addresses
given in Tables 27-30. The system must write the reset command to return the device to
reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100, avail-
able via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact your
sales representative for copies of these documents.
36
S71GL064A based MCPs
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A d v a n c e I n f o r m a t i o n
Table 6. CFI Query Identification String
Addresses (x16)
Addresses (x8)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Table 7. System Interface String
Addresses (x16)
Addresses (x8)
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
36h
0027h
VCC Max. (write/erase)
1Ch
38h
0036h
D7–D4: volt, D3–D0: 100 millivolt
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Reserved for future use
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0007h
0007h
000Ah
0000h
0001h
0005h
0004h
0000h
Typical timeout for Min. size buffer write 2N
µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Reserved for future use
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Note: CFI data related to VCC and time-outs may differ from actual VCC and time-outs of the product. Please consult the Ordering
Information tables to obtain the VCC range for particular part numbers. Please contact the Erase and Programming Performance table for
typical timeout specifications.
February 8, 2005 S71GL064A_00_A2
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37
A d v a n c e I n f o r m a t i o n
Table 8. Device Geometry Definition
Addresses (x16)
Addresses (x8)
Data
Description
Device Size = 2N byte
0017h = 64 Mb
27h
4Eh
00xxh
Flash Device Interface description (refer to CFI publication 100)
28h
29h
50h
52h
000xh
0000h
0000h = x8-only bus devices
0001h = x16-only bus devices
0002h = x8/x16 bus devices
2Ah
2Bh
54h
56h
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device (01h = uniform device,
02h = boot device)
2Ch
58h
00xxh
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
000xh
00x0h
000xh
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
007Fh, 0000h, 0000h, 0001h = 64 Mb
31h
32h
33h
34h
60h
64h
66h
68h
00xxh
0000h
0000h
000xh
Erase Block Region 2 Information (refer to CFI publication 100)
0000h, 0000h, 0000h, 0000h =64 Mb
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Table 9. Primary Vendor-Specific Extended Query
Addresses (x16)
Addresses (x8)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
000xh
Process Technology (Bits 7-2) 0010b = 200 nm MirrorBit
0009h = x8-only bus devices
0008h = all other devices
Erase Suspend
46h
47h
48h
8Ch
8Eh
90h
0002h
0001h
0000h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
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S71GL064A based MCPs
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A d v a n c e I n f o r m a t i o n
Addresses (x16)
Addresses (x8)
Data
Description
Sector Protect/Unprotect scheme
49h
92h
94h
96h
98h
0004h
0004h = Standard Mode (Refer to Text)
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
4Ah
4Bh
4Ch
0000h
0000h
0001h
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
9Ah
9Ch
00B5h
00C5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
00h = Uniform Device without WP# protect, 02h = Bottom Boot
Device, 03h = Top Boot Device, 04h = Uniform sectors bottom WP#
protect, 05h = Uniform sectors top WP# protect
4Fh
50h
9Eh
A0h
00xxh
0001h
Program Suspend
00h = Not Supported, 01h = Supported
February 8, 2005 S71GL064A_00_A2
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A d v a n c e I n f o r m a t i o n
Command Definitions
Writing specific address and data commands or sequences into the command register initiates
device operations. Table 10 defines the valid register command sequences. Writing incorrect
address and data values or writing them in the improper sequence may place the device in
an unknown state. A reset command is then required to return the device to reading array
data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data
is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Char-
acteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands
are required to retrieve data. The device is ready to read array data after completing an Em-
bedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the erase-suspend-
read mode, after which the system can read data from any non-erase-suspended sector. After
completing a programming operation in the Erase Suspend mode, the system may once again
read array data with the same exception. See the Erase Suspend/Erase Resume Commands
section for more information.
The system must issue the reset command to return the device to the read (or erase-sus-
pend-read) mode if DQ5 goes high during an active program or erase operation, or if the
device is in the autoselect mode. See the next section, Reset Command, for more
information.
See also Requirements for Reading Array Data in the Device Bus Operations section for more
information. The Read-Only Operations–“AC Characteristics” section on page 63 provides the
read parameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Ad-
dress bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase command se-
quence before erasing begins. This resets the device to the read mode. Once erasure begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command se-
quence before programming begins. This resets the device to the read mode. If the program
command sequence is written while the device is in the Erase Suspend mode, writing the
reset command returns the device to the erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command
sequence. Once in the autoselect mode, the reset command must be written to return to the
read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writ-
ing the reset command returns the device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the
device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Programming operation, the system must
write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next
operation.
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Autoselect Command Sequence
The autoselect command sequence allows the host system to read several identifier codes at
specific addresses:
A7:A0
(x16)
A6:A-1
(x8)
Identifier Code
Manufacturer ID
Device ID, Cycle 1
00h
01h
00h
02h
Device ID, Cycle 2
0Eh
1Ch
Device ID, Cycle 3
0Fh
1Eh
Secured Silicon Sector Factory Protect
Sector Protect Verify
03h
06h
(SA)02h
(SA)04h
Note: The device ID is read over three cycles. SA = Sector Address
The autoselect command sequence is initiated by first writing two unlock cycles. This is fol-
lowed by a third write cycle that contains the autoselect command. The device then enters
the autoselect mode. The system may read at any address any number of times without ini-
tiating another autoselect command sequence:
The system must write the reset command to return to the read mode (or erase-suspend-
read mode if the device was previously in Erase Suspend).
Enter Secured Silicon Sector/Exit Secured Silicon
Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing an 8-word/16-byte
random Electronic Serial Number (ESN). The system can access the Secured Silicon Sector
region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The de-
vice continues to access the Secured Silicon Sector region until the system issues the four-
cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector com-
mand sequence returns the device to normal operation. Table 10 shows the address and data
requirements for both command sequences. See also “Secured Silicon Sector Flash
Memory Region” for further information. Note that the ACC function and unlock bypass modes
are not available when the Secured Silicon Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by
writing two unlock write cycles, followed by the program set-up command. The program ad-
dress and data are written next, which in turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or timings. The device automatically pro-
vides internally generated program pulses and verifies the programmed cell margin. Tables
31 and 32 show the address and data requirements for the word program command se-
quence, respectively.
When the Embedded Program algorithm is complete, the device then returns to the read
mode and addresses are no longer latched. The system can determine the status of the pro-
gram operation by using DQ7 or DQ6. Refer to the Write Operation Status section for
information on these status bits. Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that the Secured Silicon Sector, autoselect, and CFI
functions are unavailable when a program operation is in progress. Note that a hardware
reset immediately terminates the program operation. The program command sequence
should be reinitiated once the device has returned to the read mode, to ensure data integrity.
February 8, 2005 S71GL064A_00_A2
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A d v a n c e I n f o r m a t i o n
Programming is allowed in any sequence of address locations and across sector boundaries.
Programming to the same word address multiple times without intervening erases (incremen-
tal bit programming) requires a modified programming method. For such application
requirements, please contact your local Spansion representative. Word programming is sup-
ported for backward compatibility with existing Flash driver software and for occasional
writing of individual words. Use of write buffer programming (see below) is strongly recom-
mended for general programming use when more than a few words are to be programmed.
The effective word programming time using write buffer programming is approximately four
times shorter than the single word programming time.
Any bit in a word cannot be programmed from “0” back to a “1.” Attempting to do so
may cause the device to set DQ5=1, or cause DQ7 and DQ6 status bits to indicate the oper-
ation was successful. However, a succeeding read will show that the data is still “0.” Only
erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using
the standard program command sequence. The unlock bypass command sequence is initiated
by first writing two unlock cycles. This is followed by a third write cycle containing the unlock
bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock
bypass mode command sequence is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed in the same manner.
This mode dispenses with the initial two unlock cycles required in the standard program com-
mand sequence, resulting in faster total programming time. Tables 31 and 32 show the
requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle
unlock bypass reset command sequence. The first cycle must contain the data 90h. The sec-
ond cycle must contain the data 00h. The device then returns to the read mode.
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one
programming operation. This results in faster effective programming time than the standard
programming algorithms. The Write Buffer Programming command sequence is initiated by
first writing two unlock cycles. This is followed by a third write cycle containing the Write
Buffer Load command written at the Sector Address in which programming will occur. The
fourth cycle writes the sector address and the number of word locations, minus one, to be
programmed. For example, if the system will program 6 unique address locations, then 05h
should be written to the device. This tells the device how many write buffer addresses will be
loaded with data and therefore when to expect the Program Buffer to Flash command. The
number of locations to program cannot exceed the size of the write buffer or the operation
will abort.
The fifth cycle writes the first address location and data to be programmed. The write-buffer-
page is selected by address bits AMAX–A4. All subsequent address/data pairs must fall within
the selected-write-buffer-page. The system then writes the remaining address/data pairs into
the write buffer. Write buffer locations may be loaded in any order.
The write-buffer-page address must be the same for all address/data pairs loaded into the
write buffer. (This means Write Buffer Programming cannot be performed across multiple
write-buffer pages.) This also means that Write Buffer Programming cannot be performed
across multiple sectors. If the system attempts to load programming data outside of the se-
lected write-buffer page, the operation will abort.
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Note that if a Write Buffer address location is loaded multiple times, the address/data pair
counter will be decremented for every data load operation. The host system must therefore
account for loading a write-buffer location more than once. The counter decrements for each
data load operation, not for each unique write-buffer-address location. Note also that if an
address location is loaded more than once into the buffer, the final data loaded for that ad-
dress will be programmed.
Once the specified number of write buffer locations have been loaded, the system must then
write the Program Buffer to Flash command at the sector address. Any other address and data
combination aborts the Write Buffer Programming operation. The device then begins pro-
gramming. Data polling should be used while monitoring the last address location loaded into
the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device sta-
tus during Write Buffer Programming.
The write-buffer programming operation can be suspended using the standard program sus-
pend/resume commands. Upon successful completion of the Write Buffer Programming
operation, the device is ready to execute the next command.
February 8, 2005 S71GL064A_00_A2
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A d v a n c e I n f o r m a t i o n
The Write Buffer Programming Sequence can be aborted in the following ways:
Load a value that is greater than the page buffer size during the Number of Locations to
Program step.
Write to an address in a sector different than the one specified during the Write-Buffer-
Load command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the
Starting Address during the write buffer data loading stage of the operation.
Write data other than the Confirm Command after the specified number of data load cy-
cles.
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location
loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must
be written to reset the device for the next operation.
Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a
program operation is in progress.This flash device is capable of handling multiple write buffer
programming operations on the same write buffer address range without intervening erases.
For applications requiring incremental bit programming, a modified programming method is
required; please contact your local Spansion representative. Any bit in a write buffer ad-
dress range cannot be programmed from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5=1, of cause the DQ7 and DQ6 status bits to indicate the opera-
tion was successful. However, a succeeding read will show that the data is still “0.” Only erase
operations can convert a “0” to a “1.”
Accelerated Program
The device offers accelerated program operations through the WP#/ACC or ACC pin depend-
ing on the particular product. When the system asserts VHH on the WP#/ACC or ACC pin. The
device uses the higher voltage on the WP#/ACC or ACC pin to accelerate the operation. Note
that the WP#/ACC pin must not be at VHH for operations other than accelerated program-
ming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is
at VIH
.
Figure 4 illustrates the algorithm for the program operation. Refer to the Erase and Program
Operations–“AC Characteristics” section on page 63 section for parameters, and Figure 16 for
timing diagrams.
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Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Buffer Operation?
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
Write next address/data pair
(Note 1)
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Read DQ7 - DQ0 at
Last Loaded Address
Notes:
1. When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations
Yes
with data, all addresses must fall within
DQ7 = Data?
No
the selected Write-Buffer Page.
2. DQ7 may change simultaneously with
DQ5. Therefore, DQ7 should be verified.
No
3. If this flowchart location was reached
because DQ5= “1”, then the device
FAILED. If this flowchart location was
reached because DQ1= “1”, then the
Write to Buffer operation was ABORTED.
In either case, the proper reset command
must be written before the device can
begin another operation. If DQ1=1, write
the Write-Buffer-Programming-Abort-
Reset command. if DQ5=1, write the
Reset command.
No
DQ1 = 1?
DQ5 = 1?
Yes
Yes
Read DQ7 - DQ0 with
address = Last Loaded
Address
4. See Table 10 and for command
sequences required for write buffer
programming.
Yes
(Note 2)
DQ7 = Data?
No
FAIL or ABORT
PASS
(Note 3)
Figure 3. Write Buffer Programming Operation
February 8, 2005 S71GL064A_00_A2
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A d v a n c e I n f o r m a t i o n
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
Note:See Table 10 for program command sequence.
Figure 4. Program Operation
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming operation or
a Write to Buffer programming operation so that data can be read from any non-suspended
sector. When the Program Suspend command is written during a programming process, the
device halts the program operation within 15 µs maximum (5µs typical) and updates the sta-
tus bits. Addresses are not required when writing the Program Suspend command.
After the programming operation has been suspended, the system can read array data from
any non-suspended sector. The Program Suspend command may also be issued during a pro-
gramming operation while an erase is suspended. In this case, data may be read from any
addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured
Silicon Sector area (One-time Program area), then user must use the proper command se-
quences to enter and exit this region. Note that the Secured Silicon Sector, autoselect, and
CFI functions are unavailable when a program operation is in progress.
The system may also write the autoselect command sequence when the device is in the Pro-
gram Suspend mode. The system can read as many autoselect codes as required. When the
device exits the autoselect mode, the device reverts to the Program Suspend mode, and is
ready for another valid operation. See Autoselect Command Sequence for more information.
After the Program Resume command is written, the device reverts to programming. The sys-
tem can determine the status of the program operation using the DQ7 or DQ6 status bits, just
as in the standard program operation. See Write Operation Status for more information.
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The system must write the Program Resume command (address bits are don’t care) to exit
the Program Suspend mode and continue the programming operation. Further writes of the
Resume command are ignored. Another Program Suspend command can be written after the
device has resumed programming.
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A d v a n c e I n f o r m a t i o n
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Write address/data
XXXh/B0h
Command is also valid for
Erase-suspended-program
operations
Wait 15 µs
Autoselect and SecSi Sector
read operations are also allowed
Read data as
required
Data cannot be read from erase- or
program-suspended sectors
Done
No
reading?
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Figure 5. Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writ-
ing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are
then followed by the chip erase command, which in turn invokes the Embedded Erase algo-
rithm. The device does not require the system to preprogram prior to erase. The Embedded
Erase algorithm automatically preprograms and verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to provide any controls or timings
during these operations. Table 10 shows the address and data requirements for the chip erase
command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read mode and
addresses are no longer latched. The system can determine the status of the erase operation
by using DQ7, DQ6, or DQ2. Refer to the Write Operation Status section for information on
these status bits.
Any commands written during the chip erase operation are ignored. However, note that a
hardware reset immediately terminates the erase operation. If that occurs, the chip erase
command sequence should be reinitiated once the device has returned to reading array data,
to ensure data integrity.
Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Op-
erations table in the AC Characteristics section for parameters, and Figure 18 section for
timing diagrams.
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Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by
writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are
written, and are then followed by the address of the sector to be erased, and the sector erase
command. Table 10 shows the address and data requirements for the sector erase command
sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase
algorithm automatically programs and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or timings during
these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs. During the
time-out period, additional sector addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any sequence, and the number of sectors may
be from one sector to all sectors. The time between these additional cycles must be less than
50 µs, otherwise erasure may begin. Any sector erase address and command following the
exceeded time-out may or may not be accepted. It is recommended that processor interrupts
be disabled during this time to ensure all commands are accepted. The interrupts can be
re-enabled after the last Sector Erase command is written. Any command other than Sec-
tor Erase or Erase Suspend during the time-out period resets the device to the read
mode. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable
when an erase operation is in progress. The system must rewrite the command sequence and
any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the
section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final
WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading array data
and addresses are no longer latched. The system can determine the status of the erase op-
eration by reading DQ7, DQ6, or DQ2 in the erasing sector. Refer to the Write Operation
Status section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All
other commands are ignored. However, note that a hardware reset immediately terminates
the erase operation. If that occurs, the sector erase command sequence should be reinitiated
once the device has returned to reading array data, to ensure data integrity.
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A d v a n c e I n f o r m a t i o n
Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Op-
erations table in the AC Characteristics section for parameters, and Figure 18 section for
timing diagrams.
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 10 for program command sequence.
2. See the section on DQ3 for information on the sector erase timer.
Figure 6. Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation
and then read data from, or program data to, any sector not selected for erasure. This com-
mand is valid only during the sector erase operation, including the 50 µs time-out period
during the sector erase command sequence. The Erase Suspend command is ignored if writ-
ten during the chip erase operation or Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation, the device
requires a typical of 5 µs (maximum of 20 µs) to suspend the erase operation. However, when
the Erase Suspend command is written during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the erase operation.
After the erase operation has been suspended, the device enters the erase-suspend-read
mode. The system can read data from or program data to any sector not selected for erasure.
(The device “erase suspends” all sectors selected for erasure.) Reading at any address within
erase-suspended sectors produces status information on DQ7–DQ0. The system can use
DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-sus-
pended. Refer to the Write Operation Status section for information on these status bits.
After an erase-suspended program operation is complete, the device returns to the erase-
suspend-read mode. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to the Write
Operation Status section for more information.
In the erase-suspend-read mode, the system can also issue the autoselect command se-
quence. Refer to the “Autoselect Mode” section on page 29 and “Autoselect Command
Sequence” section on page 41 sections for details.
To resume the sector erase operation, the system must write the Erase Resume command.
Further writes of the Resume command are ignored. Another Erase Suspend command can
be written after the chip has resumed erasing.
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Note: During an erase operation, this flash device performs multiple internal oper-
ations which are invisible to the system. When an erase operation is suspended, any
of the internal operations that were not fully completed must be restarted. As such,
if this flash device is continually issued suspend/resume commands in rapid suc-
cession, erase progress will be impeded as a function of the number of suspends.
The result will be a longer cumulative erase time than without suspends. Note that
the additional suspends do not affect device reliability or future performance. In
most systems rapid erase/suspend activity occurs only briefly. In such cases, erase
performance will not be significantly impacted.
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A d v a n c e I n f o r m a t i o n
Command Definitions
Table 10. Command Definitions (x16 Mode, BYTE# = VIH
)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Data
Fifth
Sixth
Addr Data
Addr
Data
Data
Addr
Addr
Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
4
RA
RD
F0
XXX
555
Manufacturer ID
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
(Note
18)
(Note
18)
Device ID (Note 9)
4
4
555
555
AA
AA
X0E
X0F
Secured SiliconSector Factory
Protect (Note 10)
2AA
2AA
55
55
555
555
90
90
X03
(Note 10)
00/01
Sector Group Protect Verify (Note
12)
4
555
AA
(SA)X02
Enter Secured Silicon Sector Region
Exit Secured Silicon Sector Region
Program
3
4
4
3
1
3
3
2
2
6
6
1
1
1
555
555
555
555
SA
AA
AA
AA
AA
29
AA
AA
A0
90
AA
AA
B0
30
98
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
00
PD
WC
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 13)
Unlock Bypass
SA
PA
PD
WBL
PD
555
555
XXX
XXX
555
555
XXX
XXX
55
2AA
2AA
PA
55
55
PD
00
55
55
555
555
F0
20
Unlock Bypass Program (Note 14)
Unlock Bypass Reset (Note 15)
Chip Erase
XXX
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend (Note 16)
Program/Erase Resume (Note 17)
CFI Query (Note 18)
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 1 for description of bus operations.
10. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
2. All values are in hexadecimal.
11. Total number of cycles in command sequence is determined by
number of words written to write buffer. Maximum number of
cycles in command sequence is 21, including “Program Buffer to
Flash” command.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
13. Unlock Bypass command is required prior to Unlock Bypass
Program command.
14. Unlock Bypass Reset command is required to return to read
mode when device is in unlock bypass mode.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are
555 or 2AA as shown in table, address bits above A11 and data
bits above DQ7 are don’t care.
5. No unlock or command cycles required when device is in read
mode.
6. Reset command is required to return to read mode (or to erase-
suspend-read mode if previously in Erase Suspend) when device
is in autoselect mode, or if DQ5 goes high while device is
providing status information.
15. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
16. Erase Resume command is valid only during Erase Suspend
mode.
7. Fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD
and WC. See Autoselect Command Sequence section for more
information.
8. Device ID must be read in three cycles.
17. Command is valid when device is ready to read array data or
when device is in autoselect mode.
18. Refer to Table 4, AutoSelect Codes for individual Device IDs per
device density and model number.
9. If WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. If WP# protects lowest
address sector, data is 88h for factory locked and 08h for not
factor locked.
52
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Write Operation Status
The device provides several bits to determine the status of a program or erase operation:
DQ2, DQ3, DQ5, DQ6, and DQ7. Table 11 and the following subsections describe the function
of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase
operation is complete or in progress. The device also provides a hardware-based output sig-
nal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress
or has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or
Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data#
Polling is valid after the rising edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Sus-
pend. When the Embedded Program algorithm is complete, the device outputs the datum
programmed to DQ7. The system must provide the program address to read valid status in-
formation on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7
is active for approximately 1 µs, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Em-
bedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data#
Polling produces a “1” on DQ7. The system must provide an address within any of the sectors
selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to the read
mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the un-
protected sectors, and ignores the selected sectors that are protected. However, if the system
reads DQ7 at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device
may change from providing status information to valid data on DQ7. Depending on when the
system samples the DQ7 output, it may read the status or valid data. Even if the device has
completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0–
DQ6 may be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.
Table 11 shows the outputs for Data# Polling on DQ7. Figure 7 shows the Data# Polling al-
gorithm. Figure 19 in the AC Characteristics section shows the Data# Polling timing diagram.
February 8, 2005 S71GL064A_00_A2
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53
A d v a n c e I n f o r m a t i o n
START
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector
being erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 7. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Al-
gorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final
WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY#
pins can be tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes pro-
gramming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read
mode, the standby mode, or in the erase-suspend-read mode. Table 11 shows the outputs
for RY/BY#.
54
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress
or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may
be read at any address, and is valid after the rising edge of the final WE# pulse in the com-
mand sequence (prior to the program or erase operation), and during the sector erase time-
out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles.
When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected,
DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ig-
nores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing
or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase al-
gorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6
stops toggling. However, the system must also use DQ2 to determine which sectors are eras-
ing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7:
Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after
the program command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Em-
bedded Program algorithm is complete.
Table 11 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit algorithm.
Figure 20 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 21
shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on
DQ2: Toggle Bit II.
February 8, 2005 S71GL064A_00_A2
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A d v a n c e I n f o r m a t i o n
START
Read DQ7–DQ0
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note:
The system should recheck the toggle bit even if DQ5 = “1”
because the toggle bit may stop toggling as DQ5 changes to
“1.” See the subsections on DQ6 and DQ2 for more
information.
Figure 8. Toggle Bit Algorithm
56
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is ac-
tively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector
is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the
command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been se-
lected for erasure. (The system may use either OE# or CE# to control the read cycles.) But
DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by
comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but can-
not distinguish which sectors are selected for erasure. Thus, both status bits are required for
sector and mode information. Refer to Table 11 to compare outputs for DQ2 and DQ6.
Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit
II” explains the algorithm. See also the RY/BY#: Ready/Busy# subsection. Figure 20 shows
the toggle bit timing diagram. Figure 21 shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle
bit is toggling. Typically, the system would note and store the value of the toggle bit after the
first read. After the second read, the system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device has completed the program or erase
operation. The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still
toggling, the system also should note whether the value of DQ5 is high (see the section on
DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the program or erase operation. If it is still
toggling, the device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling
and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5
through successive read cycles, determining the status as described in the previous para-
graph. Alternatively, it may choose to perform other system tasks. In this case, the system
must start at the beginning of the algorithm when it returns to determine the status of the
operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified
internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the pro-
gram or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that
was previously programmed to “0.” Only an erase operation can change a “0” back to a
“1.” Under this condition, the device halts the operation, and when the timing limit has been
exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset command to return the device to the read-
ing the array (or to erase-suspend-read if the device was previously in the erase-suspend-
program mode).
February 8, 2005 S71GL064A_00_A2
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57
A d v a n c e I n f o r m a t i o n
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine
whether or not erasure has begun. (The sector erase timer does not apply to the chip erase
command.) If additional sectors are selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out period is complete, DQ3 switches
from a “0” to a “1.” If the time between additional sector erase commands from the system
can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector
Erase Command Sequence section.
After the sector erase command is written, the system should read the status of DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence,
and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further com-
mands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is
“0,” the device will accept additional sector erase commands. To ensure the command has
been accepted, the system software should check the status of DQ3 prior to and following
each subsequent sector erase command. If DQ3 is high on the second status check, the last
command might not have been accepted.
Table 11 shows the status of DQ3 relative to the other status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1
produces a “1”. The system must issue the Write-to-Buffer-Abort-Reset command sequence
to return the device to reading array data. See Write Buffer section for more details.
Table 11. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
DQ1
0
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Program-Suspended
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
N/A
Invalid (not allowed)
Data
1
1
1
1
0
Program
Suspend
Mode
Program-
Suspend
Read
Sector
Non-Program
Suspended Sector
Erase-Suspended
Sector
1
No toggle
Toggle
0
N/A
Toggle
N/A
N/A
N/A
Erase-
Suspend
Read
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Erase-Suspend-Program
(Embedded Program)
DQ7#
0
N/A
Busy (Note 3)
Abort (Note 4)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Write-to-
Buffer
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.
58
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Absolute Maximum Ratings
Storage Temperature, Plastic Packages. . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground:
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
. . . . . . . . . . . . A9, OE#, ACC and RESET# (Note 2)–0.5 V to +12.5 V
All other pins (Note 1). . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs
or I/Os may overshoot V to –2.0 V for periods of up to 20 ns. See Figure 9.
SS
Maximum DC voltage on input or I/Os is V + 0.5 V. During voltage transitions,
CC
input or I/O pins may overshoot to V + 2.0 V for periods up to 20 ns. See Figure
CC
10.
2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During
voltage transitions, A9, OE#, ACC, and RESET# may overshoot V to –2.0 V for
SS
periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pin A9, OE#,
ACC, and RESET# is +12.5 V which may overshoot to +14.0V for periods up to 20
ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods may affect device
reliability.
20 ns
20 ns
20 ns
VCC
+2.0 V
+0.8 V
VCC
–0.5 V
–2.0 V
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 9. Maximum Negative Overshoot
Waveform
Figure 10. Maximum Positive Overshoot
Waveform
Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC for full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V
VCC for regulated voltage range. . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V
VIO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC
Note:Operating ranges define those limits between which the functionality of the device is guaranteed
.
February 8, 2005 S71GL064A_00_A2
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59
A d v a n c e I n f o r m a t i o n
DC Characteristics
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
(Notes)
V
IN = VSS to VCC,
ILI
Input Load Current (Note 1)
±1.0
µA
VCC = VCC max
ILIT
ILR
A9, ACC Input Load Current
Reset Leakage Current
VCC = VCC max; A9 = 12.5 V
35
35
µA
µA
VCC = VCC max; RESET# = 12.5 V
V
OUT = VSS to VCC
,
ILO
Output Leakage Current
±1.0
µA
VCC = VCC max
1 MHz
5
20
25
50
20
40
60
ICC1
VCC Initial Read Current (Notes 2, 3)
CE# = VIL, OE# = VIH
,
5 MHz
18
35
5
mA
10 MHz
10 MHz
40 MHz
ICC2
VCC Intra-Page Read Current (Notes 2, 3) CE# = VIL, OE# = VIH
mA
10
50
ICC3
ICC4
ICC5
ICC6
VCC Active Write Current (Note 3)
VCC Standby Current (Note 3)
VCC Reset Current (Note 3)
CE# = VIL, OE# = VIH
mA
µA
µA
µA
CE#, RESET# = VCC ± 0.3 V,
WP# = VIH
1
1
1
5
5
5
RESET# = VSS ± 0.3 V, WP# = VIH
VIH = VCC ± 0.3 V;
-0.1< VIL ≤ 0.3 V, WP# = VIH
Automatic Sleep Mode (Notes 3, 5)
VIL
VIH
VHH
Input Low Voltage 1 (Note 6)
–0.5
0.7 VCC
11.5
0.8
VCC + 0.5
12.5
V
V
V
Input High Voltage 1 (Note 6)
Voltage for ACC Program Acceleration
VCC = 2.7 –3.6 V
VCC = 2.7 –3.6 V
12.0
12.0
Voltage for Autoselect and Temporary
Sector Unprotect
VID
11.5
12.5
0.45
V
VOL
Output Low Voltage (Note 6)
IOL = 4.0 mA, VCC = VCC min
IOH = –2.0 mA, VCC = VCC min
IOH = –100 µA, VCC = VCC min
V
V
V
V
VOH1
VOH2
VLKO
0.85 VCC
VCC–0.4
2.3
Output High Voltage
Low VCC Lock-Out Voltage (Note 7)
2.5
Notes:
1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 2.0 µA.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH
.
3. Maximum ICC specifications are tested with VCC = VCCmax.
4.
ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
6. VCC voltage requirements.
7. Not 100% tested.
60
S71GL064A based MCPs
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A d v a n c e I n f o r m a t i o n
Test Conditions
Table 12. Test Specifications
3.3 V
Test Condition
All Speeds
1 TTL gate
Unit
Output Load
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
0.0 or VCC
Input timing measurement
reference levels (See Note)
0.5 VCC
0.5 VCC
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent.
Figure 11. Test Setup
February 8, 2005 S71GL064A_00_A2
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61
A d v a n c e I n f o r m a t i o n
Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
V
CC
0.5 V
Input
0.5 V
Measurement Level
Output
CC
CC
0.0 V
Figure 12. Input Waveforms and Measurement Levels
62
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
AC Characteristics
Read-Only Operations-S29GL064A only
Parameter
Speed Options
Description
Te s t S e t u p
Unit
JEDEC
tAVAV
tAVQV
tELQV
Std.
100
100
100
100
25
tRC Read Cycle Time (Note 1)
tACC Address to Output Delay
tCE Chip Enable to Output Delay
tPACC Page Access Time
Min
CE#, OE# = VIL Max
ns
ns
ns
ns
ns
ns
ns
OE# = VIL
Max
Max
Max
Max
Max
tGLQV
tEHQZ
tGHQZ
tOE Output Enable to Output Delay
tDF Chip Enable to Output High Z (Note 1)
tDF Output Enable to Output High Z (Note 1)
25
16
16
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold
Time (Note 1)
tOEH
Toggle and
Data# Polling
10
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 12 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tRH
tRH
tDF
tOE
OE#
WE#
tOEH
tCE
tOH
Valid Data
HIGH Z
HIGH Z
Data
RESET#
RY/BY#
0 V
Figure 13. Read Operation Timings
February 8, 2005 S71GL064A_00_A2
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63
A d v a n c e I n f o r m a t i o n
Same Page
A23-A2
A1-A0*
Ad
Aa
tACC
Ab
tPACC
Ac
tPACC
tPACC
Data Bus
Qa
Qb
Qc
Qd
CE#
OE#
Note: Shows device in word mode. Addresses are A1–A-1 for byte mode
.
Figure 14. Page Read Timings
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Input Low to Standby Mode (See Note)
RY/BY# Output High to CE#, OE# pin Low
Note:Not 100% tested
.
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S71GL064A based MCPs
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A d v a n c e I n f o r m a t i o n
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 15. Reset Timings
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
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A d v a n c e I n f o r m a t i o n
Erase and Program Operations-S29GL064A Only
Parameter
JEDEC
tAVAV
tAVWL
Speed Options
Unit
Std.
tWC
tAS
Description
Write Cycle Time (Note 1)
100
100
0
Min
Min
Min
Min
ns
ns
ns
ns
Address Setup Time
tASO
tAH
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
45
tWLAX
Address Hold Time From CE# or OE# high during toggle bit
polling
tAHT
Min
0
ns
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Min
Min
Max
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold Time
tCEPH
tOEPH
tGHWL
tCS
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
20
20
0
tGHWL
tELWL
0
tWHEH
tWLWH
tWHDL
tCH
CE# Hold Time
0
tWP
Write Pulse Width
35
30
240
60
54
0.5
250
50
90
4
tWPH
Write Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
VHH Rise and Fall Time (Note 1)
VCC Setup Time (Note 1)
tWHWH1
tWHWH1
µs
tWHWH2
tWHWH2
tVHH
sec
ns
µs
ns
µs
tVCS
tBUSY
tPOLL
WE# High to RY/BY# Low
Program Valid before Status Polling
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming has resumed
(that is, the program resume command has been written). If the suspend command was issued after tPOLL, status data is available
immediately after programming has resumed. See Figure 16.
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A d v a n c e I n f o r m a t i o n
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tPOLL
tWP
WE#
Data
tWPH
tCS
tWHWH1
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 16. Program Operation Timings
V
HH
V
or V
IL IH
V
or V
IL IH
ACC
t
t
VHH
VHH
Figure 17. Accelerated Program Timing Diagram
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67
A d v a n c e I n f o r m a t i o n
Erase Command Sequence (last two cycles)
Read Status Data
tAS
SA
tWC
VA
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.)
2. Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
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S71GL064A based MCPs
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A d v a n c e I n f o r m a t i o n
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
tPOLL
tCH
tOE
OE#
WE#
tDF
tOH
tOEH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
tAHT
tAS
Addresses
CE#
tAHT
tASO
tCEPH
tOEH
WE#
OE#
tOEPH
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6 / DQ2
RY/BY#
Valid Data
(first read)
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
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69
A d v a n c e I n f o r m a t i o n
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Erase
WE#
Erase
Erase Suspend
Read
Suspend
Program
Complete
DQ6
DQ2
Note:DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6
.
Figure 21. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Notes:
1. Not 100% tested.
VID
VID
RESET#
VIL or VIH
VIL or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 22. Temporary Sector Group Unprotect Timing Diagram
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S71GL064A based MCPs
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A d v a n c e I n f o r m a t i o n
V
V
ID
IH
RESET#
SA, A6,
A3, A2,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Group Protect or Unprotect
Verify
40h
Data
60h
60h
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note: For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.
Figure 23. Sector Group Protect and Unprotect Timing Diagram
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71
A d v a n c e I n f o r m a t i o n
AC Characteristics
Alternate CE# Controlled Erase and Program Operations-S29GL064A
Parameter
Speed Options
Unit
JEDEC
Std.
tWC
tAS
Description
Write Cycle Time (Note 1)
100
100
0
tAVAV
tAVWL
tELAX
tDVEH
tEHDX
tGHEL
tWLEL
tEHWH
tELEH
tEHEL
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
tAH
Address Hold Time
45
35
0
tDS
Data Setup Time
tDH
Data Hold Time
tGHEL
tWS
tWH
tCP
Read Recovery Time Before Write (OE# High to WE# Low)
WE# Setup Time
0
0
WE# Hold Time
0
CE# Pulse Width
35
25
240
60
54
0.5
50
4
tCPH
CE# Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
Program Valid before Status Polling (Note 5)
tWHWH1
tWHWH1
µs
tWHWH2
tWHWH2
tRH
sec
ns
tPOLL
µs
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming has resumed
(that is, the program resume command has been written). If the suspend command was issued after tPOLL, status data is available
immediately after programming has resumed. See Figure 24.
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A d v a n c e I n f o r m a t i o n
PBA for program
2AA for erase
SA for program buffer to flash
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tPOLL
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
PBD for program 29 for program buffer to flash
55 for erase
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Illustration shows device in word mode.
Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings
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A d v a n c e I n f o r m a t i o n
Erase And Programming Performance
Max
Typ (Note 1)
(Note 2)
Unit
Comments
Parameter
Sector Erase Time
0.5
3.5
Excludes 00h
programming
prior to erasure
(Note 6)
sec
Chip Erase Time
S29GL064A
64
128
Total Write Buffer Program Time (Notes 3, 5)
240
200
63
µs
µs
Excludes system
level overhead
(Note 7)
Total Accelerated Effective Write Buffer Program Time
(Notes 4, 5)
Chip Program Time
S29GL064A
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V, 10,000 cycles; checkerboard data pattern.
2. Under worst case conditions of 90°C; Worst case VCC, 100,000 cycles.
3. Effective programming time (typ) is 15 µs (per word), 7.5 µs (per byte).
4. Effective accelerated programming time (typ) is 12.5 µs (per word), 6.3 µs (per byte).
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Table 10 for further
information on command definitions.
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A d v a n c e I n f o r m a t i o n
pSRAM Type 1
4Mbit (256K Word x 16-bit)
8Mbit (512K Word x 16-bit)
16Mbit (1M Word x 16-bit)
32Mbit (2M Word x 16-bit)
64Mbit (4M Word x 16-bit)
Functional Description
Mode
CE#
CE2/ZZ#
OE#
L
WE# UB#
LB#
L
Addresses
I/O 1-8
Dout
I/O 9-16
Dout
Power
IACTIVE
Read (word)
L
L
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
L
X
X
X
X
X
X
X
X
X
Read (lower byte)
Read (upper byte)
Write (word)
L
L
Dout
High-Z
Dout
IACTIVE
L
L
H
L
High-Z
Din
IACTIVE
L
X
L
Din
IACTIVE
Write (lower byte)
Write (upper byte)
Outputs disabled
Standby
L
X
L
H
L
L
Din
Invalid
Din
IACTIVE
L
X
L
H
X
Invalid
High-Z
High-Z
High-Z
IACTIVE
L
H
X
H
X
X
X
X
X
High-Z
High-Z
High-Z
IACTIVE
H
H
X
ISTANDBY
IDEEP SLEEP
Deep power down
X
X
Absolute Maximum Ratings
Item
Voltage on any pin relative to VSS
Voltage on VCC relative to VSS
Power dissipation
Symbol
Vin, Vout
VCC
Ratings
Units
V
-0.2 to VCC +0.3
-0.2 to 3.6
1
V
PD
W
Storage temperature
TSTG
-55 to 150
-25 to 85
°C
°C
Operating temperature
TA
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A d v a n c e I n f o r m a t i o n
DC Characteristics
Table 13. 4Mb pSRAM Asynchronous
Asynchronous
Performance Grade
Density
-70
4Mb pSRAM
Max
Symbol
VCC
Parameter
Power Supply
Conditions
Min
2.7
Units
3.3
V
V
V
VIH
Input High Level
Input Low Level
0.8 Vccq
-0.3
VCC + 0.3
0.4
VIL
Input Leakage
Current
IIL
Vin = 0 to VCC
0.5
0.5
µA
µA
Output Leakage
Current
OE = VIH or
Chip Disabled
ILO
IOH = -1.0 mA
IOH = -0.2 mA
Output High
Voltage
VOH
0.8 Vccq
V
V
I
OH = -0.5 mA
OL = 2.0 mA
IOL = 0.2 mA
OL = 0.5 mA
I
Output Low
Voltage
VOL
0.2
I
Operating
Current
IACTIVE
VCC = 3.3 V
25
70
mA
µA
VCC = 3.0 V
VCC = 3.3 V
ISTANDBY Standby Current
IDEEP
SLEEP
Deep Power
x
x
x
µA
µA
µA
Down Current
1/4 Array PAR
Current
IPAR 1/4
1/2 Array PAR
Current
IPAR 1/2
Table 14. 8Mb pSRAM Asynchronous
Asynchronous
Version
B
C
-70
Performance Grade
Density
-55
8Mb pSRAM
Max
-70
8Mb pSRAM
Max
8Mb pSRAM
Max
Symbol
VCC
Parameter
Conditions
Min
2.7
Units
Min
2.7
Units
Min
Units
Power Supply
3.3
V
V
V
3.6
V
V
V
2.7
0.8
3.3
V
V
V
VIH
Input High Level
Input Low Level
2.2
VCC + 0.3
0.6
2.2
VCC + 0.3
0.6
VCC+0.3
0.4
VIL
-0.3
-0.3
-0.3
Input Leakage
Current
IIL
Vin = 0 to VCC
0.5
0.5
µA
µA
0.5
0.5
µA
µA
0.5
0.5
µA
µA
Output Leakage
Current
OE = VIH or
Chip Disabled
ILO
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S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Table 14. 8Mb pSRAM Asynchronous (Continued)
Asynchronous
Version
Performance Grade
Density
B
C
-70
-55
8Mb pSRAM
Max
-70
8Mb pSRAM
Max
8Mb pSRAM
Max
Symbol
Parameter
Conditions
IOH = -1.0 mA VCC-0.4
OH = -0.2 mA
Min
Units
Min
Units
Min
Units
VCC-0.4
VOH
Output High Voltage
Output Low Voltage
I
V
V
0.8 VCCQ
V
IOH = -0.5 mA
IOL = 2.0 mA
0.4
0.4
VOL
I
OL = 0.2 mA
V
V
0.2
V
IOL = 0.5 mA
VCC = 3.3 V
VCC = 3.0 V
IACTIVE Operating Current
ISTANDBY Standby Current
25
60
mA
µA
23
60
mA
µA
25
70
mA
µA
V
CC = 3.3 V
IDEEP
SLEEP
Deep Power Down
Current
x
x
x
µA
µA
µA
x
x
x
µA
µA
µA
x
x
x
µA
µA
µA
1/4 Array PAR
Current
IPAR 1/4
1/2 Array PAR
Current
IPAR 1/2
Table 15. 16Mb pSRAM Asynchronous
Asynchronous
Performance Grade
Density
-55
16Mb pSRAM
-70
16Mb pSRAM
Minimum Maximum Units
Symbol
Parameter
Conditions
Minimum Maximum
Units
V
VCC
VIH
VIL
IIL
Power Supply
2.7
2.2
3.6
VCC + 0.3
0.6
2.7
2.2
3.6
VCC + 0.3
0.6
V
V
Input High Level
Input Low Level
V
-0.3
V
-0.3
V
Input Leakage Current
Output Leakage Current
Vin = 0 to VCC
OE = VIH or Chip Disabled
IOH = -1.0 mA
0.5
µA
µA
0.5
µA
µA
ILO
0.5
0.5
VCC-0.4
VCC-0.4
VOH
Output High Voltage
Output Low Voltage
IOH = -0.2 mA
V
V
V
V
IOH = -0.5 mA
IOL = 2.0 mA
0.4
0.4
VOL
IOL = 0.2 mA
IOL = 0.5 mA
VCC = 3.3 V
IACTIVE
Operating Current
Standby Current
25
mA
µA
25
mA
µA
V
CC = 3.0 V
100
100
ISTANDBY
VCC = 3.3 V
IDEEP SLEEP Deep Power Down Current
IPAR 1/4 1/4 Array PAR Current
x
x
µA
µA
x
x
µA
µA
February 8, 2005 S71GL064A_00_A2
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77
A d v a n c e I n f o r m a t i o n
Table 15. 16Mb pSRAM Asynchronous (Continued)
Asynchronous
Performance Grade
Density
-55
16Mb pSRAM
Minimum Maximum
x
-70
16Mb pSRAM
Symbol
Parameter
Conditions
Units
Minimum Maximum Units
IPAR 1/2
1/2 Array PAR Current
µA
x
µA
Table 16. 16Mb pSRAM Page Mode
Page Mode
-65
Performance Grade
-60
16Mb pSRAM
Max
-70
16Mb pSRAM
Max
Density
16Mb pSRAM
Symbol
Parameter
Conditions
Min
Units
Min
Max
Units
Min
Units
VCC
Power Supply
2.7
3.3
V
2.7
3.3
V
2.7
3.3
V
Input High
Level
VIH
VIL
IIL
0.8 Vccq
-0.2
V
CC + 0.2
V
V
0.8 Vccq VCC + 0.2
V
V
0.8 Vccq
-0.2
VCC + 0.2
0.2 Vccq
1
V
V
Input Low
Level
0.2 Vccq
1
-0.2
0.2 Vccq
1
Input Leakage
Current
Vin = 0 to VCC
µA
µA
µA
Output
Leakage
Current
OE = VIH or
ILO
1
µA
V
1
µA
V
1
µA
V
Chip Disabled
IOH = -1.0 mA
IOH = -0.2 mA
Output High
Voltage
VOH
IOH = -0.5 mA 0.8 Vccq
IOL = 2.0 mA
0.8 Vccq
0.8 Vccq
Output Low
Voltage
VOL
IOL = 0.2 mA
V
V
V
IOL = 0.5 mA
0.2 Vccq
25
0.2 Vccq
25
0.2 Vccq
25
Operating
Current
IACTIVE
VCC = 3.3 V
mA
µA
mA
µA
mA
µA
V
CC = 3.0 V
Standby
Current
ISTANDBY
VCC = 3.3 V
100
10
100
10
100
10
IDEEP
SLEEP
Deep Power
µA
µA
µA
µA
µA
µA
µA
µA
µA
Down Current
1/4 Array PAR
Current
IPAR 1/4
65
80
65
80
65
80
1/2 Array PAR
Current
IPAR 1/2
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S71GL064A based MCPs
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A d v a n c e I n f o r m a t i o n
Table 17. 32Mb pSRAM Page Mode
Page Mode
Version
Performance Grade
Density
C
-65
E
-60
32Mb pSRAM
-65
32Mb pSRAM
Min Max Units
-70
32Mb pSRAM
32Mb pSRAM
Min Max Units
Symbol Parameter
Conditions
Min
Max
Units
Min
Max
Units
Power
VCC
VIH
VIL
IIL
2.7
1.4
3.6
V
V
2.7
0.8 Vccq
-0.2
3.3
V
V
2.7
0.8 Vccq
-0.2
3.3
V
V
2.7
3.3
V
V
Supply
VCC
+
0.2
Input High
Level
VCC
+
VCC
+ 0.2
VCC
+ 0.2
0.8
Vccq
0.2
Input Low
Level
0.2
Vccq
0.2
Vccq
0.2
Vccq
-0.2
0.4
0.5
V
V
V
-0.2
V
Input
Leakage
Current
Vin = 0 to VCC
µA
1
1
µA
1
1
µA
1
1
µA
Output
Leakage
Current
OE = VIH or
Chip Disabled
ILO
0.5
µA
V
µA
V
µA
V
µA
V
I
OH = -1.0 mA
0.8
Vccq
Output High IOH = -0.2 mA
Voltage
VOH
0.8
Vccq
I
OH = -0.5 mA
OL = 2.0 mA
IOL = 0.2 mA
OL = 0.5 mA
0.8 Vccq
0.8 Vccq
I
Output Low
Voltage
0.2
25
VOL
V
V
V
V
0.2
0.2
0.2
Vccq
I
Vccq
Vccq
Operating
Current
IACTIVE
VCC = 3.3 V
CC = 3.0 V
VCC = 3.3 V
mA
µA
25
mA
µA
25
mA
µA
25
mA
µA
V
Standby
Current
ISTANDBY
100
10
120
10
120
10
120
10
Deep Power
Down
Current
IDEEP
SLEEP
µA
µA
µA
µA
1/4 Array
IPAR 1/4
65
80
µA
µA
75
90
µA
µA
75
90
µA
µA
75
90
µA
µA
PAR Current
1/2 Array
PAR Current
IPAR 1/2
Table 18. 64Mb pSRAM Page Mode
Page Mode
-70
Performance Grade
Density
64Mb pSRAM
Max
Symbol
Parameter
Conditions
Min
2.7
Units
VCC
VIH
VIL
Power Supply
3.3
V
V
V
Input High Level
Input Low Level
0.8 Vccq
-0.2
VCC + 0.2
0.2 Vccq
February 8, 2005 S71GL064A_00_A2
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79
A d v a n c e I n f o r m a t i o n
Table 18. 64Mb pSRAM Page Mode (Continued)
Page Mode
Performance Grade
Density
-70
64Mb pSRAM
Max
Symbol
Parameter
Conditions
Min
Units
Input Leakage
Current
IIL
Vin = 0 to VCC
1
1
µA
Output Leakage
Current
OE = VIH or
Chip Disabled
ILO
µA
V
I
OH = -1.0 mA
IOH = -0.2 mA
OH = -0.5 mA
Output High
Voltage
VOH
I
0.8 Vccq
IOL = 2.0 mA
IOL = 0.2 mA
Output Low
Voltage
VOL
V
I
OL = 0.5 mA
CC = 3.3 V
VCC = 3.0 V
CC = 3.3 V
0.2 Vccq
25
Operating
Current
IACTIVE
V
mA
µA
ISTANDBY Standby Current
V
120
10
IDEEP
SLEEP
Deep Power
µA
µA
µA
Down Current
1/4 Array PAR
Current
IPAR 1/4
65
80
1/2 Array PAR
Current
IPAR 1/2
Timing Test Conditions
Item
Input Pulse Level
0.1 VCC to 0.9 VCC
5ns
Input Rise and Fall Time
Input and Output Timing Reference Levels
Operating Temperature
0.5 VCC
-25°C to +85°C
80
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Output Load Circuit
VCC
14.5K
30 pF
I/O
14.5K
Output Load
Figure 25. Output Load Circuit
Power Up Sequence
After applying power, maintain a stable power supply for a minimum of 200 µs
after CE# > VIH.
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
81
A d v a n c e I n f o r m a t i o n
AC Characteristics
Table 19. 4Mb pSRAM Page Mode
Asynchronous
Performance Grade
Density
-70
4Mb pSRAM
Max
3 Volt
Symbol
Parameter
Min
Units
trc
Read cycle time
70
ns
Address Access
Time
taa
70
70
20
70
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to
output
tco
toe
tba
tlz
Output enable to
valid output
UB#, LB# Access
time
Chip select to
Low-z output
10
10
5
UB#, LB# Enable
to Low-Z output
tblz
tolz
thz
Output enable to
Low-Z output
Chip enable to
High-Z output
0
20
20
20
UB#, LB#
disable to High-Z
output
tbhz
0
ns
Output disable to
High-Z output
tohz
toh
0
ns
ns
Output hold from
Address Change
10
82
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Table 19. 4Mb pSRAM Page Mode (Continued)
Asynchronous
Performance Grade
Density
-70
4Mb pSRAM
Max
3 Volt
Symbol
Parameter
Min
Units
twc
tcw
Write cycle time
70
ns
Chipselect to end
of write
70
0
ns
ns
ns
Address set up
Time
tas
Address valid to
end of write
taw
70
UB#, LB# valid
to end of write
tbw
twp
twr
70
55
0
ns
ns
ns
Write pulse width
Write recovery
time
Write to output
High-Z
twhz
tdw
tdh
20
ns
ns
ns
Data to write
time overlap
25
0
Data hold from
write time
End write to
tow
tow
5
output Low-Z
Write high pulse
width
7.5
ns
tpc
tpa
Page read cycle
x
Page address
access time
x
twpc
tcp
Page write cycle
x
x
Chip select high
pulse width
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
83
A d v a n c e I n f o r m a t i o n
Table 20. 8Mb pSRAM Asynchronous
Asynchronous
Version
B
C
-70
Performance Grade
Density
-55
8Mb pSRAM
Max
-70
8Mb pSRAM
Max
8Mb pSRAM
Max
3 Volt
Symbol
Parameter
Min
Units
Min
Units
Min
Units
trc
Read cycle time
55
ns
70
ns
70
ns
Address Access
Time
taa
55
55
30
55
ns
ns
ns
ns
ns
ns
ns
ns
70
70
35
70
ns
ns
ns
ns
ns
ns
ns
ns
70
70
20
70
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to
output
tco
toe
tba
tlz
Output enable to
valid output
UB#, LB# Access
time
Chip select to
Low-z output
5
5
5
0
5
5
5
0
10
10
5
UB#, LB# Enable
to Low-Z output
tblz
tolz
thz
Output enable to
Low-Z output
Chip enable to
High-Z output
20
20
20
25
25
25
0
20
20
20
UB#, LB#
disable to High-Z
output
tbhz
0
ns
0
ns
0
ns
Output disable to
High-Z output
tohz
toh
0
ns
ns
0
ns
ns
0
ns
ns
Output hold from
Address Change
10
10
10
84
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Table 20. 8Mb pSRAM Asynchronous (Continued)
Asynchronous
Version
Performance Grade
Density
B
C
-70
-55
8Mb pSRAM
Max
-70
8Mb pSRAM
Max
8Mb pSRAM
Max
3 Volt
Symbol
Parameter
Min
Units
Min
Units
Min
Units
twc
tcw
Write cycle time
55
ns
70
ns
70
ns
Chip select to
end of write
45
0
ns
ns
ns
55
0
ns
ns
ns
70
0
ns
ns
ns
Address set up
Time
tas
Address valid to
end of write
taw
45
55
70
UB#, LB# valid
to end of write
tbw
twp
twr
45
45
0
ns
ns
ns
55
55
0
ns
ns
ns
70
55
0
ns
ns
ns
Write pulse width
Write recovery
time
Write to output
High-Z
twhz
tdw
tdh
25
ns
ns
ns
25
20
ns
ns
ns
Data to write
time overlap
40
0
40
0
ns
ns
25
0
Data hold from
write time
End write to
tow
tow
5
5
5
output Low-Z
Write high pulse
width
x
x
x
ns
x
x
x
ns
x
x
x
ns
tpc
tpa
Page read cycle
x
x
x
Page address
access time
twpc
tcp
Page write cycle
x
x
x
x
x
x
Chip select high
pulse width
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
85
A d v a n c e I n f o r m a t i o n
Figure 26. 16Mb pSRAM Asynchronous
Asynchronous
Performance Grade
Density
-55
-70
16Mb pSRAM
16Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Min
Max
Units
trc
Read cycle time
55
ns
ns
70
ns
ns
Address Access
Time
taa
55
55
30
55
70
70
35
70
Chip select to
output
tco
toe
tba
tlz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output enable to
valid output
UB#, LB# Access
time
Chip select to
Low-z output
5
5
5
0
5
5
5
0
UB#, LB# Enable
to Low-Z output
tblz
tolz
thz
Output enable to
Low-Z output
Chip enable to
High-Z output
25
25
25
25
25
25
UB#, LB#
disable to High-Z
output
tbhz
0
ns
0
ns
Output disable to
High-Z output
tohz
toh
0
ns
ns
0
ns
ns
Output hold from
Address Change
10
10
twc
tcw
Write cycle time
55
50
ns
ns
70
55
ns
ns
Chipselect to end
of write
Address set up
Time
tas
0
ns
ns
0
ns
ns
Address valid to
end of write
taw
50
55
UB#, LB# valid
to end of write
tbw
twp
twr
50
50
0
ns
ns
ns
55
55
0
ns
ns
ns
Write pulse width
Write recovery
time
Write to output
High-Z
twhz
tdw
tdh
25
ns
ns
ns
25
ns
ns
ns
Data to write
time overlap
25
0
25
0
Data hold from
write time
End write to
tow
tow
5
5
output Low-Z
Write high pulse
width
x
x
ns
x
x
ns
86
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Figure 26. 16Mb pSRAM Asynchronous (Continued)
Asynchronous
Performance Grade
Density
-55
-70
16Mb pSRAM
16Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Min
Max
Units
tpc
tpa
Page read cycle
x
x
Page address
access time
x
x
twpc
tcp
Page write cycle
x
x
x
x
Chip select high
pulse width
Table 21. 16Mb pSRAM Page Mode
Page Mode
-65
16Mb pSRAM
Performance Grade
Density
-60
-70
16Mb pSRAM
16Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Min
Max
Units
Min
Max
Units
trc
Read cycle time
60
20k
ns
ns
65
20k
ns
ns
70
20k
ns
ns
Address Access
Time
taa
60
60
25
60
65
65
25
65
70
70
25
70
Chip select to
output
tco
toe
tba
tlz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output enable to
valid output
UB#, LB# Access
time
Chip select to
Low-z output
10
10
5
10
10
5
10
10
5
UB#, LB# Enable
to Low-Z output
tblz
tolz
thz
Output enable to
Low-Z output
Chip enable to
High-Z output
0
5
5
5
0
5
5
5
0
5
5
5
UB#, LB#
disable to High-Z
output
tbhz
0
ns
0
ns
0
ns
Output disable to
High-Z output
tohz
toh
0
5
ns
ns
0
5
ns
ns
0
5
ns
ns
Output hold from
Address Change
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
87
A d v a n c e I n f o r m a t i o n
Table 21. 16Mb pSRAM Page Mode (Continued)
Page Mode
Performance Grade
Density
-60
-65
-70
16Mb pSRAM
16Mb pSRAM
16Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Min
Max
Units
Min
Max
Units
twc
tcw
Write cycle time
60
20k
ns
ns
65
20k
ns
ns
70
20k
ns
ns
Chipselect to end
of write
50
0
60
0
60
0
Address set up
Time
tas
ns
ns
ns
ns
ns
ns
Address valid to
end of write
taw
50
60
60
UB#, LB# valid
to end of write
tbw
twp
twr
50
50
0
ns
ns
ns
60
50
0
ns
ns
ns
60
50
0
ns
ns
ns
Write pulse width
Write recovery
time
Write to output
High-Z
twhz
tdw
tdh
5
ns
ns
ns
5
ns
ns
ns
5
ns
ns
ns
Data to write
time overlap
20
0
20
0
20
0
Data hold from
write time
End write to
tow
tow
5
5
5
output Low-Z
Write high pulse
width
7.5
ns
7.5
ns
7.5
ns
tpc
tpa
Page read cycle
25
20k
25
ns
ns
ns
ns
25
20k
25
ns
ns
ns
ns
25
20k
25
ns
ns
ns
ns
Page address
access time
twpc
tcp
Page write cycle
25
10
20k
25
10
20k
25
10
20k
Chip select high
pulse width
88
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Table 22. 32Mb pSRAM Page Mode
Page Mode
Version
Performance Grade
Density
C
-65
E
-60
-65
-70
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max Units
Min
Max Units
Min
Max Units
Min
Max Units
trc
Read cycle time
65
20k
65
ns
ns
60
20k
60
ns
ns
65
20k
65
ns
ns
70
20k
70
ns
ns
Address Access
Time
taa
Chip select to
output
tco
toe
tba
tlz
65
20
65
ns
ns
ns
ns
ns
ns
ns
60
25
60
ns
ns
ns
ns
ns
ns
ns
65
25
65
ns
ns
ns
ns
ns
ns
ns
70
25
70
ns
ns
ns
ns
ns
ns
ns
Output enable to
valid output
UB#, LB# Access
time
Chip select to
Low-z output
10
10
5
10
10
5
10
10
5
10
10
5
UB#, LB# Enable
to Low-Z output
tblz
tolz
thz
Output enable to
Low-Z output
Chip enable to
High-Z output
0
20
20
20
0
5
5
5
0
5
5
5
0
5
5
5
UB#, LB#
disable to High-Z
output
tbhz
0
ns
0
ns
0
ns
0
ns
Output disable to
High-Z output
tohz
toh
0
5
ns
ns
0
5
ns
ns
0
5
ns
ns
0
5
ns
ns
Output hold from
Address Change
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
89
A d v a n c e I n f o r m a t i o n
Table 22. 32Mb pSRAM Page Mode (Continued)
Page Mode
Version
Performance Grade
Density
C
-65
E
-60
-65
-70
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max Units
Min
Max Units
Min
Max Units
Min
Max Units
twc
tcw
Write cycle time
65
55
20k
ns
ns
60
50
20k
ns
ns
65
60
20k
ns
ns
70
60
20k
ns
ns
Chipselect to end
of write
Address set up
Time
tas
0
ns
ns
0
ns
ns
0
ns
ns
0
ns
ns
Address valid to
end of write
taw
55
50
60
60
UB#, LB# valid
to end of write
tbw
twp
twr
55
55
0
ns
ns
ns
50
50
0
ns
ns
ns
60
50
0
ns
ns
ns
60
50
0
ns
ns
ns
Write pulse width
20k
5
Write recovery
time
Write to output
High-Z
twhz
tdw
tdh
ns
ns
ns
5
ns
ns
ns
5
ns
ns
ns
5
ns
ns
ns
Data to write
time overlap
25
0
20
0
20
0
20
0
Data hold from
write time
End write to
tow
tow
5
5
5
5
output Low-Z
Write high pulse
width
7.5
ns
7.5
ns
7.5
ns
7.5
ns
tpc
tpa
Page read cycle
25
20k
25
ns
ns
ns
ns
25
20k
25
ns
ns
ns
ns
25
20k
25
ns
ns
ns
ns
25
20k
25
ns
ns
ns
ns
Page address
access time
twpc
tcp
Page write cycle
25
10
20k
25
10
20k
25
10
20k
25
10
20k
Chip select high
pulse width
90
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Table 23. 64Mb pSRAM Page Mode
Page Mode
Performance Grade
Density
-70
64Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
trc
Read cycle time
70
20k
ns
ns
Address Access
Time
taa
70
70
25
70
Chip select to
output
tco
toe
tba
tlz
ns
ns
ns
ns
ns
ns
ns
Output enable to
valid output
UB#, LB# Access
time
Chip select to
Low-z output
10
10
5
UB#, LB# Enable
to Low-Z output
tblz
tolz
thz
Output enable to
Low-Z output
Chip enable to
High-Z output
0
5
5
5
UB#, LB#
disable to High-Z
output
tbhz
0
ns
Output disable to
High-Z output
tohz
toh
0
5
ns
ns
Output hold from
Address Change
twc
tcw
Write cycle time
70
60
20k
ns
ns
Chipselect to end
of write
Address set up
Time
tas
0
ns
ns
Address valid to
end of write
taw
60
UB#, LB# valid
to end of write
tbw
twp
twr
60
50
0
ns
ns
ns
Write pulse width
20k
5
Write recovery
time
Write to output
High-Z
twhz
tdw
tdh
ns
ns
ns
Data to write
time overlap
20
0
Data hold from
write time
End write to
tow
tow
5
output Low-Z
Write high pulse
width
7.5
ns
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
91
A d v a n c e I n f o r m a t i o n
Table 23. 64Mb pSRAM Page Mode (Continued)
Page Mode
Performance Grade
Density
-70
64Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
tpc
tpa
Page read cycle
20
20k
20
ns
ns
ns
ns
Page address
access time
twpc
tcp
Page write cycle
20
10
20k
Chip select high
pulse width
Timing Diagrams
Read Cycle
tRC
Address
tAA
tOH
Previous Data Valid
Data Valid
Data Out
Figure 27. Timing of Read Cycle (CE# = OE# = VIL, WE# = ZZ# = VIH
)
92
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
tRC
Address
tAA
CE#
tCO
tLZ
tHZ
tOE
OE#
tOLZ
tOHZ
tLB, UB
t
LB#, UB#
Data Out
tBHZ
Data Valid
tBLZ
High-Z
Figure 28. Timing Waveform of Read Cycle (WE# = ZZ# = VIH
)
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
93
A d v a n c e I n f o r m a t i o n
tPGMAX
Page Address (A4 - A20)
tRC
tPC
Word Address (A0 - A3)
tAA
tPA
tHZ
CE#
tCO
tOE
tOHZ
OE#
tOLZ
tBHZ
tLB, UB
t
LB#, UB#
tBLZ,
High-Z
Data Out
Figure 29. Timing Waveform of Page Mode Read Cycle (WE# = ZZ# = VIH
)
94
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Write Cycle
tWC
Address
tWR
tAW
CE#
tCW
tBW
LB#, UB#
tAS
tWP
WE#
tDW
tDH
High-Z
Data Valid
Data In
Data Out
tWHZ
tOW
High-Z
Figure 30. Timing Waveform of Write Cycle (WE# Control, ZZ# = VIH
)
tWC
Address
CE#
tAW
tWR
tCW
tAS
tBW
LB#, UB#
WE#
tWP
tDW
tDH
Data Valid
Data In
tWHZ
High-Z
Figure 31. Timing Waveform of Write Cycle (CE# Control, ZZ# = VIH
February 8, 2005 S71GL064A_00_A2 S71GL064A based MCPs
Data Out
)
95
A d v a n c e I n f o r m a t i o n
tPGMAX
Page Address
(A4 - A20)
tWC
tPWC
Wor d Address
(A0 - A3 )
tAS
tCW
CE#
tWP
WE#
tLBW, UBW
t
LB#, UB#
tDW
tDH tPDW tPDH
tPDW tPDH
High-Z
Data Out
Figure 32. Timing Waveform of Page Mode Write Cycle (ZZ# = VIH
)
Power Savings Modes
(For 16M Page Mode, 32M and 64M Only)
There are several power savings modes.
Partial Array Self Refresh
Temperature Compensated Refresh (64M)
Deep Sleep Mode
Reduced Memory Size (32M, 16M)
The operation of the power saving modes ins controlled by the settings of bits
contained in the Mode Register. This definition of the Mode Register is shown in
Figure 33 and the various bits are used to enable and disable the various low
power modes as well as enabling Page Mode operation. The Mode Register is set
by using the timings defined in Figure 34.
Partial Array Self Refresh (PAR)
In this mode of operation, the internal refresh operation can be restricted to a
16Mb, 32Mb, or 48Mb portion of the array. The array partition to be refreshed is
determined by the respective bit settings in the Mode Register. The register set-
96
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
tings for the PASR operation are defined in Table 25. In this PASR mode, when
ZZ# is active low, only the portion of the array that is set in the register is re-
freshed. The data in the remainder of the array will be lost. The PASR operation
mode is only available during standby time (ZZ# low) and once ZZ# is returned
high, the device resumes full array refresh. All future PASR cycles will use the
contents of the Mode Register that has been previously set. To change the ad-
dress space of the PASR mode, the Mode Register must be reset using the
previously defined procedures. For PASR to be activated, the register bit, A4 must
be set to a one (1) value, “PASR Enabled”. If this is the case, PASR will be acti-
vated 10 µs after ZZ# is brought low. If the A4 register bit is set equal to zero
(0), PASR will not be activated.
Temperature Compensated Refresh (for 64Mb)
In this mode of operation, the internal refresh rate can be optimized for the op-
eration temperature used and this can then lower standby current. The DRAM
array in the PSRAM must be refreshed internally on a regular basis. At higher
temperatures, the DRAM cell must be refreshed more often than at lower tem-
peratures. By setting the temperature of operation in the Mode Register, this
refresh rate can be optimized to yield the lowest standby current at the given op-
erating temperature. There are four different temperature settings that can be
programmed in to the pSRAM. These are defined in Figure 33.
Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity
of the array is lost. Deep Sleep is entered by bringing ZZ# low with the A4 reg-
ister bit set to a zero (0), “Deep Sleep Enabled”. If this is the case, Deep Sleep
will be entered 10 µs after ZZ# is brought low. The device will remain in this mode
as long as ZZ# remains low. If the A4 register bit is set equal to one (1), Deep
Sleep will not be activated.
Reduced Memory Size (for 32M and 16M)
In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb
device. The mode and array size are determined by the settings in the VA register.
The VA register is set according to the following timings and the bit settings in
the table “Address Patterns for RMS”. The RMS mode is enabled at the time of
ZZ transitioning high and the mode remains active until the register is updated.
To return to the full 32Mb address space, the VA register must be reset using the
previously defined procedures. While operating in the RMS mode, the unselected
portion of the array may not be used.
Other Mode Register Settings (for 64M)
The Page Mode operation can also be enabled and disabled using the Mode Reg-
ister. Register bit A7 controls the operation of Page Mode and setting this bit to a
one (1), enables Page Mode. If the register bit A7 is set to a zero (0), Page Mode
operation is disabled.
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
97
A d v a n c e I n f o r m a t i o n
64 Mb
32 Mb / 16 Mb
A21 - A8
A7
A6
A5
A4
A3
A2
A1
A0
Array Mode
for ZZ#
Reserved
Must set to all 0
Temp
Compensated
Refresh
0 = PAR (default)
1 = RMS
PAR Section
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1 = Top 1/4 array
0 = Top 1/2 array
1 = Top 3/4 array
0 = No PAR
1 = Bottom 1/4 array
0 = Bottom 1/2 array
1 = Bottom 3/4 array
0 = Full array (default)
1
0
0
1
0 = 15oC
1 = 45oC
0 = 70oC
1 = 85oC (default)
Page Mode
0 = Page Mode Disabled (default)
1 = Page Mode Enabled
Deep Sleep Enable/Disable
0 = Deep Sleep Enabled
1 = Deep Sleep Disabled (default)
Figure 33. Mode Register
t
WC
Address
t
AW
t
AS
t
WR
CE#
t
WP
WE#
ZZ#
t
ZZWE
t
CDZZ
Figure 34. Mode Register UpdateTimings (UB#, LB#, OE# are Don’t Care)
98
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
t
ZZMIN
ZZ#
CE#
t
t
R
CDZZ
Figure 35. Deep Sleep Mode - Entry/Exit Timings (for 64M)
t
WC
A4
t
t
AS
AW
CE#
t
WR
t
WP
WE#
t
t
BW
LB#, UB#
R
t
ZZWE
t
ZZMIN
ZZ#
Figure 36. Deep Sleep Mode - Entry/Exit Timings (for 32M and 16M)
Table 24. Mode Register Update and Deep Sleep Timings
Item
Symbol
tCDZZ
tZZWE
tWC
Min
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Note
Chip deselect to ZZ# low
ZZ# low to WE# low
Write register cycle time
Chip enable to end of write
Address valid to end of write
Write recovery time
10
500
70/85
70/85
70/85
0
1
1
1
tCW
tAW
tWR
Address setup time
tAS
0
Write pulse width
tWR
40
Deep Sleep Pulse Width
Deep Sleep Recovery
tZZMIN
tR
10
200
Notes:
1. Minimum cycle time for writing register is equal to speed grade of product.
Table 25. Address Patterns for PASR (A4=1) (64M)
A2 A1 A0
Active Section
Top quarter of die
Top half of die
Reserved
Address Space
300000h-3FFFFFh
200000h-3FFFFFh
Size
Density
16Mb
32Mb
1
1
1
1
1
0
1
0
1
1Mb x 16
2Mb x 16
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
99
A d v a n c e I n f o r m a t i o n
Table 25. Address Patterns for PASR (A4=1) (64M) (Continued)
A2 A1 A0
Active Section
No PASR
Address Space
None
Size
0
Density
0
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
Bottom quarter of die
Bottom half of die
Reserved
000000h-0FFFFFh
000000h-1FFFFFh
1Mb x 16
2Mb x 16
16Mb
32Mb
Full array
000000h-3FFFFFh
4Mb x 16
64Mb
ICC Characteristics
Table 26. Deep ICC Characteristics (for 64Mb)
Item
Symbol
Te st
Array Partition Typ Max Unit
None
10
60
1/4 Array
1/2 Array
Full Array
PASR Mode Standby Current
IPASR
VIN = VCC or 0V, Chip Disabled, tA = 85°C
µA
80
120
Item
Symbol
Max Temperature
15°C
Typ
Max
50
Unit
45°C
60
Temperature Compensated Refresh Current
ITCR
µA
70°C
80
85°C
120
Item
Symbol
Test
Typ
Max
10
Unit
Deep Sleep Current
IZZ
VIN = VCC or 0V, Chip in ZZ# mode, tA = 25°C
µA
Table 27. Address Patterns for PAR (A3= 0, A4=1) (32M)
A2 A1 A0
Active Section
One-quarter of die
Address Space
000000h - 07FFFFh
Size
Density
8Mb
0
0
x
1
1
1
1
0
1
1
1
0
0
1
0
512Kb x 16
1Mb x 16
2Mb x 16
512Kb x 16
1Mb x 16
One-half of die
Full die
000000h - 0FFFFFh
000000h - 1FFFFFh
180000h - 1FFFFFh
100000h - 1FFFFFh
16Mb
32Mb
8Mb
One-quarter of die
One-half of die
16Mb
Table 28. Address Patterns for RMS (A3 = 1, A4 = 1) (32M)
A2 A1 A0
Active Section
One-quarter of die
One-half of die
Address Space
000000h - 07FFFFh
Size
Density
8Mb
0
0
1
1
1
0
512Kb x 16
1Mb x 16
000000h - 0FFFFFh
16Mb
100
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Table 28. Address Patterns for RMS (A3 = 1, A4 = 1) (32M) (Continued)
A2 A1 A0
Active Section
One-quarter of die
One-half of die
Address Space
180000h - 1FFFFFh
Size
Density
8Mb
1
1
1
1
1
0
512Kb x 16
1Mb x 16
100000h - 1FFFFFh
16Mb
Table 29. Low Power ICC Characteristics (32M)
Item
Symbol
Te s t
Array Partition
Typ
Max
Unit
µA
1/4 Array
75
90
75
90
VIN = VCC or 0V,
Chip Disabled, tA= 85oC
PAR Mode Standby Current IPAR
RMS Mode Standby Current IRMSSB
1/2 Array
µA
8Mb Device
16Mb Device
µA
VIN = VCC or 0V,
Chip Disabled, tA= 85oC
µA
VIN = VCC or 0V,
Chip in ZZ mode, tA= 85oC
Deep Sleep Current
IZZ
10
µA
Table 30. Address Patterns for PAR (A3= 0, A4=1) (16M)
A2 A1 A0
Active Section
One-quarter of die
Address Space
00000h - 0FFFFh
Size
Density
4Mb
0
0
x
1
1
1
1
0
1
1
1
0
0
1
0
256Kb x 16
512Kb x 16
1Mb x 16
One-half of die
Full die
00000h - 7FFFFh
00000h - FFFFFh
C0000h - FFFFh
80000h - 1FFFFFh
8Mb
16Mb
4Mb
One-quarter of die
One-half of die
256Kb x 16
512Kb x 16
8Mb
Table 31. Address Patterns for RMS (A3 = 1, A4 = 1) (16M)
A2 A1 A0
Active Section
One-quarter of die
Address Space
00000h - 0FFFFh
Size
Density
4Mb
0
0
1
1
1
1
1
1
1
0
1
0
256Kb x 16
512Kb x 16
256Kb x 16
512Kb x 16
One-half of die
One-quarter of die
One-half of die
00000h - 7FFFFh
C0000h - FFFFFh
80000h - FFFFFh
8Mb
4Mb
8Mb
Table 32. Low Power ICC Characteristics (16M)
Item
Symbol
Test
Array Partition
1/4 Array
Typ
Max
Unit
65
80
65
80
VIN = VCC or 0V,
Chip Disabled, tA= 85oC
PAR Mode Standby Current
IPAR
µA
1/2 Array
4Mb Device
8Mb Device
VIN = VCC or 0V,
Chip Disabled, tA= 85oC
RMS Mode Standby Current
Deep Sleep Current
IRMSSB
µA
µA
VIN = VCC or 0V,
Chip in ZZ# mode, tA= 85oC
IZZ
10
February 8, 2005 S71GL064A_00_A2
S71GL064A based MCPs
101
A d v a n c e I n f o r m a t i o n
pSRAM Type 7
16Mb (1M word x 16-bit)
32Mb (2M word x 16-bit)
64Mb (4M word x 16-bit)
CMOS 1M/2M/4M-Word x 16-bit Fast Cycle Random Access Memory with Low
Power SRAM Interface
Features
Asynchronous SRAM Interface
Fast Access Time
— tCE = tAA = 60ns max (16M)
— tCE = tAA = 65ns max (32M/64M)
8 words Page Access Capability
— tPAA = 20ns max (32M/64M)
Low Voltage Operating Condition
— VDD = +2.7V to +3.1V
Wide Operating Temperature
— TA = -30°C to +85°C
Byte Control by LB and UB
Various Power Down modes
— Sleep (16M)
— Sleep, 4M-bit Partial, or 8M-bit Partial (32M)
— Sleep, 8M-bit Partial, or 16M-bit Partial (64M)
Pin Description
Pin Name
A21 to A0
CE1#
CE2#
WE#
Description
Address Input: A19 to A0 for 16M, A20 to A0 for 32M, A21 to A0 for 64M
Chip Enable (Low Active)
Chip Enable (High Active)
Write Enable (Low Active)
OE#
Output Enable (Low Active)
UB#
Upper Byte Control (Low Active)
Lower Byte Control (Low Active)
Upper Byte Data Input/Output
Lower Byte Data Input/Output
Power Supply
LB#
DQ16 9
-
DQ8-1
VDD
VSS
Ground
102
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e i n f o r m a t i o n
Functional Description
Mode
Standby (Deselect)
Output Disable (Note 1)
Output Disable (No Read)
Read (Upper Byte)
Read (Lower Byte)
Read (Word)
CE2#
CE1#
WE#
OE#
X
LB#
X
UB#
X
A21-0
X
DQ8-1
High-Z
DQ16-9
High-Z
H
H
X
H
H
X
X
Note 3
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
X
High-Z
High-Z
H
H
L
H
L
High-Z
High-Z
High-Z
Output Valid
High-Z
H
L
H
L
Output Valid
Output Valid
Invalid
H
L
L
Output Valid
Invalid
No Write
H
H
L
H
L
Write (Upper Byte)
Write (Lower Byte)
Write (Word)
Invalid
Input Valid
Invalid
L
H
X
H
L
Input Valid
Input Valid
High-Z
L
Input Valid
High-Z
Power Down
L
X
X
X
X
Legend:L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance.
Notes:
1. Should not be kept this logic condition longer than 1 ms. Please contact local Spansion representative for the relaxation of
1ms limitation.
2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the
selection of the Power-Down Program, 16M has data retention in all modes except Power Down. Refer to Power Down for
details.
3. Can be either VIL or VIH but must be valid before Read or Write.
Power Down (for 32M, 64M Only)
Power Down
The Power Down is a low-power idle state controlled by CE2. CE2 Low drives the
device in power-down mode and maintains the low-power idle state as long as
CE2 is kept Low. CE2 High resumes the device from power-down mode. These
devices have three power-down modes. These can be programmed by series of
read/write operation. Each mode has following features.
32M
Retention Data
No
64M
Retention Data
No
Mode
Retention Address
N/A
Mode
Retention Address
N/A
Sleep (default)
4M Partial
Sleep (default)
8M Partial
4M bit
00000h to 3FFFFh
00000h to 7FFFFh
8M bit
00000h to 7FFFFh
00000h to FFFFFh
8M Partial
8M bit
16M Partial
16M bit
The default state is Sleep and it is the lowest power consumption but all data is
lost once CE2 is brought to Low for Power Down. It is not required to program to
Sleep mode after power-up.
February 8, 2005 S71GL064A_00_A2
pSRAM Type 7
103
A d v a n c e I n f o r m a t i o n
Power Down Program Sequence
The program requires 6 read/write operations with a unique address. Between
each read/write operation requires that device be in standby mode. The following
table shows the detail sequence.
Cycle #
1st
Operation
Read
Address
3FFFFFh (MSB)
3FFFFFh
Data
Read Data (RDa)
RDa
2nd
3rd
Write
Write
Write
Write
Read
3FFFFFh
RDa
4th
3FFFFFh
Don’t Care (X)
X
5th
3FFFFFh
6th
Address Key
Read Data (RDb)
The first cycle reads from the most significant address (MSB).
The second and third cycle are to write back the data (RDa) read by first cycle.
If the second or third cycle is written into the different address, the program is
cancelled, and the data written by the second or third cycle is valid as a normal
write operation.
The fourth and fifth cycles write to MSB. The data from the fourth and fifth cycles
is “don’t care.” If the fourth or fifth cycles are written into different address, the
program is also cancelled but write data might not be written as normal write
operation.
The last cycle is to read from specific address key for mode selection.
Once this program sequence is performed from a Partial mode to the other Partial
mode, the written data stored in memory cell array can be lost. So, it should per-
form this program prior to regular read/write operation if Partial mode is used.
Address Key
The address key has following format.
Mode
Address
32M
Sleep (default)
4M Partial
8M Partial
N/A
64M
Sleep (default)
N/A
A21
1
A20
1
A19
1
A18 - A0
Binary
1
1
1
1
3FFFFFh
37FFFFh
2FFFFFh
27FFFFh
1
1
0
8M Partial
16M Partial
1
0
1
1
0
0
104
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e i n f o r m a t i o n
Absolute Maximum Ratings
Item
Symbol
VDD
Value
Unit
V
Voltage of VDD Supply Relative to VSS
Voltage at Any Pin Relative to VSS
Short Circuit Output Current
Storage temperature
-0.5 to +3.6
-0.5 to +3.6
±50
VIN, VOUT
IOUT
V
mA
°C
TSTG
-55 to +125
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
(See Warning Below)
Parameter
Symbol
VDD
VSS
VIH
Min
2.7
Max
3.1
Unit
V
Supply Voltage
0
0
V
High Level Input Voltage (Note 1)
High Level Input Voltage (Note 1)
Ambient Temperature
VDD 0.8
-0.3
-30
VDD+0.2
VDD 0.2
85
V
VIL
V
TA
°C
Notes:
1. Maximum DC voltage on input and I/O pins is VDD+0.2V. During voltage transitions, inputs can positive overshoot to
DD+1.0V for periods of up to 5 ns.
V
2. Minimum DC voltage on input or I/O pins is -0.3V. During voltage transitions, inputs can negative overshoot VSS to -1.0V for
periods of up to 5ns.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the de-
vice’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges can
adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their FUJITSU representative before-
hand.
Package Capacitance
Test conditions: TA = 25°C, f = 1.0 MHz
Symbol
Description
Test Setup
VIN = 0V
VIN = 0V
VIO = 0V
Typ
—
Max
5
Unit
pF
CIN1
CIN2
CIO
Address Input Capacitance
Control Input Capacitance
Data Input/Output Capacitance
—
5
pF
—
8
pF
February 8, 2005 S71GL064A_00_A2
pSRAM Type 7
105
A d v a n c e I n f o r m a t i o n
DC Characteristics
(Under Recommended Conditions Unless Otherwise Noted)
16M
32M
64M
Parameter
Symbol
Test Conditions
VIN = VSS to VDD
Min. Max. Min. Max. Min. Max. Unit
Input Leakage
Current
ILI
-1.0 +1.0 -1.0 +1.0 -1.0 +1.0
-1.0 +1.0 -1.0 +1.0 -1.0 +1.0
µ
A
A
Output Leakage
Current
ILO
VOH
VOL
VOUT = VSS to VDD, Output Disable
VDD = VDD(min), IOH = –0.5mA
IOL = 1mA
µ
Output High
Voltage Level
2.2
—
—
2.4
—
—
2.4
—
V
Output Low
Voltage Level
0.4
10
0.4
—
—
0.4
10
V
IDDPS
IDDP4
IDDP8
IDDP16
SLEEP
—
—
—
10
40
50
µ
A
A
A
A
VDD = VDD max.,
VIN = VIH or VIL,
4M Partial
8M Partial
16M Partial
N/A
N/A
µ
µ
µ
VDD Power
Down Current
N/A
N/A
—
—
80
CE2
≤ 0.2 V
N/A
100
VDD = VDD max.,
VIN = VIH or VIL
CE1 = CE2 = VIH
IDDS
—
—
1
—
—
1.5
80
—
—
1.5
mA
VDD Standby
Current
VDD = VDD max.,
170
90
µ
A
A
TA< +85°C
TA< +40°C
IDDS1
VIN
CE1 = CE2
≤
0.2V or VIN
≥
VDD – 0.2V,
100
µ
≥
VDD – 0.2V
VDD = VDD max.,
VIN = VIH or VIL,
CE1 = VIL and CE2= VIH,
IOUT=0mA
IDDA1
IDDA2
tRC / tWC = min.
—
—
20
3
—
—
30
3
—
—
40
mA
mA
VDD
Active Current
tRC / tWC = 1
µs
5
VDD = VDD max., VIN = VIH or VIL,
CE1 = VIL and CE2= VIH,
IOUT=0mA, tPRC = min.
VDD Page
Read Current
IDDA3
N/A
—
10
—
10
mA
Notes:
1. All voltages are referenced to VSS
.
2. DC Characteristics are measured after following POWER-UP timing.
3. IOUT depends on the output load conditions.
106
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e i n f o r m a t i o n
AC Characteristics
(Under Recommended Operating Conditions Unless Otherwise Noted)
Read Operation
16M
32M
64M
Parameter
Symbol
Unit
Notes
Min.
70
—
Max.
1000
60
Min.
65
—
—
—
—
—
20
5
Max.
1000
65
40
65
30
20
1000
—
Min.
65
—
—
—
—
—
20
5
Max.
1000
65
40
65
30
20
1000
—
Read Cycle Time
tRC
tCE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 2
CE1# Access Time
3
OE# Access Time
tOE
—
40
3
Address Access Time
tAA
—
60
3, 5
LB# / UB# Access Time
tBA
—
30
3
Page Address Access Time
Page Read Cycle Time
tPAA
tPRC
tOH
N/A
N/A
3,6
1, 6, 7
Output Data Hold Time
5
5
—
—
3
4
4
4
3
3
3
CE1# Low to Output Low-Z
OE# Low to Output Low-Z
LB# / UB# Low to Output Low-Z
CE1# High to Output High-Z
OE# High to Output High-Z
LB# / UB# High to Output High-Z
Address Setup Time to CE1# Low
Address Setup Time to OE# Low
Address Invalid Time
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
tASC
tASO
tAX
5
—
5
—
0
—
0
—
0
—
0
—
0
—
0
—
—
—
—
−6
10
—
-6
-6
10
10
20
20
20
—
—
—
—
–6
10
—
–6
–6
12
12
20
14
20
—
—
—
—
–6
10
—
–6
–6
25
12
20
14
20
—
—
—
—
10
—
10
—
10
—
5, 8
9
Address Hold Time from CE1# High
Address Hold Time from OE# High
WE# High to OE# Low Time for Read
CE1# High Pulse Width
tCHAH
tOHAH
tWHOL
tCP
—
—
—
1000
—
—
—
10
—
—
Notes:
1. Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A21. If needed by system
operation, please contact local Spansion representative for the relaxation of 1µs limitation.
2. Address should not be changed within minimum tRC
.
3. The output load 50 pF with 50 ohm termination to VDD x 0.5 (16M), The output load 50 pF (32M and 64M).
4. The output load 5pF.
5. Applicable to A3 to A21 (32M and 64M) when CE1# is kept at Low.
6. Applicable only to A0, A1 and A2 (32M and 64M) when CE1# is kept at Low for the page address access.
7. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4 µs. In other
words, Page Read Cycle must be closed within 4 µs.
8. Applicable when at least two of address inputs among applicable are switched from previous state.
9.
tRC(min) and tPRC(min) must be satisfied.
10. If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read can become longer by the
amount of subtracting the actual value from the specified minimum value.
February 8, 2005 S71GL064A_00_A2
pSRAM Type 7
107
A d v a n c e I n f o r m a t i o n
AC Characteristics
Write Operation
16M
32M
64M
Parameter
Write Cycle Time
Symbol
tWC
Min.
70
0
Max.
1000
—
Min.
65
0
Max.
Min.
65
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1000
—
1000
—
1,2
3
Address Setup Time
tAS
CE1# Write Pulse Width
tCW
tWP
45
45
45
-5
-5
0
—
40
40
40
–5
–5
0
—
40
40
40
–5
–5
0
—
3
WE# Write Pulse Width
—
—
—
3
LB#/UB# Write Pulse Width
LB#/UB# Byte Mask Setup Time
LB#/UB# Byte Mask Hold Time
Write Recovery Time
tBW
—
—
—
3
tBS
—
—
—
4
tBH
—
—
—
5
tWR
tCP
—
—
—
6
CE1# High Pulse Width
10
7.5
10
15
0
—
12
7.5
12
12
0
—
12
7.5
12
12
0
—
WE# High Pulse Width
tWHP
tBHP
tDS
1000
1000
—
1000
1000
—
1000
1000
—
7
LB#/UB# High Pulse Width
Data Setup Time
Data Hold Time
tDH
—
—
—
OE# High to CE1# Low Setup Time for Write
OE# High to Address Setup Time for Write
LB# and UB# Write Pulse Overlap
tOHCL
tOES
tBWO
-5
0
—
–5
0
—
–5
0
—
8
9
—
—
—
30
—
30
—
30
—
Notes:
1. Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system
operation, please contact local Spansion representative for the relaxation of 1µs limitation.
2. Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWR).
3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last.
4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever
occurs last.
5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever
occurs first.
6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first.
7.
tWPH minimum is absolute minimum value for device to detect High level. And it is defined at minimum VIH level.
8. If OE# is Low after minimum tOHCL, read cycle is initiated. In other words, OE# must be brought to High within 5ns after
CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met.
9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time
or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met and data
bus is in High-Z.
108
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e i n f o r m a t i o n
AC Characteristics
Power Down Parameters
16M
32M
64M
Parameter
Symbol Min. Max. Min. Max. Min. Max. Unit Note
CE2 Low Setup Time for Power Down Entry
CE2 Low Hold Time after Power Down Entry
tCSP
10
80
—
—
10
65
—
—
10
65
—
—
ns
ns
tC2LP
CE1# High Hold Time following CE2 High after Power
Down Exit [SLEEP mode only]
tCHH
tCHHP
tCHS
300
—
300
1
—
—
—
300
1
—
—
—
µ
s
s
1
2
1
CE1# High Hold Time following CE2 High after Power
Down Exit [not in SLEEP mode]
N/A
µ
CE1# High Setup Time following CE2 High after Power
Down Exit
0
—
0
0
ns
Notes:
1. Applicable also to power-up.
2. Applicable when 4Mb and 8Mb Partial modes are programmed.
Other Timing Parameters
16M
32M
64M
Parameter
Symbol Min. Max. Min. Max. Min. Max. Unit Note
CE1# High to OE# Invalid Time for Standby Entry
CE1# High to WE# Invalid Time for Standby Entry
CE2 Low Hold Time after Power-up
tCHOX
tCHWX
tC2LH
tCHH
tT
10
10
50
300
1
—
—
—
—
25
10
10
50
300
1
—
—
—
—
25
10
10
50
300
1
—
—
—
—
25
ns
ns
1
2
µ
s
s
CE1# High Hold Time following CE2 High after Power-up
Input Transition Time
µ
ns
Notes:
1. Some data might be written into any address location if tCHWX(min) is not satisfied.
2. The Input Transition Time (tT) at AC testing is 5ns as shown in below. If actual tT is longer than 5ns, it can violate the AC
specification of some of the timing parameters.
February 8, 2005 S71GL064A_00_A2
pSRAM Type 7
109
A d v a n c e I n f o r m a t i o n
AC Characteristics
AC Test Conditions
Symbol
VIH
Description
Te s t S e t up
Value
VDD * 0.8
VDD * 0.2
VDD * 0.5
5
Unit
V
Note
Input High Level
VIL
Input Low Level
V
VREF
tT
Input Timing Measurement Level
Input Transition Time
V
Between VIL and VIH
ns
AC Measurement Output Load Circuits
VDD *0.5 V
50 ohm
OUT
VDD
DEVICE
UNDER
TEST
0.1 µF
VSS
50 pF
Figure 37. AC Output Load Circuit – 16 Mb
VDD
DEVICE
UNDER
TEST
OUT
0.1µF
VSS
50pF
Figure 38. AC Output Load Circuit – 32 Mb and 64 Mb
110
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e i n f o r m a t i o n
Timing Diagrams
Read Timings
tRC
ADDRESS VALID
ADDRESS
tASC
tCE
tCHAH
tASC
CE1#
OE#
tCP
tCHZ
tOE
tOHZ
tBHZ
tBA
LB#/UB#
tBLZ
tOLZ
DQ
(Output)
tCLZ
VALID DATA OUTPUT
tOH
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 39. Read Timing #1 (Basic Timing)
tAx
tRC
tRC
ADDRESS
CE1#
ADDRESS VALID
ADDRESS VALID
tAA
tAA
tOHAH
Low
tASO
tOE
OE#
LB#/UB#
tOLZ
tOH
tOHZ
tOH
DQ
(Output)
VALID DATA OUTPUT
Note: This timing diagram assumes CE2=H and WE#=H.
VALID DATA OUTPUT
Figure 40. Read Timing #2 (OE# Address Access
February 8, 2005 S71GL064A_00_A2
pSRAM Type 7
111
A d v a n c e I n f o r m a t i o n
tAX
tRC
tAx
ADDRESS
ADDRESS VALID
tAA
Low
CE1#, OE#
tBA
tBA
LB#
tBA
UB#
tBHZ
tBHZ
tOH
tOH
tBLZ
tBLZ
DQ1-8
(Output)
VALID DATA
OUTPUT
tBHZ
VALID DATA
OUTPUT
tOH
tBLZ
DQ9-16
(Output)
VALID DATA OUTPUT
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 41. Read Timing #3 (LB#/UB# Byte Access)
tRC
ADDRESS
(A21-A3)
ADDRESS VALID
tRC
tPRC
tPRC
tPRC
ADDRESS
(A2-A0)
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS VALID
tASC
tCHAH
tPAA
tPAA
tPAA
CE1#
OE#
tCHZ
tCE
LB#/UB#
tOH
tCLZ
tOH
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
(Page Access)
VALID DATA OUTPUT
(Normal Access)
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 42. Read Timing #4 (Page Address Access after CE1# Control Access for 32M and 64M Only)
112
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e i n f o r m a t i o n
tRC
tAX
tRC
tAx
ADDRESS
(A21-A3)
ADDRESS VALID
ADDRESS VALID
tRC
tPRC
tRC
tPRC
ADDRESS
(A2-A0)
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
tAA
tPAA
tAA
tPAA
CE1#
Low
tASO
tOE
OE#
tBA
LB#/UB#
tOLZ
tBLZ
tOH
tOH
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
(Page Access)
VALID DATA OUTPUT
(Normal Access)
Notes:
1. This timing diagram assumes CE2=H and WE#=H.
2. Either or both LB# and UB# must be Low when both CE1# and OE# are Low.
Figure 43. Read Timing #5 (Random and Page Address Access for 32M and 64M Only)
Write Timings
tWC
ADDRESS
ADDRESS VALID
tAS
tCW
tWR
tWR
tWR
tAS
CE1#
WE#
tCP
tAS
tWP
tAS
tWHP
tAS
tBW
tAS
LB#, UB#
tBHP
tOHCL
OE#
tDS
tDH
DQ
(Input)
VALID DATA INPUT
Note: This timing diagram assumes CE2=H.
Figure 44. Write Timing #1 (Basic Timing)
February 8, 2005 S71GL064A_00_A2
pSRAM Type 7
113
A d v a n c e I n f o r m a t i o n
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
tOHAH
Low
tAS
tWP
tWR
tAS
tWP
tWR
WE#
tWHP
LB#, UB#
OE#
tOES
tOHZ
tDS
tDH
tDS
tDH
DQ
(Input)
VALID DATA INPUT
VALID DATA INPUT
Note:This timing diagram assumes CE2=H.
Figure 45. Write Timing #2 (WE# Control)
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
tAS
tWP
tAS
tWP
tWHP
tBS
WE#
LB#
tBH
tWR
tWR
tBS
tBH
UB#
tDS
tDH
DQ1-8
(Input)
VALID DATA INPUT
tDS
tDH
DQ9-16
(Input)
Note: This timing diagram assumes CE2=H and OE#=H.
Figure 46. Write Timing #3-1(WE#/LB#/UB# Byte Write Control)
114
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e i n f o r m a t i o n
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
tWR
tWR
WE#
LB#
tWHP
tAS
tBW
tBS
tBH
tAS
tBW
tBH
tBS
UB#
tDS
tDH
DQ1-8
(Input)
VALID DATA INPUT
tDS
tDH
DQ9-16
(Input)
VALID DATA INPUT
Note: This timing diagram assumes CE2=H and OE#=H.
Figure 47. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control)
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
WE#
LB#
tAS
tBW
tWR
tAS
tBW
tWR
tDH
tBHP
tBWO
tDS
tDH
tDS
DQ1-8
(Input)
VALID
DATA INPUT
VALID
DATA INPUT
tAS
tBW
tWR
tAS
tWR
tBWO
tBW
UB#
tBHP
tDS
tDH
tDS
tDH
DQ9-16
(Input)
VALID
DATA INPUT
VALID
DATA INPUT
Note: This timing diagram assumes CE2=H and OE#=H.
Figure 48. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control)
February 8, 2005 S71GL064A_00_A2
pSRAM Type 7
115
A d v a n c e I n f o r m a t i o n
Read/Write Timings
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tCHAH
tAS
tCW
tWR
tASC
tCE
tCHAH
tCP
tCP
WE#
UB#, LB#
OE#
tOHCL
tCHZ
tOH
tDS
tDH
tCLZ
tOH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
Notes:
1. This timing diagram assumes CE2=H.
2. Write address is valid from either CE1# or WE# of last falling edge.
Figure 49. Read/Write Timing #1-1 (CE1# Control)
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tCHAH
tAS
tWR
tASC
tCE
tCHAH
tCP
tCP
tWP
WE#
UB#, LB#
OE#
tOHCL
tOE
tCHZ
tOH
tDS
tDH
tOLZ
tOH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
READ DATA OUTPUT
Notes:
1. This timing diagram assumes CE2=H.
2. OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read sequence.
Figure 50. Read / Write Timing #1-2 (CE1#/WE#/OE# Control)
116
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e i n f o r m a t i o n
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tOHAH
tOHAH
tAA
Low
tAS
tWR
tWP
WE#
UB#, LB#
OE#
tOES
tASO
tOE
tWHOL
tOHZ
tOH
tOHZ
tOH
tDS
tDH
tOLZ
DQ
READ DATA OUTPUT
READ DATA OUTPUT
WRITE DATA INPUT
Notes:
1. This timing diagram assumes CE2=H.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
Figure 51. Read / Write Timing #2 (OE#, WE# Control)
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tAA
tOHAH
tOHAH
Low
WE#
tOES
tAS
tBW
tWR
tBA
UB#, LB#
OE#
tBHZ
tASO
tWHOL
tBHZ
tOH
tDS
tDH
tBLZ
tOH
DQ
READ DATA OUTPUT
READ DATA OUTPUT
WRITE DATA INPUT
Notes:
1. This timing diagram assumes CE2=H.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
Figure 52. Read / Write Timing #3 (OE#, WE#, LB#, UB# Control)
February 8, 2005 S71GL064A_00_A2
pSRAM Type 7
117
A d v a n c e I n f o r m a t i o n
CE1#
CE2
tCHS
tC2LH
tCHH
VDD
VDD min
0V
Note: The t
specifies after V
reaches specified minimum level.
C2LH
DD
Figure 53. Power-up Timing #1
CE1#
tCHH
CE2
VDD
VDD min
0V
Note: The t
specifies after V
reaches specified minimum level and applicable to both CE1# and CE2.
CHH
DD
Figure 54. Power-up Timing #2
CE1#
tCHS
CE2
DQ
tCSP
tC2LP
tCHH (tCHHP)
High-Z
Power Down Entry
Power Down Mode
Power Down Exit
Note: This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and
Power-Down program was not performed prior to this reset.
Figure 55. Power Down Entry and Exit Timing
118
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e i n f o r m a t i o n
CE1#
OE#
tCHOX
tCHWX
WE#
Active (Read)
and t define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes
CHWX
Standby
Active (Write)
Standby
Note: Both t
CHOX
t
(min) period for Standby mode from CE1# Low to High transition.
RC
Figure 56. Standby Entry Timing after Read or Write
tRC
tWC
tWC
tWC
tWC
tRC
MSB*1
MSB*1
MSB*1
MSB*1
MSB*1
Key*2
ADDRESS
CE1#
tCP*3
tCP
tCP
tCP
tCP
tCP
OE#
WE#
LB#, UB#
DQ*3
RDa
Cycle #1
RDa
Cycle #2
RDa
Cycle #3
X
X
RDb
Cycle #6
Cycle #4
Cycle #5
Notes:
1. The all address inputs must be High from Cycle #1 to #5.
2. The address key must confirm the format specified in page 104. If not, the operation and data are not guaranteed.
3. After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation.
Figure 57. Power Down Program Timing (for 32M/64M Only)
February 8, 2005 S71GL064A_00_A2
pSRAM Type 7
119
A d v a n c e I n f o r m a t i o n
Type 1 SRAM
4/8 Megabit CMOS SRAM
Common Features
Process Technology: Full CMOS
Power Supply Voltage: 2.7~3.3V
Three state outputs
Organization
Standby
Version
Density
4Mb
(ISB1, Max.)
x8 or x16 (note 1)
x8 or x16 (note 1)
x8 or x16 (note 1)
X16
(ICC2, Max.)
Operating
22 mA
22 mA
22 mA
TBD
Mode
F
G
C
D
10 µA
10 µA
15 µA
TBD
Dual CS, UB# / LB# (tCS)
Dual CS, UB# / LB# (tCS)
Dual CS, UB# / LB# (tCS)
Dual CS, UB# / LB# (tCS)
4Mb
8Mb
8Mb
Notes:
1. UB#, LB# swapping is available only at x16. x8 or x16 select by BYTE# pin.
Pin Description
Pin Name
CS1#, CS2
OE#
Description
I/O
Chip Selects
I
I
I
I
Output Enable
WE#
Write Enable
BYTE#
Word (VCC)/Byte (VSS) Select
A0~A17 (4M)
A0~A18 (8M)
Address Inputs
I
SA
Address Input for Byte Mode
Data Inputs/Outputs
Power Supply
I
I/O
-
I/O0~I/O15
VCC
VSS
Ground
-
DNU
Do Not Use
-
NC
No Connection
-
120
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Functional Description
4M Version F, 4M version G, 8M version C
CS1# CS2 OE# WE# BYTE#
SA
X
X
X
X
X
X
X
X
X
X
X
LB#
X
X
H
L
UB#
X
IO0~7
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
IO8~15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Standby
Standby
Active
H
X
X
L
L
L
L
L
L
L
L
X
L
X
X
X
H
H
L
X
X
X
H
H
H
H
H
L
X
Deselected
X
X
Deselected
X
H
H
H
H
H
H
H
H
X
H
X
Deselected
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X
L
L
Active
H
L
Active
L
H
L
High-Z
Dout
Active
L
L
Dout
Active
X
X
X
L
H
L
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
L
H
L
High-Z
Din
Active
L
L
Din
Active
Note: X means don’t care (must be low or high state).
Byte Mode
CS1# CS2 OE# WE# BYTE#
SA
X
LB#
X
UB#
X
IO0~7
IO8~15
High-Z
High-Z
High-Z
High-Z
High-Z
Mode
Power
Standby
Standby
Standby
Active
H
X
L
X
L
X
X
H
L
X
X
H
L
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
Deselected
X
X
X
Deselected
H
H
H
X
X
H
H
Deselected
L
VCC
VCC
X
L
X
Output Disabled
Output Disabled
L
X
L
X
X
L
Active
February 8, 2005 S71GL064A_00_A2
Type 1 SRAM
121
A d v a n c e I n f o r m a t i o n
Functional Description
8M Version D
CS1#
H
X
X
L
CS2
X
OE#
X
WE#
X
LB#
X
X
H
L
UB#
X
IO0~8
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
IO9~16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Standby
Standby
Active
Deselected
L
X
X
X
Deselected
X
X
X
H
X
Deselected
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
L
X
L
L
Active
L
H
L
Active
L
L
H
L
High-Z
Dout
Active
L
L
L
Dout
Active
L
X
L
H
L
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
L
X
L
H
L
High-Z
Din
Active
L
X
L
L
Din
Active
Note: X means don’t care (must be low or high state).
Absolute Maximum Ratings
4M Version F
Item
Symbol
Ratings
Unit
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Power Dissipation
VIN,VOUT
VCC
-0.2 to VCC+0.3V
-0.2 to 4.0V
1.0
V
V
PD
W
Operating Temperature
TA
-40 to 85
°C
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
4M Version G, 8M Version C, 8M Version D
Item
Symbol
VIN,VOUT
VCC
Ratings
-0.2 to VCC+0.3V (Max. 3.6V)
-0.2 to 3.6V
Unit
V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Power Dissipation
V
PD
1.0
W
Operating Temperature
TA
-40 to 85
°C
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
122
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
DC Characteristics
Recommended DC Operating Conditions (Note 1)
Item
Symbol
VCC
Min
Typ
3.0
0
Max
Unit
V
Supply voltage
Ground
2.7
3.3
VSS
0
2.2
0
VCC+0.2 (Note 2)
0.6
V
Input high voltage
Input low voltage
VIH
-
V
VIL
-0.2 (Note 3)
-
V
Notes:
1. T = -40 to 85°C, unless otherwise specified.
A
2. Overshoot: Vcc+1.0V in case of pulse width ≤20ns.
3. Undershoot: -1.0V in case of pulse width ≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Capacitance
(f=1MHz, TA=25°C)
Item
Symbol
CIN
Test Condition
Min
Max
8
Unit
Input capacitance
VIN=0V
VIO=0V
-
-
pF
pF
Input/Output capacitance
CIO
10
Note: Capacitance is sampled, not 100% tested
DC Operating Characteristics
Common
Typ
Item
Symbol
Test Conditions
Min
(Note)
Max
Unit
Input leakage current
ILI
VIN=VSS to VCC
-1
-
1
µ
A
A
CS1#=VIH or CS2=VIL or OE#=VIH or WE#=VIL
or LB#=UB#=VIH, VIO=Vss to VCC
Output leakage current
ILO
-1
-
1
µ
Output low voltage
Output high voltage
VOL
VOH
IOL = 2.1mA
IOH = -1.0mA
-
-
-
0.4
-
V
2.4
V
February 8, 2005 S71GL064A_00_A2
Type 1 SRAM
123
A d v a n c e I n f o r m a t i o n
4M Version F
Typ
Item
Symbol
Test Conditions
Min
(Note)
Max
Unit
Cycle time=1µs, 100% duty, IIO=0mA, CS1#
CS2 VCC-0.2V,
BYTE#=VSS or VCC, VIN
0.2V or/and UB# 0.2V
≤ 0.2V,
≥
ICC1
-
-
-
3
mA
≤
0.2V or VIN ≥ VCC-0.2V, LB#
≤
≤
Average operating current
Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL,
CS2=VIH,
ICC2
-
-
22
10
mA
µA
BYTE# = VSS or VCC, VIN=VIL or VIH, LB#
and UB# 0.2V
≤ 0.2V or/
≤
CS1#
≥ VCC-0.2V, CS2 ≥ VCC-0.2V (CS1# controlled)
ISB1
(Note)
1.0
(Note)
or CS2 0.2V (CS2 controlled), BYTE# = VSS or VCC
≤
,
Standby Current (CMOS)
Other input =0~VCC
Note: Typical values are not 100% tested.
4M Version G
Typ
Item
Symbol
Test Conditions
Min
(Note)
Max
Unit
Cycle time=1µs, 100% duty, IIO=0mA, CS1# ≤ 0.2V,
CS2
BYTE#=VSS or VCC, VIN
0.2V or/and UB# 0.2V
≥ VCC-0.2V,
ICC1
-
-
-
4
mA
≤
0.2V or VIN ≥ VCC-0.2V, LB#
≤
≤
Average operating current
Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL,
CS2=VIH,
ICC2
-
-
22
10
mA
µA
BYTE# = VSS or VCC, VIN=VIL or VIH, LB#
and UB# 0.2V
≤ 0.2V or/
≤
CS1#
≥ VCC-0.2V, CS2 ≥ VCC-0.2V (CS1# controlled)
ISB1
(Note)
3.0
(Note)
or CS2 0.2V (CS2 controlled), BYTE# = VSS or VCC
≤
,
Standby Current (CMOS)
Other input = 0~VCC
Note: Typical values are not 100% tested.
124
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
8M Version C
Typ
Item
Symbol
Test Conditions
Min
(Note)
Max
Unit
Cycle time=1µs, 100% duty, IIO=0mA, CS1# ≤ 0.2V,
CS2
BYTE#=VSS or VCC, VIN
0.2V or/and UB# 0.2V
≥ VCC-0.2V,
ICC1
-
-
3
mA
≤
0.2V or VIN ≥ VCC-0.2V, LB#
≤
≤
Average operating current
Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL,
CS2=VIH,
ICC2
-
-
-
-
22
15
mA
µA
BYTE# = VSS or VCC, VIN=VIL or VIH, LB#
and UB# 0.2V
≤ 0.2V or/
≤
CS1#
≥ VCC-0.2V, CS2 ≥ VCC-0.2V (CS1# controlled)
ISB1
(Note)
or CS2 0.2V (CS2 controlled), BYTE# = VSS or VCC
≤
,
Standby Current (CMOS)
Other input = 0~VCC
Note: Typical values are not 100% tested.
8M Version D
Typ
Item
Symbol
Test Conditions
Min
(Note)
Max
Unit
Cycle time=1µs, 100% duty, IIO=0mA, CS1# ≤ 0.2V,
CS2
BYTE#=VSS or VCC, VIN
0.2V or/and UB# 0.2V
≥ VCC-0.2V,
ICC1
-
-
TBD
mA
≤
0.2V or VIN ≥ VCC-0.2V, LB#
≤
≤
Average operating current
Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL,
CS2=VIH,
ICC2
-
-
-
-
TBD
TBD
mA
µA
BYTE# = VSS or VCC, VIN=VIL or VIH, LB#
and UB# 0.2V
≤ 0.2V or/
≤
CS1#
≥ VCC-0.2V, CS2 ≥ VCC-0.2V (CS1# controlled)
ISB1
(Note)
or CS2 0.2V (CS2 controlled), BYTE# = VSS or VCC
≤
,
Standby Current (CMOS)
Other input = 0~VCC
Note: Typical values are not 100% tested.
February 8, 2005 S71GL064A_00_A2
Type 1 SRAM
125
A d v a n c e I n f o r m a t i o n
AC Operating Conditions
Test Conditions
Test Load and Test Input/Output Reference
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See Figure 58): CL= 30pF+1TTL
V
(note 3)
TM
R2 (note 2)
R1 (note 2)
CL (note 1)
Figure 58. AC Output Load
Notes:
1. Including scope and jig capacitance.
2. R1=3070Ω, R2=3150Ω.
3. VTM =2.8V.
AC Characteristics
Table 33. Read/Write Characteristics (VCC=2.7-3.3V)
Speed Bins
70ns
Parameter List
Read cycle time
Symbol
tRC
Min
70
-
Max
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
tAA
70
70
35
70
-
Chip select to output
tCO1, tCO2
tOE
-
Output enable to valid output
LB#, UB# Access Time
-
tBA
-
Chip select to low-Z output
LB#, UB# enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB#, LB# disable to high-Z output
Output disable to high-Z output
Output hold from address change
tLZ1, tLZ2
tBLZ
10
10
5
-
tOLZ
-
tHZ1, tHZ2
tBHZ
0
25
25
25
-
0
tOHZ
0
tOH
10
126
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
Table 33. Read/Write Characteristics (VCC=2.7-3.3V) (Continued)
Speed Bins
70ns
Parameter List
Write cycle time
Symbol
tWC
tCW
tAS
Min
70
60
0
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
Chip select to end of write
Address set-up time
-
Address valid to end of write
LB#, UB# valid to end of write
Write pulse width
tAW
60
60
50
0
-
tBW
-
tWP
-
Write recovery time
tWR
tWHZ
tDW
tDH
-
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
0
20
-
30
0
-
tOW
5
-
Data Retention Characteristics
4M Version F
Item
Symbol
Test Condition
Min
Typ
Max Unit
VCC for data retention
VDR
CS1#
≥
VCC-0.2V (Note 1), VIN
≥
0V. BYTE# = VSS or VCC 1.5
-
3.3
10
V
1.0
(Note 2)
Data retention current
IDR
VCC=3.0V, CS1#
≥
VCC-0.2V (Note 1), VIN
≥
0V
-
µA
Data retention set-up time
Recovery time
tSDR
tRDR
0
-
-
-
-
See data retention waveform
ns
tRC
Notes:
1. CS1 controlled:CS1#≥ VCC-0.2V. CS2 controlled: CS2 ≤ 0.2V.
2. Typical values are not 100% tested.
February 8, 2005 S71GL064A_00_A2
Type 1 SRAM
127
A d v a n c e I n f o r m a t i o n
4M Version G
Item
Symbol
VDR
Test Condition
Min
Typ
Max Unit
VCC for data retention
CS1#
≥
VCC-0.2V (Note 1), VIN
≥
0V. BYTE# = VSS or VCC 1.5
-
-
-
-
3.3
3
V
Data retention current
Data retention set-up time
Recovery time
IDR
VCC=1.5V, CS1#
≥
VCC-0.2V (Note 1), VIN
≥
0V
-
0
µA
tSDR
tRDR
-
See data retention waveform
ns
tRC
-
Notes:
1. CS1 controlled:CS1#≥ V -0.2V. CS2 controlled: CS2 ≤ 0.2V.
CC
8M Version C
Item
Symbol
VDR
Test Condition
VCC-0.2V (Note 1). BYTE# = VSS or VCC
VCC=3.0V, CS1# VCC-0.2V (Note 1)
Min
1.5
-
Typ
Max Unit
VCC for data retention
Data retention current
Data retention set-up time
Recovery time
CS1#
≥
-
-
-
-
3.3
15
-
V
IDR
≥
µA
tSDR
tRDR
0
See data retention waveform
ns
tRC
-
Notes:
1. CS1 controlled:CS1#≥ VCC-0.2V. CS2 controlled: CS2 ≤ 0.2V.
8M Version D
Item
Symbol
VDR
Test Condition
Min
1.5
-
Typ
Max Unit
VCC for data retention
Data retention current
Data retention set-up time
Recovery time
CS1#
≥
VCC-0.2V (Note 1), BYTE# = VSS or VCC
-
-
-
-
3.3
TBD
-
V
IDR
VCC=3.0V, CS1#
≥
VCC-0.2V (Note 1)
µA
tSDR
tRDR
0
See data retention waveform
ns
tRC
-
Notes:
1. CS1 controlled:CS1#≥ VCC-0.2V. CS2 controlled: CS2 ≤ 0.2V.
Timing Diagrams
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
Figure 59. Timing Waveform of Read Cycle(1) (Address Controlled, CS#1=OE#=VIL, CS2=WE#=VIH, UB#
and/or LB#=VIL)
128
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
tRC
Address
tOH
tAA
tCO1
CS1#
CS2
tCO2
tBA
tHZ
UB#, LB#
tBHZ
tOHZ
tOE
OE#
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
Notes:
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
2. At any given temperature and voltage condition, t (Max.) is less than t (Min.) both for a given device and from
HZ
LZ
device to device interconnection.
Figure 60. Timing Waveform of Read Cycle(2) (WE#=VIH, if BYTE# is Low, Ignore UB#/LB# Timing)
tWC
Address
tCW(2)
tWR(4)
CS1#
tAW
CS2
tCW(2)
tBW
UB#, LB#
tWP(1)
WE#
tAS(3)
tDW
Data Valid
tDH
High-Z
High-Z
Data in
tWHZ
tOW
Data out
Data Undefined
Figure 61. Timing Waveform of Write Cycle(1) (WE# controlled, if BYTE# is Low, Ignore UB#/LB# Timing)
February 8, 2005 S71GL064A_00_A2
Type 1 SRAM
129
A d v a n c e I n f o r m a t i o n
tWC
Address
CS1#
tAS(3)
tCW(2)
tAW
tWR(4)
CS2
UB#, LB#
WE#
tBW
tWP(1)
tDW
Data Valid
tDH
Data in
Data out
High-Z
High-Z
Figure 62. Timing Waveform of Write Cycle(2) (CS# controlled, if BYTE# is Low, Ignore UB#/LB# Timing)
tWC
Address
tCW(2)
tWR(4)
CS1#
tAW
CS2
tCW(2)
tBW
UB#, LB#
tAS(3)
tWP(1)
WE#
tDH
tDW
Data Valid
Data in
Data out
High-Z
High-Z
Notes:
1. A write occurs during the overlap (t ) of low CS1# and low WE#. A write begins when CS1# goes low and WE#
WP
goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double
byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The t
measured from the beginning of write to the end of write.
is
WP
2. t
is measured from the CS1# going low to the end of write.
CW
3. t is measured from the address valid to the beginning of write.
AS
4. t
is measured from the end of write to the address change. t
applied in case a write ends as CS1# or WE#
WR
WR
going high.
Figure 63. Timing Waveform of Write Cycle(3) (UB#, LB# controlled)
130
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
A d v a n c e I n f o r m a t i o n
CS1# Controlled
Data Retention Mode
tSDR
tRDR
V
CC
2.7V
2.2V
V
DR
CS1# V
CC
- 0.2V
CS1#
GND
CS2 Controlled
Data Retention Mode
V
CC
2.7V
CS2
tSDR
tRDR
V
DR
CS2 0.2V
0.4V
GND
Figure 64. Data Retention Waveform
February 8, 2005 S71GL064A_00_A2
Type 1 SRAM
131
A d v a n c e I n f o r m a t i o n
Revision Summary
Revision A (October 28, 2004)
Initial release.
Revision A1 (December 7, 2004)
Global
Access speed updated.
MCP Block Diagram
Control signals updated.
Pin Description
Descriptions updated.
Ordering Information
Package Modifiers and pSRAM densities updated.
Valid Combinations table
Speed options updated.
Revision A2 (February 8, 2005)
pSRAM Type 7
Entire section updated.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable ( i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-
tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and
product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
132
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
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