S71GL128NB0_技术文档

S71GL512NB0/S71GL256NB0/

S71GL128NB0

Stacked Multi-chip Product (MCP)

512/256/128 Megabit (32/16/8 M x 16-bit) CMOS 3.0 Volt-only

MirrorBit^TMPage-mode Flash Memory with

32 Megabit (2M x 16-bit) pSRAM

ADVANCE

INFORMATION

Distinctive Characteristics

MCP Features

Power supply voltage of 2.7 to 3.1V

High Performance

90 ns access time (S71GL128N, S71GL256N)

100 ns access time (S71GL512N)

25 ns page read times

Packages:

— 9.0 x 12.0 mm x 1.2 mm FBGA (TLD084) (S71GL512N)

— 8.0 x 11.6 mm x 1.2 mm FBGA (TLA084) (S71GL128N, S71GL256N)

Operating Temperature

— -25°C to +85°C (Wireless)

— -40°C to +85°C (Industrial)

General Description

The S71GL Series is a product line of stacked Multi-chip Product (MCP) packages

and consists of

One Flash memory die

one pSRAM

The products covered by this document are listed in the table below. For details

about their specifications, please refer to the individual constituent datasheets

for further details.

Flash Memory Density

512 Mb

256 Mb

128 Mb

64 Mb

32 Mb

16 Mb

pSRAM Density

S71GL512NB0

S71GL256NB0

S71GL128NB0

Publication Number S71GL512_256_128NB0_00 Revision A Amendment 1 Issue Date December 7, 2004

This document contains information on a product under development at Spansion LLC. The information is intended to help you evaluate this product. Spansion LLC

reserves the right to change or discontinue work on this proposed product without notice.

A d v a n c e I n f o r m a t i o n

Logical Inhibit ................................................................................................... 45

Power-Up Write Inhibit ...............................................................................45

S71GL512NB0/S71GL256NB0/S71GL128NB0

General Description . . . . . . . . . . . . . . . . . . . . . . . . 1

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

MCP Block Diagram (128Mb Flash + 32Mb pSRAM) ..................................5

MCP Block Diagram (256Mb Flash + 32Mb pSRAM) .................................5

MCP Block Diagram (512Mb Flash + 32Mb pSRAM) ..................................6

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7

512 Mb Flash + 32 Mb pSRAM Pinout .............................................................7

256 Mb Flash + 32 Mb pSRAM Pinout ............................................................8

128 Mb Flash + 32 Mb pSRAM Pinout .............................................................9

128 Mb Flash + 32 Mb pSRAM Pinout (S71GL128NB0 Only) ..................10

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 11

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 12

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 16

Common Flash Memory Interface (CFI) . . . . . . . 45

Table 6. CFI Query Identification String ................................ 47

Table 7. System Interface String.......................................... 47

Table 8. Device Geometry Definition..................................... 48

Table 9. Primary Vendor-Specific Extended Query.................. 49

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 49

Reading Array Data ...........................................................................................50

Reset Command .................................................................................................50

Autoselect Command Sequence ...................................................................50

Enter Secured Silicon Sector/Exit Secured Silicon

Sector Command Sequence .............................................................................51

Word Program Command Sequence ...........................................................51

Unlock Bypass Command Sequence ........................................................ 52

Write Buffer Programming ......................................................................... 52

Accelerated Program .....................................................................................53

Figure 1. Write Buffer Programming Operation....................... 54

Figure 2. Program Operation ............................................... 55

Program Suspend/Program Resume Command Sequence .................... 55

Figure 3. Program Suspend/Program Resume........................ 56

Chip Erase Command Sequence ................................................................... 56

Sector Erase Command Sequence ................................................................ 57

Figure 4. Erase Operation ................................................... 58

Erase Suspend/Erase Resume Commands ..................................................58

Lock Register Command Set Definitions .................................................... 59

Password Protection Command Set Definitions ......................................59

Non-Volatile Sector Protection Command Set Definitions ...................61

Global Volatile Sector Protection Freeze Command Set .......................61

Volatile Sector Protection Command Set ..................................................62

Secured Silicon Sector Entry Command .....................................................62

Secured Silicon Sector Exit Command ........................................................ 63

Command Definitions ........................................................................................64

Table 10. S29GL512N, S29GL256N, S29GL128N Command

S29GLxxxN MirrorBit^TMFlash Family

Datasheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

General Description . . . . . . . . . . . . . . . . . . . . . . . 20

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .23

Table 1. Device Bus Operations ........................................... 23

Word/Byte Configuration ................................................................................23

Requirements for Reading Array Data .........................................................23

Page Mode Read ............................................................................................. 24

Writing Commands/Command Sequences ................................................ 24

Write Buffer .................................................................................................... 24

Accelerated Program Operation ...............................................................25

Autoselect Functions .....................................................................................25

Standby Mode .......................................................................................................25

Automatic Sleep Mode ......................................................................................25

RESET#: Hardware Reset Pin .........................................................................25

Output Disable Mode ....................................................................................... 26

Table 2. Sector Address Table–S29GL256N ........................... 26

Table 3. Sector Address Table–S29GL128N ........................... 33

Sector Protection ................................................................................................37

Persistent Sector Protection .......................................................................37

Password Sector Protection ........................................................................37

WP# Hardware Protection .........................................................................37

Selecting a Sector Protection Mode .........................................................37

Advanced Sector Protection ...........................................................................38

Lock Register ........................................................................................................38

Table 4. Lock Register ........................................................ 39

Persistent Sector Protection ...........................................................................39

Dynamic Protection Bit (DYB) ...................................................................39

Persistent Protection Bit (PPB) .................................................................40

Persistent Protection Bit Lock (PPB Lock Bit) ...................................... 41

Table 5. Sector Protection Schemes ..................................... 41

Persistent Protection Mode Lock Bit ........................................................... 41

Password Sector Protection ........................................................................... 42

Password and Password Protection Mode Lock Bit ............................... 42

64-bit Password ...................................................................................................43

Persistent Protection Bit Lock (PPB Lock Bit) ...........................................43

Secured Silicon Sector Flash Memory Region ............................................43

Write Protect (WP#) ........................................................................................45

Hardware Data Protection ..............................................................................45

Low VCC Write Inhibit ................................................................................45

Write Pulse “Glitch” Protection ................................................................45

Definitions, x16 .................................................................64

Table 11. S29GL512N, S29GL256N, S29GL128N Command

Definitions, x8 ...................................................................67

Write Operation Status ...................................................................................69

DQ7: Data# Polling ...........................................................................................70

Figure 5. Data# Polling Algorithm ........................................ 71

RY/BY#: Ready/Busy# ........................................................................................ 71

DQ6: Toggle Bit I ...............................................................................................72

Figure 6. Toggle Bit Algorithm ............................................. 73

DQ2: Toggle Bit II ...............................................................................................73

Reading Toggle Bits DQ6/DQ2 .....................................................................74

DQ5: Exceeded Timing Limits ........................................................................74

DQ3: Sector Erase Timer ................................................................................ 75

DQ1: Write-to-Buffer Abort ........................................................................... 75

Table 12. Write Operation Status .........................................76

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 76

Figure 7. Maximum Negative Overshoot Waveform................. 77

Figure 8. Maximum Positive

Overshoot Waveform.......................................................... 77

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 77

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 78

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 9. Test Setup........................................................... 79

Table 13. Test Specifications ...............................................79

Key to Switching Waveforms . . . . . . . . . . . . . . . . 79

Figure 10. Input Waveforms and Measurement Levels ............ 79

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 80

2

S71GL512_256_128NB0_00_A1 December 7, 2004

A d v a n c e I n f o r m a t i o n

Figure 28. Mode Register .................................................. 122

Read-Only Operations–S29GL512N Only ..................................................80

Read-Only Operations–S29GL256N Only .................................................. 81

Read-Only Operations–S29GL128N Only ..................................................82

Figure 11. Read Operation Timings....................................... 83

Figure 12. Page Read Timings.............................................. 83

Hardware Reset (RESET#) .............................................................................. 84

Figure 13. Reset Timings..................................................... 84

Erase and Program Operations–S29GL512N Only .................................. 85

Figure 29. Mode Register UpdateTimings (UB#, LB#, OE# are Don’t

Care) ............................................................................. 122

Figure 30. Deep Sleep Mode - Entry/Exit Timings (for 64M)... 123

Figure 31. Deep Sleep Mode - Entry/Exit Timings

(for 32M and 16M)........................................................... 123

pSRAM Type 7

Erase and Program Operations–S29GL256N Only .................................86

Erase and Program Operations–S29GL128N Only .................................. 87

Figure 14. Program Operation Timings.................................. 88

Figure 15. Accelerated Program Timing Diagram .................... 88

Figure 16. Chip/Sector Erase Operation Timings..................... 89

Figure 17. Data# Polling Timings

(During Embedded Algorithms)............................................ 90

Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 91

Figure 19. DQ2 vs. DQ6...................................................... 91

Alternate CE# Controlled Erase and Program Operations–

S29GL512N Only ................................................................................................ 92

Alternate CE# Controlled Erase and Program Operations–

S29GL256N Only ................................................................................................93

Alternate CE# Controlled Erase and Program Operations–

S29GL128N Only ................................................................................................ 94

Figure 20. Alternate CE# Controlled Write (Erase/Program)

Operation Timings.............................................................. 95

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 95

Erase And Programming Performance . . . . . . . 96

TSOP Pin and BGA Package Capacitance . . . . . 96

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Functional Description . . . . . . . . . . . . . . . . . . . . 128

Power Down ......................................................................................................128

Power Down Program Sequence ................................................................129

Address Key ........................................................................................................129

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 130

Package Capacitance . . . . . . . . . . . . . . . . . . . . . 130

Read Operation .................................................................................................132

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .134

Write Operation ...............................................................................................134

Power Down Parameters ...............................................................................135

Other Timing Parameters ............................................................................... 135

AC Test Conditions .........................................................................................136

AC Measurement Output Load Circuit .....................................................136

Figure 32. AC Output Load Circuit ...................................... 136

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .137

Read Timings ....................................................................................................... 137

Figure 33. Read Timing #1 (Baisc Timing)........................... 137

Figure 34. Read Timing #2 (OE# Address Access................. 137

Figure 35. Read Timing #3 (LB#/UB# Byte Access).............. 138

Figure 36. Read Timing #4 (Page Address Access after CE1# Control

Access for 32M and 64M Only)........................................... 138

Figure 37. Read Timing #5 (Random and Page Address Access for

32M and 64M Only).......................................................... 139

Write Timings ....................................................................................................139

Figure 38. Write Timing #1 (Basic Timing) .......................... 139

Figure 39. Write Timing #2 (WE# Control).......................... 140

Figure 40. Write Timing #3-1

pSRAM Type 1

Functional Description . . . . . . . . . . . . . . . . . . . . . 97

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 97

Timing Test Conditions . . . . . . . . . . . . . . . . . . . 103

Output Load Circuit ........................................................................................104

Figure 21. Output Load Circuit ........................................... 104

Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . 104

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 105

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 116

(WE#/LB#/UB# Byte Write Control)................................... 140

Figure 41. Write Timing #3-2

Read Cycle ...........................................................................................................116

Figure 22. Timing of Read Cycle (CE# = OE# = V_IL, WE# = ZZ# =

V_IH)................................................................................ 116

Figure 23. Timing Waveform of Read Cycle

(WE#/LB#/UB# Byte Write Control)................................... 141

Figure 42. Write Timing #3-3

(WE#/LB#/UB# Byte Write Control)................................... 141

Figure 43. Write Timing #3-4

(WE# = ZZ# = V_IH) ......................................................... 117

Figure 24. Timing Waveform of Page Mode Read Cycle (WE# = ZZ#

= V_IH) ............................................................................ 118

Write Cycle .........................................................................................................119

Figure 25. Timing Waveform of Write Cycle (WE# Control, ZZ# =

V_IH)................................................................................ 119

Figure 26. Timing Waveform of Write Cycle (CE# Control, ZZ# =

(WE#/LB#/UB# Byte Write Control)................................... 142

Read/Write Timings .........................................................................................142

Figure 44. Read/Write Timing #1-1 (CE1# Control).............. 142

Figure 45. Read / Write Timing #1-2

(CE1#/WE#/OE# Control) ................................................ 143

Figure 46. Read / Write Timing #2 (OE#, WE# Control)........ 143

Figure 47. Read / Write Timing #3

(OE#, WE#, LB#, UB# Control)......................................... 144

Figure 48. Power-up Timing #1 ......................................... 144

Figure 49. Power-up Timing #2 ......................................... 145

Figure 50. Power Down Entry and Exit Timing...................... 145

Figure 51. Standby Entry Timing after Read or Write............ 145

Figure 52. Power Down Program Timing (for 32M/64M Only). 146

V_IH)................................................................................ 119

Figure 27. Timing Waveform of Page Mode

Write Cycle (ZZ# = V_IH) ................................................... 120

Partial Array Self Refresh (PAR) ...................................................................120

Temperature Compensated Refresh (for 64Mb) .....................................121

Deep Sleep Mode ...............................................................................................121

Reduced Memory Size (for 32M and 16M) ..................................................121

Other Mode Register Settings (for 64M) ....................................................121

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 147

December 7, 2004 S71GL512_256_128NB0_00_A1

3

A d v a n c e I n f o r m a t i o n

Product Selector Guide

S71GL512NB0

Access Times at V = 2.7 - 3.1 V

Flash

pSRAM

65

CC

Max. Access Time (ns)

Max. CE# Access Time (ns)

Max. Page Access Time (t_PACC

Max. OE# Access Time (ns)

100

105

65

)

25

S71GL256NB0

Access Times at V = 2.7 - 3.1 V

Flash

pSRAM

65

CC

Max. Access Time (ns)

90

100

Max. CE# Access Time (ns)

65

Max. Page Access Time (t_PACC

)

25

Max. OE# Access Time (ns)

25

S71GL128NB0

Access Times at V = 2.7 - 3.1 V

Flash

pSRAM

65

CC

Max. Access Time (ns)

90

100

Max. CE# Access Time (ns)

65

Max. Page Access Time (t_PACC

)

25

Max. OE# Access Time (ns)

25

4

S71GL512_256_128NB0_00_A1 December 7, 2004

A d v a n c e I n f o r m a t i o n

MCP Block Diagram (128Mb Flash + 32Mb pSRAM)

V

f

CC

2

Flash-only Address

Shared Address

V

ID

CC

DQ15 to DQ0

21

16

DQ15 to DQ0

WP#/ACC

Flash

CE#F1

OE#

CE#

OE#

WE#

RESET#

RY/BY#

V

SS

V

s

CC

21

V

CCQ

V

CC

16

I/O15 to I/O0

WE#

OE#

pSRAM

UB#s

LB#s

CE2s

UB#

LB#

CE2s

CE1#s

V

SSQ

CE1#s

MCP Block Diagram (256Mb Flash + 32Mb pSRAM)

V

f

CC

3

Flash-only Address

Shared Address

V

CC ID

DQ15 to DQ0

21

16

DQ15 to DQ0

WP#/ACC

Flash

CE#F1

OE#

CE#

OE#

WE#

RESET#

RY/BY#

V

SS

V

s

CC

21

V

CCQ

CC

16

I/O15 to I/O0

WE#

OE#

pSRAM

UB#s

LB#s

CE2s

UB#

LB#

CE2s

CE1#s

V

SSQ

CE1#s

December 7, 2004 S71GL512_256_128NB0_00_A1

5

A d v a n c e I n f o r m a t i o n

MCP Block Diagram (512Mb Flash + 32Mb pSRAM)

V

f

CC

4

Flash-only Address

Shared Address

V

ID

CC

DQ15 to DQ0

21

16

DQ15 to DQ0

WP#/ACC

Flash

CE#F1

OE#

CE#

OE#

WE#

RESET#

RY/BY#

V

SS

V

s

CC

21

V

CCQ

V

CC

16

I/O15 to I/O0

WE#

OE#

pSRAM

UB#s

LB#s

CE2s

UB#

LB#

CE2s

CE1#s

V

SSQ

CE1#s

6

S71GL512_256_128NB0_00_A1 December 7, 2004

A d v a n c e I n f o r m a t i o n

Connection Diagrams

512 Mb Flash + 32 Mb pSRAM Pinout

84-ball Fine-Pitch Ball Grid Array

512 Mb Flash + 32 Mb pSRAM

Pinout

(Top View, Balls Facing Down)

Legend

A10

NC

A1

NC

B2

B3

RFU

C3

A7

D3

A6

E3

B4

RFU

C4

B5

RFU

C5

B6

RFU

C6

B7

RFU

C7

B8

RFU

C8

B9

RFU

C9

Shared

RFU

C2

RFU

D2

A3

Flash only

RFU

D9

LB#

D4

WP/ACC WE#

A8

A11

D8

D5

RST#f

E5

D6

CE2s

E6

D7

RAM only

UB#

E4

A19

E7

A12

E8

A15

E9

E2

Reserved for

Future Use

A2

F2

A1

G2

A0

A5

F3

A18

F4

RY/BY#

F5

A20

F6

A9

A13

F8

A21

F9

F7

A4

A17

G4

A10

G7

A14

G8

A22

G9

RFU

G5

A23

G6

G3

V_SS

DQ1

RFU

DQ6

A24

A16

H2

H3

H4

H5

H6

H7

H8

H9

CE#f1

OE#

DQ9

DQ3

DQ4

DQ13

DQ15

RFU

J9

J2

J3

J4

DQ10

K4

J5

J6

J7

J8

CE1#s

DQ0

V_CC

f

V_CC

s

DQ12

DQ7

V_SS

K2

K8

K3

K5

DQ11

L5

K7

K6

RFU

L6

K9

DQ14

DQ8

DQ2

DQ5

RFU

L2

L3

L4

L7

L8

L9

RFU

V_CC

f

RFU

M10

NC

M1

NC

December 7, 2004 S71GL512_256_128NB0_00_A1

7

A d v a n c e I n f o r m a t i o n

256 Mb Flash + 32 Mb pSRAM Pinout

84-ball Fine-Pitch Ball Grid Array

256 Mb Flash + 32 Mb pSRAM

Pinout

(Top View, Balls Facing Down)

Legend

A10

NC

A1

NC

B2

B3

RFU

C3

A7

D3

A6

E3

B4

RFU

C4

B5

RFU

C5

B6

RFU

C6

B7

RFU

C7

B8

RFU

C8

B9

RFU

C9

Shared

RFU

C2

RFU

D2

A3

Flash only

RFU

D9

LB#

D4

WP/ACC WE#

A8

A11

D8

D5

RST#f

E5

D6

CE2s

E6

D7

RAM only

UB#

E4

A19

E7

A12

E8

A15

E9

E2

Reserved for

Future Use

A2

F2

A1

G2

A0

A5

F3

A18

F4

RY/BY#

F5

A20

F6

A9

A13

F8

A21

F9

F7

A4

A17

G4

A10

G7

A14

G8

A22

G9

RFU

G5

A23

G6

G3

V_SS

DQ1

RFU

DQ6

RFU

A16

H2

H3

H4

H5

H6

H7

H8

H9

CE#f1

OE#

DQ9

DQ3

DQ4

DQ13

DQ15

RFU

J9

J2

J3

J4

DQ10

K4

J5

J6

J7

J8

CE1#s

DQ0

V_CC

f

V_CC

s

DQ12

DQ7

V_SS

K2

K8

K3

K5

DQ11

L5

K7

K6

RFU

L6

K9

DQ14

DQ8

DQ2

DQ5

RFU

L2

L3

L4

L7

L8

L9

RFU

V_CC

f

RFU

M10

NC

M1

NC

8

S71GL512_256_128NB0_00_A1 December 7, 2004

A d v a n c e I n f o r m a t i o n

128 Mb Flash + 32 Mb pSRAM Pinout

84-ball Fine-Pitch Ball Grid Array

128 Mb Flash + 32 Mb pSRAM

Pinout

(Top View, Balls Facing Down)

Legend

A10

NC

A1

NC

B2

B3

RFU

C3

A7

D3

A6

E3

B4

RFU

C4

B5

RFU

C5

B6

RFU

C6

B7

RFU

C7

B8

RFU

C8

B9

RFU

C9

Shared

RFU

C2

RFU

D2

A3

Flash only

RFU

D9

LB#

D4

WP/ACC WE#

A8

A11

D8

D5

RST#f

E5

D6

CE2s

E6

D7

RAM only

UB#

E4

A19

E7

A12

E8

A15

E9

E2

Reserved for

Future Use

A2

F2

A1

G2

A0

A5

F3

A18

F4

RY/BY#

F5

A20

F6

A9

A13

F8

A21

F9

F7

A4

A17

G4

A10

G7

A14

G8

A22

G9

RFU

G5

RFU

G6

G3

V_SS

DQ1

RFU

DQ6

RFU

A16

H2

H3

H4

H5

H6

H7

H8

H9

CE#f1

OE#

DQ9

DQ3

DQ4

DQ13

DQ15

RFU

J9

J2

J3

J4

DQ10

K4

J5

J6

J7

J8

CE1#s

DQ0

V_CC

f

V_CC

s

DQ12

DQ7

V_SS

K2

K8

K3

K5

DQ11

L5

K7

K6

RFU

L6

K9

DQ14

DQ8

DQ2

DQ5

RFU

L2

L3

L4

L7

L8

L9

RFU

V_CC

f

RFU

M10

NC

M1

NC

December 7, 2004 S71GL512_256_128NB0_00_A1

9

A d v a n c e I n f o r m a t i o n

128 Mb Flash + 32 Mb pSRAM Pinout (S71GL128NB0 Only)

64-ball Fine-Pitch Ball Grid Array

(Top View, Balls Facing Down)

A1

A10

NC

B5

RFU

B6

RFU

C6

Legend

Shared

C3

A7

C4

LB#

D4

C5

C7

A8

C8

A11

D8

WP/ACC

D5

WE#

D6

D2

A3

D9

A15

E9

D3

D7

A6

UB#

E4

RST#f

E5

CE2s

E6

A19

E7

A12

E8

E2

A2

E3

Flash only

RAM only

A5

A18

F4

RY/BY#

A20

A9

A13

F8

A21

F9

F2

F3

F7

A1

A4

A17

G4

A10

G7

A14

G8

A22

G9

G2

G3

VSS

H3

A0

DQ1

H4

DQ6

H7

RFU

H8

A16

H9

Reserved for

Future Use

H2

H5

DQ3

J5

H6

DQ4

J6

CE#f

J2

OE#

J3

DQ9

J4

DQ13

J7

DQ15

J8

RFU

J9

CE1#s

DQ0

K3

DQ10

K4

VCCf

K5

VCCs

K6

DQ12

K7

DQ7

K8

VSS

DQ8

DQ2

DQ11

RFU

DQ5

DQ14

L5

L6

RFU*

RFU

M1

NC

M10

NC

Note: Ball L5 (RFU) is a V_CCon an 84-ball package; therefore, it is recommended that L5 not be connected to V_SS

.

10

S71GL512_256_128NB0_00_A1 December 7, 2004

A d v a n c e I n f o r m a t i o n

Input/Output Descriptions

A24-A0

A23-A0

A22-A0

DQ15-DQ0

OE#

=

25 Address inputs (512 Mb)

24 Address inputs (256 Mb)

23 Address inputs (128 Mb)

Data input/output

Output Enable input. Asynchronous relative to CLK

for the Burst mode.

WE#

=

Write Enable input.

Ground

No Connect; not connected internally

Hardware reset input. Low = device resets and

returns to reading array data

V

SS

NC

RESET#

WP#/ACC

=

Hardware write protect input / programming

acceleration input.

CE1#s, CE2s

CE#f1

=

Chip-enable input for pSRAM.

Chip-enable input for Flash 1.

Flash 3.0 Volt-only single power supply.

pSRAM Power Supply.

Upper Byte Control (pSRAM).

Lower Byte Control (pSRAM).

Reserved for future use.

V

f

s

CC

UB#s

LB#s

RFU

RY/BY#

Ready/Busy output.

Logic Symbol

Max+1

A_Max*–A0

16

DQ15–DQ0

CE1#s

CE2s

OE#

WE#

WP#/ACC

WE#

RY/BY#

RESET#

UB#

LB#

CE#f1

*Max = A24

December 7, 2004 S71GL512_256_128NB0_00_A1

11

A d v a n c e I n f o r m a t i o n

Ordering Information

The order number (Valid Combination) is formed by the following:

S71GL

512

N

B0 BA

W

A

B

0

PACKING TYPE

0

2

3

=

Tray

7” Tape and Reel

13” Tape and Reel

MODEL NUMBER

Refer to the Valid Combinations Table

B

=

PACKAGE MODIFIER

A

E

9

=

1.2 mm height, 8 x 11.6 mm, 84 balls FBGA

1.2 mm height, 9 x 12.0 mm, 84 balls FBGA

1.2 mm height, 8 x 11.6 mm, 64 balls FBGA

TEMPERATURE RANGE

W

I

=

Wireless (-25

Industrial (-40

°

C to +85

°

C)

°C to +85

°C)

PACKAGE TYPE

BA

BF

=

Very Thin Fine-pitch BGA Lead (Pb)-free compliant package

Very Thin Fine-pitch BGA Lead (Pb)-free package

pSRAM DENSITY

B0 32 Mb pSRAM

=

PROCESS TECHNOLOGY

110 nm, MirrorBit^TMTechnology

N

=

FLASH DENSITY

512

256

128

=

512 Mb

256 Mb

128 Mb

PRODUCT FAMILY

S71GL Multi-chip Product (MCP)

3.0 Volt-only Uniform Sector Page Mode Flash Memory

12

S71GL512_256_128NB0_00_A1 December 7, 2004

A d v a n c e I n f o r m a t i o n

S71GL512NB0 Valid Combinations

Package

Modifier/

Model

(p)SRAM

Type/

Access

Base

Ordering

Part Number

Package &

Temperature

Flash

Address

Sector

Protection

Packing Initial/Page

(p)SRAM

Package

Type

Package

Marking

Number

Type

Speed (ns)

Supplier Time (ns)

EK

EP

EU

EZ

EJ

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Type 1

105/25

Type 7

65/25

Type 1

9mmx12mm

84-ball Lead

(Pb)-free

0, 2, 3

(Note 1)

S71GL512NB0

BAW

Compliant

EN

ET

EY

EK

EP

EU

EZ

EJ

100/25

105/25

100/25

Type 7

Type 1

(Note 2)

Type 7

65/25

Type 1

9mmx12mm

84-ball Lead

(Pb)-free

0, 2, 3

(Note 1)

S71GL512NB0

BFW

EN

ET

EY

Type 7

Notes:

Valid Combinations

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading “S” and packing type

designator from ordering part number.

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult your local sales office to confirm avail-

ability of specific valid combinations and to check on newly released

combinations.

December 7, 2004 S71GL512_256_128NB0_00_A1

13

A d v a n c e I n f o r m a t i o n

S71GL256NB0 Valid Combinations

Package

Flash

Initial/

Page

(p)SRAM

Base

Package &

Modifier/

Model

Address

Sector

Protection

Type/

Ordering

Part Number

Temperature

Packing

Type

(p)SRAM

Supplier

Access

Package

Number

Speed (ns)

Time (ns) Package Type Marking

AK

AP

AU

AZ

AJ

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Type 1

Type 7

Type 1

Type 7

Type 1

Type 7

Type 1

Type 7

100/25

90/25

8mmx11.6mm

0, 2, 3

(Note 1)

84-ball Lead

S71GL256NB0

BAW

65/25

(Pb)-free

Compliant

AN

AT

AY

AK

AP

AU

AZ

AJ

(Note 2)

100/25

90/25

8mmx11.6mm

84-ball Lead

(Pb)-free

0, 2, 3

(Note 1)

S71GL256NB0

BFW

65/25

AN

AT

AY

Notes:

Valid Combinations

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading “S” and packing type

designator from ordering part number.

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult your local sales office to confirm avail-

ability of specific valid combinations and to check on newly released

combinations.

14

S71GL512_256_128NB0_00_A1 December 7, 2004

A d v a n c e I n f o r m a t i o n

S71GL128NB0 Valid Combinations

Flash

Initial/

Page

Speed

(ns)

Package

Modifier/

Model

(p)SRAM

Type/

Access

Base

Ordering

Part Number

Package &

Temperature

Address

Sector

Protection

Packing

Type

(p)SRAM

Package

Marking

Number

Supplier Time (ns) Package Type

9K

9P

9U

9Z

9J

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Lowest Add

Highest Add

Type 1

100/25

90/25

Type 7

Type 1

Type 7

Type 1

Type 7

Type 1

Type 7

Type 1

Type 7

Type 1

Type 7

Type 1

Type 7

Type 1

Type 7

8mmx11.6mm

64-ball Lead

(Pb)-free

Compliant

9N

9T

9Y

AK

AP

AU

AZ

AJ

0, 2, 3

S71GL128NB0

BAW

65/25

(Note 1)

100/25

90/25

8mmx11.6mm

84-ball Lead

(Pb)-free

Compliant

AN

AT

AY

9K

9P

9U

9Z

9J

(Note 2)

100/25

90/25

8mmx11.6mm

64-ball Lead

(Pb)-free

Compliant

9N

9T

9Y

AK

AP

AU

AZ

AJ

0, 2, 3

(Note 1)

S71GL128NB0

BFW

65/25

100/25

90/25

8mmx11.6mm

84-ball Lead

(Pb)-free

AN

AT

AY

Notes:

Valid Combinations

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading “S” and packing type

designator from ordering part number.

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult your local sales office to confirm avail-

ability of specific valid combinations and to check on newly released

combinations.

December 7, 2004 S71GL512_256_128NB0_00_A1

15

A d v a n c e I n f o r m a t i o n

Physical Dimensions

TLD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 9.0 x 12.0 x1.2 mm MCP

Compatible Package

A

D1

D

eD

0.15

(2X)

C

10

9

8

SE

7

6

E

B

E1

5

4

3

2

1

eE

J

H

G

F

E

D

C

B

A

M

L K

INDEX MARK

10

PIN A1

CORNER

PIN A1

CORNER

7

SD

0.15

(2X)

C

TOP VIEW

BOTTOM VIEW

0.20

C

A2

A

0.08

C

A1

SIDE VIEW

6

84X

b

0.15

0.08

M

C

A

B

M

NOTES:

PACKAGE

JEDEC

TLD 084

N/A

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

D x E

12.00 mm x 9.00 mm

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

SYMBOL

MIN

NOM

---

MAX

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

---

1.20

---

PROFILE

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

0.17

0.81

---

BALL HEIGHT

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

---

0.97

BODY THICKNESS

BODY SIZE

12.00 BSC.

9.00 BSC.

8.80 BSC.

7.20 BSC.

12

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

E

BODY SIZE

D1

E1

MD

ME

n

MATRIX FOOTPRINT

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

10

84

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

b

0.35

0.40

0.45

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

eE

eD

SD / SE

0.80 BSC.

0.80 BSC

0.40 BSC.

BALL PITCH

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

SOLDER BALL PLACEMENT

A2,A3,A4,A5,A6,A7,A8,A9

B1,B10,C1,C10,D1,D10

E1,E10,F1,F10,G1,G10

H1,H10,J1,J10,K1,K10

L1,L10,M2,M3,M4,M5,M6,

M7,M8,M9

DEPOPULATED SOLDER BALLS

9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3367\ 16-038.22a

Note: BSC is an ANSI standard for Basic Space Centering

16

S71GL512_256_128NB0_00_A1 December 7, 2004

A d v a n c e I n f o r m a t i o n

TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 11.6 x1.2 mm MCP

Compatible Package

A

D1

D

eD

0.15

(2X)

C

10

9

8

SE

7

6

E

B

E1

5

4

3

2

1

eE

J

H

G

F

E

D

C

B

A

M

L K

INDEX MARK

10

PIN A1

CORNER

PIN A1

CORNER

7

SD

0.15

(2X)

C

TOP VIEW

BOTTOM VIEW

0.20

C

A2

A

0.08

C

A1

SIDE VIEW

6

84X

b

0.15

0.08

M

C

A

B

M

NOTES:

PACKAGE

JEDEC

TLA 084

N/A

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

D x E

11.60 mm x 8.00 mm

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

SYMBOL

MIN

---

NOM

---

MAX

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

1.20

---

PROFILE

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

0.17

0.81

---

BALL HEIGHT

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

A2

---

0.97

BODY THICKNESS

BODY SIZE

D

11.60 BSC.

8.00 BSC.

8.80 BSC.

7.20 BSC.

12

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

E

BODY SIZE

D1

MATRIX FOOTPRINT

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

E1

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

MD

ME

n

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

10

84

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

Ø b

eE

0.35

0.40

0.45

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

0.80 BSC.

0.80 BSC

0.40 BSC.

BALL PITCH

eD

BALL PITCH

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

SD / SE

SOLDER BALL PLACEMENT

A2,A3,A4,A5,A6,A7,A8,A9

B1,B10,C1,C10,D1,D10,

E1,E10,F1,F10,G1,G10,

H1,H10,J1,J10,K1,K10,L1,L10,

M2,M3,M4,M5,M6,M7,M8,M9

DEPOPULATED SOLDER BALLS

9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3372-2 \ 16-038.22a

Note: BSC is an ANSI standard for Basic Space Centering

December 7, 2004 S71GL512_256_128NB0_00_A1

17

A d v a n c e I n f o r m a t i o n

TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 11.6 x1.2 mm MCP

Compatible Package

A

D1

D

eD

0.15

(2X)

C

10

9

8

7

6

5

4

3

2

1

SE

7

E

E1

eE

L

J

H

G

F

E

D

C

B

A

M

K

INDEX MARK

10

PIN A1

CORNER

B

CORNER

7

SD

0.15

(2X)

C

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.20

0.08

C

A2

A

C

A1

6

64X

b

0.15

0.08

M

C

A B

M

NOTES:

PACKAGE

JEDEC

TLA 064

N/A

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

D x E

11.60 mm x 8.00 mm

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

SYMBOL

MIN

---

NOM

---

MAX

1.20

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

PROFILE

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

0.17

0.81

---

BALL HEIGHT

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

A2

---

0.97

BODY THICKNESS

BODY SIZE

D

11.60 BSC.

8.00 BSC.

8.80 BSC.

7.20 BSC.

12

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

E

BODY SIZE

D1

E1

MATRIX FOOTPRINT

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

MD

ME

n

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

10

64

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

φb

0.35

0.40

0.45

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

eE

0.80 BSC.

0.80 BSC

0.40 BSC.

BALL PITCH

eD

SD / SE

BALL PITCH

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

A2,A3,A4,A5,A6,A7,A8,A9

B1,B2,B3,B4,B7,B8,B9,B10

C1,C2,C9,C10,D1,D10,E1,E10,

F1,F5,F6,F10,G1,G5,G6,G10

H1,H10,J1,J10,K1,K2,K9,K10

L1,L2,L3,L4,L7,L8,L9,L10

9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

M2,M3,M4,M5,M6,M7,M8,M9

3352 \ 16-038.22a

Note: BSC is an ANSI standard for Basic Space Centering.

18

S71GL512_256_128NB0_00_A1 December 7, 2004

S29GLxxxN MirrorBit^TMFlash Family

S29GL512N, S29GL256N, S29GL128N

512 Megabit, 256 Megabit, and 128 Megabit,

3.0 Volt-only Page Mode Flash Memory featuring

110 nm MirrorBit process technology

ADVANCE

INFORMATION

Datasheet

Distinctive Characteristics

—

80 ns access time (S29GL128N, S29GL256N),

90 ns access time (S29GL512N)

8-word/16-byte page read buffer

25 ns page read times

16-word/32-byte write buffer reduces overall

programming time for multiple-word updates

Architectural Advantages

Single power supply operation

3 volt read, erase, and program operations

Enhanced VersatileI/O™ control

—

All input levels (address, control, and DQ input levels)

and outputs are determined by voltage on V_IOinput.

Low power consumption (typical values at 3.0 V, 5

MHz)

V

_IOrange is 1.65 to V_CC

Manufactured on 110 nm MirrorBit process

technology

—

25 mA typical active read current;

50 mA typical erase/program current

1 µA typical standby mode current

Secured Silicon Sector region

—

128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random

Electronic Serial Number, accessible through a

command sequence

May be programmed and locked at the factory or by

the customer

Software & Hardware Features

Software features

—

Program Suspend & Resume: read other sectors

before programming operation is completed

Erase Suspend & Resume: read/program other

sectors before an erase operation is completed

Data# polling & toggle bits provide status

Unlock Bypass Program command reduces overall

multiple-word or byte programming time

CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

—

Flexible sector architecture

—

S29GL512N: Five hundred twelve 64 Kword (128

Kbyte) sectors

S29GL256N: Two hundred fifty-six 64 Kword (128

Kbyte) sectors

—

S29GL128N: One hundred twenty-eight 64 Kword

(128 Kbyte) sectors

Hardware features

Compatibility with JEDEC standards

—

Advanced Sector Protection

Provides pinout and software compatibility for single-

power supply flash, and superior inadvertent write

protection

WP#/ACC input accelerates programming time

(when high voltage is applied) for greater throughput

during system production. Protects first or last sector

regardless of sector protection settings

Hardware reset input (RESET#) resets device

Ready/Busy# output (RY/BY#) detects program or

erase cycle completion

100,000 erase cycles per sector typical

20-year data retention typical

—

Performance Characteristics

High performance

Publication Number S29GLxxxN_00 Revision A Amendment 4 Issue Date June 14, 2004

This document contains information on a product under development at Spansion LLC. The information is intended to help you evaluate this product. Spansion LLC

reserves the right to change or discontinue work on this proposed product without notice.

A d v a n c e I n f o r m a t i o n

General Description

The GL512/256/128N family of devices are 3.0V single power flash memory man-

ufactured using 110 nm MirrorBit technology. The GL512N is a 512 Mbit,

organized as 33,554,432 words or 67,108,864 bytes. The GL256N is a 256 Mbit,

organized as 16,777,216 words or 33,554,432 bytes. The GL128N is a 128 Mbit,

organized as 8,388,608 words or 16,777,216 bytes. The devices have a 16-bit

wide data bus that can also function as an 8-bit wide data bus by using the BYTE#

input. The device can be programmed either in the host system or in standard

EPROM programmers.

Access times as fast as 90 ns (GL128N, GL256N) or 100 ns (GL512N) are

available.

Each device requires only a single 3.0 volt power supply for both read and

write functions. In addition to a V input, a high-voltage accelerated program

CC

(WP#/ACC) input provides shorter programming times through increased cur-

rent. This feature is intended to facilitate factory throughput during system

production, but may also be used in the field if desired.

The devices are entirely command set compatible with the JEDEC single-

power-supply Flash standard. Commands are written to the device using

standard microprocessor write timing. Write cycles also internally latch addresses

and data needed for the programming and erase operations.

The sector erase architecture allows memory sectors to be erased and repro-

grammed without affecting the data contents of other sectors. The device is fully

erased when shipped from the factory.

Device programming and erasure are initiated through command sequences.

Once a program or erase operation has begun, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#

(RY/BY#) output to determine whether the operation is complete. To facilitate

programming, an Unlock Bypass mode reduces command sequence overhead

by requiring only two write cycles to program data instead of four.

Hardware data protection measures include a low V detector that automat-

CC

ically inhibits write operations during power transitions. Persistent Sector

Protection provides in-system, command-enabled protection of any combina-

tion of sectors using a single power supply at V . Password Sector Protection

CC

prevents unauthorized write and erase operations in any combination of sectors

through a user-defined 64-bit password.

The Erase Suspend/Erase Resume feature allows the host system to pause an

erase operation in a given sector to read or program any other sector and then

complete the erase operation. The Program Suspend/Program Resume fea-

ture enables the host system to pause a program operation in a given sector to

read any other sector and then complete the program operation.

The hardware RESET# pin terminates any operation in progress and resets the

device, after which it is then ready for a new operation. The RESET# pin may be

tied to the system reset circuitry. A system reset would thus also reset the device,

enabling the host system to read boot-up firmware from the Flash memory

device.

The device reduces power consumption in the standby mode when it detects

specific voltage levels on CE# and RESET#, or when addresses have been stable

for a specified period of time.

20

S29GLxxxN MirrorBit^TMFlash Family

S29GLxxxN_00_A4 June 14, 2004

A d v a n c e I n f o r m a t i o n

The Secured Silicon Sector provides a 128-word/256-byte area for code or

data that can be permanently protected. Once this sector is protected, no further

changes within the sector can occur.

The Write Protect (WP#/ACC) feature protects the first or last sector by as-

serting a logic low on the WP# pin.

MirrorBit flash technology combines years of Flash memory manufacturing expe-

rience to produce the highest levels of quality, reliability and cost effectiveness.

The device electrically erases all bits within a sector simultaneously via hot-hole

assisted erase. The data is programmed using hot electron injection.

June 14, 2004 S29GLxxxN_00_A4

S29GLxxxN MirrorBit^TMFlash Family

21

A d v a n c e I n f o r m a t i o n

Block Diagram

DQ15–DQ0 (A-1)

RY/BY#

V_CC

V_SS

V_IO

Sector Switches

Erase Voltage

Generator

Input/Output

Buffers

RESET#

WE#

WP#/ACC

BYTE#

State

Control

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

X-Decoder

A_Max**–A0

June 14, 2004 S29GLxxxN_00A4

S29GLxxxN MirrorBit^TMFlash Family

22

A d v a n c e I n f o r m a t i o n

Device Bus Operations

This section describes the requirements and use of the device bus operations,

which are initiated through the internal command register. The command register

itself does not occupy any addressable memory location. The register is a latch

used to store the commands, along with the address and data information

needed to execute the command. The contents of the register serve as inputs to

the internal state machine. The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the inputs and control levels they

require, and the resulting output. The following subsections describe each of

these operations in further detail.

Table 1. Device Bus Operations

DQ8–DQ15

BYTE# BYTE#

WE

#

Addresses

(Note 2)

DQ0–

DQ7

Operation

CE# OE#

RESET#

WP#

ACC

= V = V

IH

IL

Read

L

H

L

H

X

A_IN

D_OUT

(Note

3)

DQ8–DQ14

= High-Z,

DQ15 = A-1

Write (Program/Erase)

Accelerated Program

Standby

H

(Note 2)

X

(Note 3)

(Note

3)

L

H

X

L

(Note 2) V_HH

A_IN

X

(Note 3)

V_CC

0.3 V

±

V_CC

0.3 V

±

X

H

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 11.5–12.5 V, V_HH= 11.5–12.5V, X = Don’t Care, SA = Sector

Address, A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are AMax:A0 in word mode; A_Max:A-1 in byte mode. Sector addresses are A_Max:A16 in both modes.

2. If WP# = V , the first or last sector group remains protected. If WP# = V , the first or last sector will be

IL

IH

protected or unprotected as determined by the method described in “Write Protect (WP#)”. All sectors are

unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending

on version ordered.)

3. D_INor D_OUTas required by command sequence, data polling, or sector protect algorithm (see Figure 2).

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins operate in the byte or

word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con-

figuration, DQ0–DQ15 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only

data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/

O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the

LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE#

pins to V . CE# is the power control and selects the device. OE# is the output

IL

control and gates array data to the output pins. WE# should remain at V .

IH

June 14, 2004 S29GLxxxN_00A4

S29GLxxxN MirrorBit^TMFlash Family

23

A d v a n c e I n f o r m a t i o n

The internal state machine is set for reading array data upon device power-up,

or after a hardware reset. This ensures that no spurious alteration of the memory

content occurs during the power transition. No command is necessary in this

mode to obtain array data. Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid data on the device data

outputs. The device remains enabled for read access until the command register

contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read-Only Op-

erations table for timing specifications and to Figure 11 for the timing diagram.

Refer to the DC Characteristics table for the active current specification on read-

ing array data.

Page Mode Read

The device is capable of fast page mode read and is compatible with the page

mode Mask ROM read operation. This mode provides faster read access speed for

random locations within a page. The page size of the device is 8 words/16 bytes.

The appropriate page is selected by the higher address bits A(max)–A3. Address

bits A2–A0 in word mode (A2–A-1 in byte mode) determine the specific word

within a page. This is an asynchronous operation; the microprocessor supplies

the specific word location.

The random or initial page access is equal to t

or t and subsequent page

CE

ACC

read accesses (as long as the locations specified by the microprocessor falls

within that page) is equivalent to t . When CE# is de-asserted and reasserted

PACC

for a subsequent access, the access time is t

or t . Fast page mode accesses

CE

ACC

are obtained by keeping the “read-page addresses” constant and changing the

“intra-read page” addresses.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data

to the device and erasing sectors of memory), the system must drive WE# and

CE# to V , and OE# to V .

IL

IH

The device features an Unlock Bypass mode to facilitate faster programming.

Once the device enters the Unlock Bypass mode, only two write cycles are re-

quired to program a word or byte, instead of four. The “Word/Byte Program

Command Sequence” section has details on programming data to the device

using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device.

Table 2 indicates the address space that each sector occupies.

Refer to the DC Characteristics table for the active current specification for the

write mode. The AC Characteristics section contains timing specification tables

and timing diagrams for write operations.

Write Buffer

Write Buffer Programming allows the system write to a maximum of 16 words/32

bytes in one programming operation. This results in faster effective programming

time than the standard programming algorithms. See “Write Buffer” for more

information.

24

S29GLxxxN MirrorBit^TMFlash Family

S29GLxxxN_00_A4 June 14, 2004

A d v a n c e I n f o r m a t i o n

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This

is one of two functions provided by the WP#/ACC pin. This function is primarily

intended to allow faster manufacturing throughput at the factory.

If the system asserts V

on this pin, the device automatically enters the afore-

HH

mentioned Unlock Bypass mode, temporarily unprotects any protected sector

groups, and uses the higher voltage on the pin to reduce the time required for

program operations. The system would use a two-cycle program command se-

quence as required by the Unlock Bypass mode. Removing V

from the WP#/

HH

ACC pin returns the device to normal operation. Note that the WP#/ACC pin must

not be at V for operations other than accelerated programming, or device dam-

HH

age may result. WP# has an internal pullup; when unconnected, WP# is at V

.

IH

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the au-

toselect mode. The system can then read autoselect codes from the internal

register (which is separate from the memory array) on DQ7–DQ0. Standard read

cycle timings apply in this mode. Refer to the “Autoselect Command Sequence”

section on page 50 sections for more information.

Standby Mode

When the system is not reading or writing to the device, it can place the device

in the standby mode. In this mode, current consumption is greatly reduced, and

the outputs are placed in the high impedance state, independent of the OE#

input.

The device enters the CMOS standby mode when the CE# and RESET# pins are

both held at V ± 0.3 V. (Note that this is a more restricted voltage range than

IO

V .) If CE# and RESET# are held at V , but not within V ± 0.3 V, the device

IH

IO

will be in the standby mode, but the standby current will be greater. The device

requires standard access time (t ) for read access when the device is in either

CE

of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-

tive current until the operation is completed.

Refer to the “DC Characteristics” section on page 78 for the standby current

specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de-

vice automatically enables this mode when addresses remain stable for t

+

ACC

30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-

trol signals. Standard address access timings provide new data when addresses

are changed. While in sleep mode, output data is latched and always available to

the system. Refer to the “DC Characteristics” section on page 78 for the

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading

array data. When the RESET# pin is driven low for at least a period of t , the

RP

device immediately terminates any operation in progress, tristates all output

pins, and ignores all read/write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to reading array data. The op-

June 14, 2004 S29GLxxxN_00_A4

S29GLxxxN MirrorBit^TMFlash Family

25

A d v a n c e I n f o r m a t i o n

eration that was interrupted should be reinitiated once the device is ready to

accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held

at V ±0.3 V, the device draws CMOS standby current (I

). If RESET# is held

SS

CC5

at V but not within V ±0.3 V, the standby current will be greater.

IL

SS

The RESET# pin may be tied to the system reset circuitry. A system reset would

thus also reset the Flash memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

Refer to the AC Characteristics tables for RESET# parameters and to Figure 13

for the timing diagram.

Output Disable Mode

When the OE# input is at V , output from the device is disabled. The output pins

IH

are placed in the high impedance state.

Table 2. Sector Address Table–S29GL256N

8-bit

16-bit

Sector Size

(Kbytes/

Kwords)

Address Range

Sector

A23–A16

(in hexadecimal)

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

128/64

0000000–001FFFF

0020000–003FFFF

0040000–005FFFF

0060000–007FFFF

0080000–009FFFF

00A0000–00BFFFF

00C0000–00DFFFF

00E0000–00FFFFF

0100000–011FFFF

0120000–013FFFF

0140000–015FFFF

0160000–017FFFF

0180000–019FFFF

01A0000–01BFFFF

01C0000–01DFFFF

01E0000–01FFFFF

0200000–021FFFF

0220000–023FFFF

0240000–025FFFF

0260000–027FFFF

0280000–029FFFF

02A0000–02BFFFF

02C0000–02DFFFF

0000000–000FFFF

0010000–001FFFF

0020000–002FFFF

0030000–003FFFF

0040000–004FFFF

0050000–005FFFF

0060000–006FFFF

0070000–007FFFF

0080000–008FFFF

0090000–009FFFF

00A0000–00AFFFF

00B0000–00BFFFF

00C0000–00CFFFF

00D0000–00DFFFF

00E0000–00EFFFF

00F0000–00FFFFF

0100000–010FFFF

0110000–011FFFF

0120000–012FFFF

0130000–013FFFF

0140000–014FFFF

0150000–015FFFF

0160000–016FFFF

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

26

S29GLxxxN MirrorBit^TMFlash Family

S29GLxxxN_00_A4 June 14, 2004

A d v a n c e I n f o r m a t i o n

Table 2. Sector Address Table–S29GL256N (Continued)

8-bit

Sector Size

16-bit

Address Range

(in hexadecimal)

Address Range

(Kbytes/

Sector

A23–A16

(in hexadecimal)

Kwords)

128/64

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

02E0000–02FFFFF

0300000–031FFFF

0320000–033FFFF

0340000–035FFFF

0360000–037FFFF

0380000–039FFFF

03A0000–03BFFFF

03C0000–03DFFFF

03E0000–03FFFFF

0400000–041FFFF

0420000–043FFFF

0440000–045FFFF

0460000–047FFFF

0480000–049FFFF

04A0000–04BFFFF

04C0000–04DFFFF

04E0000–04FFFFF

0500000–051FFFF

0520000–053FFFF

0540000–055FFFF

0560000–057FFFF

0580000–059FFFF

05A0000–05BFFFF

05C0000–05DFFFF

05E0000–05FFFFF

0600000–061FFFF

0620000–063FFFF

0640000–065FFFF

0660000–067FFFF

0680000–069FFFF

06A0000–06BFFFF

06C0000–06DFFFF

06E0000–06FFFFF

0170000–017FFFF

0180000–018FFFF

0190000–019FFFF

01A0000–01AFFFF

01B0000–01BFFFF

01C0000–01CFFFF

01D0000–01DFFFF

01E0000–01EFFFF

01F0000–01FFFFF

0200000–020FFFF

0210000–021FFFF

0220000–022FFFF

0230000–023FFFF

0240000–024FFFF

0250000–025FFFF

0260000–026FFFF

0270000–027FFFF

0280000–028FFFF

0290000–029FFFF

02A0000–02AFFFF

02B0000–02BFFFF

02C0000–02CFFFF

02D0000–02DFFFF

02E0000–02EFFFF

02F0000–02FFFFF

0300000–030FFFF

0310000–031FFFF

0320000–032FFFF

0330000–033FFFF

0340000–034FFFF

0350000–035FFFF

0360000–036FFFF

0370000–037FFFF

SA56

SA57

0

1

0

1

128/64

0380000–038FFFF

0390000–039FFFF

0700000–071FFFF

0720000–073FFFF

June 14, 2004 S29GLxxxN_00_A4

S29GLxxxN MirrorBit^TMFlash Family

27

A d v a n c e I n f o r m a t i o n

Table 2. Sector Address Table–S29GL256N (Continued)

8-bit

Sector Size

16-bit

Address Range

(in hexadecimal)

Address Range

(Kbytes/

Sector

A23–A16

(in hexadecimal)

Kwords)

128/64

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0740000–075FFFF

0760000–077FFFF

0780000–079FFFF

07A0000–7BFFFF

07C0000–07DFFFF

07E0000–07FFFFF0

0800000–081FFFF

0820000–083FFFF

0840000–085FFFF

0860000–087FFFF

0880000–089FFFF

08A0000–08BFFFF

08C0000–08DFFFF

08E0000–08FFFFF

0900000–091FFFF

0920000–093FFFF

0940000–095FFFF

0960000–097FFFF

0980000–099FFFF

09A0000–09BFFFF

09C0000–09DFFFF

09E0000–09FFFFF

0A00000–0A1FFFF

0A20000–0A3FFFF

0A40000–045FFFF

0A60000–0A7FFFF

0A80000–0A9FFFF

0AA0000–0ABFFFF

0AC0000–0ADFFFF

0AE0000–AEFFFFF

0B00000–0B1FFFF

0B20000–0B3FFFF

0B40000–0B5FFFF

0B60000–0B7FFFF

0B80000–0B9FFFF

03A0000–03AFFFF

03B0000–03BFFFF

03C0000–03CFFFF

03D0000–03DFFFF

03E0000–03EFFFF

03F0000–03FFFFF

0400000–040FFFF

0410000–041FFFF

0420000–042FFFF

0430000–043FFFF

0440000–044FFFF

0450000–045FFFF

0460000–046FFFF

0470000–047FFFF

0480000–048FFFF

0490000–049FFFF

04A0000–04AFFFF

04B0000–04BFFFF

04C0000–04CFFFF

04D0000–04DFFFF

04E0000–04EFFFF

04F0000–04FFFFF

0500000–050FFFF

0510000–051FFFF

0520000–052FFFF

0530000–053FFFF

0540000–054FFFF

0550000–055FFFF

0560000–056FFFF

0570000–057FFFF

0580000–058FFFF

0590000–059FFFF

05A0000–05AFFFF

05B0000–05BFFFF

05C0000–05CFFFF

28

S29GLxxxN MirrorBit^TMFlash Family

S29GLxxxN_00_A4 June 14, 2004

A d v a n c e I n f o r m a t i o n

Table 2. Sector Address Table–S29GL256N (Continued)

8-bit

Sector Size

16-bit

Address Range

(in hexadecimal)

Address Range

(Kbytes/

Sector

A23–A16

(in hexadecimal)

Kwords)

128/64

SA93

SA94

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0BA0000–0BBFFFF

0BC0000–0BDFFFF

0BE0000–0BFFFFF

0C00000–0C1FFFF

0C20000–0C3FFFF

0C40000–0C5FFFF

0C60000–0C7FFFF

0C80000–0C9FFFF

0CA0000–0CBFFFF

0CC0000–0CDFFFF

0CE0000–0CFFFFF

0D00000–0D1FFFF

0D20000–0D3FFFF

0D40000–0D5FFFF

0D60000–0D7FFFF

0D80000–0D9FFFF

0DA0000–0DBFFFF

0DC0000–0DDFFFF

0DE0000–0DFFFFF

0E00000–0E1FFFF

0E20000–0E3FFFF

0E40000–0E5FFFF

0E60000–0E7FFFF

0E80000–0E9FFFF

0EA0000–0EBFFFF

0EC0000–0EDFFFF

0EE0000–0EFFFFF

0F00000–0F1FFFF

0F20000–0F3FFFF

0F40000–0F5FFFF

0F60000–0F7FFFF

0F80000–0F9FFFF

0FA0000–0FBFFFF

0FC0000–0FDFFFF

0FE0000–0FFFFFF

05D0000–05DFFFF

05E0000–05EFFFF

05F0000–05FFFFF

0600000–060FFFF

0610000–061FFFF

0620000–062FFFF

0630000–063FFFF

0640000–064FFFF

0650000–065FFFF

0660000–066FFFF

0670000–067FFFF

0680000–068FFFF

0690000–069FFFF

06A0000–06AFFFF

06B0000–06BFFFF

06C0000–06CFFFF

06D0000–06DFFFF

06E0000–06EFFFF

06F0000–06FFFFF

0700000–070FFFF

0710000–071FFFF

0720000–072FFFF

0730000–073FFFF

0740000–074FFFF

0750000–075FFFF

0760000–076FFFF

0770000–077FFFF

0780000–078FFFF

0790000–079FFFF

07A0000–07AFFFF

07B0000–07BFFFF

07C0000–07CFFFF

07D0000–07DFFFF

07E0000–07EFFFF

07F0000–07FFFFF

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

June 14, 2004 S29GLxxxN_00_A4

S29GLxxxN MirrorBit^TMFlash Family

29

A d v a n c e I n f o r m a t i o n

Table 2. Sector Address Table–S29GL256N (Continued)

8-bit

Sector Size

16-bit

Address Range

(in hexadecimal)

Address Range

(Kbytes/

Sector

A23–A16

(in hexadecimal)

Kwords)

128/64

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

SA142

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

SA159

SA160

SA161

SA162

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1000000–101FFFF

1020000–103FFFF

1040000–105FFFF

1060000–107FFFF

1080000–109FFFF

10A0000–10BFFFF

10C0000–10DFFFF

10E0000–10FFFFF

1100000–111FFFF

1120000–113FFFF

1140000–115FFFF

1160000–117FFFF

1180000–119FFFF

11A0000–11BFFFF

11C0000–11DFFFF

11E0000–11FFFFF

1200000–121FFFF

1220000–123FFFF

1240000–125FFFF

1260000–127FFFF

1280000–129FFFF

12A0000–12BFFFF

12C0000–12DFFFF

12E0000–12FFFFF

1300000–131FFFF

1320000–133FFFF

1340000–135FFFF

1360000–137FFFF

1380000–139FFFF

13A0000–13BFFFF

13C0000–13DFFFF

13E0000–13FFFFF

1400000–141FFFF

1420000–143FFFF

1440000–145FFFF

0800000–080FFFF

0810000–081FFFF

0820000–082FFFF

0830000–083FFFF

0840000–084FFFF

0850000–085FFFF

0860000–086FFFF

0870000–087FFFF

0880000–088FFFF

0890000–089FFFF

08A0000–08AFFFF

08B0000–08BFFFF

08C0000–08CFFFF

08D0000–08DFFFF

08E0000–08EFFFF

08F0000–08FFFFF

0900000–090FFFF

0910000–091FFFF

0920000–092FFFF

0930000–093FFFF

0940000–094FFFF

0950000–095FFFF

0960000–096FFFF

0970000–097FFFF

0980000–098FFFF

0990000–099FFFF

09A0000–09AFFFF

09B0000–09BFFFF

09C0000–09CFFFF

09D0000–09DFFFF

09E0000–09EFFFF

09F0000–09FFFFF

0A00000–0A0FFFF

0A10000–0A1FFFF

0A20000–0A2FFFF

30

S29GLxxxN MirrorBit^TMFlash Family

S29GLxxxN_00_A4 June 14, 2004

A d v a n c e I n f o r m a t i o n

Table 2. Sector Address Table–S29GL256N (Continued)

8-bit

Sector Size

16-bit

Address Range

(in hexadecimal)

Address Range

(Kbytes/

Sector

A23–A16

(in hexadecimal)

Kwords)

128/64

SA163

SA164

SA165

SA166

SA167

SA168

SA169

SA170

SA171

SA172

SA173

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

SA185

SA186

SA187

SA188

SA189

SA190

SA191

SA192

SA193

SA194

SA195

SA196

SA197

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1460000–147FFFF

1480000–149FFFF

14A0000–14BFFFF

14C0000–14DFFFF

14E0000–14FFFFF

1500000–151FFFF

1520000–153FFFF

1540000–155FFFF

1560000–157FFFF

1580000–159FFFF

15A0000–15BFFFF

15C0000–15DFFFF

15E0000–15FFFFF

1600000–161FFFF

1620000–163FFFF

1640000–165FFFFF

1660000–167FFFF

1680000–169FFFF

16A0000–16BFFFF

16C0000–16DFFFF

16E0000–16FFFFF

1700000–171FFFF

1720000–173FFFF

1740000–175FFFF

1760000–177FFFF

1780000–179FFFF

17A0000–17BFFFF

17C0000–17DFFFF

17E0000–17FFFFF

1800000–181FFFF

1820000–183FFFF

1840000–185FFFF

1860000–187FFFF

1880000–189FFFF

18A0000–18BFFFF

0A30000–0A3FFFF

0A40000–0A4FFFF

0A50000–0A5FFFF

0A60000–0A6FFFF

0A70000–0A7FFFF

0A80000–0A8FFFF

0A90000–0A9FFFF

0AA0000–0AAFFFF

0AB0000–0ABFFFF

0AC0000–0ACFFFF

0AD0000–0ADFFFF

0AE0000–0AEFFFF

0AF0000–0AFFFFF

0B00000–0B0FFFF

0B10000–0B1FFFF

0B20000–0B2FFFF

0B30000–0B3FFFF

0B40000–0B4FFFF

0B50000–0B5FFFF

0B60000–0B6FFFF

0B70000–0B7FFFF

0B80000–0B8FFFF

0B90000–0B9FFFF

0BA0000–0BAFFFF

0BB0000–0BBFFFF

0BC0000–0BCFFFF

0BD0000–0BDFFFF

0BE0000–0BEFFFF

0BF0000–0BFFFFF

0C00000–0C0FFFF

0C10000–0C1FFFF

0C20000–0C2FFFF

0C30000–0C3FFFF

0C40000–0C4FFFF

0C50000–0C5FFFF

June 14, 2004 S29GLxxxN_00_A4

S29GLxxxN MirrorBit^TMFlash Family

31

A d v a n c e I n f o r m a t i o n

Table 2. Sector Address Table–S29GL256N (Continued)

8-bit

Sector Size

16-bit

Address Range

(in hexadecimal)

Address Range

(Kbytes/

Sector

A23–A16

(in hexadecimal)

Kwords)

128/64

SA198

SA199

SA200

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

SA224

SA225

SA226

SA227

SA228

SA229

SA230

SA231

SA232

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

18C0000–18DFFFF

18E0000–18FFFFF

1900000–191FFFF

1920000–193FFFF

1940000–195FFFF

1960000–197FFFF

1980000–199FFFF

19A0000–19BFFFF

19C0000–19DFFFF

19E0000–19FFFF

1A00000–1A1FFFF

1A20000–1A3FFFF

1A40000–1A5FFFF

1A60000–1A7FFFF

1A80000–1A9FFFF

1AA0000–1ABFFFF

1AC0000–1ADFFFF

1AE0000–1AFFFFF

1B00000–1B1FFFF

1B20000–1B3FFFF

1B40000–1B5FFFF

1B60000–1B7FFFF

1B80000–1B9FFFF

1BA0000–1BBFFFF

1BC0000–1BDFFFF

1BE0000–1BFFFFF

1C00000–1C1FFFF

1C20000–1C3FFFF

1C40000–1C5FFFF

1C60000–1C7FFFF

1C80000–1C9FFFF

1CA0000–1CBFFFF

1CC0000–1CDFFFF

1CE0000–1CFFFFF

1D00000–1D1FFFF

0C60000–0C6FFFF

0C70000–0C7FFFF

0C80000–0C8FFFF

0C90000–0C9FFFF

0CA0000–0CAFFFF

0CB0000–0CBFFFF

0CC0000–0CCFFFF

0CD0000–0CDFFFF

0CE0000–0CEFFFF

0CF0000–0CFFFFF

0D00000–0D0FFFF

0D10000–0D1FFFF

0D20000–0D2FFFF

0D30000–0D3FFFF

0D40000–0D4FFFF

0D50000–0D5FFFF

0D60000–0D6FFFF

0D70000–0D7FFFF

0D80000–0D8FFFF

0D90000–0D9FFFF

0DA0000–0DAFFFF

0DB0000–0DBFFFF

0DC0000–0DCFFFF

0DD0000–0DDFFFF

0DE0000–0DEFFFF

0DF0000–0DFFFFF

0E00000–0E0FFFF

0E10000–0E1FFFF

0E20000–0E2FFFF

0E30000–0E3FFFF

0E40000–0E4FFFF

0E50000–0E5FFFF

0E60000–0E6FFFF

0E70000–0E7FFFF

0E80000–0E8FFFF

32

S29GLxxxN MirrorBit^TMFlash Family

S29GLxxxN_00_A4 June 14, 2004

A d v a n c e I n f o r m a t i o n

Table 2. Sector Address Table–S29GL256N (Continued)

8-bit

Sector Size

16-bit

Address Range

(in hexadecimal)

Address Range

(Kbytes/

Sector

A23–A16

(in hexadecimal)

Kwords)

128/64

SA233

SA234

SA235

SA236

SA237

SA238

SA239

SA240

SA241

SA242

SA243

SA244

SA245

SA246

SA247

SA248

SA249

SA250

SA251

SA252

SA253

SA254

SA255

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1D20000–1D3FFFF

1D40000–1D5FFFF

1D60000–1D7FFFF

1D80000–1D9FFFF

1DA0000–1DBFFFF

1DC0000–1DDFFFF

1DE0000–1DFFFFF

1E00000–1E1FFFF

1E20000–1E3FFFF

1E40000–1E5FFFF

1E60000–137FFFF

1E80000–1E9FFFF

1EA0000–1EBFFFF

1EC0000–1EDFFFF

1EE0000–1EFFFFF

1F00000–1F1FFFF

1F20000–1F3FFFF

1F40000–1F5FFFF

1F60000–1F7FFFF

1F80000–1F9FFFF

1FA0000–1FBFFFF

1FC0000–1FDFFFF

1FE0000–1FFFFFF

0E90000–0E9FFFF

0EA0000–0EAFFFF

0EB0000–0EBFFFF

0EC0000–0ECFFFF

0ED0000–0EDFFFF

0EE0000–0EEFFFF

0EF0000–0EFFFFF

0F00000–0F0FFFF

0F10000–0F1FFFF

0F20000–0F2FFFF

0F30000–0F3FFFF

0F40000–0F4FFFF

0F50000–0F5FFFF

0F60000–0F6FFFF

0F70000–0F7FFFF

0F80000–0F8FFFF

0F90000–0F9FFFF

0FA0000–0FAFFFF

0FB0000–0FBFFFF

0FC0000–0FCFFFF

0FD0000–0FDFFFF

0FE0000–0FEFFFF

0FF0000–0FFFFFF

Table 3. Sector Address Table–S29GL128N

8-Bit

16-bit

Address Range

(in hexadecimal)

Sector Size

(Kbytes/

Kwords)

Address Range

Sector

A22–A16

(in hexadecimal)

SA0

SA1

SA2

SA3

SA4

SA5

SA6

0

1

0

1

0

1

0

1

0

1

0

1

0

128/64

0000000–001FFFF

0020000–003FFFF

0040000–005FFFF

0060000–007FFFF

0080000–009FFFF

00A0000–00BFFFF

00C0000–00DFFFF

0000000–000FFFF

0010000–001FFFF

0020000–002FFFF

0030000–003FFFF

0040000–004FFFF

0050000–005FFFF

0060000–006FFFF

June 14, 2004 S29GLxxxN_00_A4

S29GLxxxN MirrorBit^TMFlash Family

33

A d v a n c e I n f o r m a t i o n

Table 3. Sector Address Table–S29GL128N (Continued)

8-Bit

Sector Size

16-bit

Address Range

(in hexadecimal)

Address Range

(Kbytes/

Sector

A22–A16

(in hexadecimal)

Kwords)

128/64

SA7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

00E0000–00FFFFF

0100000–011FFFF

0120000–013FFFF

0140000–015FFFF

0160000–017FFFF

0180000–019FFFF

01A0000–01BFFFF

01C0000–01DFFFF

01E0000–01FFFFF

0200000–021FFFF

0220000–023FFFF

0240000–025FFFF

0260000–027FFFF

0280000–029FFFF

02A0000–02BFFFF

02C0000–02DFFFF

02E0000–02FFFFF

0300000–031FFFF

0320000–033FFFF

0340000–035FFFF

0360000–037FFFF

0380000–039FFFF

03A0000–03BFFFF

03C0000–03DFFFF

03E0000–03FFFFF

0400000–041FFFF

0420000–043FFFF

0440000–045FFFF

0460000–047FFFF

0480000–049FFFF

04A0000–04BFFFF

04C0000–04DFFFF

04E0000–04FFFFF

0500000–051FFFF

0520000–053FFFF

0070000–007FFFF

0080000–008FFFF

0090000–009FFFF

00A0000–00AFFFF

00B0000–00BFFFF

00C0000–00CFFFF

00D0000–00DFFFF

00E0000–00EFFFF

00F0000–00FFFFF

0100000–010FFFF

0110000–011FFFF

0120000–012FFFF

0130000–013FFFF

0140000–014FFFF

0150000–015FFFF

0160000–016FFFF

0170000–017FFFF

0180000–018FFFF

0190000–019FFFF

01A0000–01AFFFF

01B0000–01BFFFF

01C0000–01CFFFF

01D0000–01DFFFF

01E0000–01EFFFF

01F0000–01FFFFF

0200000–020FFFF

0210000–021FFFF

0220000–022FFFF

0230000–023FFFF

0240000–024FFFF

0250000–025FFFF

0260000–026FFFF

0270000–027FFFF

0280000–028FFFF

0290000–029FFFF

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

34

S29GLxxxN MirrorBit^TMFlash Family

S29GLxxxN_00_A4 June 14, 2004

A d v a n c e I n f o r m a t i o n

Table 3. Sector Address Table–S29GL128N (Continued)

8-Bit

Sector Size

16-bit

Address Range

(in hexadecimal)

Address Range

(Kbytes/

Sector

A22–A16

(in hexadecimal)

Kwords)

128/64

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0540000–055FFFF

0560000–057FFFF

0580000–059FFFF

05A0000–05BFFFF

05C0000–05DFFFF

05E0000–05FFFFF

0600000–061FFFF

0620000–063FFFF

0640000–065FFFF

0660000–067FFFF

0680000–069FFFF

06A0000–06BFFFF

06C0000–06DFFFF

06E0000–06FFFFF

0700000–071FFFF

0720000–073FFFF

0740000–075FFFF

0760000–077FFFF

0780000–079FFFF

07A0000–07BFFFF

07C0000–07DFFFF

07E0000–07FFFFF

0800000–081FFFF

0820000–083FFFF

0840000–085FFFF

0860000–087FFFF

0880000–089FFFF

08A0000–08BFFFF

08C0000–08DFFFF

08E0000–08FFFFF

0900000–091FFFF

0920000–093FFFF

0940000–095FFFF

0960000–097FFFF

0980000–099FFFF

02A0000–02AFFFF

02B0000–02BFFFF

02C0000–02CFFFF

02D0000–02DFFFF

02E0000–02EFFFF

02F0000–02FFFFF

0300000–030FFFF

0310000–031FFFF

0320000–032FFFF

0330000–033FFFF

0340000–034FFFF

0350000–035FFFF

0360000–036FFFF

0370000–037FFFF

0380000–038FFFF

0390000–039FFFF

03A0000–03AFFFF

03B0000–03BFFFF

03C0000–03CFFFF

03D0000–03DFFFF

03E0000–03EFFFF

03F0000–03FFFFF

0400000–040FFFF

0410000–041FFFF

0420000–042FFFF

0430000–043FFFF

0440000–044FFFF

0450000–045FFFF

0460000–046FFFF

0470000–047FFFF

0480000–048FFFF

0490000–049FFFF

04A0000–04AFFFF

04B0000–04BFFFF

04C0000–04CFFFF

June 14, 2004 S29GLxxxN_00_A4

S29GLxxxN MirrorBit^TMFlash Family

35

A d v a n c e I n f o r m a t i o n

Table 3. Sector Address Table–S29GL128N (Continued)

8-Bit

Sector Size

16-bit

Address Range

(in hexadecimal)

Address Range

(Kbytes/

Sector

A22–A16

(in hexadecimal)

Kwords)

128/64

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

09A0000–09BFFFF

09C0000–09DFFFF

09E0000–09FFFFF

0A00000–0A1FFFF

0A20000–0A3FFFF

0A40000–0A5FFFF

0A60000–0A7FFFF

0A80000–0A9FFFF

0AA0000–0ABFFFF

0AC0000–0ADFFFF

0AE0000–0AFFFFF

0B00000–0B1FFFF

0B20000–0B3FFFF

0B40000–0B5FFFF

0B60000–0B7FFFF

0B80000–0B9FFFF

0BA0000–0BBFFFF

0BC0000–0BDFFFF

0BE0000–0BFFFFF

0C00000–0C1FFFF

0C20000–0C3FFFF

0C40000–0C5FFFF

0C60000–0C7FFFF

0C80000–0C9FFFF

0CA0000–0CBFFFF

0CC0000–0CDFFFF

0CE0000–0CFFFFF

0D00000–0D1FFFF

0D20000–0D3FFFF

0D40000–0D5FFFF

0D60000–0D7FFFF

0D80000–0D9FFFF

0DA0000–0DBFFFF

0DC0000–0DDFFFF

0DE0000–0DFFFFF

04D0000–04DFFFF

04E0000–04EFFFF

04F0000–04FFFFF

0500000–050FFFF

0510000–051FFFF

0520000–052FFFF

0530000–053FFFF

0540000–054FFFF

0550000–055FFFF

0560000–056FFFF

0570000–057FFFF

0580000–058FFFF

0590000–059FFFF

05A0000–05AFFFF

05B0000–05BFFFF

05C0000–05CFFFF

05D0000–05DFFFF

05E0000–05EFFFF

05F0000–05FFFFF

0600000–060FFFF

0610000–061FFFF

0620000–062FFFF

0630000–063FFFF

0640000–064FFFF

0650000–065FFFF

0660000–066FFFF

0670000–067FFFF

0680000–068FFFF

0690000–069FFFF

06A0000–06AFFFF

06B0000–06BFFFF

06C0000–06CFFFF

06D0000–06DFFFF

06E0000–06EFFFF

06F0000–06FFFFF

36

S29GLxxxN MirrorBit^TMFlash Family

S29GLxxxN_00_A4 June 14, 2004

A d v a n c e I n f o r m a t i o n

Table 3. Sector Address Table–S29GL128N (Continued)

8-Bit

Sector Size

16-bit

Address Range

(in hexadecimal)

Address Range

(Kbytes/

Sector

A22–A16

(in hexadecimal)

Kwords)

128/64

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0E00000–0E1FFFF

0E20000–0E3FFFF

0E40000–0E5FFFF

0E60000–0E7FFFF

0E80000–0E9FFFF

0EA0000–0EBFFFF

0EC0000–0EDFFFF

0EE0000–0EFFFFF

0F00000–0F1FFFF

0F20000–0F3FFFF

0F40000–0F5FFFF

0F60000–0F7FFFF

0F80000–0F9FFFF

0FA0000–0FBFFFF

0FC0000–0FDFFFF

0FE0000–0FFFFFF

0700000–070FFFF

0710000–071FFFF

0720000–072FFFF

0730000–073FFFF

0740000–074FFFF

0750000–075FFFF

0760000–076FFFF

0770000–077FFFF

0780000–078FFFF

0790000–079FFFF

07A0000–07AFFFF

07B0000–07BFFFF

07C0000–07CFFFF

07D0000–07DFFFF

07E0000–07EFFFF

07F0000–07FFFFF

Sector Protection

The device features several levels of sector protection, which can disable both the

program and erase operations in certain sectors or sector groups:

Persistent Sector Protection

A command sector protection method that replaces the old 12 V controlled pro-

tection method.

Password Sector Protection

A highly sophisticated protection method that requires a password before

changes to certain sectors or sector groups are permitted

WP# Hardware Protection

A write protect pin that can prevent program or erase operations in the outermost

sectors.

The WP# Hardware Protection feature is always available, independent of the

software managed protection method chosen.

Selecting a Sector Protection Mode

All parts default to operate in the Persistent Sector Protection mode. The cus-

tomer must then choose if the Persistent or Password Protection method is most

desirable. There are two one-time programmable non-volatile bits that define

which sector protection method will be used. If the customer decides to continue

using the Persistent Sector Protection method, they must set the Persistent

Sector Protection Mode Locking Bit. This will permanently set the part to op-

June 14, 2004 S29GLxxxN_00_A4

S29GLxxxN MirrorBit^TMFlash Family

37

A d v a n c e I n f o r m a t i o n

erate only using Persistent Sector Protection. If the customer decides to use the

password method, they must set the Password Mode Locking Bit. This will

permanently set the part to operate only using password sector protection.

It is important to remember that setting either the Persistent Sector Protec-

tion Mode Locking Bit or the Password Mode Locking Bit permanently

selects the protection mode. It is not possible to switch between the two methods

once a locking bit has been set. It is important that one mode is explicitly

selected when the device is first programmed, rather than relying on the

default mode alone. This is so that it is not possible for a system program or

virus to later set the Password Mode Locking Bit, which would cause an unex-

pected shift from the default Persistent Sector Protection Mode into the Password

Protection Mode.

The device is shipped with all sectors unprotected. The factory offers the option

of programming and protecting sectors at the factory prior to shipping the device

through the ExpressFlash™ Service. Contact your sales representative for details.

It is possible to determine whether a sector is protected or unprotected. See “Au-

toselect Command Sequence” section on page 50 for details.

Advanced Sector Protection

Advanced Sector Protection features several levels of sector protection, which can

disable both the program and erase operations in certain sectors.

Persistent Sector Protection is a method that replaces the old 12V controlled

protection method.

Password Sector Protection is a highly sophisticated protection method that

requires a password before changes to certain sectors are permitted.

Advanced Sector Protection is available when ACC = V

.

HH

Lock Register

The Lock Register consists of 3 bits (DQ2, DQ1, and DQ0). These DQ2, DQ1, DQ0

bits of the Lock Register are programmable by the user. Users are not allowed to

program both DQ2 and DQ1 bits of the Lock Register to the 00 state. If the user

tries to program DQ2 and DQ1 bits of the Lock Register to the 00 state, the device

will abort the Lock Register back to the default 11 state. The programming time

of the Lock Register is same as the typical word programming time without uti-

lizing the Write Buffer of the device. During a Lock Register programming

sequence execution, the DQ6 Toggle Bit I will toggle until the programming of the

Lock Register has completed to indicate programming status. All Lock Register

bits are readable to allow users to verify Lock Register statuses. Initial access

delay is required to read the Lock Register.

The Customer Secured Silicon Sector Protection Bit is DQ0, Persistent Protection

Mode Lock Bit is DQ1, and Password Protection Mode Lock Bit is DQ2 are acces-

sible by all users. Each of these bits are non-volatile. DQ15-DQ3 are reserved and

must be 1's when the user tries to program the DQ2, DQ1, and DQ0 bits of the

Lock Register. The user is not required to program DQ2, DQ1 and DQ0 bits of the

Lock Register at the same time. This allows users to lock the Secured Silicon Sec-

tor and then set the device either permanently into Password Protection Mode or

Persistent Protection Mode and then lock the Secured Silicon Sector at separate

instances and time frames.

Secured Silicon Sector Protection allows the user to lock the Secured Silicon

Sector area

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Persistent Protection Mode Lock Bit allows the user to set the device perma-

nently to operate in the Persistent Protection Mode

Password Protection Mode Lock Bit allows the user to set the device perma-

nently to operate in the Password Protection Mode

Table 4. Lock Register

DQ15-3

DQ2

DQ1

DQ0

Secured Silicon

Sector Protection

Bit

Password Protection PersistentProtection

Mode Lock Bit Mode Lock Bit

Don’t Care

Persistent Sector Protection

The Persistent Sector Protection method replaces the old 12 V controlled protec-

tion method while at the same time enhancing flexibility by providing three

different sector protection states:

Dynamically Locked-The sector is protected and can be changed by a sim-

ple command

Persistently Locked-A sector is protected and cannot be changed

Unlocked-The sector is unprotected and can be changed by a simple com-

mand

In order to achieve these states, three types of “bits” are going to be used:

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector. After power-up or hardware

reset, the contents of all DYB bits are in the “unprotected state” if the DYB Lock

Bit of the “Lock Register” is not programmed. If the DYB Lock Bit of the “Lock

Register” is programmed, all DYB bits will power-up or hardware reset to the

“protected state”. Each DYB is individually modifiable through the DYB Set Com-

mand and DYB Clear Command. When the parts are first shipped, all of the

Persistent Protect Bits (PPB) are cleared into the unprotected state. The DYB bits

and PPB Lock bit are defaulted to power up in the cleared state or unprotected

state - meaning the all PPB bits are changeable.

The Protection State for each sector is determined by the logical OR of the PPB

and the DYB related to that sector. For the sectors that have the PPB bits cleared,

the DYB bits control whether or not the sector is protected or unprotected. By is-

suing the DYB Set and DYB Clear command sequences, the DYB bits will be

protected or unprotected, thus placing each sector in the protected or unpro-

tected state. These are the so-called Dynamic Locked or Unlocked states. They

are called dynamic states because it is very easy to switch back and forth be-

tween the protected and un-protected conditions. This allows software to easily

protect sectors against inadvertent changes yet does not prevent the easy re-

moval of protection when changes are needed.

The DYB bits maybe set or cleared as often as needed. The PPB bits allow for a

more static, and difficult to change, level of protection. The PPB bits retain their

state across power cycles because they are Non-Volatile. Individual PPB bits are

set with a program command but must all be cleared as a group through an erase

command.

The PPB Lock Bit adds an additional level of protection. Once all PPB bits are pro-

grammed to the desired settings, the PPB Lock Bit may be set to the “freeze

June 14, 2004 S29GLxxxN_00_A4

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A d v a n c e I n f o r m a t i o n

state”. Setting the PPB Lock Bit to the “freeze state” disables all program and

erase commands to the Non-Volatile PPB bits. In effect, the PPB Lock Bit locks the

PPB bits into their current state. The only way to clear the PPB Lock Bit to the

“unfreeze state” is to go through a power cycle, or hardware reset. The Software

Reset command will not clear the PPB Lock Bit to the “unfreeze state”. System

boot code can determine if any changes to the PPB bits are needed e.g. to allow

new system code to be downloaded. If no changes are needed then the boot code

can set the PPB Lock Bit to disable any further changes to the PPB bits during

system operation.

The WP# write protect pin adds a final level of hardware protection. When this

pin is low it is not possible to change the contents of the WP# protected sectors.

These sectors generally hold system boot code. So, the WP# pin can prevent any

changes to the boot code that could override the choices made while setting up

sector protection during system initialization.

It is possible to have sectors that have been persistently locked, and sectors that

are left in the dynamic state. The sectors in the dynamic state are all unprotected.

If there is a need to protect some of them, a simple DYB Set command sequence

is all that is necessary. The DYB Set and DYB Clear commands for the dynamic

sectors switch the DYB bits to signify protected and unprotected, respectively. If

there is a need to change the status of the persistently locked sectors, a few more

steps are required. First, the PPB Lock Bit must be disabled to the “unfreeze

state” by either putting the device through a power-cycle, or hardware reset. The

PPB bits can then be changed to reflect the desired settings. Setting the PPB Lock

Bit once again to the “freeze state” will lock the PPB bits, and the device operates

normally again.

Note: to achieve the best protection, it's recommended to execute the PPB Lock

Bit Set command early in the boot code, and protect the boot code by holding

WP# = V .

IL

Persistent Protection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is assigned to each sector. If a PPB

is programmed to the protected state through the “PPB Program” command, that

sector will be protected from program or erase operations will be read-only. If a

PPB requires erasure, all of the sector PPB bits must first be erased in parallel

through the “All PPB Erase” command. The “All PPB Erase” command will prepro-

grammed all PPB bits prior to PPB erasing. All PPB bits erase in parallel, unlike

programming where individual PPB bits are programmable. The PPB bits have the

same endurance as the flash memory.

Programming the PPB bit requires the typical word programming time without uti-

lizing the Write Buffer. During a PPB bit programming and A11 PPB bit erasing

sequence execution, the DQ6 Toggle Bit I will toggle until the programming of the

PPB bit or erasing of all PPB bits has completed to indicate programming and

erasing status. Erasing all of the PPB bits at once requires typical sector erase

time. During the erasing of all PPB bits, the DQ3 Sector Erase Timer bit will output

a 1 to indicate the erasure of all PPB bits are in progress. When the erasure of all

PPB bits has completed, the DQ3 Sector Erase Timer bit will output a 0 to indicate

that all PPB bits have been erased. Reading the PPB Status bit requires the initial

access time of the device.

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Persistent Protection Bit Lock (PPB Lock Bit)

A global volatile bit. When set to the “freeze state”, the PPB bits cannot be

changed. When cleared to the “unfreeze state”, the PPB bits are changeable.

There is only one PPB Lock Bit per device. The PPB Lock Bit is cleared to the “un-

freeze state” after power-up or hardware reset. There is no command sequence

to unlock or “unfreeze” the PPB Lock Bit.

Configuring the PPB Lock Bit to the freeze state requires approximately 100ns.

Reading the PPB Lock Status bit requires the initial access time of the device.

Table 5. Sector Protection Schemes

Protection States

Sector State

DYB Bit

PPB Bit

PPB Lock Bit

Unprotect

Unfreeze

Unprotected – PPB and DYB are changeable

Unprotected – PPB not changeable, DYB is

changeable

Unprotect

Freeze

Unprotect

Protect

Unfreeze

Freeze

Protected – PPB and DYB are changeable

Protected – PPB not changeable, DYB is changeable

Protected – PPB and DYB are changeable

Unprotect

Protect

Unfreeze

Freeze

Protect

Protected – PPB not changeable, DYB is changeable

Protected – PPB and DYB are changeable

Protect

Unfreeze

Freeze

Protect

Protected – PPB not changeable, DYB is changeable

Table 7 contains all possible combinations of the DYB bit, PPB bit, and PPB Lock

Bit relating to the status of the sector. In summary, if the PPB bit is set, and the

PPB Lock Bit is set, the sector is protected and the protection cannot be removed

until the next power cycle or hardware reset clears the PPB Lock Bit to “unfreeze

state”. If the PPB bit is cleared, the sector can be dynamically locked or unlocked.

The DYB bit then controls whether or not the sector is protected or unprotected.

If the user attempts to program or erase a protected sector, the device ignores

the command and returns to read mode. A program command to a protected sec-

tor enables status polling for approximately 1 µs before the device returns to read

mode without having modified the contents of the protected sector. An erase

command to a protected sector enables status polling for approximately 50 µs

after which the device returns to read mode without having erased the protected

sector. The programming of the DYB bit, PPB bit, and PPB Lock Bit for a given sec-

tor can be verified by writing a DYB Status Read, PPB Status Read, and PPB Lock

Status Read commands to the device.

The Autoselect Sector Protection Verification outputs the OR function of the DYB

bit and PPB bit per sector basis. When the OR function of the DYB bit and PPB bit

is a 1, the sector is either protected by DYB or PPB or both. When the OR function

of the DYB bit and PPB bit is a 0, the sector is unprotected through both the DYB

and PPB.

Persistent Protection Mode Lock Bit

Like the Password Protection Mode Lock Bit, a Persistent Protection Mode Lock Bit

exists to guarantee that the device remain in software sector protection. Once

programmed, the Persistent Protection Mode Lock Bit prevents programming of

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A d v a n c e I n f o r m a t i o n

the Password Protection Mode Lock Bit. This guarantees that a hacker could not

place the device in Password Protection Mode. The Password Protection Mode

Lock Bit resides in the “Lock Register”.

Password Sector Protection

The Password Sector Protection method allows an even higher level of security

than the Persistent Sector Protection method. There are two main differences be-

tween the Persistent Sector Protection and the Password Sector Protection

methods:

When the device is first powered on, or comes out of a reset cycle, the PPB

Lock Bit is set to the locked state, or the freeze state, rather than cleared to

the unlocked state, or the unfreeze state.

The only means to clear and unfreeze the PPB Lock Bit is by writing a unique

64-bit Password to the device.

The Password Sector Protection method is otherwise identical to the Persistent

Sector Protection method.

A 64-bit password is the only additional tool utilized in this method.

The password is stored in a one-time programmable (OTP) region outside of the

flash memory. Once the Password Protection Mode Lock Bit is set, the password

is permanently set with no means to read, program, or erase it. The password is

used to clear and unfreeze the PPB Lock Bit. The Password Unlock command must

be written to the flash, along with a password. The flash device internally com-

pares the given password with the pre-programmed password. If they match, the

PPB Lock Bit is cleared to the “unfreezed state”, and the PPB bits can be altered.

If they do not match, the flash device does nothing. There is a built-in 2 µs delay

for each “password check” after the valid 64-bit password has been entered for

the PPB Lock Bit to be cleared to the “unfreezed state”. This delay is intended to

thwart any efforts to run a program that tries all possible combinations in order

to crack the password.

Password and Password Protection Mode Lock Bit

In order to select the Password Sector Protection method, the customer must first

program the password. The factory recommends that the password be somehow

correlated to the unique Electronic Serial Number (ESN) of the particular flash de-

vice. Each ESN is different for every flash device; therefore each password should

be different for every flash device. While programming in the password region,

the customer may perform Password Read operations. Once the desired pass-

word is programmed in, the customer must then set the Password Protection

Mode Lock Bit. This operation achieves two objectives:

1. It permanently sets the device to operate using the Password Protection Mode.

It is not possible to reverse this function.

2. It also disables all further commands to the password region. All program, and

read operations are ignored.

Both of these objectives are important, and if not carefully considered, may lead

to unrecoverable errors. The user must be sure that the Password Sector Protec-

tion method is desired when programming the Password Protection Mode Lock

Bit. More importantly, the user must be sure that the password is correct when

the Password Protection Mode Lock Bit is programmed. Due to the fact that read

operations are disabled, there is no means to read what the password is after-

wards. If the password is lost after programming the Password Protection Mode

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Lock Bit, there will be no way to clear and unfreeze the PPB Lock Bit. The Pass-

word Protection Mode Lock Bit, once programmed, prevents reading the 64-bit

password on the DQ bus and further password programming. The Password Pro-

tection Mode Lock Bit is not erasable. Once Password Protection Mode Lock Bit is

programmed, the Persistent Protection Mode Lock Bit is disabled from program-

ming, guaranteeing that no changes to the protection scheme are allowed.

64-bit Password

The 64-bit Password is located in its own memory space and is accessible through

the use of the Password Program and Password Read commands. The password

function works in conjunction with the Password Protection Mode Lock Bit, which

when programmed, prevents the Password Read command from reading the con-

tents of the password on the pins of the device.

Persistent Protection Bit Lock (PPB Lock Bit)

A global volatile bit. The PPB Lock Bit is a volatile bit that reflects the state of the

Password Protection Mode Lock Bit after power-up reset. If the Password Protec-

tion Mode Lock Bit is also programmed after programming the Password, the

Password Unlock command must be issued to clear and unfreeze the PPB Lock Bit

after a hardware reset (RESET# asserted) or a power-up reset. Successful exe-

cution of the Password Unlock command clears and unfreezes the PPB Lock Bit,

allowing for sector PPB bits to be modified. Without issuing the Password Unlock

command, while asserting RESET#, taking the device through a power-on reset,

or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a the “freeze

state”.

If the Password Protection Mode Lock Bit is not programmed, the device defaults

to Persistent Protection Mode. In the Persistent Protection Mode, the PPB Lock Bit

is cleared to the “unfreeze state” after power-up or hardware reset. The PPB Lock

Bit is set to the “freeze state” by issuing the PPB Lock Bit Set command. Once set

to the “freeze state” the only means for clearing the PPB Lock Bit to the “unfreeze

state” is by issuing a hardware or power-up reset. The Password Unlock com-

mand is ignored in Persistent Protection Mode.

Reading the PPB Lock Bit requires a 200ns access time.

Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector feature provides a Flash memory region that enables

permanent part identification through an Electronic Serial Number (ESN). The

Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector

Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked

when shipped from the factory. This bit is permanently set at the factory and can-

not be changed, which prevents cloning of a factory locked part. This ensures the

security of the ESN once the product is shipped to the field.

The factory offers the device with the Secured Silicon Sector either customer

lockable (standard shipping option) or factory locked (contact an AMD sales rep-

resentative for ordering information). The customer-lockable version is shipped

with the Secured Silicon Sector unprotected, allowing customers to program the

sector after receiving the device. The customer-lockable version also has the Se-

cured Silicon Sector Indicator Bit permanently set to a “0.” The factory-locked

version is always protected when shipped from the factory, and has the Secured

Silicon Sector Indicator Bit permanently set to a “1.” Thus, the Secured Silicon

Sector Indicator Bit prevents customer-lockable devices from being used to re-

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A d v a n c e I n f o r m a t i o n

place devices that are factory locked. Note that the ACC function and unlock

bypass modes are not available when the Secured Silicon Sector is enabled.

The Secured Silicon sector address space in this device is allocated as follows:

Secured Silicon Sector

Address Range

ExpressFlash

Factory Locked

Customer Lockable

ESN Factory Locked

ESN

ESN or determined by

customer

000000h–000007h

000008h–00007Fh

Determined by customer

Unavailable

Determined by customer

The system accesses the Secured Silicon Sector through a command sequence

(see “Write Protect (WP#)”). After the system has written the Enter Secured Sil-

icon Sector command sequence, it may read the Secured Silicon Sector by using

the addresses normally occupied by the first sector (SA0). This mode of operation

continues until the system issues the Exit Secured Silicon Sector command se-

quence, or until power is removed from the device. On power-up, or following a

hardware reset, the device reverts to sending commands to sector SA0.

Customer Lockable: Secured Silicon Sector NOT Programmed or

Protected At the Factory

Unless otherwise specified, the device is shipped such that the customer may

program and protect the 256-byte Secured Silicon sector.

The system may program the Secured Silicon Sector using the write-buffer, ac-

celerated and/or unlock bypass methods, in addition to the standard

programming command sequence. See Command Definitions.

Programming and protecting the Secured Silicon Sector must be used with cau-

tion since, once protected, there is no procedure available for unprotecting the

Secured Silicon Sector area and none of the bits in the Secured Silicon Sector

memory space can be modified in any way.

The Secured Silicon Sector area can be protected using one of the following

procedures:

Write the three-cycle Enter Secured Silicon Sector Region command se-

quence, and then follow the in-system sector protect algorithm as shown in

Figure 2, except that RESET# may be at either V or V . This allows in-sys-

IH

ID

tem protection of the Secured Silicon Sector without raising any device pin to

a high voltage. Note that this method is only applicable to the Secured Silicon

Sector.

To verify the protect/unprotect status of the Secured Silicon Sector, follow the

algorithm shown in Figure 1.

Once the Secured Silicon Sector is programmed, locked and verified, the system

must write the Exit Secured Silicon Sector Region command sequence to return

to reading and writing within the remainder of the array.

Factory Locked: Secured Silicon Sector Programmed and

Protected At the Factory

In devices with an ESN, the Secured Silicon Sector is protected when the device

is shipped from the factory. The Secured Silicon Sector cannot be modified in any

way. An ESN Factory Locked device has an 16-byte random ESN at addresses

000000h–000007h. Please contact your sales representative for details on order-

ing ESN Factory Locked devices.

Customers may opt to have their code programmed by the factory through the

ExpressFlash service (Express Flash Factory Locked). The devices are then

44

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shipped from the factory with the Secured Silicon Sector permanently locked.

Contact your sales representative for details on using the ExpressFlash service.

Write Protect (WP#)

The Write Protect function provides a hardware method of protecting the first or

last sector group without using V . Write Protect is one of two functions provided

ID

by the WP#/ACC input.

If the system asserts V on the WP#/ACC pin, the device disables program and

IL

erase functions in the first or last sector group independently of whether those

sector groups were protected or unprotected using the method described in“Ad-

vanced Sector Protection” section on page 38. Note that if WP#/ACC is at V

IL

when the device is in the standby mode, the maximum input load current is in-

creased. See the table in “DC Characteristics” section on page 78.

If the system asserts V

on the WP#/ACC pin, the device reverts to

IH

whether the first or last sector was previously set to be protected or un-

protected using the method described in “Sector Group Protection and

Unprotection”. Note that WP# has an internal pullup; when uncon-

nected, WP# is at V

.

IH

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing

provides data protection against inadvertent writes (refer to Tables 16 and 17 for

command definitions). In addition, the following hardware data protection mea-

sures prevent accidental erasure or programming, which might otherwise be

caused by spurious system level signals during V

transitions, or from system noise.

power-up and power-down

CC

Low V

Write Inhibit

CC

When V is less than V

, the device does not accept any write cycles. This pro-

LKO

CC

tects data during V power-up and power-down. The command register and all

CC

internal program/erase circuits are disabled, and the device resets to the read

mode. Subsequent writes are ignored until V is greater than V

. The system

LKO

CC

must provide the proper signals to the control pins to prevent unintentional writes

when V is greater than V

.

LKO

CC

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write

cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V , CE# = V or WE# =

IL

IH

V . To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a

IH

logical one.

Power-Up Write Inhibit

If WE# = CE# = V and OE# = V during power up, the device does not accept

IL

IH

commands on the rising edge of WE#. The internal state machine is automatically

reset to the read mode on power-up.

Common Flash Memory Interface (CFI)

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A d v a n c e I n f o r m a t i o n

The Common Flash Interface (CFI) specification outlines device and host system

software interrogation handshake, which allows specific vendor-specified soft-

ware algorithms to be used for entire families of devices. Software support can

then be device-independent, JEDEC ID-independent, and forward- and back-

ward-compatible for the specified flash device families. Flash vendors can

standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query

command, 98h, to address 55h, any time the device is ready to read array data.

The system can read CFI information at the addresses given in Tables 8-11. To

terminate reading CFI data, the system must write the reset command.

The system can also write the CFI query command when the device is in the au-

toselect mode. The device enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 8–11. The system must write the reset

command to return the device to reading array data.

For further information, please refer to the CFI Specification and CFI Publication

100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alter-

natively, contact your sales representative for copies of these documents.

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Table 6. CFI Query Identification String

Addresses (x16)

Data

Description

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

0000h

Table 7. System Interface String

Addresses (x16)

Data

Description

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

0027h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0036h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0007h

000Ah

0000h

0001h

0005h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^N

µs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

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Table 8. Device Geometry Definition

Addresses (x16)

Data

Description

001Ah

0019h

0018h

Device Size = 2^Nbyte

27h

1A = 512 Mb, 19 = 256 Mb, 18 = 128 Mb

28h

29h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0005h

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

Number of Erase Block Regions within device (01h = uniform device, 02h = boot

device)

2Ch

0001h

Erase Block Region 1 Information

2Dh

2Eh

2Fh

30h

00xxh

000xh

0000h

000xh

(refer to the CFI specification or CFI publication 100)

00FFh, 001h, 0000h, 0002h = 512 Mb

00FFh, 0000h, 0000h, 0002h = 256 Mb

007Fh, 0000h, 0000h, 0002h = 128 Mb

31h

32h

33h

34h

0000h

Erase Block Region 2 Information (refer to CFI publication 100)

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

35h

36h

37h

38h

0000h

39h

3Ah

3Bh

3Ch

0000h

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Table 9. Primary Vendor-Specific Extended Query

Addresses (x16)

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

0010h

Process Technology (Bits 7-2) 0100b = 110 nm MirrorBit

Erase Suspend

46h

47h

48h

49h

4Ah

4Bh

4Ch

0002h

0001h

0000h

0008h

0000h

0002h

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

0008h = Advanced Sector Protection

Simultaneous Operation

00 = Not Supported, X = Number of Sectors in Bank

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

00B5h

00C5h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

0004h/

0005h

00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h =

Top Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform

sectors top WP# protect

4Fh

50h

Program Suspend

0001h

00h = Not Supported, 01h = Supported

Command Definitions

Writing specific address and data commands or sequences into the command

register initiates device operations. Table 10 and Table 11 define the valid register

command sequences. Writing incorrect address and data values or writing them

in the improper sequence may place the device in an unknown state. A reset com-

mand is then required to return the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens

later. All data is latched on the rising edge of WE# or CE#, whichever happens

first. Refer to the AC Characteristics section for timing diagrams.

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Reading Array Data

The device is automatically set to reading array data after device power-up. No

commands are required to retrieve data. The device is ready to read array data

after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the

erase-suspend-read mode, after which the system can read data from any non-

erase-suspended sector. After completing a programming operation in the Erase

Suspend mode, the system may once again read array data with the same ex-

ception. See the Erase Suspend/Erase Resume Commands section for more

information.

The system must issue the reset command to return the device to the read (or

erase-suspend-read) mode if DQ5 goes high during an active program or erase

operation, or if the device is in the autoselect mode. See the next section, Reset

Command, for more information.

See also Requirements for Reading Array Data in the Device Bus Operations sec-

tion for more information. The Read-Only Operations–“AC Characteristics”

section on page 80 provides the read parameters, and Figure 11 shows the timing

diagram.

Reset Command

Writing the reset command resets the device to the read or erase-suspend-read

mode. Address bits are don’t cares for this command.

The reset command may be written between the sequence cycles in an erase

command sequence before erasing begins. This resets the device to the read

mode. Once erasure begins, however, the device ignores reset commands until

the operation is complete.

The reset command may be written between the sequence cycles in a program

command sequence before programming begins. This resets the device to the

read mode. If the program command sequence is written while the device is in

the Erase Suspend mode, writing the reset command returns the device to the

erase-suspend-read mode. Once programming begins, however, the device ig-

nores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect

command sequence. Once in the autoselect mode, the reset command must be

written to return to the read mode. If the device entered the autoselect mode

while in the Erase Suspend mode, writing the reset command returns the device

to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation, writing the reset command

returns the device to the read mode (or erase-suspend-read mode if the device

was in Erase Suspend).

Note that if DQ1 goes high during a Write Buffer Programming operation, the sys-

tem must write the Write-to-Buffer-Abort Reset command sequence to reset the

device for the next operation.

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manu-

facturer and device codes, and determine whether or not a sector is protected.

Table 10 and Table 11 show the address and data requirements. This method re-

quires V on address pin A9. The autoselect command sequence may be written

ID

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to an address that is either in the read or erase-suspend-read mode. The autose-

lect command may not be written while the device is actively programming or

erasing.

The autoselect command sequence is initiated by first writing two unlock cycles.

This is followed by a third write cycle that contains the autoselect command. The

device then enters the autoselect mode. The system may read at any address any

number of times without initiating another autoselect command sequence:

A read cycle at address XX00h returns the manufacturer code.

Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code.

A read cycle to an address containing a sector address (SA), and the address

02h on A7–A0 in word mode returns 01h if the sector is protected, or 00h if

it is unprotected.

The system must write the reset command to return to the read mode (or erase-

suspend-read mode if the device was previously in Erase Suspend).

Enter Secured Silicon Sector/Exit Secured Silicon

Sector Command Sequence

The Secured Silicon Sector region provides a secured data area containing an 8-

word/16-byte random Electronic Serial Number (ESN). The system can access

the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon

Sector command sequence. The device continues to access the Secured Silicon

Sector region until the system issues the four-cycle Exit Secured Silicon Sector

command sequence. The Exit Secured Silicon Sector command sequence returns

the device to normal operation. Table 10 and Table 11 show the address and data

requirements for both command sequences. See also “Secured Silicon Sector

Flash Memory Region” for further information. Note that the ACC function and un-

lock bypass modes are not available when the Secured Silicon Sector is enabled.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is

initiated by writing two unlock write cycles, followed by the program set-up com-

mand. The program address and data are written next, which in turn initiate the

Embedded Program algorithm. The system is not required to provide further con-

trols or timings. The device automatically provides internally generated program

pulses and verifies the programmed cell margin. Table 10 and Table 11 show the

address and data requirements for the word program command sequence.

When the Embedded Program algorithm is complete, the device then returns to

the read mode and addresses are no longer latched. The system can determine

the status of the program operation by using DQ7 or DQ6. Refer to the Write Op-

eration Status section for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm

are ignored. Note that the Secured Silicon Sector, autoselect, and CFI

functions are unavailable when a program operation is in progress. Note

that a hardware reset immediately terminates the program operation. The pro-

gram command sequence should be reinitiated once the device has returned to

the read mode, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. Program-

ming to the same word address multiple times without intervening erases is

limited. For such application requirements, please contact your local Spansion

representative. Any word cannot be programmed from “0” back to a “1.”

Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and

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A d v a n c e I n f o r m a t i o n

DQ6 status bits to indicate the operation was successful. However, a succeeding

read will show that the data is still “0.” Only erase operations can convert a “0”

to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program words to the device

faster than using the standard program command sequence. The unlock bypass

command sequence is initiated by first writing two unlock cycles. This is followed

by a third write cycle containing the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cycle unlock bypass program com-

mand sequence is all that is required to program in this mode. The first cycle in

this sequence contains the unlock bypass program command, A0h; the second

cycle contains the program address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial two unlock cycles required

in the standard program command sequence, resulting in faster total program-

ming time. Table 10 and Table 11 show the requirements for the command

sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-

pass Reset commands are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset command sequence. (See Table 10

and Table 11).

Write Buffer Programming

Write Buffer Programming allows the system write to a maximum of 16 words/32

bytes in one programming operation. This results in faster effective programming

time than the standard programming algorithms. The Write Buffer Programming

command sequence is initiated by first writing two unlock cycles. This is followed

by a third write cycle containing the Write Buffer Load command written at the

Sector Address in which programming will occur. The fourth cycle writes the sec-

tor address and the number of word locations, minus one, to be programmed. For

example, if the system will program 6 unique address locations, then 05h should

be written to the device. This tells the device how many write buffer addresses

will be loaded with data and therefore when to expect the Program Buffer to Flash

command. The number of locations to program cannot exceed the size of the

write buffer or the operation will abort.

The fifth cycle writes the first address location and data to be programmed. The

write-buffer-page is selected by address bits A

–A . All subsequent address/

4

MAX

data pairs must fall within the selected-write-buffer-page. The system then

writes the remaining address/data pairs into the write buffer. Write buffer loca-

tions may be loaded in any order.

The write-buffer-page address must be the same for all address/data pairs loaded

into the write buffer. (This means Write Buffer Programming cannot be performed

across multiple write-buffer pages. This also means that Write Buffer Program-

ming cannot be performed across multiple sectors. If the system attempts to load

programming data outside of the selected write-buffer page, the operation will

abort.)

Note that if a Write Buffer address location is loaded multiple times, the address/

data pair counter will be decremented for every data load operation. The host

system must therefore account for loading a write-buffer location more than

once. The counter decrements for each data load operation, not for each unique

write-buffer-address location. Note also that if an address location is loaded more

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than once into the buffer, the final data loaded for that address will be

programmed.

Once the specified number of write buffer locations have been loaded, the system

must then write the Program Buffer to Flash command at the sector address. Any

other address and data combination aborts the Write Buffer Programming oper-

ation. The device then begins programming. Data polling should be used while

monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5,

and DQ1 should be monitored to determine the device status during Write Buffer

Programming.

The write-buffer programming operation can be suspended using the standard

program suspend/resume commands. Upon successful completion of the Write

Buffer Programming operation, the device is ready to execute the next command.

The Write Buffer Programming Sequence can be aborted in the following ways:

Load a value that is greater than the page buffer size during the Number of

Locations to Program step.

Write to an address in a sector different than the one specified during the

Write-Buffer-Load command.

Write an Address/Data pair to a different write-buffer-page than the one se-

lected by the Starting Address during the write buffer data loading stage of

the operation.

Write data other than the Confirm Command after the specified number of

data load cycles.

The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address

location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset com-

mand sequence must be written to reset the device for the next operation. Note

that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required

when using Write-Buffer-Programming features in Unlock Bypass mode.

Write buffer programming is allowed in any sequence. Note that the Secured Sil-

icon sector, autoselect, and CFI functions are unavailable when a program

operation is in progress. This flash device is capable of handling multiple write

buffer programming operations on the same write buffer address range without

intervening erases. For applications requiring an excessive number of such re-

peated write buffer programming operations, please contact your local Spansion

representative. Any bit in a write buffer address range cannot be pro-

grammed from “0” back to a “1.” Attempting to do so may cause the device

to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation

was successful. However, a succeeding read will show that the data is still “0.”

Only erase operations can convert a “0” to a “1.”

Accelerated Program

The device offers accelerated program operations through the WP#/ACC pin.

When the system asserts V

on the WP#/ACC pin, the device automatically en-

HH

ters the Unlock Bypass mode. The system may then write the two-cycle Unlock

Bypass program command sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not

be at V

for operations other than accelerated programming, or device damage

HH

may result. WP# has an internal pullup; when unconnected, WP# is at V

.

IH

Figure 3 illustrates the algorithm for the program operation. Refer to the Erase

and Program Operations–“AC Characteristics” section on page 80 section for pa-

rameters, and Figure 14 for timing diagrams.

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A d v a n c e I n f o r m a t i o n

Write “Write to Buffer”

command and

Sector Address

Part of “Write to Buffer”

Command Sequence

Write number of addresses

to program minus 1(WC = 31)

and Sector Address

Write first address/data

Yes

WC = 0 ?

No

Write to a different

sector address

Abort Write to

Buffer Operation?

Yes

Write to buffer ABORTED.

Must write “Write-to-buffer

Abort Reset” command

sequence to return

No

Write next address/data pair

to read mode.

WC = WC - 1

Write program buffer to

flash sector address

Notes:

1. When Sector Address is specified, any

address in the selected sector is acceptable.

However, when loading Write-Buffer

address locations with data, all addresses

must fall within the selected Write-Buffer

Page.

Read DQ15 - DQ0 at

Last Loaded Address

2. DQ7 may change simultaneously with DQ5.

Therefore, DQ7 should be verified.

3. If this flowchart location was reached

because DQ5= “1”, then the device FAILED.

If this flowchart location was reached

because DQ1= “1”, then the Write to Buffer

operation was ABORTED. In either case, the

proper reset command must be written

before the device can begin another

operation. If DQ1=1, write the Write-

Buffer-Programming-Abort-Reset

Yes

DQ7 = Data?

No

DQ1 = 1?

Yes

DQ5 = 1?

Yes

command. if DQ5=1, write the Reset

command.

Read DQ15 - DQ0 with

address = Last Loaded

Address

4. See Tables 16 and 17 for command

sequences required for write buffer

programming.

Yes

DQ7 = Data?

No

FAIL or ABORT

PASS

Figure 1. Write Buffer Programming Operation

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START

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 10 and Table 11 for program com-

mand sequence.

Figure 2. Program Operation

Program Suspend/Program Resume Command Sequence

The Program Suspend command allows the system to interrupt a programming

operation or a Write to Buffer programming operation so that data can be read

from any non-suspended sector. When the Program Suspend command is written

during a programming process, the device halts the program operation within 15

µs maximum (5µs typical) and updates the status bits. Addresses are not re-

quired when writing the Program Suspend command.

After the programming operation has been suspended, the system can read array

data from any non-suspended sector. The Program Suspend command may also

be issued during a programming operation while an erase is suspended. In this

case, data may be read from any addresses not in Erase Suspend or Program

Suspend. If a read is needed from the Secured Silicon Sector area (One-time Pro-

gram area), then user must use the proper command sequences to enter and exit

this region.

The system may also write the autoselect command sequence when the device

is in the Program Suspend mode. The system can read as many autoselect codes

as required. When the device exits the autoselect mode, the device reverts to the

Program Suspend mode, and is ready for another valid operation. See Autoselect

Command Sequence for more information.

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After the Program Resume command is written, the device reverts to program-

ming. The system can determine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard program operation. See Write Op-

eration Status for more information.

The system must write the Program Resume command (address bits are don’t

care) to exit the Program Suspend mode and continue the programming opera-

tion. Further writes of the Resume command are ignored. Another Program

Suspend command can be written after the device has resume programming.

Program Operation

or Write-to-Buffer

Sequence in Progress

Write Program Suspend

Command Sequence

Write address/data

XXXh/B0B0h

Command is also valid for

Erase-suspended-program

operations

Wait 15 µs

Autoselect and SecSi Sector

read operations are also allowed

Read data as

required

Data cannot be read from erase- or

program-suspended sectors

Done

No

reading?

Yes

Write Program Resume

Command Sequence

Write address/data

XXXh/3030h

Device reverts to

operation prior to

Program Suspend

Figure 3. Program Suspend/Program Resume

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is ini-

tiated by writing two unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the chip erase command,

which in turn invokes the Embedded Erase algorithm. The device does not require

the system to preprogram prior to erase. The Embedded Erase algorithm auto-

matically preprograms and verifies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to provide any controls or tim-

ings during these operations. Table 10 and Table 11 show the address and data

requirements for the chip erase command sequence.

When the Embedded Erase algorithm is complete, the device returns to the read

mode and addresses are no longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation

Status section for information on these status bits.

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Any commands written during the chip erase operation are ignored, including

erase suspend commands. However, note that a hardware reset immediately

terminates the erase operation. If that occurs, the chip erase command sequence

should be reinitiated once the device has returned to reading array data, to en-

sure data integrity.

Figure 4 illustrates the algorithm for the erase operation. Note that the Secured

Silicon Sector, autoselect, and CFI functions are unavailable when an

erase operation in is progress. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters, and Figure 16 section for

timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is

initiated by writing two unlock cycles, followed by a set-up command. Two addi-

tional unlock cycles are written, and are then followed by the address of the

sector to be erased, and the sector erase command. Table 10 and Table 11 shows

the address and data requirements for the sector erase command sequence.

The device does not require the system to preprogram prior to erase. The Em-

bedded Erase algorithm automatically programs and verifies the entire memory

for an all zero data pattern prior to electrical erase. The system is not required to

provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs occurs.

During the time-out period, additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer may be done in any

sequence, and the number of sectors may be from one sector to all sectors. The

time between these additional cycles must be less than 50 µs, otherwise erasure

may begin. Any sector erase address and command following the exceeded time-

out may or may not be accepted. It is recommended that processor interrupts be

disabled during this time to ensure all commands are accepted. The interrupts

can be re-enabled after the last Sector Erase command is written. Any com-

mand other than Sector Erase or Erase Suspend during the time-out

period resets the device to the read mode. Note that the Secured Silicon

Sector, autoselect, and CFI functions are unavailable when an erase op-

eration in is progress. The system must rewrite the command sequence and

any additional addresses and commands.

The system can monitor DQ3 to determine if the sector erase timer has timed out

(See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete, the device returns to reading

array data and addresses are no longer latched. The system can determine the

status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector.

Refer to the Write Operation Status section for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is

valid. All other commands are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that occurs, the sector erase

command sequence should be reinitiated once the device has returned to reading

array data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and

Program Operations table in the AC Characteristics section for parameters, and

Figure 16 section for timing diagrams.

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A d v a n c e I n f o r m a t i o n

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 10 and Table 11 for program command

sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 4. Erase Operation

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase

operation and then read data from, or program data to, any sector not selected

for erasure. This command is valid only during the sector erase operation, includ-

ing the 50 µs time-out period during the sector erase command sequence. The

Erase Suspend command is ignored if written during the chip erase operation or

Embedded Program algorithm.

When the Erase Suspend command is written during the sector erase operation,

the device requires a typical of 5 µs (maximum of 20 µs) to suspend the erase

operation. However, when the Erase Suspend command is written during the sec-

tor erase time-out, the device immediately terminates the time-out period and

suspends the erase operation.

After the erase operation has been suspended, the device enters the erase-sus-

pend-read mode. The system can read data from or program data to any sector

not selected for erasure. (The device “erase suspends” all sectors selected for

erasure.) Reading at any address within erase-suspended sectors produces sta-

tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively erasing or is erase-suspended. Refer

to the Write Operation Status section for information on these status bits.

After an erase-suspended program operation is complete, the device returns to

the erase-suspend-read mode. The system can determine the status of the pro-

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gram operation using the DQ7 or DQ6 status bits, just as in the standard word

program operation. Refer to the Write Operation Status section for more

information.

In the erase-suspend-read mode, the system can also issue the autoselect com-

mand sequence. Refer to the “Autoselect Command Sequence” section on page

50 sections for details.

To resume the sector erase operation, the system must write the Erase Resume

command. The address of the erase-suspended sector is required when writing

this command. Further writes of the Resume command are ignored. Another

Erase Suspend command can be written after the chip has resumed erasing.

Lock Register Command Set Definitions

The Lock Register Command Set permits the user to one-time program the Se-

cured Silicon Sector Protection Bit, Persistent Protection Mode Lock Bit, and

Password Protection Mode Lock Bit. The Lock Register bits are all readable after

an initial access delay.

The Lock Register Command Set Entry command sequence must be issued

prior to any of the following commands listed, to enable proper command

execution.

Note that issuing the Lock Register Command Set Entry command disables

reads and writes for the flash memory.

Lock Register Program Command

Lock Register Read Command

The Lock Register Command Set Exit command must be issued after the ex-

ecution of the commands to reset the device to read mode. Otherwise the device

will hang. If this happens, the flash device must be reset. Please refer to RESET#

for more information. It is important to note that the device will be in either Per-

sistent Protection mode or Password Protection mode depending on the mode

selected prior to the device hang.

For either the Secured Silicon Sector to be locked, or the device to be perma-

nently set to the Persistent Protection Mode or the Password Protection Mode, the

associated Lock Register bits must be programmed. Note that the Persistent

Protection Mode Lock Bit and Password Protection Mode Lock Bit can

never be programmed together at the same time. If so, the Lock Register

Program operation will abort.

The Lock Register Command Set Exit command must be initiated to re-

enable reads and writes to the main memory.

Password Protection Command Set Definitions

The Password Protection Command Set permits the user to program the 64-bit

password, verify the programming of the 64-bit password, and then later unlock

the device by issuing the valid 64-bit password.

The Password Protection Command Set Entry command sequence must be

issued prior to any of the following commands listed, to enable proper command

execution.

Note that issuing the Password Protection Command Set Entry command

disables reads and writes for the main memory.

Password Program Command

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A d v a n c e I n f o r m a t i o n

The Password Program command permits programming the password that is

used as part of the hardware protection scheme. The actual password is 64-bits

long. There is no special addressing order required for programming the pass-

word. The password is programmed in 8-bit or 16-bit portions. Each

portion requires a Password Program Command.

Once the Password is written and verified, the Password Protection Mode Lock Bit

in the “Lock Register” must be programmed in order to prevent verification. The

Password Program command is only capable of programming “0”s. Programming

a “1” after a cell is programmed as a “0” results in a time-out by the Embedded

Program Algorithm™ with the cell remaining as a “0”. The password is all F's when

shipped from the factory. All 64-bit password combinations are valid as a

password.

Password Read Command

The Password Read command is used to verify the Password. The Password is

verifiable only when the Password Protection Mode Lock Bit in the “Lock Register”

is not programmed. If the Password Protection Mode Lock Bit in the “Lock Regis-

ter” is programmed and the user attempts to read the Password, the device will

always drive all F's onto the DQ data bus.

The lower two address bits (A1-A0) for word mode and (A1-A-1) for by byte mode

are valid during the Password Read, Password Program, and Password Unlock

commands. Writing a “1” to any other address bits (A

-A2) will abort

MAX

the Password Read, Password Program, and Password Unlock com-

mands and return the device to reading memory array. The address bits

(A1-A0) for word mode and (A1-A-1) for byte mode must be entered into

the device sequentially for Password Read and Password Unlock

commands.

Password Unlock Command

The Password Unlock command is used to clear the PPB Lock Bit to the “unfreeze

state” so that the PPB bits can be modified. The exact password must be entered

in order for the unlocking function to occur. This 64-bit Password Unlock com-

mand sequence will take at least 2 µs to process each time to prevent a

hacker from running through the all 64-bit combinations in an attempt

to correctly match a password. If another password unlock is issued be-

fore the 64-bit password check execution window is completed, the

command will be ignored.

The Password Unlock function is accomplished by writing Password Unlock com-

mand and data to the device to perform the clearing of the PPB Lock Bit to the

“unfreeze state”. The password is 64 bits long. A1 and A0 are used for matching

in word mode and A1, A0, A-1 in byte mode. Writing the Password Unlock com-

mand does not need to be address order specific. An example sequence is

starting with the lower address A1-A0= 00, followed by A1-A0= 01, A1-A0= 10,

and A1-A0= 11 if device is configured to operate in word mode.

Approximately 2 µs is required for unlocking the device after the valid

64-bit password is given to the device. It is the responsibility of the mi-

croprocessor to keep track of the entering the portions of the 64-bit

password with the Password Unlock command, the order, and when to

read the PPB Lock bit to confirm successful password unlock. In order to

re-lock the device into the Password Protection Mode, the PPB Lock Bit Set com-

mand can be re-issued.

60

S29GLxxxN MirrorBit^TMFlash Family

S29GLxxxN_00_A4 June 14, 2004

A d v a n c e I n f o r m a t i o n

The Password Protection Command Set Exit command must be issued after

the execution of the commands listed previously to reset the device to read

mode. Otherwise the device will hang.

Note that issuing the Password Protection Command Set Exit command re-

enables reads and writes for the main memory.

Non-Volatile Sector Protection Command Set Definitions

The Non-Volatile Sector Protection Command Set permits the user to program the

Persistent Protection Bits (PPB bits), erase all of the Persistent Protection Bits

(PPB bits), and read the logic state of the Persistent Protection Bits (PPB bits).

The Non-Volatile Sector Protection Command Set Entry command se-

quence must be issued prior to any of the commands listed following to enable

proper command execution.

Note that issuing the Non-Volatile Sector Protection Command Set Entry

command disables reads and writes for the main memory.

PPB Program Command

The PPB Program command is used to program, or set, a given PPB bit. Each PPB

bit is individually programmed (but is bulk erased with the other PPB bits). The

specific sector address (A24-A16 for S29GL512N, A23-A16 for S29GL256N, A22-

A16 for S29GL128N) is written at the same time as the program command. If the

PPB Lock Bit is set to the “freeze state”, the PPB Program command will not exe-

cute and the command will time-out without programming the PPB bit.

All PPB Erase Command

The All PPB Erase command is used to erase all PPB bits in bulk. There is no

means for individually erasing a specific PPB bit. Unlike the PPB program, no spe-

cific sector address is required. However, when the All PPB Erase command is

issued, all Sector PPB bits are erased in parallel. If the PPB Lock Bit is set to

“freeze state”, the ALL PPB Erase command will not execute and the command

will time-out without erasing the PPB bits.

The device will preprogram all PPB bits prior to erasing when issuing the All PPB

Erase command. Also note that the total number of PPB program/erase cycles has

the same endurance as the flash memory array.

PPB Status Read Command

The programming state of the PPB for a given sector can be verified by writing a

PPB Status Read Command to the device. This requires an initial access time

latency.

The Non-Volatile Sector Protection Command Set Exit command must be

issued after the execution of the commands listed previously to reset the device

to read mode.

Note that issuing the Non-Volatile Sector Protection Command Set Exit

command re-enables reads and writes for the main memory.

Global Volatile Sector Protection Freeze Command Set

The Global Volatile Sector Protection Freeze Command Set permits the user to set

the PPB Lock Bit and reading the logic state of the PPB Lock Bit.

The Global Volatile Sector Protection Freeze Command Set Entry com-

mand sequence must be issued prior to any of the commands listed following to

enable proper command execution.

June 14, 2004 S29GLxxxN_00_A4

S29GLxxxN MirrorBit^TMFlash Family

61

A d v a n c e I n f o r m a t i o n

Reads and writes from the main memory are allowed.

PPB Lock Bit Set Command

The PPB Lock Bit Set command is used to set the PPB Lock Bit to the “freeze state”

if it is cleared either at reset or if the Password Unlock command was successfully

executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set

to the “freeze state”, it cannot be cleared unless the device is taken through a

power-on clear (for Persistent Protection Mode) or the Password Unlock command

is executed (for Password Protection Mode). If the Password Protection Mode Lock

Bit is programmed, the PPB Lock Bit status is reflected as set to the “freeze state”,

even after a power-on reset cycle.

PPB Lock Bit Status Read Command

The programming state of the PPB Lock Bit can be verified by executing a PPB

Lock Bit Status Read command to the device.

The Global Volatile Sector Protection Freeze Command Set Exit command

must be issued after the execution of the commands listed previously to reset the

device to read mode.

Volatile Sector Protection Command Set

The Volatile Sector Protection Command Set permits the user to set the Dynamic

Protection Bit (DYB) to the “protected state”, clear the Dynamic Protection Bit

(DYB) to the “unprotected state”, and read the logic state of the Dynamic Protec-

tion Bit (DYB).

The Volatile Sector Protection Command Set Entry command sequence

must be issued prior to any of the commands listed following to enable proper

command execution.

Note that issuing the Volatile Sector Protection Command Set Entry com-

mand disables reads for the bank selected with the command. Reads and

Writes for other banks excluding that bank are allowed.

DYB Set Command

DYB Clear Command

The DYB Set and DYB Clear commands are used to protect or unprotect a DYB for

a given sector. The high order address bits are issued at the same time as the

code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are ignored during the

data write cycle. The DYB bits are modifiable at any time, regardless of the state

of the PPB bit or PPB Lock Bit. The DYB bits are cleared to the “unprotected state”

at power-up or hardware reset.

—DYB Status Read Command

The programming state of the DYB bit for a given sector can be verified by writing

a DYB Status Read command to the device. This requires an initial access delay.

The Volatile Sector Protection Command Set Exit command must be issued

after the execution of the commands listed previously to reset the device to read

mode.

Note that issuing the Volatile Sector Protection Command Set Exit com-

mand re-enables reads and writes to the main memory.

Secured Silicon Sector Entry Command

The Secured Silicon Sector Entry command allows the following commands to be

executed

62

S29GLxxxN MirrorBit^TMFlash Family

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A d v a n c e I n f o r m a t i o n

Read from Secured Silicon Sector

Program to Secured Silicon Sector

Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon

Sector Exit command has to be issued to exit Secured Silicon Sector Mode.

Secured Silicon Sector Exit Command

The Secured Silicon Sector Exit command may be issued to exit the Secured Sil-

icon Sector Mode.

June 14, 2004 S29GLxxxN_00_A4

S29GLxxxN MirrorBit^TMFlash Family

63

A d v a n c e I n f o r m a t i o n

Command Definitions

Table 10. S29GL512N, S29GL256N, S29GL128N Command Definitions, x16

Bus Cycles (Notes 2–5)

Command (Notes)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (6)

1

4

RA

RD

F0

Reset (7)

XXX

555

Manufacturer ID

AA

2AA

55

555

90

X00

X01

01

Note

17

Note

17

Device ID

4

555

AA

227E

X0E

X0F

XX00

XX01

(SA)

X02

Sector Protect Verify

Secure Device Verify (9)

2AA

55

555

90

Note

10

X03

CFI Query (11)

1

4

3

1

3

2

6

1

555

SA

98

AA

29

AA

A0

80

90

AA

B0

30

Program

2AA

55

555

SA

A0

25

PA

SA

PD

Write to Buffer

WC

PA

PD

WBL

PD

Program Buffer to Flash (confirm)

Write-to-Buffer-Abort Reset (16)

Unlock Bypass

555

XXX

555

XXX

2AA

PA

55

PD

30

10

00

55

555

F0

20

Unlock Bypass Program (12)

Unlock Bypass Sector Erase (12)

Unlock Bypass Chip Erase (12)

Unlock Bypass Reset (13)

Chip Erase

SA

XXX

2AA

555

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Erase Suspend/Program Suspend (14)

Erase Resume/Program Resume (15)

Sector Command Definitions

Secured Silicon Sector Entry

3

4

555

AA

2AA

55

555

88

90

Secured Silicon Sector Exit (18)

555

AA

2AA

55

555

XX

00

Lock Register Command Set Definitions

Lock Register Command Set Entry

Lock Register Bits Program (22)

Lock Register Bits Read (22)

3

2

1

2

555

XXX

00

AA

A0

2AA

XXX

55

555

40

Data

90

Lock Register Command Set Exit (18, 23)

XXX

00

Password Protection Command Set Definitions

64

S29GLxxxN MirrorBit^TMFlash Family

S29GLxxxN_00_A4 June 14, 2004

A d v a n c e I n f o r m a t i o n

Bus Cycles (Notes 2–5)

Third Fourth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Command (Notes)

First

Second

Fifth

Sixth

Password Protection Command Set Entry

Password Program (20)

3

2

555

XXX

AA

A0

2AA

55

555

60

PWA

x

PWD

x

PWD

0

PWD

1

PWD

2

PWD

3

Password Read (19)

Password Unlock (19)

4

7

2

XXX

01

00

02

00

03

01

PWD

0

PWD

1

PWD

2

PWD

3

00

25

29

90

03

02

03

Password Protection Command Set Exit

(18, 23)

XXX

00

Non-Volatile Sector Protection Command Set Definitions

Nonvolatile Sector Protection Command

Set Entry

3

555

AA

2AA

55

555

C0

PPB Program (24, 25)

All PPB Erase

2

XXX

A0

80

SA

00

30

RD

(0)

PPB Status Read (25)

1

2

SA

Non-Volatile Sector Protection Command

Set Exit (18)

XXX

90

XXX

00

Global Non-Volatile Sector Protection Freeze Command Set Definitions

Global Non-Volatile Sector Protection

Freeze Command Set Entry

3

2

1

555

XXX

AA

A0

2AA

XXX

55

00

555

50

PPB Lock Bit Set (25)

RD

(0)

PPB Lock Status Read (25)

Global Non-Volatile Sector Protection

Freeze Command Set Exit (18)

2

XXX

90

XXX

00

Volatile Sector Protection Command Set Definitions

Volatile Sector Protection Command Set

Entry

3

555

AA

2AA

55

555

E0

DYB Set (24, 25)

DYB Clear (25)

2

XXX

A0

SA

00

01

RD

(0)

DYB Status Read (25)

1

2

SA

Volatile Sector Protection Command Set

Exit (18)

XXX

90

XXX

00

Legend:

X = Don’t care

RA = Address of the memory to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever

happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A_max–A16 uniquely select any sector.

WBL = Write Buffer Location. The address must be within the same write buffer page as PA.

June 14, 2004 S29GLxxxN_00_A4

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65

A d v a n c e I n f o r m a t i o n

WC = Word Count is the number of write buffer locations to load minus 1.

PWD = Password

PWD_x= Password word0, word1, word2, and word3.

DATA = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2)

= Password Protection Mode Lock Bit.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write

cycles.

4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles.

5. Address bits A_MAX:A16 are don't cares for unlock and command cycles, unless SA or PA required. (A_MAXis the Highest

Address pin.).

6. No unlock or command cycles required when reading array data.

7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high

(while the device is providing status data).

8. The fourth, fifth, and sixth cycle of the autoselect command sequence is a read cycle.

9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more

information. This is same as PPB Status Read except that the protect and unprotect statuses are inverted here.

10. The data value for DQ7 is “1” for a serialized and protected OTP region and “0” for an unserialized and unprotected Secured

Silicon Sector region. See “Secured Silicon Sector Flash Memory Region” for more information. For Am29LVxxxMH: XX18h/

18h = Not Factory Locked. XX98h/98h = Factory Locked. For Am29LVxxxML: XX08h/08h = Not Factory Locked. XX88h/88h

= Factory Locked.

11. Command is valid when device is ready to read array data or when device is in autoselect mode.

12. The Unlock-Bypass command is required prior to the Unlock-Bypass-Program command.

13. The Unlock-Bypass-Reset command is required to return to reading array data when the device is in the unlock bypass

mode.

14. The system may read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the

Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.

15. The Erase Resume/Program Resume command is valid only during the Erase Suspend/Program Suspend modes.

16. Issue this command sequence to return to READ mode after detecting device is in a Write-to-Buffer-Abort state. NOTE: the

full command sequence is required if resetting out of ABORT while using Unlock Bypass Mode.

17. S29GL512NH/L = 2223h/23h, 220h/01h; S29GL256NH/L = 2222h/22h, 2201h/01h; S29GL128NH/L = 2221h/21h, 2201h/

01h.

18. The Exit command returns the device to reading the array.

19. Note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.

20. For PWDx, only one portion of the password can be programmed per each “A0” command.

21. The All PPB Erase command embeds programming of all PPB bits before erasure.

22. All Lock Register bits are one-time programmable. Note that the program state = “0” and the erase state = “1”. Also note

that of both the Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the

same time or the Lock Register Bits Program operation will abort and return the device to read mode. Lock Register bits that

are reserved for future use will default to “1's”. The Lock Register is shipped out as “FFFF's” before Lock Register Bit program

execution.

23. If any of the Entry command was initiated, an Exit command must be issued to reset the device into read mode. Otherwise

the device will hang.

24. If ACC = V_HH, sector protection will match when ACC = V_IH

25. Protected State = “00h”, Unprotected State = “01h”.

66

S29GLxxxN MirrorBit^TMFlash Family

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A d v a n c e I n f o r m a t i o n

Table 11. S29GL512N, S29GL256N, S29GL128N Command Definitions, x8

Bus Cycles (Notes 2–5)

Command (Notes)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (6)

1

4

RA

RD

F0

Reset (7)

XXX

AAA

Manufacturer ID

AA

555

55

AAA

90

9

X00

X02

01

Note

17

Note

17

Device ID

4

AAA

AA

XX7E

X1C

X1E

00

01

(SA)

X04

Sector Protect Verify

Secure Device Verify (9)

555

55

AAA

90

Note

10

X06

SA

CFI Query (11)

1

3

1

3

2

6

1

AAA

SA

98

AA

29

AA

90

AA

B0

30

Write to Buffer

555

55

SA

25

F0

WC

PA

PD

WBL

PD

Program Buffer to Flash (confirm)

Write-to-Buffer-Abort Reset (16)

Unlock Bypass Reset (13)

Chip Erase

AAA

XXX

AAA

XXX

PA

55

00

55

555

XXX

555

AAA

80

AAA

AA

555

55

AAA

SA

10

30

Sector Erase

Erase Suspend/Program Suspend (14)

Erase Resume/Program Resume (15)

Secured Silicon Sector Command Definitions

Secured Silicon Sector Entry

3

AAA

AA

555

55

AAA

88

Secured Silicon Sector Exit (18)

4

AAA

AA

555

55

AAA

90

XX

00

Lock Register Command Set Definitions

Lock Register Command Set Entry

Lock Register Bits Program (22)

Lock Register Bits Read (22)

3

2

1

2

AAA

XXX

00

AA

A0

555

XXX

55

AAA

40

Data

90

Lock Register Command Set Exit (18, 23)

XXX

00

Password Protection Command Set Definitions

June 14, 2004 S29GLxxxN_00_A4

S29GLxxxN MirrorBit^TMFlash Family

67

A d v a n c e I n f o r m a t i o n

Bus Cycles (Notes 2–5)

Command (Notes)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Password Protection Command Set Entry

Password Program (20)

3

2

AAA

XXX

AA

A0

555

55

AAA

02

60

PWA PWD

x

PWD

0

PWD

1

00

06

01

PWD

2

PWD

3

PWD

4

PWD

5

Password Read (19)

Password Unlock (19)

8

03

04

05

03

PWD

6

PWD

7

07

00

PWD

0

PWD

1

PWD

2

PWD

3

00

25

03

00

06

01

07

02

00

11

2

PWD

4

PWD

5

PWD

6

PWD

7

04

05

29

Password Protection Command Set Exit

(18, 23)

XXX

90

XXX

00

Non-Volatile Sector Protection Command Set Definitions

Nonvolatile Sector Protection Command

Set Entry

3

AAA

AA

55

AAA

C0

PPB Program (24, 25)

All PPB Erase

2

XXX

A0

80

SA

00

30

RD

(0)

PPB Status Read (25)

1

2

SA

Non-Volatile Sector Protection Command

Set Exit (18)

XXX

90

XXX

00

Global Non-Volatile Sector Protection Freeze Command Set Definitions

Global Non-Volatile Sector Protection

Freeze Command Set Entry

3

2

1

AAA

XXX

AA

A0

555

XXX

55

00

AAA

50

PPB Lock Bit Set (25)

RD

(0)

PPB Lock Status Read (25)

Global Non-Volatile Sector Protection

Freeze Command Set Exit (18)

2

XXX

90

XXX

00

Volatile Sector Protection Command Set Definitions

Volatile Sector Protection Command Set

Entry

3

AAA

AA

555

55

AAA

E0

DYB Set (24, 25)

DYB Clear (25)

2

XXX

A0

SA

00

01

RD

(0)

DYB Status Read (25)

1

2

SA

Volatile Sector Protection Command Set

Exit (18)

XXX

90

XXX

00

Legend:

X = Don’t care

RA = Address of the memory to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever

happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first.

68

S29GLxxxN MirrorBit^TMFlash Family

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A d v a n c e I n f o r m a t i o n

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A_max–A16 uniquely select any sector.

WBL = Write Buffer Location. The address must be within the same write buffer page as PA.

WC = Word Count is the number of write buffer locations to load minus 1.

PWD = Password

PWD_x= Password word0, word1, word2, word3. word 4, word 5, word 6, and word 7.