S71JL064H80BFI020 [SPANSION]
Memory Circuit, 4MX16, CMOS, PBGA73, 8 X 11.60 MM, LEAD FREE, FBGA-73;
| 型号： | S71JL064H80BFI020 |
| 厂家： | 
SPANSION |
| 描述： | Memory Circuit, 4MX16, CMOS, PBGA73, 8 X 11.60 MM, LEAD FREE, FBGA-73 |
| 文件： | 总153页 (文件大小：3659K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S71JL128HC0/128HB0/064HB0/
064HA0/064H80
Stacked Multi-Chip Product (MCP) Flash Memory
and pSRAM CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memories and
Static RAM/Pseudo-static RAM
PRELIMINARY
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The S71JLxxxH Series is a product line of stacked Multi-Chip
Products (MCP) and consists of
MCP Features
Operating Voltage Range of 2.7 to 3.3 V
One or more S29JL064H Flash devices
High Performance
SRAM or pSRAM options
— 8Mb x 8/x 16 SRAM
— 16Mb x 16-only SRAM
— pSRAM x 16 only:
8Mb pSRAM
— Access time as fast as 55 ns
Packages
— 73-ball FBGA—8 x 11.6 mm
— 88-ball FBGA—8 x 11.6 mm
Operating Temperatures
— Wireless: –25°C to +85°C
— Industrial: –40°C to +85°C
16Mb pSRAM
32Mb pSRAM
64Mb pSRAM
The products covered by this document are listed below. For
details about their specifications, please refer to the individual
constituent data sheets for further details.
MCP
Number of S29JL064H
Tot a l Fl as h De ns i t y
64Mb
SRAM/pSRAM Density
S71JL064H80
S71JL064HA0
S71JL064HB0
S71JL128HB0
S71JL128HC0
1
1
1
2
2
8Mb
64Mb
16Mb
32Mb
32Mb
64Mb
64Mb
128Mb
128Mb
Notes:
1. This MCP is only guaranteed to operate @ 2.7 - 3.3 V regardless of component operating ranges.
2. BYTE# operation is only supported on the S71JL064H80xx0x.
Publication Number S71JLxxxHxx_00 Revision A Amendment 3 Issue Date May 25, 2004
P r e l i m i n a r y
Product Selector Guide
FlashAccess RAMAccess
Device-Model #
SRAM/pSRAM Density
SRAM/pSRAM Type
Supplier
Time (ns)
Time (ns)
Packages
FLB073
FLB073
FLJ073
FLJ073
FLJ073
S71JL064H80Bxx01
S71JL064H80Bxx02
S71JL064H80Bxx10
S71JL064H80Bxx11
S71JL064H80Bxx12
8Mb
8Mb
8Mb
8Mb
8Mb
SRAM - x8/x16
SRAM - x8/x16
pSRAM - x16
pSRAM - x16
pSRAM - x16
Supplier 1
Supplier 1
Supplier 2
Supplier 2
Supplier 2
70
85
55
70
85
70
85
55
70
85
S71JL064HA0Bxx01
S71JL064HA0Bxx02
S71JL064HA0Bxx10
S71JL064HA0Bxx11
S71JL064HA0Bxx12
S71JL064HA0Bxx62
16Mb
16Mb
16Mb
16Mb
16Mb
16Mb
SRAM - x16
SRAM - x16
pSRAM - x16
pSRAM - x16
pSRAM - x16
pSRAM - x16
Supplier 1
Supplier 1
Supplier 2
Supplier 2
Supplier 2
Supplier 4
70
85
55
70
85
70
70
85
55
70
85
70
FLB073
FLB073
FLJ073
FLJ073
FLJ073
FLJ073
S71JL128HB0Bxx01
S71JL128HB0Bxx02
32Mb
32Mb
pSRAM - x16
pSRAM - x16
Supplier 3
Supplier 3
70
85
70
85
FTA073
FTA073
S71JL128HC0Bxx01
S71JL128HC0Bxx02
64Mb
64Mb
pSRAM - x16
pSRAM - x16
Supplier 3
Supplier 3
70
85
70
85
FTA088
FTA088
2
S71JL128HC0/128HB0/064HB0/064HA0/064H80
S71JLxxxHxx_00A3 May 25, 2004
A d v a n c e I n f o r m a t i o n
TABLE OF CONTENTS
Accelerated Program Operation .................................................................8
Autoselect Functions .......................................................................................8
Simultaneous Read/Write Operations with Zero Latency .....................8
Standby Mode .........................................................................................................9
Automatic Sleep Mode ....................................................................................... 9
RESET#: Hardware Reset Pin ........................................................................... 9
Output Disable Mode ........................................................................................10
Table 2. S29JL064H Sector Architecture ............................... 11
Table 3. Bank Address ........................................................ 14
Table 4. SecSiTM Sector Addresses....................................... 14
Autoselect Mode .................................................................................................14
Sector/Sector Block Protection and Unprotection ..................................15
Table 5. S29JL064H Boot Sector/Sector Block Addresses for
Protection/Unprotection ...................................................... 15
Write Protect (WP#) ........................................................................................17
Table 6. WP#/ACC Modes ................................................... 17
Temporary Sector Unprotect .........................................................................17
Figure 1. Temporary Sector Unprotect Operation ................... 18
Figure 2. In-System Sector Protect/Unprotect Algorithms ....... 19
SecSi™ (Secured Silicon) Sector
Flash Memory Region ........................................................................................20
Figure 3. SecSi Sector Protect Verify .................................... 21
Hardware Data Protection ..............................................................................21
Low VCC Write Inhibit .................................................................................21
Write Pulse “Glitch” Protection ...............................................................22
Logical Inhibit ...................................................................................................22
Power-Up Write Inhibit ...............................................................................22
Common Flash Memory Interface (CFI) . . . . . . .22
Table 1. CFI Query Identification String................................ 23
Table 7. System Interface String ......................................... 23
Table 2. Device Geometry Definition .................................... 24
Table 3. Primary Vendor-Specific Extended Query.................. 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 26
Reading Array Data ...........................................................................................26
Reset Command .................................................................................................26
Autoselect Command Sequence .................................................................... 27
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence ..........................................................................................27
Byte/Word Program Command Sequence ................................................. 27
Unlock Bypass Command Sequence ........................................................28
Figure 4. Program Operation............................................... 29
Chip Erase Command Sequence ...................................................................29
Sector Erase Command Sequence ................................................................30
Figure 5. Erase Operation ................................................... 31
Erase Suspend/Erase Resume Commands ................................................... 31
Table 4. S29JL064H Command Definitions ............................ 33
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 34
DQ7: Data# Polling ............................................................................................ 34
Figure 6. Data# Polling Algorithm ........................................ 35
RY/BY#: Ready/Busy# ........................................................................................36
DQ6: Toggle Bit I ............................................................................................... 36
Figure 7. Toggle Bit Algorithm............................................. 37
DQ2: Toggle Bit II .............................................................................................. 37
Reading Toggle Bits DQ6/DQ2 .....................................................................38
DQ5: Exceeded Timing Limits ........................................................................38
DQ3: Sector Erase Timer ................................................................................38
Table 8. Write Operation Status ........................................... 39
S71JL128HC0/128HB0/064HB0/064HA0/064H80
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MCP Block Diagram of S71JL064H80, Model Numbers 01/02 ................7
MCP Block Diagram of S71JL064H80, Model Numbers 10/11/12 ..............7
MCP Block Diagram of S71JL064HA0, Model Numbers 01/02 ................8
MCP Block Diagram of S71JL064HA0, Model Numbers 10/11/12/62 .......8
MCP Block Diagram of S71JL064HB0, Model Numbers 00/01/02 ..........9
MCP Block Diagram of S71JL128HB0, Model Numbers 00/01/02 ......... 10
MCP Block Diagram of S71JL128HC0, Model Numbers 00/01/02 ......... 11
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . 12
Connection Diagram of S71JL064H80, Model Numbers 01/02 ............. 12
Special Package Handling Instructions .......................................................13
Pin Description .................................................................................................13
Logic Symbol .................................................................................................... 14
Connection Diagram of S71JL064H80, Model Numbers 10/11/12 ............15
Pin Description ................................................................................................ 16
Logic Symbol .................................................................................................... 16
Connection Diagram of S71JL064HA0, Model Numbers 01/02 ..............17
Pin Description ................................................................................................ 18
Logic Symbol .................................................................................................... 19
Connection Diagram of S71JL064HA0, Model Numbers 10/11/12/62 ... 20
Pin Description ................................................................................................ 21
Logic Symbol .................................................................................................... 21
Connection Diagram of S71JL064HB0, Model Numbers 00/01/02 ...... 22
Pin Description ................................................................................................23
Logic Symbol ....................................................................................................23
Connection Diagram of S71JL128HB0, Model Numbers 00/01/02 ....... 24
Pin Description ................................................................................................25
Logic Symbol ....................................................................................................25
Connection Diagram of S71JL128HC0, Model Numbers 00/01/02 ...... 26
Special Package Handling Instructions ..................................................... 26
Pin Description ................................................................................................27
Logic Symbol ....................................................................................................27
Look-ahead Connection Diagram ................................................................. 28
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .30
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 34
FLB073 ....................................................................................................................34
FLJ073 ......................................................................................................................35
FTA073 ...................................................................................................................36
FTA088 ..................................................................................................................37
S29JL064H
General Description 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . .6
Table 1. S29JL064H Device Bus Operations ............................ 6
Word/Byte Configuration .................................................................................. 7
Requirements for Reading Array Data ...........................................................7
Writing Commands/Command Sequences ...................................................7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . .40
Figure 8. Maximum Negative Overshoot Waveform ................ 40
Figure 9. Maximum Positive Overshoot Waveform.................. 40
May 25, 2004 S71JLxxxHxx_00A3
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A d v a n c e I n f o r m a t i o n
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 40
8 Mb pSRAM (supplier 2)
Wireless (W) Devices ..................................................................................40
Industrial (I) Devices .....................................................................................40
VCC Supply Voltages .....................................................................................40
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 41
CMOS Compatible ............................................................................................. 41
Zero-Power Flash ........................................................................................... 42
Figure 10. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents)................................................... 42
Figure 11. Typical ICC1 vs. Frequency.................................... 42
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
General Description . . . . . . . . . . . . . . . . . . . . . . . 67
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 34. Functional Block Diagram .................................... 68
Table 9. Functional Description ............................................ 68
Absolute Maximum Ratings (See Note) . . . . . . . 68
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 69
Operating Characteristics (Over Specified Temperature Range) .......69
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 12. Test Setup ........................................................ 43
Key To Switching Waveforms . . . . . . . . . . . . . . . .43
Figure 13. Input Waveforms and Measurement Levels............. 43
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .44
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 10. Timing Test Conditions ......................................... 69
Table 11. Timings .............................................................. 70
Timing Diagrams ..................................................................................................71
Figure 35. Timing of Read Cycle (CE1# = OE# = VIL, WE# = CE2
= VIH).............................................................................. 71
Figure 36. Timing Waveform of Read Cycle (WE# = VIH) ........ 71
Figure 37. Timing Waveform of Write Cycle (WE# Control) ..... 72
Figure 38. Timing Waveform of Write Cycle (CE1# Control)..... 72
Read-Only Operations .................................................................................... 44
Figure 14. Read Operation Timings....................................... 44
Hardware Reset (RESET#) ...............................................................................45
Figure 15. Reset Timings..................................................... 45
Word/Byte Configuration (BYTE#) ............................................................. 46
Figure 16. BYTE# Timings for Read Operations ...................... 47
Figure 17. BYTE# Timings for Write Operations...................... 47
Erase and Program Operations ..................................................................... 48
Figure 18. Program Operation Timings .................................. 49
Figure 19. Accelerated Program Timing Diagram .................... 49
Figure 20. Chip/Sector Erase Operation Timings..................... 50
Figure 21. Back-to-back Read/Write Cycle Timings ................. 51
Figure 22. Data# Polling Timings (During Embedded Algorithms) .
51
16 Mb pSRAM (supplier 2)
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
General Description . . . . . . . . . . . . . . . . . . . . . . . 73
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 39. Functional Block Diagram .................................... 74
Table 12. Functional Description .......................................... 74
Absolute Maximum Ratings (See Note) . . . . . . . 75
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 75
Operating Characteristics (Over Specified Temperature Range) ....... 75
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 76
Timing Test Conditions ....................................................................................76
Timings ...................................................................................................................76
Figure 23. Toggle Bit Timings (During Embedded Algorithms) .. 52
Figure 24. DQ2 vs. DQ6 ...................................................... 52
Temporary Sector Unprotect .........................................................................53
Figure 25. Temporary Sector Unprotect Timing Diagram.......... 53
Figure 26. Sector/Sector Block Protect and
Timings ................................................................................................................... 77
Figure 40. Timing of Read Cycle (CE1# = OE# = VIL, WE# = CE2
= VIH).............................................................................. 77
Figure 41. Timing Waveform of Read Cycle (WE# = VIH) ........ 77
Figure 42. Timing Waveform of Write Cycle (WE# Control) ..... 78
Figure 43. Timing Waveform of Write Cycle (CE1# Control, CE2 =
High) ............................................................................... 78
Unprotect Timing Diagram................................................... 54
Alternate CE# Controlled Erase and Program Operations ..................55
Figure 27. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.............................................................. 56
Erase And Programming Performance . . . . . . . .57
16 Mb SRAM (supplier 1)
16 Mb pSRAM (supplier 4)
Functional Description . . . . . . . . . . . . . . . . . . . . . 59
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 59
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60
Recommended DC Operating Conditions (Note 1) ............................... 60
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Absolute Maxumum Ratings (see Note) . . . . . . 80
Capacitance (f=1MHz, TA=25°C) ................................................................... 60
DC Operating Characteristics .......................................................................60
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 61
Read/Write Charcteristics (VCC=2.7-3.3V) ................................................. 61
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 13. DC Recommended Operating Conditions ................. 80
Data Retention Characteristics ...................................................................... 61
Timing Diagrams ................................................................................................. 62
Figure 28. Timing Waveform of Read Cycle(1) (address controlled,
CD#1=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL)......... 62
Figure 29. Timing Waveform of Read Cycle(2) (WE#=VIH)....... 62
Figure 30. Timing Waveform of Write Cycle(1) (WE# controlled) ..
63
Figure 31. Timing Waveform of Write Cycle(2) (CS# controlled)...
63
Figure 32. Timing Waveform of Write Cycle(3) (UB#, LB#
controlled) ........................................................................ 64
Figure 33. Data Retention Waveform .................................... 65
Table 14. DC Characteristics (TA = -25°C to 85°C, VDD = 2.6 to
3.3V) ............................................................................... 81
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 15. AC Characteristics and Operating Conditions (TA = -25°C
to 85°C, VDD = 2.6 to 3.3V) ................................................ 81
Table 16. AC Test Conditions ............................................... 82
Figure 44. AC Test Loads.................................................... 82
Figure 45. State Diagram ................................................... 83
Table 17. Standby Mode Characteristics ................................ 83
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 46. Read Cycle 1—Addressed Controlled ..................... 83
Figure 47. Read Cycle 2—CS1# Controlled............................ 84
4
S71JLxxxHxx_00A3 May 25, 2004
A d v a n c e I n f o r m a t i o n
Figure 48. Write Cycle 1—WE# Controlled ............................. 84
3.3V) ............................................................................... 99
Table 25. Capacitance (TA = 25 C, f = 1 MHz) ....................... 99
Figure 49. Write Cycle 2—CS1# Controlled............................ 85
Figure 50. Write Cycle3—UB#, LB# Controlled....................... 85
Figure 51. Deep Power-down Mode....................................... 86
Figure 52. Power-up Mode................................................... 86
Figure 53. Abnormal Timing................................................. 86
°
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 26. AC Characteristics and Operating Conditions (TA = -25
°C
to 85 C, VDD = 2.6 to 3.3V) ................................................ 99
°
Table 27. AC Test Conditions ............................................. 100
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 62. Read Cycle ...................................................... 101
Figure 63. Page Read Cycle (8 words access) ...................... 102
Figure 64. Write Cycle 1 (WE# controlled) .......................... 103
Figure 65. Write Cycle 2 (CE# controlled)........................... 104
Figure 66. Deep Power-down Timing.................................. 104
Figure 67. Power-on Timing .............................................. 104
Figure 68. Read Address Skew Provisions ........................... 105
Figure 69. Write Address Skew Provisions........................... 105
32 Mb pSRAM (Supplier 3)
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Absolute Maxumum Ratings . . . . . . . . . . . . . . . . 88
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 18. DC Recommended Operating Conditions (TA = -40
85 C) ............................................................................... 88
Table 19. DC Characteristics (TA = -40 C to 85 C, VDD = 2.6 to
3.3V) ............................................................................... 89
Table 20. Capacitance (TA = 25 C, f = 1 MHz) ....................... 89
°C to
8 Mb SRAM (supplier 1)
°
°
°
Functional Description . . . . . . . . . . . . . . . . . . . . . 107
Table 28. Word Mode ....................................................... 107
Table 29. Byte Mode ........................................................ 107
Absolute Maximum Ratings . . . . . . . . . . . . . . . 108
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 108
Recommended DC Operating Conditions ............................................... 108
°
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 21. AC Characteristics and Operating Conditions (TA = -40
°C
to 85 C, VDD = 2.6 to 3.3V) ................................................ 89
Table 22. AC Test Conditions .............................................. 90
°
Capacitance (f=1MHz, TA=25°C) ................................................................. 108
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 54. Read Cycle......................................................... 91
Figure 55. Page Read Cycle (8 words access)......................... 92
Figure 56. Write Cycle 1 (WE# controlled)............................. 93
Figure 57. Write Cycle 2 (CE# controlled).............................. 94
Figure 58. Deep Power-down Timing..................................... 94
Figure 59. Power-on Timing................................................. 94
Figure 60. Read Address Skew Provisions.............................. 95
Figure 61. Write Address Skew Provisions.............................. 95
DC and Operating Characteristics ............................................................. 109
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 110
Read/Write Charcteristics (VCC=2.7-3.3V) ................................................110
Data Retention Characteristics .....................................................................110
Timing Diagrams ..................................................................................................111
Figure 70. Timing Waveform of Read Cycle(1) (address controlled,
CD#1=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL)...... 111
Figure 71. Timing Waveform of Read Cycle(2) (WE#=VIH, if BYTE#
is low, ignore UB#/LB# timing)......................................... 111
Figure 72. Timing Waveform of Write Cycle(1) (WE# controlled, if
BYTE# is low, ignore UB#/LB# timing)............................... 111
Figure 73. Timing Waveform of Write Cycle(2) (CE1# controlled, if
BYTE# is low, ignore UB#/LB# timing)............................... 112
Figure 74. Timing Waveform of Write Cycle(3) (UB#, LB#
64 Mb pSRAM (supplier 3)
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Absolute Maxumum Ratings . . . . . . . . . . . . . . . . 98
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 98
controlled, BYTE# must be high) ....................................... 112
Data Retention Waveforms ............................................................................113
Figure 75. CE1# Controlled............................................... 113
Figure 76. CS2 Controlled................................................. 113
Table 23. DC Recommended Operating Conditions (TA = -25
°C to
85 C) ............................................................................... 98
Table 24. DC Characteristics (TA = -25°C to 85°C, VDD = 2.6 to
°
Revision Summary
May 25, 2004 S71JLxxxHxx_00A3
5
A d v a n c e I n f o r m a t i o n
6
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
Block Diagrams
MCP Block Diagram of S71JL064H80, Model Numbers 01/02
VCC
f
VSS
A21 to A0
RY/BY#
A21 to A0
A–1
WP#/ACC
RESET#
CE#f
64 MBit
Flash Memory
DQ15/A-1 to DQ0
CIOf
DQ15/A–1 to DQ0
VCCs
VSS
A18 to A0
SA
8 MBit
SRAM
LB#
UB#
WE#
DQ15/A-1 to DQ0
OE#
CE1#s
CE2s
CIOs
MCP Block Diagram of S71JL064H80, Model Numbers 10/11/12
VCC
f
VSS
RY/BY#
A21 to A0
A21 to A0
WP#/ACC
RESET#
CE#f
64 MBit
Flash Memory
DQ15 to DQ0
DQ15 to DQ0
VCCs
VSS
RY/BY#
A18 to A0
8 MBit
PSRAM
LB#
DQ15 to DQ0
UB#
WE#
OE#
CE1#s
CE2s
May 25, 2004 S71JLxxxHxx_00A3
7
P r e l i m i n a r y
MCP Block Diagram of S71JL064HA0, Model Numbers 01/02
VCC
f
VSS
A21 to A0
RY/BY#
A21 to A0
WP#/ACC
RESET#
CE#f
64 MBit
Flash Memory
DQ15 to DQ0
DQ15 to DQ0
VCCs
VSS
A19 to A0
16 MBit
SRAM
LB#
DQ15 to DQ0
UB#
WE#
OE#
CE1#s
CE2s
MCP Block Diagram of S71JL064HA0, Model Numbers 10/11/12/62
VCC
f
VSS
A21 to A0
RY/BY#
A21 to A0
WP#/ACC
RESET#
CE#f
64 MBit
Flash Memory
DQ15 to DQ0
DQ15 to DQ0
VCCs
VSS
A19 to A0
16 MBit
pSRAM
LB#
DQ15 to DQ0
UB#
WE#
OE#
CE1#s
CE2s
8
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
MCP Block Diagram of S71JL064HB0, Model Numbers 00/01/02
VCC
f
VSS
A21 to A0
RY/BY#
A21 to A0
WP#/ACC
RESET#
CE#f
64 MBit
Flash Memory
DQ15 to DQ0
DQ15 to DQ0
VCCs
VSS
A20 to A0
16 MBit
pSRAM
LB#
DQ15 to DQ0
UB#
WE#
OE#
CE1#s
CE2s
May 25, 2004 S71JLxxxHxx_00A3
9
P r e l i m i n a r y
MCP Block Diagram of S71JL128HB0, Model Numbers 00/01/02
VCC
f
VSS
A21 to A0
64 MBit
Flash Memory
#1
DQ15 to DQ0
CE#f1
VCC
f
VSS
A21 to A0
A21 to A0
RY/BY#
WP#/ACC
RESET#
64 MBit
Flash Memory
#2
DQ15 to DQ0
CE#f2
DQ15 to DQ0
VCCs
VSS
A20 to A0
32 MBit
pSRAM
LB#
UB#
WE#
DQ15 to DQ0
OE#
CE1#s
CE2s
10
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
MCP Block Diagram of S71JL128HC0, Model Numbers 00/01/02
VCC
f
VSS
A21 to A0
RY/BY#1
RESET#1
CE#f1
64 MBit
Flash Memory
#1
DQ15 to DQ0
VCC
f
VSS
A21 to A0
A21 to A0
RY/BY#2
WP#/ACC
RESET#2
CE#f2
64 MBit
Flash Memory
#2
DQ15 to DQ0
DQ15 to DQ0
VCCs
VSS
A21 to A0
64 MBit
pSRAM
LB#
UB#
WE#
DQ15 to DQ0
OE#
CE1#ps
CE2ps
May 25, 2004 S71JLxxxHxx_00A3
11
P r e l i m i n a r y
Connection Diagrams
Connection Diagram of S71JL064H80, Model Numbers 01/02
73-Ball FBGA
Top View
Flash only
SRAM only
A1
A10
NC
NC
B1
B5
NC
C5
B6
B10
NC
NC
NC
Shared
C1
C3
C4
C6
C7
C8
NC
A7
LB# WP#/ACC WE#
A8
A11
D2
A3
D3
A6
D4
D5
D6
D7
A19
E7
A9
D8
A12
E8
A13
F8
D9
A15
E9
A21
F9
NC
UB# RESET# CE2s
E5
E2
A2
E3
A5
E4
E6
A18 RY/BY# A20
F1
NC
G1
NC
F2
A1
F3
A4
F4
A17
G4
DQ1
F7
F10
A10
G7
DQ6
H7
A14
G8
SA
NC
G2
A0
G3
G9 G10
V
SS
A16
NC
H2
CE#f
J2
H3
OE#
J3
H4
DQ9
J4
H5
DQ3
J5
H6
DQ4
J6
H8
H9
DQ13 DQ15/A-1 CIOf
J7
DQ12
K7
J8
DQ7
K8
J9
V
CC
f
V
s
CC
CE1#s DQ0
DQ10
K4
V
SS
K3
K5
K6
DQ8
DQ2
DQ11 CIOs
DQ5
DQ14
L1
NC
M1
NC
L5
L6
L10
NC
NC
NC
M10
NC
12
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(FBGA). The package and/or data integrity may be compromised if the package
body is exposed to temperatures above 150°C for prolonged periods of time.
Pin Description
A18–A0
A21–A19, A-1
SA
DQ15–DQ0
CE#f
CE#s
OE#
WE#
RY/BY#
UB#
=
=
=
=
=
=
=
=
=
=
=
=
19 Address Inputs (Common)
4 Address Inputs (Flash)
Highest Order Address Pin (SRAM) Byte mode
16 Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Output
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
LB#
CIOf
I/O Configuration (Flash)
CIOf = VIH = Word mode (x16),
CIOf = VIL = Byte mode (x8)
CIOs
=
I/O Configuration (SRAM)
CIOs = VIH = Word mode (x16),
CIOs = VIL = Byte mode (x8)
RESET#
WP#/ACC
=
=
=
Hardware Reset Pin, Active Low
Hardware Write Protect/Acceleration Pin (Flash)
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
VCCf
VCC
VSS
NC
s
=
=
=
SRAM Power Supply
Device Ground (Common)
Pin Not Connected Internally
May 25, 2004 S71JLxxxHxx_00A3
13
P r e l i m i n a r y
Logic Symbol
19
A18–A0
A21–A19, A-1
SA
16 or 8
CE#f
DQ15–DQ0
RY/BY#
CE1#s
CE2s
OE#
WE#
WP#/ACC
RESET#
UB#
LB#
CIOf
CIOs
14
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
Connection Diagram of S71JL064H80, Model Numbers 10/11/12
73-Ball FBGA
Top View
Flash only
SRAM only
A1
A10
NC
NC
B1
B5
NC
C5
B6
B10
NC
NC
NC
Shared
C1
C3
C4
C6
C7
C8
NC
A7
LB# WP#/ACC WE#
A8
A11
D2
A3
D3
A6
D4
D5
D6
D7
A19
E7
A9
D8
A12
E8
A13
F8
D9
A15
E9
A21
F9
NC
UB# RESET# CE2s
E5
E2
A2
E3
A5
E4
E6
A18 RY/BY# A20
F1
NC
G1
NC
F2
A1
F3
A4
F4
A17
G4
DQ1
F7
F10
A10
G7
DQ6
H7
A14
G8
NC
NC
G2
A0
G3
G9 G10
V
SS
A16
H9
NC
J9
NC
H2
CE#f
J2
H3
OE#
J3
H4
DQ9
J4
H5
DQ3
J5
H6
DQ4
J6
H8
DQ13 DQ15
J7
DQ12
K7
J8
DQ7
K8
V
CC
f
V
s
CC
CE1#s DQ0
DQ10
K4
V
SS
K3
K5
K6
NC
L6
NC
DQ8
DQ2
DQ11
L5
DQ5
DQ14
L1
NC
M1
NC
L10
NC
NC
M10
NC
May 25, 2004 S71JLxxxHxx_00A3
15
P r e l i m i n a r y
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(TSOP, BGA, PDIP, SSOP, PLCC). The package and/or data integrity may be com-
promised if the package body is exposed to temperatures above 150°C for
prolonged periods of time.
Pin Description
A18–A0
A21–A19
DQ15–DQ0
CE#f
CE1#s
CE2s
OE#
WE#
RY/BY#
UB#
LB#
=
=
=
=
=
=
=
=
=
=
=
=
=
=
19 Address Inputs (Common)
2 Address Inputs (Flash)
16 Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable 1 (pSRAM)
Chip Enable 2 (pSRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Output
Upper Byte Control (pSRAM)
Lower Byte Control (pSRAM)
Hardware Reset Pin, Active Low
Hardware Write Protect/Acceleration Pin (Flash)
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
RESET#
WP#/ACC
VCCf
VCC
VSS
NC
s
=
=
=
pSRAM Power Supply
Device Ground (Common)
Pin Not Connected Internally
Logic Symbol
19
A18–A0
A21, A19
SA
16
CE#f
DQ15–DQ0
RY/BY#
CE1#s
CE2s
OE#
WE#
WP#/ACC
RESET#
UB#
LB#
16
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
Connection Diagram of S71JL064HA0, Model Numbers 01/02
73-Ball FBGA
Top View
Flash only
SRAM only
A1
A10
NC
NC
B1
B5
NC
C5
B6
B10
NC
NC
NC
Shared
C1
C3
C4
C6
C7
C8
NC
A7
LB# WP#/ACC WE#
A8
A11
D2
A3
D3
A6
D4
D5
D6
D7
A19
E7
A9
D8
A12
E8
A13
F8
D9
A15
E9
A21
F9
NC
UB# RESET# CE2s
E5
E2
A2
E3
A5
E4
E6
A18 RY/BY# A20
F1
NC
G1
NC
F2
A1
F3
A4
F4
A17
G4
DQ1
F7
F10
A10
G7
DQ6
H7
A14
G8
NC
NC
G2
A0
G3
G9 G10
V
SS
A16
H9
NC
J9
NC
H2
CE#f
J2
H3
OE#
J3
H4
DQ9
J4
H5
DQ3
J5
H6
DQ4
J6
H8
DQ13 DQ15
J7
DQ12
K7
J8
DQ7
K8
V
CC
f
V
s
CC
CE1#s DQ0
DQ10
K4
V
SS
K3
K5
K6
NC
L6
NC
DQ8
DQ2
DQ11
L5
DQ5
DQ14
L1
NC
M1
NC
L10
NC
NC
M10
NC
May 25, 2004 S71JLxxxHxx_00A3
17
P r e l i m i n a r y
Special Package Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic
cleaning methods. The package and/or data integrity may be compromised if the
package body is exposed to temperatures above 150°C for prolonged periods of
time.
Pin Description
A19–A0
A21–A20
DQ15–DQ0
CE#f
CE#s
OE#
WE#
RY/BY#
UB#
LB#
RESET#
WP#/ACC
=
=
=
=
=
=
=
=
=
=
=
=
=
20 Address Inputs (Common)
2 Address Inputs (Flash)
16 Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Output
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
Hardware Reset Pin, Active Low
Hardware Write Protect/Acceleration Pin (Flash)
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
VCCf
VCC
VSS
NC
s
=
=
=
SRAM Power Supply
Device Ground (Common)
Pin Not Connected Internally
18
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
Logic Symbol
20
A19–A0
A21–A20
16
CE#f
DQ15–DQ0
RY/BY#
CE1#s
CE2s
OE#
WE#
WP#/ACC
RESET#
UB#
LB#
May 25, 2004 S71JLxxxHxx_00A3
19
P r e l i m i n a r y
Connection Diagram of S71JL064HA0, Model Numbers 10/11/12/62
73-Ball FBGA
Top View
Flash only
SRAM only
A1
A10
NC
NC
B1
B5
NC
C5
B6
B10
NC
NC
NC
Shared
C1
C3
C4
C6
C7
C8
NC
A7
LB# WP#/ACC WE#
A8
A11
D2
A3
D3
A6
D4
D5
D6
D7
A19
E7
A9
D8
A12
E8
A13
F8
D9
A15
E9
A21
F9
NC
UB# RESET# CE2s
E5
E2
A2
E3
A5
E4
E6
A18 RY/BY# A20
F1
NC
G1
NC
F2
A1
F3
A4
F4
A17
G4
DQ1
F7
F10
A10
G7
DQ6
H7
A14
G8
NC
NC
G2
A0
G3
G9 G10
V
SS
A16
H9
NC
J9
NC
H2
CE#f
J2
H3
OE#
J3
H4
DQ9
J4
H5
DQ3
J5
H6
DQ4
J6
H8
DQ13 DQ15
J7
DQ12
K7
J8
DQ7
K8
V
CC
f
V
s
CC
CE1#s DQ0
DQ10
K4
V
SS
K3
K5
K6
NC
L6
NC
DQ8
DQ2
DQ11
L5
DQ5
DQ14
L1
NC
M1
NC
L10
NC
NC
M10
NC
20
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(TSOP, BGA, PDIP, SSOP, PLCC). The package and/or data integrity may be com-
promised if the package body is exposed to temperatures above 150°C for
prolonged periods of time.
Pin Description
A19–A0
A21–A20
DQ15–DQ0
CE#f
CE1#s
CE2s
OE#
WE#
RY/BY#
UB#
LB#
=
=
=
=
=
=
=
=
=
=
=
=
=
=
20 Address Inputs (Common)
2 Address Inputs (Flash)
16 Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable 1 (pSRAM)
Chip Enable 2 (pSRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Output
Upper Byte Control (pSRAM)
Lower Byte Control (pSRAM)
Hardware Reset Pin, Active Low
Hardware Write Protect/Acceleration Pin (Flash)
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
RESET#
WP#/ACC
VCCf
VCC
VSS
NC
s
=
=
=
pSRAM Power Supply
Device Ground (Common)
Pin Not Connected Internally
Logic Symbol
20
A19–A0
SA
16
CE#f
DQ15–DQ0
RY/BY#
CE1#s
CE2s
OE#
WE#
WP#/ACC
RESET#
UB#
LB#
May 25, 2004 S71JLxxxHxx_00A3
21
P r e l i m i n a r y
Connection Diagram of S71JL064HB0, Model Numbers 00/01/02
73-Ball FBGA
Top View
Flash only
SRAM only
A1
A10
NC
NC
B1
B5
NC
C5
B6
B10
NC
NC
NC
Shared
C1
C3
C4
C6
C7
C8
NC
A7
LB# WP#/ACC WE#
A8
A11
D2
A3
D3
A6
D4
D5
D6
D7
A19
E7
A9
D8
A12
E8
A13
F8
D9
A15
E9
A21
F9
NC
UB# RESET# CE2s
E5
E2
A2
E3
A5
E4
E6
A18 RY/BY# A20
F1
NC
G1
NC
F2
A1
F3
A4
F4
A17
G4
DQ1
F7
F10
A10
G7
DQ6
H7
A14
G8
NC
NC
G2
A0
G3
G9 G10
V
SS
A16
H9
NC
J9
NC
H2
CE#f
J2
H3
OE#
J3
H4
DQ9
J4
H5
DQ3
J5
H6
DQ4
J6
H8
DQ13 DQ15
J7
DQ12
K7
J8
DQ7
K8
V
CC
f
V
s
CC
CE1#s DQ0
DQ10
K4
V
SS
K3
K5
K6
NC
L6
NC
DQ8
DQ2
DQ11
L5
DQ5
DQ14
L1
NC
M1
NC
L10
NC
NC
M10
NC
22
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(TSOP, BGA, PDIP, SSOP, PLCC). The package and/or data integrity may be com-
promised if the package body is exposed to temperatures above 150°C for
prolonged periods of time.
Pin Description
A20–A0
A21
DQ15–DQ0
CE#f
CE1#s
CE2s
OE#
WE#
RY/BY#
UB#
LB#
RESET#
WP#/ACC
=
=
=
=
=
=
=
=
=
=
=
=
=
=
20 Address Inputs (Common)
1 Address Input (Flash)
16 Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable 1 (pSRAM)
Chip Enable 2 (pSRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Output
Upper Byte Control (pSRAM)
Lower Byte Control (pSRAM)
Hardware Reset Pin, Active Low
Hardware Write Protect/Acceleration Pin (Flash)
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
VCCf
VCC
VSS
NC
s
=
=
=
pSRAM Power Supply
Device Ground (Common)
Pin Not Connected Internally
Logic Symbol
21
A20–A0
A21
SA
16
CE#f
DQ15–DQ0
RY/BY#
CE1#s
CE2s
OE#
WE#
WP#/ACC
RESET#
UB#
LB#
May 25, 2004 S71JLxxxHxx_00A3
23
P r e l i m i n a r y
Connection Diagram of S71JL128HB0, Model Numbers 00/01/02
73-Ball FBGA
Top View
Flash 1 only
Flash 2 only
A1
A10
NC
NC
B1
B5
NC
C5
B6
B10
NC
NC
NC
Pseudo SRAM
only
C1
C3
C4
C6
C7
C8
NC
A7
LB# WP#/ACC WE#
A8
A11
Flash 1 and 2
shared
D2
A3
D3
A6
D4
D5
D6
D7
A19
E7
A9
D8
A12
E8
A13
F8
D9
A15
E9
UB# RESET# CE2s
Flash 1, 2, and
Pseudo SRAM
shared
E5
E2
A2
E3
A5
E4
E6
A18 RY/BY# A20
A21
F9
F1
NC
G1
NC
F2
A1
F3
A4
F4
A17
G4
DQ1
F7
F10
A10
G7
DQ6
H7
A14
G8
NC
CE#f2
NC
G2
A0
G3
G9 G10
V
SS
A16
H9
NC
J9
NC
HH22
CE#f1
J2
H3
OE#
J3
H4
DQ9
J4
H5
DQ3
J5
H6
DQ4
J6
H8
DQ13 DQ15
J7
DQ12
K7
J8
DQ7
K8
V
CC
f
V
s
CC
CE1#s DQ0
DQ10
K4
V
SS
K3
K5
K6
NC
L6
NC
DQ8
DQ2
DQ11
L5
DQ5
DQ14
L1
NC
M1
NC
L10
NC
NC
M10
NC
24
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(BGA). The package and/or data integrity may be compromised if the package
body is exposed to temperatures above 150°C for prolonged periods of time.
Pin Description
A20–A0
A21
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
21 Address Inputs (Common)
1 Address Input (Flash)
16 Data Inputs/Outputs (Common)
Chip Enable 1 (Flash 1)
Chip Enable 2 (Flash 2)
Chip Enable 1 (pSRAM)
Chip Enable 2 (pSRAM)
Output Enable (Common)
Write Enable (Common)
DQ15–DQ0
CE#f1
CE#f2
CE1#ps
CE2ps
OE#
WE#
RY/BY#
UB#
Ready/Busy Output
Upper Byte Control (pSRAM)
Lower Byte Control (pSRAM)
Hardware Reset Pin, Active Low
Hardware Write Protect/Acceleration Pin (Flash)
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
LB#
RESET#
WP#/ACC
VCCf
VCCps
VSS
NC
=
=
=
pSRAM Power Supply
Device Ground (Common)
Pin Not Connected Internally
Logic Symbol
21
A20–A0
A21
16
CE#f1
DQ15–DQ0
RY/BY#
CE#f2
CE1#ps
CE2ps
OE#
WE#
WP#/ACC
RESET#
UB#
LB#
May 25, 2004 S71JLxxxHxx_00A3
25
P r e l i m i n a r y
Connection Diagram of S71JL128HC0, Model Numbers 00/01/02
88-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
Shared
A2
NC
A10
NC
A1
NC
A9
NC
Flash 1 and 2
Shared
B4
B5
B6
NC
B7
NC
B8
NC
B9
NC
B2
NC
B3
Flash 1 Only
Flash 2 Only
SRAM Only
VSS
Ry/BY#2 CE#f2
CC44
C2
NC
C3
A7
C5
C6
C7
A8
C8
C9
NC
LB#
WP#/Acc
WE#
A11
D4
D2
A3
D3
A6
D5
D7
D8
D9
D6
UB# RESET#1 CE2s
A19
A12
A15
E2
A2
E3
A5
E4
E5
E6
E7
A9
E8
E9
A18
RY/BY#1
A20
A13
A21
F2
A1
F3
A4
F4
F5
F6
F7
F8
F9
A17
NC
NC
A10
A14
NC
G2
A0
G3
G4
G5
NC
G6
NC
G7
G8
NC
G9
V
DQ1
DQ6
A16
SS
H4
H5
H6
H7
H8
H9
NC
HH22
H3
DQ9
DQ3
DQ4
DQ13
DQ15
CE#f1
OE#
JJ22
J3
J4
JJ45
J4
J7
J8
J9
DQ12
V
CE1#fs
DQ0
DQ10
V
f
V
s
DQ7
SS
CC
CC
K4
K5
K6
NC
K7
K8
K9
NC
K2
NC
K3
DQ2
DQ11
L5
DQ5
DQ14
DQ8
L2
L3
L4
L6
L7
L8
L9
NC
NC
RESET#2
V
V
f
NC
NC
NC
SS
CC
M1
NC
M2
NC
M9
NC
M10
NC
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(TSOP, BGA, PLCC, PDIP, SSOP). The package and/or data integrity may be com-
promised if the package body is exposed to temperatures above 150°C for
prolonged periods of time.
26
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
Pin Description
A21–A0
DQ15–DQ0
CE#f1
CE#f2
CE1#ps
CE2ps
OE#
WE#
RY/BY#1
RY/BY#2
UB#
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
22 Address Inputs (Common)
16 Data Inputs/Outputs (Common)
Chip Enable 1 (Flash 1)
Chip Enable 2 (Flash 2)
Chip Enable 1 (pSRAM)
Chip Enable 2 (pSRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Output (Flash 1)
Ready/Busy Output (Flash 2)
Upper Byte Control (pSRAM)
Lower Byte Control (pSRAM)
Hardware Reset Pin, Active Low (Flash 1)
Hardware Reset Pin, Active Low (Flash 2)
Hardware Write Protect/Acceleration Pin (Flash)
LB#
RESET#1
RESET#2
WP#/ACC
VCCf
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
VCCps
VSS
NC
=
=
=
pSRAM Power Supply
Device Ground (Common)
Pin Not Connected Internally
Logic Symbol
22
A21–A0
16
CE#f1
DQ15–DQ0
CE#f2
CE1#ps
RY/BY#1
RY/BY#2
CE2ps
OE#
WE#
WP#/ACC
RESET#1
RESET#2
UB#
LB#
May 25, 2004 S71JLxxxHxx_00A3
27
P r e l i m i n a r y
Look-ahead Connection Diagram
96-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
Legend:
A9
NC
A2
NC
A10
NC
A1
NC
ds = Data storage only
f = Flash shared only
f1 = 1st Flash only
f2 = 2nd Flash only
NC = Outrigger balls
s = RAM shared
B9
NC
B1
NC
B2
NC
B10
NC
s1 = 1st RAM only
s2 = 2nd RAM only
C4
C5
C6
C7
C8
C9
C2
C3
AVD#
VSSds
CLK
CE#f2
VCCds RESET#ds CLKds RY/BY#ds
D4
D2
D3
A7
D5
D6
D7
A8
D8
D9
WP#
LB#s WP#/ACC WE#
E4 E5 E6
UB#s RESET#f CE2s1
A11
CE1#ds
E2
A3
E3
A6
E7
E8
E9
A19
A12
A15
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
A18
RY/BY#
A20
A13
A21
G2
A1
G3
A4
G4
G5
G6
G7
G8
G9
A17
CE1#s2
A23
A10
A14
A22
H2
A0
H3
H4
H5
H6
H7
H8
H9
VSS
DQ1
VCCs2
CE2s2
DQ6
A24
A16
J2
J3
J4
J5
J6
J7
J8
J2
DQ9
DQ3
DQ4
DQ13
DQ15
CREs
CE#f1
OE#
K2
K3
K4
KK55
K6
K7
K8
K9
DQ12
VSS
CE1#s1
DQ0
DQ10
VCCf
VCCs1
DQ7
L4
L5
L6
L7
L8
L9
L2
L3
DQ2
DQ11
A25
DQ5
DQ14 LOCK
or WP#/ACCds
VCCds
DQ8
M2
M3
M4
M5
M6
M7
M8 M9
TEST
A27
A26
VSSnds
VCCf
or VCCQf
CE2#ds VCCQs1 VCCQds
N9
NC
N1
NC
N2
NC
N10
NC
P1
P9
P2
P10
NC
NC
NC
NC
Note: To provide customers with a migration path to higher densities and an option to stack more die in a package,
FASL has prepared a standard pinout that supports
NOR Flash and SRAM densities up to 4 Gigabits
NOR Flash and pSRAM densities up to 4 Gigabits
28
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
NOR Flash and pSRAM and DATA STORAGE densities up to 4 Gigabits
The signal locations of the resultant MCP device are shown above. Note that for different densities, the actual package
outline may vary. Any pinout in any MCP, however, will be a subset of the pinout above.
In some cases, there may be outrigger balls in locations outside the grid shown above. In such cases, the user is rec-
ommended to treat them as reserved and not connect them to any other signal.
For any further inquiries about the above look-ahead pinout, please refer to the application note on this subject or con-
tact your sales office.
May 25, 2004 S71JLxxxHxx_00A3
29
P r e l i m i n a r y
Ordering Information
The order number (Valid Combination) is formed by the following:
S
71
J
L
064 A W 00
H
A
0
B
0
PACKING TYPE
0
2
3
= Tray
= 7” Tape & Reel
= 13” Tape & Reel
Additional ordering options
See Product Selector Guide
TEMPERATURE (and RELIABILITY) GRADE
E
W
I
= Engineering Samples
= Wireless (-25 C to +85
= Industrial (-40 C to +85
°
°
C)
C)
°
°
PACKAGE MATERIAL SET (BGA Package Type)
A
= Standard (Pb-free compliant) Package
F
= Lead (Pb)-free Package
PACKAGE TYPE
B
= BGA Package
CHIP CONTENTS—2
0
= No second content
CHIP CONTENTS—1
8
A
B
C
= 8 Mb
= 16 Mb
= 32 Mb
= 64 Mb
Spansion FLASH MEMORY PROCESS TECHNOLOGY
(Highest-density Flash described in Characters 4-8)
H
= 130 nm Floating Gate Technology
BASE NOR FLASH DENSITY
064
=
one S29JL064H
128
=
two S29JL064H
BASE NOR FLASH CORE VOLTAGE
L
= 3-volt V
CC
BASE NOR FLASH INTERFACE and SIMULTANEOUS READ/
WRITE
J
= Simultaneous Read/Write
PRODUCT FAMILY
71
= Flash Base + xRAM.
PREFIX
S
= Spansion
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device.
Consult the local sales office to confirm availability of specific valid combinations and to
check on newly released combinations.
Valid Combinations
Flash Access
Time (ns)
(p)SRAM Access
Time (ns)
Temperature
Range
Order Number
Package Marking
71JL064H80BAI01
71JL064H80BAI02
71JL064H80BAI10
71JL064H80BAI11
Supplier
S71JL064H80BAI01
S71JL064H80BAI02
S71JL064H80BAI10
S71JL064H80BAI11
70
85
55
70
70
85
55
70
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
Supplier 1
Supplier 1
Supplier 2
Supplier 2
30
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
Valid Combinations
Order Number
Flash Access
Time (ns)
(p)SRAM Access
Time (ns)
Temperature
Range
Package Marking
71JL064H80BAI12
71JL064H80BAW01
71JL064H80BAW02
71JL064H80BAW10
71JL064H80BAW11
71JL064H80BAW12
71JL064H80BFI01
71JL064H80BFI02
71JL064H80BFI10
71JL064H80BFI11
71JL064H80BFI12
71JL064H80BFW01
71JL064H80BFW02
71JL064H80BFW10
71JL064H80BFW11
71JL064H80BFW12
Supplier
S71JL064H80BAI12
S71JL064H80BAW01
S71JL064H80BAW02
S71JL064H80BAW10
S71JL064H80BAW11
S71JL064H80BAW12
S71JL064H80BFI01
S71JL064H80BFI02
S71JL064H80BFI10
S71JL064H80BFI11
S71JL064H80BFI12
S71JL064H80BFW01
S71JL064H80BFW02
S71JL064H80BFW10
S71JL064H80BFW11
S71JL064H80BFW12
85
85
70
85
55
70
85
70
85
55
70
85
70
85
55
70
85
-40C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
Supplier 2
Supplier 1
Supplier 1
Supplier 2
Supplier 2
Supplier 2
Supplier 1
Supplier 1
Supplier 2
Supplier 2
Supplier 2
Supplier 1
Supplier 1
Supplier 2
Supplier 2
Supplier 2
70
85
55
70
85
70
85
55
70
85
70
85
55
70
85
S71JL064HA0BAI01
S71JL064HA0BAI02
S71JL064HA0BAI10
S71JL064HA0BAI11
S71JL064HA0BAI12
S71JL064HA0BAI62
S71JL064HA0BAW01
S71JL064HA0BAW02
S71JL064HA0BAW10
S71JL064HA0BAW11
S71JL064HA0BAW12
S71JL064HA0BAW62
S71JL064HA0BFI01
S71JL064HA0BFI02
S71JL064HA0BFI10
S71JL064HA0BFI11
S71JL064HA0BFI12
S71JL064HA0BFI62
71JL064HA0BAI01
71JL064HA0BAI02
71JL064HA0BAI10
71JL064HA0BAI11
71JL064HA0BAI12
71JL064HA0BAI62
71JL064HA0BAW01
71JL064HA0BAW02
71JL064HA0BAW10
71JL064HA0BAW11
71JL064HA0BAW12
71JL064HA0BAW62
71JL064HA0BFI01
71JL064HA0BFI02
71JL064HA0BFI10
71JL064HA0BFI11
71JL064HA0BFI12
71JL064HA0BFI62
70
85
55
70
85
70
70
85
55
70
85
70
70
85
55
70
85
70
70
85
55
70
85
70
70
85
55
70
85
70
70
85
55
70
85
70
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
Supplier 1
Supplier 1
Supplier 2
Supplier 2
Supplier 2
Supplier 4
Supplier 1
Supplier 1
Supplier 2
Supplier 2
Supplier 2
Supplier 4
Supplier 1
Supplier 1
Supplier 2
Supplier 2
Supplier 2
Supplier 4
May 25, 2004 S71JLxxxHxx_00A3
31
P r e l i m i n a r y
Valid Combinations
Order Number
Flash Access
Time (ns)
(p)SRAM Access
Temperature
Range
Package Marking
71JL064HA0BFW01
71JL064HA0BFW02
71JL064HA0BFW10
71JL064HA0BFW11
71JL064HA0BFW12
71JL064HA0BFW62
Time (ns)
Supplier
S71JL064HA0BFW01
S71JL064HA0BFW02
S71JL064HA0BFW10
S71JL064HA0BFW11
S71JL064HA0BFW12
S71JL064HA0BFW62
70
85
55
70
85
70
70
-25C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
Supplier 1
Supplier 1
Supplier 2
Supplier 2
Supplier 2
Supplier 4
85
55
70
85
70
S71JL064HB0BAI00
S71JL064HB0BAI01
S71JL064HB0BAI02
S71JL064HB0BAW00
S71JL064HB0BAW01
S71JL064HB0BAW02
S71JL064HB0BFI00
S71JL064HB0BFI01
S71JL064HB0BFI02
S71JL064HB0BFW00
S71JL064HB0BFW01
S71JL064HB0BFW02
71JL064HB0BAI00
71JL064HB0BAI01
71JL064HB0BAI02
71JL064HB0BAW00
71JL064HB0BAW01
71JL064HB0BAW02
71JL064HB0BFI00
71JL064HB0BFI01
71JL064HB0BFI02
71JL064HB0BFW00
71JL064HB0BFW01
71JL064HB0BFW02
55
70
85
55
70
85
55
70
85
55
70
85
55
70
85
55
70
85
55
70
85
55
70
85
-40C to +85C
-40C to +85C
-40C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
S71JL128HB0BAI00
S71JL128HB0BAI01
S71JL128HB0BAI02
S71JL128HB0BAW00
S71JL128HB0BAW01
S71JL128HB0BAW02
S71JL128HB0BFI00
S71JL128HB0BFI01
S71JL128HB0BFI02
S71JL128HB0BFW00
S71JL128HB0BFW01
S71JL128HB0BFW02
71JL128HB0BAI00
71JL128HB0BAI01
71JL128HB0BAI02
71JL128HB0BAW00
71JL128HB0BAW01
71JL128HB0BAW02
71JL128HB0BFI00
71JL128HB0BFI01
71JL128HB0BFI02
71JL128HB0BFW00
71JL128HB0BFW01
71JL128HB0BFW02
55
70
85
55
70
85
55
70
85
55
70
85
55
70
85
55
70
85
55
70
85
55
70
85
-40C to +85C
-40C to +85C
-40C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
S71JL128HC0BAI00
S71JL128HC0BAI01
71JL128HC0BAI00
71JL128HC0BAI01
55
70
55
70
-40C to +85C
-40C to +85C
Supplier 3
Supplier 3
32
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
Valid Combinations
Order Number
Flash Access
Time (ns)
(p)SRAM Access
Time (ns)
Temperature
Range
Package Marking
71JL128HC0BAI02
71JL128HC0BAW00
71JL128HC0BAW01
71JL128HC0BAW02
71JL128HC0BFI00
71JL128HC0BFI01
71JL128HC0BFI02
71JL128HC0BFW00
71JL128HC0BFW01
71JL128HC0BFW02
Supplier
S71JL128HC0BAI02
S71JL128HC0BAW00
S71JL128HC0BAW01
S71JL128HC0BAW02
S71JL128HC0BFI00
S71JL128HC0BFI01
S71JL128HC0BFI02
S71JL128HC0BFW00
S71JL128HC0BFW01
S71JL128HC0BFW02
85
85
55
70
85
55
70
85
55
70
85
-40C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-25C to +85C
-25C to +85C
-25C to +85C
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
Supplier 3
55
70
85
55
70
85
55
70
85
May 25, 2004 S71JLxxxHxx_00A3
33
P r e l i m i n a r y
Physical Dimensions
FLB073
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
E1
5
4
eE
3
2
1
L
J
H G F E D C B A
M
K
INDEX MARK
10
PIN A1
PIN A1
CORNER
B
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20
C
A2
A
0.08
C
C
A1
6
73X
b
0.15 M C
0.08 M C
A B
NOTES:
PACKAGE
JEDEC
FLB 073
N/A
11.60 mm x 8.00 mm
PACKAGE
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
NOTE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
SYMBOL
A
MIN.
---
NOM.
MAX.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
---
1.40
---
PROFILE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A1
0.20
0.95
---
---
BALL HEIGHT
BODY THICKNESS
BODY SIZE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
A2
1.13
D
11.60 BSC.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
E
8.00 BSC.
8.80 BSC.
BODY SIZE
D1
MATRIX FOOTPRINT
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E1
7.20 BSC.
12
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MATRIX SIZE D DIRECTION
MD
ME
n
10
MATRIX SIZE E DIRECTION
BALL COUNT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
73
Ob
0.25
0.30
0.35
BALL DIAMETER
BALL PITCH
eE
0.80 BSC
0.80 BSC
0.40 BSC
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
eD
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
SD/SE
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B2,B3,B4,B7,B8,B9
C2,C9,C10,D1,D10,E1,E10
F5,F6,G5,G6,H1,H10
DEPOPULATED SOLDER BALL
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9. N/A
J1,J10,K1,K2, K9,K10,L2,L3,L4,L7,L8,L9
M2,M3,M4,M5,M6,M7,M8,M9
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTION OR OTHER MEANS.
3188\38.14b
34
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
FLJ073
A
D1
D
eD
0.15
(2X)
C
10
9
8
7
6
5
4
3
2
1
SE
7
E
B
E1
eE
L
J
H
G
F
E
D
C
B
A
M
K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
6
73X
b
0.15
0.08
M
C
C
A B
M
NOTES:
PACKAGE
JEDEC
FLJ 073
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER ASME
Y14.5M-1994.
11.60 mm x 8.00 mm
PACKAGE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.25
0.95
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E"
DIRECTION.
A2
---
1.13
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULATED SOLDER BALL
POSITIONS FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
73
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = 0.000.
φb
0.30
0.35
0.40
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC.
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9,B2,B3,B4,B7,B8,B9
9. NOT USED.
C2,C9,C10,D1,D10,E1,E10,F5,F6,G5,G6,H1,H10 DEPOPULATED SOLDER BALLS
J1,J10,K1,K2,K9,K10,L2,L3,L4,L7,L8,L9
10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
M2,M3,M4,M5,M6,M7,M8,M9
3232 \ 16-038.14b
May 25, 2004 S71JLxxxHxx_00A3
35
P r e l i m i n a r y
FTA073
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
E1
5
4
3
2
1
eE
L
J
H
G
F
E
D
C
B
A
M
K
INDEX MARK
10
PIN A1
PIN A1
CORNER
B
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
6
73X
b
0.15
0.08
M
C
C
A B
M
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
PACKAGE
JEDEC
FTA 073
N/A
11.60 mm x 8.00 mm
PACKAGE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL
A
MIN.
NOM.
MAX.
e
---
---
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
A1
0.25
1.00
---
---
BALL HEIGHT
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
1.11
D
11.60 BSC.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
8.00 BSC.
8.80 BSC.
BODY SIZE
D1
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
7.20 BSC.
12
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MD
ME
n
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
10
MATRIX SIZE E DIRECTION
BALL COUNT
73
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ob
0.30
0.35
0.40
BALL DIAMETER
BALL PITCH
eE
0.80 BSC
0.80 BSC
0.40 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eD
BALL PITCH
SD/SE
SOLDER BALL PLACEMENT
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
A2,A3,A4,A5,A6,A7,A8,A9
B2,B3,B4,B7,B8,B9,C2,C9,C10
D1,D10,E1,E10,F5,F6,G5,G6
H1,H10,J1,J10,K1,K2,K9,K10
L2,L3,L4,L7,L8,L9
DEPOPULATED SOLDER BALL
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTION OR OTHER MEANS.
M2,M3,M4,M5,M6,M7,M8,M9
3159\38.14b
36
S71JLxxxHxx_00A3 May 25, 2004
P r e l i m i n a r y
FTA088
A
D1
D
eD
0.15
(2X)
C
10
9
8
7
6
5
4
3
2
1
SE
7
E
B
E1
eE
L
J
H
G
F
E
D
C
B
A
M
K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
6
88X
b
M
0.15
C
C
A B
0.08
M
NOTES:
PACKAGE
JEDEC
FTA 088
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
11.60 mm x 8.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.25
1.00
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
1.11
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
88
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.30
0.35
0.40
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
A3,A4,A5,A6,A7,A8,B1,B10,C1,C10,D1,D10 DEPOPULATED SOLDER BALLS
E1,E10,F1,F10,G1,G10,H1,H10
J1,J10,K1,K10,L1,L10,M3,M4,M5,M6,M7,M8
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3237 \ 16-038.14b
May 25, 2004 S71JLxxxHxx_00A3
37
P r e l i m i n a r y
38
S71JLxxxHxx_00A3 May 25, 2004
S29JL064H
For Multi-Chip Products (MCP)
64 Megabit (8 M x 8-Bit/4 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write
Flash Memory
PRELIMINARY
Distinctive Characteristics
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
Architectural Advantages
Simultaneous Read/Write operations
Cycling Endurance: 1 million cycles per sector
typical
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
Data Retention: 20 years typical
Flexible Bank architecture
Software Features
— Read may occur in any of the three banks not being
written or erased.
— Four banks may be grouped by customer to achieve
desired bank divisions.
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
— Suspends erase operations to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation.
Boot Sectors
— Top and bottom boot sectors in the same device
— Any combination of sectors can be erased
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
Manufactured on 130 nm process technology
SecSi™ (Secured Silicon) Sector: Extra 256 Byte
sector
Unlock Bypass Program command
—
Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function.
— Reduces overall programming time when issuing
multiple program command sequences
Hardware Features
—
Customer lockable: One-time programmable only.
Once locked, data cannot be changed
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero.
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
Compatible with JEDEC standards
— Pinout and software compatible with single-power-
supply flash standard
WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1,
140, and 141, regardless of sector protect status
— Acceleration (ACC) function accelerates program
timing
Performance Characteristics
High performance
— Access time as fast as 55 ns
— Program time: 4 µs/word typical using accelerated
programming function
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
Sector protection
— Hardware method to prevent any program or erase
operation within a sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
Publication Number S29JL064H Revision A Amendment 1 Issue Date May 7, 2004
This document contains information on a product under development at FASL LLC. The information is intended to help you evaluate this product. FASL LLC reserves the
right to change or discontinue work on this proposed product without notice.
P r e l i m i n a r y
General Description
The S29JL064H is a 64 megabit, 3.0 volt-only flash memory device, organized as
4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode
Data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device
is designed to be programmed in-system with the standard 3.0 volt VCC supply,
and can also be programmed in standard EPROM programmers.
Standard control pins—chip enable (CE#), write enable (WE#), and output en-
able (OE#)—control normal read and write operations, and avoid bus contention
issues.
The device requires only a single 3.0 volt power supply for both read and write
functions. Internally generated and regulated voltages are provided for the pro-
gram and erase operations.
Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation
by dividing the memory space into four banks, two 8 Mb banks with small and
large sectors, and two 24 Mb banks of large sectors. Sector addresses are fixed,
system software can be used to form user-defined bank groups.
During an Erase/Program operation, any of the three non-busy banks may be
read from. Note that only two banks can operate simultaneously. The device can
improve overall system performance by allowing a host system to program or
erase in one bank, then immediately and simultaneously read from the other
bank, with zero latency. This releases the system from waiting for the completion
of program or erase operations.
The S29JL064H can be organized as both a top and bottom boot sector
configuration.
Bank
Megabits
Sector Sizes
Eight 8 Kbyte/4 Kword,
Fifteen 64 Kbyte/32 Kword
Bank 1
8 Mb
Bank 2
Bank 3
24 Mb
24 Mb
Forty-eight 64 Kbyte/32 Kword
Forty-eight 64 Kbyte/32 Kword
Eight 8 Kbyte/4 Kword,
Fifteen 64 Kbyte/32 Kword
Bank 4
8 Mb
S29JL064H Features
The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector capable of
being permanently locked by FASL or customers. [The SecSi Customer Indicator
Bit (DQ6) is permanently set to 1 if the part has been customer locked and per-
manently set to 0 if the part has been factory locked.] This way, customer
lockable parts can never be used to replace a factory locked part.
Factory locked parts provide several options. The SecSi Sector may store a se-
cure, random 16 byte ESN (Electronic Serial Number), customer code
(programmed through Spansion programming services), or both. Customer Lock-
able parts may utilize the SecSi Sector as bonus space, reading and writing like
any other flash sector, or may permanently lock their own code there.
DMS (Data Management Software) allows systems to easily take advantage
of the advanced architecture of the simultaneous read/write product line by al-
2
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
lowing removal of EEPROM devices. DMS will also allow the system software to
be simplified, as it will perform all functions necessary to modify data in file struc-
tures, as opposed to single-byte modifications. To write or update a particular
piece of data (a phone number or configuration data, for example), the user only
needs to state which piece of data is to be updated, and where the updated data
is located in the system. This is an advantage compared to systems where user-
written software must keep track of the old data location, status, logical to phys-
ical translation of the data onto the Flash memory device (or memory devices),
and more. Using DMS, user-written software does not need to interface with the
Flash memory directly. Instead, the user's software accesses the Flash memory
by calling one of only six functions.
The device offers complete compatibility with the JEDEC 42.4 sin-
gle-power-supply Flash command set standard. Commands are written to
the command register using standard microprocessor write timings. Reading data
out of the device is similar to reading from other Flash or EPROM devices.
The host system can detect whether a program or erase operation is complete by
using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2
(toggle bits). After a program or erase cycle has been completed, the device au-
tomatically returns to the read mode.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automat-
ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-system or via
programming equipment.
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the automatic sleep mode.
The system can also place the device into the standby mode. Power consump-
tion is greatly reduced in both modes.
May 7, 2004 S29JL064HA1
S29JL064H
3
P r e l i m i n a r y
Product Selector Guide
Part Number
S29JL064H
Speed Option
Standard Voltage Range: V
CC
= 2.7–3.6 V
55
55
55
25
70
70
70
30
85
85
85
40
Max Access Time (ns), tACC
CE# Access (ns), tCE
OE# Access (ns), tOE
Block Diagram
OE# BYTE#
ux
Bank 1
Bank 1 Address
X-Decoder
Bank 2 Address
/BY#
Bank 2
X-Decoder
L
Status
D
R
Control
X-Decoder
Bank 3
Bank 3 Address
X-Decoder
Bank 4
Bank 4 Address
ux
4
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
Pin Description
A21–A0
DQ14–DQ0
DQ15/A-1
=
=
=
22 Addresses
15 Data Inputs/Outputs (x16-only devices)
DQ15 (Data Input/Output, word mode), A-1 (LSB
Address Input, byte mode)
CE#
OE#
WE#
WP#/ACC
=
=
=
=
Chip Enable
Output Enable
Write Enable
Hardware Write Protect/
Acceleration Pin
RESET#
BYTE#
RY/BY#
VCC
=
=
=
=
Hardware Reset Pin, Active Low
Selects 8-bit or 16-bit mode
Ready/Busy Output
3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
VSS
NC
=
=
Device Ground
Pin Not Connected Internally
Logic Symbol
22
A21–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
May 7, 2004 S29JL064HA1
S29JL064H
5
P r e l i m i n a r y
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 1. S29JL064H Device Bus Operations
DQ15–DQ8
Addresses
(Note 2)
BYTE#
= V
BYTE#
= V
DQ7–
DQ0
Operation
CE# OE# WE# RESET# WP#/ACC
IH
IL
Read
Write
L
L
L
H
L
H
H
L/H
AIN
AIN
DOUT
DIN
DOUT
DIN
DQ14–DQ8 = High-
Z, DQ15 = A-1
H
(Note 3)
VCC
0.3 V
VCC
0.3 V
Standby
X
X
L/H
X
High-Z
High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
L/H
L/H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
SA, A6 = L,
A1 = H, A0 = L
Sector Protect (Note 2)
L
L
H
H
X
L
L
VID
VID
VID
L/H
X
X
X
X
DIN
DIN
DIN
SA, A6 = H,
A1 = H, A0 = L
Sector Unprotect (Note 2)
(Note 3)
(Note 3)
Temporary Sector
Unprotect
X
X
AIN
DIN
High-Z
Legend: L = Logic Low = V , H = Logic High = V , V = 11.5–12.5 V, V = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector
HH
IL
IH
ID
Address, A = Address In, D = Data In, D = Data Out
IN
IN
OUT
Notes:
1. Addresses are A21:A0 in word mode (BYTE# = V ), A21:A-1 in byte mode (BYTE# = V ).
IH
IL
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See
the “Sector/Sector Block Protection and Unprotection” section.
3. If WP#/ACC = V , sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = V , protection on sectors 0, 1, 140,
IL
IH
and 141 depends on whether they were last protected or unprotected using the method described in “Sector/Sector
Block Protection and Unprotection”. If WP#/ACC = V , all sectors will be unprotected.
HH
6
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only
data I/O pins DQ7–DQ0 are active and controlled by CE# and OE#. The data I/
O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE#
pins to VIL. CE# is the power control and selects the device. OE# is the output
control and gates array data to the output pins. WE# should remain at VIH. The
BYTE# pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.
Refer to the AC Read-Only Operations table for timing specifications and to 14 for
the timing diagram. ICC1 in the DC Characteristics table represents the active cur-
rent specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH
.
For program operations, the BYTE# pin determines whether the device accepts
program data in bytes or words. Refer to “Word/Byte Configuration” for more
information.
The device features an Unlock Bypass mode to facilitate faster programming.
Once a bank enters the Unlock Bypass mode, only two write cycles are required
to program a word or byte, instead of four. The “Byte/Word Program Command
Sequence” section has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 3 indicates the address space that each sector occupies. Similarly, a “sector
address” is the address bits required to uniquely select a sector. The “Command
Definitions” section has details on erasing a sector or the entire chip, or suspend-
ing/resuming the erase operation.
The device address space is divided into four banks. A “bank address” is the ad-
dress bits required to uniquely select a bank.
ICC2 in the DC Characteristics table represents the active current specification for
the write mode. The AC Characteristics section contains timing specification ta-
bles and timing diagrams for write operations.
May 7, 2004 S29JL064HA1
S29JL064H
7
P r e l i m i n a r y
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
is one of two functions provided by the WP#/ACC pin. This function is primarily
intended to allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the afore-
mentioned Unlock Bypass mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin re-
turns the device to normal operation. Note that VHH must not be asserted on
WP#/ACC for operations other than accelerated programming, or device damage
may result. In addition, the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavior of the device may result. See “Write Protect
(WP#)” on page 17. for related information.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ15–DQ0. Standard
read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more information.
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while program-
ming or erasing in the other bank of memory. An erase operation may also be
suspended to read from or program to another location within the same bank (ex-
cept the sector being erased). Figure 21 shows how read and write cycles may be
initiated for simultaneous operation with zero latency. ICC6 and ICC7 in the DC
Characteristics table represent the current specifications for read-while-program
and read-while-erase, respectively.
8
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device
will be in the standby mode, but the standby current will be greater. The device
requires standard access time (tCE) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
ICC3 in the DC Characteristics table represents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for tACC
+
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. ICC5 in the DC Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is “1”), the reset
operation is completed within a time of tREADY (not during Embedded Algorithms).
The system can read data tRH after the RESET# pin returns to VIH
.
Refer to the AC Characteristics tables for RESET# parameters and to 15 for the
timing diagram.
May 7, 2004 S29JL064HA1
S29JL064H
9
P r e l i m i n a r y
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins
are placed in the high impedance state.
10
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
Table 2. S29JL064H Sector Architecture
Sector Size
(Kbytes/
Kwords)
Sector Address
(x8)
Address Range
(x16)
Address Range
Bank
Sector
A21–A12
SA0
SA1
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001110xxx
0001111xxx
8/4
8/4
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
Bank 1
May 7, 2004 S29JL064HA1
S29JL064H
11
P r e l i m i n a r y
Table 2. S29JL064H Sector Architecture (Continued)
Sector Size
(Kbytes/
Kwords)
Sector Address
A21–A12
(x8)
Address Range
(x16)
Address Range
Bank
Sector
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
0011101xxx
0011110xxx
0011111xxx
0100000xxx
0100001xxx
0100010xxx
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
0101111xxx
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0110100xxx
0110101xxx
0110110xxx
0110111xxx
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
0111110xxx
0111111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
100000h–10FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
Bank 2
12
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
Table 2. S29JL064H Sector Architecture (Continued)
Sector Size
(Kbytes/
Kwords)
Sector Address
A21–A12
(x8)
Address Range
(x16)
Address Range
Bank
Sector
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
1000000xxx
1000001xxx
1000010xxx
1000011xxx
1000100xxx
1000101xxx
1000110xxx
1000111xxx
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
1010000xxx
1010001xxx
1010010xxx
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
1011101xxx
1011110xxx
1011111xxx
1100000xxx
1100001xxx
1100010xxx
1100011xxx
1100100xxx
1100101xxx
1100110xxx
1100111xxx
1101000xxx
1101001xxx
1101010xxx
1101011xxx
1101100xxx
1101101xxx
1101110xxx
1101111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
400000h–40FFFFh
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
470000h–47FFFFh
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
4B0000h–4BFFFFh
4C0000h–4CFFFFh
4D0000h–4DFFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
580000h–58FFFFh
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
650000h–65FFFFh
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
6B0000h–6BFFFFh
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
Bank 3
May 7, 2004 S29JL064HA1
S29JL064H
13
P r e l i m i n a r y
Table 2. S29JL064H Sector Architecture (Continued)
Sector Size
(Kbytes/
Kwords)
Sector Address
A21–A12
(x8)
Address Range
(x16)
Address Range
Bank
Sector
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
1110000xxx
1110001xxx
1110010xxx
1110011xxx
1110100xxx
1110101xxx
1110110xxx
1110111xxx
1111000xxx
1111001xxx
1111010xxx
1111011xxx
1111100xxx
1111101xxx
1111110xxx
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7F1FFFh
7F2000h–7F3FFFh
7F4000h–7F5FFFh
7F6000h–7F7FFFh
7F8000h–7F9FFFh
7FA000h–7FBFFFh
7FC000h–7FDFFFh
7FE000h–7FFFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3F8FFFh
3F9000h–3F9FFFh
3FA000h–3FAFFFh
3FB000h–3FBFFFh
3FC000h–3FCFFFh
3FD000h–3FDFFFh
3FE000h–3FEFFFh
3FF000h–3FFFFFh
Bank 4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Note: The address range is A21:A-1 in byte mode (BYTE#=VIL) or A21:A0 in word mode (BYTE#=VIH).
Table 3. Bank Address
Bank
A21–A19
000
1
2
3
4
001, 010, 011
100, 101, 110
111
Table 4. SecSiTM Sector Addresses
(x8)
(x16)
Device
Sector Size
Address Range
Address Range
S29JL064H
256 bytes
000000h–0000FFh
000000h–00007Fh
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
protection verification, through identifier codes output on DQ7–DQ0. This mode
is primarily intended for programming equipment to automatically match a device
to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
14
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
Sector/Sector Block Protection and Unprotection
(Note: For the following discussion, the term “sector” applies to both sectors and
sector blocks. A sector block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table 5).
The hardware sector protection feature disables both program and erase opera-
tions in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected sectors. Sector protection/
unprotection can be implemented via two methods.
Table 5. S29JL064H Boot Sector/Sector Block Addresses for Protection/Unprotection
Sector/
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A21–A12
Sector Block Size
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
0000001XXX,
0000010XXX,
0000011XXX,
SA8–SA10
192 (3x64) Kbytes
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
SA83–SA86
SA87–SA90
SA91–SA94
SA95–SA98
SA99–SA102
SA103–SA106
SA107–SA110
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
May 7, 2004 S29JL064HA1
S29JL064H
15
P r e l i m i n a r y
Sector/
Sector
A21–A12
Sector Block Size
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
SA111–SA114
SA115–SA118
SA119–SA122
SA123–SA126
SA127–SA130
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
1111100XXX,
1111101XXX,
1111110XXX
SA131–SA133
192 (3x64) Kbytes
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
16
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
Sector protect/Sector Unprotect requires VID on the RESET# pin only, and can be
implemented either in-system or via programming equipment. Figure 2 shows
the algorithms and Figure 26 shows the timing diagram. For sector unprotect, all
unprotected sectors must first be protected prior to the first sector unprotect
write cycle. Note that the sector unprotect algorithm unprotects all sectors in par-
allel. All previously protected sectors must be individually re-protected. To
change data in protected sectors efficiently, the temporary sector unprotect func-
tion is available. See “Temporary Sector Unprotect” .
The device is shipped with all sectors unprotected. Optional Spansion program-
ming service enable programming and protecting sectors at the factory prior to
shipping the device. Contact your local sales office for details.
It is possible to determine whether a sector is protected or unprotected. See the
Autoselect Mode section for details.
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting without
using VID. This function is one of two provided by the WP#/ACC pin.
If the system asserts VIL on the WP#/ACC pin, the device disables program and
erase functions in sectors 0, 1, 140, and 141, independently of whether those
sectors were protected or unprotected using the method described in “Sector/
Sector Block Protection and Unprotection”.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether sec-
tors 0, 1, 140, and 141 were last set to be protected or unprotected. That is,
sector protection or unprotection for these sectors depends on whether they were
last protected or unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”.
Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent
behavior of the device may result.
Table 6. WP#/ACC Modes
Device
WP# Input Voltage
Mode
VIL
Disables programming and erasing in SA0, SA1, SA140, and SA141
Enables programming and erasing in SA0, SA1, SA140, and SA141, dependent on
whether they were last protected or unprotected.
VIH
Enables accelerated progamming (ACC). See “Accelerated Program Operation” on
page 8..
VHH
Temporary Sector Unprotect
(Note: For the following discussion, the term “sector” applies to both sectors and
sector blocks. A sector block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table 5).
This feature allows temporary unprotection of previously protected sectors to
change data in-system. The Temporary Sector Unprotect mode is activated by
setting the RESET# pin to VID. During this mode, formerly protected sectors can
be programmed or erased by selecting the sector addresses. Once VID is removed
from the RESET# pin, all the previously protected sectors are protected again.
shows the algorithm, and 25 shows the timing diagrams, for this feature. If the
WP#/ACC pin is at VIL, sectors 0, 1, 140, and 141 will remain protected during
the Temporary sector Unprotect mode.
May 7, 2004 S29JL064HA1
S29JL064H
17
P r e l i m i n a r y
.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected (If WP#/ACC =
V , sectors 0, 1, 140, and 141 will remain
IL
protected).
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
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START
START
Protect all sectors:
PLSCNT = 1
PLSCNT = 1
RESET# = VID
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
RESET# = VID
Wait 1 ms
Wait 1 ms
unprotect address
No
No
First Write
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
No
from RESET#
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Figure 2. In-System Sector Protect/Unprotect Algorithms
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SecSi™ (Secured Silicon) Sector
Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that
enables permanent part identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator
Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from
the factory. This bit is permanently set at the factory and cannot be changed,
which prevents cloning of a factory locked part. This ensures the security of the
ESN once the product is shipped to the field.
The product is available with the SecSi Sector either factory locked or customer
lockable. The factory-locked version is always protected when shipped from the
factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set
to a “1.” The customer-lockable version is shipped with the SecSi Sector unpro-
tected, allowing customers to utilize the that sector in any manner they choose.
The customer-lockable version has the SecSi (Secured Silicon) Sector Indicator
Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents cus-
tomer-lockable devices from being used to replace devices that are factory
locked. The SecSi Customer Indicator Bit (DQ6) is permanently set to 1 if the part
has been customer locked, permanently set to 0 if the part has been factory
locked, and is 0 if customer lockable.
The system accesses the SecSi Sector Secure through a command sequence (see
“Enter SecSi™ Sector/Exit SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command sequence, it may read the SecSi
Sector by using the addresses normally occupied by the boot sectors. This mode
of operation continues until the system issues the Exit SecSi Sector command se-
quence, or until power is removed from the device. On power-up, or following a
hardware reset, the device reverts to sending commands to the first 256 bytes of
Sector 0. Note that the ACC function and unlock bypass modes are not available
when the SecSi Sector is enabled.
Factory Locked: SecSi Sector Programmed and Protected At the Factory
In a factory locked device, the SecSi Sector is protected when the device is
shipped from the factory. The SecSi Sector cannot be modified in any way. The
device is preprogrammed with both a random number and a secure ESN. The 8-
word random number is at addresses 000000h–000007h in word mode (or
000000h–00000Fh in byte mode). The secure ESN is programmed in the next 8
words at addresses 000008h–00000Fh (or 000010h–00001Fh in byte mode). The
device is available preprogrammed with one of the following:
A random, secure ESN only
Customer code through Spansion programming services
Both a random, secure ESN and customer code through Spansion program-
ming services
Contact an your local sales office for details on using Spansion programming
services.
Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory
If the security feature is not required, the SecSi Sector can be treated as an ad-
ditional Flash memory space. The SecSi Sector can be read any number of times,
but can be programmed and locked only once. Note that the accelerated pro-
gramming (ACC) and unlock bypass functions are not available when
programming the SecSi Sector.
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The SecSi Sector area can be protected using one of the following procedures:
Write the three-cycle Enter SecSi Sector Region command sequence, and
then follow the in-system sector protect algorithm as shown in Figure 2, ex-
cept that RESET# may be at either VIH or VID. This allows in-system protec-
tion of the SecSi Sector Region without raising any device pin to a high
voltage. Note that this method is only applicable to the SecSi Sector.
To verify the protect/unprotect status of the SecSi Sector, follow the algo-
rithm shown in Figure 3.
Once the SecSi Sector is locked and verified, the system must write the Exit SecSi
Sector Region command sequence to return to reading and writing the remainder
of the array.
The SecSi Sector lock must be used with caution since, once locked, there is no
procedure available for unlocking the SecSi Sector area and none of the bits in
the SecSi Sector memory space can be modified in any way.
START
If data = 00h,
RESET# =
SecSi Sector is
unprotected.
VIH or VID
If data = 01h,
SecSi Sector is
protected.
Wait 1 ms
Write 60h to
any address
Remove VIH or VID
from RESET#
Write 40h to SecSi
Sector address
with A6 = 0,
command
A1 = 1, A0 = 0
Write reset
SecSi Sector
Protect Verify
Sector address
complete
Read from SecSi
with A6 = 0,
A1 = 1, A0 = 0
Figure 3. SecSi Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Table 4 for command
definitions). In addition, the following hardware data protection measures pre-
vent accidental erasure or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and power-down transitions,
or from system noise.
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This pro-
tects data during VCC power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
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mode. Subsequent writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# =
VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The system can read CFI information
at the addresses given in Tables 1–3. To terminate reading CFI data, the system
must write the reset command.The CFI Query mode is not accessible when the
device is executing an Embedded Program or embedded Erase algorithm.
The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 1–3. The system must write the reset
command to reading array data.
For further information, please refer to the CFI Specification and CFI Publication
100. Contact your local sales office for copies of these documents.
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Table 1. CFI Query Identification String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Table 7. System Interface String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
1Ch
36h
38h
0027h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0003h
0000h
0009h
0000h
0005h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N
µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
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Table 2. Device Geometry Definition
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Description
27h
4Eh
0017h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
007Dh
0000h
0000h
0001h
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
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Table 3. Primary Vendor-Specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
Query-unique ASCII string “PRI”
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII (reflects modifications to the silicon)
Minor version number, ASCII (reflects modifications to the CFI table)
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
000Ch
Silicon Revision Number (Bits 7-2)
Erase Suspend
46h
47h
48h
8Ch
8Eh
90h
0002h
0001h
0001h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
49h
92h
0004h
01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800
mode
Simultaneous Operation
00 = Not Supported, X = Number of Sectors (excluding Bank 1)
4Ah
4Bh
4Ch
94h
96h
98h
0077h
0000h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
9Ah
9Ch
0085h
0095h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom
Boot with Write Protect, 02h = Bottom Boot Device, 03h = Top Boot
Device, 04h= Both Top and Bottom
4Fh
9Eh
0001h
Program Suspend
50h
57h
58h
59h
5Ah
5Bh
A0h
AEh
B0h
B2h
B4h
B6h
0001h
0004h
0017h
0030h
0030h
0017h
0 = Not supported, 1 = Supported
Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
Bank 1 Region Information
X = Number of Sectors in Bank 1
Bank 2 Region Information
X = Number of Sectors in Bank 2
Bank 3 Region Information
X = Number of Sectors in Bank 3
Bank 4 Region Information
X = Number of Sectors in Bank 4
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Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 4 defines the valid register command
sequences. Writing incorrect address and data values or writing them in the im-
proper sequence may place the device in an unknown state. A reset command is
then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank
enters the erase-suspend-read mode, after which the system can read data from
any non-erase-suspended sector within the same bank. The system can read
array data using the standard read timing, except that if it reads at an address
within erase-suspended sectors, the device outputs status data. After completing
a programming operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See the Erase Suspend/Erase Re-
sume Commands section for more information.
The system must issue the reset command to return a bank to the read (or erase-
suspend-read) mode if DQ5 goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the next section, Reset
Command, for more information.
See also Requirements for Reading Array Data in the Device Bus Operations sec-
tion for more information. The Read-Only Operations table provides the read
parameters, and 14 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the bank to which
the system was writing to the read mode. If the program command sequence is
written to a bank that is in the Erase Suspend mode, writing the reset command
returns that bank to the erase-suspend-read mode. Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If a bank entered the autoselect mode while
in the Erase Suspend mode, writing the reset command returns that bank to the
erase-suspend-read mode.
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If DQ5 goes high during a program or erase operation, writing the reset command
returns the banks to the read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manu-
facturer and device codes, and determine whether or not a sector is protected.
The autoselect command sequence may be written to an address within a bank
that is either in the read or erase-suspend-read mode. The autoselect command
may not be written while the device is actively programming or erasing in another
bank.
The autoselect command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle that contains the bank address and the au-
toselect command. The bank then enters the autoselect mode. The system may
read any number of autoselect codes without reinitiating the command sequence.
Table 4 shows the address and data requirements. To determine sector protection
information, the system must write to the appropriate bank address (BA) and
sector address (SA). Table 3 shows the address range and bank number associ-
ated with each sector.
The system must write the reset command to return to the read mode (or erase-
suspend-read mode if the bank was previously in Erase Suspend).
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area containing a random, six-
teen-byte electronic serial number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi Sector command sequence.
The device continues to access the SecSi Sector region until the system issues
the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector com-
mand sequence returns the device to normal operation. The SecSi Sector is not
accessible when the device is executing an Embedded Program or embedded
Erase algorithm. Table 4 shows the address and data requirements for both com-
mand sequences. See also “SecSi™ (Secured Silicon) Sector
Flash Memory Region” for further information. Note that the ACC function and un-
lock bypass modes are not available when the SecSi Sector is enabled.
Byte/Word Program Command Sequence
The system may program the device by word or byte, depending on the state of
the BYTE# pin. Programming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The system is not required to
provide further controls or timings. The device automatically provides internally
generated program pulses and verifies the programmed cell margin. Table 4
shows the address and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete, that bank then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the
Write Operation Status section for information on these status bits.
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Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately terminates the program
operation. The program command sequence should be reinitiated once that bank
has returned to the read mode, to ensure data integrity. Note that the SecSi Sec-
tor, autoselect, and CFI functions are unavailable when a program operation is in
progress.
Programming is allowed in any sequence and across sector boundaries. A bit
cannot be programmed from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeeding read will show that the data
is still “0.” Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to a bank
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. That bank
then enters the unlock bypass mode. A two-cycle unlock bypass program com-
mand sequence is all that is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program command, A0h; the second
cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required
in the standard program command sequence, resulting in faster total program-
ming time. Table 4 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. (See Table
12).
The device offers accelerated program operations through the WP#/ACC pin.
When the system asserts VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then write the two-cycle Unlock
Bypass program command sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not
be at VHH for any operation other than accelerated programming, or device dam-
age may result. In addition, the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may result.
4 illustrates the algorithm for the program operation. Refer to the Erase and Pro-
gram Operations table in the AC Characteristics section for parameters, and
Figure 18 for timing diagrams.
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START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Table 4 for program command sequence.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Table 4 shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write
Operation Status section for information on these status bits.
Any commands written during the chip erase operation are ignored. However,
note that a hardware reset immediately terminates the erase operation. If that
occurs, the chip erase command sequence should be reinitiated once that bank
has returned to reading array data, to ensure data integrity. Note that the SecSi
Sector, autoselect, and CFI functions are unavailable when an erase operation is
in progress.
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5 illustrates the algorithm for the erase operation. Refer to the Erase and Program
Operations tables in the AC Characteristics section for parameters, and Figure 20
section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table 4 shows the address
and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire sector for
an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 80 µs occurs.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 80 µs, otherwise erasure
may begin. Any sector erase address and command following the exceeded time-
out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written. Any com-
mand other than Sector Erase or Erase Suspend during the time-out
period resets that bank to the read mode. The system must rewrite the com-
mand sequence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# or CE# pulse (first rising edge) in the command
sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading
array data and addresses are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Sta-
tus section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity. Note that the SecSi Sector, autoselect, and
CFI functions are unavailable when an erase operation is in progress.
5 illustrates the algorithm for the erase operation. Refer to the Erase and Program
Operations tables in the AC Characteristics section for parameters, and Figure 20
section for timing diagrams.
30
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 4 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 5. Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase
operation and then read data from, or program data to, any sector not selected
for erasure. The bank address is required when writing this command. This com-
mand is valid only during the sector erase operation, including the 80 µs time-out
period during the sector erase command sequence. The Erase Suspend command
is ignored if written during the chip erase operation or Embedded Program
algorithm. The bank address must contain one of the sectors currently selected
for erase.
When the Erase Suspend command is written during the sector erase operation,
the device requires a maximum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out period and suspends
the erase operation.
After the erase operation has been suspended, the bank enters the erase-sus-
pend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for
erasure.) Reading at any address within erase-suspended sectors produces sta-
tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer
to the Write Operation Status section for information on these status bits.
May 7, 2004 S29JL064HA1
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31
P r e l i m i n a r y
After an erase-suspended program operation is complete, the bank returns to the
erase-suspend-read mode. The system can determine the status of the program
operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program
operation. Refer to the Write Operation Status section for more information.
In the erase-suspend-read mode, the system can also issue the autoselect com-
mand sequence. The device allows reading autoselect codes even at addresses
within erasing sectors, since the codes are not stored in the memory array. When
the device exits the autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. Refer to the Autoselect Mode and
Autoselect Command Sequence sections for details.
To resume the sector erase operation, the system must write the Erase Resume
command. The bank address of the erase-suspended bank is required when writ-
ing this command. Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip has resumed erasing.
32
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
Table 4. S29JL064H Command Definitions
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Addr
Sixth
Addr Data Addr Data
Data
Addr
Data
Data
Addr
Data
Read (Note 6)
Reset (Note 7)
1
1
RA
RD
F0
XXX
555
AAA
555
AAA
555
AAA
555
Word
Byte
Word
Byte
Word
Byte
Word
2AA
555
2AA
555
2AA
555
2AA
(BA)555
(BA)AAA
(BA)555
(BA)AAA
(BA)555
(BA)AAA
(BA)555
Manufacturer ID
4
6
4
AA
AA
AA
55
55
55
90
90
90
(BA)X00
01
7E
(BA)X01
(BA)X02
(BA)X03
(BA)X06
(SA)X02
(BA)X0E
(BA)X1C
(BA)X0F
(BA)X1E
Device ID (Note 9)
02
01
SecSi Sector Factory
Protect (Note 10)
80/
00
Sector/Sector Block
Protect Verify
(Note 11)
00/
01
4
AA
55
90
Byte
AAA
555
(BA)AAA
(SA)X04
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555
AAA
555
AAA
555
AAA
555
AAA
XXX
XXX
555
AAA
555
AAA
BA
2AA
555
2AA
555
2AA
555
2AA
555
PA
XXX
2AA
555
2AA
555
555
AAA
555
AAA
555
AAA
555
AAA
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
AA
AA
AA
AA
55
55
55
55
88
90
A0
20
XXX
PA
00
PD
Unlock Bypass
Unlock Bypass Program (Note 12)
Unlock Bypass Reset (Note 13)
2
2
A0
90
PD
00
Word
Byte
Word
Byte
555
AAA
555
AAA
555
AAA
555
AAA
2AA
555
2AA
555
555
AAA
Chip Erase
6
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
Sector Erase
SA
Erase Suspend (Note 14)
Erase Resume (Note 15)
1
1
B0
30
BA
Word
CFI Query (Note 16)
Byte
55
AA
1
98
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A21–A12 uniquely select any sector. Refer to
Table 3 for information on sector addresses.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased. A21–A19 uniquely select a bank.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
9. The device ID must be read across the fourth, fifth, and sixth
cycles.
3. Except for the read cycle and the fourth, fifth, and sixth cycle of
the autoselect command sequence, all bus cycles are write
cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
5. Unless otherwise noted, address bits A21–A11 are don’t cares for
unlock and command cycles, unless SA or PA is required.
6. No unlock or command cycles required when bank is reading
array data.
7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high
(while the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. Data bits DQ15–DQ8 are don’t care. While reading
the autoselect addresses, the bank address must be the same
until a reset command is given. See the Autoselect Command
Sequence section for more information.
10. The data is 80h for factory locked, 40h for customer locked, and
00h for not factory/customer locked.
11. The data is 00h for an unprotected sector/sector block and 01h
for a protected sector/sector block.
12. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
13. The Unlock Bypass Reset command is required to return to the
read mode when the bank is in the unlock bypass mode.
14. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
16. Command is valid when device is ready to read array data or
when device is in autoselect mode.
May 7, 2004 S29JL064HA1
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33
P r e l i m i n a r y
Write Operation Status
The device provides several bits to determine the status of a program or erase
operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 8 and the following subsections
describe the function of these bits. DQ7 and DQ6 each offer a method for deter-
mining whether a program or erase operation is complete or in progress. The
device also provides a hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is in progress or has been
completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Program or Erase algorithm is in progress or completed, or whether a bank is in
Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse
in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then that bank returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide
an address within any of the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
bank returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
When the system detects DQ7 has changed from the complement to true data,
it can read valid data at DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the fol-
lowing read cycles. Just prior to the completion of an Embedded Program or Erase
operation, DQ7 may change asynchronously with DQ15–DQ8 (DQ7–DQ0 for x8-
only device) while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read the status or valid data.
Even if the device has completed the program or erase operation and DQ7 has
valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on
DQ15–DQ0 (or DQ7–DQ0 for x8-only device) will appear on successive read
cycles.
Table 8 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling
algorithm. 22 in the AC Characteristics section shows the Data# Polling timing
diagram.
34
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a
sector erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 6. Data# Polling Algorithm
May 7, 2004 S29JL064HA1
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35
P r e l i m i n a r y
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an
Embedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel with
a pull-up resistor to VCC
.
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is in the read mode, the standby mode, or one of the banks is in the
erase-suspend-read mode.
Table 8 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
36
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
START
Read Byte
(DQ7–DQ0)
Address =VA
Read Byte
(DQ7–DQ0)
Address =VA
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ7–DQ0)
Address = VA
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Program/Erase
Operation Complete
Complete, Write
Reset Command
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Figure 7. Toggle Bit Algorithm
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
May 7, 2004 S29JL064HA1
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37
P r e l i m i n a r y
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 8 to compare outputs for DQ2 and DQ6.
7 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle
Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. 23
shows the toggle bit timing diagram. 24 shows the differences between DQ2 and
DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to 7 for the following discussion. Whenever the system initially begins read-
ing toggle bit status, it must read DQ15–DQ0 (or DQ7–DQ0 for x8-only device)
at least twice in a row to determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit after the first read. After
the second read, the system would compare the new value of the toggle bit with
the first. If the toggle bit is not toggling, the device has completed the program
or erase operation. The system can read array data on DQ15–DQ0 (or DQ7–DQ0
for x8-only device) on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of 7).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified in-
ternal pulse count limit. Under these conditions DQ5 produces a “1,” indicating
that the program or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a
location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the device halts the opera-
tion, and when the timing limit has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write the reset command to return
to the read mode (or to the erase-suspend-read mode if a bank was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not erasure has begun. (The sector erase timer does not
38
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase commands from the system can be as-
sumed to be less than 50 µs, the system need not monitor DQ3. See also the
Sector Erase Command Sequence section.
After the sector erase command is written, the system should read the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device will accept addi-
tional sector erase commands. To ensure the command has been accepted, the
system software should check the status of DQ3 prior to and following each sub-
sequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 8 shows the status of DQ3 relative to the other status bits.
Table 8. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
1
No toggle
0
N/A
Toggle
1
Suspended Sector
Erase-Suspend-
Read
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing
limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded
Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
May 7, 2004 S29JL064HA1
S29JL064H
39
P r e l i m i n a r y
Absolute Maximum Ratings
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C
Voltage with Respect to Ground
V
(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
CC
OE# and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V
WP#/ACC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V
All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V +0.5 V
CC
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V to –
SS
2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V
+0.5 V. See Figure 8. During voltage
CC
transitions, input or I/O pins may overshoot to V +2.0 V for periods up to 20 ns. See Figure 9.
CC
2. Minimum DC input voltage on pins OE#, RESET#, and WP#/ACC is –0.5 V. During voltage transitions, OE#, WP#/ACC,
and RESET# may overshoot V to –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on WP#/
SS
ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one
second.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those indicated in the operational
sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods
may affect device reliability.
20 ns
20 ns
20 ns
+0.8 V
VCC
+2.0 V
–0.5 V
–2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 8. Maximum Negative
Overshoot Waveform
Figure 9. Maximum Positive
Overshoot Waveform
Operating Ranges
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
VCC Supply Voltages
VCC for standard voltage range . . . . . . . . . . . . . . . . . . . . . . . .2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is
guaranteed.
40
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
DC Characteristics
CMOS Compatible
Paramete
r Symbol
Parameter Description
Input Load Current
Test Conditions
Min
Typ
Max
Unit
VIN = VSS to VCC
VCC = VCC max
,
ILI
1.0
µA
OE# and RESET# Input Load
Current
VCC = VCC max, OE# = VIH;
OE# or RESET# = 12.5 V
ILIT
ILO
ILR
35
1.0
35
µA
µA
µA
VOUT = VSS to VCC
,
Output Leakage Current
Reset Leakage Current
VCC = VCC max, OE# = VIH
VCC = VCC max; RESET# =
12.5 V
5 MHz
10
2
16
4
CE# = VIL,OE# = VIH,
Byte Mode
1 MHz
5 MHz
1 MHz
VCC Active Read Current
(Notes 1, 2)
ICC1
mA
10
2
16
4
CE# = VIL, OE# =
VIH, Word Mode
VCC Active Write Current (Notes 2,
3)
ICC2
CE# = VIL, OE# = VIH, WE# = VIL
15
30
mA
ICC3
ICC4
VCC Standby Current (Note 2)
VCC Reset Current (Note 2)
CE#, RESET# = VCC 0.3 V
RESET# = VSS 0.3 V
0.2
0.2
5
5
µA
µA
VIH = VCC 0.3 V;
VIL = VSS 0.3 V
ICC5
ICC6
Automatic Sleep Mode (Notes 2, 4)
0.2
5
µA
Byte
CE# = VIL, OE# = VIH
Word
21
21
21
21
45
45
45
45
VCC Active Read-While-Program
Current (Notes 1, 2)
mA
Byte
CE# = VIL, OE# = VIH
Word
VCC Active Read-While-Erase
Current (Notes 1, 2)
ICC7
ICC8
mA
mA
VCC Active Program-While-Erase-
Suspended Current (Notes 2, 5)
CE# = VIL, OE# = VIH
17
35
VIL
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
VIH
0.7 x VCC
VCC + 0.3
Voltage for WP#/ACC Sector
Protect/Unprotect and Program
Acceleration
VHH
VCC = 3.0 V ± 10%
VCC = 3.0 V 10%
8.5
9.5
V
Voltage for Autoselect and
Temporary Sector Unprotect
VID
11.5
12.5
0.45
V
VOL
VOH1
VOH2
VLKO
Output Low Voltage
IOL = 2.0 mA, VCC = VCC min
IOH = –2.0 mA, VCC = VCC min
IOH = –100 µA, VCC = VCC min
V
V
0.85 VCC
VCC–0.4
2.3
Output High Voltage
Low VCC Lock-Out Voltage (Note 5)
2.5
V
Notes:
1. The I current listed is typically less than 2 mA/MHz, with OE# at V
.
IH
CC
2. Maximum I
specifications are tested with V = V max.
CC CC
CC
3.
I
active while Embedded Erase or Embedded Program is in progress.
CC
4. Automatic sleep mode enables the low power mode when addresses remain stable for t
current is 200 nA.
+ 30 ns. Typical sleep mode
ACC
5. Not 100% tested.
May 7, 2004 S29JL064HA1
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41
P r e l i m i n a r y
DC Characteristics
Zero-Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12
10
8
3.6 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 11. Typical ICC1 vs. Frequency
42
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
Test Conditions
3.3 V
2.7 kΩ
Device
Under
Test
C
L
6.2 k
Ω
Note: Diodes are IN3064 or equivalent
Figure 12. Test Setup
Table 5. Test Specifications
Test Condition
All Speeds
1 TTL gate
Unit
Output Load
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
5
0.0–3.0
1.5
ns
V
Input Pulse Levels
Input timing measurement reference levels
Output timing measurement reference levels
V
1.5
V
Key To Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
0.0 V
Figure 13. Input Waveforms and Measurement Levels
May 7, 2004 S29JL064HA1
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P r e l i m i n a r y
AC Characteristics
Read-Only Operations
Parameter
Speed Options
JEDEC
Std. Description
Test Setup
55
70
85 Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
55
70
85
85
ns
ns
CE#,
OE# = VIL
tAVQV
tACC
Address to Output Delay
Max
55
70
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
Output Enable to Output Delay
OE# = VIL
Max
Max
Max
Max
55
25
70
30
16
16
85
40
ns
ns
ns
ns
Chip Enable to Output High Z (Notes 1, 3)
Output Enable to Output High Z (Notes 1, 3)
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold Time
(Note 1)
tOEH
Toggle and
5
10
Data# Polling
Notes:
1. Not 100% tested.
2. See 12 and Table 5 for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V /2. The time from OE#
CC
high to the data bus driven to V /2 is taken as t
CC
DF
.
tRC
Addresses Stable
Addresses
tACC
CE#
OE#
tRH
tRH
tDF
tOE
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 14. Read Operation Timings
44
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S29JL064HA1 May 7, 2004
P r e l i m i n a r y
AC Characteristics
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 15. Reset Timings
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P r e l i m i n a r y
AC Characteristics
Word/Byte Configuration (BYTE#)
Parameter
Speed Options
JEDEC
Std.
tELFL/ ELFH
tFLQZ
tFHQV
Description
55
70
5
85
Unit
ns
t
CE# to BYTE# Switching Low or High
BYTE# Switching Low to Output HIGH Z
BYTE# Switching High to Output Active
Max
Max
Min
16
70
ns
55
85
ns
46
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
CE#
OE#
BYTE#
tELFL
Data Output
(DQ14–DQ0)
Data Output
(DQ7–DQ0)
BYTE#
Switching
from word
to byte
DQ14–DQ0
DQ15/A-1
Address
Input
DQ15
Output
mode
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte
to word
Data Output
(DQ7–DQ0)
Data Output
DQ14–DQ0
DQ15/A-1
(DQ14–DQ0)
mode
Address
Input
DQ15
Output
tFHQV
Figure 16. BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS
)
tHOLD (tAH
)
Note: Refer to the Erase/Program Operations table for t and t
specifications.
AH
AS
Figure 17. BYTE# Timings for Write Operations
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47
P r e l i m i n a r y
AC Characteristics
Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
Description
55
70
70
0
85
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Min
55
85
tAVWL
Min
Min
Min
Min
ns
Address Setup Time to OE# low during toggle bit
polling
tASO
tAH
15
40
0
ns
ns
ns
tWLAX
Address Hold Time
30
30
45
45
Address Hold Time From CE# or OE# high
during toggle bit polling
tAHT
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
40
0
ns
ns
ns
Data Hold Time
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
ns
ns
ns
CE# Hold Time
tWP
Write Pulse Width
25
25
30
30
0
35
30
tWPH
tSR/W
Write Pulse Width High
Latency Between Read and Write Operations
Byte
Word
5
tWHWH1
tWHWH1
Programming Operation (Note 2)
µs
µs
7
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
tWHWH2
tWHWH1
Typ
4
tWHWH2
tVCS
Sector Erase Operation (Note 2)
VCC Setup Time (Note 1)
Typ
Min
Min
Max
0.4
50
0
sec
µs
ns
tRB
Write Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
tBUSY
90
ns
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
48
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode.
Figure 18. Program Operation Timings
VHH
VIL or VIH
VIL or VIH
WP#/ACC
tVHH
tVHH
Figure 19. Accelerated Program Timing Diagram
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49
P r e l i m i n a r y
AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.
Figure 20. Chip/Sector Erase Operation Timings
50
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
AC Characteristics
tWC
Valid PA
tWC
tRC
tWC
Valid PA
tAH
Valid RA
Valid PA
Addresses
tCPH
tACC
tCE
CE#
OE#
tCP
tOE
tOEH
tGHWL
tWP
WE#
Data
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE# or CE2# Controlled Write Cycles
Figure 21. Back-to-back Read/Write Cycle Timings
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Valid Data
Status Data
True
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 22. Data# Polling Timings (During Embedded Algorithms)
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P r e l i m i n a r y
AC Characteristics
tAHT
tAS
Addresses
tAHT
tASO
CE#
tOEH
WE#
tCEPH
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 23. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 24. DQ2 vs. DQ6
52
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
AC Characteristics
Temporary Sector Unprotect
Parameter
JEDEC
Std
tVIDR
tVHH
Description
All Speed Options
Unit
ns
VID Rise and Fall Time (See Note)
VHH Rise and Fall Time (See Note)
Min
Min
500
250
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
Min
Min
4
4
µs
µs
RESET# Hold Time from RY/BY# High for
Temporary Sector Unprotect
tRRB
Note: Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 25. Temporary Sector Unprotect Timing Diagram
May 7, 2004 S29JL064HA1
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53
P r e l i m i n a r y
AC Characteristics
V
ID
IH
V
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Group Protect/Unprotect
Verify
40h
Data
60h
60h
1 µs
Sector Group Protect: 150 µs
Sector Group Unprotect: 15 ms
CE#
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram
54
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
AC Characteristics
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
JEDEC
Std.
tWC
tAS
Description
55
70
70
0
85
Unit
ns
tAVAV
tAVWL
tELAX
tDVEH
tEHDX
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
55
85
ns
tAH
tDS
tDH
30
30
40
40
0
45
45
ns
ns
Data Hold Time
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
ns
ns
CE# Pulse Width
CE# Pulse Width High
25
25
40
45
tCPH
30
Byte
5
7
Programming Operation
(Note 2)
tWHWH1
tWHWH1
µs
Word
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
tWHWH2
tWHWH1
tWHWH2
Typ
Typ
4
µs
Sector Erase Operation (Note 2)
0.4
sec
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
May 7, 2004 S29JL064HA1
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55
P r e l i m i n a r y
AC Characteristics
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings
56
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
Erase And Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
sec
sec
µs
Comments
Sector Erase Time
0.4
56
7
5
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
Word Program Time
210
120
30
Accelerated Byte/Word Program Time
Accelerated Chip Programming Time
Byte Program Time
4
µs
10
5
sec
µs
Excludes system level
overhead (Note 5)
150
126
84
Byte Mode
Word Mode
42
28
Chip Program Time
(Note 3)
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 100,000 cycles; checkerboard data
CC
pattern.
2. Under worst case conditions of 90°C, V
= 2.7 V, 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 4 for further information on command definitions.
6. The device has a minimum cycling endurance of 100,000 cycles per sector.
May 7, 2004 S29JL064HA1
S29JL064H
57
P r e l i m i n a r y
58
S29JL064H
S29JL064HA1 May 7, 2004
P r e l i m i n a r y
16 Mb SRAM (supplier 1)
16 Megabit (1Mb x 16 bit) CMOS SRAM
Functional Description
CE1#
H
X
X
L
CS2
X
OE#
X
WE#
X
LB#
X
X
H
L
UB#
X
IO
IO
Mode
Power
Standby
Standby
Standby
Active
0~7
8~15
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Deselected
L
X
X
X
Deselected
X
X
X
H
X
Deselected
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
L
X
L
L
Active
L
H
L
Active
L
L
H
L
High-Z
Dout
Active
L
L
L
Dout
Active
L
X
L
H
L
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
L
X
L
H
L
High-Z
Din
Active
L
X
L
L
Din
Active
Note: X means don’t care (must be low or high state).
Absolute Maximum Ratings
Item
Symbol
VIN,VOUT
VCC
Ratings
Unit
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Power Dissipation
-0.2 to VCC+0.3V (Max. 3.6V)
V
V
-0.2 to 3.6V
1.0
PD
W
Storage Temperature
TSTG
TA
-85 to 150
-40 to 85
°
C
C
Operating Temperature
°
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
February 25, 2004 SRAM_Samsung_01A2
16 Mb SRAM (supplier 1)
59
P r e l i m i n a r y
DC Characteristics
Recommended DC Operating Conditions (Note 1)
Item
Symbol
VCC
Min
Typ
3.0
0
Max
Unit
V
Supply voltage
Ground
2.7
3.3
VSS
0
2.2
0
VCC+0.2 (Note 2)
0.6
V
Input high voltage
Input low voltage
VIH
-
V
VIL
-0.2 (Note 3)
-
V
Notes:
1. T = -40 to 85
°C, otherwise specified.
A
2. Overshoot: Vcc+2.0V in case of pulse width ≤20ns.
3. Undershoot: -2.0V in case of pulse width ≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Capacitance (f=1MHz, T =25°C)
A
Item
Symbol
CIN
Test Condition
Min
Max
8
Unit
Input capacitance
Input/Output capacitance
VIN=0V
VIO=0V
-
-
pF
pF
CIO
10
Note: Capacitance is sampled, not 100% tested
DC Operating Characteristics
Typ
Min (Note) Max
Item
Symbol
Test Conditions
Unit
Input leakage current
ILI
VIN=VSS to VCC
-1
-1
-
-
1
1
µ
A
A
CE1#=VIH, CS2=VIL or OE#=VIH or WE#=VIL or
LB#=UB#=VIH, VIO=VSS to VCC
Output leakage current
ILO
µ
Cycle time=1
LB# 0.2V and/or UB#
VIN 0.2V or VIN
µ
s, 100% duty, IIO=0mA, CE1#
0.2V, CS2
VCC-0.2V
≤
0.2V,
VCC-0.2V,
ICC1
≤
≤
≥
-
-
-
-
5
µ
A
≤
≥
Average operating current
Cycle time=Min, IIO=0mA, 100% duty,
CE1#=VIL, CS2=VIH, LB#=VIL and/or
UB#=VIL, VIN=VIL or VIH
ICC2
70ns
30
mA
Output low voltage
Output high voltage
VOL
VOH
IOL = 2.1mA
IOH = -1.0mA
-
-
-
0.4
-
V
V
2.4
Other input = 0-VCC
Standby Current (CMOS)
ISB1
-
-5.0
25
µA
1. CE1#
≥
VCC-0.2V, CS2
≥VCC-0.2V (CE1# controlled) or
2. 0V CS2 0.2V (CS2 controlled)
≥
≤
Note: Typical values are measured at V =2.0V, T =25°C and not 100% tested.
CC
A
60
16 Mb SRAM (supplier 1)
SRAM_Samsung_01A2 February 25, 2004
P r e l i m i n a r y
AC Characteristics
Read/Write Charcteristics (V =2.7-3.3V)
CC
Parameter List
Read cycle time
Symbol
tRC
Min
70
-
Max
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
tAA
70
70
35
70
-
Chip select to output
tCO1, tCO2
tOE
-
Output enable to valid output
LB#, UB# valid to data output
Chip select to low-Z output
Output enable to low-Z output
LB#, UB# enable to low-Z output
Output hold from address change
Chip disable to high-Z output
OE# disable to high-Z output
UB#, LB# disable to high-Z output
Write cycle time
-
tBA
-
tLZ1, tLZ2
tOLZ
10
5
-
tBLZ
10
10
0
-
tOH
-
tHZ1, tHZ2
tOHZ
tBHZ
25
25
25
-
0
0
tWC
70
60
0
Chip select to end of write
Address set-up time
tCW1, tCW2
tAS
-
-
Address valid to end of write
Write pulse width
tAW
60
50
0
-
tWP
-
Write recovery time
tWR
-
Write to output high-Z
tWHZ
tDW
0
20
-
Data to write time overlap
Data hold from write time
End write to output low-Z
LB#, UB# valid to end of write
30
0
tDH
-
tOW
5
-
tBW
60
-
Data Retention Characteristics
Item
Symbol
Test Condition
VCC-0.2V (Note 1), VIN
VCC=1.5V, CE1# V-0.2V (Note 1),
Min
Typ
Max
Unit
VCC for data retention
VDR
CE1#
≥
≥0V
1.5
-
3.3
15
V
≥
1.0
(Note 2)
Data retention current
IDR
-
µA
VIN 0V
≥
Data retention set-up time
Recovery time
tSDR
tRDR
0
-
-
-
-
See data retention waveform
ns
tRC
Notes:
1. CE1#≤VCC-0.2, CS2≤VCC-0.2V (CE1# controlled) or 0≤CS2-0.2V (CS2 controlled)
2. Typical values are measured at T =26
°C and not 100% tested.
A
February 25, 2004 SRAM_Samsung_01A2
16 Mb SRAM (supplier 1)
61
P r e l i m i n a r y
Timing Diagrams
t
RC
Address
t
AA
t
OH
Data Valid
Data Out
Previous Data Valid
Figure 28. Timing Waveform of Read Cycle(1) (address controlled, CD#1=OE#=VIL, CS2=WE#=VIH, UB#
and/or LB#=VIL)
t
RC
Address
CS1#
CS2
t
OH
t
AA
t
CO1
t
CO2
t
HZ
t
BA
UB#, LB#
OE#
t
BHZ
t
OE
t
OLZ
t
OHZ
t
BLZ
t
LZ
Data out
High-Z
Data Valid
Notes:
1. t and t
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
OHZ
HZ
to output voltage levels.
2. At any given temperature and voltage condition, t (Max.) is less than t (Min.) both for a given device and from
HZ
LZ
device to device interconnection.
Figure 29. Timing Waveform of Read Cycle(2) (WE#=VIH
)
62
16 Mb SRAM (supplier 1)
SRAM_Samsung_01A2 February 25, 2004
P r e l i m i n a r y
t
WC
Address
t
CW(2)
t
WR(4)
CS1#
CS2
t
AW
t
BW
UB#, LB#
WE#
t
WP(1)
t
AS(3)
t
t
DH
DW
High-Z
High-Z
Data in
Data Valid
t
t
OW
WHZ
Data Undefined
Data out
Figure 30. Timing Waveform of Write Cycle(1) (WE# controlled)
t
WC
Address
t
WR(4)
t
t
CW(2)
AS(3)
CS1#
CS2
t
AW
t
BW
UB#, LB#
t
WP(1)
WE#
Data in
t
t
DW
DH
Data Valid
Data out
High-Z
High-Z
Figure 31. Timing Waveform of Write Cycle(2) (CS# controlled)
February 25, 2004 SRAM_Samsung_01A2
16 Mb SRAM (supplier 1)
63
P r e l i m i n a r y
t
WC
Address
CS1#
t
WR(4)
t
CW(2)
t
AW
CS2
t
BW
UB#, LB#
t
AS(3)
t
WP(1)
WE#
t
DH
t
DW
Data Valid
Data in
High-Z
Data out
High-Z
Notes:
1. A write occurs during the overlap(t ) of low CS1# and low WE#. A write begins when CS1# goes low and WE#
WP
goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double
byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The t
measured from the beginning of write to the end of write.
is
WP
2. t
is measured from the CS1# going low to the end of write.
CW
3. t is measured from the address valid to the beginning of write.
AS
4. t
is measured from the end of write to the address change. t
applied in case a write ends as CS1# or WE#
WR
WR
going high.
Figure 32. Timing Waveform of Write Cycle(3) (UB#, LB# controlled)
64
16 Mb SRAM (supplier 1)
SRAM_Samsung_01A2 February 25, 2004
P r e l i m i n a r y
CS1# Controlled
Data Retention Mode
t
tSDR
RDR
V
CC
2.7V
2.2V
V
DR
CS1#≥ V
CC
- 0.2V, CS2 ≥ V -0.2V
CC
CS1#
GND
CS2 Controlled
Data Retention Mode
V
CC
2.7V
CS2
t
t
SDR
RDR
V
DR
CS2 ≤ 0.2V
0.4V
GND
Figure 33. Data Retention Waveform
February 25, 2004 SRAM_Samsung_01A2
16 Mb SRAM (supplier 1)
65
P r e l i m i n a r y
66
16 Mb SRAM (supplier 1)
SRAM_Samsung_01A2 February 25, 2004
P r e l i m i n a r y
8 Mb pSRAM (supplier 2)
8 Megabit (512 K x 16 bit) Ultra-low Power
Asynchronous CMOS Pseudo SRAM
Features
Single Wide Power Supply Range
— 2.7 to 3.6 Volts
Very low standby current
— 65µA at 3.0V (Max)
Simple memory control
— Dual Chip Enables (CE1# and CE2)
— Byte control for independent byte operation
— Output Enable (OE#) for memory expansion
Very fast output enable access time
— 35ns OE# access time
Automatic power down to standby mode
TTL compatible three-state output driver
Operating Temperature
— -40°C to +85°C
Power Supply
— 2.3V - 3.6V
Speed
— 70ns @ 2.7V
General Description
The S71JL064H80—10/11/12 contains an integrated memory device containing
a low power 8 Mbit SRAM built using a self-refresh DRAM array organized as
512,288 words by 16 bits. It is designed to be identical in operation and interface
to standard 6T SRAMS. The device is designed for low standby and operating cur-
rent and includes a power-down feature to automatically enter standby mode.
The device operates with two chip enable (CE1# and CE2) controls and output
enable (OE#) to allow for easy memory expansion. Byte controls (UB# and LB#)
allow the upper and lower bytes to be accessed independently and can also be
used to deselect the device. The S71JL064H80 is optimal for various applications
where low-power is critical such as battery backup and hand-held devices. The
device can operate over a very wide temperature range of -40°C to +85°C and
is available in tested wafer format.
February 25, 2004 pSRAM_NanoAmp_03A2
8 Mb pSRAM (supplier 2)
67
P r e l i m i n a r y
Block Diagram
Address
Decode
Logic
Address
Inputs
A - A
Input/
512K x 16 bit
RAM Array
Output
Mux and
Buffers
0
18
I/O - I/O
0
7
I/O - I/O
8
15
CE1#
CE2
Control
Logic
WE#
OE#
UB#
LB#
Figure 34. Functional Block Diagram
Table 9. Functional Description
CE1#
CE2
WE#
X
OE#
X
UB#
X
LB#
X
I/O - I/O (Note 1)
MODE
POWER
Standby
Standby
Standby
Active
0
15
H
X
L
L
L
L
X
L
High Z
Standby (Note 2)
Standby (Note 2)
Standby
X
X
X
X
High Z
High Z
H
H
H
H
X
X
H
H
L
X (Note 3) L (Note 1) L (Note 1)
Data In
Data Out
High Z
Write
H
L
L (Note 1) L (Note 1)
L (Note 1) L (Note 1)
Read
Active
H
H
Active
Active
Notes:
1. When UB# and LB# are in select mode (low), I/O - I/O are affected as shown. When LB# only is in the select mode
0
15
only I/O - I/O7 are affected as shown. When UB# is in the select mode only I/O8 - I/O15 are affected as shown.
0
2. When the device is in standby mode, control inputs (WE#, OE#, UB#, and LB#), address inputs and data input/
outputs are internally isolated from any external influence and disabled from exerting any influence externally.
3. When WE# is invoked, the OE# input is internally disabled and has no effect on the circuit.
Absolute Maximum Ratings (See Note)
Item
Symbol
VIN,OUT
VCC
Rating
Unit
V
Voltage on any pin relative to VSS
Voltage on VCC Supply Relative to VSS
Operating Temperature
–0.3 to VCC+0.3
–0.3 to 4.5
V
TA
-40 to +85
°C
Note: Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at these or any other conditions above those indicated in the operating section of
68
8 Mb pSRAM (supplier 2)
pSRAM_NanoAmp_03A2 February 25, 2004
P r e l i m i n a r y
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
DC Characteristics
Operating Characteristics (Over Specified Temperature Range)
Typ.
Item
Symbol
VCC
VIH
Test Conditions
Min
2.7
(Note 1)
Max.
3.6
Unit
V
Supply Voltage
3.0
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
2.2
VCC+0.3
0.6
V
VIL
–0.3
VCC–0.4
V
VOH
VOL
ILI
IOH = -1.0mA
IOL = 2.0mA
V
0.4
0.5
0.5
V
VIN = 0 to VCC
µ
A
A
ILO
OE# = VIH or Chip Disabled
µ
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
ICC1
5.0
Read/Write Operating Supply Current
3.0
mA
mA
@ 1 µs Cycle Time (Note 2)
VCC=3.3 V, VIN=VIH or VIL Chip
Enabled, IOUT = 0
ICC2
ICC3
ICC4
5.0
VCC=3.6 V, VIN=VIH or VIL Chip
Enabled, IOUT = 0
25.0
23.0
Read/Write Operating Supply Current
@ 70ns Cycle Time (Note 2)
12.0
VCC=3.3 V, VIN=VIH or VIL Chip
Enabled, IOUT = 0
VIN = VCC or 0V
Chip Disabled
tA= 85oC, VCC = 3.0 V
Maximum Standby Current
(Standard Part)
ISB1
70.0
60.0
µ
A
A
VIN = VCC or 0V
Chip Disabled
tA= 85oC, VCC = 3.0 V
Maximum Standby Current
(Ultra Low Power Part)
ISB1
µ
Notes:
1. Typical values are measured at V =V Typ., TA=25°C, and not 100% tested.
CC
CC
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current
required to drive output capacitance expected in the actual system.
AC Characteristics
Table 10. Timing Test Conditions
Item
Input Pulse Level
Input Rise and Fall Time
0.1VCC to 0.9 VCC
5ns
Input and Output Timing Reference Levels
Operating Temperature
0.5 VCC
-40 °C to +85 °C
February 25, 2004 pSRAM_NanoAmp_03A2
8 Mb pSRAM (supplier 2)
69
P r e l i m i n a r y
Table 11. Timings
Speed Bins
55
70
Parameter List
Symbol
tRC
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
55
70
Address Access Time
tAA
55
55
30
55
70
70
35
70
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
tCO
tOE
tLB, tUB
tLZ
5
5
5
5
tOLZ
tLBZ, tUBZ
tHZ
5
5
0
20
20
20
0
25
25
25
tOHZ
tLBHZ, tUBHZ
tOH
0
0
0
0
10
55
45
45
45
45
0
10
70
55
55
55
55
0
tWC
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
tCW
tAW
tLBW, tUBW
tWP
Address Setup Time
tAS
Write Recovery Time
tWR
0
0
Write to High-Z Output
tWHZ
tDW
25
25
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
40
0
40
0
tDH
tOW
5
5
70
8 Mb pSRAM (supplier 2)
pSRAM_NanoAmp_03A2 February 25, 2004
P r e l i m i n a r y
Timing Diagrams
t
RC
Address
t
AA
t
OH
Previous Data Valid
Data Valid
Data Out
Figure 35. Timing of Read Cycle (CE1# = OE# = VIL, WE# = CE2 = VIH
)
t
RC
Address
CE1#
CE2
tAA
t
HZ
t
CO
t
LZ
t
OHZ
t
t
OE
OE#
t
OLZ
t
LB, UB
LB#, UB
Data Out
t
t
tLBLZ, UBLZ
t
LBHZ, UBHZ
High-Z
Data Valid
Figure 36. Timing Waveform of Read Cycle (WE# = VIH
)
February 25, 2004 pSRAM_NanoAmp_03A2
8 Mb pSRAM (supplier 2)
71
P r e l i m i n a r y
t
WC
Address
t
WR
t
AW
CE1#
CE2
t
CW
t
, t
LBW UBW
LB#, UB
t
t
AS
WP
WE#
Data In
t
t
DW
DH
High-Z
Data Valid
tWHZ
t
OW
High-Z
Data Out
Figure 37. Timing Waveform of Write Cycle (WE# Control)
t
WC
Address
t
t
AW
WR
CE1#
(for CE2 Control,
use inverted signal
t
CW
t
AS
t
, t
LBW UBW
LB#, UB
WE#
t
WP
t
t
DH
DW
Data In
Data Valid
High-Z
t
LZ
t
WHZ
Data Out
Figure 38. Timing Waveform of Write Cycle (CE1# Control)
72
8 Mb pSRAM (supplier 2)
pSRAM_NanoAmp_03A2 February 25, 2004
P r e l i m i n a r y
16 Mb pSRAM (supplier 2)
16 Megabit (1Mb x 16bit) Ultra-low Power
Asynchronous CMOS Pseudo SRAM
Features
Single Wide Power Supply Range
— 2.7 to 3.6 Volts
Very low standby current
— 100µA at 3.0V (Max)
Simple memory control
— Dual Chip Enables (CE1# and CE2)
— Byte control for independent byte operation
— Output Enable (OE#) for memory expansion
Very fast access time
— 55ns address access option
— 35ns OE# access time
Automatic power down to standby mode
TTL compatible three-state output driver
Operating Temperature
— -40°C to +85°C
Speed
— 70ns
— 55 ns
General Description
The S71JL064HA0-10/11/12 contains an integrated memory device containing a
low-power, 16 Mbit SRAM built using a self-refresh DRAM array organized as
1,024,576 words by 16 bits. It is designed to be identical in operation and inter-
face to standard 6T SRAMS. The device is designed for low standby and operating
current and includes a power-down feature to automatically enter standby mode.
The device operates with two chip enable (CE1# and CE2) controls and output
enable (OE#) to allow for easy memory expansion. Byte controls (UB# and LB#)
allow the upper and lower bytes to be accessed independently and can also be
used to deselect the device. The S71JL064HA0 is optimal for various applications
where low-power is critical, such as battery backup and hand-held devices. The
device can operate over a very wide temperature range of -40°C to +85°C and
is available in tested wafer format.
February 25, 2004 pSRAM_NanoAmp_02A2
16 Mb pSRAM (supplier 2)
73
P r e l i m i n a r y
Block Diagram
Address
Decode
Logic
Address
Inputs
A - A
Input/
1024K x 16 bit
RAM Array
Output
Mux and
Buffers
0
19
I/O - I/O
0
7
I/O - I/O
8
15
CE1#
CE2
Control
Logic
WE#
OE#
UB#
LB#
Figure 39. Functional Block Diagram
Table 12. Functional Description
CE1#
CE2
X
WE#
X
OE#
UB#/LB#
I/O (Note 1)
High Z
MODE
POWER
Standby
H
X
L
L
L
L
X
X
X
X
L
X
Standby (Note 2)
Standby (Note 4)
Standby (Note 4)
Write (Note 3)
Read
L
X
X
High Z
Standby
H
X
H
High Z
Standby
H
L
L (Note 3)
L (Note 3)
L (Note 3)
Data In
Data Out
High Z
Active -> Standby (Note 4)
Active -> Standby (Note 4)
Standby (Note 4)
H
H
H
H
H
Active
Notes:
1. When UB# and LB# are in select mode (low), I/O - I/O are affected as shown. When LB# only is in the select
0
15
mode only I/O - IO are affected as shown. When UB is in the select mode only I/O - I/O are affected as shown.
0
7
8
15
If both UB# and LB# are in the deselect mode (high), the chip is in a standby mode regardless of the state of CE1#
or CE2.#
2. When the device is in standby mode, control inputs (WE#, OE#, UB#, and LB), address inputs and data input/
outputs are internally isolated from any external influence and disabled from exerting any influence externally.
3. When WE# is invoked, the OE# input is internally disabled and has no effect on the circuit.
4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally
isolated from any external influence.
74
16 Mb pSRAM (supplier 2)
pSRAM_NanoAmp_02A2 February 25, 2004
P r e l i m i n a r y
Absolute Maximum Ratings (See Note)
Item
Symbol
VIN,OUT
VCC
Rating
–0.3 to VCC+0.3
–0.3 to 4.0
500
Unit
V
Voltage on any pin relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
V
PD
mW
°C
°C
Storage Temperature
TSTG
TA
–40 to 125
-40 to +85
Operating Temperature
Note: Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating section of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
DC Characteristics
Operating Characteristics (Over Specified Temperature Range)
Typ.
Item
Supply Voltage
Symbol
VCC
VIH
Comments
Min
2.7
(Note 1)
Max.
3.6
Unit
V
3.0
Input High Voltage
2.2
VCC+0.3
0.6
V
Input Low Voltage
VIL
–0.3
VCC-0.2
V
Output High Voltage
Output Low Voltage
VOH
VOL
ILI
IOH = -0.2 mA
IOL = 0.2 mA
V
0.2
0.5
0.5
V
Input Leakage Current
Output Leakage Current
Read/Write Operating Supply Current
VIN = 0 to VCC
µ
A
A
ILO
OE# = VIH or Chip Disabled
µ
VCC=VCCMAX, VIN=VIH/VIL
Chip Enabled, IOUT = 0
ICC1
5
mA
mA
@ 1 µs Cycle Time (Note 2)
Read/Write Operating Supply Current
@ Min Cycle Time (Note 2)
VCC=VCCMAX, VIN=VIH/VIL
Chip Enabled, IOUT = 0
ICC2
25
VIN = VCC or 0V
Chip Disabled
tA = 85°C, VCC= 3.0V
Standby Current
ISB
100.0
µA
Notes:
1. Typical values are measured at V =V Typ., T =25°C, and not 100% tested.
CC
CC
A
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current
required to drive output capacitance expected in the actual system.
February 25, 2004 pSRAM_NanoAmp_02A2
16 Mb pSRAM (supplier 2)
75
P r e l i m i n a r y
AC Characteristics
Timing Test Conditions
Item
Input Pulse Level
0.1 VCC to 0.9 VCC
5ns
Input Rise and Fall Time
Input and Output Timing Reference Levels
Operating Temperature
0.5 VCC
-40 °C to +85 °C
Timings
55
70
Item
Symbol
tRC
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
55
70
Address Access Time
tAA
55
55
30
55
70
70
35
70
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
tCO
tOE
tLB, tUB
tLZ
5
5
5
5
tOLZ
tLBZ, tUBZ
tHZ
5
5
0
25
25
25
0
25
25
25
tOHZ
tLBHZ, tUBHZ
tOH
0
0
0
0
10
55
50
50
50
50
0
10
70
55
55
55
55
0
tWC
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
tCW
tAW
tLBW, tUBW
tWP
Write Recovery Time
tWR
Write to High-Z Output
tWHZ
tAS
25
25
Address Setup Time
0
25
0
0
25
0
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
tDW
tDH
tOW
5
5
76
16 Mb pSRAM (supplier 2)
pSRAM_NanoAmp_02A2 February 25, 2004
P r e l i m i n a r y
Timings
t
RC
Address
t
AA
t
OH
Previous Data Valid
Data Valid
Data Out
Figure 40. Timing of Read Cycle (CE1# = OE# = VIL, WE# = CE2 = VIH
)
t
RC
Address
t
AA
CE1#
CE2
t
CO
t
LZ
t
HZ
t
t
OE
OE#
t
OLZ
t
OHZ
, t
LB UB
LB#, UB#
Data Out
t
, t
LBHZ UBHZ
t
, t
LBLZ UBLZ
High-Z
Data Valid
Figure 41. Timing Waveform of Read Cycle (WE# = VIH
)
February 25, 2004 pSRAM_NanoAmp_02A2
16 Mb pSRAM (supplier 2)
77
P r e l i m i n a r y
t
WC
Address
CE1#
t
WR
t
AW
t
CW
CE2
t
, t
LBW UBW
LB#, UB#
WE#
t
t
AS
WP
t
t
DH
DW
High-Z
Data Valid
Data In
t
WHZ
t
OW
High- Z
Data Out
Figure 42. Timing Waveform of Write Cycle (WE# Control)
t
WC
Address
CE1#
t
AW
t
WR
t
CW
t
AS
t
, t
LBW UBW
LB#, UB#
WE#
t
WP
t
t
DH
DW
Data Valid
Data In
t
WHZ
High- Z
Data Out
Figure 43. Timing Waveform of Write Cycle (CE1# Control, CE2 = High)
16 Mb pSRAM (supplier 2) pSRAM_NanoAmp_02A2 February 25, 2004
78
P r e l i m i n a r y
16 Mb pSRAM (supplier 4)
16 Megabit (1M x 16) CMOS Pseudo SRAM
Features
Organized as 1M words by 16 bits
Fast Cycle Time : 70 ns
Standby Current : 100 µA
Deep power-down Current : 10 µA (Memory cell data invalid)
Byte data control: LB# (DQ0 - 7), UB# (DQ8 - 15)
Compatible with low-power SRAM
Single Power Supply Voltage : 3.0V±0.3V
Description
The S71JL064HA0 Model #62 contains a 16M-bit Pseudo SRAM organized as 1M
words by 16 bits. It is designed with advanced CMOS technology specified RAM
featuring low-power static RAM-compatible function and pin configuration. This
device operates from a single power supply. Advanced circuit technology provides
both high speed and low power. It is automatically placed in low-power mode
when CS1# or both UB# and LB# are asserted high or CS2 is asserted low. There
are three control inputs. CS1# and CS2 are used to select the device, and output
enable (OE#) provides fast memory access. Data byte control pins (LB#,UB#)
provide lower and upper byte access. This device is well suited to various micro-
processor system applications where high speed, low power and battery backup
are required.
Pin Description
A0 – A19
=
=
=
=
=
=
=
=
=
=
Address Inputs
Data Inputs/Outputs
Chip Enable
Deep Power Down
Output Enable
Write Control
Lower Byte Control
Upper Byte Control
Power Supply
DQ0 – DQ15
CE1#
CE2
OE#
WE#
LB#
UB#
VCC
VSS
Ground
February 25, 2004 pSRAM_EtronTech_06A2
16 Mb pSRAM (supplier 4)
79
P r e l i m i n a r y
Operation Mode
MODE
CE1#
H
X
L
CE2
H
OE#
X
WE#
X
LB#
X
X
H
L
UB#
X
DQ0 to DQ7
High-Z
High-Z
High-Z
High-Z
High-Z
D-out
DQ8 to DQ15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D-out
POWER
Standby
Deep Power Down
Standby
Active
Deselect
Deselect
L
X
X
X
Deselect
H
X
X
H
X
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
L
H
H
H
L
H
H
H
H
H
L
L
H
X
L
L
Active
L
H
H
L
Active
L
H
L
H
L
High-Z
D-out
Active
L
H
L
L
D-out
Active
Lower Byte Write
Upper Byte Write
Word Write
L
H
X
L
H
L
D-in
High-Z
D-in
Active
L
H
X
L
H
L
High-Z
D-in
Active
L
H
X
L
L
D-in
Active
Note: X=don’t care. H=logic high. L=logic low.
Absolute Maxumum Ratings (see Note)
SYMBOL
VCC
RATING
VALUE
UNIT
V
Supply Voltage
-0.2 to +3.6
-0.2 to VCC + 0.3
-2.0 to +3.6
100
VIN
Input Voltages
V
VIN, VOUT
ISH
Output and output Voltages
Output short circuit current
Power Dissipation
V
mA
W
PD
1
Note: Absolute maximum DC requirements contains stress ratings only. Functional operation at the absolute maximum
limits is not implied or guaranteed. Extended exposure to maximum ratings may affect device reliability.
DC Characteristics
Table 13. DC Recommended Operating Conditions
SYMBOL
VDD
PARAMETER
Power Supply Voltage
Ground
MIN
TYP.
MAX
UNIT
2.7
3.0
3.3
VSS
0
2.2
-
-
-
0
V
VIH
Input High Voltage
Input Low Voltage
VCC + 0.2 (Note 1)
+0.6
VIL
-0.2 (Note 2)
Notes:
1. Overshoot: V + 2.0V in case of pulse width ≤ 20ns
CC
2. Undershoot: -2.0V in case of pulse width ≤ 20ns
3. Overshoot and undershoot are sampled, not 100% tested.
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16 Mb pSRAM (supplier 4)
pSRAM_EtronTech_06A2 February 25, 2004
P r e l i m i n a r y
Table 14. DC Characteristics (TA = -25°C to 85°C, VDD = 2.6 to 3.3V)
SYMBOL
PARAMETER
TEST CONDITION
MIN MAX UNIT
IIL
Input Leakage Current
VIN = VSS to VDD
-1
1
µA
VIO = VSS to VDD
ILO
Output Leakage Current
CE1# = VIH, CE2 = VIL or
OE# = VIH or WE# = VIL
-1
1
µA
Cycle time = Min., 100% duty,
IO = 0mA, CE1# = VIL, CE2 = VIH,
VIN = VIH or VIL
ICC1
Operating Current @ Min Cycle Time
I
-
-
-
35
5
mA
mA
Cycle time = 1
µ
s, 100% duty
0.2V,
-0.2V, V ≤ 0.2V
DD IN
I
= 0mA, CE1#
≤
IO
ICC2
Operating Current @ Max Cycle Time
Standby Current (CMOS)
CE2
≥
V
or V
≥
V
-0.2V
IN
DD
CE1# = VDD – 0.2V and
CE2 = VDD – 0.2V,
Other inputs = VSS ~ VCC
ISB1
100
µ
A
A
ISBD
VOL
Deep Power-down
Output Low Voltage
Output High Voltage
CE2
≤
0.2V, Other inputs = VSS ~ VCC
IOL = 2.1mA
10
0.4
-
µ
-
V
VOH
IOH = -1.0mA
2.4
V
AC Characteristics
Table 15. AC Characteristics and Operating Conditions (TA = -25°C to 85°C, VDD = 2.6 to 3.3V)
70
Cycle
Symbol
tRC
Parameter
Min
70
-
Max
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
tAA
Address Access Time
70
70
70
35
70
-
tCO1
tCO2
tOE
Chip Enable (CE#1) Access Time
Chip Enable (CE2) Access Time
Output Enable Access Time
-
-
-
tBA
Data Byte Control Access Time
Chip Enable Low to Output in Low-Z
Output Enable Low to Output in Low-Z
Data Byte Control Low to Output in Low-Z
Chip Enable High to Output in High-Z
Output Enable High to Output in High-Z
Data Byte Control High to Output in High-Z
Output Data Hold Time
-
tLZ
10
5
tOLZ
tBLZ
tHZ
-
10
-
-
25
25
25
-
tOHZ
tBHZ
tOH
-
-
10
February 25, 2004 pSRAM_EtronTech_06A2
16 Mb pSRAM (supplier 4)
81
P r e l i m i n a r y
Table 15. AC Characteristics and Operating Conditions (TA = -25°C to 85°C, VDD = 2.6 to 3.3V) (Continued)
70
Cycle
Symbol
tWC
Parameter
Write Cycle Time
Min
70
50
60
60
60
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
tWP
Write Pulse Width
tAW
Address Valid to End of Write
Chip Enable to End of Write
Data Byte Control to End of Write
Address Set-up Time
Write Recovery Time
WE# Low to Output High-Z
WE# High to Output in High-Z
Data to Write Overlap
Data Hold Time
-
tCW
-
tBW
-
tAS
-
tWR
0
-
tWZH
tOW
tDW
tDH
-
20
-
5
35
0
-
-
tWEH
WE# High Time
5
10
Table 16. AC Test Conditions
Parameter
Condition
Output load
50 pF
+
1 TTL Gate
Input pulse level
0.4 V, 2.4
Timing measurements
t , t
0.5
× VCC
5 ns
R
F
R
= 50 Ω
L
V
= 1.5 V
D
L
OUT
C
= 50 pF (see Note)
L
Z
= 50 Ω
0
Note: Including scope and jig capacitance
Figure 44. AC Test Loads
82
16 Mb pSRAM (supplier 4)
pSRAM_EtronTech_06A2 February 25, 2004
P r e l i m i n a r y
Deep Power Down Exit Sequence
CE1# = V
or V ,
IL
IH
CE2=V
IH
Deep Power
Down Mode
CE2=VIH
CE2=V
IL
or
CE2=V
CE1# =V
,
IH
IH
Power
on
Initial State
Active
CE2=V
IL
(Wait 200 µs)
UB#, LB# =V
IH
CE1# =V , CE2=V
UB# & LB# or/and LB# = V
,
Standby
Mode
IL
IH
Power Up Sequence
IL
Figure 45. State Diagram
Table 17. Standby Mode Characteristics
Power Mode
Standby
Memory Cell Data
Valid
Standby Current (µA)
Wait Time (µs)
100
10
0
Deep Power Down
Invalid
200
Timing Diagrams
t
RC
Address
t
AA
t
OH
t
OH
Previous Data Valid
Data Valid
Data Out
Note: CE1# = OE# = V , CE2 = WE# = V , UB# and/or LB# = V
IL
IH
IL
Figure 46. Read Cycle 1—Addressed Controlled
February 25, 2004 pSRAM_EtronTech_06A2
16 Mb pSRAM (supplier 4)
83
P r e l i m i n a r y
t
RC
Address
t
A
A
t
OH
t
CO
t
LZ
CE1#
t
HZ
t
BA
t
BLZ
UB#, LB#
t
BHZ
t
OE
OE#
t
OHZ
t
OLZ
High-Z
High-Z
Data Out
Data Valid
Note: CE2 = WE# = V
IH
Figure 47. Read Cycle 2—CS1# Controlled
t
WC
Address
t
WR
t
AW
t
CW
CE1#
t
UB#, LB#
BW
WE#
t
t
AS
t
t
DW
DH
High-Z
High-Z
Data In
Data Valid
t
WHZ
t
OW
Data Out
Data Undefined
Notes:
1. CE2 = V
IH
2. CE2 = WE# = V
IH
Figure 48. Write Cycle 1—WE# Controlled
84
16 Mb pSRAM (supplier 4)
pSRAM_EtronTech_06A2 February 25, 2004
P r e l i m i n a r y
t
WC
Address
t
WR
t
AW
t
AS
t
CW
CE1#
t
UB#, LB#
BW
WE#
t
WP
t
t
DH
DW
Data In
Data Valid
High-Z
Data Out
Notes:
1. CE2 = V
IH
2. CE2 = WE# = V
IH
Figure 49. Write Cycle 2—CS1# Controlled
t
WC
Address
tWR
t
AW
t
CE1#
CW
UB#, LB#
t
BW
t
AS
WE#
tWP
t
DH
t
DW
Data In
Data Valid
High-Z
Data Out
Notes:
1. CE2 = V
IH
2. CE2 = WE# = V
IH
Figure 50. Write Cycle3—UB#, LB# Controlled
February 25, 2004 pSRAM_EtronTech_06A2
16 Mb pSRAM (supplier 4)
85
P r e l i m i n a r y
200 µs
1µs
CE2
Wake Up
Deep Power
Down Mode
Suspend
Normal Operation
Normal Operation
Mode
CE1#
Figure 51. Deep Power-down Mode
µs
200
V
CC
CE2
CE1#
Figure 52. Power-up Mode
>
15µs
CE1#
WE#
<
t
RC
Address
Note: The S71JL064HA0 Model 61 has a timing that is not supported at read operation. Data will be lost if your system
has multiple invalid address signal shorter than t during over 15µs at the read operation shown above.
RC
Figure 53. Abnormal Timing
86
16 Mb pSRAM (supplier 4)
pSRAM_EtronTech_06A2 February 25, 2004
P r e l i m i n a r y
32 Mb pSRAM (Supplier 3)
32 Megabit CMOS Pseudo Static RAM
Features
Organized as 2,097,152 words by 16 bits
Single power supply voltage of 2.6 to 3.3 V
Direct TTL compatibility for all inputs and outputs
Deep power-down mode: Memory cell data invalid
Page operation mode:
— Page read operation by 8 words
Logic compatible with SRAM R/W (WE#) pin
Standby current
— Standby
70 µA
— Deep power-down standby 5 µA
Access Times:
— Access Time
70 ns
70 ns
25 ns
30 ns
— CE1# Access Time
— OE# Access Time
— Page Access Time
Description
The S71JL128HB0 contains a 33,554,432-bit, pseudo static random access mem-
ory (PSRAM) organized as 2,097,152 words by 16 bits. It provides high density,
high speed, and low power. The device operates single power supply. The device
also features SRAM-like W/R timing whereby the device is controlled by DE1#,
OE#, and WE# on asynchronous. The device has the page access operation. Page
size is 8 words. The device also supports deep power-down mode, realizing low-
power standby.
Pin Description
A0 to A20
=
=
=
=
=
=
=
=
=
=
=
Address Inputs
A0 to A2
I/O1 to I/O16
CE1#
CE2
WE#
OE#
LB#, UB#
VDD
GND
NC
Page Address Inputs
Data Inputs/Outputs
Chip Enable Input
Chip select Input
Write Enable Input
Output Enable Input
Data Byte Control Inputs
Power
Ground
No Connection
February 25, 2004 pSRAM_Toshiba_04A2
32 Mb pSRAM (Supplier 3)
87
P r e l i m i n a r y
Operation Mode
MODE
Read (Word)
CE1# CE2 OE# WE# LB# UB# Add
I/O1 to I/O8
DOUT
I/O9 to I/O16
DOUT
POWER
IDDO
IDDO
IDDO
IDDO
IDDO
IDDO
IDDO
IDDS
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
Read (Lower Byte)
Read (Upper Byte)
Write (Word)
DOUT
High-Z
DOUT
L
H
L
High-Z
DIN
X
X
X
H
X
X
L
DIN
Write (Lower Byte)
Write (Upper Byte)
Outputs Disabled
Standby
L
L
H
L
DIN
Invalid
DIN
L
H
X
X
X
Invalid
High-Z
High-Z
High-Z
H
X
X
X
X
X
High-Z
High-Z
High-Z
Deep Power-down Standby
IDDSD
Note: L = Low-level Input (V ), H = High-level Input (V ), X = V or V , High-Z = High impedance
IL
IH
IH
IL
Absolute Maxumum Ratings
SYMBOL
VDD
RATING
VALUE
-1.0 to 3.6
-1.0 to 3.6
-1.0 to 3.6
-40 to 85
-55 to 150
0.6
UNIT
V
Power Supply Voltage
Input Voltage
VIN
V
VOUT
Topr.
Output Voltage
V
Operating Temperature
Storage Temperature
Power Dissipation
°C
°C
W
Tstrg.
PD
IOUT
Short Circuit Output Current
50
mA
Note: (Stresses greater than listed under "Absolute Maximum Ratings" may cause permanent damage to the device
DC Characteristics
Table 18. DC Recommended Operating Conditions (TA = -40°C to 85°C)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
VDD
Power Supply Voltage
2.6
2.75
3.3
VDD + 0.3
(Note)
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
-
-
V
-0.3 (Note
0.4
Note: V (Min) -1.0 V with 10 ns pulse width; VIH(Max) VDD+1.0 V with 10 ns pulse width
IL
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32 Mb pSRAM (Supplier 3)
pSRAM_Toshiba_04A2 February 25, 2004
P r e l i m i n a r y
Table 19. DC Characteristics (TA = -40°C to 85°C, VDD = 2.6 to 3.3V)
SYMBOL
IIL
PARAMETER
TEST CONDITION
VIN = 0 V to VDD
MIN TYP. MAX UNIT
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
-1.0
-1.0
2.4
-
-
-
-
-
+1.0
+1.0
-
µ
A
A
ILO
Output disable, VOUT = 0 V to VDD
IOH = - 0.5 mA
µ
VOH
V
VOL
IOL = 1.0 mA
0.4
V
CE1# = VIL
CE2 = VIH, IOUT = 0 mA
IDDO1
Operating Current
tRC = min
-
-
-
-
40
25
mA
CE1# = VIL, CE2 = VIH,
Page add. cycling, IOUT = 0 mA
IDDO2
Page Access Operating Current
tPC = min
mA
IDDS
Standby Current (MOS)
CE1# = VDD - 0.2 V, CE2 = VDD - 0.2 V
CE2 = 0.2 V
-
-
-
-
70
5
µ
A
A
IDDSD
Deep Power-down Standby Current
µ
Notes:
1. I
depends on the cycle time.
DDO
2. I
depends on output loading. Specified values are defined with the output open condition.
DDO
Table 20. Capacitance (TA = 25°C, f = 1 MHz)
Symbol
CIN
Parameter
Test Condition
Max
10
Unit
Input Capacitance
Output Capacitance
VIN
=
GND
GND
pF
pF
COUT
VOUT
=
10
AC Characteristics
Table 21. AC Characteristics and Operating Conditions (TA = -40°C to 85°C, VDD = 2.6 to 3.3V)
Symbol
tRC
Parameter
Min
70
–
Max
10000
70
Unit
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tACC
tCO
Address Access Time
Chip Enable (CE#) Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold Time
–
70
tOE
–
25
tBA
–
25
tCOE
tOEE
tBE
10
0
–
–
0
–
tOD
–
20
tODO
tBD
–
20
–
20
tOH
10
70
30
–
tPM
Page Mode Time
10000
–
tPC
Page Mode Cycle Time
February 25, 2004 pSRAM_Toshiba_04A2
32 Mb pSRAM (Supplier 3)
89
P r e l i m i n a r y
Table 21. AC Characteristics and Operating Conditions (TA = -40°C to 85°C, VDD = 2.6 to 3.3V) (Continued)
Symbol
tAA
Parameter
Page Mode Address Access Time
Page Mode Output Data Hold Time
Write Cycle Time
Min
–
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
tAOH
tWC
10
70
50
70
60
60
0
–
10000
tWP
Write Pulse Width
–
–
–
–
–
–
–
–
20
–
–
–
–
–
–
–
–
tCW
Chip Enable to End of Write
Data Byte Control to End of Write
Address Valid to End of Write
Address Set-up Time
tBW
tAW
tAS
tWR
Write Recovery Time
0
tCEH
tWEH
tODW
tOEW
tDS
Chip Enable High Pulse Width
Write Enable High Pulse Width
WE# Low to Output High-Z
WE# High to Output Active
Data Set-up Time
10
6
–
0
30
0
tDH
Data Hold Time
tCS
CE2 Set-up Time
0
tCH
CE2 Hold Time
300
10
0
µs
tDPD
tCHC
tCHP
CE2 Pulse Width
ms
ns
CE2 Hold from CE1#
CE2 Hold from Power On
30
µs
Notes:
1. AC measurements are assumed t , t = 5 ns.
R
F
2. Parameters t , t
, t and t
define the time at which the output goes the open condition and are not output
ODW
OD ODO BD
voltage reference levels.
3. Data cannot be retained at deep power-down stand-by mode.
4. If OE# is high during the write cycle, the outputs will remain at high impedance.
5. During the output state of I/O signals, input signals of reverse polarity must not be applied.
6. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance.
7. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high
impedance.
Table 22. AC Test Conditions
Parameter
Output load
Condition
30 pF 1 TTL Gate
VDD 0.2 V, 0.2 V
+
Input pulse level
Timing measurements
Reference level
−
VDD
VDD
×
0.5
0.5
×
tR
,
tF
5 ns
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32 Mb pSRAM (Supplier 3)
pSRAM_Toshiba_04A2 February 25, 2004
P r e l i m i n a r y
Timing Diagrams
tRC
Addresses
A0 to A20
tACC
tOH
tCO
CE#1
Fixed High
CE2
OE#
tOD
tOE
tODO
WE#
tBA
LB#, UB#
tBE
tOEE
tBD
Indeterminate
High-Z
High-Z
D
OUT
Valid Data Out
I/O1 to I/O16
tCOE
Indeterminate
Figure 54. Read Cycle
February 25, 2004 pSRAM_Toshiba_04A2
32 Mb pSRAM (Supplier 3)
91
P r e l i m i n a r y
t
PM
Address
A0 toA2
t
t
t
t
PC
PC
PC
RC
Address
A3 to A20
CE1#
Fix-H
CE2
OE#
WE#
UB#, LB#
t
t
OD
OE
t
BD
t
BA
t
t
t
AOH
AOH
AOH
t
t
OEE
OH
t
BE
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
Hi-Z
Hi-Z
I/O1 to I/O1
t
COE
t
t
t
t
t
ODO
CO
AA
AA
AA
* Maximum 8 words
t
ACC
Figure 55. Page Read Cycle (8 words access)
92
32 Mb pSRAM (Supplier 3)
pSRAM_Toshiba_04A2 February 25, 2004
P r e l i m i n a r y
t
WC
Address
A0 to A20
t
t
WEH
AW
t
t
t
AS
WP
WR
WE#
t
t
CW
WR
CE#1
t
CH
CE2
t
t
BW
WR
UB#, LB#
t
t
OEW
ODW
D
OUT
(See Note 2)
Hi-Z
(See Note 4)
I/O1 to I/O16
t
t
DH
DS
D
IN
I/O1 to I/O16
Notes:
1. If OE# is high during the write cycle, the outputs will remain at high impedance
(See Note 3)
VALID DATA IN
(See Note 3)
2. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance
3. During the output state of I/O signals, input signals of reverse polarity must not be applied
4. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high
impedance
Figure 56. Write Cycle 1 (WE# controlled)
February 25, 2004 pSRAM_Toshiba_04A2
32 Mb pSRAM (Supplier 3)
93
P r e l i m i n a r y
t
WC
Address
A0 to A20
t
AW
t
t
t
AS
WP
WR
WE#
t
CEH
t
t
CW
WR
CE1#
CE2
t
CH
t
t
BW
WR
UB#, LB#
t
t
ODW
BE
D
OUT
Hi-Z
Hi-Z
I/O1 to I/O16
t
COE
t
t
DH
DS
D
IN
I/O1 to I/O16
Notes:
1. If OE# is high during the write cycle, the outputs will remain at high impedance
(See Note 2)
VALID DATA IN
2. During the output state of I/O signals, input signals of reverse polarity must not be applied
Figure 57. Write Cycle 2 (CE# controlled)
CE1#
t
DPD
CE2
t
t
CH
CS
Figure 58. Deep Power-down Timing
V
min
V
DD
DD
CE1#
CE2
t
CHC
t
CH
t
CHP
Figure 59. Power-on Timing
94
32 Mb pSRAM (Supplier 3)
pSRAM_Toshiba_04A2 February 25, 2004
P r e l i m i n a r y
over 10 µs
CE1#
WE#
Address
t
min
RC
Note: If multiple invalid address cycles shorter than tRC min occur for a period greater than 10 µs, at least one valid address
cycle over tRC min is required during that period.
Figure 60. Read Address Skew Provisions
over 10 µs
CE1#
t
min
WP
WE#
Address
t
min
WC
Note: If multiple invalid address cycles shorter than tWC min occur for a period greater than 10 µs, at least one valid address
cycle over tWC min, in addition to tWP min, is required during that period.
Figure 61. Write Address Skew Provisions
February 25, 2004 pSRAM_Toshiba_04A2
32 Mb pSRAM (Supplier 3)
95
P r e l i m i n a r y
96
32 Mb pSRAM (Supplier 3)
pSRAM_Toshiba_04A2 February 25, 2004
P r e l i m i n a r y
64 Mb pSRAM (supplier 3)
64 Megabit CMOS Pseudo Static SRAM
Features
Organized as 4,194,304 words by 16 bits
Single power supply voltage of 2.6 to 3.3 V
Direct TTL compatibility for all inputs and outputs
Deep power-down mode: Memory cell data invalid
Page operation mode:
— Page read operation by 8 words
Logic compatible with SRAM R/W (WE#) pin
Standby current
— Standby
100 µA
— Deep power-down standby 5 µA
Access Times:
— Access Time
70 ns
70 ns
25 ns
30 ns
— CE1# Access Time
— OE# Access Time
— Page Access Time
Description
The S71JL128HC0 contains a 67,108,864-bit, pseudo static random access mem-
ory (PSRAM) organized as 4,194,304 words by 16 bits. It provides high density,
high speed, and low power. The device operates on a single power supply. The
device also features SRAM-like W/R timing whereby the device is controlled by
DE1#, OE#, and WE# on asynchronous. The device has the page access opera-
tion. Page size is 8 words. The device also supports deep power-down mode,
realizing low-power standby.
Pin Description
A0 to A21
=
=
=
=
=
=
=
=
=
=
=
Address Inputs
A0 to A2
I/O1 to I/O16
CE1#
CE2
WE#
OE#
LB#, UB#
VDD
GND
NC
Page Address Inputs
Data Inputs/Outputs
Chip Enable Input
Chip select Input
Write Enable Input
Output Enable Input
Data Byte Control Inputs
Power
Ground
No Connection
February 25, 2004 pSRAM_Toshiba_05A2
64 Mb pSRAM (supplier 3)
97
P r e l i m i n a r y
Operation Mode
MODE
Read (Word)
CE1# CE2 OE# WE# LB# UB# Add
I/O1 to I/O8
DOUT
I/O9 to I/O16
DOUT
POWER
IDDO
IDDO
IDDO
IDDO
IDDO
IDDO
IDDO
IDDS
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
Read (Lower Byte)
Read (Upper Byte)
Write (Word)
DOUT
High-Z
DOUT
L
H
L
High-Z
DIN
X
X
X
H
X
X
L
DIN
Write (Lower Byte)
Write (Upper Byte)
Outputs Disabled
Standby
L
L
H
L
DIN
Invalid
DIN
L
H
X
X
X
Invalid
High-Z
High-Z
High-Z
H
X
X
X
X
X
High-Z
High-Z
High-Z
Deep Power-down Standby
IDDSD
Note: L = Low-level Input (V ), H = High-level Input (V ), X = V or V , High-Z = High impedance
IL
IH
IH
IL
Absolute Maxumum Ratings
SYMBOL
VDD
RATING
VALUE
-1.0 to 3.6
-1.0 to 3.6
-1.0 to 3.6
-25 to 85
-55 to 150
0.6
UNIT
V
Power Supply Voltage
Input Voltage
VIN
V
VOUT
Topr.
Output Voltage
V
Operating Temperature
Storage Temperature
Power Dissipation
°C
°C
W
Tstrg.
PD
IOUT
Short Circuit Output Current
50
mA
Note: (Stresses greater than listed under "Absolute Maximum Ratings" may cause permanent damage to the device
DC Characteristics
Table 23. DC Recommended Operating Conditions (TA = -25°C to 85°C)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
VDD
Power Supply Voltage
2.6
2.75
3.3
VDD + 0.3
(Note)
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
-
-
V
-0.3 (Note
0.4
Note: V (Min) -1.0 V with 10 ns pulse width; VIH(Max) VDD+1.0 V with 10 ns pulse width
IL
98
64 Mb pSRAM (supplier 3)
pSRAM_Toshiba_05A2 February 25, 2004
P r e l i m i n a r y
Table 24. DC Characteristics (TA = -25°C to 85°C, VDD = 2.6 to 3.3V)
SYMBOL
IIL
PARAMETER
TEST CONDITION
VIN = 0 V to VDD
MIN TYP. MAX UNIT
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
-1.0
-1.0
2.4
-
-
-
-
-
+1.0
+1.0
-
µA
ILO
Output disable, VOUT = 0 V to VDD
IOH = - 0.5 mA
mA
V
VOH
VOL
IOL = 1.0 mA
0.4
V
CE1# = VIL
CE2 = VIH, IOUT = 0 mA
IDDO1
Operating Current
tRC = min
-
-
-
-
50
25
mA
mA
CE1# = VIL, CE2 = VIH,
Page add. cycling, IOUT = 0 mA
IDDO2
Page Access Operating Current
tPC = min
IDDS
Standby Current (MOS)
CE1# = VDD - 0.2 V, CE2 = VDD - 0.2 V
CE2 = 0.2 V
-
-
-
-
100
5
µ
A
A
IDDSD
Deep Power-down Standby Current
µ
Notes:
1. I
depends on the cycle time.
DDO
2. I
depends on output loading. Specified values are defined with the output open condition.
DDO
Table 25. Capacitance (TA = 25°C, f = 1 MHz)
SYMBOL
CIN
PARAMETER
TEST CONDITION
MAX
10
UNIT
Input Capacitance
Output Capacitance
VIN
=
GND
GND
pF
pF
COUT
VOUT
=
10
AC Characteristics
Table 26. AC Characteristics and Operating Conditions (TA = -25°C to 85°C, VDD = 2.6 to 3.3V)
Symbol
tRC
Parameter
Min
70
–
Max
10000
70
Unit
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tACC
tCO
Address Access Time
Chip Enable (CE#) Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold Time
–
70
tOE
–
25
tBA
–
25
tCOE
tOEE
tBE
10
0
–
–
0
–
tOD
–
20
tODO
tBD
–
20
–
20
tOH
10
70
30
–
tPM
Page Mode Time
10000
–
tPC
Page Mode Cycle Time
February 25, 2004 pSRAM_Toshiba_05A2
64 Mb pSRAM (supplier 3)
99
P r e l i m i n a r y
Table 26. AC Characteristics and Operating Conditions (TA = -25°C to 85°C, VDD = 2.6 to 3.3V) (Continued)
Symbol
tAA
Parameter
Page Mode Address Access Time
Page Mode Output Data Hold Time
Write Cycle Time
Min
–
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
tAOH
tWC
10
70
50
70
60
60
0
–
10000
tWP
Write Pulse Width
–
–
–
–
–
–
–
–
20
–
–
–
–
–
–
–
–
tCW
Chip Enable to End of Write
Data Byte Control to End of Write
Address Valid to End of Write
Address Set-up Time
tBW
tAW
tAS
tWR
Write Recovery Time
0
tCEH
tWEH
tODW
tOEW
tDS
Chip Enable High Pulse Width
Write Enable High Pulse Width
WE# Low to Output High-Z
WE# High to Output Active
Data Set-up Time
10
15
–
0
30
0
tDH
Data Hold Time
tCS
CE2 Set-up Time
0
tCH
CE2 Hold Time
300
10
0
µs
tDPD
tCHC
tCHP
CE2 Pulse Width
ms
ns
CE2 Hold from CE1#
CE2 Hold from Power On
30
µs
Notes:
1. AC measurements are assumed t , t = 5 ns.
R
F
2. Parameters t , t
, t and t
define the time at which the output goes the open condition and are not output
ODW
OD ODO BD
voltage reference levels.
3. Data cannot be retained at deep power-down stand-by mode.
4. If OE# is high during the write cycle, the outputs will remain at high impedance.
5. During the output state of I/O signals, input signals of reverse polarity must not be applied.
6. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance.
7. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high
impedance.
Table 27. AC Test Conditions
Parameter
Output load
Condition
30 pF 1 TTL Gate
VDD 0.2 V, 0.2 V
+
Input pulse level
Timing measurements
Reference level
−
VDD
VDD
×
0.5
0.5
×
t , t
5 ns
R
F
100
64 Mb pSRAM (supplier 3)
pSRAM_Toshiba_05A2 February 25, 2004
P r e l i m i n a r y
Timing Diagrams
tRC
Addresses
A0 to A21
tACC
tOH
tCO
CE#1
Fixed High
CE2
OE#
tOD
tOE
tODO
WE#
tBA
LB#, UB#
tBE
tOEE
tBD
Indeterminate
High-Z
High-Z
D
OUT
Valid Data Out
I/O1 to I/O16
tCOE
Indeterminate
Figure 62. Read Cycle
February 25, 2004 pSRAM_Toshiba_05A2
64 Mb pSRAM (supplier 3)
101
P r e l i m i n a r y
t
PM
Address
A0 to A2
t
t
t
t
PC
PC
PC
RC
Address
A3 to A21
CE1#
Fix-H
CE2
OE#
WE#
UB#, LB#
t
t
OD
OE
t
BD
t
BA
t
t
t
AOH
AOH
AOH
t
t
OEE
OH
t
BE
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
Hi-Z
Hi-Z
I/O1 to I/O1
t
COE
t
t
t
t
t
ODO
CO
AA
AA
AA
* Maximum 8 words
t
ACC
Figure 63. Page Read Cycle (8 words access)
102
64 Mb pSRAM (supplier 3)
pSRAM_Toshiba_05A2 February 25, 2004
P r e l i m i n a r y
t
WC
Address
A0 to A21
t
t
WEH
AW
t
t
t
AS
WP
WR
WE#
t
t
CW
WR
CE#1
t
CH
CE2
t
t
BW
WR
UB#, LB#
t
t
OEW
ODW
D
OUT
(See Note 2)
Hi-Z
(See Note 4)
I/O1 to I/O16
t
t
DH
DS
D
IN
I/O1 to I/O16
Notes:
1. If OE# is high during the write cycle, the outputs will remain at high impedance
(See Note 3)
VALID DATA IN
(See Note 3)
2. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance
3. During the output state of I/O signals, input signals of reverse polarity must not be applied
4. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high
impedance
Figure 64. Write Cycle 1 (WE# controlled)
February 25, 2004 pSRAM_Toshiba_05A2
64 Mb pSRAM (supplier 3)
103
P r e l i m i n a r y
t
WC
Address
A0 to A21
t
AW
t
t
t
AS
WP
WR
WE#
t
CEH
t
t
CW
WR
CE1#
CE2
t
CH
t
t
BW
WR
UB#, LB#
t
t
ODW
BE
D
OUT
Hi-Z
Hi-Z
I/O1 to I/O16
t
COE
t
t
DH
DS
D
IN
I/O1 to I/O16
Notes:
1. If OE# is high during the write cycle, the outputs will remain at high impedance
(See Note 2)
VALID DATA IN
2. During the output state of I/O signals, input signals of reverse polarity must not be applied
Figure 65. Write Cycle 2 (CE# controlled)
CE1#
t
DPD
CE2
t
t
CH
CS
Figure 66. Deep Power-down Timing
V
min
V
DD
DD
CE1#
CE2
t
CHC
t
CH
t
CHP
Figure 67. Power-on Timing
104
64 Mb pSRAM (supplier 3)
pSRAM_Toshiba_05A2 February 25, 2004
P r e l i m i n a r y
over10 µs
CE1#
WE#
Address
t
min
RC
Note: If multiple invalid address cycles shorter than tRC min occur for a period greater than 10 µs, at least one valid address
cycle over tRC min is required during that period.
Figure 68. Read Address Skew Provisions
over 10 µs
CE1#
t
min
WP
WE#
Address
t
min
WC
Note: If multiple invalid address cycles shorter than tWC min occur for a period greater than 10 µs, at least one valid address
cycle over tWC min, in addition to tWP min, is required during that period.
Figure 69. Write Address Skew Provisions
February 25, 2004 pSRAM_Toshiba_05A2
64 Mb pSRAM (supplier 3)
105
P r e l i m i n a r y
106
64 Mb pSRAM (supplier 3)
pSRAM_Toshiba_05A2 February 25, 2004
P r e l i m i n a r y
8 Mb SRAM (supplier 1)
8 Megabit (x8/x16) CMOS SRAM
Functional Description
Table 28. Word Mode
CS1#
H
X
X
L
CS#2
X
OE#
X
WE# BYTE#
SA
X
X
X
X
X
X
X
X
X
X
X
LB#
X
X
H
L
UB#
X
DQ
DQ
Mode
Power
Standby
Standby
Standby
Active
0~7
8~15
X
X
X
H
H
H
H
H
L
X
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Deselected
L
X
X
X
Deselected
X
X
X
H
X
Deselected
H
H
H
L
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
L
H
X
L
L
Active
L
H
H
L
Active
L
H
L
H
L
High-Z
Dout
Active
L
H
L
L
Dout
Active
L
H
X
L
H
L
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
L
H
X
L
H
L
High-Z
Din
Active
L
H
X
L
L
Din
Active
Note: X = V or V
IL
IH
Table 29. Byte Mode
CS1# CS#2 OE# WE# BYTE#
SA
LB#
X
UB#
X
DQ
DQ
Mode
Power
Standby
Standby
Active
0~7
8~15
H
X
L
X
L
X
X
H
L
X
X
H
H
L
X
X
X
High-Z
High-Z
High-Z
Dout
High-Z
High-Z
DNU
Deselected
X
X
X
Deselected
H
H
H
VSS
VSS
VSS
SA (Note 2) DNU
SA (Note 2) DNU
SA (Note 2) DNU
DNU
DNU
DNU
Output Disabled
Lower Byte Read
Lower Byte Write
L
DNU
Active
L
X
Din
DNU
Active
Notes:
1. X = V or V
IL
IH
2. Address input for byte operation.
February 25, 2004 SRAM_Samsung_00A2
8 Mb SRAM (supplier 1)
107
P r e l i m i n a r y
Absolute Maximum Ratings
Item
Symbol
Ratings
-0.2 to VCC+0.3V (Max. 3.6V)
-0.2 to 3.6V
Unit
V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Power Dissipation
VIN,VOUT
VCC
V
PD
1.0
W
Operating Temperature
TA
-40 to 85
°C
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DC Characteristics
Recommended DC Operating Conditions
Item
Symbol
VCC
Min
Typ
3.0
0
Max
Unit
V
Supply voltage
Ground
2.7
3.3
VSS
0
2.2
0
VCC+0.2 (Note 1)
0.6
V
Input high voltage
Input low voltage
VIH
-
V
VIL
-0.2 (Note 2)
-
V
Notes:
1. Overshoot: Vcc+1.0V in case of pulse width ≤20ns.
2. Undershoot: -1.0V in case of pulse width ≤20ns.
3. Overshoot and undershoot are sampled, not 100% tested.
Capacitance (f=1MHz, T =25°C)
A
Item
Symbol
CIN
Test Condition
Min
Max
8
Unit
Input capacitance
Input/Output capacitance
VIN=0V
VIO=0V
-
-
pF
pF
CIO
10
Note: Capacitance is sampled, not 100% tested
108
8 Mb SRAM (supplier 1)
SRAM_Samsung_00A2 February 25, 2004
P r e l i m i n a r y
DC and Operating Characteristics
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
ILI
VIN=VSS to VCC
-1
-
1
mA
CE1#=VIH, CS2=VIL or OE#=VIH or WE#=VIL,
VIO=VSS to VCC
Output leakage current
ILO
-1
-
-
-
1
3
mA
mA
Cycle time=1
CS2 VCC-0.2V, BYTE#=VSS or VCC, VIN
VIN VCC-0.2V
µ
s, 100% duty, IIO=0mA, CE1#
≤0.2V,
ICC1
≥
≤0.2V or
≥
Average operating current
Cycle time=Min, IIO=0mA, 100% duty,
CE1#=VIL, CS2=VIH, BYTE#=VSS or VCC
VIN=VIL or VIH
ICC2
,
70ns
-
-
22
mA
Output low voltage
Output high voltage
VOL
VOH
IOL = 2.1mA
IOH = -1.0mA
-
-
-
0.4
V
V
2.4
CE1#
≥
VCC-0.2V, CS2
≥VCC-0.2V (CE1# controlled) or
Standby Current (CMOS)
ISB1
CS2
≤
0.2V(CS2 controlled), BYTE3=VSS or VCC,
-
-
15
mA
Other input =0~VCC
February 25, 2004 SRAM_Samsung_00A2
8 Mb SRAM (supplier 1)
109
P r e l i m i n a r y
AC Characteristics
Read/Write Charcteristics (V =2.7-3.3V)
CC
Parameter List
Read cycle time
Symbol
tRC
Min
70
-
Max
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip select to output
tAA
70
70
35
70
-
tCO1, tCO2
tOE
-
Output enable to valid output
UB#, LB# Access Time
-
tBA
-
Chip select to low-Z output
UB#, LB# enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB#, LB# disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
tLZ1, tLZ2
tBLZ
10
10
5
-
tOLZ
-
tHZ1, tHZ2
tBHZ
tOHZ
tOH
0
25
25
25
-
0
0
10
70
60
0
tWC
-
Chip select to end of write
Address set-up time
tCW
-
tAS
-
Address valid to end of write
UB#, LB# Valid to End of Write
Write pulse width
tAW
60
60
50
0
-
tBW
-
tWP
-
Write recovery time
tWR
-
Write to output high-Z
tWHZ
tDW
0
20
-
Data to write time overlap
Data hold from write time
End write to output low-Z
30
0
tDH
-
tOW
5
-
Data Retention Characteristics
Item
Symbol
VDR
Test Condition
CS1# VCC-0.2V
VCC=3.0V, CS1# VCC-0.2V
Min
1.5
-
Typ
Max
Unit
VCC for data retention
Data retention current
Data retention set-up time
Recovery time
≥
-
-
-
-
3.3
15
-
V
IDR
≥
µA
tSDR
tRDR
0
See data retention waveform
ns
tRC
-
Note: CE1#≤VCC-0.2V. CS2≤VCC-0.2V (CE1# controlled) or CS2≤0.2V (CS2 controlled), BYTE#=V or V
SS
CC
110
8 Mb SRAM (supplier 1)
SRAM_Samsung_00A2 February 25, 2004
P r e l i m i n a r y
Timing Diagrams
t
RC
Address
t
AA
t
OH
Data Valid
Data Out
Previous Data Valid
Figure 70. Timing Waveform of Read Cycle(1) (address controlled, CD#1=OE#=VIL, CS2=WE#=VIH, UB#
and/or LB#=VIL)
t
RC
Address
CS1#
CS2
t
OH
t
AA
t
CO1
t
CO2
t
HZ
t
BA
UB#, LB#
OE#
t
BHZ
t
OE
t
OLZ
t
OHZ
t
BLZ
t
LZ
Data out
High-Z
Data Valid
Notes:
1. t and t
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
HZ OHZ
2. At any given temperature and voltage condition, t (Max.) is less than t (Min.) both for a given device and from device to device
HZ LZ
interconnection.
Figure 71. Timing Waveform of Read Cycle(2) (WE#=VIH, if BYTE# is low, ignore UB#/LB# timing)
t
WC
Address
t
CW(2)
t
WR(4)
CS1#
CS2
t
AW
t
BW
UB#, LB#
WE#
t
WP(1)
t
AS(3)
t
t
DH
DW
High-Z
High-Z
Data in
Data Valid
t
t
OW
WHZ
Data Undefined
Data out
Figure 72. Timing Waveform of Write Cycle(1) (WE# controlled, if BYTE# is low, ignore UB#/LB# timing)
February 25, 2004 SRAM_Samsung_00A2 8 Mb SRAM (supplier 1) 111
P r e l i m i n a r y
t
WC
Address
CS#
t
t
CW(2)
AS(3)
t
WR(4)
t
AW
CS2
UB#, LB#
t
BW
t
WP(1)
WE#
t
t
DH
DW
Data Valid
Data in
Data out
High-Z
High-Z
Figure 73. Timing Waveform of Write Cycle(2) (CE1# controlled, if BYTE# is low, ignore UB#/LB# timing)
t
WC
Address
CS1#
t
)
CW(2
t
WR(4)
t
AW
CS2
t
CW(2)
t
BW
UB#, LB#
t
AS(3)
t
WP(1)
WE#
Data in
t
t
DH
DW
Data Valid
High-Z
Data out
High-Z
Notes:
1. A write occurs during the overlap(t ) of low CS1# and low WE#. A write begins when CS1# goes low and WE#
WP
goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double
byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The t
measured from the beginning of write to the end of write.
is
WP
2. t
is measured from the CS1# going low to the end of write.
CW
3. t is measured from the address valid to the beginning of write.
AS
4. t
is measured from the end of write to the address change. t
applied in case a write ends as CS1# or WE#
WR
WR
going high.
Figure 74. Timing Waveform of Write Cycle(3) (UB#, LB# controlled, BYTE# must be high)
112
8 Mb SRAM (supplier 1)
SRAM_Samsung_00A2 February 25, 2004
P r e l i m i n a r y
Data Retention Waveforms
Data Retention Mode
t
t
RDR
SDR
V
CC
2.7V
2.2V
V
DR
CS1# ≥ V - 0.2V
CC
CS1#
GND
Figure 75. CE1# Controlled
Data Retention Mode
V
CC
2.7V
CS2
t
t
SDR
RDR
V
DR
CS2≤ 0.2V
0.4V
GND
Figure 76. CS2 Controlled
February 25, 2004 SRAM_Samsung_00A2
8 Mb SRAM (supplier 1)
113
P r e l i m i n a r y
114
8 Mb SRAM (supplier 1)
SRAM_Samsung_00A2 February 25, 2004
P r e l i m i n a r y
Revision Summary
Revision A (February 23, 2004)
Initial release.
Revision A+1 (February 25, 2004)
Global
Corrected Supplier 4 Model Number to 62.
Revision A+2 (February 26, 2004)
Global
Corrected missed Supplier 4 Model Number to 62.
Revision A+3 (May 25, 2004)
S29JL064H Module
Removed Latchup Characteristics.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
FASL LLC. FASL LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided ìas isî
without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of
third-party rights, or any other warranty, express, implied, or statutory. FASL LLC assumes no liability for any damages of any kind arising out of the use of
the information in this document.
Copyright © 2003 FASL LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL
LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
May 25, 2004 S71JLxxxHxx_00A3
Revision Summary
115
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