S71NS032J80BJWRA0 [SPANSION]
Memory Circuit, 2MX16, CMOS, PBGA56, 9.20 X 8 MM, LEAD FREE, TFBGA-56;
| 型号： | S71NS032J80BJWRA0 |
| 厂家： | 
SPANSION |
| 描述： | Memory Circuit, 2MX16, CMOS, PBGA56, 9.20 X 8 MM, LEAD FREE, TFBGA-56 静态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S71NS-J
Stacked Multi-Chip Product (MCP)
110 nm CMOS 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Multiplexed Flash Memory with pSRAM
S71NS-J Cover Sheet
Data Sheet (Advance Information)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S71NS-J_00
Revision 03
Issue Date October 10, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or V range. Changes may also include those needed to clarify a
IO
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local Spansion sales office.
ii
S71NS-J
October 10, 2006 S71NS-J_00_03
S71NS-J
Stacked Multi-Chip Product (MCP)
110 nm CMOS 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Multiplexed Flash Memory with pSRAM
Data Sheet (Advance Information)
Features
Single 1.8 volt read, program and erase (1.7 to 1.95 V)
Simultaneous Read/Write operation
– Data can be continuously read from one bank while executing
erase/program functions in other bank
Multiplexed Data and Address for reduced
I/O count
– Zero latency between read and write operations
– A15–A0 multiplexed as DQ15–DQ0
Package
– Addresses are latched by AVD# control input when CE# low
– 56-ball Very Thin FBGA
Product Selector Guide
MCP
Flash
pSRAM
16 Mb
8 Mb
pSRAM Type
Mux pSRAM 2
Mux pSRAM 1
pSRAM Read
Asynchronous only
Asynchronous only
OPN
S71NS032JA0
S71NS032J80
S29NS032J
S29NS032J
S71NS032JA0BJWRT
S71NS032J80BJWRA
General Description
The products covered by this document are listed in the table below
Document
S29NS-J
Publication Identification Number
S29NS-J_00
muxpsram_06
muxpsram_05
8 Mb Multiplexed pSRAM Type 1
16Mb Multiplexed pSRAM Type 2 (Asynchronous only)
Publication Number S71NS-J_00
Revision 03
Issue Date October 10, 2006
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design
in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
1. MCP Block Diagram
VCC VCCQ
RESET#
ACC
CE#
Flash
Memory
OE#
WE#
CLK
RDY
AVD#
A19-A16
A20
A/DQ15 – A/DQ0
VSS VCC VSSQ VCCQ
F-RDY/R-WAIT
WAIT
LB#
pSRAM
UB#
CRE
CS#
VSS
VSSQ
Note:
A19 is shared for S71NS032JA0, but flash only for S71NS032J80.
2
S71NS-J
S71NS-J_00_03 October 10, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
2. Connection Diagram
Legend
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
NC
NC
No Connect
Flash, pSRAM Shared
NC
RFU
A21
A16
R-LB# R-UB#
RFU
A17
NC
Reserved for Future Use
F-RDY/
R-WAIT
VSS
A20
CLK
VCC
WE# F-ACC
A19
RFU
Flash Only
VCCQ
VSS
AVD#
RFU F-RST# F-WP# A-18
F-CE# VSSQ
pSRAM Only
A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8
OE#
G
A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0
H
J
NC
RFU
R-CE# R-CRE
RFU
NC
K
NC
NC
MCP
Flash-only Address
Shared Address
A19:A16
ADQ15:ADQ0
S71NS032JA0
S71NS032J80
A20
A18:A16
ADQ15:ADQ0
A20-A19
S71NS-J_00_03 October 10, 2006
S71NS-J
3
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
3. Input/Output Descriptions
Signal
R-UB#
Description
Flash
RAM
X
pSRAM Upper Byte Control
pSRAM Lower Byte Control
Address Inputs
R-LB#
X
A21–A16
X
X
X
ADQ15–ADQ0 Multiplexed Address/Data input/output
X
R-CE#
F-CE#
OE#
pSRAM Chip Select Input
X
Flash Chip Enable Input. Asynchronous relative to CLK for the Burst mode.
Output Enable Input. Asynchronous relative to CLK for the Burst mode.
Write Enable Input.
X
X
X
X
X
X
X
X
X
X
X
WE#
V
V
Device Power Supply (1.7 V–1.95 V).
CC
SS
Ground
NC
No Connect; not connected internally
Ready output; indicates the status of the Burst read. VOL= data invalid. WAIT# pin of pSRAM is
shared with Flash RDY pin for synchronous pSRAM.
RDY
X
X
Clock input. The first rising edge of CLK in conjunction with AVD# low latches address input and
activates burst mode operation. After the initial word is output, subsequent rising edges of CLK
increment the internal address counter. CLK should remain low during asynchronous access.
CLK is present on MuxpSRAM Type 3, but not on MuxpSRAM Type 2. As a result, it is a shared
signal on S71NS064JA0, but a flash-only signal on S71NS032J.
CLK
X
X
Address Valid input. Indicates to device that the valid address is present on the address inputs
(address bits A15–A0 are multiplexed, address bits A22–A16 are address only).
AVD#
V
= for asynchronous mode, indicates valid address; for burst mode, causes starting address to
X
X
IL
be latched on rising edge of CLK.
V
= device ignores address inputs
IH
F-RST#
F-ACC
R-CRE
Hardware reset input. V = device resets and returns to reading array data
IL
X
X
At 12 V, accelerates programming; automatically places device in unlock bypass mode. At V
,
IL
disables program and erase functions. Should be at V for all other conditions.
IH
Command Register Enable of pSRAM
I/O Power Supply (1.7 V to 1.95 V)
I/O Ground
X
X
X
V
V
X
X
CCQ
SSQ
4
S71NS-J
S71NS-J_00_03 October 10, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
4. Ordering Information
The order number (Valid Combination) is formed by the following:
S71NS
032
J
A0
BJ
W
RT
0
PACKING TYPE
0 = Tray
2 = 7-inch Tape and Reel
3 = 13-inch Tape and Reel
ADDITIONAL ORDERING OPTIONS
See Valid Combinations Table
TEMPERATURE RANGE
W = Wireless (–25°C to +85°C)
For Industrial (–40°C to +85°C), contact local sales office
PACKAGE TYPE
BJ = Very Thin Fine-Pitch BGA Lead (Pb)-Free LF35 Package
pSRAM DENSITY
A0 = 16 Megabit (1M x 16-Bit)
FLASH PROCESS TECHNOLOGY
J = 110 nm Floating Gate Technology
FLASH DENSITY
064 = 64 Megabit (4 M x 16-Bit)
032 = 32 Megabit (2M x 16-Bit)
DEVICE FAMILY
S71NS = Stacked Multi-Chip Product,
Simultaneous Read/Write, Burst Mode Flash Memory with Multiplexed I/O
1.8-Volt Operation, Top Boot Sectors, and pSRAM
Table 4.1 Valid Combinations
Process
Technology
pSRAM
Density
Base OPN
Density
Package Type Temperature
BJ
Options
RA
Packing Type
80
A0
S71NS
032
J
W
0, 2, 3
RT
S71NS-J_00_03 October 10, 2006
S71NS-J
5
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
5. Physical Dimensions
5.1
NLB056—56-Ball Very Thin Fine Pitch Ball Grid Array (FBGA)
9.2 x 8.0 mm Package
D1
A
D
eD
0.10
(2X)
C
14
13
12
11
10
9
SE
7
8
7
6
5
4
3
E
B
E1
eE
2
1
K
J H G F E D C B A
INDEX MARK
9
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.10
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
C
A2
A
A1
0.08
C
C
SIDE VIEW
6
56X
b
0.15
0.08
M
M
C
C
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
PACKAGE
JEDEC
NLB 056
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
9.20 mm x 8.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,
SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.20
0.85
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
9.20 BSC.
8.00 BSC.
4.50 BSC.
6.50 BSC.
10
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
14
56
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.25
0.30
0.35
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.50 BSC.
0.50 BSC
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
0.25 BSC.
SOLDER BALL PLACEMENT
A2 ~ A13,B1 ~ B14
DEPOPULATED SOLDER BALLS
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
C1,C2,C5,C6,C9,C10,C13,C14
D1,D2,D13,D14,E1,E2,E13,E14,F1,F2,F13,F14
G1,G2,G13,G14,H1,H2,H5,H6,H9,H10,H13,H14
J1 ~ J14, K2 ~ K13
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3507\ 16-038.22 \ 7.14.5
6
S71NS-J
S71NS-J_00_03 October 10, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
6. Revision History
6.1
6.2
Revision 01 (March 2, 2006)
Initial release.
Revision 02 (April 21, 2006)
Added the S71NS032JA0
Updated the MCP Block Diagram
Updated the Connection Diagram notes
Updated the Input/Output Descriptions
6.3
Revision 03 (October 10, 2006)
Added the S71NS032J80
Removed the S71NS064JA0
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, and combinations thereof are
trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
S71NS-J_00_03 October 10, 2006
S71NS-J
7
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