S71NS128JA0BAW32 [SPANSION]
Memory Circuit, 8MX16, CMOS, PBGA48, 10 X 11 MM, LEAD FREE COMPLIANT, FBGA-48;
| 型号： | S71NS128JA0BAW32 |
| 厂家： | 
SPANSION |
| 描述： | Memory Circuit, 8MX16, CMOS, PBGA48, 10 X 11 MM, LEAD FREE COMPLIANT, FBGA-48 |
| 文件： | 总23页 (文件大小：525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S71NS128JA0/S71NS064JA0
Stacked Multi-Chip Product (MCP)
128 Megabit (8 M x 16-Bit) and 64 Megabit (4 M x 16-Bit),
110 nm CMOS 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Flash Memories with
16 Megabit (1M x 16-Bit) pSRAM
ADVANCE
INFORMATION
Data Sheet
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Publication Number S71NS-JA0_00 Revision A Amendment 6 Issue Date September 22, 2005
A d v a n c e I n f o r m a t i o n
Notice On Data Sheet Designations
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S71NS128JA0/S71NS064JA0
S71NS-JA0_00_A6 September 22, 2005
S71NS128JA0/S71NS064JA0
Stacked Multi-Chip Product (MCP)
128 Megabit (8 M x 16-Bit) and 64 Megabit (4 M x 16-Bit),
110 nm CMOS 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Flash Memories with
16 Megabit (1M x 16-Bit) pSRAM
ADVANCE
INFORMATION
Data Sheet
Distinctive Characteristics
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Publication Number S71NS-JA0_00 Revision A Amendment 6 Issue Date September 22, 2005
A d v a n c e I n f o r m a t i o n
Contents
Notice On Data Sheet Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Physical Dimensions–S71NS128JA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
NLA048—48-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 10 x 11 mm Package ...........................................10
NLB044—44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 9.2 x 8 mm Package ..........................................11
Device History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Appendix B: Daisy Chain Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
pSRAM Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
pSRAM Device Bus Operations ...............................................................................................................................................16
pSRAM DC Characteristics ......................................................................................................................................................16
pSRAM AC Characteristics .......................................................................................................................................................16
pSRAM Device Operation ......................................................................................................................................................... 17
pSRAM Read Access ................................................................................................................................................................... 17
pSRAM Write Access ................................................................................................................................................................. 17
Configuration Register Access ................................................................................................................................................. 17
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Tables
Table 1 Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figures
Figure 1 NLA048 Daisy Chain Layout (Top View, Balls Facing Down).................................................................................................... 14
Figure 2 NLB044 Daisy Chain Layout (Top View, Balls Facing Down)..................................................................................................... 15
Figure 3 Configuration Register Read Access.................................................................................................................................................. 18
Figure 4 Configuration Register Write Access................................................................................................................................................. 18
Figure 5 pSRAM Read Cycle 1 (WE# = VIH)..................................................................................................................................................... 19
Figure 6 pSRAM Read Cycle 2 (WE# = VIH).................................................................................................................................................... 19
Figure 7 pSRAM Write Cycle 1 (OE# = VIH)................................................................................................................................................... 20
Figure 8 pSRAM Write Cycle 2 (OE# = VIH)................................................................................................................................................. 20
2
S71NS128JA0/S71NS064JA0
S71NS-JA0_00_A6 September22,2005
A d v a n c e I n f o r m a t i o n
Product Selector Guide
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S71NS128JA0/S71NS064JA0
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S71NS128JA0/S71NS064JA0
S71NS-JA0_00_A6 September 22, 2005
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September 22, 2005 S71NS-JA0_00_A6
S71NS128JA0/S71NS064JA0
7
A d v a n c e I n f o r m a t i o n
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S71NS-JA0_00_A6 September 22, 2005
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September 22, 2005 S71NS-JA0_00_A6
S71NS128JA0/S71NS064JA0
9
A d v a n c e I n f o r m a t i o n
Physical Dimensions–S71NS128JA0
NLA048—48-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 10 x 11 mm Package
A
D
D1
A1 CORNER
INDEX MARK
A1 CORNER
10
10
9
8
7
6
5
4
3
2
1
NF2
NF1
NF3
NF4
A
B
C
D
e
E1
E
SE
1.00
7
NF5
NF6
1.00
NF7
NF8
B
TOP VIEW
SD
7
1.00
1.00
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6
0.10
0.08
C
A2
φ0.05 M
φ0.15 M
C
C
A
A
B
A1
C
C
BOTTOM VIEW
SEATING PLANE
SIDE VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
PACKAGE
JEDEC
NLA 048
N/A
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
9.95 mm x 10.95 mm NOM
PACKAGE
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL
MIN
1.05
0.20
0.85
9.85
10.85
NOM
---
MAX
1.20
---
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
A
A1
A2
D
OVERALL THICKNESS
BALL HEIGHT
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
---
0.91
0.97
BODY THICKNESS
N IS THE TOTAL NUMBER OF SOLDER BALLS.
9.95
10.05 BODY SIZE
11.05 BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E
10.95
4.50 BSC.
1.50 BSC.
10
D1
E1
MD
ME
N
BALL FOOTPRINT
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
4
48
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
φb
0.25
0.30
0.35
BALL DIAMETER
e
0.50 BSC.
0.25 BSC.
---
BALL PITCH
8. NOT USED.
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
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S71NS128JA0/S71NS064JA0
S71NS-JA0_00_A6 September 22, 2005
A d v a n c e I n f o r m a t i o n
Physical Dimensions–S71NS064JA0
NLB044—44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 9.2 x 8 mm Package
A
D
A1 CORNER
INDEX MARK
D1
A1 CORNER
10
10
9
8
7
6
5
4
3
2
1
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NF1
e
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B
C
D
E1
E
SE
7
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0.10
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A
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φ0.15
M
M
C
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A1
0.08
C
SEATING PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
PACKAGE
JEDEC
NLB 044
N/A
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
8.00 mm x 9.20 mm NOM
PACKAGE
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL
MIN
1.05
0.20
0.85
7.90
9.10
NOM
---
MAX
1.20
---
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
A
A1
A2
D
OVERALL THICKNESS
BALL HEIGHT
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
---
0.91
0.97
8.10
9.30
BODY THICKNESS
BODY SIZE
N IS THE TOTAL NUMBER OF SOLDER BALLS.
8.00
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E
9.20
BODY SIZE
D1
E1
MD
ME
N
4.50 BSC.
1.50 BSC.
10
BALL FOOTPRINT
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
4
44
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
φb
0.25
0.30
0.35
BALL DIAMETER
e
0.50 BSC.
0.25 BSC.
---
BALL PITCH
8. NOT USED.
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3298 \ 16-038.22a1
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September 22, 2005 S71NS-JA0_00_A6
S71NS128JA0/S71NS064JA0
11
A d v a n c e I n f o r m a t i o n
Device History
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12
S71NS128JA0/S71NS064JA0
S71NS-JA0_00_A6 September 22, 2005
A d v a n c e I n f o r m a t i o n
Appendix A: Daisy Chain Information
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September 22, 2005 S71NS-JA0_00_A6
S71NS128JA0/S71NS064JA0
13
A d v a n c e I n f o r m a t i o n
NF2
NF1
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2
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6
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8
9
10
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B
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Figure 1 NLA048 Daisy Chain Layout (Top View, Balls Facing Down)
14
S71NS128JA0/S71NS064JA0
S71NS-JA0_00_A6 September 22, 2005
A d v a n c e I n f o r m a t i o n
Appendix B: Daisy Chain Information
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Figure 2 NLB044 Daisy Chain Layout (Top View, Balls Facing Down)
September 22, 2005 S71NS-JA0_00_A6
S71NS128JA0/S71NS064JA0
15
A d v a n c e I n f o r m a t i o n
pSRAM Characteristics
pSRAM Device Bus Operations
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S71NS128JA0/S71NS064JA0
S71NS-JA0_00_A6 September 22, 2005
A d v a n c e I n f o r m a t i o n
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September 22, 2005 S71NS-JA0_00_A6
S71NS128JA0/S71NS064JA0
17
A d v a n c e I n f o r m a t i o n
pSRAM Characteristics
Configuration Register Access
(Continued)
Table 1 Configuration Register
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Figure 3 Configuration Register Read Access
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Figure 4 Configuration Register Write Access
18
S71NS128JA0/S71NS064JA0
S71NS-JA0_00_A6 September 22, 2005
A d v a n c e I n f o r m a t i o n
pSRAM Characteristics
pSRAM Read Access Timing Diagrams
A/DQ15-0
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September 22, 2005 S71NS-JA0_00_A6
S71NS128JA0/S71NS064JA0
19
A d v a n c e I n f o r m a t i o n
pSRAM Characteristics
pSRAM Write Access Timing Diagrams
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20
S71NS128JA0/S71NS064JA0
S71NS-JA0_00_A6 September 22, 2005
A d v a n c e I n f o r m a t i o n
Revision Summary
Revision A0 (December 8, 2003)
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Revision A1 (February 5, 2004)
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September 22, 2005 S71NS-JA0_00_A6
S71NS128JA0/S71NS064JA0
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A d v a n c e I n f o r m a t i o n
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-
mentioned uses of the products. Any semiconductor device has an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-
port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2003-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and
product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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S71NS128JA0/S71NS064JA0
S71NS-JA0_00_A6 September 22, 2005
相关型号：
S71NS128JA0BAW33
Memory Circuit, 8MX16, CMOS, PBGA48, 10 X 11 MM, LEAD FREE COMPLIANT, FBGA-48
SPANSION
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