S71NS256PC0ZJETW0

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品牌:SPANSION
描述:Memory IC,

S71NS256PC0ZJETW0 概述

Memory IC, 其他内存集成电路

S71NS256PC0ZJETW0 规格参数

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包装说明:,Reach Compliance Code:unknown
风险等级:5.69Base Number Matches:1

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S71NS-P Memory Subsystem Solutions  
MirrorBit® 1.8 Volt-only Simultaneous Read/Write,  
Burst Mode Multiplexed Flash Memory and Burst Mode  
Multiplexed pSRAM  
256 Mb (16 Mb x 16-bit) and 128 Mb (8 Mb x 16-bit) Flash  
64 Mb (4 Mb x 16-bit), and 32 Mb (2 Mb x 16-bit) pSRAM  
S71NS-P Memory Subsystem Solutions Cover Sheet  
Data Sheet (Preliminary)  
Notice to Readers: This document states the current technical specifications regarding the Spansion  
product(s) described herein. Each product described herein may be designated as Advance Information,  
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.  
Publication Number S71NS-P_00  
Revision 07  
Issue Date March 30, 2010  
D a t a S h e e t ( P r e l i m i n a r y )  
Notice On Data Sheet Designations  
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of  
product information or intended specifications throughout the product life cycle, including development,  
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify  
that they have the latest information before finalizing their design. The following descriptions of Spansion data  
sheet designations are presented here to highlight their presence and definitions.  
Advance Information  
The Advance Information designation indicates that Spansion Inc. is developing one or more specific  
products, but has not committed any design to production. Information presented in a document with this  
designation is likely to change, and in some cases, development on the product may discontinue. Spansion  
Inc. therefore places the following conditions upon Advance Information content:  
“This document contains information on one or more products under development at Spansion Inc.  
The information is intended to help you evaluate this product. Do not design in this product without  
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed  
product without notice.”  
Preliminary  
The Preliminary designation indicates that the product development has progressed such that a commitment  
to production has taken place. This designation covers several aspects of the product life cycle, including  
product qualification, initial production, and the subsequent phases in the manufacturing process that occur  
before full production is achieved. Changes to the technical specifications presented in a Preliminary  
document should be expected while keeping these aspects of production under consideration. Spansion  
places the following conditions upon Preliminary content:  
“This document states the current technical specifications regarding the Spansion product(s)  
described herein. The Preliminary status of this document indicates that product qualification has been  
completed, and that initial production has begun. Due to the phases of the manufacturing process that  
require maintaining efficiency and quality, this document may be revised by subsequent versions or  
modifications due to changes in technical specifications.”  
Combination  
Some data sheets contain a combination of products with different designations (Advance Information,  
Preliminary, or Full Production). This type of document distinguishes these products and their designations  
wherever necessary, typically on the first page, the ordering information page, and pages with the DC  
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first  
page refers the reader to the notice on this page.  
Full Production (No Designation on Document)  
When a product has been in production for a period of time such that no changes or only nominal changes  
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include  
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed  
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a  
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following  
conditions to documents in this category:  
“This document states the current technical specifications regarding the Spansion product(s)  
described herein. Spansion Inc. deems the products to have been in sufficient production volume such  
that subsequent versions of this document are not expected to change. However, typographical or  
specification corrections, or modifications to the valid combinations offered may occur.”  
Questions regarding these document designations may be directed to your local sales office.  
2
S71NS-P Memory Subsystem Solutions  
S71NS-P_00_07 March 30, 2010  
S71NS-P Memory Subsystem Solutions  
MirrorBit® 1.8 Volt-only Simultaneous Read/Write,  
Burst Mode Multiplexed Flash Memory and Burst Mode  
Multiplexed pSRAM  
256 Mb (16 Mb x 16-bit) and 128 Mb (8 Mb x 16-bit) Flash  
64 Mb (4 Mb x 16-bit), and 32 Mb (2 Mb x 16-bit) pSRAM  
Data Sheet (Preliminary)  
Features  
„ Power supply voltage of 1.7 V to 1.95 V  
„ MCP BGA Package  
– 56 ball, 9.2 x 8.0 mm, 0.5 mm ball pitch  
„ Burst Speed (Flash and pSRAM): 66 MHz, 83 MHz  
„ Operating Temperature  
– Wireless, –25°C to +85°C  
General Description  
The S71NS-P Series is a product line of stacked Multi-Chip Package (MCP) memory solutions and consists of the following  
items:  
„ One or more S29NS-P flash memory die  
„ Multiplexed pSRAM  
The products covered by this document are listed in the table below. For details about their specifications, please refer to their  
individual data sheet for further details.  
pSRAM  
Density  
128 Mb  
256 Mb  
32 Mb  
64 Mb  
S71NS128PB0  
S71NS256PB0  
S71NS128PC0  
S71NS256PC0  
Flash  
For detailed specifications, please refer to the individual data sheets:  
Document  
Publication Identification Number  
S29NS-P  
S29NS-P_00  
muxpsram_10  
muxpsram_01  
32 M Multiplexed pSRAM Type 3  
64 M Multiplexed pSRAM Type 3  
Publication Number S71NS-P_00  
Revision 07  
Issue Date March 30, 2010  
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual-  
ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document  
may be revised by subsequent versions or modifications due to changes in technical specifications.  
D a t a S h e e t ( P r e l i m i n a r y )  
1. Ordering Information  
The order number is formed by a valid combinations of the following:  
S71NS  
256  
P
C
0
ZJ  
E
TV  
0
Packing Type  
0
2
3
= Tray  
= 7-inch Tape and Reel  
= 13-inch Tape and Reel  
Model Number  
See Valid Combinations table below  
Package Modifier  
E
= 9.2 x 8.0, 56-ball BGA  
Package Type  
ZJ = Very Thin Fine-Pitch Ball Grid Array (VFBGA)—-1.2 mm max height with  
0.5 mm pitch; Lead (Pb)-free Package (LF35)  
ZH = Very Thin Fine-Pitch Ball Grid Array (VFBGA) - 1.2 mm max height with  
0.5 mm pitch; Low-Halogen, Lead (Pb)-free Package  
Chip Contents  
0
= No content (default)  
pSRAM Density  
C
B
= 64 Mb  
= 32 Mb  
Process Technology  
= 90 nm MirrorBit Technology  
P
Flash Density  
256 = 256 Mb  
128 = 128 Mb  
Product Family  
S71NS=Multi-Chip Product 1.8 Volt-only Simultaneous Read/Write Burst Mode  
Multiplexed Flash Memory + pSRAM  
1.1  
Valid Combinations  
Valid Combinations  
Code Flash  
Density (Mb)  
Process  
Technology  
pSRAM Density  
(Mb)  
Package Type/  
Material  
Product Family  
Model Number  
Packing Type  
128  
256  
TV, JR, TW, TS  
(Note 4)  
0, 2, 3  
S71NS  
P
B0, C0  
ZJE, ZHE  
(Note 1)  
Notes:  
1. Packing Type 0 is standard. Specify other options as required.  
2. BGA package marking omits leading “S” and packing type designator from ordering part number.  
3. Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to availability of  
specific valid combinations and to check on newly released combinations.  
4. Model Numbers TW and TS indicate products intended for use with MediaTek chipsets. Model numbers TV and JR are not intended for  
use with MediaTek chipsets.  
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S71NS-P Memory Subsystem Solutions  
S71NS-P_00_07 March 30, 2010  
D a t a S h e e t ( P r e l i m i n a r y )  
1.2  
Product Selector Guide  
Device OPN  
Flash Density  
pSRAM Density  
MCP Speed (MHz)  
pSRAM Supplier  
Package  
S71NS128PB0ZJETV  
S71NS128PB0ZHETW  
S71NS128PB0ZJEJR  
S71NS128PB0ZHETS  
S71NS128PC0ZHETV  
S71NS128PC0ZJETV  
S71NS128PC0ZHETW  
S71NS128PC0ZJEJR  
S71NS128PC0ZHETS  
S71NS256PB0ZJETV  
S71NS256PB0ZHETW  
S71NS256PB0ZJEJR  
S71NS256PB0ZHETS  
S71NS256PC0ZHETV  
S71NS256PC0ZHETW  
S71NS256PC0ZJETV  
S71NS256PC0ZJEJR  
S71NS256PC0ZHETS  
66  
32 Mb  
83  
66  
128 Mb  
64 Mb  
32 Mb  
64 Mb  
83  
66  
83  
9.2 x 8.0 mm,  
56-ball MCP  
Type 3  
256 Mb  
66  
83  
2. Input/Output Descriptions  
Table 2.1 identifies the input and output package connections provided on the device.  
Table 2.1 Input/Output Descriptions (Sheet 1 of 2)  
Symbol  
Description  
Flash  
RAM  
X
AMAX – A16  
Address inputs  
X
X
X
X
X
X
A/DQ15-A/DQ0 Multiplexed Address/Data  
X
OE#  
WE#  
Output Enable input. Asynchronous relative to CLK for the Burst mode.  
X
Write Enable input.  
X
V
Ground  
X
SS  
NC  
No Connect; not connected internally  
X
Ready output; indicates the status of the Burst read.  
Flash Memory RDY (using default “Active HIGH” configuration)  
V
V
= data invalid  
= data valid  
OL  
OH  
Note: The default polarity for the pSRAM WAIT signal is opposite the default polarity of the  
Flash RDY signal.  
F-RDY/R-WAIT  
X
X
pSRAM WAIT (using default “Active HIGH” configuration)  
V
V
= data valid  
OL  
= data invalid  
OH  
To match polarities, change bit 10 of the pSRAM Bus Configuration Register to 0 (Active  
LOW WAIT). Alternately, change bit 10 of the Flash Configuration Register to 0 (Active LOW  
RDY)  
Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK  
CLK  
X
X
X
increment the internal address counter. Should be at V or V while in asynchronous mode  
IL  
IH  
Address Valid input. Indicates to device that the valid address is present on the address  
inputs.  
AVD#  
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting  
address to be latched.  
X
X
High = device ignores address inputs  
F-RST#  
Hardware reset input. Low = device resets and returns to reading array data  
March 30, 2010 S71NS-P_00_07  
S71NS-P Memory Subsystem Solutions  
5
D a t a S h e e t ( P r e l i m i n a r y )  
Table 2.1 Input/Output Descriptions (Sheet 2 of 2)  
Symbol  
F-WP#  
Description  
Flash  
RAM  
Hardware write protect input. At V , disables program and erase functions in the four  
outermost sectors. Should be at V for all other conditions.  
IL  
X
IH  
Accelerated input. At V , accelerates programming; automatically places device in unlock  
HH  
F-ACC  
bypass mode. At V , disables all program and erase functions. Should be at V for all other  
X
IL  
IH  
conditions.  
R-CE#  
F-CE#  
R-CRE  
F-VCC  
R-VCC  
R-UB#  
R-LB#  
DNU  
Chip-enable input for pSRAM.  
X
X
Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode.  
Control Register Enable (pSRAM).  
Flash 1.8 Volt-only single power supply.  
pSRAM Power Supply.  
X
X
X
X
X
Upper Byte Control (pSRAM).  
Lower Byte Control (pSRAM)  
Do Not Use  
3. MCP Block Diagram  
Figure 3.1 MCP Block Diagram  
F-RST#  
RST#  
F-ACC  
F-WP#  
F-CE#  
OE#  
ACC  
WP#  
CE#  
RDY  
F-RDY/R-WAIT  
A/DQ15-A/DQ0  
NS  
OE#  
WE#  
AVD#  
CLK  
AD15-AD0  
WE#  
AVD#  
CLK  
Amax-A16  
Amax-A16  
OE#  
WE#  
AVD#  
CLK  
CE#  
CRE  
WAIT  
pSRAM  
R-CE#  
R-CRE  
R-UB#  
R-LB#  
AD15-AD0  
UB#  
LB#  
Amax-A16  
6
S71NS-P Memory Subsystem Solutions  
S71NS-P_00_07 March 30, 2010  
D a t a S h e e t ( P r e l i m i n a r y )  
4. Connection Diagrams/Physical Dimensions  
This section contains the I/O designations and package specifications for the S71NS-P.  
4.1  
Special Handling Instructions for FBGA Packages  
Special handling is required for Flash Memory products in FBGA packages.  
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The  
package and/or data integrity may be compromised if the package body is exposed to temperatures above  
150°C for prolonged periods of time.  
4.2  
Connection Diagrams  
Figure 4.1 56-ball Fine-Pitch Ball Grid Array  
(Top View, Balls Facing Down)  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
Legend  
A
B
C
D
E
F
Flash/pSRAM Shared  
NC  
NC  
No Connect  
Do Not Use  
Flash Only  
NC  
RFU  
A21  
A16  
R-LB# R-UB#  
RFU  
A17  
NC  
F-RDY/  
R-WAIT  
VSS  
A20  
CLK  
VCC  
WE# F-ACC  
A19  
A18  
A22  
VCCQ  
VSS  
AVD#  
A23 F-RST# F-WP#  
F-CE# VSSQ  
pSRAM Only  
A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8  
OE#  
G
A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0  
H
J
NC  
RFU  
R-CE# R-CRE  
RFU  
NC  
K
NC  
NC  
Note:  
Addresses are shared between Flash and RAM depending on the density of the pSRAM.  
MCP  
Flash-Only Addresses  
A22-A21  
Shared Addresses  
A20-A16  
Shared ADQ Pins  
S71NS128PB0  
S71NS128PC0  
S71NS256PB0  
S71NS256PC0  
A22  
A21-A16  
A/DQ15-A/DQ0  
A23-A21  
A20-A16  
A23-A22  
A21-A16  
March 30, 2010 S71NS-P_00_07  
S71NS-P Memory Subsystem Solutions  
7
D a t a S h e e t ( P r e l i m i n a r y )  
Figure 4.2 Look Ahead Diagram 112-ball x16 MUX NOR Flash + x16 MUX pSRAM on Shared Bus + x16  
NAND-based ORNAND on separate bus  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
NC  
NC  
Legend  
A
B
C
D
E
F
NC  
NC  
NOR Flash/pSRAM  
Shared Only  
No Connect  
Do Not Use  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
DNU  
DNU  
N-IO7 N-IO15  
NOR Flash 1 Only  
pSRAM Only  
DNU N-RDY N2-CE# F2-CE#  
R-LB# R-UB#  
N-IO5 N-IO13 N-IO6 N-IO14  
N1-CE# N-RE# F-RDY/  
R-WAIT  
A21  
A16  
VSS  
A20  
CLK  
VCC  
WE# F-ACC  
A19  
A17  
A22  
N-IO4 N-IO12  
G
ORNAND Flash Only  
NOR Flash 2 Only  
N-VCC N-VCC VCCQ  
AVD#  
A23 F-RST# F-WP#  
A18 F1-CE# VSSQ N-IO11 N-PRE  
H
J
N-VSS N-VSS  
VSS  
A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8  
OE#  
VCC  
VSS  
NOR Flash Shared Only  
N-CLE N-ALE A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 N-IO18 N-IO3  
K
L
DNU N-WE# N-WP#  
A24  
R-CE# R-CRE  
VSS  
N-IO1 N-IO9 N-IO2  
NC  
NC  
NC  
NC  
DNU  
NC  
DNU  
N-IO0 N-IO8  
NC  
NC  
NC  
NC  
NC  
M
N
NC  
NC  
NC  
NC  
P
8
S71NS-P Memory Subsystem Solutions  
S71NS-P_00_07 March 30, 2010  
D a t a S h e e t ( P r e l i m i n a r y )  
4.3  
Physical Dimensions  
Figure 4.3 NLB056—56-ball VFBGA 9.2 x 8.0 mm  
D1  
A
D
eD  
0.10  
(2X)  
C
14  
13  
12  
11  
10  
9
SE  
7
8
7
6
5
4
3
E
B
E1  
eE  
2
1
K
J H G F E D C B A  
INDEX MARK  
9
PIN A1  
CORNER  
PIN A1  
CORNER  
7
SD  
0.10  
(2X)  
C
TOP VIEW  
BOTTOM VIEW  
0.20  
C
A2  
A
A1  
0.08  
C
C
SIDE VIEW  
6
56X  
b
0.15  
0.08  
M
M
C
C
A
B
NOTES:  
1. DIMENSIONING AND TOLERANCING METHODS PER  
ASME Y14.5M-1994.  
PACKAGE  
JEDEC  
NLB 056  
N/A  
2. ALL DIMENSIONS ARE IN MILLIMETERS.  
D x E  
9.20 mm x 8.00 mm  
PACKAGE  
3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,  
SPP-010.  
SYMBOL  
MIN  
NOM  
---  
MAX  
NOTE  
4.  
e REPRESENTS THE SOLDER BALL GRID PITCH.  
A
A1  
---  
1.20  
---  
PROFILE  
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"  
DIRECTION.  
0.20  
0.85  
---  
BALL HEIGHT  
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE  
"E" DIRECTION.  
A2  
---  
0.97  
BODY THICKNESS  
BODY SIZE  
D
9.20 BSC.  
8.00 BSC.  
4.50 BSC.  
6.50 BSC.  
10  
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS  
FOR MATRIX SIZE MD X ME.  
E
BODY SIZE  
D1  
E1  
MATRIX FOOTPRINT  
MATRIX FOOTPRINT  
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL  
DIAMETER IN A PLANE PARALLEL TO DATUM C.  
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A  
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER  
BALL IN THE OUTER ROW.  
MD  
ME  
n
MATRIX SIZE D DIRECTION  
MATRIX SIZE E DIRECTION  
BALL COUNT  
14  
56  
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE  
OUTER ROW SD OR SE = 0.000.  
Øb  
eE  
0.25  
0.30  
0.35  
BALL DIAMETER  
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE  
OUTER ROW, SD OR SE = e/2  
0.50 BSC.  
0.50 BSC  
BALL PITCH  
eD  
SD / SE  
BALL PITCH  
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED  
BALLS.  
0.25 BSC.  
SOLDER BALL PLACEMENT  
A2 ~ A13,B1 ~ B14  
DEPOPULATED SOLDER BALLS  
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK  
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.  
C1,C2,C5,C6,C9,C10,C13,C14  
D1,D2,D13,D14,E1,E2,E13,E14,F1,F2,F13,F14  
G1,G2,G13,G14,H1,H2,H5,H6,H9,H10,H13,H14  
J1 ~ J14, K2 ~ K13  
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.  
3507\ 16-038.22 \ 7.14.5  
March 30, 2010 S71NS-P_00_07  
S71NS-P Memory Subsystem Solutions  
9
D a t a S h e e t ( P r e l i m i n a r y )  
Figure 4.4 NSB056—56-ball VFBGA 9.2 x 8.0 mm  
PACKAGE  
JEDEC  
NSB  
N/A  
056  
NOTES:  
1. DIMENSIONING AND TOLERANCING METHODS PER ASME  
Y14.5M-1994.  
NOTE  
9.20 mm x 8.00 mm  
PACKAGE  
D X E  
2. ALL DIMENSIONS ARE IN MILLIMETERS.  
3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010  
SYMBOL  
MIN  
NOM  
---  
MAX  
A
A1  
---  
0.20  
0.85  
1.20  
---  
PROFILE  
4.  
e REPRESENTS THE SOLDER BALL GRID PITCH.  
---  
BALL HEIGHT  
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.  
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.  
A2  
---  
0.97  
BODY THICKNESS  
BODY SIZE  
D
9.20 BSC.  
8.00 BSC.  
4.50 BSC.  
6.50 BSC  
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS  
FOR MATRIX SIZE MD X ME.  
E
BODY SIZE  
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER  
IN A PLANE PARALLEL TO DATUM C.  
D1  
E1  
MATRIX FOOTPRINT  
MATRIX FOOTPRINT  
MATRIX SIZE D DIRECTION  
MATRIX SIZE E DIRECTION  
BALL COUNT  
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND  
B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN  
THE OUTER ROW.  
MD  
ME  
n
10  
14  
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE  
OUTER ROW SD OR SE = 0.000.  
56  
0.25  
Ø b  
eE  
0.30  
0.35  
BALL DIAMETER  
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE  
OUTER ROW, SD OR SE = e/2  
0.50 BSC.  
0.50 BSC.  
0.25 BSC.  
BALL PITCH  
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED  
BALLS.  
eD  
SE SD  
BALL PITCH  
SOLDER BALL PLACEMENT  
DEPOPULATED SOLDER BALLS  
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK  
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.  
A2- A13,B1-B14,C1,  
C2,C5,C6,C9,C10,C13,  
C14,  
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.  
D1,D2,D13,D14,E1,E2,  
E13,E14,F1,F2,F13,F14,G1  
,G2,G13,G14,H1,H2,  
H5,H6,H9,H10,H13,H14,  
J1-J14, K2-K13  
NSB056 \ 16.038.22 \ 9.25.7  
10  
S71NS-P Memory Subsystem Solutions  
S71NS-P_00_07 March 30, 2010  
D a t a S h e e t ( P r e l i m i n a r y )  
5. Revision History  
Section  
Description  
Revision 01 (October 12, 2006)  
Initial release  
Revision 02 (December 8, 2006)  
Global  
Added S71NS128PC0  
Revision 03 (September 10, 2007)  
Global  
Added product details including ordering information for S71NS256PB0  
Added mechanical drawing for the NSB056 package  
Revision 04 (September 26, 2007)  
Physical Dimension  
Revision 05 (December 13, 2007)  
Added product information for 83 MHz MCPs, including ordering part numbers and valid  
combinations  
Global  
Revision 06 (May 2, 2008)  
General Description  
Changed 32 M Multiplexed pSRAM Type 3 Publication Identification Number to muxpsram_10  
Added Low-Halogen package option  
Removed height and ball pitch information from Package Modifier description  
Removed Character Position Descriptions table  
Updated Valid Combinations table  
Ordering Information  
Added Product Selector Guide table  
Revision 07 (March 30, 2010)  
Ordering Information  
Added model numbers TW and TS to indicate products intended for MediaTek chipsets.  
March 30, 2010 S71NS-P_00_07  
S71NS-P Memory Subsystem Solutions  
11  
D a t a S h e e t ( P r e l i m i n a r y )  
Colophon  
The products described in this document are designed, developed and manufactured as contemplated for general use, including without  
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as  
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the  
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,  
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for  
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to  
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor  
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design  
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal  
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under  
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,  
the prior authorization by the respective government entity will be required for export of those products.  
Trademarks and Notice  
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under  
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this  
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,  
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any  
damages of any kind arising out of the use of the information in this document.  
Copyright © 2006-2010 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse, ORNAND, EcoRAM™  
and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names  
used are for informational purposes only and may be trademarks of their respective owners.  
12  
S71NS-P Memory Subsystem Solutions  
S71NS-P_00_07 March 30, 2010  

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