S71PL129JA0BAW9B0_技术文档

S71PL129JC0/S71PL129JB0/S71PL129JA0

Stacked Multi-Chip Product (MCP) Flash Memory and

pSRAM 128 Megabit (8M x 16-bit) CMOS 3.0 Volt-only

Simultaneous Operation, Page Mode Flash Memory with

64/32/16 Megabit (4M/2M/1M x 16-bit) Pseudo-Static RAM

ADVANCE

INFORMATION

Distinctive Characteristics

Package

— 8 x 11.6 x 1.2 mm 64 ball FBGA

MCP Features

Power supply voltage of 2.7 to 3.1 volt

Operating Temperature

High performance

— –25°C to +85°C (Wireless)

— –40°C to +85°C (Industrial)

— 65ns (65ns Flash, 70ns pSRAM)

Dual CE# Flash memory

General Description

The S71PL129J series is a product line of stacked Multi-Chip Product (MCP) pack-

ages and consists of:

One S29PL129J Flash memory die

One 16M, 32M, or 64M pSRAM

The products covered by this document are listed in the table below. For details

about their specifications, please refer to the individual constituent datasheets for

further details.

Flash Memory Density

128Mb

64Mb

32Mb

16Mb

S71PL129JC0

S71PL129JB0

S71PL129JA0

pSRAM

Density

Publication Number S71PL129Jxx_00 Revision A Amendment 5 Issue Date December 23, 2004

This document contains information on a product under development at Spansion, LLC. The information is intended to help you evaluate this product. Do not design in

this product without contacting the factory. Spansion reserves the right to change or discontinue work on this proposed product without notice.

A d v a n c e I n f o r m a t i o n

Product Selector Guide

128 Mb Flash Memory

Device-Model#

S71PL129JA0-9P

S71PL129JB0-9Z

S71PL129JB0-9B

S71PL129JB0-9U

S71PL129JC0-9Z

S71PL129JC0-9U

pSRAM density Flash Access time (ns) (p)SRAM Access time (ns) pSRAM type Package

16M pSRAM

32M pSRAM

64M pSRAM

65

70

Type 7

Type 2

Type 6

Type 7

Type 6

TLA064

2

S71PL129JC0/S71PL129JB0/S71PL129JA0

S71PL129Jxx_00_A5_E December 23, 2004

A d v a n c e I n f o r m a t i o n

Write Protect (WP#) ....................................................................................... 36

Persistent Protection Bit Lock ................................................................... 37

S71PL129JC0/S71PL129JB0/S71PL129JA0

Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1

MCP Features ........................................................................................................ 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . 1

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2

128 Mb Flash Memory ..........................................................................................2

MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .7

Input/Output Description . . . . . . . . . . . . . . . . . . . 8

Pin Description ......................................................................................................8

Logic Symbol ...........................................................................................................8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .9

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 11

TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA)

High Voltage Sector Protection ..................................................................... 37

Figure 1. In-System Sector Protection/Sector Unprotection

Algorithms........................................................................ 38

Temporary Sector Unprotect ........................................................................39

Figure 2. Temporary Sector Unprotect Operation ................... 39

Secured Silicon Sector Flash Memory Region ...........................................39

Factory-Locked Area (64 words) ..............................................................40

Customer-Lockable Area (64 words) ......................................................40

Secured Silicon Sector Protection Bits ....................................................40

Figure 3. Secured Silicon Sector Protect Verify ...................... 41

Hardware Data Protection ..............................................................................41

Low VCC Write Inhibit .................................................................................41

Write Pulse “Glitch” Protection ................................................................41

Logical Inhibit ....................................................................................................41

Power-Up Write Inhibit ................................................................................41

8 x 11.6 mm Package ............................................................................................ 11

Common Flash Memory Interface (CFI) . . . . . . 42

Table 8. CFI Query Identification String ................................ 42

Table 9. System Interface String ......................................... 43

Table 10. Device Geometry Definition ................................... 43

Table 11. Primary Vendor-Specific Extended Query ................ 43

S29PL129J for MCP

General Description . . . . . . . . . . . . . . . . . . . . . . . . 14

Simultaneous Read/Write Operation with Zero Latency ...................... 14

Page Mode Features ........................................................................................... 14

Standard Flash Memory Features ................................................................... 14

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 19

Table 1. PL129J Device Bus Operations ................................ 19

Requirements for Reading Array Data ......................................................... 19

Random Read (Non-Page Read) ...............................................................20

Page Mode Read .............................................................................................20

Table 2. Page Select .......................................................... 20

Simultaneous Read/Write Operation .......................................................... 20

Writing Commands/Command Sequences ................................................. 21

Accelerated Program Operation ............................................................... 21

Autoselect Functions ..................................................................................... 21

Standby Mode ........................................................................................................21

Automatic Sleep Mode ..................................................................................... 22

RESET#: Hardware Reset Pin ........................................................................ 22

Output Disable Mode ....................................................................................... 22

Table 3. S29PL129J Sector Architecture ............................... 23

Table 4. Secured Silicon Sector Addresses ............................ 29

Autoselect Mode ................................................................................................ 29

Table 5. Autoselect Codes for PL129J ................................... 30

Table 6. PL129J Boot Sector/Sector Block Addresses for Protection/

Unprotection ..................................................................... 31

Selecting a Sector Protection Mode ..............................................................32

Table 7. Sector Protection Schemes ..................................... 32

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 45

Reading Array Data ...........................................................................................45

Reset Command .................................................................................................45

Autoselect Command Sequence ....................................................................46

Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-

quence ....................................................................................................................46

Word Program Command Sequence ...........................................................46

Unlock Bypass Command Sequence ........................................................47

Figure 4. Program Operation............................................... 48

Chip Erase Command Sequence ...................................................................48

Sector Erase Command Sequence ................................................................49

Figure 5. Erase Operation................................................... 50

Erase Suspend/Erase Resume Commands ..................................................50

Password Program Command ........................................................................51

Password Verify Command ..............................................................................51

Password Protection Mode Locking Bit Program Command ...............51

Persistent Sector Protection Mode Locking Bit Program Command 52

Secured Silicon Sector Protection Bit Program Command ..................52

PPB Lock Bit Set Command ............................................................................52

DYB Write Command ......................................................................................52

Password Unlock Command ..........................................................................52

PPB Program Command .................................................................................. 53

All PPB Erase Command .................................................................................. 53

DYB Write Command ...................................................................................... 53

PPB Lock Bit Set Command ............................................................................ 53

Command .............................................................................................................54

Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 32

Persistent Sector Protection ...........................................................................32

Password Sector Protection ............................................................................32

WP# Hardware Protection .............................................................................32

Selecting a Sector Protection Mode ..............................................................32

Persistent Sector Protection . . . . . . . . . . . . . . . . 33

Persistent Protection Bit (PPB) .......................................................................33

Persistent Protection Bit Lock (PPB Lock) .................................................33

Dynamic Protection Bit (DYB) .......................................................................33

Persistent Sector Protection Mode Locking Bit ........................................35

Password Protection Mode . . . . . . . . . . . . . . . . . 35

Password and Password Mode Locking Bit ................................................36

64-bit Password ...................................................................................................36

Command Definitions Tables .........................................................................54

Table 12. Memory Array Command Definitions ...................... 54

Table 13. Sector Protection Command Definitions .................. 55

Write Operation Status . . . . . . . . . . . . . . . . . . . . 56

DQ7: Data# Polling ............................................................................................56

Figure 6. Data# Polling Algorithm........................................ 58

RY/BY#: Ready/Busy# ....................................................................................... 58

DQ6: Toggle Bit I ...............................................................................................58

Figure 7. Toggle Bit Algorithm............................................. 59

DQ2: Toggle Bit II ..............................................................................................60

Reading Toggle Bits DQ6/DQ2 .....................................................................60

DQ5: Exceeded Timing Limits ........................................................................60

DQ3: Sector Erase Timer .................................................................................61

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A d v a n c e I n f o r m a t i o n

Table 14. Write Operation Status ......................................... 61

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .62

Figure 8. Maximum Overshoot Waveforms............................. 62

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .63

Industrial (I) Devices ..........................................................................................63

Extended (E) Devices .........................................................................................63

Supply Voltages ....................................................................................................63

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 15. CMOS Compatible ................................................ 64

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .65

Test Conditions ...................................................................................................65

Figure 9. Test Setups......................................................... 65

Table 16. Test Specifications ............................................... 65

Switching Waveforms ........................................................................................65

Table 17. Key to Switching Waveforms ................................. 65

Figure 10. Input Waveforms and Measurement Levels............. 66

VCC RampRate .................................................................................................. 66

Read Operations ................................................................................................ 66

Table 18. Read-Only Operations .......................................... 66

Figure 11. Read Operation Timings....................................... 67

Figure 12. Page Read Operation Timings ............................... 67

Reset ......................................................................................................................68

Table 19. Hardware Reset (RESET#) .................................... 68

Figure 13. Reset Timings..................................................... 68

Erase/Program Operations ............................................................................. 69

Table 20. Erase and Program Operations .............................. 69

Timing Diagrams ................................................................................................. 70

Figure 14. Program Operation Timings.................................. 70

Figure 15. Accelerated Program Timing Diagram .................... 70

Figure 16. Chip/Sector Erase Operation Timings..................... 71

Figure 17. Back-to-back Read/Write Cycle Timings ................. 72

Figure 18. Data# Polling Timings

Write Timings ......................................................................................................85

Figure 26. Write Cycle #1 (WE# Controlled) (See Note 8)....... 85

Figure 27. Write Cycle #2 (CE# Controlled) (See Note 8) ....... 86

Deep Power-down Timing ..............................................................................86

Figure 28. Deep Power Down Timing.................................... 86

Power-on Timing ................................................................................................86

Figure 29. Power-on Timing ................................................ 86

Provisions of Address Skew ............................................................................87

Read ....................................................................................................................87

Figure 30. Read................................................................. 87

Write ..................................................................................................................87

Figure 31. Write ................................................................ 87

pSRAM Type 1

Functional Description . . . . . . . . . . . . . . . . . . . . . 88

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 88

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .89

Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 94

Output Load Circuit ..........................................................................................95

Figure 32. Output Load Circuit............................................. 95

Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 95

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .96

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 107

Read Cycle ...........................................................................................................107

Figure 33. Timing of Read Cycle

(CE# = OE# = V , WE# = ZZ# = V ).............................. 107

IL

IH

Figure 34. Timing Waveform of Read Cycle

(WE# = ZZ# = V )......................................................... 108

IH

Figure 35. Timing Waveform of Page Mode Read Cycle

(WE# = ZZ# = V )......................................................... 109

IH

Write Cycle ..........................................................................................................110

Figure 36. Timing Waveform of Write Cycle

(During Embedded Algorithms)............................................ 72

Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 73

Figure 20. DQ2 vs. DQ6...................................................... 73

(WE# Control, ZZ# = V )................................................ 110

IH

Figure 37. Timing Waveform of Write Cycle

(CE# Control, ZZ# = V )................................................. 110

Figure 38. Timing Waveform of Page Mode Write Cycle

Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 21. Temporary Sector Unprotect ................................. 74

Figure 21. Temporary Sector Unprotect Timing Diagram.......... 74

Figure 22. Sector/Sector Block Protect and Unprotect Timing

Diagram............................................................................ 75

Controlled Erase Operations ..........................................................................76

Table 22. Alternate CE# Controlled Erase and

IH

(ZZ# = V ) ................................................................... 111

IH

Partial Array Self Refresh (PAR) .....................................................................111

Temperature Compensated Refresh (for 64Mb) .....................................112

Deep Sleep Mode ...............................................................................................112

Reduced Memory Size (for 32M and 16M) ..................................................112

Program Operations ........................................................... 76

Table 23. Alternate CE# Controlled Write (Erase/Program)

Other Mode Register Settings (for 64M) ....................................................112

Figure 39. Mode Register.................................................. 113

Figure 40. Mode Register Update Timings (UB#, LB#, OE# are

Don’t Care)..................................................................... 113

Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M)... 114

Figure 42. Deep Sleep Mode - Entry/Exit Timings

Operation Timings ............................................................. 77

Table 24. CE1#/CE2# Timing ............................................. 77

Figure 23. Timing Diagram for Alternating Between CE1# and CE2#

Control ............................................................................. 78

Table 25. Erase And Programming Performance .................... 78

(for 32M and 16M)........................................................... 114

BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 78

Type 2 pSRAM

pSRAM Type 6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Product Information . . . . . . . . . . . . . . . . . . . . . . 118

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 119

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 119

Power Up ..............................................................................................................119

Figure 43. Power Up 1 (CS1# Controlled) ........................... 119

Figure 44. Power Up 2 (CS2 Controlled).............................. 119

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Functional Description . . . . . . . . . . . . . . . . . . . . . 80

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 80

AC Characteristics and Operating Conditions . 81

AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . 82

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .83

Functional Description . . . . . . . . . . . . . . . . . . . . 120

Absolute Maximum Ratings . . . . . . . . . . . . . . . 120

DC Recommended Operating Conditions . . . . 120

Read Timings ........................................................................................................83

Figure 24. Read Cycle......................................................... 83

Figure 25. Page Read Cycle (8 Words Access)........................ 84

4

S71PL129Jxx_00_A5 December 23, 2004

A d v a n c e I n f o r m a t i o n

Power Down Parameters ...............................................................................137

Other Timing Parameters ...............................................................................137

AC Test Conditions .........................................................................................138

AC Measurement Output Load Circuits ...................................................138

Figure 53. AC Output Load Circuit – 16 Mb.......................... 138

Figure 54. AC Output Load Circuit – 32 Mb and 64 Mb.......... 138

DC and Operating Characteristics . . . . . . . . . . . 121

Common ...............................................................................................................121

16M pSRAM .........................................................................................................122

32M pSRAM ........................................................................................................122

64M pSRAM ........................................................................................................ 123

128M pSRAM ....................................................................................................... 123

AC Operating Conditions . . . . . . . . . . . . . . . . . 124

Test Conditions (Test Load and Test Input/Output Reference) .......124

Figure 45. Output Load ..................................................... 124

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 126

Read Timings ......................................................................................................126

Figure 46. Timing Waveform of Read Cycle(1)...................... 126

Figure 47. Timing Waveform of Read Cycle(2)...................... 126

Figure 48. Timing Waveform of Page Cycle (Page Mode Only) 127

Write Timings .................................................................................................... 127

Figure 49. Write Cycle #1 (WE# Controlled) ........................ 127

Figure 50. Write Cycle #2 (CS1# Controlled)....................... 128

Figure 51. Timing Waveform of Write Cycle(3)

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 139

Read Timings .......................................................................................................139

Figure 55. Read Timing #1 (Basic Timing) .......................... 139

Figure 56. Read Timing #2 (OE# Address Access................. 139

Figure 57. Read Timing #3 (LB#/UB# Byte Access) ............. 140

Figure 58. Read Timing #4 (Page Address Access after CE1#

Control Access for 32M and 64M Only) ............................... 140

Figure 59. Read Timing #5 (Random and Page Address Access for

32M and 64M Only) ......................................................... 141

Write Timings ......................................................................................................141

Figure 60. Write Timing #1 (Basic Timing).......................... 141

Figure 61. Write Timing #2 (WE# Control).......................... 142

Figure 62. Write Timing #3-1

(WE#/LB#/UB# Byte Write Control) .................................. 142

Figure 63. Write Timing #3-3

(WE#/LB#/UB# Byte Write Control) .................................. 143

Figure 64. Write Timing #3-4

(WE#/LB#/UB# Byte Write Control) .................................. 143

Read/Write Timings ..........................................................................................144

Figure 65. Read/Write Timing #1-1 (CE1# Control) ............. 144

Figure 66. Read / Write Timing #1-2

(CE1#/WE#/OE# Control)................................................ 144

Figure 67. Read / Write Timing #2 (OE#, WE# Control) ....... 145

Figure 68. Read / Write Timing #3

(CS2 Controlled) .............................................................. 128

Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB#

Controlled)...................................................................... 129

pSRAM Type 7

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Functional Description . . . . . . . . . . . . . . . . . . . . . 131

Power Down (for 32M, 64M Only) . . . . . . . . . . . . 131

Power Down ....................................................................................................... 131

Power Down Program Sequence ................................................................. 132

Address Key ....................................................................................................... 132

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 133

Package Capacitance . . . . . . . . . . . . . . . . . . . . . . 133

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 134

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 135

Read Operation ..................................................................................................135

Write Operation ............................................................................................... 136

(OE#, WE#, LB#, UB# Control) ........................................ 145

Figure 69. Power-up Timing #1 ......................................... 146

Figure 70. Power-up Timing #2 ......................................... 146

Figure 71. Power Down Entry and Exit Timing ..................... 146

Figure 72. Standby Entry Timing after Read or Write............ 147

Figure 73. Power Down Program Timing (for 32M/64M Only). 147

Revision Summary

December 23, 2004 S71PL129Jxx_00_A5

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A d v a n c e I n f o r m a t i o n

MCP Block Diagram

V_CC

f

VV_CCCC

CE1#f

CE2#f

WP#/ACC

RESET#

Flash-only Address

Flash 1

Shared Address

OE#

WE#

V_SS

RY/BY#

DQ₁₅to DQ₀

V_CCS

V_CC

pSRAM

IO₁₅-IO₀

CE#s

UB#s

CE#

UB#

LB#

LB#s

CE2#ps

CEM1#ps

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S71PL129Jxx_00_A5 December 23, 2004

A d v a n c e I n f o r m a t i o n

Connection Diagram

64-ball Fine-Pitch Ball Grid Array

(Top View, Balls Facing Down)

A1

A10

NC

B5

RFU

B6

RFU

C6

Legend

C3

A7

C4

LB#

D4

C5

C7

A8

C8

A11

D8

WP/ACC

D5

WE#

D6

D2

A3

D9

A15

E9

D3

D7

Shared

(Note 1)

A6

UB#

E4

RST#f

E5

CE2s

E6

A19

E7

A12

E8

E2

A2

E3

A5

A18

F4

RY/BY#

A20

A9

A13

F8

A21

F9

Flash only

RAM only

F2

F3

F7

A1

A4

A17

G4

A10

G7

A14

G8

CE2#

G9

G2

G3

VSS

H3

A0

DQ1

H4

DQ6

H7

RFU

H8

A16

H9

H2

H5

DQ3

J5

H6

DQ4

J6

Reserved for

Future Use

CE1#f

J2

OE#

J3

DQ9

J4

DQ13

J7

DQ15

J8

RFU

J9

CE1#s

DQ0

K3

DQ10

K4

VCCf

K5

VCCs

K6

DQ12

K7

DQ7

K8

VSS

DQ8

DQ2

DQ11

RFU

DQ5

DQ14

L5

L6

RFU

M1

NC

M10

NC

Note: May be shared depending on density:

— A21 is shared for the 64M pSRAM configuration.

— A20 is shred for the 32M pSRAM configuration.

— A19 is shared for the 16M pSRAM configuration.

MCP

S71PL129JC0

Flash-only Addresses

Shared Addresses

A21-A0

A22

S71PL129JB0

S71PL129JA0

A22-A21

A22-A20

A20-A0

A19-A0

Note: It is advised to tie J5 and L5 together on the board.

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A d v a n c e I n f o r m a t i o n

Input/Output Description

Pin Description

A21–A0

DQ15–DQ0

CE1#f

CE2#f

CE1#ps

CE2ps

OE#

WE#

RY/BY#

UB#

LB#

=

22 Address Inputs (Common)

16 Data Inputs/Outputs (Common)

Chip Enable 1 (Flash)

Chip Enable 2 (Flash)

Chip Enable 1 (pSRAM)

Chip Enable 2 (pSRAM)

Output Enable (Common)

Write Enable (Common)

Ready/Busy Output

Upper Byte Control (pSRAM)

Lower Byte Control (pSRAM)

Hardware Reset Pin, Active Low (Flash 1)

Hardware Write Protect/Acceleration Pin (Flash)

Flash 3.0 volt-only single power supply (see Product

Selector Guide for speed options and voltage supply

tolerances)

RESET#

WP#/ACC

V_CC

f

V_CCps

V_SS

NC

=

pSRAM Power Supply

Device Ground (Common)

Pin Not Connected Internally

Logic Symbol

22

A21–A0

16

CE1#f

DQ15–DQ0

R Y/BY#

CE2#f

CE1#ps

CE2ps

OE#

WE#

WP#/ACC

RESET#

UB#

LB#

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A d v a n c e I n f o r m a t i o n

Ordering Information

The order number is formed by a valid combinations of the following:

S71PL

129

J

B0 BA

W

9

Z

0

PACKING TYPE

0

2

3

=

Tray

7” Tape and Reel

13” Tape and Reel

MODEL NUMBER

See valid combinations table.

PACKAGE MODIFIER

9

=

8 x 11.6 mm, 1.2 mm height, 64 balls (TLA064)

TEMPERATURE RANGE

W

I

=

Wireless (-25

Industrial (-40

°

C to +85

°

C)

°C to +85

°C)

PACKAGE TYPE

BA

BF

=

Fine-pitch BGA Lead (Pb)-free compliant package

Fine-pitch BGA Lead (Pb)-free package

pSRAM DENSITY

C0

B0

A0

=

64 Mb pSRAM

32 Mb pSRAM

16 Mb pSRAM

PROCESS TECHNOLOGY

110 nm, Floating Gate Technology

J

=

FLASH DENSITY

129 128Mb, dual CE#

=

PRODUCT FAMILY

S71PL Multi-chip Product (MCP)

3.0-volt Simultaneous Read/Write, Page Mode Flash Memory and RAM

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A d v a n c e I n f o r m a t i o n

S71PL129J Valid Combinations

(p)SRAM

Type/Access

Time (ns)

Base Ordering

Part Number

Package &

Package Modifier/

Model Number

Speed Options

(ns)

Package

Marking

Temperature

Packing Type

S71PL129JA0

S71PL129JB0

S71PL129JC0

S71PL129JA0

S71PL129JB0

S71PL129JC0

S71PL129JA0

S71PL129JB0

S71PL129JC0

S71PL129JA0

S71PL129JB0

S71PL129JC0

9P

9Z

9B

9U

9Z

9U

9P

9Z

9B

9U

9Z

9U

9P

9Z

9B

9U

9Z

9U

9P

9Z

9B

9U

9Z

9U

pSRAM 7 / 70

pSRAM 2 / 70

pSRAM 6 / 70

pSRAM 7 / 70

pSRAM 6 / 70

pSRAM 7 / 70

pSRAM 2 / 70

pSRAM 6 / 70

pSRAM 7 / 70

pSRAM 6 / 70

pSRAM 7 / 70

pSRAM 2 / 70

pSRAM 6 / 70

pSRAM 7 / 70

pSRAM 6 / 70

pSRAM 7 / 70

pSRAM 2 / 70

pSRAM 6 / 70

pSRAM 7 / 70

pSRAM 6 / 70

BAW

BFW

BAI

0, 2, 3 (Note 1)

65

0, 2, 3 (Note 1)

(Note 2)

BFI

Notes:

Valid Combinations

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading “S” and packing type

designator from ordering part number.

3. Contact factory for availability of any of the above OPNs. RAM

type availability may vary over time.

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult your local sales office to confirm avail-

ability of specific valid combinations and to check on newly released

combinations.

10

S71PL129Jxx_00_A5 December 23, 2004

A d v a n c e I n f o r m a t i o n

Physical Dimensions

TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA)

8 x 11.6 mm Package

A

D1

D

eD

0.15

(2X)

C

10

9

8

SE

7

6

E

B

E1

5

4

eE

3

2

1

L

J

H

G

F

E

D

C

B

A

M

K

INDEX MARK

10

PIN A1

CORNER

PIN A1

CORNER

7

SD

0.15

(2X)

C

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.20

0.08

C

A2

A

C

A1

6

64X

b

0.15

0.08

M

C

A B

M

NOTES:

PACKAGE

JEDEC

TLA 064

N/A

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

D x E

11.60 mm x 8.00 mm

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

SYMBOL

MIN

---

NOM

---

MAX

1.20

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

PROFILE

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

0.17

0.81

---

BALL HEIGHT

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

A2

---

0.97

BODY THICKNESS

BODY SIZE

D

11.60 BSC.

8.00 BSC.

8.80 BSC.

7.20 BSC.

12

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

E

BODY SIZE

D1

E1

MATRIX FOOTPRINT

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

MD

ME

n

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

10

64

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

φb

0.35

0.40

0.45

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

eE

0.80 BSC.

0.80 BSC

0.40 BSC.

BALL PITCH

eD

SD / SE

BALL PITCH

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

A2,A3,A4,A5,A6,A7,A8,A9

B1,B2,B3,B4,B7,B8,B9,B10

C1,C2,C9,C10,D1,D10,E1,E10,

F1,F5,F6,F10,G1,G5,G6,G10

H1,H10,J1,J10,K1,K2,K9,K10

L1,L2,L3,L4,L7,L8,L9,L10

9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

M2,M3,M4,M5,M6,M7,M8,M9

3352 \ 16-038.22a

December 23, 2004 S71PL129Jxx_00_A5

11

S29PL129J for MCP

128 Megabit (8 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Read/Write

Flash Memory with Enhanced VersatileIO^TMControl

ADVANCE

INFORMATION

Datasheet

Distinctive Characteristics

Architectural Advantages

Performance Characteristics

128 Mbit Page Mode devices

High Performance

— Page size of 8 words: Fast page read access from

random locations within the page

— Page access times as fast as 20 ns

— Random access times as fast as 55 ns

Single power supply operation

— Full Voltage range: 2.7 to 3.6 volt read, erase, and

program operations for battery-powered applications

Power consumption (typical values at 10 MHz)

— 45 mA active read current

— 17 mA program/erase current

— 0.2 µA typical standby mode current

Dual Chip Enable inputs (only in PL129J)

— Two CE# inputs control selection of each half of the

memory space

Software Features

Simultaneous Read/Write Operation

Software command-set compatible with JEDEC

42.4 standard

— Backward compatible with Am29F, Am29LV,

Am29DL, and AM29PDL families and MBM29QM/RM,

MBM29LV, MBM29DL, MBM29PDL families

— Data can be continuously read from one bank while

executing erase/program functions in another bank

— Zero latency switching from write to read operations

FlexBank Architecture

— 4 separate banks, with up to two simultaneous

operations per device

— CE#1 controlled banks:

Bank 1A:

CFI (Common Flash Interface) compliant

— Provides device-specific information to the system,

allowing host software to easily reconfigure for

different Flash devices

- 16Mbit (4Kw x 8 and 32Kw x 31)

Bank 1B:

- 48Mbit (32Kw x 96)

Erase Suspend / Erase Resume

— Suspends an erase operation to allow read or

program operations in other sectors of same bank

— CE#2 controlled banks:

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

Bank 2A:

- 48 Mbit (32Kw x 96)

Bank 2B:

- 16Mbit (4Kw x 8 and 32Kw x 31)

Enhanced VersatileI/O^TM(V_IO) Control

— Output voltage generated and input voltages

tolerated on all control inputs and I/Os is determined

by the voltage on the V_IOpin

Hardware Features

Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting program or

erase cycle completion

Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

Secured Silicon Sector region

— Up to 128 words accessible through a command

sequence

WP#/ ACC (Write Protect/Acceleration) input

— At V_IL, hardware level protection for the first and

last two 4K word sectors.

— Up to 64 factory-locked words

— Up to 64 customer-lockable words

Both top and bottom boot blocks in one device

Manufactured on 110 nm process technology

Data Retention: 20 years typical

— At V_IH, allows removal of sector protection

— At V_HH, provides accelerated programming in a

factory setting

Persistent Sector Protection

— A command sector protection method to lock

combinations of individual sectors and sector groups

Cycling Endurance: 1 million cycles per sector

typical

Publication Number S29PL129J_MCP_00 Revision A Amendment 0 Issue Date June 4, 2004

A d v a n c e I n f o r m a t i o n

to prevent program or erase operations within that

Password Sector Protection

sector

— A sophisticated sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector using a user-defined 64-bit password

— Sectors can be locked and unlocked in-system at V_CC

level

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

13

A d v a n c e I n f o r m a t i o n

General Description

The PL129J is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write

Flash memory device organized as 8 Mwords.

The word-wide data (x16) appears on DQ15-DQ0. This device can be pro-

grammed in-system or in standard EPROM programmers. A 12.0 V V_PPis not

required for write or erase operations.

The device offers fast page access times of 20 to 30 ns, with corresponding ran-

dom access times of 55 to 70 ns, respectively, allowing high speed

microprocessors to operate without wait states. To eliminate bus contention the

device has separate chip enable (CE#), write enable (WE#) and output enable

(OE#) controls. Note: Device PL129J has 2 chip enable inputs (CE1#, CE2#).

Simultaneous Read/Write Operation with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation

by dividing the memory space into 4 banks, which can be considered to be four

separate memory arrays as far as certain operations are concerned. The device

can improve overall system performance by allowing a host system to program

or erase in one bank, then immediately and simultaneously read from another

bank with zero latency (with two simultaneous operations operating at any one

time). This releases the system from waiting for the completion of a program or

erase operation, greatly improving system performance.

The device can be organized in both top and bottom sector configurations. The

banks are organized as follows:

Bank

1A

PL129J Sectors

CE# Control

CE1#

16 Mbit (4 Kw x 8 and 32 Kw x 31)

48 Mbit (32 Kw x 96)

1B

CE1#

2A

48 Mbit (32 Kw x 96)

CE2#

2B

16 Mbit (4 Kw x 8 and 32 Kw x 31)

CE2#

Page Mode Features

The page size is 8 words. After initial page access is accomplished, the page mode

operation provides fast read access speed of random locations within that page.

Standard Flash Memory Features

The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both

read and write functions. Internally generated and regulated voltages are pro-

vided for the program and erase operations.

The device is entirely command set compatible with the JEDEC 42.4 single-

power-supply Flash standard. Commands are written to the command regis-

ter using standard microprocessor write timing. Register contents serve as inputs

to an internal state-machine that controls the erase and programming circuitry.

Write cycles also internally latch addresses and data needed for the programming

and erase operations. Reading data out of the device is similar to reading from

other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. The

Unlock Bypass mode facilitates faster programming times by requiring only two

14

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

write cycles to program data instead of four. Device erasure occurs by executing

the erase command sequence.

The host system can detect whether a program or erase operation is complete by

reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program

or erase cycle has been completed, the device is ready to read array data or ac-

cept another command.

The sector erase architecture allows memory sectors to be erased and repro-

grammed without affecting the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low V_CCdetector that automat-

ically inhibits write operations during power transitions. The hardware sector

protection feature disables both program and erase operations in any combina-

tion of sectors of memory. This can be achieved in-system or via programming

equipment.

The Erase Suspend/Erase Resume feature enables the user to put erase on

hold for any period of time to read data from, or program data to, any sector that

is not selected for erasure. True background erase can thus be achieved. If a read

is needed from the Secured Silicon Sector area (One Time Program area) after

an erase suspend, then the user must use the proper command sequence to

enter and exit this region.

The device offers two power-saving features. When addresses have been stable

for a specified amount of time, the device enters the automatic sleep mode.

The system can also place the device into the standby mode. Power consumption

is greatly reduced in both these modes.

The device electrically erases all bits within a sector simultaneously via Fowler-

Nordheim tunneling. The data is programmed using hot electron injection.

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

15

A d v a n c e I n f o r m a t i o n

Block Diagram

DQ15–DQ0

RY/BY# (See Note)

V

CC

V

SS

Sector

Switches

V

IO

Input/Output

Buffers

RESET#

WE#

Erase Voltage

Generator

State

Control

Command

Register

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

CE#

OE#

Data Latch

Y-Gating

Y-Decoder

X-Decoder

V

CC

Detector

Timer

Amax–A3

Cell Matrix

A2–A0

Notes:

1. RY/BY# is an open drain output.

2. For PL129J there are two CE# (CE1# and CE2#)

16

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

Simultaneous Read/Write Block Diagram (PL129J)

V

CC

OE#

SS

CE1#=L

CE2#=H

Mux

Bank 1A

Bank 1A Address

Bank 1B Address

A21–A0

X-Decoder

RY/BY#

Bank 1B

X-Decoder

A21–A0

RESET#

STATE

CONTROL

&

Status

WE#

CE1#

DQ15–DQ0

CE2#

COMMAND

REGISTER

Control

Mux

WP#/ACC

CE1#=H

CE2#=L

X-Decoder

Bank 2A

DQ0–DQ15

Bank 2A Address

Bank 2B Address

X-Decoder

Bank 2B

A21–A0

Mux

Notes:

1. Amax = A21 (PL129J)

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

17

A d v a n c e I n f o r m a t i o n

Pin Description

Amax–A0

DQ15–DQ0

CE#

OE#

WE#

V_SS

NC

RY/BY#

=

Address bus

16-bit data inputs/outputs/float

Chip Enable Inputs

Output Enable Input

Write Enable

Device Ground

Pin Not Connected Internally

Ready/Busy output and open drain.

When RY/BY#= V_IH, the device is ready to accept

read operations and commands. When RY/BY#=

V_OL, the device is either executing an embedded

algorithm or the device is executing a hardware

reset operation.

WP#/ACC

=

Write Protect/Acceleration Input.

When WP#/ACC= V_IL, the highest and lowest two

4K-word sectors are write protected regardless of

other sector protection configurations. When WP#/

ACC= V_IH, these sector are unprotected unless the

DYB or PPB is programmed. When WP#/ACC= 12V,

program and erase operations are accelerated.

V_IO

V_CC

=

Input/Output Buffer Power Supply 2.7 V to 3.6 V

Chip Power Supply

(2.7 V to 3.6 V or 2.7 to 3.3 V)

RESET#

CE1#, CE2#

=

Hardware Reset Pin

Chip Enable Inputs.

CE1# controls the 64Mb in Banks 1A and 1B. CE2#

controls the 64 Mb in Banks 2A and 2B.

Notes:

1. Amax = A21

Logic Symbol

max+1

Amax–A0

16

DQ15–DQ0

CE#

OE#

WE#

WP#/ACC

RESET#

RY/BY#

V_IO(V_CCQ

)

18

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

Device Bus Operations

This section describes the requirements and use of the device bus operations,

which are initiated through the internal command register. The command register

itself does not occupy any addressable memory location. The register is a latch

used to store the commands, along with the address and data information

needed to execute the command. The contents of the register serve as inputs to

the internal state machine. The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the inputs and control levels re-

quired, and the resulting output. The following subsections describe each of these

operations in further detail.

Table 1. PL129J Device Bus Operations

Addresses

(A21–A0)

DQ15–

DQ0

Operation

CE1#

CE2#

OE#

WE#

RESET#

WP#/ACC

L

H

L

H

L

Read

L

H

X

A_IN

D_OUT

H

L

X

Write

H

X

L

H

A_IN

X

D_IN

(Note 2)

H

V_IO

0.3 V

±

V_IO

0.3 V

±

V_IO±

0.3 V

Standby

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z

X

Temporary Sector Unprotect

(High Voltage)

X

V_ID

X

A_IN

D_IN

Legend: L = Logic Low = V , H = Logic High = V , V = 11.5–12.5 V, V = 8.5–9.5 V, X = Don’t Care, SA = Sector

HH

IL

IH

ID

Address, A = Address In, D = Data In, D = Data Out

IN

OUT

Notes:

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See

““High Voltage Sector Protection” on page 37.”

2. WP#/ACC must be high when writing to upper two and lower two sectors.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the OE# and appro-

priate CE# pins to V_IL. In PL129J, CE1# and CE2# are the power control and

select the lower (CE1#) or upper (CE2#) halves of the device. CE# is the power

control. OE# is the output control and gates array data to the output pins. WE#

should remain at V_IH.

The internal state machine is set for reading array data upon device power-up,

or after a hardware reset. This ensures that no spurious alteration of the memory

content occurs during the power transition. No command is necessary in this

mode to obtain array data. Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid data on the device data

outputs. Each bank remains enabled for read access until the command register

contents are altered.

See Table 24 for timing specifications and Figure 11 for the timing diagram. I_CC1

in the DC Characteristics table represents the active current specification for

reading array data.

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

19

A d v a n c e I n f o r m a t i o n

Random Read (Non-Page Read)

Address access time (t_ACC) is equal to the delay from stable addresses to valid

output data. The chip enable access time (t_CE) is the delay from the stable ad-

dresses and stable CE# to valid data at the output inputs. The output enable

access time is the delay from the falling edge of the OE# to valid data at the out-

put inputs (assuming the addresses have been stable for at least t_ACC–t_OEtime).

Page Mode Read

The device is capable of fast page mode read and is compatible with the page

mode Mask ROM read operation. This mode provides faster read access speed for

random locations within a page. Address bits Amax–A3 select an 8 word page,

and address bits A2–A0 select a specific word within that page. This is an asyn-

chronous operation with the microprocessor supplying the specific word location.

The random or initial page access is t_ACCor t_CEand subsequent page read ac-

cesses (as long as the locations specified by the microprocessor falls within that

page) is equivalent to t_PACC. When CE1# and CE#2 are deasserted (=V_IH), the

reassertion of CE1# or CE#2 for subsequent access has access time of t_ACCor

t_CE. Here again, CE1#/CE#2 selects the device and OE# is the output control and

should be used to gate data to the output inputs if the device is selected. Fast

page mode accesses are obtained by keeping Amax–A3 constant and changing

A2–A0 to select the specific word within that page.

Table 2. Page Select

Word

A2

0

A1

0

1

0

1

A0

0

Word 0

Word 1

Word 2

Word 3

Word 4

Word 5

Word 6

Word 7

0

1

0

1

0

1

0

1

Simultaneous Read/Write Operation

In addition to the conventional features (read, program, erase-suspend read, and

erase-suspend program), the device is capable of reading data from one bank of

memory while a program or erase operation is in progress in another bank of

memory (simultaneous operation). The bank can be selected by bank addresses

(A21–A19) with zero latency.

The simultaneous operation can execute multi-function mode in the same bank.

Bank

CE1#

CE2#

PL129J: A21–A20

00

Bank 1A

Bank 1B

0

1

01, 10, 11

20

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

Bank 2A

Bank 2B

1

0

00, 01, 10

11

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data

to the device and erasing sectors of memory), the system must drive WE# and

CE1# or CE#2 to V_IL, and OE# to V_IH.

The device features an Unlock Bypass mode to facilitate faster programming.

Once a bank enters the Unlock Bypass mode, only two write cycles are required

to program a word, instead of four. “Word Program Command Sequence” on page

46 has details on programming data to the device using both standard and Unlock

Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device.

Table 4 indicates the set of address space that each sector occupies. A “bank ad-

dress” is the set of address bits required to uniquely select a bank. Similarly, a

“sector address” refers to the address bits required to uniquely select a sector.

“Command Definitions” on page 45 has details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

I_CC2in the DC Characteristics table represents the active current specification for

the write mode. See the timing specification tables and timing diagrams in “Re-

set” for write operations.

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This

function is primarily intended to allow faster manufacturing throughput at the

factory.

If the system asserts V_HHon this pin, the device automatically enters the afore-

mentioned Unlock Bypass mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the time required for program

operations. The system would use a two-cycle program command sequence as

required by the Unlock Bypass mode. Removing V_HHfrom the WP#/ACC pin re-

turns the device to normal operation. Note that V_HHmust not be asserted on

WP#/ACC for operations other than accelerated programming, or device damage

may result. In addition, the WP#/ACC pin should be raised to V_CCwhen not in

use. That is, the WP#/ACC pin should not be left floating or unconnected; incon-

sistent behavior of the device may result.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the au-

toselect mode. The system can then read autoselect codes from the internal

register (which is separate from the memory array) on DQ15–DQ0. Standard

read cycle timings apply in this mode. See “Secured Silicon Sector Addresses” on

page 29 and “Autoselect Command Sequence” on page 46 for more information.

Standby Mode

When the system is not reading or writing to the device, it can place the device

in the standby mode. In this mode, current consumption is greatly reduced, and

the outputs are placed in the high impedance state, independent of the OE#

input.

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

21

A d v a n c e I n f o r m a t i o n

The device enters the CMOS standby mode when the CE1# or CE#2 and RESET#

pins are both held at V_IO± 0.3 V. (Note that this is a more restricted voltage

range than V_IH.) If CE1# or CE#2 and RESET# are held at V_IH, but not within V_IO

± 0.3 V, the device is in standby mode, but the standby current is greater. The

device requires standard access time (t_CE) for read access when the device is in

either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-

tive current until the operation is completed.

I_CC3in “DC Characteristics” represents the CMOS standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de-

vice automatically enables this mode when addresses remain stable for t_ACC

+

30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-

trol signals. Standard address access timings provide new data when addresses

are changed. While in sleep mode, output data is latched and always available to

the system. Note that during automatic sleep mode, OE# must be at V_IHbefore

the device reduces current to the stated sleep mode specification. I_CC5in “DC

Characteristics” represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading

array data. When the RESET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in progress, tristates all output

pins, and ignores all read/write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to reading array data. The op-

eration that was interrupted should be reinitiated once the device is ready to

accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held

at V_SS±0.3 V, the device draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS±0.3 V, the standby current is greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would

thus also reset the Flash memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin re-

mains a “0” (busy) until the internal reset operation is complete, which requires

a time of t_READY(during Embedded Algorithms). The system can thus monitor RY/

BY# to determine whether the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing (RY/BY# pin is “1”), the reset

operation is completed within a time of t_READY(not during Embedded Algorithms).

The system can read data t_RHafter the RESET# pin returns to V_IH.

Refer to the AC Characteristics tables for RESET# parameters and to Figure 13

for the timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is disabled. The output pins

(except for RY/BY#) are placed in the highest Impedance state

22

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

Table 3. S29PL129J Sector Architecture (Sheet 1 of 7)

Sector Address (A21-

A12)

Sector Size

(Kwords)

Bank

Sector

SA1-0

CE1#

0

CE2#

1

Address Range (x16)

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

0000100XXX

0000101XXX

0000110XXX

0000111XXX

0001000XXX

0001001XXX

0001010XXX

0001011XXX

0001100XXX

0001101XXX

0001110XXX

0001111XXX

0010000XXX

0010001XXX

0010010XXX

0010011XXX

0010100XXX

0010101XXX

0010110XXX

0010111XXX

0011000XXX

0011001XXX

0011010XXX

0011011XXX

0011100XXX

0011101XXX

0011110XXX

0011111XXX

4

SA1-1

4

SA1-2

4

SA1-3

4

SA1-4

4

SA1-5

4

SA1-6

4

SA1-7

4

SA1-8

32

SA1-9

SA1-10

SA1-11

SA1-12

SA1-13

SA1-14

SA1-15

SA1-16

SA1-17

SA1-18

SA1-19

SA1-20

SA1-21

SA1-22

SA1-23

SA1-24

SA1-25

SA1-26

SA1-27

SA1-28

SA1-29

SA1-30

SA1-31

SA1-32

SA1-33

SA1-34

SA1-35

SA1-36

SA1-37

SA1-38

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

23

A d v a n c e I n f o r m a t i o n

Table 3. S29PL129J Sector Architecture (Sheet 2 of 7)

Sector Address (A21-

A12)

Sector Size

Bank

Sector

SA1-39

SA1-40

SA1-41

SA1-42

SA1-43

SA1-44

SA1-45

SA1-46

SA1-47

SA1-48

SA1-49

SA1-50

SA1-51

SA1-52

SA1-53

SA1-54

SA1-55

SA1-56

SA1-57

SA1-58

SA1-59

SA1-60

SA1-61

SA1-62

SA1-63

SA1-64

SA1-65

SA1-66

SA1-67

SA1-68

SA1-69

SA1-70

SA1-71

SA1-72

SA1-73

SA1-74

SA1-75

SA1-76

SA1-77

SA1-78

SA1-79

SA1-80

SA1-81

SA1-82

CE1#

0

CE2#

1

(Kwords)

32

Address Range (x16)

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

0100000XXX

0100001XXX

0100010XXX

0100011XXX

0100100XXX

0100101XXX

0100110XXX

0100111XXX

0101000XXX

0101001XXX

0101010XXX

0101011XXX

0101100XXX

0101101XXX

0101110XXX

0101111XXX

0110000XXX

0110001XXX

0110010XXX

0110011XXX

0110100XXX

0110101XXX

0110110XXX

0110111XXX

0111000XXX

0111001XXX

0111010XXX

0111011XXX

0111100XXX

0111101XXX

0111110XXX

0111111XXX

1000000XXX

1000001XXX

1000010XXX

1000011XXX

1000100XXX

1000101XXX

1000110XXX

1000111XXX

1001000XXX

1001001XXX

1001010XXX

1001011XXX

24

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

Table 3. S29PL129J Sector Architecture (Sheet 3 of 7)

Sector Address (A21-

A12)

Sector Size

Bank

Sector

SA1-83

CE1#

0

CE2#

1

(Kwords)

32

Address Range (x16)

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

1001100XXX

1001101XXX

1001110XXX

1001111XXX

1010000XXX

1010001XXX

1010010XXX

1010011XXX

1010100XXX

1010101XXX

1010110XXX

1010111XXX

1011000XXX

1011001XXX

1011010XXX

1011011XXX

1011100XXX

1011101XXX

1011110XXX

1011111XXX

1100000XXX

1100001XXX

1100010XXX

1100011XXX

1100100XXX

1100101XXX

1100110XXX

1100111XXX

1101000XXX

1101001XXX

1101010XXX

1101011XXX

1101100XXX

1101101XXX

1101110XXX

1101111XXX

1110000XXX

1110001XXX

1110010XXX

1110011XXX

1110100XXX

1110101XXX

1110110XXX

1110111XXX

SA1-84

SA1-85

SA1-86

SA1-87

SA1-88

SA1-89

SA1-90

SA1-91

SA1-92

SA1-93

SA1-94

SA1-95

SA1-96

SA1-97

SA1-98

SA1-99

SA1-100

SA1-101

SA1-102

SA1-103

SA1-104

SA1-105

SA1-106

SA1-107

SA1-108

SA1-109

SA1-110

SA1-111

SA1-112

SA1-113

SA1-114

SA1-115

SA1-116

SA1-117

SA1-118

SA1-119

SA1-120

SA1-121

SA1-122

SA1-123

SA1-124

SA1-125

SA1-126

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

25

A d v a n c e I n f o r m a t i o n

Table 3. S29PL129J Sector Architecture (Sheet 4 of 7)

Sector Address (A21-

A12)

Sector Size

Bank

Sector

SA1-127

SA1-128

SA1-129

SA1-130

SA1-131

SA1-132

SA1-133

SA1-134

SA2-0

CE1#

0

1

CE2#

1

0

(Kwords)

32

Address Range (x16)

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3FFFFFh

000000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

1111000XXX

1111001XXX

1111010XXX

1111011XXX

1111100XXX

1111101XXX

1111110XXX

1111111XXX

0000000XXX

0000001XXX

0000010XXX

0000011XXX

0000100XXX

0000101XXX

0000110XXX

0000111XXX

0001000XXX

0001001XXX

0001010XXX

0001011XXX

0001100XXX

0001101XXX

0001110XXX

0001111XXX

0010000XXX

0010001XXX

0010010XXX

0010011XXX

0010100XXX

0010101XXX

0010110XXX

0010111XXX

0011000XXX

0011001XXX

0011010XXX

0011011XXX

0011100XXX

0011101XXX

0011110XXX

0011111XXX

0100000XXX

0100001XXX

0100010XXX

0100011XXX

SA2-1

SA2-2

SA2-3

SA2-4

SA2-5

SA2-6

SA2-7

SA2-8

SA2-9

SA2-10

SA2-11

SA2-12

SA2-13

SA2-14

SA2-15

SA2-16

SA2-17

SA2-18

SA2-19

SA2-20

SA2-21

SA2-22

SA2-23

SA2-24

SA2-25

SA2-26

SA2-27

SA2-28

SA2-29

SA2-30

SA2-31

SA2-32

SA2-33

SA2-34

SA2-35

26

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

Table 3. S29PL129J Sector Architecture (Sheet 5 of 7)

Sector Address (A21-

A12)

Sector Size

Bank

Sector

SA2-36

SA2-37

SA2-38

SA2-39

SA2-40

SA2-41

SA2-42

SA2-43

SA2-44

SA2-45

SA2-46

SA2-47

SA2-48

SA2-49

SA2-50

SA2-51

SA2-52

SA2-53

SA2-54

SA2-55

SA2-56

SA2-57

SA2-58

SA2-59

SA2-60

SA2-61

SA2-62

SA2-63

SA2-64

SA2-65

SA2-66

SA2-67

SA2-68

SA2-69

SA2-70

SA2-71

SA2-72

SA2-73

SA2-74

SA2-75

SA2-76

SA2-77

SA2-78

SA2-79

CE1#

1

CE2#

0

(Kwords)

32

Address Range (x16)

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

0100100XXX

0100101XXX

0100110XXX

0100111XXX

0101000XXX

0101001XXX

0101010XXX

0101011XXX

0101100XXX

0101101XXX

0101110XXX

0101111XXX

0110000XXX

0110001XXX

0110010XXX

0110011XXX

0110100XXX

0110101XXX

0110110XXX

0110111XXX

0111000XXX

0111001XXX

0111010XXX

0111011XXX

0111100XXX

0111101XXX

0111110XXX

0111111XXX

1000000XXX

1000001XXX

1000010XXX

1000011XXX

1000100XXX

1000101XXX

1000110XXX

1000111XXX

1001000XXX

1001001XXX

1001010XXX

1001011XXX

1001100XXX

1001101XXX

1001110XXX

1001111XXX

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

27

A d v a n c e I n f o r m a t i o n

Table 3. S29PL129J Sector Architecture (Sheet 6 of 7)

Sector Address (A21-

A12)

Sector Size

Bank

Sector

SA2-80

SA2-81

SA2-82

SA2-83

SA2-84

SA2-85

SA2-86

SA2-87

SA2-88

SA2-89

SA2-90

SA2-91

SA2-92

SA2-93

SA2-94

SA2-95

SA2-96

SA2-97

SA2-98

SA2-99

SA2-100

SA2-101

SA2-102

SA2-103

SA2-104

SA2-105

SA2-106

SA2-107

SA2-108

SA2-109

SA2-110

SA2-111

SA2-112

SA2-113

SA2-114

SA2-115

SA2-116

SA2-117

SA2-118

SA2-119

SA2-120

SA2-121

SA2-122

SA2-123

CE1#

1

CE2#

0

(Kwords)

32

Address Range (x16)

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

1010000XXX

1010001XXX

1010010XXX

1010011XXX

1010100XXX

1010101XXX

1010110XXX

1010111XXX

1011000XXX

1011001XXX

1011010XXX

1011011XXX

1011100XXX

1011101XXX

1011110XXX

1011111XXX

1100000XXX

1100001XXX

1100010XXX

1100011XXX

1100100XXX

1100101XXX

1100110XXX

1100111XXX

1101000XXX

1101001XXX

1101010XXX

1101011XXX

1101100XXX

1101101XXX

1101110XXX

1101111XXX

1110000XXX

1110001XXX

1110010XXX

1110011XXX

1110100XXX

1110101XXX

1110110XXX

1110111XXX

1111000XXX

1111001XXX

1111010XXX

1111011XXX

28

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

Table 3. S29PL129J Sector Architecture (Sheet 7 of 7)

Sector Address (A21-

A12)

Sector Size

(Kwords)

Bank

Sector

CE1#

1

CE2#

Address Range (x16)

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3F8FFFh

3F9000h–3F9FFFh

3FA000h–3FAFFFh

3FB000h–3FBFFFh

3FC000h–3FCFFFh

3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

SA2-124

SA2-125

SA2-126

SA2-127

SA2-128

SA2-129

SA2-130

SA2-131

SA2-132

SA2-133

SA2-134

0

1111100XXX

1111101XXX

1111110XXX

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

32

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

Table 4. Secured Silicon Sector Addresses

Sector Size

64 words

Address Range

Factory-Locked Area

000000h-00003Fh

000040h-00007Fh

Customer-Lockable Area

64 words

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector

protection verification, through identifier codes output on DQ7–DQ0. This mode

is primarily intended for programming equipment to automatically match a device

to be programmed with its corresponding programming algorithm. However, the

autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V_IDon ad-

dress pin A9. Address pins must be as shown in Table 5. In addition, when

verifying sector protection, the sector address must appear on the appropriate

highest order address bits. Table 5 shows the remaining address bits that are

don’t care. When all necessary bits have been set as required, the programming

equipment may then read the corresponding identifier code on DQ7–DQ0. How-

ever, the autoselect codes can also be accessed in-system through the command

register, for instances when the device is erased or programmed in a system with-

out access to high voltage on the A9 pin. The command sequence is illustrated in

Table 12. Note: If a Bank Address (BA) (on address bits A21–A19) is asserted

during the third write cycle of the autoselect command, the host system can read

autoselect data that bank and then immediately read array data from the other

bank, without exiting the autoselect mode.

To access the autoselect codes in-system, the host system can issue the autose-

lect command via the command register, as shown in Table 12. This method does

not require V_ID. See “Autoselect Command Sequence” on page 46 for more

information.

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

29

A d v a n c e I n f o r m a t i o n

Table 5. Autoselect Codes for PL129J

A21

to

A5

to

DQ15

Description

CE1# CE2# OE# WE# A12

A10 A9 A8 A7 A6

A4 A3 A2 A1 A0

to DQ0

Manufacturer

L

H

L

V_I

ID:

Spansion

L

H

X

L

X

L

0001h

D

H

products

L

H

L

H

L

Read

Cycle 1

L

H

L

H

L

H

L

227Eh

2221h

2200h

H

L

Read

Cycle 2

V_I

L

H

D

H

L

H

L

Read

Cycle 3

H

L

Sector

Protection

Verification

H

V_I

0001h (protected),

0000h (unprotected)

L

H

SA

X

L

H

L

D

H

L

Secured

Silicon

Indicator Bit

(DQ7, DQ6)

H

DQ7=1 (factory

locked),

DQ6=1 (factory and

V_I

X

H

D

H

L

customer locked)

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, BA = Bank Address, SA = Sector Address, X = Don’t care.

Note: The autoselect codes may also be accessed in-system via command sequences

30

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

Table 6. PL129J Boot Sector/Sector Block Addresses for Protection/Unprotection

CE1# Control

CE2# Control

Sector/Sector Block

Size

Sector/Sector Block

Size

Sector Group

SA1-0

A21-12

Sector Group

SA2-0–SA2-3

SA2-4–SA2-7

SA2-8–SA2-11

SA2-12–SA2-15

SA2-16–SA2-19

SA2-20–SA2-23

SA2-24–SA2-27

SA2-28–SA2-31

SA2-32–SA2-35

SA2-36–SA2-39

SA2-40–SA2-43

SA2-44–SA2-47

SA2-48–SA2-51

SA2-52–SA2-55

SA2-56–SA2-59

SA2-60–SA2-63

SA2-64–SA2-67

SA2-68–SA2-71

SA2-72–SA2-75

SA2-76–SA2-79

SA2-80–SA2-83

SA2-84–SA2-87

SA2-88–SA2-91

SA2-92–SA2-95

SA2-96–SA2-99

SA2-100–SA2-103

SA2-104–SA2-107

SA2-108–SA2-111

SA2-112–SA2-115

SA2-116–SA2-119

SA2-120–SA2-123

SA2-124

A21-12

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

11111XXXXX

4 Kwords

00000XXXXX

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

1111100XXX

1111101XXX

1111110XXX

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

128 (4x32) Kwords

32 Kwords

SA1-1

4 Kwords

SA1-2

4 Kwords

SA1-3

4 Kwords

SA1-4

4 Kwords

SA1-5

4 Kwords

SA1-6

4 Kwords

SA1-7

4 Kwords

SA1-8

32 Kwords

SA1-9

32 Kwords

SA1-10

32 Kwords

SA1-11 - SA1-14

SA1-15 - SA1-18

SA1-19 - SA1-22

SA1-23 - SA1-26

SA1-27 - SA1-30

SA1-31 - SA1-34

SA1-35 - SA1-38

SA1-39 - SA1-42

SA1-43 - SA1-46

SA1-47 - SA1-50

SA1-51 - SA1-54

SA1-55 - SA1-58

SA1-59 - SA1-62

SA1-63 - SA1-66

SA1-67 - SA1-70

SA1-71 - SA1-74

SA1-75 - SA1-78

SA1-79 - SA1-82

SA1-83 - SA1-86

SA1-87 - SA1-90

SA1-91 - SA1-94

SA1-95 - SA1-98

SA1-99 - SA1-102

SA1-103 - SA1-106

SA1-107 - SA1-110

SA1-111 - SA1-114

SA1-115 - SA1-118

SA1-119 - SA1-122

SA1-123 - SA1-126

SA1-127 - SA1-130

SA1-131 - SA1-134

128 (4x32) Kwords

SA2-125

32 Kwords

SA2-126

32 Kwords

SA2-127

4 Kwords

SA2-128

4 Kwords

SA2-129

4 Kwords

SA2-130

4 Kwords

SA2-131

4 Kwords

SA2-132

4 Kwords

SA2-133

4 Kwords

SA2-134

4 Kwords

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

31

A d v a n c e I n f o r m a t i o n

Selecting a Sector Protection Mode

The device is shipped with all sectors unprotected. Optional Spansion program-

ming services enable programming and protecting sectors at the factory prior to

shipping the device. Contact your local sales office for details.

It is possible to determine whether a sector is protected or unprotected. See “Se-

cured Silicon Sector Addresses” on page 29 for details.

Table 7. Sector Protection Schemes

DYB

0

PPB

0

PPB Lock

Sector State

0

1

0

1

Unprotected—PPB and DYB are changeable

Unprotected—PPB not changeable, DYB is changeable

0

1

0

Protected—PPB and DYB are changeable

1

0

1

0

Protected—PPB not changeable, DYB is changeable

1

Sector Protection

The PL129J features several levels of sector protection, which can disable both

the program and erase operations in certain sectors or sector groups:

Persistent Sector Protection

A command sector protection method that replaces the old 12 V controlled pro-

tection method.

Password Sector Protection

A highly sophisticated protection method that requires a password before

changes to certain sectors or sector groups are permitted

WP# Hardware Protection

A write protect pin that can prevent program or erase operations in sectors SA1-

133, SA1-134, SA2-0 and SA2-1.

The WP# Hardware Protection feature is always available, independent of the

software managed protection method chosen.

Selecting a Sector Protection Mode

All parts default to operate in the Persistent Sector Protection mode. The cus-

tomer must then choose if the Persistent or Password Protection method is most

desirable. There are two one-time programmable non-volatile bits that define

which sector protection method is used. If the Persistent Sector Protection

method is desired, programming the Persistent Sector Protection Mode Locking

Bit permanently sets the device to the Persistent Sector Protection mode. If the

Password Sector Protection method is desired, programming the Password Mode

Locking Bit permanently sets the device to the Password Sector Protection mode.

It is not possible to switch between the two protection modes once a locking bit

has been set. One of the two modes must be selected when the device is first

32

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

programmed. This prevents a program or virus from later setting the Password

Mode Locking Bit, which would cause an unexpected shift from the default Per-

sistent Sector Protection Mode into the Password Protection Mode.

The device is shipped with all sectors unprotected. Optional Spansion program-

ming services enable programming and protecting sectors at the factory prior to

shipping the device. Contact your local sales office for details.

It is possible to determine whether a sector is protected or unprotected. See Au-

toselect Mode for details.

Persistent Sector Protection

The Persistent Sector Protection method replaces the 12 V controlled protection

method in previous flash devices. This new method provides three different sec-

tor protection states:

Persistently Locked—The sector is protected and cannot be changed.

Dynamically Locked—The sector is protected and can be changed by a simple

command.

Unlocked—The sector is unprotected and can be changed by a simple com-

mand.

To achieve these states, three types of “bits” are used:

Persistent Protection Bit

Persistent Protection Bit Lock

Persistent Sector Protection Mode Locking Bit

Persistent Protection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is assigned to a maximum four

sectors (see the sector address tables for specific sector protection groupings).

All 4 Kword boot-block sectors have individual sector Persistent Protection Bits

(PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB

Write Command.

The device erases all PPBs in parallel. If any PPB requires erasure, the device

must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Oth-

erwise, a previously erased sector PPBs can potentially be over-erased. The flash

device does not have a built-in means of preventing sector PPBs over-erasure.

Persistent Protection Bit Lock (PPB Lock)

The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to

“1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable.

There is only one PPB Lock bit per device. The PPB Lock is cleared after power-

up or hardware reset. There is no command sequence to unlock the PPB Lock.

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector. After power-up or hardware

reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through

the DYB Write Command.

When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and

PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are

changeable.

When the device is first powered on the DYBs power up cleared (sectors not pro-

tected). The Protection State for each sector is determined by the logical OR of

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

33

A d v a n c e I n f o r m a t i o n

the PPB and the DYB related to that sector. For the sectors that have the PPBs

cleared, the DYBs control whether or not the sector is protected or unprotected.

By issuing the DYB Write command sequences, the DYBs are set or cleared, thus

placing each sector in the protected or unprotected state. These are the so-called

Dynamic Locked or Unlocked states. These states are called dynamic states be-

cause it is very easy to switch back and forth between the protected and

unprotected conditions. This allows software to easily protect sectors against in-

advertent changes yet does not prevent the easy removal of protection when

changes are needed. The DYBs maybe set or cleared as often as needed.

The PPBs allow for a more static, and difficult to change, level of protection. The

PPBs retain their state across power cycles because the PPBs are non-volatile. In-

dividual PPBs are set with a command but must all be cleared as a group through

a complex sequence of program and erasing commands. The PPBs are also lim-

ited to 100 erase cycles.

The PPB Lock bit adds an additional level of protection. Once all PPBs are pro-

grammed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB

Lock disables all program and erase commands to the non-volatile PPBs. In ef-

fect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear

the PPB Lock is to go through a power cycle. System boot code can determine if

any changes to the PPB are needed; for example, to allow new system code to

be downloaded. If no changes are needed then the boot code can set the PPB

Lock to disable any further changes to the PPBs during system operation.

The WP#/ACC write protect pin adds a final level of hardware protection to sec-

tors SA1-133, SA1-134, SA2-0 and SA2-1. When this pin is low it is not possible

to change the contents of these sectors. These sectors generally hold system

boot code. The WP#/ACC pin can prevent any changes to the boot code that could

override the choices made while setting up sector protection during system

initialization.

For customers who are concerned about malicious viruses there is another level

of security - the persistently locked state. To persistently protect a given sector

or sector group, the PPBs associated with that sector need to be set to “1”. Once

all PPBs are programmed to the desired settings, the PPB Lock should be set to

“1”. Setting the PPB Lock automatically disables all program and erase commands

to the Non-Volatile PPBs. In effect, the PPB Lock “freezes” the PPBs into their cur-

rent state. The only way to clear the PPB Lock is to go through a power cycle.

It is possible to have sectors that have been persistently locked, and sectors that

are left in the dynamic state. The sectors in the dynamic state are all unprotected.

If there is a need to protect some of them, a simple DYB Write command se-

quence is all that is necessary. The DYB write command for the dynamic sectors

switch the DYBs to signify protected and unprotected, respectively. If there is a

need to change the status of the persistently locked sectors, a few more steps

are required. First, the PPB Lock bit must be disabled by either putting the device

through a power-cycle, or hardware reset. The PPBs can then be changed to re-

flect the desired settings. Setting the PPB lock bit once again lock the PPBs, and

the device operates normally again.

The best protection is achieved by executing the PPB lock bit set command early

in the boot code, and protect the boot code by holding WP#/ACC = VIL.

Table 17 contains all possible combinations of the DYB, PPB, and PPB lock relating

to the status of the sector.

34

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

In summary, if the PPB is set, and the PPB lock is set, the sector is protected and

the protection can not be removed until the next power cycle clears the PPB lock.

If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB

then controls whether or not the sector is protected or unprotected.

If the user attempts to program or erase a protected sector, the device ignores

the command and returns to read mode. A program command to a protected sec-

tor enables status polling for approximately 1 µs before the device returns to read

mode without having modified the contents of the protected sector. An erase

command to a protected sector enables status polling for approximately 50 µs

after which the device returns to read mode without having erased the protected

sector.

The programming of the DYB, PPB, and PPB lock for a given sector can be verified

by writing a DYB/PPB/PPB lock verify command to the device. There is an alter-

native means of reading the protection status. Take RESET# to VIL and hold WE#

at VIH.(The high voltage A9 Autoselect Mode also works for reading the status of

the PPBs). Scanning the addresses (A18–A11) while (A6, A1, A0) = (0, 1, 0) pro-

duces a logical ‘1” code at device output DQ0 for a protected sector or a “0” for

an unprotected sector. In this mode, the other addresses are don’t cares. Address

location with A1 = VIL are reserved for autoselect manufacturer and device

codes.

Persistent Sector Protection Mode Locking Bit

Like the password mode locking bit, a Persistent Sector Protection mode locking

bit exists to guarantee that the device remain in software sector protection. Once

set, the Persistent Sector Protection locking bit prevents programming of the

password protection mode locking bit. This guarantees that a hacker could not

place the device in password protection mode.

Password Protection Mode

The Password Sector Protection Mode method allows an even higher level of se-

curity than the Persistent Sector Protection Mode. There are two main differences

between the Persistent Sector Protection and the Password Sector Protection

Mode:

When the device is first powered on, or comes out of a reset cycle, the PPB Lock

bit set to the locked state, rather than cleared to the unlocked state.

The only means to clear the PPB Lock bit is by writing a unique 64-bit Password

to the device.

The Password Sector Protection method is otherwise identical to the Persistent

Sector Protection method.

A 64-bit password is the only additional tool utilized in this method.

Once the Password Mode Locking Bit is set, the password is permanently set with

no means to read, program, or erase it. The password is used to clear the PPB

Lock bit. The Password Unlock command must be written to the flash, along with

a password. The flash device internally compares the given password with the

pre-programmed password. If they match, the PPB Lock bit is cleared, and the

PPBs can be altered. If they do not match, the flash device does nothing. There

is a built-in 2 µs delay for each “password check.” This delay is intended to thwart

any efforts to run a program that tries all possible combinations in order to crack

the password.

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

35

A d v a n c e I n f o r m a t i o n

Password and Password Mode Locking Bit

In order to select the Password sector protection scheme, the customer must first

program the password. The password may be correlated to the unique Electronic

Serial Number (ESN) of the particular flash device. Each ESN is different for every

flash device; therefore each password should be different for every flash device.

While programming in the password region, the customer may perform Password

Verify operations.

Once the desired password is programmed in, the customer must then set the

Password Mode Locking Bit. This operation achieves two objectives:

Permanently sets the device to operate using the Password Protection Mode. It is

not possible to reverse this function.

Disables all further commands to the password region. All program, and read op-

erations are ignored.

Both of these objectives are important, and if not carefully considered, may lead

to unrecoverable errors. The user must be sure that the Password Protection

method is desired when setting the Password Mode Locking Bit. More importantly,

the user must be sure that the password is correct when the Password Mode

Locking Bit is set. Due to the fact that read operations are disabled, there is no

means to verify what the password is afterwards. If the password is lost after set-

ting the Password Mode Locking Bit, there is not any way to clear the PPB Lock bit.

The Password Mode Locking Bit, once set, prevents reading the 64-bit password

on the DQ bus and further password programming. The Password Mode Locking

Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persis-

tent Sector Protection Locking Bit is disabled from programming, guaranteeing

that no changes to the protection scheme are allowed.

64-bit Password

The 64-bit Password is located in its own memory space and is accessible through

the use of the Password Program and Verify commands (see “Password Verify

Command”). The password function works in conjunction with the Password

Mode Locking Bit, which when set, prevents the Password Verify command from

reading the contents of the password on the pins of the device.

Write Protect (WP#)

The Write Protect feature provides a hardware method of protecting the upper

two and lower two sectors(PL127J: 0, 1, 268, and 269, PL064J: 0, 1, 140, and

141, PL032J: 0, 1, 76, and 77, PL129J: SA1-133, SA1-134,SA2-0 and SA2-1)

without using V_ID. This function is provided by the WP# pin and overrides the pre-

viously discussed method, “High Voltage Sector Protection” on page 37.

If the system asserts V_ILon the WP#/ACC pin, the device disables program and

erase functions in the two outermost 4 Kword sectors on both ends of the flash

array independent of whether it was previously protected or unprotected.

If the system asserts V_IHon the WP#/ACC pin, the device reverts the upper two

and lower two sectors to whether they were last set to be protected or unpro-

tected. That is, sector protection or unprotection for these sectors depends on

whether they were last protected or unprotected using the method described in

“High Voltage Sector Protection” on page 37.

Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent

behavior of the device may result.

36

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of

the Password Mode Locking Bit after power-up reset. If the Password Mode Lock

Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the

ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue

the Password Unlock command. Successful execution of the Password Unlock

command clears the PPB Lock Bit, allowing for sector PPBs modifications. Assert-

ing RESET#, taking the device through a power-on reset, or issuing the PPB Lock

Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit

is not set.

If the Password Mode Locking Bit is not set, including Persistent Protection Mode,

the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is

set by issuing the PPB Lock Bit Set command. Once set the only means for clear-

ing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password

Unlock command is ignored in Persistent Protection Mode.

High Voltage Sector Protection

Sector protection and unprotection may also be implemented using programming

equipment. The procedure requires high voltage (V_ID) to be placed on the RE-

SET# pin. Refer to Figure 1 for details on this procedure. Note that for sector

unprotect, all unprotected sectors must first be protected prior to the first sector

write cycle.

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

37

A d v a n c e I n f o r m a t i o n

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 4 µs

unprotect address

No

First Write

Cycle = 60h?

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A7-A0 =

Yes

Set up first sector

address

00000010

Sector Unprotect:

Wait 100 µs

Write 60h to sector

address with

A7-A0 =

Verify Sector

Protect: Write 40h

to sector address

with A7-A0 =

01000010

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 1.2 ms

00000010

Verify Sector

Unprotect: Write

40h to sector

address with

A7-A0 =

Read from

sector address

with A7-A0 =

00000010

Increment

PLSCNT

No

00000010

No

PLSCNT

= 25?

Read from

sector address

with A7-A0 =

00000010

Data = 01h?

Yes

No

Yes

Set up

next sector

address

Yes

Remove V_ID

from RESET#

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

No

Write reset

command

Yes

Remove V_ID

from RESET#

Remove V_ID

from RESET#

No

Last sector

verified?

Sector Protect

complete

Write reset

command

Yes

Write reset

command

Remove V_ID

from RESET#

Device failed

Sector Protect

complete

Sector Unprotect

complete

Write reset

command

Sector Protect

Algorithm

Device failed

Sector Unprotect

complete

Sector Unprotect

Algorithm

Figure 1. In-System Sector Protection/Sector Unprotection Algorithms

38

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to

change data in-system. The Sector Unprotect mode is activated by setting the

RESET# pin to V_ID. During this mode, formerly protected sectors can be pro-

grammed or erased by selecting the sector addresses. Once V_IDis removed from

the RESET# pin, all the previously protected sectors are protected again.

Figure 2 shows the algorithm, and Figure 21 shows the timing diagrams, for this

feature. While PPB lock is set, the device cannot enter the Temporary Sector Un-

protection Mode.

START

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors are unprotected (If WP#/ACC = V , upper two and lower

IL

two sectors remain protected).

2. All previously protected sectors are protected once again

Figure 2. Temporary Sector Unprotect Operation

Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector feature provides a Flash memory region that enables

permanent part identification through an Electronic Serial Number (ESN) The

128-word Secured Silicon sector is divided into 64 factory-lockable words that

can be programmed and locked by the customer. The Secured Silicon sector is

located at addresses 000000h-00007Fh in both Persistent Protection mode and

Password Protection mode. Indicator bits DQ6 and DQ7 are used to indicate the

factory-locked and customer locked status of the part.

The system accesses the Secured Silicon Sector through a command sequence

(see “Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-

quence” on page 46). After the system has written the Enter Secured Silicon

Sector command sequence, it may read the Secured Silicon Sector by using the

addresses normally occupied by the boot sectors. This mode of operation contin-

ues until the system issues the Exit Secured Silicon Sector command sequence,

or until power is removed from the device. On power-up, or following a hardware

reset, the device reverts to sending commands to the normal address space. Note

that the ACC function and unlock bypass modes are not available when the Se-

cured Silicon Sector is enabled.

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

39

A d v a n c e I n f o r m a t i o n

Factory-Locked Area (64 words)

The factory-locked area of the Secured Silicon Sector (000000h-00003Fh) is

locked when the part is shipped, whether or not the area was programmed at the

factory. The Secured Silicon Sector Factory-locked Indicator Bit (DQ7) is perma-

nently set to a “1”. Optional Spansion programming services can program the

factory-locked area with a random ESN, a customer-defined code, or any combi-

nation of the two. Because only FASL can program and protect the factory-locked

area, this method ensures the security of the ESN once the product is shipped to

the field. Contact your local sales office for details on using Spansion’s program-

ming services. Note that the ACC function and unlock bypass modes are not

available when the Secured Silicon sector is enabled.

Customer-Lockable Area (64 words)

The customer-lockable area of the Secured Silicon Sector (000040h-00007Fh) is

shipped unprotected, which allows the customer to program and optionally lock

the area as appropriate for the application. The Secured Silicon Sector Customer-

locked Indicator Bit (DQ6) is shipped as “0” and can be permanently locked to “1”

by issuing the Secured Silicon Protection Bit Program Command. The Secured Sil-

icon Sector can be read any number of times, but can be programmed and locked

only once. Note that the accelerated programming (ACC) and unlock bypass func-

tions are not available when programming the Secured Silicon Sector.

The Customer-lockable Secured Silicon Sector area can be protected using one

of the following procedures:

Write the three-cycle Enter Secured Silicon Sector Region command se-

quence, and then follow the in-system sector protect algorithm as shown in

Figure 1, except that RESET# may be at either V_IHor V_ID. This allows in-sys-

tem protection of the Secured Silicon Sector Region without raising any de-

vice pin to a high voltage. Note that this method is only applicable to the

Secured Silicon Sector.

To verify the protect/unprotect status of the Secured Silicon Sector, follow the

algorithm shown in Figure 3.

Once the Secured Silicon Sector is locked and verified, the system must write the

Exit Secured Silicon Sector Region command sequence to return to reading and

writing the remainder of the array.

The Secured Silicon Sector lock must be used with caution since, once locked,

there is no procedure available for unlocking the Secured Silicon Sector area and

none of the bits in the Secured Silicon Sector memory space can be modified in

any way.

Secured Silicon Sector Protection Bits

The Secured Silicon Sector Protection Bits prevent programming of the Secured

Silicon Sector memory area. Once set, the Secured Silicon Sector memory area

contents are non-modifiable.

40

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

START

If data = 00h,

RESET# =

V_IHor V_ID

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Wait 1 µs

Write 60h to

any address

Remove V_IHor V_ID

from RESET#

Write 40h to SecSi

Sector address

with A6 = 0,

Write reset

command

A1 = 1, A0 = 0

SecSi Sector

Protect Verify

complete

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

Figure 3. Secured Silicon Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing

provides data protection against inadvertent writes. In addition, the following

hardware data protection measures prevent accidental erasure or programming,

which might otherwise be caused by spurious system level signals during V_CC

power-up and power-down transitions, or from system noise.

Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not accept any write cycles. This pro-

tects data during V_CCpower-up and power-down. The command register and all

internal program/erase circuits are disabled, and the device resets to the read

mode. Subsequent writes are ignored until V_CCis greater than V_LKO. The system

must provide the proper signals to the control pins to prevent unintentional writes

when V_CCis greater than V_LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE#, CE1#, CE2# or WE# do not ini-

tiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V_IL, CE1# = CE2# = V_IH

or WE# = V_IH. To initiate a write cycle, CE1# / CE2# and WE# must be a logical

zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# (CE1#, CE2# in PL129J) = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising edge of WE#. The internal

state machine is automatically reset to the read mode on power-up.

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

41

A d v a n c e I n f o r m a t i o n

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system

software interrogation handshake, which allows specific vendor-specified soft-

ware algorithms to be used for entire families of devices. Software support can

then be device-independent, JEDEC ID-independent, and forward- and back-

ward-compatible for the specified flash device families. Flash vendors can

standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query

command, 98h, to address 55h, any time the device is ready to read array data.

The system can read CFI information at the addresses given in Table 8, Table 9,

Table 10, and Table 11. To terminate reading CFI data, the system must write the

reset command. The CFI Query mode is not accessible when the device is exe-

cuting an Embedded Program or embedded Erase algorithm.

The system can also write the CFI query command when the device is in the au-

toselect mode. The device enters the CFI query mode, and the system can read

CFI data at the addresses given in Table 8, Table 9, Table 10, and Table 11. The

system must write the reset command to return the device to reading array data.

For further information, please refer to the CFI Specification and CFI Publication

100. Contact your local sales office for copies of these documents.

Table 8. CFI Query Identification String

Addresses

Data

Description

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

19h

1Ah

0000h

Address for Alternate OEM Extended Table (00h = none exists)

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Table 9. System Interface String

Addresses

Data

Description

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

0027h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0036h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0003h

0000h

0009h

0000h

0004h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^N

Typical timeout per individual block erase 2^Nms

µs (00h = not supported)

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 10. Device Geometry Definition

Addresses

Data

Description

27h

0018h (PL129J)

Device Size = 2^Nbyte

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ch

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

00FDh (PL129J)

Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

32h

33h

34h

0000h

0001h

35h

36h

37h

38h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

39h

3Ah

3Bh

3Ch

0000h

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

Table 11. Primary Vendor-Specific Extended Query

Addresses

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

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A d v a n c e I n f o r m a t i o n

Table 11. Primary Vendor-Specific Extended Query (Continued)

Addresses

43h

Data

Description

0031h

0033h

Major version number, ASCII (reflects modifications to the silicon)

Minor version number, ASCII (reflects modifications to the CFI table)

44h

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

TBD

Silicon Revision Number (Bits 7-2)

Erase Suspend

46h

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

0002h

0001h

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

0001h

Sector Protect/Unprotect scheme

07 = Advanced Sector Protection

0007h (PLxxxJ)

00E7h (PL129J)

0000h

Simultaneous Operation

00 = Not Supported, X = Number of Sectors excluding Bank 1

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

0002h (PLxxxJ)

0085h

ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

0095h

Top/Bottom Boot Sector Flag

00h = Uniform device, 01h = Both top and bottom boot with write protect,

02h = Bottom Boot Device, 03h = Top Boot Device,

04h = Both Top and Bottom

4Fh

0001h

Program Suspend

0 = Not supported, 1 = Supported

50h

57h

58h

59h

5Ah

5Bh

0001h

Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

0004h

Bank 1 Region Information

X = Number of Sectors in Bank 1

0027h (PL129J)

0060h (PL129J)

0027h (PL129J)

Bank 2 Region Information

X = Number of Sectors in Bank 2

Bank 3 Region Information

X = Number of Sectors in Bank 3

Bank 4 Region Information

X = Number of Sectors in Bank 4

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Command Definitions

Writing specific address and data commands or sequences into the command

register initiates device operations. Table 12 defines the valid register command

sequences. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state. A reset com-

mand is then required to return the device to reading array data.

All addresses are latched on the falling edge of WE# or CE# (CE1# / CE2# in

PL129J), whichever happens later. All data is latched on the rising edge of WE#

or CE# (CE1# / CE2# in PL129J), whichever happens first. See AC Characteristics

for timing diagrams.

Reading Array Data

The device is automatically set to reading array data after device power-up. No

commands are required to retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the corresponding bank

enters the erase-suspend-read mode, after which the system can read data from

any non-erase-suspended sector within the same bank. The system can read

array data using the standard read timing, except that if it reads at an address

within erase-suspended sectors, the device outputs status data. After completing

a programming operation in the Erase Suspend mode, the system may once

again read array data with the same exception. See “Erase Suspend/Erase Re-

sume Commands” on page 50 for more information.

The system must issue the reset command to return a bank to the read (or erase-

suspend-read) mode if DQ5 goes high during an active program or erase opera-

tion, or if the bank is in the autoselect mode. See “Reset Command,” for more

information.

See “Requirements for Reading Array Data” on page 19 in “Device Bus Opera-

tions” for more information. The AC Characteristics table provides the read

parameters, and Figure 12 shows the timing diagram.

Reset Command

Writing the reset command resets the banks to the read or erase-suspend-read

mode. Address bits are don’t cares for this command.

The reset command may be written between the sequence cycles in an erase

command sequence before erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure begins, however, the device

ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program

command sequence before programming begins. This resets the bank to which

the system was writing to the read mode. If the program command sequence is

written to a bank that is in the Erase Suspend mode, writing the reset command

returns that bank to the erase-suspend-read mode. Once programming begins,

however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect

command sequence. Once in the autoselect mode, the reset command must be

written to return to the read mode. If a bank entered the autoselect mode while

in the Erase Suspend mode, writing the reset command returns that bank to the

erase-suspend-read mode.

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A d v a n c e I n f o r m a t i o n

If DQ5 goes high during a program or erase operation, writing the reset command

returns the banks to the read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manu-

facturer and device codes, and determine whether or not a sector is protected.

The autoselect command sequence may be written to an address within a bank

that is either in the read or erase-suspend-read mode. The autoselect command

may not be written while the device is actively programming or erasing in the

other bank.

The autoselect command sequence is initiated by first writing two unlock cycles.

This is followed by a third write cycle that contains the bank address and the au-

toselect command. The bank then enters the autoselect mode. The system may

read any number of autoselect codes without reinitiating the command sequence.

Table 12 shows the address and data requirements. To determine sector protec-

tion information, the system must write to the appropriate bank address (BA) and

sector address (SA).

The system must write the reset command to return to the read mode (or erase-

suspend-read mode if the bank was previously in Erase Suspend).

Enter Secured Silicon Sector/Exit Secured Silicon Sector Command

Sequence

The Secured Silicon Sector region provides a secured data area containing a ran-

dom, eight word electronic serial number (ESN). The system can access the

Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon

Sector command sequence. The device continues to access the Secured Silicon

Sector region until the system issues the four-cycle Exit Secured Silicon Sector

command sequence. The Exit Secured Silicon Sector command sequence returns

the device to normal operation. The Secured Silicon Sector is not accessible when

the device is executing an Embedded Program or embedded Erase algorithm.

Table 12 shows the address and data requirements for both command sequences.

Also see, “Secured Silicon Sector Flash Memory Region” on page 39 for further in-

formation. Note: The ACC function and unlock bypass modes are not available

when the Secured Silicon Sector is enabled.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is

initiated by writing two unlock write cycles, followed by the program set-up com-

mand. The program address and data are written next, which in turn initiate the

Embedded Program algorithm. The system is not required to provide further con-

trols or timings. The device automatically provides internally generated program

pulses and verifies the programmed cell margin. Table 12 shows the address and

data requirements for the program command sequence. Note that the Secured

Silicon Sector, autoselect, and CFI functions are unavailable when a [program/

erase] operation is in progress.

When the Embedded Program algorithm is complete, that bank then returns to

the read mode and addresses are no longer latched. The system can determine

the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write

Operation Status” on page 56 for information on these status bits.

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Any commands written to the device during the Embedded Program Algorithm

are ignored. Note that a hardware reset immediately terminates the program

operation. The program command sequence should be reinitiated once that bank

has returned to the read mode, to ensure data integrity. Note that the Secured

Silicon Sector, autoselect and CFI functions are unavailable when the Secured Sil-

icon Sector is enabled.

Programming is allowed in any sequence and across sector boundaries. A bit

cannot be programmed from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate

the operation was successful. However, a succeeding read shows that the data is

still “0.” Only erase operations can convert a “0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program data to a bank faster

than using the standard program command sequence. The unlock bypass com-

mand sequence is initiated by first writing two unlock cycles. This is followed by

a third write cycle containing the unlock bypass command, 20h. That bank then

enters the unlock bypass mode. A two-cycle unlock bypass program command

sequence is all that is required to program in this mode. The first cycle in this se-

quence contains the unlock bypass program command, A0h; the second cycle

contains the program address and data. Additional data is programmed in the

same manner. This mode dispenses with the initial two unlock cycles required in

the standard program command sequence, resulting in faster total programming

time. Table 12 shows the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-

pass Reset commands are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset command sequence. (Table 13)

The device offers accelerated program operations through the WP#/ACC pin.

When the system asserts V_HHon the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then write the two-cycle Unlock

Bypass program command sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not

be at V_HHany operation other than accelerated programming, or device damage

may result. In addition, the WP#/ACC pin must not be left floating or uncon-

nected; inconsistent behavior of the device may result.

Figure 4 illustrates the algorithm for the program operation. See the Erase/Pro-

gram Operations table in AC Characteristics for parameters, and Figure 14 for

timing diagrams.

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A d v a n c e I n f o r m a t i o n

START

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

No

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 12 for program command sequence.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is ini-

tiated by writing two unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the chip erase command,

which in turn invokes the Embedded Erase algorithm. The device does not require

the system to preprogram prior to erase. The Embedded Erase algorithm auto-

matically preprograms and verifies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to provide any controls or tim-

ings during these operations. Table 12 shows the address and data requirements

for the chip erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read

mode and addresses are no longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to “Write Op-

eration Status” on page 56 for information on these status bits.

Any commands written during the chip erase operation are ignored. Note that Se-

cured Silicon Sector, autoselect, and CFI functions are unavailable when a

[program/erase] operation is in progress. However, note that a hardware reset

immediately terminates the erase operation. If that occurs, the chip erase com-

mand sequence should be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

Figure 5 illustrates the algorithm for the erase operation. See the Erase/Program

Operations tables in AC Characteristics for parameters, and Figure 16 for timing

diagrams.

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A d v a n c e I n f o r m a t i o n

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is

initiated by writing two unlock cycles, followed by a set-up command. Two addi-

tional unlock cycles are written, and are then followed by the address of the

sector to be erased, and the sector erase command. Table 12 shows the address

and data requirements for the sector erase command sequence.

The device does not require the system to preprogram prior to erase. The Em-

bedded Erase algorithm automatically programs and verifies the entire memory

for an all zero data pattern prior to electrical erase. The system is not required to

provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs occurs.

During the time-out period, additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer may be done in any

sequence, and the number of sectors may be from one sector to all sectors. The

time between these additional cycles must be less than 50 µs, otherwise erasure

may begin. Any sector erase address and command following the exceeded time-

out may or may not be accepted. It is recommended that processor interrupts be

disabled during this time to ensure all commands are accepted. The interrupts

can be re-enabled after the last Sector Erase command is written. If any com-

mand other than 30h, B0h, F0h is input during the time-out period, the

normal operation cannot be guaranteed. The system must rewrite the com-

mand sequence and any additional addresses and commands. Note that Secured

Silicon Sector, autoselect, and CFI functions are unavailable when a [program/

erase] operation is in progress.

The system can monitor DQ3 to determine if the sector erase timer has timed out

(See “DQ3: Sector Erase Timer” on page 61). The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete, the bank returns to reading

array data and addresses are no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read data from the non-erasing

bank. The system can determine the status of the erase operation by reading

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. See “Write Operation Status” on

page 56 for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is

valid. All other commands are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that occurs, the sector erase

command sequence should be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

Figure 5 illustrates the algorithm for the erase operation. See the Erase/Program

Operations tables in AC Characteristics for parameters, and Figure 16 for timing

diagrams.

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A d v a n c e I n f o r m a t i o n

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 12 for erase command sequence.

2. See “DQ3: Sector Erase Timer” on page 61 for information on the sector erase

timer.

Figure 5. Erase Operation

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase

operation and then read data from, or program data to, any sector not selected

for erasure. The bank address is required when writing this command. This com-

mand is valid only during the sector erase operation, including the 80 µs time-out

period during the sector erase command sequence. The Erase Suspend command

is ignored if written during the chip erase operation or Embedded Program

algorithm.

When the Erase Suspend command is written during the sector erase operation,

the device requires a maximum of 35 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written during the sector erase

time-out, the device immediately terminates the time-out period and suspends

the erase operation. Addresses are “don’t-cares” when writing the Erase suspend

command.

After the erase operation has been suspended, the bank enters the erase-sus-

pend-read mode. The system can read data from or program data to any sector

not selected for erasure. (The device “erase suspends” all sectors selected for

erasure.) Reading at any address within erase-suspended sectors produces sta-

tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively erasing or is erase-suspended. See

“Write Operation Status” on page 56 for information on these status bits.

After an erase-suspended program operation is complete, the bank returns to the

erase-suspend-read mode. The system can determine the status of the program

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operation using the DQ7 or DQ6 status bits, just as in the standard Word Program

operation. See “Write Operation Status” on page 56 for more information.

In the erase-suspend-read mode, the system can also issue the autoselect com-

mand sequence. The device allows reading autoselect codes even at addresses

within erasing sectors, since the codes are not stored in the memory array. When

the device exits the autoselect mode, the device reverts to the Erase Suspend

mode, and is ready for another valid operation. See “Secured Silicon Sector Ad-

dresses” on page 29 and “Autoselect Command Sequence” on page 46 for details.

To resume the sector erase operation, the system must write the Erase Resume

command (address bits are don’t care). The bank address of the erase-sus-

pended bank is required when writing this command. Further writes of the

Resume command are ignored. Another Erase Suspend command can be written

after the chip has resumed erasing.

Password Program Command

The Password Program Command permits programming the password that is

used as part of the hardware protection scheme. The actual password is 64-bits

long. Four Password Program commands are required to program the password.

The system must enter the unlock cycle, password program command (38h) and

the program address/data for each portion of the password when programming.

There are no provisions for entering the 2-cycle unlock cycle, the password pro-

gram command, and all the password data. There is no special addressing order

required for programming the password. Also, when the password is undergoing

programming, Simultaneous Operation is disabled. Read operations to any mem-

ory location will return the programming status. Once programming is complete,

the user must issue a Read/Reset command to return the device to normal oper-

ation. Once the Password is written and verified, the Password Mode Locking Bit

must be set in order to prevent verification. The Password Program Command is

only capable of programming “0”s. Programming a “1” after a cell is programmed

as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell

remaining as a “0”. The password is all ones when shipped from the factory. All

64-bit password combinations are valid as a password.

Password Verify Command

The Password Verify Command is used to verify the Password. The Password is

verifiable only when the Password Mode Locking Bit is not programmed. If the

Password Mode Locking Bit is programmed and the user attempts to verify the

Password, the device will always drive all F’s onto the DQ data bus.

The Password Verify command is permitted if the Secured Silicon sector is en-

abled. Also, the device will not operate in Simultaneous Operation when the

Password Verify command is executed. Only the password is returned regardless

of the bank address. The lower two address bits (A1-A0) are valid during the

Password Verify. Writing the Read/Reset command returns the device back to

normal operation.

Password Protection Mode Locking Bit Program Command

The Password Protection Mode Locking Bit Program Command programs the

Password Protection Mode Locking Bit, which prevents further verifies or updates

to the Password. Once programmed, the Password Protection Mode Locking Bit

cannot be erased! If the Password Protection Mode Locking Bit is verified as pro-

gram without margin, the Password Protection Mode Locking Bit Program

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A d v a n c e I n f o r m a t i o n

command can be executed to improve the program margin. Once the Password

Protection Mode Locking Bit is programmed, the Persistent Sector Protection

Locking Bit program circuitry is disabled, thereby forcing the device to remain in

the Password Protection mode. Exiting the Mode Locking Bit Program command

is accomplished by writing the Read/Reset command.

Persistent Sector Protection Mode Locking Bit Program Command

The Persistent Sector Protection Mode Locking Bit Program Command programs

the Persistent Sector Protection Mode Locking Bit, which prevents the Password

Mode Locking Bit from ever being programmed. If the Persistent Sector Protec-

tion Mode Locking Bit is verified as programmed without margin, the Persistent

Sector Protection Mode Locking Bit Program Command should be reissued to im-

prove program margin. By disabling the program circuitry of the Password Mode

Locking Bit, the device is forced to remain in the Persistent Sector Protection

mode of operation, once this bit is set. Exiting the Persistent Protection Mode

Locking Bit Program command is accomplished by writing the Read/Reset

command.

Secured Silicon Sector Protection Bit Program Command

The Secured Silicon Sector Protection Bit Program Command programs the Se-

cured Silicon Sector Protection Bit, which prevents the Secured Silicon sector

memory from being cleared. If the Secured Silicon Sector Protection Bit is verified

as programmed without margin, the Secured Silicon Sector Protection Bit Pro-

gram Command should be reissued to improve program margin. Exiting the V_CC-

level Secured Silicon Sector Protection Bit Program Command is accomplished by

writing the Read/Reset command.

PPB Lock Bit Set Command

The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either

at reset or if the Password Unlock command was successfully executed. There is

no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared

unless the device is taken through a power-on clear or the Password Unlock com-

mand is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the

DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected

as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command

is accomplished by writing the Read/Reset command (only in the Persistent Pro-

tection Mode).

DYB Write Command

The DYB Write command is used to set or clear a DYB for a given sector. The high

order address bits (Amax–A12) are issued at the same time as the code 01h or

00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write

cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or

PPB Lock Bit. The DYBs are cleared at power-up or hardware reset.Exiting the

DYB Write command is accomplished by writing the Read/Reset command.

Password Unlock Command

The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs

can be unlocked for modification, thereby allowing the PPBs to become accessible

for modification. The exact password must be entered in order for the unlocking

function to occur. This command cannot be issued any faster than 2 µs at a time

to prevent a hacker from running through all 64-bit combinations in an attempt

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A d v a n c e I n f o r m a t i o n

to correctly match a password. If the command is issued before the 2 µs execu-

tion window for each portion of the unlock, the command will be ignored.

Once the Password Unlock command is entered, the RY/BY# indicates that the

device is busy. Approximately 1 µs is required for each portion of the unlock. Once

the first portion of the password unlock completes (RY/BY# is not low or DQ6

does not toggle when read), the next part of the password is written. The system

must thus monitor RY/BY# or the status bits to confirm when to write the next

portion of the password. Seven cycles are required to successfully clear the PPB

Lock Bit.

PPB Program Command

The PPB Program command is used to program, or set, a given PPB. Each PPB is

individually programmed (but is bulk erased with the other PPBs). The specific

sector address (A22–A12) are written at the same time as the program command

60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for

the sector, the PPB Program command will not execute and the command will

time-out without programming the PPB.

After programming a PPB, two additional cycles are needed to determine whether

the PPB has been programmed with margin. If the PPB has been programmed

without margin, the program command should be reissued to improve the pro-

gram margin. Also note that the total number of PPB program/erase cycles is

limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed.

The PPB Program command does not follow the Embedded Program algorithm.

All PPB Erase Command

The All PPB Erase command is used to erase all PPBs in bulk. There is no means

for individually erasing a specific PPB. Unlike the PPB program, no specific sector

address is required. However, when the PPB erase command is written all Sector

PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command

will not execute and the command will time-out without erasing the PPBs. After

erasing the PPBs, two additional cycles are needed to determine whether the PPB

has been erased with margin. If the PPBs has been erased without margin, the

erase command should be reissued to improve the program margin.

It is the responsibility of the user to preprogram all PPBs prior to issuing the All

PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure

may occur making it difficult to program the PPB at a later time. Also note that

the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the

PPBs beyond 100 cycles is not guaranteed.

DYB Write Command

The DYB Write command is used for setting the DYB, which is a volatile bit that

is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is

protected regardless of the value of the DYB. If the PPB is cleared, setting the

DYB to a 1 protects the sector from programs or erases. Since this is a volatile

bit, removing power or resetting the device will clear the DYBs. The bank address

is latched when the command is written.

PPB Lock Bit Set Command

The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit

that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector

is protected regardless of the value of the DYB. If the PPB is cleared, setting the

June 4, 2004 S29PL129J_MCP_00_A0

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A d v a n c e I n f o r m a t i o n

DYB to a 1 protects the sector from programs or erases. Since this is a volatile

bit, removing power or resetting the device will clear the DYBs. The bank address

is latched when the command is written.

Command

The programming of either the PPB or DYB for a given sector or sector group can

be verified by writing a Sector Protection Status command to the device.

Note that there is no single command to independently verify the programming

of a DYB for a given sector group.

Command Definitions Tables

Table 12. Memory Array Command Definitions

Bus Cycles (Notes 1–4)

Command (Notes)

Addr Data Addr Data Addr Data Addr

Data

Addr

Data

Addr

Data

Read (Note 5)

Reset (Note 6)

1

RA

RD

F0

XXX

(BA)

555

(BA)

X00

Manufacturer ID

4

6

555

AA

2AA

55

90

01

(BA)

555

(BA)

X01

(BA)

X0E

(Note

10)

(BA)

X0F

(Note

10)

Device ID (Note 10)

227E

Autoselect

(Note 7)

SecuredSiliconSector

Factory Protect (Note

8)

(BA)

555

(Note

8)

4

555

AA

2AA

55

90

X03

Sector Group Protect

Verify (Note 9)

(BA)

555

(SA)

X02

XX00/

XX01

AAA

Program

4

6

1

2

3

2

1

2

555

BA

AA

B0

30

98

A0

AA

A0

80

98

90

2AA

55

555

A0

80

PA

PD

AA

Chip Erase

Sector Erase

555

2AA

55

555

SA

10

30

Program/Erase Suspend (Note 11)

Program/Erase Resume (Note 12)

CFI Query (Note 13)

BA

55

Accelerated Program (Note 15)

Unlock Bypass Entry (Note 15)

Unlock Bypass Program (Note 15)

Unlock Bypass Erase (Note 15)

Unlock Bypass CFI (Notes 13, 15)

Unlock Bypass Reset (Note 15)

XX

PA

2AA

PA

PD

55

PD

10

555

XX

555

20

XX

XXX

00

Legend:

BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by Amax:A19.

PA = Program Address (Amax:A0). Addresses latch on falling edge of WE# or CE1#/CE2# pulse, whichever happens

later.

PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE1#/CE2# pulse,

whichever happens first.

RA = Read Address (Amax:A0).

RD = Read Data (DQ15:DQ0) from location RA.

SA = Sector Address (Amax:A12) for verifying (in autoselect mode) or erasing.

WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#.

X = Don’t care

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles are write operations.

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4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than

A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.

5. No unlock or command cycles required when bank is reading array data.

6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend)

when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information).

7. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID

or device ID information. See “Autoselect Command Sequence” on page 46 for more information.

8. The data is DQ6=1 for factory and customer locked and DQ7=1 for factory locked.

9. The data is 00h for an unprotected sector group and 01h for a protected sector group.

10. Device ID must be read across cycles 4, 5, and 6. PL129J (X0Eh = 2221h, X0Fh = 2200h).

11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode.

Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address.

12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address.

13. Command is valid when device is ready to read array data or when device is in autoselect mode.

14. WP#/ACC must be at V_IDduring the entire operation of command.

15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required

to return to the reading array.

Table 13. Sector Protection Command Definitions

Bus Cycles (Notes 1-4)

Command (Notes)

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset

1

3

4

XXX

555

F0

AA

Secured Silicon Sector Entry

Secured Silicon Sector Exit

2AA

55

555

88

90

XX

00

68

Secured Silicon Protection Bit Program

(Notes 5, 6)

RD

(0)

6

5

4

7

6

4

555

AA

2AA

55

555

60

38

C8

28

60

90

OW

48

OW

RD

(0)

Secured Silicon Protection Bit Status

Password Program (Notes 5, 7, 8)

Password Verify (Notes 6, 8, 9)

Password Unlock (Notes 7, 10, 11)

PPB Program (Notes 5, 6, 12)

PPB Status

OW

XX

48

PD

[0-3] [0-3]

PWA PWD

[0-3] [0-3]

PWA PWD PWA PWD PWA PWD PWA PWD

[0]

[1]

[2]

[3]

(SA)

WP

(SA)

WP

(SA)

WP

RD

(0)

68

48

(SA)

WP

RD

(0)

(SA)

WP

RD

(0)

All PPB Erase (Notes 5, 6, 13, 14)

PPB Lock Bit Set

6

3

4

555

AA

2AA

55

555

60

78

58

WP

60

(SA)

40

RD

(1)

PPB Lock Bit Status (Note 15)

SA

DYB Write (Note 7)

DYB Erase (Note 7)

4

555

AA

2AA

55

555

48

SA

X1

X0

RD

(0)

DYB Status (Note 6)

4

6

5

6

5

555

AA

2AA

55

555

58

60

SA

PL

SL

RD

(0)

PPMLB Program (Notes 5, 6, 12)

PPMLB Status (Note 5)

68

48

68

48

PL

SL

48

PL

SL

RD

(0)

RD

(0)

SPMLB Program (Notes 5, 6, 12)

SPMLB Status (Note 5)

48

RD

(0)

Legend:

DYB = Dynamic Protection Bit

OW = Address (A7:A0) is (00011010)

PD[3:0] = Password Data (1 of 4 portions)

PPB = Persistent Protection Bit

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A d v a n c e I n f o r m a t i o n

PWA = Password Address. A1:A0 selects portion of password.

PWD = Password Data being verified.

PL = Password Protection Mode Lock Address (A7:A0) is (00001010)

RD(0) = Read Data DQ0 for protection indicator bit.

RD(1) = Read Data DQ1 for PPB Lock status.

SA = Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)

WP = PPB Address (A7:A0) is (00000010)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles are write operations.

4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than

A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.

5. The reset command returns device to reading array.

6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 =

0 in cycle 6, program command must be issued and verified again.

7. Data is latched on the rising edge of WE#.

8. Entire command sequence must be entered for each portion of password.

9. Command sequence returns FFh if PPMLB is set.

10. The password is written over four consecutive cycles, at addresses 0-3.

11. A 2 µs timeout is required between any two portions of password.

12. A 100 µs timeout is required between cycles 4 and 5.

13. A 1.2 ms timeout is required between cycles 4 and 5.

14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase

command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB

overerasure.

15. DQ1 = 1 if PPB locked, 0 if unlocked.

Write Operation Status

The device provides several bits to determine the status of a program or erase opera-

tion: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 14 and the following subsections describe

the function of these bits. DQ7 and DQ6 each offer a method for determining whether

a program or erase operation is complete or in progress. The device also provides a

hardware-based output signal, RY/BY#, to determine whether an Embedded Program

or Erase operation is in progress or has been completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Pro-

gram or Erase algorithm is in progress or completed, or whether a bank is in Erase

Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the com-

mand sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the complement

of the datum programmed to DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is complete, the device out-

puts the datum programmed to DQ7. The system must provide the program address

to read valid status information on DQ7. If a program address falls within a protected

sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns

to the read mode.

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During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.

When the Embedded Erase algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide

an address within any of the sectors selected for erasure to read valid status in-

formation on DQ7.

After an erase command sequence is written, if all sectors selected for erasing

are protected, Data# Polling on DQ7 is active for approximately 400 µs, then the

bank returns to the read mode. If not all selected sectors are protected, the Em-

bedded Erase algorithm erases the unprotected sectors, and ignores the selected

sectors that are protected. However, if the system reads DQ7 at an address within

a protected sector, the status may not be valid.

When the system detects DQ7 has changed from the complement to true data,

it can read valid data at DQ15–DQ0 on the following read cycles. Just prior to the

completion of an Embedded Program or Erase operation, DQ7 may change asyn-

chronously with DQ15–DQ0 while Output Enable (OE#) is asserted low. That is,

the device may change from providing status information to valid data on DQ7.

Depending on when the system samples the DQ7 output, it may read the status

or valid data. Even if the device has completed the program or erase operation

and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid

data on DQ15–DQ0 appears on successive read cycles.

Table 14 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling

algorithm. Figure 18 in AC Characteristics shows the Data# Polling timing

diagram.

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A d v a n c e I n f o r m a t i o n

START

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid address is

any sector address within the sector being erased. During chip erase, a valid address is

any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously

with DQ5.

Figure 6. Data# Polling Algorithm

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an

Embedded Algorithm is in progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command sequence. Since RY/BY#

is an open-drain output, several RY/BY# pins can be tied together in parallel with

a pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively erasing or programming. (This

includes programming in the Erase Suspend mode.) If the output is high (Ready),

the device is in the read mode, the standby mode, or one of the banks is in the

erase-suspend-read mode.

Table 14 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm

is in progress or complete, or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is valid after the rising edge

of the final WE# pulse in the command sequence (prior to the program or erase

operation), and during the sector erase time-out.

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During an Embedded Program or Erase algorithm operation, successive read cy-

cles to any address cause DQ6 to toggle. The system may use either OE# or CE#

to control the read cycles. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing

are protected, DQ6 toggles for approximately 400 µs, then returns to reading

array data. If not all selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the selected sectors that are

protected.

The system can use DQ6 and DQ2 together to determine whether a sector is ac-

tively erasing or is erase-suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-

ters the Erase Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-

natively, the system can use DQ7 (see “DQ7: Data# Polling” on page 56).

If a program address falls within a protected sector, DQ6 toggles for approxi-

mately 1 µs after the program command sequence is written, then returns to

reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling

once the Embedded Program algorithm is complete.

Table 14 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit

algorithm. Figure 19 in “Read Operation Timings” shows the toggle bit timing di-

agrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical

form. See also “DQ2: Toggle Bit II”.

START

Read Byte

(DQ7–DQ0)

Address =VA

Read Byte

(DQ7–DQ0)

Address =VA

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

Read Byte Twice

(DQ7–DQ0)

Address = VA

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Figure 7. Toggle Bit Algorithm

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A d v a n c e I n f o r m a t i o n

Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle

bit may stop toggling as DQ5 changes to “1.” See “DQ6: Toggle Bit I” and “DQ2: Tog-

gle Bit II” for more information.

Figure 7. Toggle Bit Algorithm

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular

sector is actively erasing (that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit II is valid after the rising

edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have

been selected for erasure. (The system may use either OE# or CE1# / CE2# to

control the read cycles.) But DQ2 cannot distinguish whether the sector is actively

erasing or is erase-suspended. DQ6, by comparison, indicates whether the device

is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors

are selected for erasure. Thus, both status bits are required for sector and mode

information. See Table 14 to compare outputs for DQ2 and DQ6.

Figure 7 shows the toggle bit algorithm in flowchart form, and the “DQ2: Toggle

Bit II” explains the algorithm. See also “DQ6: Toggle Bit I.” Figure 19 shows the

toggle bit timing diagram. Figure 20 shows the differences between DQ2 and DQ6

in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 7 for the following discussion. Whenever the system initially be-

gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the system would note and

store the value of the toggle bit after the first read. After the second read, the

system would compare the new value of the toggle bit with the first. If the toggle

bit is not toggling, the device has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle

bit is still toggling, the system also should note whether the value of DQ5 is high

(see “DQ5: Exceeded Timing Limits”). If it is, the system should then determine

again whether the toggle bit is toggling, since the toggle bit may have stopped

toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase operation. If it is still toggling,

the device did not completed the operation successfully, and the system must

write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit

is toggling and DQ5 has not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, determining the status as de-

scribed in the previous paragraph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the beginning of the algo-

rithm when it returns to determine the status of the operation (top of Figure 7).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified inter-

nal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the

program or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries to program a “1” to a

location that was previously programmed to “0.” Only an erase operation can

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A d v a n c e I n f o r m a t i o n

change a “0” back to a “1.” Under this condition, the device halts the opera-

tion, and when the timing limit has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write the reset command to return

to the read mode (or to the erase-suspend-read mode if a bank was previously

in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to de-

termine whether or not erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional sectors are selected for erasure,

the entire time-out also applies after each additional sector erase command.

When the time-out period is complete, DQ3 switches from a “0” to a “1.” See also

“Sector Erase Command Sequence” on page 49.

After the sector erase command is written, the system should read the status of

DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase

algorithm has begun; all further commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the device accepts additional

sector erase commands. To ensure the command has been accepted, the system

software should check the status of DQ3 prior to and following each subsequent

sector erase command. If DQ3 is high on the second status check, the last com-

mand might not have been accepted.

Table 14 shows the status of DQ3 relative to the other status bits.

Table 14. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase-Suspend-

Read

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing

limits.“DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for

further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded

Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.

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A d v a n c e I n f o r m a t i o n

Absolute Maximum Ratings

Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

V_CC(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . .–0.5 V to +13.0 V

WP#/ACC (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions,

input or I/O pins may overshoot V to –2.0 V for periods of up to 20 ns. Maximum

SS

DC voltage on input or I/O pins is V +0.5 V. During voltage transitions, input or

CC

I/O pins may overshoot to V +2.0 V for periods up to 20 ns. See Figure 8.

CC

2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V.

During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot V

SS

to –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on

pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods

up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may

overshoot to +12.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the

short circuit should not be greater than one second.

4. Stresses above those listed under “Absolute Maximum Ratings” may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this data sheet is not implied. Exposure of the device to absolute max-

imum rating conditions for extended periods may affect device reliability.

20 ns

V_CC

+2.0 V

+0.8 V

V_CC

–0.5 V

–2.0 V

+0.5 V

2.0 V

20 ns

Maximum Negative Overshoot Waveform

Maximum Positive Overshoot Waveform

Figure 8. Maximum Overshoot Waveforms

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Operating Ranges

Operating ranges define those limits between which the functionality of the de-

vice is guaranteed.

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T_A) . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Supply Voltages

V_CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7–3.6 V

V_IOor 2.7–3.6 V

Notes:

For all AC and DC specifications, V = V ; contact your local sales office for other

IO

CC

V

options.

IO

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

63

A d v a n c e I n f o r m a t i o n

DC Characteristics

Table 15. CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

Min

Typ

Max

Unit

V_IN= V_SSto V_CC

,

I_LI

Input Load Current

±1.0

µA

V_CC= V_{CC max}

I_LIT

I_LR

A9, OE#, RESET# Input Load Current

Reset Leakage Current

V_CC= V_{CC max}; V_ID= 12.5 V

35

µA

V_OUT= V_SSto V_CC, OE# = V_IH

V_CC= V_{CC max}

I_LO

Output Leakage Current

±1.0

µA

5 MHz

20

45

15

30

55

25

OE# = V_IH, V_CC= V_{CC max}

(Note 1)

I_CC1

V_CCActive Read Current (Notes 1, 2)

mA

10 MHz

I_CC2

I_CC3

I_CC4

I_CC5

V_CCActive Write Current (Notes 2, 3)

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

OE# = V_IH, WE# = V_IL

mA

µA

CE#, RESET#, WP#/ACC

= V_IO± 0.3 V

0.2

5

RESET# = V_SS± 0.3 V

V_IH= V_IO± 0.3 V;

V_IL= V_SS± 0.3 V

Automatic Sleep Mode (Notes 2, 4)

5 MHz

10 MHz

5 MHz

21

46

21

46

45

70

45

70

V_CCActive Read-While-Program Current

(Notes 1, 2)

I_CC6

OE# = V_IH

,

mA

V_CCActive Read-While-Erase Current

(Notes 1, 2)

I_CC7

OE# = V_IH

mA

10 MHz

V_CCActive Program-While-Erase-

Suspended Current (Notes 2, 5)

I_CC8

17

10

25

I_CC9

V_IL

V_CCActive Page Read Current (Note 2)

Input Low Voltage

OE# = V_IH, 8 word Page Read

V_IO= 2.7–3.6 V

15

0.8

mA

V

–0.5

2.0

V_IH

V_HH

Input High Voltage

V_IO= 2.7–3.6 V

V_CC+0.3

9.5

V

Voltage for ACC Program Acceleration

V_CC= 3.0 V ± 10%

8.5

V

Voltage for Autoselect and Temporary

Sector Unprotect

V_ID

V_OL

V_CC= 3.0 V ± 10%

11.5

12.5

0.4

V

Output Low Voltage

I_OL= 2.0 mA, V_CC= V_{CC min}, V_IO= 2.7–3.6

V

I_OH= –2.0 mA, V_CC= V_{CC min}, V_IO= 2.7–3.6

V

V_OH

Output High Voltage

2.4

2.3

V

V_LKO

Low V_CCLock-Out Voltage (Note 5)

2.5

Notes:

1. The I current listed is typically less than 5 mA/MHz, with OE# at V

.

IH

CC

2. Maximum I specifications are tested with V = V .

CCmax

CC

3. I active while Embedded Erase or Embedded Program is in progress.

CC

4. Automatic sleep mode enables the low power mode when addresses remain stable for t

+ 30 ns. Typical sleep

ACC

mode current is 1 mA.

5. Not 100% tested.

6. In S29PL129J there are two CE# (CE1#, CE2#).

7. Valid CE1#/CE2# conditions: (CE1# = V CE2# = V ) or (CE1# = V CE2# = V ) or (CE1# = V CE2# = V )

IH

IL,

IH,

IL

IH,

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S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

AC Characteristics

Test Conditions

3.6 V

2.7 kΩ

Device

Under

Test

C

6.2 kΩ

L

V_IO= 3.0 V

Note: Diodes are IN3064 or equivalent

Figure 9. Test Setups

Table 16. Test Specifications

Test Condition

All Speeds

1 TTL gate

30

Unit

Output Load

Output Load Capacitance, C_L(including jig capacitance)

Input Rise and Fall Times

pF

ns

V

V_IO= 3.0 V

5

Input Pulse Levels

0.0–3.0

V_IO/2

Input timing measurement reference levels

Output timing measurement reference levels

V

V_IO/2

V

Switching Waveforms

Table 17. Key to Switching Waveforms

Waveform

Inputs

Outputs

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

65

A d v a n c e I n f o r m a t i o n

VIO

VIO/2

In

Measurement Level

Output

0.0 V

Figure 10. Input Waveforms and Measurement Levels

VCC RampRate

All DC characteristics are specified for a V_CCramp rate > 1V/100 µs and V_CC

>=V_CCQ- 100 mV. If the V_CCramp rate is < 1V/100 µs, a hardware reset

required.+

Read Operations

Table 18. Read-Only Operations

Parameter

JEDEC Std. Description

Speed Options

Test Setup

55

20

60

25

65

25

70

30

Unit

ns

t_AVAV

t_AVQV

t_ELQV

t_RC

Read Cycle Time (Note 1)

Min

t_ACCAddress to Output Delay

CE#, OE# = V_IL

OE# = V_IL

Max

ns

t_CE

t_PACCPage Access Time

t_OEOutput Enable to Output Delay

t_DF

Chip Enable to Output Delay

ns

t_GLQV

t_EHQZ

30

ns

Chip Enable to Output High Z (Note 3)

16

ns

Output Enable to Output High Z

(Notes 1, 3)

t_GHQZ

t_DF

Max

ns

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 3)

t_AXQX

t_OH

Min

5

0

ns

Read

Output Enable Hold

Time (Note 1)

t_OEH

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 9 and Table 16 for test specifications

3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V /2. The time from OE#

CC

high to the data bus driven to V /2 is taken as t

.

CC

DF

4. S29PL129J has two CE# (CE1#, CE2#).

5. Valid CE1# / CE2# conditions: (CE1# = V ,CE2# = V ) or (CE1# = V ,CE2# = V ) or (CE1# = V CE2# = V )

IH

IL

IH

IL

IH,

6. Valid CE1# / CE2# transitions: (CE1# = V ,CE2# = V ) or (CE1# = V ,CE2# = V ) to (CE1# = CE2# = V

)

IL

IH

IL

IH

7. Valid CE1# / CE2# transitions: (CE1# = CE2# = V ) to (CE1# = V ,CE2# = V ) or (CE1# = V ,CE2# = V

IL

IH

IL

IH

8. For 70pF Output Load Capacitance, 2 ns is added to the above t

,t ,t

,t values for all speed grades

ACC CE PACC OE

66

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

Data

t_CE

t_OH

HIGH Z

Valid Data

RESET#

RY/BY#

0 V

Notes:

1. S29PL129J - During CE1# transitions, CE2# = V ; During CE2# transitions, CE1# = V

IH

2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 11. Read Operation Timings

Same Page

Amax

A2

-

A3

A0

Ad

Aa

t_ACC

Ab

t_PACC

Ac

t_PACC

Data

Qa

Qb

Qc

Qd

CE#

OE#

Notes:

1. S29PL129J - During CE1# transitions, CE2# = V ; During CE2# transitions, CE1# = V

IH

2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 12. Page Read Operation Timings

June 4, 2004 S29PL129J_MCP_00_A0

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67

A d v a n c e I n f o r m a t i o n

Reset

Table 19. Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Notes:

1. S29PL129J - During CE1# transitions, CE2# = V ; During CE2# transitions, CE1# = V

IH

2. S29PL129J - There are two CE# (CE1#, CE2#). In the below waveform CE# = CE1# or CE2#

Figure 13. Reset Timings

68

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

Erase/Program Operations

Table 20. Erase and Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

t_AVWL

Std

t_WC

t_AS

Description

55

60

65

70

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Min

55

60

65

70

0

ns

Address Setup Time to OE# low during toggle bit

polling

t_ASO

t_AH

Min

15

ns

t_WLAX

Address Hold Time

30

25

35

30

Address Hold Time From CE1#, CE#2 or OE# high

during toggle bit polling

t_AHT

0

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

ns

Data Hold Time

0

t_OEPH

Output Enable High during toggle bit polling

10

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE1# or CE#2 Setup Time

CE1# or CE#2 Hold Time

Write Pulse Width

Min

Typ

Min

Max

Min

0

ns

µs

sec

µs

ns

t_WP

35

t_WPH

t_SR/W

Write Pulse Width High

20

25

Latency Between Read and Write Operations

0

6

t_WHWH1

t_WHWH2

t_WHWH1Programming Operation (Note 4)

t_WHWH1Accelerated Programming Operation (Note 4)

t_WHWH2Sector Erase Operation (Note 4)

4

0.5

50

0

t_VCS

t_RB

V_CCSetup Time (Note 1)

Write Recovery Time from RY/BY#

90

35

t_BUSY

Program/Erase Valid to RY/BY# Delay

Notes:

1. Not 100% tested.

2. S29PL129J - During CE1# transitions, CE2# = V ; During CE2# transitions, CE1# = V

IH

3. S29PL129J - There are two CE# (CE1#, CE2#).

4. See Table 25, “Erase And Programming Performance,” on page 78 for more information.

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

69

A d v a n c e I n f o r m a t i o n

Timing Diagrams

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

555h

Addresses

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D

is the true data at the program address

OUT

2. S29PL129J - During CE1# transitions, CE2# = V ; During CE2# transitions, CE1# = V

IH

3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 14. Program Operation Timings

V_HH

V_ILor V_IH

WP#/ACC

V_ILor V_IH

t_VHH

Figure 15. Accelerated Program Timing Diagram

70

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

Data

Status

D

OUT

55h

30h

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status” on

page 56

2. S29PL129J - During CE1# transitions, CE2# = V ; During CE2# transitions, CE1# = V

IH

3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 16. Chip/Sector Erase Operation Timings

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

71

A d v a n c e I n f o r m a t i o n

t_WC

t_RC

t_WC

Valid PA

t_AH

Valid RA

Valid PA

Addresses

t_AS

t_CPH

t_AS

t_AH

t_ACC

t_CE

CE#

OE#

t_CP

t_OE

t_OEH

t_GHWL

t_WP

WE#

Data

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

Figure 17. Back-to-back Read/Write Cycle Timings

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ6–DQ0

Status Data

True

Valid Data

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array

data read cycle

Figure 18. Data# Polling Timings (During Embedded Algorithms)

72

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

t_AHT

t_AS

Addresses

CE#

t_AHT

t_ASO

t_CEPH

t_OEH

WE#

OE#

t_OEPH

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Notes:

1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last

status read cycle, and array data read cycle

2. S29PL129J - During CE1# transitions, CE2# = V ; During CE2# transitions, CE1# = V

IH

3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 19. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note:Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or

CE# to toggle DQ2 and DQ6.

Figure 20. DQ2 vs. DQ6

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

73

A d v a n c e I n f o r m a t i o n

Protect/Unprotect

Table 21. Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

250

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_ILor V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 21. Temporary Sector Unprotect Timing Diagram

74

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

V

ID

IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector Group Protect/Unprotect

Verify

40h

Data

60h

1 µs

Sector Group Protect: 150 µs

Sector Group Unprotect: 15 ms

CE#

WE#

OE#

Notes:

1. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

2. S29PL129J - During CE1# transitions, CE2# = V ; During CE2# transitions, CE1# = V

IH

3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram

June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

75

A d v a n c e I n f o r m a t i o n

Controlled Erase Operations

Table 22. Alternate CE# Controlled Erase and Program Operations

Parameter

JEDEC

Speed Options

Std

t_WC

t_AS

t_AH

t_DS

t_DH

Description

55

60

65

70

Unit

ns

t_AVAV

t_AVWL

t_ELAX

t_DVEH

t_EHDX

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

55

60

65

70

0

ns

30

25

35

30

ns

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

ns

t_WLEL

t_EHWH

t_ELEH

t_WS

t_WH

WE# Setup Time

Min

Typ

0

ns

µs

sec

WE# Hold Time

t_CP

CE1# or CE#2 Pulse Width

CE1# or CE#2 Pulse Width High

Programming Operation (Note 2)

Accelerated Programming Operation (Note 2)

Sector Erase Operation (Note 2)

35

20

40

25

t_EHEL

t_CPH

t_WHWH1

t_WHWH2

t_WHWH1

t_WHWH2

6

4

0.5

Notes:

1. Not 100% tested.

2. See the Table 25, “Erase And Programming Performance,” on page 78 for more information.

76

S29PL129J for MCP

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A d v a n c e I n f o r m a t i o n

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D

is the data written to the device

OUT

4. S29PL129J - During CE1# transitions, CE2# = V ; During CE2# transitions, CE1# = V

IH

5. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Table 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings

Table 24. CE1#/CE2# Timing

Parameter

JEDEC

Std

Description

CE1#/CE2# Recover Time

All Speed Options

Unit

t_CCR

Min

30

ns

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S29PL129J for MCP

77

A d v a n c e I n f o r m a t i o n

CE1#

CE2#

t_CCR

Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control

Table 25. Erase And Programming Performance

Parameter

Typ (Note 1)

Max (Note 2)

Unit

sec

Comments

0.5

2

Sector Erase Time

Chip Erase Time

Excludes 00h programming

prior to erasure (Note 4)

PL129J

135

216

sec

Excludes system level

overhead (Note 5)

6

4

100

60

µs

Word Program Time

Accelerated Word Program Time

Chip Program Time

(Note 3)

PL129J

50.4

200

sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 100,000 cycles. Additionally,

CC

programming typicals assume checkerboard pattern. All values are subject to change.

2. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles. All values are subject to change.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most

bytes program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program

command. See Table 12 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles.

BGA Pin Capacitance

Parameter Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

6.3

7.0

5.5

11

Max

7

Unit

pF

C_IN

C_OUT

C_IN2

C_IN3

Output Capacitance

V_OUT= 0

V_IN= 0

8

pF

Control Pin Capacitance

WP#/ACC Pin Capacitance

8

pF

V_IN= 0

12

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

78

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

A d v a n c e I n f o r m a t i o n

pSRAM Type 6

2M Word by 16-bit Cmos Pseudo Static RAM (32M Density)

4M Word by 16-bit Cmos Pseudo Static RAM (64M Density)

Features

Single power supply voltage of 2.6 to 3.3 V

Direct TTL compatibility for all inputs and outputs

Deep power-down mode: Memory cell data invalid

Page operation mode:

— Page read operation by 8 words

Logic compatible with SRAM R/W pin

Standby current

— Standby = 70 µA (32M)

— Standby = 100 µA (64M)

— Deep power-down Standby = 5 µA

Access Times

32M

64M

Access Time

70 ns

25 ns

30 ns

CE1# Access Time

OE# Access Time

Page Access Time

Pin Description

Pin Name

Description

A₀to A₂₁

A0 to A2

I/O1 to I/O16

CE1#

Address Inputs

Page Address Inputs

Data Inputs/Outputs

Chip Enable Input

Chip select Input

Write Enable Input

Output Enable Input

Data Byte Control Inputs

Power Supply

CE2

WE#

OE#

LB#,UB#

V_DD

GND

Ground

NC

Not Connection

Ocotober 16, 2004 pSRAM_Type06_14_A1

pSRAM Type 6

79

A d v a n c e I n f o r m a t i o n

Functional Description

Mode

Read (Word)

CE1#

CE2

H

OE#

L

WE#

LB#

L

UB# Address

I/O_1-8

D_OUT

I/O_9-16

D_OUT

Power

I_DDO

I_DDSD

L

H

L

H

L

X

Read (Lower Byte)

Read (Upper Byte)

Write (Word)

H

L

D_OUT

High-Z

D_OUT

H

L

H

L

High-Z

D_IN

H

X

L

D_IN

Write (Lower Byte)

Write (Upper Byte)

Outputs Disabled

Standby

H

X

L

H

L

D_IN

Invalid

D_IN

H

X

L

H

X

Invalid

High-Z

H

X

H

X

High-Z

H

X

Deep Power-down Standby

L

X

Legend:L = Low-level Input (V_IL), H = High-level Input (V_IH), X = V_ILor V_IH, High-Z = High Impedance.

Absolute Maximum Ratings

Symbol

V_DD

V_IN

Rating

Value

-1.0 to 3.6

-40 to 85

-55 to 150

0.6

Unit

V

Power Supply Voltage

Input Voltage

V

V_OUT

T_opr

Output Voltage

V

Operating Temperature

Storage Temperature

Power Dissipation

°C

W

T_strg

P_D

I_OUT

Short Circuit Output Current

50

mA

Note: ESD Immunity: Spansion Flash memory Multi-Chip Products (MCPs) may contain component devices that are

developed by Spansion and component devices that are developed by a third party (third-party components). Spansion

components are tested and guaranteed to the ESD immunity levels listed in the corresponding Spansion Flash memory

Qualification Database. Third-party components are neither tested nor guaranteed by Spansion for ESD immunity. How-

ever, ESD test results for third-party components may be available from the component manufacturer. Component man-

ufacturer contact information is listed in the Spansion MCP Qualification Report, when available. The Spansion Flash

memory Qualification Database and Spansion MCP Qualification Report are available from Spansion sales offices.

DC Recommended Operating Conditions (Ta = -40°C to 85°C)

Symbol

V_DD

Parameter

Min

2.6

Typ

2.75

—

Max

Unit

Power Supply Voltage

Input High Voltage

Input Low Voltage

3.3

V_DD+ 0.3 (Note)

0.4

V_IH

2.0

V

V_IL

-0.3 (Note)

—

Note: V (Max) V

= 1.0 V with 10 ns pulse width. V (Min) -1.0 V with 10 ns pulse width.

IL

IH

DD

80

pSRAM Type 6

pSRAM_Type06_14_A1 Ocotober 16, 2004

A d v a n c e I n f o r m a t i o n

DC Characteristics (Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 3 to 4)

Symbol

Parameter

Test Condition

Min

Typ.

Max

Unit

Input Leakage

Current

I_IL

V_IN= 0 V to V_DD

-1.0

—

+1.0

µA

Output Leakage

Current

I_LO

Output disable, V_OUT= 0 V to V_DD

-1.0

—

+1.0

µA

V_OH

V_OL

Output High Voltage

Output Low Voltage

I_OH= - 0.5 mA

I_OL= 1.0 mA

2.0

—

¾

—

V

0.4

40

50

ET5UZ8A-43DS

ET5VB5A-43DS

—

CE1#= V_IL, CE2 = V_IH, I_OUT= 0

mA, t_RC= min.

I_DDO1Operating Current

mA

—

Page Access

I_DDO2

CE1#= V_IL, CE2 = V_IH, I_OUT= 0 mA

Page add. cycling, t_RC= min.

—

25

Operating Current

ET5UZ8A-43DS

ET5VB5A-43DS

—

70

mA

µA

Standby Current

(MOS)

CE1# = V_DD- 0.2 V,

CE2 = V_DD- 0.2 V

I_DDS

100

Deep Power-down

I_DDSD

CE2 = 0.2 V

—

5

µA

Standby Current

Capacitance (Ta = 25°C, f = 1 MHz)

Symbol

C_IN

Parameter

Test Condition

Max

10

Unit

Input Capacitance

Output Capacitance

V_IN= GND

pF

C_OUT

V_OUT= GND

10

Note: This parameter is sampled periodically and is not 100% tested.

AC Characteristics and Operating Conditions

(Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 5 to 11)

Symbol

t_RC

t_ACC

t_CO

Parameter

Min

Max

Unit

ns

Read Cycle Time

70

—

10

0

10000

70

25

—

Address Access Time

Chip Enable (CE1#) Access Time

Output Enable Access Time

t_OE

t_BA

Data Byte Control Access Time

t_COE

t_OEE

t_BE

Chip Enable Low to Output Active

Output Enable Low to Output Active

Data Byte Control Low to Output Active

Chip Enable High to Output High-Z

Output Enable High to Output High-Z

Data Byte Control High to Output High-Z

—

0

—

t_OD

t_ODO

t_BD

—

20

Ocotober 16, 2004 pSRAM_Type06_14_A1

pSRAM Type 6

81

A d v a n c e I n f o r m a t i o n

Symbol

t_OH

Parameter

Min

10

70

30

—

Max

—

Unit

ns

µs

ms

ns

µs

Output Data Hold Time

Page Mode Time

t_PM

10000

—

t_PC

Page Mode Cycle Time

Page Mode Address Access Time

t_AA

30

t_AOH

t_WC

t_WP

t_CW

t_BW

t_AW

t_AS

Page Mode Output Data Hold Time

Write Cycle Time

10

70

50

70

60

0

—

10000

—

Write Pulse Width

Chip Enable to End of Write

Data Byte Control to End of Write

Address Valid to End of Write

Address Set-up Time

—

t_WR

t_CEH

t_WEH

t_ODW

t_OEW

t_DS

Write Recovery Time

0

—

Chip Enable High Pulse Width

Write Enable High Pulse Width

WE# Low to Output High-Z

WE# High to Output Active

Data Set-up Time

10

6

—

20

0

30

0

—

t_DH

Data Hold Time

t_CS

CE2 Set-up Time

0

t_CH

CE2 Hold Time

300

10

0

t_DPD

t_CHC

t_CHP

CE2 Pulse Width

CE2 Hold from CE1#

CE2 Hold from Power On

30

AC Test Conditions

Parameter

Output load

Condition

30 pF + 1 TTL Gate

V_DD- 0.2 V, 0.2 V

V_DDx 0.5

Input pulse level

Timing measurements

Reference level

t_R, t_F

V_DDx 0.5

5 ns

82

pSRAM Type 6

pSRAM_Type06_14_A1 Ocotober 16, 2004

A d v a n c e I n f o r m a t i o n

Timing Diagrams

Read Timings

t

RC

Address

A0 to A20(32M)

A0 to A21(64M)

t

ACC

OH

t

CO

CE1#

Fix-H

CE2

OE#

WE#

t

OD

OE

t

ODO

t

BA

,

UB# LB#

t

BE

t

BD

t

OEE

D

OUT

Hi-Z

VALID DATA OUT

Hi-Z

t

COE

I/O1 to I/O16

INDETERMINATE

Figure 24. Read Cycle

Ocotober 16, 2004 pSRAM_Type06_14_A1

pSRAM Type 6

83

A d v a n c e I n f o r m a t i o n

t

PM

Address

A0 to A2

t

PC

RC

Address

A3 to A20(32M)

A3 to A21(64M)

CE1#

Fix-H

CE2

OE#

WE#

UB#, LB#

t

OD

OE

t

BD

t

BA

t

AOH

t

OEE

OH

t

BE

D

OUT

D

OUT

D

OUT

D

OUT

D

OUT

Hi-Z

I/O1 to I/O16

t

COE

t

ODO

CO

AA

* Maximum 8 words

t

ACC

Figure 25. Page Read Cycle (8 Words Access)

84

pSRAM Type 6

pSRAM_Type06_14_A1 Ocotober 16, 2004

A d v a n c e I n f o r m a t i o n

Write Timings

t

WC

Address

A0 to A20(32M)

A0 to A21(64M)

t

WEH

AW

t

AS

WP

WR

WE#

t

CW

WR

CE1#

t

CH

CE2

t

BW

WR

UB#, LB#

t

OEW

ODW

D

OUT

(See Note 10)

Hi-Z

(See Note 11)

I/O1 to I/O16

t

DH

DS

D

IN

(See Note 9)

VALID DATA IN

(See Note 9)

I/O1 to I/O16

Figure 26. Write Cycle #1 (WE# Controlled) (See Note 8)

Ocotober 16, 2004 pSRAM_Type06_14_A1

pSRAM Type 6

85

A d v a n c e I n f o r m a t i o n

t

WC

Address

A0 to A20(32M)

A0 to A21(64M)

t

AW

t

AS

WP

WR

WE#

t

CEH

t

CW

WR

CE1#

CE2

t

CH

t

BW

WR

UB#, LB#

t

ODW

BE

D

OUT

Hi-Z

I/O1 to I/O16

t

COE

t

DH

DS

D

IN

(See Note 9)

VALID DATA IN

I/O1 to I/O16

Figure 27. Write Cycle #2 (CE# Controlled) (See Note 8)

Deep Power-down Timing

CE1#

t

DPD

CE2

t

CH

CS

Figure 28. Deep Power Down Timing

Power-on Timing

V

min

DD

V

DD

CE1#

CE2

t

CHC

t

CH

t

CHP

Figure 29. Power-on Timing

86

pSRAM Type 6

pSRAM_Type06_14_A1 Ocotober 16, 2004

A d v a n c e I n f o r m a t i o n

Provisions of Address Skew

Read

In case multiple invalid address cycles shorter than t_RCmin. sustain over 10 µs

in an active status, at least one valid address cycle over t_RCmin. is required dur-

ing 10µs.

over 10µs

CE1#

WE#

Address

t min

RC

Figure 30. Read

Write

In case multiple invalid address cycles shorter than t_WCmin. sustain over 10 µs

in an active status, at least one valid address cycle over t_WCmin. is required dur-

ing 10 µs.

CE1#

WE#

t min

WP

Address

t min

WC

Figure 31. Write

Notes:

1. Stresses greater than listed under "Absolute Maximum Ratings" section may cause permanent damage to the device.

2. All voltages are reference to GND.

3. I_DDOdepends on the cycle time.

4.

I_DDOdepends on output loading. Specified values are defined with the output open condition.

5. AC measurements are assumed t_R, t_F= 5 ns.

6. Parameters t_OD, t_ODO, t_BDand t_ODW define the time at which the output goes the open condition and are not output voltage

reference levels.

7. Data cannot be retained at deep power-down stand-by mode.

8. If OE# is high during the write cycle, the outputs will remain at high impedance.

9. During the output state of I/O signals, input signals of reverse polarity must not be applied.

10. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance.

11. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance.

Ocotober 16, 2004 pSRAM_Type06_14_A1

pSRAM Type 6

87

A d v a n c e I n f o r m a t i o n

pSRAM Type 1

4Mbit (256K Word x 16-bit)

8Mbit (512K Word x 16-bit)

16Mbit (1M Word x 16-bit)

32Mbit (2M Word x 16-bit)

64Mbit (4M Word x 16-bit)

Functional Description

Mode

CE#

CE2/ZZ#

OE#

L

WE# UB#

LB#

L

Addresses

I/O 1-8

Dout

I/O 9-16

Dout

Power

I_ACTIVE

Read (word)

L

H

L

H

L

H

L

X

Read (lower byte)

Read (upper byte)

Write (word)

L

Dout

High-Z

Dout

I_ACTIVE

L

H

L

High-Z

Din

I_ACTIVE

L

X

L

Din

I_ACTIVE

Write (lower byte)

Write (upper byte)

Outputs disabled

Standby

L

X

L

H

L

Din

Invalid

Din

I_ACTIVE

L

X

L

H

X

Invalid

High-Z

I_ACTIVE

L

H

X

H

X

High-Z

I_ACTIVE

H

X

I_STANDBY

I_{DEEP SLEEP}

Deep power down

X

Absolute Maximum Ratings

Item

Voltage on any pin relative to V_SS

Voltage on V_CCrelative to V_SS

Power dissipation

Symbol

Vin, Vout

V_CC

Ratings

Units

V

-0.2 to V_CC+0.3

-0.2 to 3.6

1

V

P_D

W

Storage temperature

T_STG

-55 to 150

-25 to 85

°C

Operating temperature

T_A

88

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

DC Characteristics

(4Mb pSRAM Asynchronous)

Asynchronous

-70

Performance Grade

Density

4Mb pSRAM

Max

Symbol

V_CC

Parameter

Power Supply

Conditions

Min

2.7

Units

3.3

V

V_IH

Input High Level

Input Low Level

0.8 Vccq

-0.3

V_CC+ 0.3

0.4

V_IL

Input Leakage

Current

I_IL

Vin = 0 to V_CC

0.5

µA

Output Leakage

Current

OE = V_IHor

Chip Disabled

I_LO

I_OH= -1.0 mA

Output High

Voltage

V_OH

I

_OH= -0.2 mA

0.8 Vccq

V

I_OH= -0.5 mA

I_OL= 2.0 mA

I_OL= 0.2 mA

I_OL= 0.5 mA

Output Low

Voltage

V_OL

0.2

Operating

Current

I_ACTIVE

V_CC= 3.3 V

25

70

mA

µA

V

_CC= 3.0 V

I_STANDBYStandby Current

V_CC= 3.3 V

I_DEEP

SLEEP

Deep Power

x

µA

Down Current

1/4 Array PAR

Current

I_{PAR 1/4}

1/2 Array PAR

Current

I_{PAR 1/2}

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

89

A d v a n c e I n f o r m a t i o n

DC Characteristics

(8Mb pSRAM Asynchronous)

Asynchronous

B

Version

Performance Grade

Density

C

-70

-55

8Mb pSRAM

Max

-70

8Mb pSRAM

Max

8Mb pSRAM

Max

Symbol

V_CC

Parameter

Conditions

Min

2.7

Units

Min

2.7

Units

Min

2.7

Units

Power Supply

3.3

V

3.6

V

3.3

V

V_IH

Input High Level

Input Low Level

2.2

V_CC+ 0.3

0.6

2.2

V_CC+ 0.3

0.6

0.8

V_CC+0.3

0.4

V_IL

-0.3

Input Leakage

Current

I_IL

Vin = 0 to V_CC

0.5

µA

0.5

µA

0.5

µA

Output Leakage

Current

OE = V_IHor

Chip Disabled

I_LO

I

_OH= -1.0 mA V_CC-0.4

V_CC-0.4

V_OH

Output High Voltage I_OH= -0.2 mA

I_OH= -0.5 mA

V

0.8 V_CCQ

V

I

_OL= 2.0 mA

Output Low Voltage I_OL= 0.2 mA

_OL= 0.5 mA

0.4

V_OL

0.2

I

I_ACTIVEOperating Current

V_CC= 3.3 V

V_CC= 3.0 V

25

60

mA

µA

23

60

mA

µA

25

70

mA

µA

I_STANDBYStandby Current

V

_CC= 3.3 V

I_DEEP

SLEEP

Deep Power Down

Current

x

µA

x

µA

x

µA

1/4 Array PAR

Current

I_{PAR 1/4}

1/2 Array PAR

Current

I_{PAR 1/2}

90

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

DC Characteristics

(16Mb pSRAM Asynchronous)

Asynchronous

Performance Grade

Density

-55

16Mb pSRAM

-70

16Mb pSRAM

Symbol

V_CC

V_IH

Parameter

Power Supply

Conditions

Minimum Maximum

Units

V

Minimum Maximum Units

2.7

2.2

3.6

V_CC+ 0.3

0.6

2.7

2.2

3.6

V_CC+ 0.3

0.6

V

Input High Level

V

V_IL

Input Low Level

-0.3

V

-0.3

V

I_IL

Input Leakage Current

Output Leakage Current

Vin = 0 to V_CC

OE = V_IHor Chip Disabled

I_OH= -1.0 mA

0.5

µA

0.5

µA

I_LO

0.5

V_CC-0.4

V_OH

Output High Voltage

Output Low Voltage

I_OH= -0.2 mA

V

I_OH= -0.5 mA

I_OL= 2.0 mA

0.4

V_OL

I_OL= 0.2 mA

I_OL= 0.5 mA

V_CC= 3.3 V

I_ACTIVE

Operating Current

Standby Current

25

mA

µA

25

mA

µA

V

_CC= 3.0 V

100

I_STANDBY

V_CC= 3.3 V

I_{DEEP SLEEP}Deep Power Down Current

x

µA

x

µA

I_{PAR 1/4}

I_{PAR 1/2}

1/4 Array PAR Current

1/2 Array PAR Current

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

91

A d v a n c e I n f o r m a t i o n

DC Characteristics

(16Mb pSRAM Page Mode)

Page Mode

Performance Grade

Density

-60

16Mb pSRAM

Max

-65

16Mb pSRAM

Max

-70

16Mb pSRAM

Max

Symbol

Parameter

Conditions

Min

Units

Min

Units

Min

Units

V_CC

Power Supply

2.7

3.3

V

2.7

3.3

V

2.7

3.3

V

Input High

Level

V_IH

V_IL

I_IL

0.8 Vccq V_CC+ 0.2

V

0.8 Vccq V_CC+ 0.2

V

0.8 Vccq

-0.2

V_CC+ 0.2

0.2 Vccq

1

V

Input Low

Level

-0.2

0.2 Vccq

1

-0.2

0.2 Vccq

1

Input Leakage

Current

Vin = 0 to V_CC

µA

Output

Leakage

Current

OE = V_IHor

I_LO

1

µA

V

1

µA

V

1

µA

V

Chip Disabled

I_OH= -1.0 mA

I_OH= -0.2 mA

Output High

Voltage

V_OH

I_OH= -0.5 mA 0.8 Vccq

I_OL= 2.0 mA

0.8 Vccq

Output Low

Voltage

V_OL

I_OL= 0.2 mA

V

I_OL= 0.5 mA

0.2 Vccq

25

0.2 Vccq

25

0.2 Vccq

25

Operating

Current

I_ACTIVE

V_CC= 3.3 V

mA

µA

mA

µA

mA

µA

V

_CC= 3.0 V

Standby

Current

I_STANDBY

V_CC= 3.3 V

100

10

100

10

100

10

I_DEEP

SLEEP

Deep Power

µA

Down Current

1/4 Array PAR

Current

I_{PAR 1/4}

65

80

65

80

65

80

1/2 Array PAR

Current

I_{PAR 1/2}

92

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

DC Characteristics

(32Mb pSRAM Page Mode)

Page Mode

Version

C

-65

E

Performance Grade

Density

-60

32Mb pSRAM

-65

32Mb pSRAM

Min Max Units

-70

32Mb pSRAM

Min Max Units

Symbol Parameter

Conditions

Min

Max

Units

Min

Max

Units

Power

V_CC

V_IH

V_IL

I_IL

2.7

1.4

3.6

V

2.7

0.8 Vccq

-0.2

3.3

V

2.7

0.8 Vccq

-0.2

3.3

V

2.7

3.3

V

Supply

V_CC

+

0.2

Input High

Level

V_CC

+

V_CC

+ 0.2

V_CC

+ 0.2

0.8

Vccq

0.2

Input Low

Level

0.2

Vccq

0.2

Vccq

0.2

Vccq

-0.2

0.4

0.5

V

-0.2

V

Input

Leakage

Current

Vin = 0 to V_CC

µA

1

µA

1

µA

1

µA

Output

Leakage

Current

OE = V_IHor

Chip Disabled

I_LO

0.5

µA

V

µA

V

µA

V

µA

V

I_OH= -1.0 mA

0.8

Vccq

Output High

Voltage

I_OH= -0.2 mA

V_OH

0.8

Vccq

I_OH= -0.5 mA

I_OL= 2.0 mA

0.8 Vccq

Output Low

Voltage

I

_OL= 0.2 mA

_OL= 0.5 mA

0.2

25

V_OL

V

0.2

Vccq

Operating

Current

I_ACTIVE

V_CC= 3.3 V

_CC= 3.0 V

V_CC= 3.3 V

mA

µA

25

mA

µA

25

mA

µA

25

mA

µA

V

Standby

Current

I_STANDBY

100

10

120

10

120

10

120

10

Deep Power

Down

Current

I_DEEP

SLEEP

µA

1/4 Array

I_{PAR 1/4}

65

80

µA

75

90

µA

75

90

µA

75

90

µA

PAR Current

1/2 Array

PAR Current

I_{PAR 1/2}

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

93

A d v a n c e I n f o r m a t i o n

DC Characteristics

(64Mb pSRAM Page Mode)

Page Mode

Performance Grade

-70

64Mb pSRAM

Max

Density

Symbol

V_CC

Parameter

Power Supply

Conditions

Min

2.7

Units

3.3

V

V_IH

Input High Level

Input Low Level

0.8 Vccq

-0.2

V_CC+ 0.2

0.2 Vccq

V_IL

Input Leakage

Current

I_IL

Vin = 0 to V_CC

1

µA

Output Leakage

Current

OE = V_IHor

Chip Disabled

I_LO

I_OH= -1.0 mA

Output High

Voltage

V_OH

I

_OH= -0.2 mA

V

I_OH= -0.5 mA

I_OL= 2.0 mA

I_OL= 0.2 mA

I_OL= 0.5 mA

0.8 Vccq

Output Low

Voltage

V_OL

0.2 Vccq

25

Operating

Current

I_ACTIVE

V_CC= 3.3 V

mA

µA

V

_CC= 3.0 V

I_STANDBYStandby Current

V_CC= 3.3 V

120

10

I_DEEP

SLEEP

Deep Power

Down Current

µA

1/4 Array PAR

Current

I_{PAR 1/4}

65

80

1/2 Array PAR

Current

I_{PAR 1/2}

Timing Test Conditions

Item

Input Pulse Level

0.1 V_CCto 0.9 V_CC

5ns

Input Rise and Fall Time

Input and Output Timing Reference Levels

Operating Temperature

0.5 V_CC

-25°C to +85°C

94

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

Output Load Circuit

V_CC

14.5K

30 pF

I/O

14.5K

Output Load

Figure 32. Output Load Circuit

Power Up Sequence

After applying power, maintain a stable power supply for a minimum of 200 µs

after CE# > V_IH.

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

95

A d v a n c e I n f o r m a t i o n

AC Characteristics

(4Mb pSRAM Page Mode)

Asynchronous

Performance Grade

Density

-70

4Mb pSRAM

Max

3 Volt

Symbol

Parameter

Min

Units

trc

Read cycle time

70

ns

Address Access

Time

taa

70

20

70

ns

Chip select to

output

tco

toe

tba

tlz

Output enable to

valid output

UB#, LB# Access

time

Chip select to

Low-z output

10

5

UB#, LB# Enable

to Low-Z output

tblz

tolz

thz

Output enable to

Low-Z output

Chip enable to

High-Z output

0

20

UB#, LB#

disable to High-Z

output

tbhz

0

ns

Output disable to

High-Z output

tohz

toh

0

ns

Output hold from

Address Change

10

96

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

Asynchronous

-70

Performance Grade

Density

4Mb pSRAM

3 Volt

Symbol

Parameter

Min

Max

Units

twc

Write cycle time

70

ns

Chipselect to end

of write

tcw

tas

Address set up

Time

0

ns

Address valid to

end of write

taw

70

UB#, LB# valid

to end of write

tbw

twp

twr

70

55

0

ns

Write pulse width

Write recovery

time

Write to output

High-Z

twhz

tdw

tdh

20

ns

Data to write

time overlap

25

0

Data hold from

write time

End write to

tow

5

output Low-Z

Write high pulse

width

7.5

ns

tpc

tpa

Page read cycle

x

Page address

access time

x

twpc

tcp

Page write cycle

x

Chip select high

pulse width

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

97

A d v a n c e I n f o r m a t i o n

AC Characteristics

(8Mb pSRAM Asynchronous)

Asynchronous

B

Version

Performance Grade

Density

C

-70

-55

8Mb pSRAM

Max

-70

8Mb pSRAM

Max

8Mb pSRAM

Max

3 Volt

Symbol

Parameter

Min

Units

Min

Units

Min

Units

trc

Read cycle time

55

ns

70

ns

70

ns

Address Access

Time

taa

55

30

55

ns

70

35

70

ns

70

20

70

ns

Chip select to

output

tco

toe

tba

tlz

Output enable to

valid output

UB#, LB# Access

time

Chip select to

Low-z output

5

0

5

0

10

5

UB#, LB# Enable

to Low-Z output

tblz

tolz

thz

Output enable to

Low-Z output

Chip enable to

High-Z output

20

25

0

20

UB#, LB#

disable to High-Z

output

tbhz

0

ns

0

ns

0

ns

Output disable to

High-Z output

tohz

toh

0

ns

0

ns

0

ns

Output hold from

Address Change

10

98

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

Asynchronous

Version

Performance Grade

Density

B

C

-70

-55

8Mb pSRAM

Max

-70

8Mb pSRAM

Max

3 Volt

Symbol

Parameter

Min

Units

Min

Max

Units

Min

Units

twc

tcw

Write cycle time

55

ns

70

55

ns

70

ns

Chip select to

end of write

45

0

ns

70

0

ns

Address set up

Time

tas

0

ns

Address valid to

end of write

taw

45

55

70

UB#, LB# valid

to end of write

tbw

twp

twr

45

0

ns

55

0

ns

70

55

0

ns

Write pulse width

Write recovery

time

Write to output

High-Z

twhz

tdw

tdh

25

ns

25

20

ns

Data to write

time overlap

40

0

40

0

ns

25

0

Data hold from

write time

End write to

tow

5

output Low-Z

Write high pulse

width

x

ns

x

ns

x

ns

tpc

tpa

Page read cycle

x

Page address

access time

twpc

tcp

Page write cycle

x

Chip select high

pulse width

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

99

A d v a n c e I n f o r m a t i o n

AC Characteristics

(16Mb pSRAM Asynchronous)

Asynchronous

Performance Grade

Density

-55

-70

16Mb pSRAM

3 Volt

Symbol

Parameter

Min

Max

Units

Min

Max

Units

trc

Read cycle time

55

ns

70

ns

Address Access

Time

taa

55

30

55

70

35

70

Chip select to

output

tco

toe

tba

tlz

ns

Output enable to

valid output

UB#, LB# Access

time

Chip select to

Low-z output

5

0

5

0

UB#, LB# Enable

to Low-Z output

tblz

tolz

thz

Output enable to

Low-Z output

Chip enable to

High-Z output

25

UB#, LB#

disable to High-Z

output

tbhz

0

ns

0

ns

Output disable to

High-Z output

tohz

toh

0

ns

0

ns

Output hold from

Address Change

10

100

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

Asynchronous

Performance Grade

Density

-55

-70

16Mb pSRAM

3 Volt

Symbol

Parameter

Min

Max

Units

Min

Max

Units

twc

tcw

Write cycle time

55

ns

70

ns

Chipselect to end

of write

50

0

55

0

Address set up

Time

tas

ns

Address valid to

end of write

taw

50

55

UB#, LB# valid

to end of write

tbw

twp

twr

50

0

ns

55

0

ns

Write pulse width

Write recovery

time

Write to output

High-Z

twhz

tdw

tdh

25

ns

25

ns

Data to write

time overlap

25

0

25

0

Data hold from

write time

End write to

tow

5

output Low-Z

Write high pulse

width

x

ns

x

ns

tpc

tpa

Page read cycle

x

Page address

access time

twpc

tcp

Page write cycle

x

Chip select high

pulse width

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

101

A d v a n c e I n f o r m a t i o n

AC Characteristics

(16Mb pSRAM Page Mode)

Page Mode

Performance Grade

Density

-60

-65

-70

16Mb pSRAM

3 Volt

Symbol

Parameter

Min

Max

Units

Min

Max

Units

Min

Max

Units

trc

Read cycle time

60

20k

ns

65

20k

ns

70

20k

ns

Address Access

Time

taa

60

25

60

65

25

65

70

25

70

Chip select to

output

tco

toe

tba

tlz

ns

Output enable to

valid output

UB#, LB# Access

time

Chip select to

Low-z output

10

5

10

5

10

5

UB#, LB# Enable

to Low-Z output

tblz

tolz

thz

Output enable to

Low-Z output

Chip enable to

High-Z output

0

5

0

5

0

5

UB#, LB#

disable to High-Z

output

tbhz

0

ns

0

ns

0

ns

Output disable to

High-Z output

tohz

toh

0

5

ns

0

5

ns

0

5

ns

Output hold from

Address Change

102

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

Page Mode

-65

Performance Grade

Density

Parameter

-60

-70

16Mb pSRAM

3 Volt

Symbol

Min

Max

Units

Min

Max

Units

Min

Max

Units

twc

Write cycle time

60

20k

ns

65

20k

ns

70

20k

ns

Chipselect to end

of write

tcw

tas

50

0

60

0

60

0

Address set up

Time

ns

Address valid to

end of write

taw

50

60

UB#, LB# valid

to end of write

tbw

twp

twr

50

0

ns

60

50

0

ns

60

50

0

ns

Write pulse width

Write recovery

time

Write to output

High-Z

twhz

tdw

tdh

5

ns

5

ns

5

ns

Data to write

time overlap

20

0

20

0

20

0

Data hold from

write time

End write to

tow

5

output Low-Z

Write high pulse

width

7.5

ns

7.5

ns

7.5

ns

tpc

tpa

Page read cycle

25

20k

25

ns

25

20k

25

ns

25

20k

25

ns

Page address

access time

twpc

tcp

Page write cycle

25

10

20k

25

10

20k

25

10

20k

Chip select high

pulse width

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

103

A d v a n c e I n f o r m a t i o n

AC Characteristics

(32Mb pSRAM Page Mode)

Page Mode

E

Version

Performance Grade

Density

C

-65

-60

-65

-70

32Mb pSRAM

3 Volt

Symbol

Parameter

Min

Max Units

Min

Max Units

Min

Max Units

Min

Max Units

trc

Read cycle time

65

20k

65

ns

60

20k

60

ns

65

20k

65

ns

70

20k

70

ns

Address Access

Time

taa

Chip select to

output

tco

toe

tba

tlz

65

20

65

ns

60

25

60

ns

65

25

65

ns

70

25

70

ns

Output enable to

valid output

UB#, LB# Access

time

Chip select to

Low-z output

10

5

10

5

10

5

10

5

UB#, LB# Enable

to Low-Z output

tblz

tolz

thz

Output enable to

Low-Z output

Chip enable to

High-Z output

0

20

0

5

0

5

0

5

UB#, LB#

disable to High-Z

output

tbhz

0

ns

0

ns

0

ns

0

ns

Output disable to

High-Z output

tohz

toh

0

5

ns

0

5

ns

0

5

ns

0

5

ns

Output hold from

Address Change

104

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

Page Mode

Version

Performance Grade

Density

C

-65

E

-60

-65

-70

32Mb pSRAM

Min Max Units

32Mb pSRAM

3 Volt

Symbol

Parameter

Min

Max Units

Min

Max Units

Min

Max Units

twc

tcw

Write cycle time

65

55

20k

ns

60

50

20k

ns

65

60

20k

ns

70

60

20k

ns

Chipselect to end

of write

Address set up

Time

tas

0

ns

0

ns

0

ns

0

ns

Address valid to

end of write

taw

55

50

60

UB#, LB# valid

to end of write

tbw

twp

twr

55

0

ns

50

0

ns

60

50

0

ns

60

50

0

ns

Write pulse width

20k

5

Write recovery

time

Write to output

High-Z

twhz

tdw

tdh

ns

5

ns

5

ns

5

ns

Data to write

time overlap

25

0

20

0

20

0

20

0

Data hold from

write time

End write to

tow

5

output Low-Z

Write high pulse

width

7.5

ns

7.5

ns

7.5

ns

7.5

ns

tpc

tpa

Page read cycle

25

20k

25

ns

25

20k

25

ns

25

20k

25

ns

25

20k

25

ns

Page address

access time

twpc

tcp

Page write cycle

25

10

20k

25

10

20k

25

10

20k

25

10

20k

Chip select high

pulse width

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

105

A d v a n c e I n f o r m a t i o n

AC Characteristics

(64Mb pSRAM Page Mode)

Page Mode

Performance Grade

Density

-70

64Mb pSRAM

3 Volt

Symbol

Parameter

Min

Max

Units

trc

Read cycle time

70

20k

ns

Address Access

Time

taa

70

25

70

Chip select to

output

tco

toe

tba

tlz

ns

Output enable to

valid output

UB#, LB# Access

time

Chip select to

Low-z output

10

5

UB#, LB# Enable

to Low-Z output

tblz

tolz

thz

Output enable to

Low-Z output

Chip enable to

High-Z output

0

5

UB#, LB#

disable to High-Z

output

tbhz

0

ns

Output disable to

High-Z output

tohz

toh

0

5

ns

Output hold from

Address Change

106

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

Page Mode

-70

Performance Grade

Density

64Mb pSRAM

3 Volt

Symbol

Parameter

Min

Max

Units

twc

Write cycle time

70

20k

ns

Chipselect to end

of write

tcw

tas

60

0

Address set up

Time

ns

Address valid to

end of write

taw

60

UB#, LB# valid

to end of write

tbw

twp

twr

60

50

0

ns

Write pulse width

20k

5

Write recovery

time

Write to output

High-Z

twhz

tdw

tdh

ns

Data to write

time overlap

20

0

Data hold from

write time

End write to

tow

5

output Low-Z

Write high pulse

width

7.5

ns

tpc

tpa

Page read cycle

20

20k

20

ns

Page address

access time

twpc

tcp

Page write cycle

20

10

20k

Chip select high

pulse width

Timing Diagrams

Read Cycle

t_RC

Address

t_AA

t_OH

Previous Data Valid

Figure 33. Timing of Read Cycle (CE# = OE# = V_IL, WE# = ZZ# = V_IH)

August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1

Data Valid

Data Out

107

A d v a n c e I n f o r m a t i o n

t_RC

Address

t_AA

CE#

t_CO

t_LZ

t_HZ

t_OE

OE#

t_OLZ

t_OHZ

t_{LB, UB}

t

LB#, UB#

Data Out

t_BHZ

Data Valid

t_BLZ

High-Z

Figure 34. Timing Waveform of Read Cycle (WE# = ZZ# = V_IH)

108

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

t_PGMAX

Page Address (A4 - A20)

t_RC

t_PC

Word Address (A0 - A3)

t_AA

t_PA

t_HZ

CE#

t_CO

t_OE

t_OHZ

OE#

t_OLZ

t_{LB, UB}

t_BHZ

t

LB#, UB#

t_BLZ,

High-Z

Data Out

Figure 35. Timing Waveform of Page Mode Read Cycle (WE# = ZZ# = V_IH)

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

109

A d v a n c e I n f o r m a t i o n

Write Cycle

t_WC

Address

t_WR

t_AW

CE#

t_CW

t_BW

LB#, UB#

t_AS

t_WP

WE#

t_DW

t_DH

High-Z

Data Valid

Data In

Data Out

t_WHZ

t_OW

High-Z

Figure 36. Timing Waveform of Write Cycle (WE# Control, ZZ# = V_IH)

t_WC

Address

CE#

t_AW

t_WR

t_CW

t_AS

t_BW

LB#, UB#

WE#

t_WP

t_DW

t_DH

Data Valid

Data In

t_WHZ

High-Z

Figure 37. Timing Waveform of Write Cycle (CE# Control, ZZ# = V_IH)

pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004

Data Out

110

A d v a n c e I n f o r m a t i o n

t_PGMAX

Page Address

(A4 - A20)

t_WC

t_PWC

Wor d Address

(A0 - A3 )

t_AS

t_CW

CE#

t_WP

WE#

t_{LBW, UBW}

t

LB#, UB#

t_DW

t_DHt_PDWt_PDH

t_PDWt_PDH

High-Z

Data Out

Figure 38. Timing Waveform of Page Mode Write Cycle (ZZ# = V_IH)

Power Savings Modes (For 16M Page Mode, 32M and 64M Only)

There are several power savings modes.

Partial Array Self Refresh

Temperature Compensated Refresh (64M)

Deep Sleep Mode

Reduced Memory Size (32M, 16M)

The operation of the power saving modes ins controlled by the settings of bits

contained in the Mode Register. This definition of the Mode Register is shown in

Figure 39 and the various bits are used to enable and disable the various low

power modes as well as enabling Page Mode operation. The Mode Register is set

by using the timings defined in Figure xxx.

Partial Array Self Refresh (PAR)

In this mode of operation, the internal refresh operation can be restricted to a

16Mb, 32Mb, or 48Mb portion of the array. The array partition to be refreshed is

determined by the respective bit settings in the Mode Register. The register set-

tings for the PASR operation are defined in Table xxx. In this PASR mode, when

ZZ# is active low, only the portion of the array that is set in the register is re-

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

111

A d v a n c e I n f o r m a t i o n

freshed. The data in the remainder of the array will be lost. The PASR operation

mode is only available during standby time (ZZ# low) and once ZZ# is returned

high, the device resumes full array refresh. All future PASR cycles will use the

contents of the Mode Register that has been previously set. To change the ad-

dress space of the PASR mode, the Mode Register must be reset using the

previously defined procedures. For PASR to be activated, the register bit, A4 must

be set to a one (1) value, “PASR Enabled”. If this is the case, PASR will be acti-

vated 10 µs after ZZ# is brought low. If the A4 register bit is set equal to zero

(0), PASR will not be activated.

Temperature Compensated Refresh (for 64Mb)

In this mode of operation, the internal refresh rate can be optimized for the op-

eration temperature used and this can then lower standby current. The DRAM

array in the PSRAM must be refreshed internally on a regular basis. At higher

temperatures, the DRAM cell must be refreshed more often than at lower tem-

peratures. By setting the temperature of operation in the Mode Register, this

refresh rate can be optimized to yield the lowest standby current at the given op-

erating temperature. There are four different temperature settings that can be

programmed in to the PSRAM. These are defined in Figure 39.

Deep Sleep Mode

In this mode of operation, the internal refresh is turned off and all data integrity

of the array is lost. Deep Sleep is entered by bringing ZZ# low with the A4 reg-

ister bit set to a zero (0), “Deep Sleep Enabled”. If this is the case, Deep Sleep

will be entered 10 µs after ZZ# is brought low. The device will remain in this mode

as long as ZZ# remains low. If the A4 register bit is set equal to one (1), Deep

Sleep will not be activated.

Reduced Memory Size (for 32M and 16M)

In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb

device. The mode and array size are determined by the settings in the VA register.

The VA register is set according to the following timings and the bit settings in

the table “Address Patterns for RMS”. The RMS mode is enabled at the time of ZZ

transitioning high and the mode remains active until the register is updated. To

return to the full 32Mb address space, the VA register must be reset using the

previously defined procedures. While operating in the RMS mode, the unselected

portion of the array may not be used.

Other Mode Register Settings (for 64M)

The Page Mode operation can also be enabled and disabled using the Mode Reg-

ister. Register bit A7 controls the operation of Page Mode and setting this bit to a

one (1), enables Page Mode. If the register bit A7 is set to a zero (0), Page Mode

operation is disabled.

112

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

64 Mb

32 Mb / 16 Mb

A21 - A8

A7

A6

A5

A4

A3

A2

A1

A0

Array Mode

for ZZ#

Reserved

Must set to all 0

Temp

Compensated

Refresh

0 = PAR (default)

1 = RMS

PAR Section

1

0

1

0

1

0

1 = Top 1/4 array

0 = Top 1/2 array

1 = Top 3/4 array

0 = No PAR

1 = Bottom 1/4 array

0 = Bottom 1/2 array

1 = Bottom 3/4 array

0 = Full array (default)

1

0

1

0 = 15^oC

1 = 45^oC

0 = 70^oC

1 = 85^oC (default)

Page Mode

0 = Page Mode Disabled (default)

1 = Page Mode Enabled

Deep Sleep Enable/Disable

0 = Deep Sleep Enabled

1 = Deep Sleep Disabled (default)

Figure 39. Mode Register

t

WC

Address

t

AW

t

AS

t

WR

CE#

t

WP

WE#

ZZ#

t

ZZWE

t

CDZZ

Figure 40. Mode Register Update Timings (UB#, LB#, OE# are Don’t Care)

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

113

A d v a n c e I n f o r m a t i o n

t

ZZMIN

ZZ#

CE#

t

R

CDZZ

Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M)

t

WC

A4

t

AS

AW

CE#

t

WR

t

WP

WE#

t

BW

LB#, UB#

R

t

ZZWE

t

ZZMIN

ZZ#

Figure 42. Deep Sleep Mode - Entry/Exit Timings (for 32M and 16M)

Mode Register Update and Deep Sleep Timings

Item

Chip deselect to ZZ# low

ZZ# low to WE# low

Symbol

t_CDZZ

t_ZZWE

t_WC

Min

5

Max

Unit

ns

µs

Note

10

500

Write register cycle time

Chip enable to end of write

Address valid to end of write

Write recovery time

70/85

0

1

t_CW

t_AW

t_WR

Address setup time

t_AS

0

Write pulse width

t_WR

40

Deep Sleep Pulse Width

Deep Sleep Recovery

t_ZZMIN

t_R

10

200

Notes:

1. Minimum cycle time for writing register is equal to speed grade of product.

114

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

Address Patterns for PASR (A4=1) (64M)

A2 A1 A0

Active Section

Top quarter of die

Top half of die

Reserved

Address Space

300000h-3FFFFFh

200000h-3FFFFFh

Size

Density

16Mb

32Mb

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1Mb x 16

2Mb x 16

No PASR

None

0

Bottom quarter of die

Bottom half of die

Reserved

000000h-0FFFFFh

000000h-1FFFFFh

1Mb x 16

2Mb x 16

16Mb

32Mb

Full array

000000h-3FFFFFh

4Mb x 16

64Mb

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

115

A d v a n c e I n f o r m a t i o n

Deep ICC Characteristics (for 64Mb)

Item

Symbol

Te st

Array Partition Typ Max Unit

None

10

60

1/4 Array

1/2 Array

Full Array

PASR Mode Standby Current

I_PASR

V_IN= V_CCor 0V, Chip Disabled, t_A= 85°C

µA

80

120

Item

Symbol

Max Temperature

15°C

Typ

Max

50

Unit

45°C

60

Temperature Compensated Refresh Current

I_TCR

µA

70°C

80

85°C

120

Item

Symbol

Test

Typ

Max

10

Unit

Deep Sleep Current

I_ZZ

V_IN= V_CCor 0V, Chip in ZZ# mode, t_A= 25°C

µA

Address Patterns for PAR (A3= 0, A4=1) (32M)

A2 A1 A0

Active Section

One-quarter of die

Address Space

000000h - 07FFFFh

Size

Density

8Mb

0

x

1

0

1

0

1

0

512Kb x 16

1Mb x 16

2Mb x 16

512Kb x 16

1Mb x 16

One-half of die

Full die

000000h - 0FFFFFh

000000h - 1FFFFFh

180000h - 1FFFFFh

100000h - 1FFFFFh

16Mb

32Mb

8Mb

One-quarter of die

One-half of die

16Mb

Address Patterns for RMS (A3 = 1, A4 = 1) (32M)

A2 A1 A0

Active Section

One-quarter of die

Address Space

000000h - 07FFFFh

Size

Density

8Mb

0

1

0

1

0

512Kb x 16

1Mb x 16

512Kb x 16

1Mb x 16

One-half of die

One-quarter of die

One-half of die

000000h - 0FFFFFh

180000h - 1FFFFFh

100000h - 1FFFFFh

16Mb

8Mb

16Mb

116

pSRAM Type 1

pSRAM_Type01_12_A1 August 30, 2004

A d v a n c e I n f o r m a t i o n

Low Power ICC Characteristics (32M)

Item

Symbol

Te s t

Array Partition

1/4 Array

Typ

Max

75

Unit

µA

V_IN= V_CCor 0V,

Chip Disabled, t_A= 85^oC

PAR Mode Standby Current I_PAR

RMS Mode Standby Current I_RMSSB

1/2 Array

90

µA

8Mb Device

16Mb Device

75

µA

V_IN= V_CCor 0V,

Chip Disabled, t_A= 85^oC

90

µA

V_IN= V_CCor 0V,

Chip in ZZ mode, t_A= 85^oC

Deep Sleep Current

I_ZZ

10

µA

Address Patterns for PAR (A3= 0, A4=1) (16M)

A2 A1 A0

Active Section

One-quarter of die

Address Space

00000h - 0FFFFh

Size

Density

4Mb

0

x

1

0

1

0

1

0

256Kb x 16

512Kb x 16

1Mb x 16

One-half of die

Full die

00000h - 7FFFFh

00000h - FFFFFh

C0000h - FFFFh

80000h - 1FFFFFh

8Mb

16Mb

4Mb

One-quarter of die

One-half of die

256Kb x 16

512Kb x 16

8Mb

Address Patterns for RMS (A3 = 1, A4 = 1) (16M)

A2 A1 A0

Active Section

One-quarter of die

Address Space

00000h - 0FFFFh

Size

Density

4Mb

0

1

0

1

0

256Kb x 16

512Kb x 16

256Kb x 16

512Kb x 16

One-half of die

One-quarter of die

One-half of die

00000h - 7FFFFh

C0000h - FFFFFh

80000h - FFFFFh

8Mb

4Mb

8Mb

Low Power ICC Characteristics (16M)

Item

Symbol

Test

Array Partition

1/4 Array

Typ

Max

Unit

65

80

65

80

V_IN= V_CCor 0V,

Chip Disabled, t_A= 85^oC

PAR Mode Standby Current

I_PAR

µA

1/2 Array

4Mb Device

8Mb Device

V_IN= V_CCor 0V,

Chip Disabled, t_A= 85^oC

RMS Mode Standby Current

Deep Sleep Current

I_RMSSB

µA

V_IN= V_CCor 0V,

Chip in ZZ# mode, t_A= 85^oC

I_ZZ

10

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

117

A d v a n c e I n f o r m a t i o n

Type 2 pSRAM

16Mbit (1M Word x 16-bit)

32Mbit (2M Word x 16-bit)

64Mbit (4M Word x 16-bit)

128Mbit (8M Word x 16-bit)

Features

Process Technology: CMOS

Organization: x16 bit

Power Supply Voltage: 2.7~3.1V

Three State Outputs

Compatible with Low Power SRAM

Product Information

Standby

Operating

Density

16Mb

32Mb

64Mb

128Mb

V_CCRange

2.7-3.1V

(ISB1, Max.)

(ICC2, Max.)

Mode

80 µA

100 µA

TBD

30 mA

35 mA

40 mA

TBD

Dual CS

Dual CS and Page Mode

Dual CS

Dual CS and Page Mode

Dual CS

TBD

Dual CS and Page Mode

TBD

Pin Description

Pin Name

Description

I/O

CS1#, CS2

OE#

Chip Select

I

Output Enable

Write Enable

WE#

LB#, UB#

Lower/Upper Byte Enable

A0-A19 (16M)

A0-A20 (32M)

A0-A21 (64M)

A0-A22 (128M)

Address Inputs

I

I/O0-I/O15

V_CC/V_CCQ

V_SS/V_SSQ

NC

Data Inputs/Outputs

Power Supply

Ground

I/O

—

Not Connection

Do Not Use

—

DNU

—

118

Type 2 pSRAM

pSRAM_Type02_15A1 June 25, 2004

A d v a n c e I n f o r m a t i o n

Power Up Sequence

1. Apply power.

2. Maintain stable power (V_CCmin.=2.7V) for a minimum 200 µs with

CS1#=high or CS2=low.

Timing Diagrams

Power Up

Min. 200 s

VCC(Min)

VCC

CS1#

CS2

Power Up Mode

Normal Operation

Figure 43. Power Up 1 (CS1# Controlled)

Notes:

1. After V_CCreaches V_CC(Min.), wait 200 µs with CS1# high. Then the device gets into the normal operation.

Min. 200µs

VCC(Mni )

VCC

CS1#

CS2

PowerUp Mode

Normal Operation

Figure 44. Power Up 2 (CS2 Controlled)

Notes:

1. After V_CCreaches V_CC(Min.), wait 200 µs with CS2 low. Then the device gets into the normal operation.

June 25, 2004 pSRAM_Type02_15A1

Type 2 pSRAM

119

A d v a n c e I n f o r m a t i o n

Functional Description

Mode

CS1#

CS2

X

OE#

X

WE#

LB#

X

UB#

X

I/O_1-8

High-Z

D_OUT

I/O_9-16

High-Z

D_OUT

Power

Standby

Active

Deselected

H

X

L

X

H

L

X

H

L

H

X

Output Disabled

Outputs Disabled

Lower Byte Read

Upper Byte Read

Word Read

H

L

H

X

L

Active

H

L

H

L

Active

H

L

H

L

High-Z

D_OUT

Active

H

L

D_OUT

Active

Lower Byte Write

Upper Byte Write

Word Write

H

X

L

H

L

D_IN

High-Z

D_IN

Active

H

X

L

H

L

High-Z

D_IN

Active

H

X

L

D_IN

Active

Legend:X = Don’t care (must be low or high state).

Absolute Maximum Ratings

Item

Symbol

V_{IN ,}V_OUT

V_CC

Ratings

Unit

V

Voltage on any pin relative to V_SS

Voltage on V_CCsupply relative to V_SS

Power Dissipation

-0.2 to V_CC+0.3V

-0.2 to 3.6V

1.0

V

P_D

W

Operating Temperature

T_A

-40 to 85

°C

Notes:

1. Stresses greater than those listed under "Absolute Maximum Ratings" section may cause permanent damage to the device.

Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute

maximum rating conditions longer than one second may affect reliability.

DC Recommended Operating Conditions

Symbol

V_CC

Parameter

Power Supply Voltage

Ground

Min

Typ

2.9

0

Max

Unit

2.7

3.1

V_SS

0

2.2

0

V_CC+ 0.3 (Note 2)

0.6

V

V_IH

Input High Voltage

Input Low Voltage

—

V_IL

-0.2 (Note 3)

—

Notes:

1. TA=-40 to 85°C, unless otherwise specified.

2. Overshoot: V_CC+1.0V in case of pulse width ≤ 20ns.

3. Undershoot: -1.0V in case of pulse width ≤ 20ns.

4. Overshoot and undershoot are sampled, not 100% tested.

120

Type 2 pSRAM

pSRAM_Type02_15A1 June 25, 2004

A d v a n c e I n f o r m a t i o n

Capacitance (Ta = 25°C, f = 1 MHz)

Symbol

C_IN

Parameter

Test Condition

V_IN= 0V

Min

—

Max

8

Unit

pF

Input Capacitance

C_IO

Input/Output Capacitance

V_OUT= 0V

—

10

pF

Note: This parameter is sampled periodically and is not 100% tested.

DC and Operating Characteristics

Common

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Input Leakage Current

I_LI

V_IN=V_SSto V_CC

-1

—

1

µA

CS1#=V_IHor CS2=V_ILor OE#=V_IHor WE#=V_ILor

LB#=UB#=V_IH, V_IO=V_SSto V_CC

Output Leakage Current

I_LO

-1

—

µA

Output Low Voltage

Output High Voltage

V_OL

V_OH

I_OL=2.1mA

—

0.4

—

V

I_OH=-1.0mA

2.4

June 25, 2004 pSRAM_Type02_15A1

Type 2 pSRAM

121

A d v a n c e I n f o r m a t i o n

16M pSRAM

Item

Symbol

Test Conditions

Min Typ Max Unit

Cycle time=1µs, 100% duty, I_IO=0mA,

I_CC1

CS1#

≤

0.2V, LB#

≤

0.2V and/or UB#

≤

0.2V,

—

7

mA

CS2 V_CC-0.2V, V_IN

≥

≤

0.2V or V_INVCC-0.2V

≥

Cycle time=Min, I_IO=0mA, 100% duty,

CS1#=V_IL, CS2=V_IHLB#=V_ILand/or UB#=V_IL,

V_IN=V_IHor V_IL

Average Operating

Current

Async

30 mA

35 mA

I_CC2

Cycle time=t_RC+3t_PC, I_IO=0mA, 100% duty,

CS1#=V_IL, CS2=V_IHLB#=V_ILand/or UB#=V_IL,

V_IN-V_IHor V_IL

Page

Other inputs=0-VCC

1. CS1#

controlled) or

2. 0V CS2

≥

V_CC- 0.2, CS2

≥

V_CC- 0.2V (CS1#

Standby Current (CMOS)

I_SB1(Note 1)

—

80 mA

≤

≤ 0.2V (CS2 controlled)

Notes:

1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from

the time when standby mode is set up.

32M pSRAM

Item

Symbol

Test Conditions

Min Typ Max Unit

Cycle time=1µs, 100% duty, I_IO=0mA,

I_CC1

CS1#

≤

0.2V, LB#

≤

0.2V and/or UB#

≤

0.2V,

—

7

mA

CS2 V_CC-0.2V, V_IN

≥

≤

0.2V or V_INVCC-0.2V

≥

Cycle time=Min, I_IO=0mA, 100% duty,

CS1#=V_IL, CS2=V_IHLB#=V_ILand/or UB#=V_IL,

V_IN=V_IHor V_IL

Average Operating

Current

Async

35 mA

40 mA

I_CC2

Cycle time=t_RC+3t_PC, I_IO=0mA, 100% duty,

CS1#=V_IL, CS2=V_IHLB#=V_ILand/or UB#=V_IL,

V_IN-V_IHor V_IL

Page

Other inputs=0-VCC

1. CS1#

controlled) or

2. 0V CS2

≥

V_CC- 0.2, CS2

≥

V_CC- 0.2V (CS1#

Standby Current (CMOS)

I_SB1(Note 1)

—

100 mA

≤

≤ 0.2V (CS2 controlled)

Notes:

1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from

the time when standby mode is set up.

122

Type 2 pSRAM

pSRAM_Type02_15A1 June 25, 2004

A d v a n c e I n f o r m a t i o n

64M pSRAM

Item

Symbol

Test Conditions

Cycle time=1µs, 100% duty, I_IO=0mA,

Min Typ Max Unit

I_CC1

CS1# 0.2V, LB# 0.2V and/or UB# 0.2V,

≤

—

TBD mA

CS2 V_CC-0.2V, V_IN0.2V or V_INVCC-0.2V

≥

≤

≥

Cycle time=Min, I_IO=0mA, 100% duty,

CS1#=V_IL, CS2=V_IHLB#=V_ILand/or UB#=V_IL,

V_IN=V_IHor V_IL

Average Operating

Current

Async

I_CC2

Cycle time=t_RC+3t_PC, I_IO=0mA, 100% duty,

CS1#=V_IL, CS2=V_IHLB#=V_ILand/or UB#=V_IL,

V_IN-V_IHor V_IL

Page

Other inputs=0-VCC

1. CS1#

controlled) or

2. 0V CS2

≥

V_CC- 0.2, CS2

≥

V_CC- 0.2V (CS1#

Standby Current (CMOS)

I_SB1(Note 1)

—

TBD mA

≤

≤ 0.2V (CS2 controlled)

Notes:

1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from

the time when standby mode is set up.

128M pSRAM

Item

Symbol

Test Conditions

Min Typ Max Unit

Cycle time=1µs, 100% duty, I_IO=0mA, CS1#

≤0.2V,

I_CC1

LB#

≤

0.2V and/or UB#

≤

0.2V, CS2

≥

V_CC-0.2V, V_IN

≤

0.2V or

—

TBD mA

Average Operating

Current

V_IN≥

VCC-0.2V

Cycle time=t_RC+3t_PC, I_IO=0mA, 100% duty, CS1#=V_IL,

CS2=V_IHLB#=V_ILand/or UB#=V_IL, V_IN-V_IHor V_IL

I_CC2

Other inputs=0-V_CC

1. CS1#

≥

V_CC- 0.2, CS2

≥ V_CC- 0.2V (CS1# controlled) or

Standby Current (CMOS) I_SB1(Note 1)

—

TBD mA

2. 0V

≤

CS2 0.2V (CS2 controlled)

≤

Notes:

1. Standby mode is supposed to be set up after at least one active operation after power up. I_SB1is measured after 60ms from

the time when standby mode is set up.

June 25, 2004 pSRAM_Type02_15A1

Type 2 pSRAM

123

A d v a n c e I n f o r m a t i o n

AC Operating Conditions

Test Conditions (Test Load and Test Input/Output Reference)

Input pulse level: 0.4 to 2.2V

Input rising and falling time: 5ns

Input and output reference voltage: 1.5V

Output load (See Figure 45): CL=50pF

Dout

CL

Figure 45. Output Load

Note: Including scope and jig capacitance.

124

Type 2 pSRAM

pSRAM_Type02_15A1 June 25, 2004

A d v a n c e I n f o r m a t i o n

AC Characteristics (Ta = -40°C to 85°C, V_CC= 2.7 to 3.1 V)

Speed Bins

70ns

Symbol

Parameter

Min

Max

Unit

ns

t_RC

Read Cycle Time

70

—

70

35

70

—

t_AA

Address Access Time

—

t_CO

t_OE

Chip Select to Output

Output Enable to Valid Output

UB#, LB# Access Time

Chip Select to Low-Z Output

—

t_BA

—

t_LZ

10

t_BLZ

t_OLZ

t_HZ

UB#, LB# Enable to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

UB#, LB# Disable to High-Z Output

Output Disable to High-Z Output

Output Hold from Address Change

Page Cycle Time

10

—

5

—

0

25

—

t_BHZ

t_OHZ

t_OH

t_PC

0

5

25

—

t_PA

Page Access Time

—

20

—

t_WC

t_CW

t_AS

Write Cycle Time

70

Chip Select to End of Write

Address Set-up Time

60

—

0

—

t_AW

t_BW

t_WP

t_WR

t_WHZ

t_DW

t_DH

t_OW

Address Valid to End of Write

UB#, LB# Valid to End of Write

Write Pulse Width

60

—

60

—

55 (Note 1)

—

Write Recovery Time

0

—

Write to Output High-Z

25

—

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

30

0

—

5

—

Notes:

1. t_WP(min)=70ns for continuous write operation over 50 times.

June 25, 2004 pSRAM_Type02_15A1

Type 2 pSRAM

125

A d v a n c e I n f o r m a t i o n

Timing Diagrams

Read Timings

tRC

Address

Data Out

tAA

tOH

Data Valid

Previous Data Valid

Figure 46. Timing Waveform of Read Cycle(1)

Notes:

1. Address Controlled, CS1#=OE#=V_IL, CS2=WE#=V_IH, UB# and/or LB#=V_IL

.

tRC

Address

tOH

tAA

tCO

CS1#

CS2

tHZ

tBA

UB#, LB#

tBHZ

tOE

OE#

tOLZ

tBLZ

tLZ

tOHZ

High-Z

Data out

Data Valid

Figure 47. Timing Waveform of Read Cycle(2)

Notes:

1. WE#=V_IH

.

126

Type 2 pSRAM

pSRAM_Type02_15A1 June 25, 2004

A d v a n c e I n f o r m a t i o n

Address¹⁾

A1~A0

Valid

Address

Valid

Address

Address Address Address

tAA

tPC

CS1#

CS2

tCO

OE#

tPA

tOHZ

tOE

High Z

Data

Valid

Data

Valid

Data

Valid

Data

Valid

DQ15~DQ0

Figure 48. Timing Waveform of Page Cycle (Page Mode Only)

Notes:

1. 16Mb: A2 ~ A19, 32Mb: A2 ~ A20, 64Mb: A2 ~ A21, 128Mb: A2 ~ A22.

t_HZand t_OHZare defined as the time at which the outputs achieve the open circuit conditions and are not referenced to

output voltage levels.

At any given temperature and voltage condition, t_HZ(Max.) is less than t_LZ(Min.) both for a given device and from device

to device interconnection.

t_OE(max) is met only when OE# becomes enabled after t_AA(max).

If invalid address signals shorter than min. t_RCare continuously repeated for over 4µs, the device needs a normal read

timing (t_RC) or needs to sustain standby state for min. t_RCat least once in every 4µs.

Write Timings

tWC

Address

tCW

tWR

CS1#

CS2

tAW

tBW

UB#, LB#

tWP

WE#

tAS

tDW

tDH

High-Z

Data in

Data Valid

tWHZ

tOW

Data Undefined

Data out

Figure 49. Write Cycle #1 (WE# Controlled)

June 25, 2004 pSRAM_Type02_15A1

Type 2 pSRAM

127

A d v a n c e I n f o r m a t i o n

tWC

Address

tWR

tAS

tCW

tAW

CS1#

CS2

tBW

UB#, LB#

tWP

WE#

tDW

tDH

Data Valid

Data in

High-Z

Data out

Figure 50. Write Cycle #2 (CS1# Controlled)

tWC

Address

tWR

tAS

tCW

tAW

CS1#

CS2

tBW

UB#, LB#

WE#

tWP(1)

tDW

tDH

Data Valid

Data in

Data out

High-Z

Figure 51. Timing Waveform of Write Cycle(3) (CS2 Controlled)

128

Type 2 pSRAM

pSRAM_Type02_15A1 June 25, 2004

A d v a n c e I n f o r m a t i o n

t

WC

Address

CS1#

t

WR

t

CW

t

AW

CS2

t

BW

UB#, LB#

t

AS

t

WP

WE#

t

DH

t

DW

Data Valid

Data in

Data out

High-Z

Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled)

Notes:

1. A write occurs during the overlap (t_WP) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes low

with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A

write ends at the earliest transition when CS1# goes high and WE# goes high. The t_WPis measured from the beginning of

write to the end of write.

2. t_CWis measured from the CS1# going low to the end of write.

3. t_ASis measured from the address valid to the beginning of write.

4.

t_WRis measured from the end of write to the address change. t_WRis applied in case a write ends with CS1# or WE# going

high.

June 25, 2004 pSRAM_Type02_15A1

Type 2 pSRAM

129

A d v a n c e I n f o r m a t i o n

pSRAM Type 7

16Mb (1M word x 16-bit)

32Mb (2M word x 16-bit)

64Mb (4M word x 16-bit)

CMOS 1M/2M/4M-Word x 16-bit Fast Cycle Random Access Memory with Low

Power SRAM Interface

Features

Asynchronous SRAM Interface

Fast Access Time

— tCE = tAA = 60ns max (16M)

— tCE = tAA = 65ns max (32M/64M)

8 words Page Access Capability

— tPAA = 20ns max (32M/64M)

Low Voltage Operating Condition

— VDD = +2.7V to +3.1V

Wide Operating Temperature

— TA = -30°C to +85°C

Byte Control by LB and UB

Various Power Down modes

— Sleep (16M)

— Sleep, 4M-bit Partial, or 8M-bit Partial (32M)

— Sleep, 8M-bit Partial, or 16M-bit Partial (64M)

Pin Description

Pin Name

A₂₁to A₀

CE1#

CE2#

WE#

Description

Address Input: A₁₉to A₀for 16M, A₂₀to A₀for 32M, A₂₁to A₀for 64M

Chip Enable (Low Active)

Chip Enable (High Active)

Write Enable (Low Active)

OE#

Output Enable (Low Active)

UB#

Upper Byte Control (Low Active)

Lower Byte Control (Low Active)

Upper Byte Data Input/Output

Lower Byte Data Input/Output

Power Supply

LB#

DQ_{16 9}

-

DQ₈-₁

V_DD

V_SS

Ground

130

pSRAM Type 7

pSRAM_Type07_13_A1 November 2, 2004

A d v a n c e i n f o r m a t i o n

Functional Description

Mode

Standby (Deselect)

Output Disable (Note 1)

Output Disable (No Read)

Read (Upper Byte)

Read (Lower Byte)

Read (Word)

CE2#

CE1#

WE#

OE#

X

LB#

X

UB#

X

A_21-0

X

DQ_8-1

High-Z

DQ_16-9

High-Z

H

X

H

X

Note 3

Valid

X

High-Z

H

L

H

L

High-Z

Output Valid

High-Z

H

L

H

L

Output Valid

Invalid

H

L

Output Valid

Invalid

No Write

H

L

H

L

Write (Upper Byte)

Write (Lower Byte)

Write (Word)

Invalid

Input Valid

Invalid

L

H

X

H

L

Input Valid

High-Z

L

Input Valid

High-Z

Power Down

L

X

Legend:L = V_IL, H = V_IH, X can be either V_ILor V_IH, High-Z = High Impedance.

Notes:

1. Should not be kept this logic condition longer than 1 ms. Please contact local Spansion representative for the relaxation of

1ms limitation.

2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the

selection of the Power-Down Program, 16M has data retention in all modes except Power Down. Refer to Power Down for

details.

3. Can be either V_ILor V_IHbut must be valid before Read or Write.

Power Down (for 32M, 64M Only)

Power Down

The Power Down is a low-power idle state controlled by CE2. CE2 Low drives the

device in power-down mode and maintains the low-power idle state as long as

CE2 is kept Low. CE2 High resumes the device from power-down mode. These

devices have three power-down modes. These can be programmed by series of

read/write operation. Each mode has following features.

32M

Retention Data

No

64M

Retention Data

No

Mode

Retention Address

N/A

Mode

Retention Address

N/A

Sleep (default)

4M Partial

Sleep (default)

8M Partial

4M bit

00000h to 3FFFFh

00000h to 7FFFFh

8M bit

00000h to 7FFFFh

00000h to FFFFFh

8M Partial

8M bit

16M Partial

16M bit

The default state is Sleep and it is the lowest power consumption but all data is

lost once CE2 is brought to Low for Power Down. It is not required to program to

Sleep mode after power-up.

November 2, 2004 pSRAM_Type07_13_A1

pSRAM Type 7

131

A d v a n c e I n f o r m a t i o n

Power Down Program Sequence

The program requires 6 read/write operations with a unique address. Between

each read/write operation requires that device be in standby mode. The following

table shows the detail sequence.

Cycle #

1st

Operation

Read

Address

3FFFFFh (MSB)

3FFFFFh

Data

Read Data (RDa)

RDa

2nd

3rd

Write

Read

3FFFFFh

RDa

4th

3FFFFFh

Don’t Care (X)

X

5th

3FFFFFh

6th

Address Key

Read Data (RDb)

The first cycle reads from the most significant address (MSB).

The second and third cycle are to write back the data (RDa) read by first cycle.

If the second or third cycle is written into the different address, the program is

cancelled, and the data written by the second or third cycle is valid as a normal

write operation.

The fourth and fifth cycles write to MSB. The data from the fourth and fifth cycles

is “don’t care.” If the fourth or fifth cycles are written into different address, the

program is also cancelled but write data might not be written as normal write

operation.

The last cycle is to read from specific address key for mode selection.

Once this program sequence is performed from a Partial mode to the other Partial

mode, the written data stored in memory cell array can be lost. So, it should per-

form this program prior to regular read/write operation if Partial mode is used.

Address Key

The address key has following format.

Mode

Address

32M

Sleep (default)

4M Partial

8M Partial

N/A

64M

Sleep (default)

N/A

A21

1

A20

1

A19

1

A18 - A0

Binary

1

3FFFFFh

37FFFFh

2FFFFFh

27FFFFh

1

0

8M Partial

16M Partial

1

0

1

0

132

pSRAM Type 7

pSRAM_Type07_13_A1 November 2, 2004

A d v a n c e i n f o r m a t i o n

Absolute Maximum Ratings

Item

Symbol

V_DD

Value

Unit

V

Voltage of V_DDSupply Relative to V_SS

Voltage at Any Pin Relative to V_SS

Short Circuit Output Current

Storage temperature

-0.5 to +3.6

±50

V_IN, V_OUT

I_OUT

V

mA

°C

T_STG

-55 to +125

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,

etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Recommended Operating Conditions (See Warning Below)

Parameter

Symbol

V_DD

V_SS

V_IH

Min

2.7

Max

3.1

Unit

V

Supply Voltage

0

V

High Level Input Voltage (Note 1)

Ambient Temperature

V_DD0.8

-0.3

-30

V_DD+0.2

V_DD0.2

85

V

V_IL

V

T_A

°C

Notes:

1. Maximum DC voltage on input and I/O pins is V_DD+0.2V. During voltage transitions, inputs can positive overshoot to

_DD+1.0V for periods of up to 5 ns.

V

2. Minimum DC voltage on input or I/O pins is -0.3V. During voltage transitions, inputs can negative overshoot V_SSto -1.0V for

periods of up to 5ns.

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the de-

vice’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges can

adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.

Users considering application outside the listed conditions are advised to contact their FUJITSU representative before-

hand.

Package Capacitance

Test conditions: T_A= 25°C, f = 1.0 MHz

Symbol

Description

Test Setup

V_IN= 0V

V_IO= 0V

Typ

—

Max

5

Unit

pF

C_IN1

C_IN2

C_IO

Address Input Capacitance

Control Input Capacitance

Data Input/Output Capacitance

—

5

pF

—

8

pF

November 2, 2004 pSRAM_Type07_13_A1

pSRAM Type 7

133

A d v a n c e I n f o r m a t i o n

DC Characteristics

(Under Recommended Conditions Unless Otherwise Noted)

16M

32M

64M

Parameter

Symbol

Test Conditions

Min. Max. Min. Max. Min. Max. Unit

Input Leakage

Current

I_LI

V_IN= V_SSto V_DD

-1.0 +1.0 -1.0 +1.0 -1.0 +1.0

µ

A

Output Leakage

Current

I_LO

V_OH

V_OL

V_OUT= V_SSto V_DD, Output Disable

V_DD= V_DD(min), I_OH= –0.5mA

I_OL= 1mA

µ

Output High

Voltage Level

2.2

—

2.4

—

2.4

—

V

Output Low

Voltage Level

0.4

10

0.4

—

0.4

10

V

I_DDPS

I_DDP4

I_DDP8

I_DDP16

SLEEP

—

10

40

50

µ

A

V_DD= V_DDmax.,

V_IN= V_IHor V_IL,

4M Partial

8M Partial

16M Partial

N/A

µ

V_DDPower

Down Current

N/A

—

80

CE2

≤ 0.2 V

N/A

100

V_DD= V_DDmax.,

V_IN= V_IHor V_IL

CE1 = CE2 = V_IH

I_DDS

—

1

—

1.5

80

—

1.5

mA

V_DDStandby

Current

170

90

µ

A

TA< +85°C

TA< +40°C

V_DD= V_DDmax.,

I_DDS1

V_IN

≤

0.2V or V_IN

≥

V_DD– 0.2V,

100

CE1 = CE2

≥

V_DD– 0.2V

µ

I_DDA1

I_DDA2

V_DD= V_DDmax.,

V_IN= V_IHor V_IL,

CE1 = V_ILand CE2= V_IH,

t_RC/ t_WC= min.

—

20

3

—

30

3

—

40

mA

V_DD

Active Current

t_RC/ t_WC= 1

µs

5

I_OUT=0mA

V_DD= V_DDmax., V_IN= V_IHor V_IL,

CE1 = V_ILand CE2= V_IH,

I_OUT=0mA, t_PRC= min.

V_DDPage

Read Current

I_DDA3

N/A

—

10

—

10

mA

Notes:

1. All voltages are referenced to V_SS

.

2. DC Characteristics are measured after following POWER-UP timing.

3. I_OUTdepends on the output load conditions.

134

pSRAM Type 7

pSRAM_Type07_13_A1 November 2, 2004

A d v a n c e i n f o r m a t i o n

AC Characteristics

(Under Recommended Operating Conditions Unless Otherwise Noted)

Read Operation

16M

32M

64M

Parameter

Symbol

Unit

Notes

Min.

70

—

Max.

1000

60

Min.

65

—

20

5

Max.

1000

65

40

65

30

20

1000

—

Min.

65

—

20

5

Max.

1000

65

40

65

30

20

1000

—

Read Cycle Time

t_RC

t_CE

ns

1, 2

CE1# Access Time

3

OE# Access Time

t_OE

—

40

3

Address Access Time

t_AA

—

60

3, 5

LB# / UB# Access Time

t_BA

—

30

3

Page Address Access Time

Page Read Cycle Time

t_PAA

t_PRC

t_OH

N/A

3,6

1, 6, 7

Output Data Hold Time

5

—

3

4

3

CE1# Low to Output Low-Z

OE# Low to Output Low-Z

LB# / UB# Low to Output Low-Z

CE1# High to Output High-Z

OE# High to Output High-Z

LB# / UB# High to Output High-Z

Address Setup Time to CE1# Low

Address Setup Time to OE# Low

Address Invalid Time

t_CLZ

t_OLZ

t_BLZ

t_CHZ

t_OHZ

t_BHZ

t_ASC

t_ASO

t_AX

5

—

5

—

0

—

0

—

0

—

0

—

0

—

0

—

−6

10

—

-6

10

20

—

–6

10

—

–6

12

20

14

20

—

–6

10

—

–6

25

12

20

14

20

—

10

—

10

—

10

—

5, 8

9

Address Hold Time from CE1# High

Address Hold Time from OE# High

WE# High to OE# Low Time for Read

CE1# High Pulse Width

t_CHAH

t_OHAH

t_WHOL

t_CP

—

1000

—

10

—

Notes:

1. Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A21. If needed by system

operation, please contact local Spansion representative for the relaxation of 1µs limitation.

2. Address should not be changed within minimum t_RC

.

3. The output load 50 pF with 50 ohm termination to V_DDx 0.5 (16M), The output load 50 pF (32M and 64M).

4. The output load 5pF.

5. Applicable to A3 to A21 (32M and 64M) when CE1# is kept at Low.

6. Applicable only to A0, A1 and A2 (32M and 64M) when CE1# is kept at Low for the page address access.

7. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4 µs. In other

words, Page Read Cycle must be closed within 4 µs.

8. Applicable when at least two of address inputs among applicable are switched from previous state.

9.

t_RC(min) and t_PRC(min) must be satisfied.

10. If actual value of t_WHOLis shorter than specified minimum values, the actual t_AAof following Read can become longer by the

amount of subtracting the actual value from the specified minimum value.

November 2, 2004 pSRAM_Type07_13_A1

pSRAM Type 7

135

A d v a n c e I n f o r m a t i o n

AC Characteristics

Write Operation

16M

32M

64M

Parameter

Write Cycle Time

Symbol

t_WC

Min.

70

0

Max.

1000

—

Min.

65

0

Max.

1000

—

Min.

65

0

Max.

Unit

ns

Notes

1000

—

1,2

3

Address Setup Time

t_AS

CE1# Write Pulse Width

WE# Write Pulse Width

LB#/UB# Write Pulse Width

LB#/UB# Byte Mask Setup Time

LB#/UB# Byte Mask Hold Time

Write Recovery Time

t_CW

t_WP

45

-5

0

—

40

–5

0

—

40

–5

0

—

3

—

3

t_BW

—

3

t_BS

—

4

t_BH

—

5

t_WR

—

6

CE1# High Pulse Width

WE# High Pulse Width

t_CP

10

7.5

10

15

0

—

12

7.5

12

0

—

12

7.5

12

0

—

t_WHP

t_BHP

t_DS

1000

—

1000

—

1000

—

7

LB#/UB# High Pulse Width

Data Setup Time

Data Hold Time

t_DH

—

OE# High to CE1# Low Setup Time for Write

OE# High to Address Setup Time for Write

LB# and UB# Write Pulse Overlap

Notes:

t_OHCL

t_OES

t_BWO

-5

0

—

–5

0

—

–5

0

—

8

9

—

30

—

30

—

30

—

1. Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system

operation, please contact local Spansion representative for the relaxation of 1µs limitation.

2. Minimum value must be equal or greater than the sum of write pulse (t_CW, t_WPor t_BW) and write recovery time (t_WR).

3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last.

4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever

occurs last.

5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever

occurs first.

6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first.

7.

t_WPHminimum is absolute minimum value for device to detect High level. And it is defined at minimum V_IHlevel.

8. If OE# is Low after minimum t_OHCL, read cycle is initiated. In other words, OE# must be brought to High within 5ns after

CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum t_RCis met.

9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time

or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum t_RCis met and data

bus is in High-Z.

136

pSRAM Type 7

pSRAM_Type07_13_A1 November 2, 2004

A d v a n c e i n f o r m a t i o n

AC Characteristics

Power Down Parameters

16M

32M

64M

Parameter

Symbol Min. Max. Min. Max. Min. Max. Unit Note

CE2 Low Setup Time for Power Down Entry

CE2 Low Hold Time after Power Down Entry

t_CSP

10

80

—

10

65

—

10

65

—

ns

t_C2LP

CE1# High Hold Time following CE2 High after Power

Down Exit [SLEEP mode only]

t_CHH

t_CHHP

t_CHS

300

—

300

1

—

300

1

—

µ

s

1

2

1

CE1# High Hold Time following CE2 High after Power

Down Exit [not in SLEEP mode]

N/A

µ

CE1# High Setup Time following CE2 High after Power

Down Exit

0

—

0

ns

Notes:

1. Applicable also to power-up.

2. Applicable when 4Mb and 8Mb Partial modes are programmed.

Other Timing Parameters

16M

32M

64M

Parameter

CE1# High to OE# Invalid Time for Standby Entry

CE1# High to WE# Invalid Time for Standby Entry

CE2 Low Hold Time after Power-up

CE1# High Hold Time following CE2 High after Power-up

Input Transition Time

Symbol Min. Max. Min. Max. Min. Max. Unit Note

t_CHOX

t_CHWX

t_C2LH

t_CHH

t_T

10

50

300

1

—

25

10

50

300

1

—

25

10

50

300

1

—

25

ns

1

2

µ

s

µ

ns

Notes:

1. Some data might be written into any address location if t_CHWX(min) is not satisfied.

2. The Input Transition Time (t_T) at AC testing is 5ns as shown in below. If actual tT is longer than 5ns, it can violate the AC

specification of some of the timing parameters.

November 2, 2004 pSRAM_Type07_13_A1

pSRAM Type 7

137

A d v a n c e I n f o r m a t i o n

AC Characteristics

AC Test Conditions

Symbol

V_IH

Description

Te s t S e t up

Value

V_DD* 0.8

V_DD* 0.2

V_DD* 0.5

5

Unit

V

Note

Input High Level

V_IL

Input Low Level

V

V_REF

t_T

Input Timing Measurement Level

Input Transition Time

V

Between V_ILand V_IH

ns

AC Measurement Output Load Circuits

VDD *0.5 V

50 ohm

OUT

VDD

DEVICE

UNDER

TEST

0.1 µF

VSS

50 pF

Figure 53. AC Output Load Circuit – 16 Mb

V_DD

DEVICE

UNDER

TEST

OUT

0.1µF

V_SS

50pF

Figure 54. AC Output Load Circuit – 32 Mb and 64 Mb

138

pSRAM Type 7

pSRAM_Type07_13_A1 November 2, 2004

A d v a n c e i n f o r m a t i o n

Timing Diagrams

Read Timings

tRC

ADDRESS VALID

ADDRESS

tASC

tCE

tCHAH

tASC

CE1#

OE#

tCP

tCHZ

tOE

tOHZ

tBHZ

tBA

LB#/UB#

tBLZ

tOLZ

DQ

(Output)

tCLZ

VALID DATA OUTPUT

tOH

Note: This timing diagram assumes CE2=H and WE#=H.

Figure 55. Read Timing #1 (Basic Timing)

tAx

tRC

ADDRESS

CE1#

ADDRESS VALID

tAA

tOHAH

Low

tASO

tOE

OE#

LB#/UB#

tOLZ

tOH

tOHZ

tOH

DQ

(Output)

VALID DATA OUTPUT

Note: This timing diagram assumes CE2=H and WE#=H.

VALID DATA OUTPUT

Figure 56. Read Timing #2 (OE# Address Access

November 2, 2004 pSRAM_Type07_13_A1

pSRAM Type 7

139

A d v a n c e I n f o r m a t i o n

tAX

tRC

tAx

ADDRESS

ADDRESS VALID

tAA

Low

CE1#, OE#

tBA

LB#

tBA

UB#

tBHZ

tOH

tBLZ

DQ1-8

(Output)

VALID DATA

OUTPUT

tBHZ

VALID DATA

OUTPUT

tOH

tBLZ

DQ9-16

(Output)

VALID DATA OUTPUT

Note: This timing diagram assumes CE2=H and WE#=H.

Figure 57. Read Timing #3 (LB#/UB# Byte Access)

tRC

ADDRESS

(A21-A3)

ADDRESS VALID

tRC

tPRC

ADDRESS

(A2-A0)

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS VALID

tASC

tCHAH

tPAA

CE1#

OE#

tCHZ

tCE

LB#/UB#

tOH

tCLZ

tOH

DQ

(Output)

VALID DATA OUTPUT

(Page Access)

VALID DATA OUTPUT

(Normal Access)

Note: This timing diagram assumes CE2=H and WE#=H.

Figure 58. Read Timing #4 (Page Address Access after CE1# Control Access for 32M and 64M Only)

140

pSRAM Type 7

pSRAM_Type07_13_A1 November 2, 2004

A d v a n c e i n f o r m a t i o n

tRC

tAX

tRC

tAx

ADDRESS

(A21-A3)

ADDRESS VALID

tRC

tPRC

t^RC

tPRC

ADDRESS

(A2-A0)

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

tAA

tPAA

tAA

tPAA

CE1#

Low

tASO

tOE

OE#

tBA

LB#/UB#

tOLZ

tBLZ

tOH

DQ

(Output)

VALID DATA OUTPUT

(Page Access)

VALID DATA OUTPUT

(Normal Access)

Notes:

1. This timing diagram assumes CE2=H and WE#=H.

2. Either or both LB# and UB# must be Low when both CE1# and OE# are Low.

Figure 59. Read Timing #5 (Random and Page Address Access for 32M and 64M Only)

Write Timings

tWC

ADDRESS

ADDRESS VALID

tAS

tCW

tWR

tAS

CE1#

WE#

tCP

tAS

tWP

tAS

tWHP

tAS

tBW

tAS

LB#, UB#

tBHP

tOHCL

OE#

tDS

tDH

DQ

(Input)

VALID DATA INPUT

Note: This timing diagram assumes CE2=H.

Figure 60. Write Timing #1 (Basic Timing)

November 2, 2004 pSRAM_Type07_13_A1

pSRAM Type 7

141

A d v a n c e I n f o r m a t i o n

tWC

ADDRESS VALID

ADDRESS

CE1#

tOHAH

Low

tAS

tWP

tWR

tAS

tWP

tWR

WE#

tWHP

LB#, UB#

OE#

tOES

tOHZ

tDS

tDH

tDS

tDH

DQ

(Input)

VALID DATA INPUT

Note:This timing diagram assumes CE2=H.

Figure 61. Write Timing #2 (WE# Control)

tWC

ADDRESS VALID

ADDRESS

CE1#

Low

tAS

tWP

tAS

tWP

tWHP

tBS

WE#

LB#

tBH

tWR

tBS

tBH

UB#

tDS

tDH

DQ1-8

(Input)

VALID DATA INPUT

tDS

tDH

DQ9-16

(Input)

Note: This timing diagram assumes CE2=H and OE#=H.

Figure 62. Write Timing #3-1 (WE#/LB#/UB# Byte Write Control)

142

pSRAM Type 7

pSRAM_Type07_13_A1 November 2, 2004

A d v a n c e i n f o r m a t i o n

tWC

ADDRESS VALID

ADDRESS

CE1#

Low

tWR

WE#

LB#

tWHP

tAS

tBW

tBS

tBH

tAS

tBW

tBH

tBS

UB#

tDS

tDH

DQ1-8

(Input)

VALID DATA INPUT

tDS

tDH

DQ9-16

(Input)

VALID DATA INPUT

Note: This timing diagram assumes CE2=H and OE#=H.

Figure 63. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control)

tWC

ADDRESS VALID

ADDRESS

CE1#

Low

WE#

LB#

tAS

tBW

tWR

tAS

tBW

tWR

tDH

tBHP

tBWO

tDS

tDH

tDS

DQ1-8

(Input)

VALID

DATA INPUT

VALID

DATA INPUT

tAS

tBW

tWR

tAS

tWR

tBWO

tBW

UB#

tBHP

tDS

tDH

tDS

tDH

DQ9-16

(Input)

VALID

DATA INPUT

VALID

DATA INPUT

Note: This timing diagram assumes CE2=H and OE#=H.

Figure 64. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control)

November 2, 2004 pSRAM_Type07_13_A1

pSRAM Type 7

143

A d v a n c e I n f o r m a t i o n

Read/Write Timings

tWC

tRC

ADDRESS

CE1#

WRITE ADDRESS

READ ADDRESS

tCHAH

tAS

tCW

tWR

tASC

tCE

tCHAH

tCP

WE#

UB#, LB#

OE#

tOHCL

tCHZ

tOH

tDS

tDH

tCLZ

tOH

DQ

READ DATA OUTPUT

WRITE DATA INPUT

Notes:

1. This timing diagram assumes CE2=H.

2. Write address is valid from either CE1# or WE# of last falling edge.

Figure 65. Read/Write Timing #1-1 (CE1# Control)

tWC

tRC

ADDRESS

CE1#

WRITE ADDRESS

READ ADDRESS

tCHAH

tAS

tWR

tASC

tCE

tCHAH

tCP

tWP

WE#

UB#, LB#

OE#

tOHCL

tOE

tCHZ

tOH

tDS

tDH

tOLZ

tOH

DQ

READ DATA OUTPUT

WRITE DATA INPUT

READ DATA OUTPUT

Notes:

1. This timing diagram assumes CE2=H.

2. OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read sequence.

Figure 66. Read / Write Timing #1-2 (CE1#/WE#/OE# Control)

144

pSRAM Type 7

pSRAM_Type07_13_A1 November 2, 2004

A d v a n c e i n f o r m a t i o n

tWC

tRC

ADDRESS

CE1#

WRITE ADDRESS

READ ADDRESS

tOHAH

tAA

Low

tAS

tWR

tWP

WE#

UB#, LB#

OE#

tOES

tASO

tOE

tWHOL

tOHZ

tOH

tOHZ

tOH

tDS

tDH

tOLZ

DQ

READ DATA OUTPUT

WRITE DATA INPUT

Notes:

1. This timing diagram assumes CE2=H.

2. CE1# can be tied to Low for WE# and OE# controlled operation.

Figure 67. Read / Write Timing #2 (OE#, WE# Control)

tWC

tRC

ADDRESS

CE1#

WRITE ADDRESS

READ ADDRESS

tAA

tOHAH

Low

WE#

tOES

tAS

tBW

tWR

tBA

UB#, LB#

OE#

tBHZ

tASO

tWHOL

tBHZ

tOH

tDS

tDH

tBLZ

tOH

DQ

READ DATA OUTPUT

WRITE DATA INPUT

Notes:

1. This timing diagram assumes CE2=H.

2. CE1# can be tied to Low for WE# and OE# controlled operation.

Figure 68. Read / Write Timing #3 (OE#, WE#, LB#, UB# Control)

November 2, 2004 pSRAM_Type07_13_A1

pSRAM Type 7

145

A d v a n c e I n f o r m a t i o n

CE1#

CE2

tCHS

tC2LH

tCHH

VDD

VDD min

0V

Note: The t

specifies after V

reaches specified minimum level.

C2LH

DD

Figure 69. Power-up Timing #1

CE1#

tCHH

CE2

VDD

VDD min

0V

Note: The t

specifies after V

reaches specified minimum level and applicable to both CE1# and CE2.

CHH

DD

Figure 70. Power-up Timing #2

CE1#

tCHS

CE2

DQ

tCSP

tC2LP

tCHH (tCHHP)

High-Z

Power Down Entry

Power Down Mode

Power Down Exit

Note: This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and

Power-Down program was not performed prior to this reset.

Figure 71. Power Down Entry and Exit Timing

146

pSRAM Type 7

pSRAM_Type07_13_A1 November 2, 2004

A d v a n c e i n f o r m a t i o n

CE1#

OE#

tCHOX

tCHWX

WE#

Active (Read)

and t define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes

CHWX

Standby

Active (Write)

Standby

Note: Both t

CHOX

t

(min) period for Standby mode from CE1# Low to High transition.

RC

Figure 72. Standby Entry Timing after Read or Write

tRC

tWC

tRC

MSB*¹

Key*²

ADDRESS

CE1#

tCP*³

tCP

OE#

WE#

LB#, UB#

DQ*³

RDa

Cycle #1

RDa

Cycle #2

RDa

Cycle #3

X

RDb

Cycle #6

Cycle #4

Cycle #5

Notes:

1. The all address inputs must be High from Cycle #1 to #5.

2. The address key must confirm the format specified in page 132. If not, the operation and data are not guaranteed.

3. After t_CPfollowing Cycle #6, the Power Down Program is completed and returned to the normal operation.

Figure 73. Power Down Program Timing (for 32M/64M Only)

November 2, 2004 pSRAM_Type07_13_A1

pSRAM Type 7

147

A d v a n c e I n f o r m a t i o n

Revision Summary

Revision A0 (June 9, 2004)

Initial release.

Revision A1 (July 19, 2004)

Global Change

Change all instances of FASL to Spansion

Added Colophon text.

“Product Selector Guide” on page 2

Replaced “S71PL129JA0-9Z” with “S71PL129JA0-9P”.

“Ordering Information” on page 9

In Model Number section replaced pSRAM part number with “See valid combinations table”.

Revision A2 (July 21, 2004)

“Connection Diagram” on page 7

Changed Row D of pinout for accuracy.

Added the following note: “May be shared depending on density:A21 is shared for the 64M pSRAM

configuration;A20 is shred for the 32M pSRAM configuration; A19 is shared for the 16M pSRAM

configuration.

Revision A3 (October 18, 2004)

Core Flash Module

Replaced core flash module from S29PL127J_064J_032J_MCP_00_A1_E to

S29PL129J_MCP_00_A0

Revision A4 (November 30, 2004)

Product Selector Guide

Added a new model number.

Valid Combinations Table

Whole table updated with new OPNs.

Revision A5 (December 23, 2004)

Connection Diagram

Updated pin L5.

Valid Combinations Table

Added a note to the bottom of the table.

148

Revision Summary

S71PL129Jxx_00_A5_E December 23, 2004

A d v a n c e I n f o r m a t i o n

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary

industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that

includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,

medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and

artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-

mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such

failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels

and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-

port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the

prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development

by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided

as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement

of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the

use of the information in this document.

names used in this publication are for identification purposes only and may be trademarks of their respective companies.

December 23, 2004 S71PL129Jxx_00_A5_E

Revision Summary

149


型号：	S71PL129JA0BAW9B0
厂家：	SPANSION
描述：	Stacked Multi-Chip Product (MCP) Flash Memory 堆叠式多芯片产品（ MCP ）闪存闪存
文件：	总149页 (文件大小：2994K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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