S71VS256RD0ZHEC00 [SPANSION]
Memory Circuit, 16X16, CMOS, PBGA56, 9.20 X 8 MM, 0.50 MM PITCH, LEAD FREE, VFBGA-56;
| 型号： | S71VS256RD0ZHEC00 |
| 厂家： | 
SPANSION |
| 描述： | Memory Circuit, 16X16, CMOS, PBGA56, 9.20 X 8 MM, 0.50 MM PITCH, LEAD FREE, VFBGA-56 静态存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：570K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S71VS/XS-R Memory Subsystem
Solutions
MirrorBit® 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Multiplexed Flash Memory and Burst Mode
pSRAM
256 Mb (16 Mb x 16-bit) / 128 Mb (8 Mb x 16-bit) Flash,
128 Mb (8 Mb x 16-bit) pSRAM / 64 Mb (4 Mb x 16-bit) pSRAM
S71VS/XS-R Memory Subsystem Solutions Cover Sheet
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S71VS_XS-R_00
Revision 01
Issue Date August 25, 2008
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_01 August 25, 2008
S71VS/XS-R Memory Subsystem
Solutions
MirrorBit® 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Multiplexed Flash Memory and Burst Mode
pSRAM
256 Mb (16 Mb x 16-bit) / 128 Mb (8 Mb x 16-bit) Flash,
128 Mb (8 Mb x 16-bit) pSRAM / 64 Mb (4 Mb x 16-bit) pSRAM
Data Sheet
Features
Power supply voltage of 1.7 V to 1.95 V
Flash Burst Speed: 104 MHz, 83 MHz
pSRAM Burst Speed: 104 MHz
MCP BGA Packages
– 56 ball, 7.7 x 6.2 mm, 0.5 mm ball pitch
– 56 ball, 9.2 x 8.0 mm, 0.5 mm ball pitch
Operating Temperature
– Wireless, –25°C to +85°C
General Description
The S71VS-R Series is a product line of stacked Multi-Chip Package (MCP) memory solutions and consists of the following
items:
One or more S29VS-R or S29XS-R Flash memory die
One or more pSRAM
The products covered by this document are listed in the table below. For details about their specifications, please refer to their
individual datasheet for further details.
Flash Density
128 Mb
pSRAM Density
64 Mb
Product
S71VS128RC0
S71VS256RC0
S71VS256RD0
S71XS256RD0
256 Mb
64 Mb
256 Mb
128 Mb
256 Mb
128 Mb
For detailed specifications, please refer to the individual data sheets:
Document
S29VS-R
Publication Identification Number
S29VS_XS-R_00
S29VS_XS-R_00
TBD
S29XS-R
128 Mb MUX pSRAM Type 5
64 Mb MUX pSRAM Type 3
muxpsram_14
Publication Number S71VS_XS-R_00
Revision 01
Issue Date August 25, 2008
D a t a S h e e t
1. Ordering Information
The order number is formed by a valid combinations of the following:
S71VS
256
R
C
0
ZH
K
Z0
0
Packing Type
0
2
3
= Tray
= 7-inch Tape and Reel
= 13-inch Tape and Reel
Model Number
See Valid Combinations table below
Package Modifier
K
E
= 7.7 x 6.2, 56-ball BGA, 0.5 mm ball pitch (0.3 mm ball diameter)
= 9.2 x 8.0, 56-ball BGA, 0.5 mm ball pitch (0.3 mm ball diameter)
Package Type
ZH = Very Thin Fine-Pitch Ball Grid Array (VFBGA)—-1.2 mm max height with
0.5mm pitch; Lead (Pb)-free Package; Low-Halogen
Chip Contents
0
= No content (default)
pSRAM Density
C
D
= 64 Mb
= 128 Mb
Process Technology
= 65 nm MirrorBit® Technology
R
Flash Density
256 = 256 Mb
128 = 128 Mb
Product Family
S71VS = Multi-Chip Product 1.8 Volt-only Simultaneous Read/Write Burst
Mode Address and Data Multiplexed (ADM) Flash Memory + pSRAM
S71XS = Multi-Chip Product 1.8V-only Simultaneous Read/Write Burst Mode,
Address-High, Address-Low Data Multiplexed (AADM) Flash Memory +
pSRAM
1.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
Base Ordering Part Number
Package
Model Number
Packing Type
pSRAM Type
pSRAM Speed
Flash Boot
Top Boot
Flash Speed
20
A0
24
A4
20
A0
24
A4
40
C0
44
C4
40
C0
44
C4
104 MHz
Bottom Boot
Top Boot
S71VS128RC0
83 MHz
104 MHz
83 MHz
104 MHz
83 MHz
104 MHz
83 MHz
Bottom Boot
Top Boot
ZHK
Mux pSRAM Type 3
Bottom Boot
Top Boot
S71VS256RC0
S71VS256RD0
S71XS256RD0
Bottom Boot
Top Boot
0, 2, 3
104 MHz
Bottom Boot
Top Boot
Bottom Boot
Top Boot
ZHE
Mux pSRAM Type 5
Bottom Boot
Top Boot
Bottom Boot
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S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_01 August 25, 2008
D a t a S h e e t
2. Input/Output Descriptions
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
Description
Flash
RAM
X
AMAX – A16
Address inputs
X
X
X
X
X
X
X
A/DQ15-A/DQ0 Multiplexed Address/Data
X
OE#
WE#
Output Enable input. Asynchronous relative to CLK for the Burst mode.
X
Write Enable input.
X
V
V
Ground
X
SS
Input/Output Ground
No Connect; not connected internally
X
SSQ
NC
X
Ready output; indicates the status of the Burst read.
Flash Memory RDY (using default "Active HIGH" configuration)
V
V
= data invalid
= data valid
OL
OH
Note: The default polarity for the pSRAM WAIT signal is opposite the default polarity of the
Flash RDY signal.
F-RDY/R-WAIT
X
X
pSRAM WAIT (using default “Active HIGH” configuration)
V
V
= data valid
OL
= data invalid
OH
To match polarities, change bit 10 of the pSRAM Bus Configuration Register to 0 (Active
LOW WAIT). Alternately, change bit 10 of the Flash Configuration Register to 0 (Active LOW
RDY)
Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK
CLK
X
X
X
X
increment the internal address counter. Should be at V or V while in asynchronous mode
IL
IH
Address Valid input. Indicates to device that the valid address is present on the address
inputs.
AVD#
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting
address to be latched.
High = device ignores address inputs
F-RST#
Hardware reset input. Low = device resets and returns to reading array data
X
X
Accelerated input. At V , accelerates programming; automatically places device in unlock
HH
F-V
bypass mode. At V , disables all program and erase functions. Should be at V for all other
PP
I
L
I
H
conditions.
R-CE#
F-CE#
R-CRE
Chip-enable input for pSRAM.
X
Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode.
Control Register Enable (pSRAM).
X
X
X
X
X
X
V
V
Flash and pSRAM 1.8 Volt-only single power supply.
Flash and pSRAM Input/Output Power Supply
Upper Byte Control (pSRAM).
X
X
CC
CCQ
R-UB#
R-LB#
RFU
Lower Byte Control (pSRAM)
Reserved For Future Use
August 25, 2008 S71VS_XS-R_00_01
S71VS/XS-R Memory Subsystem Solutions
5
D a t a S h e e t
3. MCP Block Diagram
Figure 3.1 S71VS-R MCP Block Diagram
F-RST#
RST#
A/DQ15-A/DQ0
CLK
ADQ15-ADQ0
CLK
F-VPP
F-RDY/R-WAIT
F-CE#
VPP
RDY
CE#
OE#
WE#
AVD#
MUX
FLASH
MEMORY
VS-R
OE#
WE#
AVD#
Amax-A16
Amax-A16
VCC
VCC
VSS, VSSQ
VSS
VCCQ
VCCQ
VSSQ
R-UB#
R-LB#
R-CE#
UB#
LB#
A/DQ15-A/DQ0
CLK
MUX
pSRAM
MEMORY
CE#
OE#
WE#
ADV#
VSS
Amax-A16
VCC
VCCQ
VSSQ
WAIT
CRE
R-CRE
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S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_01 August 25, 2008
D a t a S h e e t
Figure 3.2 S71XS-R MCP Block Diagram
Amax-A16 (no connect)
ADQ15-ADQ0
F-RST#
RST#
ADQ15-ADQ0
CLK
F-VPP
F-RDY/R-WAIT
F-CE#
VPP
RDY
CE#
OE#
WE#
AVD#
CLK
FLASH
MEMORY
XS-R
OE#
WE#
AVD#
(AADM)
VCC
VCC
VSS
VSS
VCCQ
VCCQ
VSSQ
R-UB#
R-LB#
R-CE#
UB#
LB#
ADQ15-ADQ0
CLK
CE#
OE#
pSRAM
WE#
ADV#
VSS
VSSQ
WAIT
Amax-A16
VCC
Amax-A16
R-CRE
MEMORY
VCCQ
CRE
August 25, 2008 S71VS_XS-R_00_01
S71VS/XS-R Memory Subsystem Solutions
7
D a t a S h e e t
4. Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S71VS-R.
4.1
Special Handling Instructions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
4.2
Connection Diagrams
Figure 4.1 S71VS-R 56-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Legend
A
B
C
D
E
F
Flash/RAM Shared
NC
NC
No Connect
Do Not Use
Flash Only
NC
RFU
A21
A16
R-LB# R-UB#
RFU
A17
NC
F-RDY/
R-WAIT
VSS
A20
CLK
VCC
WE#
F-VPP
A19
A18
A22
VCCQ
VSS
AVD#
A23 F-RST# RFU
F-CE# VSSQ
RAM Only
A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8
OE#
G
A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0
H
J
NC
RFU
R-CE# R-CRE
RFU
NC
K
NC
NC
Notes:
1. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
2. and V must be connected together.
V
SS
SSQ
MCP
Flash-Only Addresses
Shared Addresses
A21-A16
Shared ADQ Pins
S71VS128RC0
S71VS256RC0
S71VS256RD0
A22
A23-A22
A23
A/DQ15-A/DQ0
A/DQ15-A/DQ0
A21-A16
A22-A16
8
S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_01 August 25, 2008
D a t a S h e e t
Figure 4.2 S71XS-R 56-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Legend
A
B
C
D
E
F
Flash/RAM Shared
NC
NC
No Connect
Do Not Use
Flash Only
NC
RFU
A21
A16
R-LB# R-UB#
RFU
A17
NC
F-RDY/
R-WAIT
VSS
A20
CLK
VCC
WE#
F-VPP
A19
A18
A22
VCCQ
VSS
AVD#
RFU F-RST# RFU
F-CE#
VSS
OE#
RAM Only
A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8
G
A/DQ15 A/DQ14 VSS
A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0
H
J
NC
RFU
R-CE# R-CRE
RFU
NC
K
NC
NC
MCP
pSRAM-Only Addresses
Shared Addresses
Shared ADQ Pins
A/DQ15-A/DQ0
S71XS256RD0
A22-A16
N/A
August 25, 2008 S71VS_XS-R_00_01
S71VS/XS-R Memory Subsystem Solutions
9
D a t a S h e e t
4.3
Physical Dimensions
Figure 4.3 NLB056—56-ball VFBGA 9.2 x 8.0 mm
D1
A
D
eD
0.10
(2X)
C
14
13
12
11
10
9
SE
7
8
7
6
5
4
3
E
B
E1
eE
2
1
K
J H G F E D C B A
INDEX MARK
9
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.10
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
C
A2
A
A1
0.08
C
C
SIDE VIEW
6
56X
b
0.15
0.08
M
M
C
C
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
PACKAGE
JEDEC
NLB 056
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
9.20 mm x 8.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,
SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.20
0.85
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
9.20 BSC.
8.00 BSC.
4.50 BSC.
6.50 BSC.
10
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
14
56
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.25
0.30
0.35
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.50 BSC.
0.50 BSC
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
0.25 BSC.
SOLDER BALL PLACEMENT
A2 ~ A13,B1 ~ B14
DEPOPULATED SOLDER BALLS
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
C1,C2,C5,C6,C9,C10,C13,C14
D1,D2,D13,D14,E1,E2,E13,E14,F1,F2,F13,F14
G1,G2,G13,G14,H1,H2,H5,H6,H9,H10,H13,H14
J1 ~ J14, K2 ~ K13
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3507\ 16-038.22 \ 7.14.5
10
S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_01 August 25, 2008
D a t a S h e e t
Figure 4.4 NLD056—56-ball VFBGA 6.2 x 7.7 mm
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
PACKAGE
JEDEC
NLD 056
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
7.70 mm x 6.20 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,
SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.20
0.85
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
7.70 BSC.
6.20 BSC.
6.50 BSC.
4.50 BSC.
14
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
10
56
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.25
0.30
0.35
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.50 BSC.
0.50 BSC
0.25 BSC.
BALL PITCH
eD
SD SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3629 \ 16-038.22 \ 2.22.7
August 25, 2008 S71VS_XS-R_00_01
S71VS/XS-R Memory Subsystem Solutions
11
D a t a S h e e t
5. Revision History
Section
Description
Revision 01 (August 25, 2008)
Initial release
12
S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_01 August 25, 2008
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2008 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, ORNAND2™,
HD-SIM™, EcoRAM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for
informational purposes only and may be trademarks of their respective owners.
August 25, 2008 S71VS_XS-R_00_01
S71VS/XS-R Memory Subsystem Solutions
13
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